[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cavium / liquidio / octeon_config.h

/**********************************************************************
 * Author: Cavium, Inc.
 *
 * Contact: support@cavium.com
 *          Please include "LiquidIO" in the subject.
 *
 * Copyright (c) 2003-2016 Cavium, Inc.
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more details.
 ***********************************************************************/
/*! \file  octeon_config.h
 *  \brief Host Driver: Configuration data structures for the host driver.
 */

#ifndef __OCTEON_CONFIG_H__
#define __OCTEON_CONFIG_H__

/*--------------------------CONFIG VALUES------------------------*/

/* The following macros affect the way the driver data structures
 * are generated for Octeon devices.
 * They can be modified.
 */

/* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
 * multiple(<= MAX_OCTEON_NICIF) Miniports
 */
#define   MAX_OCTEON_NICIF             128
#define   MAX_OCTEON_DEVICES           MAX_OCTEON_NICIF
#define   MAX_OCTEON_LINKS	       MAX_OCTEON_NICIF
#define   MAX_OCTEON_MULTICAST_ADDR    32

/* CN6xxx IQ configuration macros */
#define   CN6XXX_MAX_INPUT_QUEUES      32
#define   CN6XXX_MAX_IQ_DESCRIPTORS    2048
#define   CN6XXX_DB_MIN                1
#define   CN6XXX_DB_MAX                8
#define   CN6XXX_DB_TIMEOUT            1

/* CN6xxx OQ configuration macros */
#define   CN6XXX_MAX_OUTPUT_QUEUES     32
#define   CN6XXX_MAX_OQ_DESCRIPTORS    2048
#define   CN6XXX_OQ_BUF_SIZE           1536
#define   CN6XXX_OQ_PKTSPER_INTR       ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
					(CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
#define   CN6XXX_OQ_REFIL_THRESHOLD    ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
					(CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)

#define   CN6XXX_OQ_INTR_PKT           64
#define   CN6XXX_OQ_INTR_TIME          100
#define   DEFAULT_NUM_NIC_PORTS_66XX   2
#define   DEFAULT_NUM_NIC_PORTS_68XX   4
#define   DEFAULT_NUM_NIC_PORTS_68XX_210NV  2

/* CN23xx  IQ configuration macros */
#define   CN23XX_MAX_VFS_PER_PF_PASS_1_0 8
#define   CN23XX_MAX_VFS_PER_PF_PASS_1_1 31
#define   CN23XX_MAX_VFS_PER_PF          63
#define   CN23XX_MAX_RINGS_PER_VF        8

#define   CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
#define   CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
#define   CN23XX_MAX_RINGS_PER_PF          64
#define   CN23XX_MAX_RINGS_PER_VF          8

#define   CN23XX_MAX_INPUT_QUEUES	CN23XX_MAX_RINGS_PER_PF
#define   CN23XX_MAX_IQ_DESCRIPTORS	512
#define   CN23XX_DB_MIN                 1
#define   CN23XX_DB_MAX                 8
#define   CN23XX_DB_TIMEOUT             1

#define   CN23XX_MAX_OUTPUT_QUEUES	CN23XX_MAX_RINGS_PER_PF
#define   CN23XX_MAX_OQ_DESCRIPTORS	512
#define   CN23XX_OQ_BUF_SIZE		1536
#define   CN23XX_OQ_PKTSPER_INTR	128
/*#define CAVIUM_ONLY_CN23XX_RX_PERF*/
#define   CN23XX_OQ_REFIL_THRESHOLD	16

#define   CN23XX_OQ_INTR_PKT		64
#define   CN23XX_OQ_INTR_TIME		100
#define   DEFAULT_NUM_NIC_PORTS_23XX	1

#define   CN23XX_CFG_IO_QUEUES		CN23XX_MAX_RINGS_PER_PF
/* PEMs count */
#define   CN23XX_MAX_MACS		4

#define   CN23XX_DEF_IQ_INTR_THRESHOLD	32
#define   CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD   (64 * 1024)
/* common OCTEON configuration macros */
#define   CN6XXX_CFG_IO_QUEUES         32
#define   OCTEON_32BYTE_INSTR          32
#define   OCTEON_64BYTE_INSTR          64
#define   OCTEON_MAX_BASE_IOQ          4
#define   OCTEON_OQ_BUFPTR_MODE        0
#define   OCTEON_OQ_INFOPTR_MODE       1

#define   OCTEON_DMA_INTR_PKT          64
#define   OCTEON_DMA_INTR_TIME         1000

#define MAX_TXQS_PER_INTF  8
#define MAX_RXQS_PER_INTF  8
#define DEF_TXQS_PER_INTF  4
#define DEF_RXQS_PER_INTF  4

#define INVALID_IOQ_NO          0xff

#define   DEFAULT_POW_GRP       0

/* Macros to get octeon config params */
#define CFG_GET_IQ_CFG(cfg)                      ((cfg)->iq)
#define CFG_GET_IQ_MAX_Q(cfg)                    ((cfg)->iq.max_iqs)
#define CFG_GET_IQ_PENDING_LIST_SIZE(cfg)        ((cfg)->iq.pending_list_size)
#define CFG_GET_IQ_INSTR_TYPE(cfg)               ((cfg)->iq.instr_type)
#define CFG_GET_IQ_DB_MIN(cfg)                   ((cfg)->iq.db_min)
#define CFG_GET_IQ_DB_TIMEOUT(cfg)               ((cfg)->iq.db_timeout)

#define CFG_GET_IQ_INTR_PKT(cfg)                 ((cfg)->iq.iq_intr_pkt)
#define CFG_SET_IQ_INTR_PKT(cfg, val)            (cfg)->iq.iq_intr_pkt = val

#define CFG_GET_OQ_MAX_Q(cfg)                    ((cfg)->oq.max_oqs)
#define CFG_GET_OQ_INFO_PTR(cfg)                 ((cfg)->oq.info_ptr)
#define CFG_GET_OQ_PKTS_PER_INTR(cfg)            ((cfg)->oq.pkts_per_intr)
#define CFG_GET_OQ_REFILL_THRESHOLD(cfg)         ((cfg)->oq.refill_threshold)
#define CFG_GET_OQ_INTR_PKT(cfg)                 ((cfg)->oq.oq_intr_pkt)
#define CFG_GET_OQ_INTR_TIME(cfg)                ((cfg)->oq.oq_intr_time)
#define CFG_SET_OQ_INTR_PKT(cfg, val)            (cfg)->oq.oq_intr_pkt = val
#define CFG_SET_OQ_INTR_TIME(cfg, val)           (cfg)->oq.oq_intr_time = val

#define CFG_GET_DMA_INTR_PKT(cfg)                ((cfg)->dma.dma_intr_pkt)
#define CFG_GET_DMA_INTR_TIME(cfg)               ((cfg)->dma.dma_intr_time)
#define CFG_GET_NUM_NIC_PORTS(cfg)               ((cfg)->num_nic_ports)
#define CFG_GET_NUM_DEF_TX_DESCS(cfg)            ((cfg)->num_def_tx_descs)
#define CFG_GET_NUM_DEF_RX_DESCS(cfg)            ((cfg)->num_def_rx_descs)
#define CFG_GET_DEF_RX_BUF_SIZE(cfg)             ((cfg)->def_rx_buf_size)

#define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].max_txqs)
#define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].num_txqs)
#define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].max_rxqs)
#define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].num_rxqs)
#define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].num_rx_descs)
#define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].num_tx_descs)
#define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].rx_buf_size)
#define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].base_queue)
#define CFG_GET_GMXID_NIC_IF(cfg, idx) \
				((cfg)->nic_if_cfg[idx].gmx_port_id)

#define CFG_GET_CTRL_Q_GRP(cfg)                  ((cfg)->misc.ctrlq_grp)
#define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
				((cfg)->misc.host_link_query_interval)
#define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
				((cfg)->misc.oct_link_query_interval)
#define CFG_GET_IS_SLI_BP_ON(cfg)                ((cfg)->misc.enable_sli_oq_bp)

/* Max IOQs per OCTEON Link */
#define MAX_IOQS_PER_NICIF              64

enum lio_card_type {
	LIO_210SV = 0, /* Two port, 66xx */
	LIO_210NV,     /* Two port, 68xx */
	LIO_410NV,     /* Four port, 68xx */
	LIO_23XX       /* 23xx */
};

#define LIO_210SV_NAME "210sv"
#define LIO_210NV_NAME "210nv"
#define LIO_410NV_NAME "410nv"
#define LIO_23XX_NAME  "23xx"

/** Structure to define the configuration attributes for each Input queue.
 *  Applicable to all Octeon processors
 **/
struct octeon_iq_config {
#ifdef __BIG_ENDIAN_BITFIELD
	u64 reserved:16;

	/** Tx interrupt packets. Applicable to 23xx only */
	u64 iq_intr_pkt:16;

	/** Minimum ticks to wait before checking for pending instructions. */
	u64 db_timeout:16;

	/** Minimum number of commands pending to be posted to Octeon
	 *  before driver hits the Input queue doorbell.
	 */
	u64 db_min:8;

	/** Command size - 32 or 64 bytes */
	u64 instr_type:32;

	/** Pending list size (usually set to the sum of the size of all Input
	 *  queues)
	 */
	u64 pending_list_size:32;

	/* Max number of IQs available */
	u64 max_iqs:8;
#else
	/* Max number of IQs available */
	u64 max_iqs:8;

	/** Pending list size (usually set to the sum of the size of all Input
	 *  queues)
	 */
	u64 pending_list_size:32;

	/** Command size - 32 or 64 bytes */
	u64 instr_type:32;

	/** Minimum number of commands pending to be posted to Octeon
	 *  before driver hits the Input queue doorbell.
	 */
	u64 db_min:8;

	/** Minimum ticks to wait before checking for pending instructions. */
	u64 db_timeout:16;

	/** Tx interrupt packets. Applicable to 23xx only */
	u64 iq_intr_pkt:16;

	u64 reserved:16;
#endif
};

/** Structure to define the configuration attributes for each Output queue.
 *  Applicable to all Octeon processors
 **/
struct octeon_oq_config {
#ifdef __BIG_ENDIAN_BITFIELD
	u64 reserved:16;

	u64 pkts_per_intr:16;

	/** Interrupt Coalescing (Time Interval). Octeon will interrupt the
	 *  host if atleast one packet was sent in the time interval specified
	 *  by this field. The driver uses time interval interrupt coalescing
	 *  by default. The time is specified in microseconds.
	 */
	u64 oq_intr_time:16;

	/** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
	 *  only if it sent as many packets as specified by this field.
	 *  The driver
	 *  usually does not use packet count interrupt coalescing.
	 */
	u64 oq_intr_pkt:16;

	/** The number of buffers that were consumed during packet processing by
	 *   the driver on this Output queue before the driver attempts to
	 *   replenish
	 *   the descriptor ring with new buffers.
	 */
	u64 refill_threshold:16;

	/** If set, the Output queue uses info-pointer mode. (Default: 1) */
	u64 info_ptr:32;

	/* Max number of OQs available */
	u64 max_oqs:8;

#else
	/* Max number of OQs available */
	u64 max_oqs:8;

	/** If set, the Output queue uses info-pointer mode. (Default: 1) */
	u64 info_ptr:32;

	/** The number of buffers that were consumed during packet processing by
	 *   the driver on this Output queue before the driver attempts to
	 *   replenish
	 *   the descriptor ring with new buffers.
	 */
	u64 refill_threshold:16;

	/** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
	 *  only if it sent as many packets as specified by this field.
	 *  The driver
	 *  usually does not use packet count interrupt coalescing.
	 */
	u64 oq_intr_pkt:16;

	/** Interrupt Coalescing (Time Interval). Octeon will interrupt the
	 *  host if atleast one packet was sent in the time interval specified
	 *  by this field. The driver uses time interval interrupt coalescing
	 *  by default.  The time is specified in microseconds.
	 */
	u64 oq_intr_time:16;

	u64 pkts_per_intr:16;

	u64 reserved:16;
#endif

};

/** This structure conatins the NIC link configuration attributes,
 *  common for all the OCTEON Modles.
 */
struct octeon_nic_if_config {
#ifdef __BIG_ENDIAN_BITFIELD
	u64 reserved:56;

	u64 base_queue:16;

	u64 gmx_port_id:8;

	/* SKB size, We need not change buf size even for Jumbo frames.
	 * Octeon can send jumbo frames in 4 consecutive descriptors,
	 */
	u64 rx_buf_size:16;

	/* Num of desc for tx rings */
	u64 num_tx_descs:16;

	/* Num of desc for rx rings */
	u64 num_rx_descs:16;

	/* Actual configured value. Range could be: 1...max_rxqs */
	u64 num_rxqs:16;

	/* Max Rxqs: Half for each of the two ports :max_oq/2  */
	u64 max_rxqs:16;

	/* Actual configured value. Range could be: 1...max_txqs */
	u64 num_txqs:16;

	/* Max Txqs: Half for each of the two ports :max_iq/2 */
	u64 max_txqs:16;
#else
	/* Max Txqs: Half for each of the two ports :max_iq/2 */
	u64 max_txqs:16;

	/* Actual configured value. Range could be: 1...max_txqs */
	u64 num_txqs:16;

	/* Max Rxqs: Half for each of the two ports :max_oq/2  */
	u64 max_rxqs:16;

	/* Actual configured value. Range could be: 1...max_rxqs */
	u64 num_rxqs:16;

	/* Num of desc for rx rings */
	u64 num_rx_descs:16;

	/* Num of desc for tx rings */
	u64 num_tx_descs:16;

	/* SKB size, We need not change buf size even for Jumbo frames.
	 * Octeon can send jumbo frames in 4 consecutive descriptors,
	 */
	u64 rx_buf_size:16;

	u64 gmx_port_id:8;

	u64 base_queue:16;

	u64 reserved:56;
#endif

};

/** Structure to define the configuration attributes for meta data.
 *  Applicable to all Octeon processors.
 */

struct octeon_misc_config {
#ifdef __BIG_ENDIAN_BITFIELD
	/** Host link status polling period */
	u64 host_link_query_interval:32;
	/** Oct link status polling period */
	u64 oct_link_query_interval:32;

	u64 enable_sli_oq_bp:1;
	/** Control IQ Group */
	u64 ctrlq_grp:4;
#else
	/** Control IQ Group */
	u64 ctrlq_grp:4;
	/** BP for SLI OQ */
	u64 enable_sli_oq_bp:1;
	/** Host link status polling period */
	u64 oct_link_query_interval:32;
	/** Oct link status polling period */
	u64 host_link_query_interval:32;
#endif
};

/** Structure to define the configuration for all OCTEON processors. */
struct octeon_config {
	u16 card_type;
	char *card_name;

	/** Input Queue attributes. */
	struct octeon_iq_config iq;

	/** Output Queue attributes. */
	struct octeon_oq_config oq;

	/** NIC Port Configuration */
	struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF];

	/** Miscellaneous attributes */
	struct octeon_misc_config misc;

	int num_nic_ports;

	int num_def_tx_descs;

	/* Num of desc for rx rings */
	int num_def_rx_descs;

	int def_rx_buf_size;

};

/* The following config values are fixed and should not be modified. */

#define  BAR1_INDEX_DYNAMIC_MAP          2
#define  BAR1_INDEX_STATIC_MAP          15
#define  OCTEON_BAR1_ENTRY_SIZE         (4 * 1024 * 1024)

#define  MAX_BAR1_IOREMAP_SIZE  (16 * OCTEON_BAR1_ENTRY_SIZE)

/* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
 * NoResponse Lists are now maintained with each IQ. (Dec' 2007).
 */
#define MAX_RESPONSE_LISTS           4

/* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
 * dispatch table.
 */
#define OPCODE_MASK_BITS             6

/* Mask for the 6-bit lookup hash */
#define OCTEON_OPCODE_MASK           0x3f

/* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
#define DISPATCH_LIST_SIZE                      BIT(OPCODE_MASK_BITS)

/* Maximum number of Octeon Instruction (command) queues */
#define MAX_OCTEON_INSTR_QUEUES(oct)		\
		(OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \
					CN6XXX_MAX_INPUT_QUEUES)

/* Maximum number of Octeon Instruction (command) queues */
#define MAX_OCTEON_OUTPUT_QUEUES(oct)		\
		(OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \
					CN6XXX_MAX_OUTPUT_QUEUES)

#define MAX_POSSIBLE_OCTEON_INSTR_QUEUES	CN23XX_MAX_INPUT_QUEUES
#define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES	CN23XX_MAX_OUTPUT_QUEUES

#define MAX_POSSIBLE_VFS			64

#endif /* __OCTEON_CONFIG_H__  */
Commit	Line	Data
f21fb3ed	1	/**********************************************************************
50579d3d RV	2	* Author: Cavium, Inc.
	3	*
	4	* Contact: support@cavium.com
	5	* Please include "LiquidIO" in the subject.
	6	*
	7	* Copyright (c) 2003-2016 Cavium, Inc.
	8	*
	9	* This file is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License, Version 2, as
	11	* published by the Free Software Foundation.
	12	*
	13	* This file is distributed in the hope that it will be useful, but
	14	* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
	15	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
	16	* NONINFRINGEMENT. See the GNU General Public License for more details.
	17	***********************************************************************/
f21fb3ed RV	18	/*! \file octeon_config.h
	19	* \brief Host Driver: Configuration data structures for the host driver.
	20	*/
	21
	22	#ifndef __OCTEON_CONFIG_H__
	23	#define __OCTEON_CONFIG_H__
	24
	25	/--------------------------CONFIG VALUES------------------------/
	26
	27	/* The following macros affect the way the driver data structures
	28	* are generated for Octeon devices.
	29	* They can be modified.
	30	*/
	31
	32	/* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
	33	* multiple(<= MAX_OCTEON_NICIF) Miniports
	34	*/
63da8404	35	#define MAX_OCTEON_NICIF 128
f21fb3ed RV	36	#define MAX_OCTEON_DEVICES MAX_OCTEON_NICIF
	37	#define MAX_OCTEON_LINKS MAX_OCTEON_NICIF
	38	#define MAX_OCTEON_MULTICAST_ADDR 32
	39
	40	/* CN6xxx IQ configuration macros */
	41	#define CN6XXX_MAX_INPUT_QUEUES 32
	42	#define CN6XXX_MAX_IQ_DESCRIPTORS 2048
	43	#define CN6XXX_DB_MIN 1
	44	#define CN6XXX_DB_MAX 8
	45	#define CN6XXX_DB_TIMEOUT 1
	46
	47	/* CN6xxx OQ configuration macros */
	48	#define CN6XXX_MAX_OUTPUT_QUEUES 32
	49	#define CN6XXX_MAX_OQ_DESCRIPTORS 2048
	50	#define CN6XXX_OQ_BUF_SIZE 1536
	51	#define CN6XXX_OQ_PKTSPER_INTR ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
	52	(CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
	53	#define CN6XXX_OQ_REFIL_THRESHOLD ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
	54	(CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
	55
	56	#define CN6XXX_OQ_INTR_PKT 64
	57	#define CN6XXX_OQ_INTR_TIME 100
	58	#define DEFAULT_NUM_NIC_PORTS_66XX 2
	59	#define DEFAULT_NUM_NIC_PORTS_68XX 4
	60	#define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2
	61
e86b1ab6	62	/* CN23xx IQ configuration macros */
d13520c7 RV	63	#define CN23XX_MAX_VFS_PER_PF_PASS_1_0 8
	64	#define CN23XX_MAX_VFS_PER_PF_PASS_1_1 31
	65	#define CN23XX_MAX_VFS_PER_PF 63
	66	#define CN23XX_MAX_RINGS_PER_VF 8
	67
e86b1ab6 RV	68	#define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
	69	#define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
	70	#define CN23XX_MAX_RINGS_PER_PF 64
d13520c7	71	#define CN23XX_MAX_RINGS_PER_VF 8
e86b1ab6 RV	72
e86b1ab6 RV	73	#define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
67e303e0	74	#define CN23XX_MAX_IQ_DESCRIPTORS 512
e86b1ab6 RV	75	#define CN23XX_DB_MIN 1
	76	#define CN23XX_DB_MAX 8
	77	#define CN23XX_DB_TIMEOUT 1
	78
	79	#define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
67e303e0	80	#define CN23XX_MAX_OQ_DESCRIPTORS 512
e86b1ab6 RV	81	#define CN23XX_OQ_BUF_SIZE 1536
	82	#define CN23XX_OQ_PKTSPER_INTR 128
	83	/#define CAVIUM_ONLY_CN23XX_RX_PERF/
67e303e0	84	#define CN23XX_OQ_REFIL_THRESHOLD 16
e86b1ab6 RV	85
	86	#define CN23XX_OQ_INTR_PKT 64
	87	#define CN23XX_OQ_INTR_TIME 100
	88	#define DEFAULT_NUM_NIC_PORTS_23XX 1
	89
	90	#define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
	91	/* PEMs count */
	92	#define CN23XX_MAX_MACS 4
	93
	94	#define CN23XX_DEF_IQ_INTR_THRESHOLD 32
	95	#define CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD (64 * 1024)
f21fb3ed RV	96	/* common OCTEON configuration macros */
	97	#define CN6XXX_CFG_IO_QUEUES 32
	98	#define OCTEON_32BYTE_INSTR 32
	99	#define OCTEON_64BYTE_INSTR 64
	100	#define OCTEON_MAX_BASE_IOQ 4
	101	#define OCTEON_OQ_BUFPTR_MODE 0
	102	#define OCTEON_OQ_INFOPTR_MODE 1
	103
	104	#define OCTEON_DMA_INTR_PKT 64
	105	#define OCTEON_DMA_INTR_TIME 1000
	106
	107	#define MAX_TXQS_PER_INTF 8
	108	#define MAX_RXQS_PER_INTF 8
	109	#define DEF_TXQS_PER_INTF 4
	110	#define DEF_RXQS_PER_INTF 4
	111
	112	#define INVALID_IOQ_NO 0xff
	113
	114	#define DEFAULT_POW_GRP 0
	115
	116	/* Macros to get octeon config params */
	117	#define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
	118	#define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
	119	#define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
	120	#define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
	121	#define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
	122	#define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
	123
3451b97c RV	124	#define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
	125	#define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
	126
f21fb3ed RV	127	#define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs)
	128	#define CFG_GET_OQ_INFO_PTR(cfg) ((cfg)->oq.info_ptr)
	129	#define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr)
	130	#define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
	131	#define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
	132	#define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
	133	#define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val
	134	#define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val
	135
	136	#define CFG_GET_DMA_INTR_PKT(cfg) ((cfg)->dma.dma_intr_pkt)
	137	#define CFG_GET_DMA_INTR_TIME(cfg) ((cfg)->dma.dma_intr_time)
	138	#define CFG_GET_NUM_NIC_PORTS(cfg) ((cfg)->num_nic_ports)
	139	#define CFG_GET_NUM_DEF_TX_DESCS(cfg) ((cfg)->num_def_tx_descs)
	140	#define CFG_GET_NUM_DEF_RX_DESCS(cfg) ((cfg)->num_def_rx_descs)
	141	#define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size)
	142
	143	#define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
	144	((cfg)->nic_if_cfg[idx].max_txqs)
	145	#define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
	146	((cfg)->nic_if_cfg[idx].num_txqs)
	147	#define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
	148	((cfg)->nic_if_cfg[idx].max_rxqs)
	149	#define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
	150	((cfg)->nic_if_cfg[idx].num_rxqs)
	151	#define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
	152	((cfg)->nic_if_cfg[idx].num_rx_descs)
	153	#define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
	154	((cfg)->nic_if_cfg[idx].num_tx_descs)
	155	#define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
	156	((cfg)->nic_if_cfg[idx].rx_buf_size)
	157	#define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
	158	((cfg)->nic_if_cfg[idx].base_queue)
	159	#define CFG_GET_GMXID_NIC_IF(cfg, idx) \
	160	((cfg)->nic_if_cfg[idx].gmx_port_id)
	161
	162	#define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp)
	163	#define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
	164	((cfg)->misc.host_link_query_interval)
	165	#define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
	166	((cfg)->misc.oct_link_query_interval)
	167	#define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp)
	168
	169	/* Max IOQs per OCTEON Link */
63da8404	170	#define MAX_IOQS_PER_NICIF 64
f21fb3ed RV	171
	172	enum lio_card_type {
	173	LIO_210SV = 0, /* Two port, 66xx */
	174	LIO_210NV, /* Two port, 68xx */
e86b1ab6 RV	175	LIO_410NV, /* Four port, 68xx */
e86b1ab6 RV	176	LIO_23XX /* 23xx */
f21fb3ed RV	177	};
	178
	179	#define LIO_210SV_NAME "210sv"
	180	#define LIO_210NV_NAME "210nv"
	181	#define LIO_410NV_NAME "410nv"
e86b1ab6	182	#define LIO_23XX_NAME "23xx"
f21fb3ed RV	183
	184	/** Structure to define the configuration attributes for each Input queue.
	185	* Applicable to all Octeon processors
	186	**/
	187	struct octeon_iq_config {
	188	#ifdef __BIG_ENDIAN_BITFIELD
e86b1ab6 RV	189	u64 reserved:16;
	190
	191	/** Tx interrupt packets. Applicable to 23xx only */
	192	u64 iq_intr_pkt:16;
f21fb3ed RV	193
	194	/** Minimum ticks to wait before checking for pending instructions. */
	195	u64 db_timeout:16;
	196
	197	/** Minimum number of commands pending to be posted to Octeon
	198	* before driver hits the Input queue doorbell.
	199	*/
	200	u64 db_min:8;
	201
	202	/** Command size - 32 or 64 bytes */
	203	u64 instr_type:32;
	204
	205	/** Pending list size (usually set to the sum of the size of all Input
	206	* queues)
	207	*/
	208	u64 pending_list_size:32;
	209
	210	/* Max number of IQs available */
	211	u64 max_iqs:8;
	212	#else
	213	/* Max number of IQs available */
	214	u64 max_iqs:8;
	215
	216	/** Pending list size (usually set to the sum of the size of all Input
	217	* queues)
	218	*/
	219	u64 pending_list_size:32;
	220
	221	/** Command size - 32 or 64 bytes */
	222	u64 instr_type:32;
	223
	224	/** Minimum number of commands pending to be posted to Octeon
	225	* before driver hits the Input queue doorbell.
	226	*/
	227	u64 db_min:8;
	228
	229	/** Minimum ticks to wait before checking for pending instructions. */
	230	u64 db_timeout:16;
	231
e86b1ab6 RV	232	/** Tx interrupt packets. Applicable to 23xx only */
	233	u64 iq_intr_pkt:16;
	234
	235	u64 reserved:16;
f21fb3ed RV	236	#endif
	237	};
	238
	239	/** Structure to define the configuration attributes for each Output queue.
	240	* Applicable to all Octeon processors
	241	**/
	242	struct octeon_oq_config {
	243	#ifdef __BIG_ENDIAN_BITFIELD
	244	u64 reserved:16;
	245
	246	u64 pkts_per_intr:16;
	247
	248	/** Interrupt Coalescing (Time Interval). Octeon will interrupt the
	249	* host if atleast one packet was sent in the time interval specified
	250	* by this field. The driver uses time interval interrupt coalescing
	251	* by default. The time is specified in microseconds.
	252	*/
	253	u64 oq_intr_time:16;
	254
	255	/** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
	256	* only if it sent as many packets as specified by this field.
	257	* The driver
	258	* usually does not use packet count interrupt coalescing.
	259	*/
	260	u64 oq_intr_pkt:16;
	261
	262	/** The number of buffers that were consumed during packet processing by
	263	* the driver on this Output queue before the driver attempts to
	264	* replenish
	265	* the descriptor ring with new buffers.
	266	*/
	267	u64 refill_threshold:16;
	268
a2c64b67	269	/** If set, the Output queue uses info-pointer mode. (Default: 1) */
f21fb3ed RV	270	u64 info_ptr:32;
	271
	272	/* Max number of OQs available */
	273	u64 max_oqs:8;
	274
	275	#else
	276	/* Max number of OQs available */
	277	u64 max_oqs:8;
	278
a2c64b67	279	/** If set, the Output queue uses info-pointer mode. (Default: 1) */
f21fb3ed RV	280	u64 info_ptr:32;
	281
	282	/** The number of buffers that were consumed during packet processing by
	283	* the driver on this Output queue before the driver attempts to
	284	* replenish
	285	* the descriptor ring with new buffers.
	286	*/
	287	u64 refill_threshold:16;
	288
	289	/** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
	290	* only if it sent as many packets as specified by this field.
	291	* The driver
	292	* usually does not use packet count interrupt coalescing.
	293	*/
	294	u64 oq_intr_pkt:16;
	295
	296	/** Interrupt Coalescing (Time Interval). Octeon will interrupt the
	297	* host if atleast one packet was sent in the time interval specified
	298	* by this field. The driver uses time interval interrupt coalescing
	299	* by default. The time is specified in microseconds.
	300	*/
	301	u64 oq_intr_time:16;
	302
	303	u64 pkts_per_intr:16;
	304
	305	u64 reserved:16;
	306	#endif
	307
	308	};
	309
	310	/** This structure conatins the NIC link configuration attributes,
	311	* common for all the OCTEON Modles.
	312	*/
	313	struct octeon_nic_if_config {
	314	#ifdef __BIG_ENDIAN_BITFIELD
	315	u64 reserved:56;
	316
	317	u64 base_queue:16;
	318
	319	u64 gmx_port_id:8;
	320
	321	/* SKB size, We need not change buf size even for Jumbo frames.
	322	* Octeon can send jumbo frames in 4 consecutive descriptors,
	323	*/
	324	u64 rx_buf_size:16;
	325
	326	/* Num of desc for tx rings */
	327	u64 num_tx_descs:16;
	328
	329	/* Num of desc for rx rings */
	330	u64 num_rx_descs:16;
	331
	332	/* Actual configured value. Range could be: 1...max_rxqs */
	333	u64 num_rxqs:16;
	334
	335	/* Max Rxqs: Half for each of the two ports :max_oq/2 */
	336	u64 max_rxqs:16;
	337
	338	/* Actual configured value. Range could be: 1...max_txqs */
	339	u64 num_txqs:16;
	340
	341	/* Max Txqs: Half for each of the two ports :max_iq/2 */
	342	u64 max_txqs:16;
	343	#else
344	/* Max Txqs: Half for each of the two ports :max_iq/2 */
345	u64 max_txqs:16;
346
347	/* Actual configured value. Range could be: 1...max_txqs */
348	u64 num_txqs:16;
349
350	/* Max Rxqs: Half for each of the two ports :max_oq/2 */
351	u64 max_rxqs:16;
352
353	/* Actual configured value. Range could be: 1...max_rxqs */
354	u64 num_rxqs:16;
355
356	/* Num of desc for rx rings */
357	u64 num_rx_descs:16;
358
359	/* Num of desc for tx rings */
360	u64 num_tx_descs:16;
361
362	/* SKB size, We need not change buf size even for Jumbo frames.
363	* Octeon can send jumbo frames in 4 consecutive descriptors,
364	*/
365	u64 rx_buf_size:16;
366
367	u64 gmx_port_id:8;
368
369	u64 base_queue:16;
370
371	u64 reserved:56;
372	#endif
373
374	};
375
376	/** Structure to define the configuration attributes for meta data.
377	* Applicable to all Octeon processors.
378	*/
379
380	struct octeon_misc_config {
381	#ifdef __BIG_ENDIAN_BITFIELD
382	/** Host link status polling period */
383	u64 host_link_query_interval:32;
384	/** Oct link status polling period */
385	u64 oct_link_query_interval:32;
386
387	u64 enable_sli_oq_bp:1;
388	/** Control IQ Group */
389	u64 ctrlq_grp:4;
390	#else
391	/** Control IQ Group */
392	u64 ctrlq_grp:4;
393	/** BP for SLI OQ */
394	u64 enable_sli_oq_bp:1;
395	/** Host link status polling period */
396	u64 oct_link_query_interval:32;
397	/** Oct link status polling period */
398	u64 host_link_query_interval:32;
399	#endif
400	};
401
402	/** Structure to define the configuration for all OCTEON processors. */
403	struct octeon_config {
404	u16 card_type;
405	char *card_name;
406
407	/** Input Queue attributes. */
408	struct octeon_iq_config iq;
409
410	/** Output Queue attributes. */
411	struct octeon_oq_config oq;
412
413	/** NIC Port Configuration */
414	struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF];
415
416	/** Miscellaneous attributes */
417	struct octeon_misc_config misc;
418
419	int num_nic_ports;
420
421	int num_def_tx_descs;
422
423	/* Num of desc for rx rings */
424	int num_def_rx_descs;
425
426	int def_rx_buf_size;
427
428	};
429
430	/* The following config values are fixed and should not be modified. */
431
15d3afcc FM	432	#define BAR1_INDEX_DYNAMIC_MAP 2
15d3afcc FM	433	#define BAR1_INDEX_STATIC_MAP 15
f21fb3ed RV	434	#define OCTEON_BAR1_ENTRY_SIZE (4 * 1024 * 1024)
f21fb3ed RV	435
15d3afcc	436	#define MAX_BAR1_IOREMAP_SIZE (16 * OCTEON_BAR1_ENTRY_SIZE)
f21fb3ed RV	437
	438	/* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
	439	* NoResponse Lists are now maintained with each IQ. (Dec' 2007).
	440	*/
	441	#define MAX_RESPONSE_LISTS 4
	442
	443	/* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
	444	* dispatch table.
	445	*/
	446	#define OPCODE_MASK_BITS 6
	447
	448	/* Mask for the 6-bit lookup hash */
	449	#define OCTEON_OPCODE_MASK 0x3f
	450
	451	/* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
	452	#define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS)
	453
	454	/* Maximum number of Octeon Instruction (command) queues */
e86b1ab6 RV	455	#define MAX_OCTEON_INSTR_QUEUES(oct) \
	456	(OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \
	457	CN6XXX_MAX_INPUT_QUEUES)
f21fb3ed	458
e86b1ab6 RV	459	/* Maximum number of Octeon Instruction (command) queues */
	460	#define MAX_OCTEON_OUTPUT_QUEUES(oct) \
	461	(OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \
	462	CN6XXX_MAX_OUTPUT_QUEUES)
f21fb3ed	463
e86b1ab6 RV	464	#define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
e86b1ab6 RV	465	#define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
ca6139ff RV	466
	467	#define MAX_POSSIBLE_VFS 64
	468
f21fb3ed	469	#endif /* __OCTEON_CONFIG_H__ */