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1 | /********************************************************************** |
2 | * Author: Cavium, Inc. | |
3 | * | |
4 | * Contact: support@cavium.com | |
5 | * Please include "LiquidIO" in the subject. | |
6 | * | |
7 | * Copyright (c) 2003-2015 Cavium, Inc. | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * This file may also be available under a different license from Cavium. | |
20 | * Contact Cavium, Inc. for more information | |
21 | **********************************************************************/ | |
22 | ||
23 | /*! \file octeon_iq.h | |
24 | * \brief Host Driver: Implementation of Octeon input queues. "Input" is | |
25 | * with respect to the Octeon device on the NIC. From this driver's | |
26 | * point of view they are egress queues. | |
27 | */ | |
28 | ||
29 | #ifndef __OCTEON_IQ_H__ | |
30 | #define __OCTEON_IQ_H__ | |
31 | ||
32 | #define IQ_STATUS_RUNNING 1 | |
33 | ||
34 | #define IQ_SEND_OK 0 | |
35 | #define IQ_SEND_STOP 1 | |
36 | #define IQ_SEND_FAILED -1 | |
37 | ||
38 | /*------------------------- INSTRUCTION QUEUE --------------------------*/ | |
39 | ||
40 | /* \cond */ | |
41 | ||
42 | #define REQTYPE_NONE 0 | |
43 | #define REQTYPE_NORESP_NET 1 | |
44 | #define REQTYPE_NORESP_NET_SG 2 | |
45 | #define REQTYPE_RESP_NET 3 | |
46 | #define REQTYPE_RESP_NET_SG 4 | |
47 | #define REQTYPE_SOFT_COMMAND 5 | |
48 | #define REQTYPE_LAST 5 | |
49 | ||
50 | struct octeon_request_list { | |
51 | u32 reqtype; | |
52 | void *buf; | |
53 | }; | |
54 | ||
55 | /* \endcond */ | |
56 | ||
57 | /** Input Queue statistics. Each input queue has four stats fields. */ | |
58 | struct oct_iq_stats { | |
59 | u64 instr_posted; /**< Instructions posted to this queue. */ | |
60 | u64 instr_processed; /**< Instructions processed in this queue. */ | |
61 | u64 instr_dropped; /**< Instructions that could not be processed */ | |
62 | u64 bytes_sent; /**< Bytes sent through this queue. */ | |
63 | u64 sgentry_sent;/**< Gather entries sent through this queue. */ | |
64 | u64 tx_done;/**< Num of packets sent to network. */ | |
65 | u64 tx_iq_busy;/**< Numof times this iq was found to be full. */ | |
66 | u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */ | |
67 | u64 tx_tot_bytes;/**< Total count of bytes sento to network. */ | |
68 | }; | |
69 | ||
70 | #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats)) | |
71 | ||
72 | /** The instruction (input) queue. | |
73 | * The input queue is used to post raw (instruction) mode data or packet | |
74 | * data to Octeon device from the host. Each input queue (upto 4) for | |
75 | * a Octeon device has one such structure to represent it. | |
76 | */ | |
77 | struct octeon_instr_queue { | |
6a885b60 RV |
78 | struct octeon_device *oct_dev; |
79 | ||
f21fb3ed RV |
80 | /** A spinlock to protect access to the input ring. */ |
81 | spinlock_t lock; | |
82 | ||
9a96bde4 RV |
83 | /** A spinlock to protect while posting on the ring. */ |
84 | spinlock_t post_lock; | |
85 | ||
86 | /** A spinlock to protect access to the input ring.*/ | |
87 | spinlock_t iq_flush_running_lock; | |
88 | ||
f21fb3ed RV |
89 | /** Flag that indicates if the queue uses 64 byte commands. */ |
90 | u32 iqcmd_64B:1; | |
91 | ||
26236fa9 RV |
92 | /** Queue info. */ |
93 | union oct_txpciq txpciq; | |
f21fb3ed RV |
94 | |
95 | u32 rsvd:17; | |
96 | ||
97 | /* Controls the periodic flushing of iq */ | |
98 | u32 do_auto_flush:1; | |
99 | ||
100 | u32 status:8; | |
101 | ||
102 | /** Maximum no. of instructions in this queue. */ | |
103 | u32 max_count; | |
104 | ||
105 | /** Index in input ring where the driver should write the next packet */ | |
106 | u32 host_write_index; | |
107 | ||
108 | /** Index in input ring where Octeon is expected to read the next | |
109 | * packet. | |
110 | */ | |
111 | u32 octeon_read_index; | |
112 | ||
113 | /** This index aids in finding the window in the queue where Octeon | |
114 | * has read the commands. | |
115 | */ | |
116 | u32 flush_index; | |
117 | ||
118 | /** This field keeps track of the instructions pending in this queue. */ | |
119 | atomic_t instr_pending; | |
120 | ||
121 | u32 reset_instr_cnt; | |
122 | ||
123 | /** Pointer to the Virtual Base addr of the input ring. */ | |
124 | u8 *base_addr; | |
125 | ||
126 | struct octeon_request_list *request_list; | |
127 | ||
128 | /** Octeon doorbell register for the ring. */ | |
129 | void __iomem *doorbell_reg; | |
130 | ||
131 | /** Octeon instruction count register for this ring. */ | |
132 | void __iomem *inst_cnt_reg; | |
133 | ||
134 | /** Number of instructions pending to be posted to Octeon. */ | |
135 | u32 fill_cnt; | |
136 | ||
137 | /** The max. number of instructions that can be held pending by the | |
138 | * driver. | |
139 | */ | |
140 | u32 fill_threshold; | |
141 | ||
142 | /** The last time that the doorbell was rung. */ | |
143 | u64 last_db_time; | |
144 | ||
145 | /** The doorbell timeout. If the doorbell was not rung for this time and | |
146 | * fill_cnt is non-zero, ring the doorbell again. | |
147 | */ | |
148 | u32 db_timeout; | |
149 | ||
150 | /** Statistics for this input queue. */ | |
151 | struct oct_iq_stats stats; | |
152 | ||
153 | /** DMA mapped base address of the input descriptor ring. */ | |
154 | u64 base_addr_dma; | |
155 | ||
156 | /** Application context */ | |
157 | void *app_ctx; | |
0cece6c5 RV |
158 | |
159 | /* network stack queue index */ | |
160 | int q_index; | |
161 | ||
162 | /*os ifidx associated with this queue */ | |
163 | int ifidx; | |
164 | ||
f21fb3ed RV |
165 | }; |
166 | ||
167 | /*---------------------- INSTRUCTION FORMAT ----------------------------*/ | |
168 | ||
169 | /** 32-byte instruction format. | |
170 | * Format of instruction for a 32-byte mode input queue. | |
171 | */ | |
172 | struct octeon_instr_32B { | |
173 | /** Pointer where the input data is available. */ | |
174 | u64 dptr; | |
175 | ||
176 | /** Instruction Header. */ | |
177 | u64 ih; | |
178 | ||
179 | /** Pointer where the response for a RAW mode packet will be written | |
180 | * by Octeon. | |
181 | */ | |
182 | u64 rptr; | |
183 | ||
184 | /** Input Request Header. Additional info about the input. */ | |
185 | u64 irh; | |
186 | ||
187 | }; | |
188 | ||
189 | #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B)) | |
190 | ||
191 | /** 64-byte instruction format. | |
192 | * Format of instruction for a 64-byte mode input queue. | |
193 | */ | |
6a885b60 | 194 | struct octeon_instr2_64B { |
f21fb3ed RV |
195 | /** Pointer where the input data is available. */ |
196 | u64 dptr; | |
197 | ||
198 | /** Instruction Header. */ | |
6a885b60 | 199 | u64 ih2; |
f21fb3ed RV |
200 | |
201 | /** Input Request Header. */ | |
202 | u64 irh; | |
203 | ||
204 | /** opcode/subcode specific parameters */ | |
205 | u64 ossp[2]; | |
206 | ||
207 | /** Return Data Parameters */ | |
208 | u64 rdp; | |
209 | ||
210 | /** Pointer where the response for a RAW mode packet will be written | |
211 | * by Octeon. | |
212 | */ | |
213 | u64 rptr; | |
214 | ||
215 | u64 reserved; | |
6a885b60 RV |
216 | }; |
217 | ||
218 | struct octeon_instr3_64B { | |
219 | /** Pointer where the input data is available. */ | |
220 | u64 dptr; | |
221 | ||
222 | /** Instruction Header. */ | |
223 | u64 ih3; | |
224 | ||
225 | /** Instruction Header. */ | |
226 | u64 pki_ih3; | |
227 | ||
228 | /** Input Request Header. */ | |
229 | u64 irh; | |
230 | ||
231 | /** opcode/subcode specific parameters */ | |
232 | u64 ossp[2]; | |
233 | ||
234 | /** Return Data Parameters */ | |
235 | u64 rdp; | |
236 | ||
237 | /** Pointer where the response for a RAW mode packet will be written | |
238 | * by Octeon. | |
239 | */ | |
240 | u64 rptr; | |
f21fb3ed RV |
241 | |
242 | }; | |
243 | ||
6a885b60 RV |
244 | union octeon_instr_64B { |
245 | struct octeon_instr2_64B cmd2; | |
246 | struct octeon_instr3_64B cmd3; | |
247 | }; | |
248 | ||
249 | #define OCT_64B_INSTR_SIZE (sizeof(union octeon_instr_64B)) | |
f21fb3ed RV |
250 | |
251 | /** The size of each buffer in soft command buffer pool | |
252 | */ | |
63da8404 | 253 | #define SOFT_COMMAND_BUFFER_SIZE 1536 |
f21fb3ed RV |
254 | |
255 | struct octeon_soft_command { | |
256 | /** Soft command buffer info. */ | |
257 | struct list_head node; | |
258 | u64 dma_addr; | |
259 | u32 size; | |
260 | ||
261 | /** Command and return status */ | |
6a885b60 RV |
262 | union octeon_instr_64B cmd; |
263 | ||
f21fb3ed RV |
264 | #define COMPLETION_WORD_INIT 0xffffffffffffffffULL |
265 | u64 *status_word; | |
266 | ||
267 | /** Data buffer info */ | |
268 | void *virtdptr; | |
269 | u64 dmadptr; | |
270 | u32 datasize; | |
271 | ||
272 | /** Return buffer info */ | |
273 | void *virtrptr; | |
274 | u64 dmarptr; | |
275 | u32 rdatasize; | |
276 | ||
277 | /** Context buffer info */ | |
278 | void *ctxptr; | |
279 | u32 ctxsize; | |
280 | ||
281 | /** Time out and callback */ | |
282 | size_t wait_time; | |
283 | size_t timeout; | |
284 | u32 iq_no; | |
285 | void (*callback)(struct octeon_device *, u32, void *); | |
286 | void *callback_arg; | |
287 | }; | |
288 | ||
289 | /** Maximum number of buffers to allocate into soft command buffer pool | |
290 | */ | |
63da8404 | 291 | #define MAX_SOFT_COMMAND_BUFFERS 256 |
f21fb3ed RV |
292 | |
293 | /** Head of a soft command buffer pool. | |
294 | */ | |
295 | struct octeon_sc_buffer_pool { | |
296 | /** List structure to add delete pending entries to */ | |
297 | struct list_head head; | |
298 | ||
299 | /** A lock for this response list */ | |
300 | spinlock_t lock; | |
301 | ||
302 | atomic_t alloc_buf_count; | |
303 | }; | |
304 | ||
305 | int octeon_setup_sc_buffer_pool(struct octeon_device *oct); | |
306 | int octeon_free_sc_buffer_pool(struct octeon_device *oct); | |
307 | struct octeon_soft_command * | |
308 | octeon_alloc_soft_command(struct octeon_device *oct, | |
309 | u32 datasize, u32 rdatasize, | |
310 | u32 ctxsize); | |
311 | void octeon_free_soft_command(struct octeon_device *oct, | |
312 | struct octeon_soft_command *sc); | |
313 | ||
314 | /** | |
315 | * octeon_init_instr_queue() | |
316 | * @param octeon_dev - pointer to the octeon device structure. | |
26236fa9 | 317 | * @param txpciq - queue to be initialized (0 <= q_no <= 3). |
f21fb3ed RV |
318 | * |
319 | * Called at driver init time for each input queue. iq_conf has the | |
320 | * configuration parameters for the queue. | |
321 | * | |
322 | * @return Success: 0 Failure: 1 | |
323 | */ | |
26236fa9 RV |
324 | int octeon_init_instr_queue(struct octeon_device *octeon_dev, |
325 | union oct_txpciq txpciq, | |
f21fb3ed RV |
326 | u32 num_descs); |
327 | ||
328 | /** | |
329 | * octeon_delete_instr_queue() | |
330 | * @param octeon_dev - pointer to the octeon device structure. | |
331 | * @param iq_no - queue to be deleted (0 <= q_no <= 3). | |
332 | * | |
333 | * Called at driver unload time for each input queue. Deletes all | |
334 | * allocated resources for the input queue. | |
335 | * | |
336 | * @return Success: 0 Failure: 1 | |
337 | */ | |
338 | int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no); | |
339 | ||
340 | int lio_wait_for_instr_fetch(struct octeon_device *oct); | |
341 | ||
342 | int | |
343 | octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, | |
344 | void (*fn)(void *)); | |
345 | ||
346 | int | |
347 | lio_process_iq_request_list(struct octeon_device *oct, | |
9a96bde4 | 348 | struct octeon_instr_queue *iq, u32 napi_budget); |
f21fb3ed RV |
349 | |
350 | int octeon_send_command(struct octeon_device *oct, u32 iq_no, | |
351 | u32 force_db, void *cmd, void *buf, | |
352 | u32 datasize, u32 reqtype); | |
353 | ||
354 | void octeon_prepare_soft_command(struct octeon_device *oct, | |
355 | struct octeon_soft_command *sc, | |
356 | u8 opcode, u8 subcode, | |
357 | u32 irh_ossp, u64 ossp0, | |
358 | u64 ossp1); | |
359 | ||
360 | int octeon_send_soft_command(struct octeon_device *oct, | |
361 | struct octeon_soft_command *sc); | |
362 | ||
0cece6c5 RV |
363 | int octeon_setup_iq(struct octeon_device *oct, int ifidx, |
364 | int q_index, union oct_txpciq iq_no, u32 num_descs, | |
365 | void *app_ctx); | |
9a96bde4 RV |
366 | int |
367 | octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, | |
368 | u32 pending_thresh, u32 napi_budget); | |
f21fb3ed | 369 | #endif /* __OCTEON_IQ_H__ */ |