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4863dea3 SG |
1 | /* |
2 | * Copyright (C) 2015 Cavium, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of version 2 of the GNU General Public License | |
6 | * as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef NIC_H | |
10 | #define NIC_H | |
11 | ||
12 | #include <linux/netdevice.h> | |
13 | #include <linux/interrupt.h> | |
d768b678 | 14 | #include <linux/pci.h> |
4863dea3 SG |
15 | #include "thunder_bgx.h" |
16 | ||
17 | /* PCI device IDs */ | |
18 | #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E | |
19 | #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 | |
20 | #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 | |
21 | #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 | |
22 | ||
a5c3d498 | 23 | /* Subsystem device IDs */ |
f7ff0ae8 SG |
24 | #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E |
25 | #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E | |
26 | #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E | |
27 | ||
28 | #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E | |
29 | #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134 | |
30 | #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234 | |
31 | #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334 | |
32 | ||
a5c3d498 | 33 | |
4863dea3 SG |
34 | /* PCI BAR nos */ |
35 | #define PCI_CFG_REG_BAR_NUM 0 | |
36 | #define PCI_MSIX_REG_BAR_NUM 4 | |
37 | ||
38 | /* NIC SRIOV VF count */ | |
39 | #define MAX_NUM_VFS_SUPPORTED 128 | |
40 | #define DEFAULT_NUM_VF_ENABLED 8 | |
41 | ||
42 | #define NIC_TNS_BYPASS_MODE 0 | |
43 | #define NIC_TNS_MODE 1 | |
44 | ||
45 | /* NIC priv flags */ | |
46 | #define NIC_SRIOV_ENABLED BIT(0) | |
47 | ||
48 | /* Min/Max packet size */ | |
49 | #define NIC_HW_MIN_FRS 64 | |
712c3185 | 50 | #define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */ |
4863dea3 SG |
51 | |
52 | /* Max pkinds */ | |
53 | #define NIC_MAX_PKIND 16 | |
54 | ||
a5c3d498 SG |
55 | /* Max when CPI_ALG is IP diffserv */ |
56 | #define NIC_MAX_CPI_PER_LMAC 64 | |
4863dea3 SG |
57 | |
58 | /* NIC VF Interrupts */ | |
59 | #define NICVF_INTR_CQ 0 | |
60 | #define NICVF_INTR_SQ 1 | |
61 | #define NICVF_INTR_RBDR 2 | |
62 | #define NICVF_INTR_PKT_DROP 3 | |
63 | #define NICVF_INTR_TCP_TIMER 4 | |
64 | #define NICVF_INTR_MBOX 5 | |
65 | #define NICVF_INTR_QS_ERR 6 | |
66 | ||
67 | #define NICVF_INTR_CQ_SHIFT 0 | |
68 | #define NICVF_INTR_SQ_SHIFT 8 | |
69 | #define NICVF_INTR_RBDR_SHIFT 16 | |
70 | #define NICVF_INTR_PKT_DROP_SHIFT 20 | |
71 | #define NICVF_INTR_TCP_TIMER_SHIFT 21 | |
72 | #define NICVF_INTR_MBOX_SHIFT 22 | |
73 | #define NICVF_INTR_QS_ERR_SHIFT 23 | |
74 | ||
75 | #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) | |
76 | #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) | |
77 | #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) | |
78 | #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) | |
79 | #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) | |
80 | #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) | |
81 | #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) | |
82 | ||
83 | /* MSI-X interrupts */ | |
84 | #define NIC_PF_MSIX_VECTORS 10 | |
85 | #define NIC_VF_MSIX_VECTORS 20 | |
86 | ||
87 | #define NIC_PF_INTR_ID_ECC0_SBE 0 | |
88 | #define NIC_PF_INTR_ID_ECC0_DBE 1 | |
89 | #define NIC_PF_INTR_ID_ECC1_SBE 2 | |
90 | #define NIC_PF_INTR_ID_ECC1_DBE 3 | |
91 | #define NIC_PF_INTR_ID_ECC2_SBE 4 | |
92 | #define NIC_PF_INTR_ID_ECC2_DBE 5 | |
93 | #define NIC_PF_INTR_ID_ECC3_SBE 6 | |
94 | #define NIC_PF_INTR_ID_ECC3_DBE 7 | |
95 | #define NIC_PF_INTR_ID_MBOX0 8 | |
96 | #define NIC_PF_INTR_ID_MBOX1 9 | |
97 | ||
4c0b6eaf SG |
98 | /* Minimum FIFO level before all packets for the CQ are dropped |
99 | * | |
100 | * This value ensures that once a packet has been "accepted" | |
101 | * for reception it will not get dropped due to non-availability | |
102 | * of CQ descriptor. An errata in HW mandates this value to be | |
103 | * atleast 0x100. | |
104 | */ | |
105 | #define NICPF_CQM_MIN_DROP_LEVEL 0x100 | |
106 | ||
4863dea3 SG |
107 | /* Global timer for CQ timer thresh interrupts |
108 | * Calculated for SCLK of 700Mhz | |
109 | * value written should be a 1/16th of what is expected | |
110 | * | |
006394a7 | 111 | * 1 tick per 0.025usec |
4863dea3 | 112 | */ |
006394a7 | 113 | #define NICPF_CLK_PER_INT_TICK 1 |
4863dea3 | 114 | |
3d7a8aaa SG |
115 | /* Time to wait before we decide that a SQ is stuck. |
116 | * | |
117 | * Since both pkt rx and tx notifications are done with same CQ, | |
118 | * when packets are being received at very high rate (eg: L2 forwarding) | |
119 | * then freeing transmitted skbs will be delayed and watchdog | |
120 | * will kick in, resetting interface. Hence keeping this value high. | |
121 | */ | |
122 | #define NICVF_TX_TIMEOUT (50 * HZ) | |
123 | ||
4863dea3 | 124 | struct nicvf_cq_poll { |
39ad6eea | 125 | struct nicvf *nicvf; |
4863dea3 SG |
126 | u8 cq_idx; /* Completion queue index */ |
127 | struct napi_struct napi; | |
128 | }; | |
129 | ||
4863dea3 SG |
130 | #define NIC_MAX_RSS_HASH_BITS 8 |
131 | #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) | |
132 | #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ | |
133 | ||
134 | struct nicvf_rss_info { | |
135 | bool enable; | |
136 | #define RSS_L2_EXTENDED_HASH_ENA BIT(0) | |
137 | #define RSS_IP_HASH_ENA BIT(1) | |
138 | #define RSS_TCP_HASH_ENA BIT(2) | |
139 | #define RSS_TCP_SYN_DIS BIT(3) | |
140 | #define RSS_UDP_HASH_ENA BIT(4) | |
141 | #define RSS_L4_EXTENDED_HASH_ENA BIT(5) | |
142 | #define RSS_ROCE_ENA BIT(6) | |
143 | #define RSS_L3_BI_DIRECTION_ENA BIT(7) | |
144 | #define RSS_L4_BI_DIRECTION_ENA BIT(8) | |
145 | u64 cfg; | |
146 | u8 hash_bits; | |
147 | u16 rss_size; | |
148 | u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; | |
149 | u64 key[RSS_HASH_KEY_SIZE]; | |
150 | } ____cacheline_aligned_in_smp; | |
151 | ||
430da208 SG |
152 | struct nicvf_pfc { |
153 | u8 autoneg; | |
154 | u8 fc_rx; | |
155 | u8 fc_tx; | |
156 | }; | |
157 | ||
4863dea3 SG |
158 | enum rx_stats_reg_offset { |
159 | RX_OCTS = 0x0, | |
160 | RX_UCAST = 0x1, | |
161 | RX_BCAST = 0x2, | |
162 | RX_MCAST = 0x3, | |
163 | RX_RED = 0x4, | |
164 | RX_RED_OCTS = 0x5, | |
165 | RX_ORUN = 0x6, | |
166 | RX_ORUN_OCTS = 0x7, | |
167 | RX_FCS = 0x8, | |
168 | RX_L2ERR = 0x9, | |
169 | RX_DRP_BCAST = 0xa, | |
170 | RX_DRP_MCAST = 0xb, | |
171 | RX_DRP_L3BCAST = 0xc, | |
172 | RX_DRP_L3MCAST = 0xd, | |
173 | RX_STATS_ENUM_LAST, | |
174 | }; | |
175 | ||
176 | enum tx_stats_reg_offset { | |
177 | TX_OCTS = 0x0, | |
178 | TX_UCAST = 0x1, | |
179 | TX_BCAST = 0x2, | |
180 | TX_MCAST = 0x3, | |
181 | TX_DROP = 0x4, | |
182 | TX_STATS_ENUM_LAST, | |
183 | }; | |
184 | ||
185 | struct nicvf_hw_stats { | |
a2dc5ded | 186 | u64 rx_bytes; |
964cb69b | 187 | u64 rx_frames; |
a2dc5ded SG |
188 | u64 rx_ucast_frames; |
189 | u64 rx_bcast_frames; | |
190 | u64 rx_mcast_frames; | |
964cb69b | 191 | u64 rx_drops; |
4863dea3 SG |
192 | u64 rx_drop_red; |
193 | u64 rx_drop_red_bytes; | |
194 | u64 rx_drop_overrun; | |
195 | u64 rx_drop_overrun_bytes; | |
196 | u64 rx_drop_bcast; | |
197 | u64 rx_drop_mcast; | |
198 | u64 rx_drop_l3_bcast; | |
199 | u64 rx_drop_l3_mcast; | |
964cb69b SG |
200 | u64 rx_fcs_errors; |
201 | u64 rx_l2_errors; | |
202 | ||
203 | u64 tx_bytes; | |
204 | u64 tx_frames; | |
205 | u64 tx_ucast_frames; | |
206 | u64 tx_bcast_frames; | |
207 | u64 tx_mcast_frames; | |
208 | u64 tx_drops; | |
209 | }; | |
210 | ||
211 | struct nicvf_drv_stats { | |
212 | /* CQE Rx errs */ | |
a2dc5ded SG |
213 | u64 rx_bgx_truncated_pkts; |
214 | u64 rx_jabber_errs; | |
215 | u64 rx_fcs_errs; | |
216 | u64 rx_bgx_errs; | |
217 | u64 rx_prel2_errs; | |
218 | u64 rx_l2_hdr_malformed; | |
219 | u64 rx_oversize; | |
220 | u64 rx_undersize; | |
221 | u64 rx_l2_len_mismatch; | |
222 | u64 rx_l2_pclp; | |
223 | u64 rx_ip_ver_errs; | |
224 | u64 rx_ip_csum_errs; | |
225 | u64 rx_ip_hdr_malformed; | |
226 | u64 rx_ip_payload_malformed; | |
227 | u64 rx_ip_ttl_errs; | |
228 | u64 rx_l3_pclp; | |
229 | u64 rx_l4_malformed; | |
230 | u64 rx_l4_csum_errs; | |
231 | u64 rx_udp_len_errs; | |
232 | u64 rx_l4_port_errs; | |
233 | u64 rx_tcp_flag_errs; | |
234 | u64 rx_tcp_offset_errs; | |
235 | u64 rx_l4_pclp; | |
236 | u64 rx_truncated_pkts; | |
237 | ||
964cb69b SG |
238 | /* CQE Tx errs */ |
239 | u64 tx_desc_fault; | |
240 | u64 tx_hdr_cons_err; | |
241 | u64 tx_subdesc_err; | |
242 | u64 tx_max_size_exceeded; | |
243 | u64 tx_imm_size_oflow; | |
244 | u64 tx_data_seq_err; | |
245 | u64 tx_mem_seq_err; | |
246 | u64 tx_lock_viol; | |
247 | u64 tx_data_fault; | |
248 | u64 tx_tstmp_conflict; | |
249 | u64 tx_tstmp_timeout; | |
250 | u64 tx_mem_fault; | |
251 | u64 tx_csum_overlap; | |
252 | u64 tx_csum_overflow; | |
253 | ||
254 | /* driver debug stats */ | |
a05d4845 | 255 | u64 rcv_buffer_alloc_failures; |
4863dea3 | 256 | u64 tx_tso; |
a05d4845 | 257 | u64 tx_timeout; |
74840b83 SG |
258 | u64 txq_stop; |
259 | u64 txq_wake; | |
964cb69b SG |
260 | |
261 | struct u64_stats_sync syncp; | |
4863dea3 SG |
262 | }; |
263 | ||
264 | struct nicvf { | |
92dc8769 | 265 | struct nicvf *pnicvf; |
4863dea3 SG |
266 | struct net_device *netdev; |
267 | struct pci_dev *pdev; | |
1d368790 | 268 | void __iomem *reg_base; |
a5c3d498 | 269 | #define MAX_QUEUES_PER_QSET 8 |
1d368790 SG |
270 | struct queue_set *qs; |
271 | struct nicvf_cq_poll *napi[8]; | |
83abb7d7 | 272 | void *iommu_domain; |
4863dea3 | 273 | u8 vf_id; |
1d368790 SG |
274 | u8 sqs_id; |
275 | bool sqs_mode; | |
40fb5f8a | 276 | bool hw_tso; |
7ceb8a13 | 277 | bool t88; |
1d368790 SG |
278 | |
279 | /* Receive buffer alloc */ | |
280 | u32 rb_page_offset; | |
281 | u16 rb_pageref; | |
282 | bool rb_alloc_fail; | |
283 | bool rb_work_scheduled; | |
284 | struct page *rb_page; | |
285 | struct delayed_work rbdr_work; | |
286 | struct tasklet_struct rbdr_task; | |
287 | ||
288 | /* Secondary Qset */ | |
289 | u8 sqs_count; | |
92dc8769 SG |
290 | #define MAX_SQS_PER_VF_SINGLE_NODE 5 |
291 | #define MAX_SQS_PER_VF 11 | |
92dc8769 | 292 | struct nicvf *snicvf[MAX_SQS_PER_VF]; |
1d368790 SG |
293 | |
294 | /* Queue count */ | |
92dc8769 SG |
295 | u8 rx_queues; |
296 | u8 tx_queues; | |
297 | u8 max_queues; | |
1d368790 SG |
298 | |
299 | u8 node; | |
300 | u8 cpi_alg; | |
4863dea3 | 301 | bool link_up; |
1cc70259 | 302 | u8 mac_type; |
4863dea3 SG |
303 | u8 duplex; |
304 | u32 speed; | |
1d368790 SG |
305 | bool tns_mode; |
306 | bool loopback_supported; | |
4863dea3 | 307 | struct nicvf_rss_info rss_info; |
430da208 | 308 | struct nicvf_pfc pfc; |
1d368790 SG |
309 | struct tasklet_struct qs_err_task; |
310 | struct work_struct reset_task; | |
311 | ||
4863dea3 SG |
312 | /* Interrupt coalescing settings */ |
313 | u32 cq_coalesce_usecs; | |
4863dea3 | 314 | u32 msg_enable; |
1d368790 SG |
315 | |
316 | /* Stats */ | |
a2dc5ded | 317 | struct nicvf_hw_stats hw_stats; |
964cb69b | 318 | struct nicvf_drv_stats __percpu *drv_stats; |
4863dea3 | 319 | struct bgx_stats bgx_stats; |
4863dea3 SG |
320 | |
321 | /* MSI-X */ | |
322 | bool msix_enabled; | |
323 | u8 num_vec; | |
324 | struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; | |
b4e28c1f | 325 | char irq_name[NIC_VF_MSIX_VECTORS][IFNAMSIZ + 15]; |
4863dea3 | 326 | bool irq_allocated[NIC_VF_MSIX_VECTORS]; |
fb4b7d98 | 327 | cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS]; |
4863dea3 | 328 | |
6051cba7 | 329 | /* VF <-> PF mailbox communication */ |
4863dea3 SG |
330 | bool pf_acked; |
331 | bool pf_nacked; | |
bd049a90 | 332 | bool set_mac_pending; |
4863dea3 SG |
333 | } ____cacheline_aligned_in_smp; |
334 | ||
335 | /* PF <--> VF Mailbox communication | |
336 | * Eight 64bit registers are shared between PF and VF. | |
337 | * Separate set for each VF. | |
338 | * Writing '1' into last register mbx7 means end of message. | |
339 | */ | |
340 | ||
341 | /* PF <--> VF mailbox communication */ | |
342 | #define NIC_PF_VF_MAILBOX_SIZE 2 | |
343 | #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ | |
344 | ||
345 | /* Mailbox message types */ | |
346 | #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ | |
347 | #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ | |
348 | #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ | |
349 | #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ | |
350 | #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ | |
351 | #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ | |
352 | #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ | |
353 | #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ | |
354 | #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ | |
355 | #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ | |
356 | #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ | |
357 | #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ | |
358 | #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ | |
359 | #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ | |
360 | #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ | |
361 | #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ | |
362 | #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ | |
92dc8769 SG |
363 | #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ |
364 | #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ | |
365 | #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ | |
366 | #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ | |
d77a2384 | 367 | #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ |
3458c40d | 368 | #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */ |
430da208 | 369 | #define NIC_MBOX_MSG_PFC 0x18 /* Pause frame control */ |
92dc8769 SG |
370 | #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ |
371 | #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ | |
4863dea3 SG |
372 | |
373 | struct nic_cfg_msg { | |
374 | u8 msg; | |
375 | u8 vf_id; | |
4863dea3 | 376 | u8 node_id; |
92dc8769 SG |
377 | u8 tns_mode:1; |
378 | u8 sqs_mode:1; | |
d77a2384 | 379 | u8 loopback_supported:1; |
e610cb32 | 380 | u8 mac_addr[ETH_ALEN]; |
4863dea3 SG |
381 | }; |
382 | ||
383 | /* Qset configuration */ | |
384 | struct qs_cfg_msg { | |
385 | u8 msg; | |
386 | u8 num; | |
92dc8769 | 387 | u8 sqs_count; |
4863dea3 SG |
388 | u64 cfg; |
389 | }; | |
390 | ||
391 | /* Receive queue configuration */ | |
392 | struct rq_cfg_msg { | |
393 | u8 msg; | |
394 | u8 qs_num; | |
395 | u8 rq_num; | |
396 | u64 cfg; | |
397 | }; | |
398 | ||
399 | /* Send queue configuration */ | |
400 | struct sq_cfg_msg { | |
401 | u8 msg; | |
402 | u8 qs_num; | |
403 | u8 sq_num; | |
92dc8769 | 404 | bool sqs_mode; |
4863dea3 SG |
405 | u64 cfg; |
406 | }; | |
407 | ||
408 | /* Set VF's MAC address */ | |
409 | struct set_mac_msg { | |
410 | u8 msg; | |
411 | u8 vf_id; | |
e610cb32 | 412 | u8 mac_addr[ETH_ALEN]; |
4863dea3 SG |
413 | }; |
414 | ||
415 | /* Set Maximum frame size */ | |
416 | struct set_frs_msg { | |
417 | u8 msg; | |
418 | u8 vf_id; | |
419 | u16 max_frs; | |
420 | }; | |
421 | ||
422 | /* Set CPI algorithm type */ | |
423 | struct cpi_cfg_msg { | |
424 | u8 msg; | |
425 | u8 vf_id; | |
426 | u8 rq_cnt; | |
427 | u8 cpi_alg; | |
428 | }; | |
429 | ||
430 | /* Get RSS table size */ | |
431 | struct rss_sz_msg { | |
432 | u8 msg; | |
433 | u8 vf_id; | |
434 | u16 ind_tbl_size; | |
435 | }; | |
436 | ||
437 | /* Set RSS configuration */ | |
438 | struct rss_cfg_msg { | |
439 | u8 msg; | |
440 | u8 vf_id; | |
441 | u8 hash_bits; | |
442 | u8 tbl_len; | |
443 | u8 tbl_offset; | |
444 | #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 | |
445 | u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; | |
446 | }; | |
447 | ||
448 | struct bgx_stats_msg { | |
449 | u8 msg; | |
450 | u8 vf_id; | |
451 | u8 rx; | |
452 | u8 idx; | |
453 | u64 stats; | |
454 | }; | |
455 | ||
456 | /* Physical interface link status */ | |
457 | struct bgx_link_status { | |
458 | u8 msg; | |
1cc70259 | 459 | u8 mac_type; |
4863dea3 SG |
460 | u8 link_up; |
461 | u8 duplex; | |
462 | u32 speed; | |
463 | }; | |
464 | ||
92dc8769 SG |
465 | /* Get Extra Qset IDs */ |
466 | struct sqs_alloc { | |
467 | u8 msg; | |
468 | u8 vf_id; | |
469 | u8 qs_count; | |
470 | }; | |
471 | ||
472 | struct nicvf_ptr { | |
473 | u8 msg; | |
474 | u8 vf_id; | |
475 | bool sqs_mode; | |
476 | u8 sqs_id; | |
477 | u64 nicvf; | |
478 | }; | |
479 | ||
d77a2384 SG |
480 | /* Set interface in loopback mode */ |
481 | struct set_loopback { | |
482 | u8 msg; | |
483 | u8 vf_id; | |
484 | bool enable; | |
485 | }; | |
486 | ||
3458c40d JJ |
487 | /* Reset statistics counters */ |
488 | struct reset_stat_cfg { | |
489 | u8 msg; | |
490 | /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */ | |
491 | u16 rx_stat_mask; | |
492 | /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */ | |
493 | u8 tx_stat_mask; | |
494 | /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1) | |
495 | * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1) | |
496 | * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1) | |
497 | * .. | |
498 | * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1) | |
499 | * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1) | |
500 | */ | |
501 | u16 rq_stat_mask; | |
502 | /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1) | |
503 | * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1) | |
504 | * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1) | |
505 | * .. | |
506 | * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1) | |
507 | * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1) | |
508 | */ | |
509 | u16 sq_stat_mask; | |
510 | }; | |
511 | ||
430da208 SG |
512 | struct pfc { |
513 | u8 msg; | |
514 | u8 get; /* Get or set PFC settings */ | |
515 | u8 autoneg; | |
516 | u8 fc_rx; | |
517 | u8 fc_tx; | |
518 | }; | |
519 | ||
4863dea3 SG |
520 | /* 128 bit shared memory between PF and each VF */ |
521 | union nic_mbx { | |
522 | struct { u8 msg; } msg; | |
523 | struct nic_cfg_msg nic_cfg; | |
524 | struct qs_cfg_msg qs; | |
525 | struct rq_cfg_msg rq; | |
526 | struct sq_cfg_msg sq; | |
527 | struct set_mac_msg mac; | |
528 | struct set_frs_msg frs; | |
529 | struct cpi_cfg_msg cpi_cfg; | |
530 | struct rss_sz_msg rss_size; | |
531 | struct rss_cfg_msg rss_cfg; | |
532 | struct bgx_stats_msg bgx_stats; | |
533 | struct bgx_link_status link_status; | |
92dc8769 SG |
534 | struct sqs_alloc sqs_alloc; |
535 | struct nicvf_ptr nicvf; | |
d77a2384 | 536 | struct set_loopback lbk; |
3458c40d | 537 | struct reset_stat_cfg reset_stat; |
430da208 | 538 | struct pfc pfc; |
4863dea3 SG |
539 | }; |
540 | ||
d768b678 RR |
541 | #define NIC_NODE_ID_MASK 0x03 |
542 | #define NIC_NODE_ID_SHIFT 44 | |
543 | ||
544 | static inline int nic_get_node_id(struct pci_dev *pdev) | |
545 | { | |
546 | u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); | |
547 | return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); | |
548 | } | |
549 | ||
40fb5f8a SG |
550 | static inline bool pass1_silicon(struct pci_dev *pdev) |
551 | { | |
02a72bd8 SG |
552 | return (pdev->revision < 8) && |
553 | (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); | |
554 | } | |
555 | ||
556 | static inline bool pass2_silicon(struct pci_dev *pdev) | |
557 | { | |
558 | return (pdev->revision >= 8) && | |
559 | (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); | |
40fb5f8a SG |
560 | } |
561 | ||
4863dea3 SG |
562 | int nicvf_set_real_num_queues(struct net_device *netdev, |
563 | int tx_queues, int rx_queues); | |
564 | int nicvf_open(struct net_device *netdev); | |
565 | int nicvf_stop(struct net_device *netdev); | |
566 | int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); | |
4863dea3 SG |
567 | void nicvf_config_rss(struct nicvf *nic); |
568 | void nicvf_set_rss_key(struct nicvf *nic); | |
4863dea3 SG |
569 | void nicvf_set_ethtool_ops(struct net_device *netdev); |
570 | void nicvf_update_stats(struct nicvf *nic); | |
571 | void nicvf_update_lmac_stats(struct nicvf *nic); | |
572 | ||
573 | #endif /* NIC_H */ |