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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cavium / thunder / nic_main.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <linux/etherdevice.h>
13#include <linux/of.h>
14
15#include "nic_reg.h"
16#include "nic.h"
17#include "q_struct.h"
18#include "thunder_bgx.h"
19
20#define DRV_NAME "thunder-nic"
21#define DRV_VERSION "1.0"
22
23struct nicpf {
24 struct pci_dev *pdev;
4863dea3
SG		 25 u8 node;
26 unsigned int flags;
27 u8 num_vf_en; /* No of VF enabled */
28 bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
29 void __iomem *reg_base; /* Register start address */
92dc8769
SG		 30 u8 num_sqs_en; /* Secondary qsets enabled */
31 u64 nicvf[MAX_NUM_VFS_SUPPORTED];
32 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
33 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
34 bool sqs_used[MAX_NUM_VFS_SUPPORTED];
4863dea3
SG		 35 struct pkind_cfg pkind;
36#define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
37#define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
38#define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
39 u8 vf_lmac_map[MAX_LMAC];
40 struct delayed_work dwork;
41 struct workqueue_struct *check_link;
42 u8 link[MAX_LMAC];
43 u8 duplex[MAX_LMAC];
44 u32 speed[MAX_LMAC];
45 u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
34411b68 46 u16 rssi_base[MAX_NUM_VFS_SUPPORTED];
4863dea3
SG		 47 u16 rss_ind_tbl_size;
48 bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
49
50 /* MSI-X */
51 bool msix_enabled;
52 u8 num_vec;
53 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS];
54 bool irq_allocated[NIC_PF_MSIX_VECTORS];
55};
56
57/* Supported devices */
58static const struct pci_device_id nic_id_table[] = {
59 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
60 { 0, } /* end of table */
61};
62
63MODULE_AUTHOR("Sunil Goutham");
64MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
65MODULE_LICENSE("GPL v2");
66MODULE_VERSION(DRV_VERSION);
67MODULE_DEVICE_TABLE(pci, nic_id_table);
68
69/* The Cavium ThunderX network controller can *only* be found in SoCs
70 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
71 * registers on this platform are implicitly strongly ordered with respect
72 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
73 * with no memory barriers in this driver. The readq()/writeq() functions add
74 * explicit ordering operation which in this case are redundant, and only
75 * add overhead.
76 */
77
78/* Register read/write APIs */
79static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
80{
81 writeq_relaxed(val, nic->reg_base + offset);
82}
83
84static u64 nic_reg_read(struct nicpf *nic, u64 offset)
85{
86 return readq_relaxed(nic->reg_base + offset);
87}
88
89/* PF -> VF mailbox communication APIs */
90static void nic_enable_mbx_intr(struct nicpf *nic)
91{
92 /* Enable mailbox interrupt for all 128 VFs */
93 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull);
94 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull);
95}
96
97static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
98{
99 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
100}
101
102static u64 nic_get_mbx_addr(int vf)
103{
104 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
105}
106
107/* Send a mailbox message to VF
108 * @vf: vf to which this message to be sent
109 * @mbx: Message to be sent
110 */
111static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
112{
113 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
114 u64 *msg = (u64 *)mbx;
115
116 /* In first revision HW, mbox interrupt is triggerred
117 * when PF writes to MBOX(1), in next revisions when
118 * PF writes to MBOX(0)
119 */
40fb5f8a 120 if (pass1_silicon(nic->pdev)) {
4863dea3
SG		 121 /* see the comment for nic_reg_write()/nic_reg_read()
122 * functions above
123 */
124 writeq_relaxed(msg[0], mbx_addr);
125 writeq_relaxed(msg[1], mbx_addr + 8);
126 } else {
127 writeq_relaxed(msg[1], mbx_addr + 8);
128 writeq_relaxed(msg[0], mbx_addr);
129 }
130}
131
132/* Responds to VF's READY message with VF's
133 * ID, node, MAC address e.t.c
134 * @vf: VF which sent READY message
135 */
136static void nic_mbx_send_ready(struct nicpf *nic, int vf)
137{
138 union nic_mbx mbx = {};
139 int bgx_idx, lmac;
140 const char *mac;
141
142 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
143 mbx.nic_cfg.vf_id = vf;
144
145 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
146
92dc8769
SG		 147 if (vf < MAX_LMAC) {
148 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
149 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
4863dea3 150
92dc8769
SG		 151 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
152 if (mac)
153 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
154 }
155 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false;
4863dea3 156 mbx.nic_cfg.node_id = nic->node;
d77a2384
SG		 157
158 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC;
159
4863dea3
SG		 160 nic_send_msg_to_vf(nic, vf, &mbx);
161}
162
163/* ACKs VF's mailbox message
164 * @vf: VF to which ACK to be sent
165 */
166static void nic_mbx_send_ack(struct nicpf *nic, int vf)
167{
168 union nic_mbx mbx = {};
169
170 mbx.msg.msg = NIC_MBOX_MSG_ACK;
171 nic_send_msg_to_vf(nic, vf, &mbx);
172}
173
174/* NACKs VF's mailbox message that PF is not able to
175 * complete the action
176 * @vf: VF to which ACK to be sent
177 */
178static void nic_mbx_send_nack(struct nicpf *nic, int vf)
179{
180 union nic_mbx mbx = {};
181
182 mbx.msg.msg = NIC_MBOX_MSG_NACK;
183 nic_send_msg_to_vf(nic, vf, &mbx);
184}
185
186/* Flush all in flight receive packets to memory and
187 * bring down an active RQ
188 */
189static int nic_rcv_queue_sw_sync(struct nicpf *nic)
190{
191 u16 timeout = ~0x00;
192
193 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
194 /* Wait till sync cycle is finished */
195 while (timeout) {
196 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
197 break;
198 timeout--;
199 }
200 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
201 if (!timeout) {
202 dev_err(&nic->pdev->dev, "Receive queue software sync failed");
203 return 1;
204 }
205 return 0;
206}
207
208/* Get BGX Rx/Tx stats and respond to VF's request */
209static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
210{
211 int bgx_idx, lmac;
212 union nic_mbx mbx = {};
213
214 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
215 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
216
217 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
218 mbx.bgx_stats.vf_id = bgx->vf_id;
219 mbx.bgx_stats.rx = bgx->rx;
220 mbx.bgx_stats.idx = bgx->idx;
221 if (bgx->rx)
222 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
223 lmac, bgx->idx);
224 else
225 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
226 lmac, bgx->idx);
227 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
228}
229
230/* Update hardware min/max frame size */
231static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
232{
233 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) {
234 dev_err(&nic->pdev->dev,
235 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
236 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);
237 return 1;
238 }
239 new_frs += ETH_HLEN;
240 if (new_frs <= nic->pkind.maxlen)
241 return 0;
242
243 nic->pkind.maxlen = new_frs;
244 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind);
245 return 0;
246}
247
248/* Set minimum transmit packet size */
249static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
250{
251 int lmac;
252 u64 lmac_cfg;
253
254 /* Max value that can be set is 60 */
255 if (size > 60)
256 size = 60;
257
258 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) {
259 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
260 lmac_cfg &= ~(0xF << 2);
261 lmac_cfg |= ((size / 4) << 2);
262 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
263 }
264}
265
266/* Function to check number of LMACs present and set VF::LMAC mapping.
267 * Mapping will be used while initializing channels.
268 */
269static void nic_set_lmac_vf_mapping(struct nicpf *nic)
270{
271 unsigned bgx_map = bgx_get_map(nic->node);
272 int bgx, next_bgx_lmac = 0;
273 int lmac, lmac_cnt = 0;
274 u64 lmac_credit;
275
276 nic->num_vf_en = 0;
277
278 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) {
279 if (!(bgx_map & (1 << bgx)))
280 continue;
281 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
282 for (lmac = 0; lmac < lmac_cnt; lmac++)
283 nic->vf_lmac_map[next_bgx_lmac++] =
284 NIC_SET_VF_LMAC_MAP(bgx, lmac);
285 nic->num_vf_en += lmac_cnt;
286
287 /* Program LMAC credits */
288 lmac_credit = (1ull << 1); /* channel credit enable */
289 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
290 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
291 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
292 NIC_HW_MAX_FRS) / 16) << 12);
293 lmac = bgx * MAX_LMAC_PER_BGX;
294 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
295 nic_reg_write(nic,
296 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
297 lmac_credit);
298 }
299}
300
301#define BGX0_BLOCK 8
302#define BGX1_BLOCK 9
303
304static void nic_init_hw(struct nicpf *nic)
305{
306 int i;
307
4863dea3
SG		 308 /* Enable NIC HW block */
309 nic_reg_write(nic, NIC_PF_CFG, 0x3);
310
311 /* Enable backpressure */
312 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
313
314 /* Disable TNS mode on both interfaces */
315 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
316 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
317 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
318 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
319 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
320 (1ULL << 63) | BGX0_BLOCK);
321 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
322 (1ULL << 63) | BGX1_BLOCK);
323
324 /* PKIND configuration */
325 nic->pkind.minlen = 0;
326 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN;
327 nic->pkind.lenerr_en = 1;
328 nic->pkind.rx_hdr = 0;
329 nic->pkind.hdr_sl = 0;
330
331 for (i = 0; i < NIC_MAX_PKIND; i++)
332 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
333 *(u64 *)&nic->pkind);
334
335 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
336
337 /* Timer config */
338 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
aa2e259b
SG		 339
340 /* Enable VLAN ethertype matching and stripping */
341 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
342 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q);
4863dea3
SG		 343}
344
345/* Channel parse index configuration */
346static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
347{
348 u32 vnic, bgx, lmac, chan;
349 u32 padd, cpi_count = 0;
350 u64 cpi_base, cpi, rssi_base, rssi;
351 u8 qset, rq_idx = 0;
352
353 vnic = cfg->vf_id;
354 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
355 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
356
357 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
358 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX);
359 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX);
360
361 /* Rx channel configuration */
362 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
363 (1ull << 63) | (vnic << 0));
364 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
365 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
366
367 if (cfg->cpi_alg == CPI_ALG_NONE)
368 cpi_count = 1;
369 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
370 cpi_count = 8;
371 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
372 cpi_count = 16;
373 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
374 cpi_count = NIC_MAX_CPI_PER_LMAC;
375
376 /* RSS Qset, Qidx mapping */
377 qset = cfg->vf_id;
378 rssi = rssi_base;
379 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
380 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
381 (qset << 3) | rq_idx);
382 rq_idx++;
383 }
384
385 rssi = 0;
386 cpi = cpi_base;
387 for (; cpi < (cpi_base + cpi_count); cpi++) {
388 /* Determine port to channel adder */
389 if (cfg->cpi_alg != CPI_ALG_DIFF)
390 padd = cpi % cpi_count;
391 else
392 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
393
394 /* Leave RSS_SIZE as '0' to disable RSS */
40fb5f8a 395 if (pass1_silicon(nic->pdev)) {
34411b68
TS		 396 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
397 (vnic << 24) | (padd << 16) |
398 (rssi_base + rssi));
399 } else {
400 /* Set MPI_ALG to '0' to disable MCAM parsing */
401 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
402 (padd << 16));
403 /* MPI index is same as CPI if MPI_ALG is not enabled */
404 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3),
405 (vnic << 24) | (rssi_base + rssi));
406 }
4863dea3
SG		 407
408 if ((rssi + 1) >= cfg->rq_cnt)
409 continue;
410
411 if (cfg->cpi_alg == CPI_ALG_VLAN)
412 rssi++;
413 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
414 rssi = ((cpi - cpi_base) & 0xe) >> 1;
415 else if (cfg->cpi_alg == CPI_ALG_DIFF)
416 rssi = ((cpi - cpi_base) & 0x38) >> 3;
417 }
418 nic->cpi_base[cfg->vf_id] = cpi_base;
34411b68 419 nic->rssi_base[cfg->vf_id] = rssi_base;
4863dea3
SG		 420}
421
422/* Responsds to VF with its RSS indirection table size */
423static void nic_send_rss_size(struct nicpf *nic, int vf)
424{
425 union nic_mbx mbx = {};
426 u64 *msg;
427
428 msg = (u64 *)&mbx;
429
430 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
431 mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
432 nic_send_msg_to_vf(nic, vf, &mbx);
433}
434
435/* Receive side scaling configuration
436 * configure:
437 * - RSS index
438 * - indir table i.e hash::RQ mapping
439 * - no of hash bits to consider
440 */
441static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
442{
443 u8 qset, idx = 0;
444 u64 cpi_cfg, cpi_base, rssi_base, rssi;
34411b68 445 u64 idx_addr;
4863dea3 446
34411b68 447 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;
4863dea3
SG		 448
449 rssi = rssi_base;
450 qset = cfg->vf_id;
451
452 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
92dc8769
SG		 453 u8 svf = cfg->ind_tbl[idx] >> 3;
454
455 if (svf)
456 qset = nic->vf_sqs[cfg->vf_id][svf - 1];
457 else
458 qset = cfg->vf_id;
4863dea3
SG		 459 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
460 (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
461 idx++;
462 }
463
34411b68 464 cpi_base = nic->cpi_base[cfg->vf_id];
40fb5f8a 465 if (pass1_silicon(nic->pdev))
34411b68
TS		 466 idx_addr = NIC_PF_CPI_0_2047_CFG;
467 else
468 idx_addr = NIC_PF_MPI_0_2047_CFG;
469 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));
4863dea3
SG		 470 cpi_cfg &= ~(0xFULL << 20);
471 cpi_cfg |= (cfg->hash_bits << 20);
34411b68 472 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
4863dea3
SG		 473}
474
475/* 4 level transmit side scheduler configutation
476 * for TNS bypass mode
477 *
478 * Sample configuration for SQ0
479 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
480 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
481 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
482 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
483 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
484 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
485 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
486 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
487 */
92dc8769
SG		 488static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
489 struct sq_cfg_msg *sq)
4863dea3
SG		 490{
491 u32 bgx, lmac, chan;
492 u32 tl2, tl3, tl4;
493 u32 rr_quantum;
92dc8769
SG		 494 u8 sq_idx = sq->sq_num;
495 u8 pqs_vnic;
496
497 if (sq->sqs_mode)
498 pqs_vnic = nic->pqs_vf[vnic];
499 else
500 pqs_vnic = vnic;
501
502 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
503 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
4863dea3 504
4863dea3
SG		 505 /* 24 bytes for FCS, IPG and preamble */
506 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
507
508 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX);
509 tl4 += sq_idx;
92dc8769
SG		 510 if (sq->sqs_mode)
511 tl4 += vnic * 8;
512
4863dea3
SG		 513 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3);
514 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
515 ((u64)vnic << NIC_QS_ID_SHIFT) |
516 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
517 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
518 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
519
520 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
521 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
522 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
523 /* Enable backpressure on the channel */
524 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
525
526 tl2 = tl3 >> 2;
527 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
528 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
529 /* No priorities as of now */
530 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
531}
532
92dc8769
SG		 533/* Send primary nicvf pointer to secondary QS's VF */
534static void nic_send_pnicvf(struct nicpf *nic, int sqs)
535{
536 union nic_mbx mbx = {};
537
538 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
539 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]];
540 nic_send_msg_to_vf(nic, sqs, &mbx);
541}
542
543/* Send SQS's nicvf pointer to primary QS's VF */
544static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf)
545{
546 union nic_mbx mbx = {};
547 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id];
548
549 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
550 mbx.nicvf.sqs_id = nicvf->sqs_id;
551 mbx.nicvf.nicvf = nic->nicvf[sqs_id];
552 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx);
553}
554
555/* Find next available Qset that can be assigned as a
556 * secondary Qset to a VF.
557 */
558static int nic_nxt_avail_sqs(struct nicpf *nic)
559{
560 int sqs;
561
562 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) {
563 if (!nic->sqs_used[sqs])
564 nic->sqs_used[sqs] = true;
565 else
566 continue;
567 return sqs + nic->num_vf_en;
568 }
569 return -1;
570}
571
572/* Allocate additional Qsets for requested VF */
573static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs)
574{
575 union nic_mbx mbx = {};
576 int idx, alloc_qs = 0;
577 int sqs_id;
578
579 if (!nic->num_sqs_en)
580 goto send_mbox;
581
582 for (idx = 0; idx < sqs->qs_count; idx++) {
583 sqs_id = nic_nxt_avail_sqs(nic);
584 if (sqs_id < 0)
585 break;
586 nic->vf_sqs[sqs->vf_id][idx] = sqs_id;
587 nic->pqs_vf[sqs_id] = sqs->vf_id;
588 alloc_qs++;
589 }
590
591send_mbox:
592 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
593 mbx.sqs_alloc.vf_id = sqs->vf_id;
594 mbx.sqs_alloc.qs_count = alloc_qs;
595 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx);
596}
597
d77a2384
SG		 598static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk)
599{
600 int bgx_idx, lmac_idx;
601
602 if (lbk->vf_id > MAX_LMAC)
603 return -1;
604
605 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
606 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
607
608 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable);
609
610 return 0;
611}
612
f406ce42
PF		 613static void nic_enable_vf(struct nicpf *nic, int vf, bool enable)
614{
615 int bgx, lmac;
616
617 nic->vf_enabled[vf] = enable;
618
619 if (vf >= nic->num_vf_en)
620 return;
621
622 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
623 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
624
625 bgx_lmac_rx_tx_enable(nic->node, bgx, lmac, enable);
626}
627
4863dea3
SG		 628/* Interrupt handler to handle mailbox messages from VFs */
629static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
630{
631 union nic_mbx mbx = {};
632 u64 *mbx_data;
633 u64 mbx_addr;
634 u64 reg_addr;
92dc8769 635 u64 cfg;
4863dea3
SG		 636 int bgx, lmac;
637 int i;
638 int ret = 0;
639
640 nic->mbx_lock[vf] = true;
641
642 mbx_addr = nic_get_mbx_addr(vf);
643 mbx_data = (u64 *)&mbx;
644
645 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
646 *mbx_data = nic_reg_read(nic, mbx_addr);
647 mbx_data++;
648 mbx_addr += sizeof(u64);
649 }
650
651 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg %d from VF%d\n",
652 __func__, mbx.msg.msg, vf);
653 switch (mbx.msg.msg) {
654 case NIC_MBOX_MSG_READY:
655 nic_mbx_send_ready(nic, vf);
92dc8769
SG		 656 if (vf < MAX_LMAC) {
657 nic->link[vf] = 0;
658 nic->duplex[vf] = 0;
659 nic->speed[vf] = 0;
660 }
4863dea3
SG		 661 ret = 1;
662 break;
663 case NIC_MBOX_MSG_QS_CFG:
664 reg_addr = NIC_PF_QSET_0_127_CFG |
665 (mbx.qs.num << NIC_QS_ID_SHIFT);
92dc8769
SG		 666 cfg = mbx.qs.cfg;
667 /* Check if its a secondary Qset */
668 if (vf >= nic->num_vf_en) {
669 cfg = cfg & (~0x7FULL);
670 /* Assign this Qset to primary Qset's VF */
671 cfg |= nic->pqs_vf[vf];
672 }
673 nic_reg_write(nic, reg_addr, cfg);
4863dea3
SG		 674 break;
675 case NIC_MBOX_MSG_RQ_CFG:
676 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
677 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
678 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
679 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
680 break;
681 case NIC_MBOX_MSG_RQ_BP_CFG:
682 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
683 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
684 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
685 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
686 break;
687 case NIC_MBOX_MSG_RQ_SW_SYNC:
688 ret = nic_rcv_queue_sw_sync(nic);
689 break;
690 case NIC_MBOX_MSG_RQ_DROP_CFG:
691 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
692 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
693 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
694 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
695 break;
696 case NIC_MBOX_MSG_SQ_CFG:
697 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
698 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
699 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
700 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
92dc8769 701 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
4863dea3
SG		 702 break;
703 case NIC_MBOX_MSG_SET_MAC:
92dc8769
SG		 704 if (vf >= nic->num_vf_en)
705 break;
4863dea3
SG		 706 lmac = mbx.mac.vf_id;
707 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
708 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
e610cb32 709 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
4863dea3
SG		 710 break;
711 case NIC_MBOX_MSG_SET_MAX_FRS:
712 ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
713 mbx.frs.vf_id);
714 break;
715 case NIC_MBOX_MSG_CPI_CFG:
716 nic_config_cpi(nic, &mbx.cpi_cfg);
717 break;
718 case NIC_MBOX_MSG_RSS_SIZE:
719 nic_send_rss_size(nic, vf);
720 goto unlock;
721 case NIC_MBOX_MSG_RSS_CFG:
722 case NIC_MBOX_MSG_RSS_CFG_CONT:
723 nic_config_rss(nic, &mbx.rss_cfg);
724 break;
725 case NIC_MBOX_MSG_CFG_DONE:
726 /* Last message of VF config msg sequence */
f406ce42 727 nic_enable_vf(nic, vf, true);
4863dea3
SG		 728 goto unlock;
729 case NIC_MBOX_MSG_SHUTDOWN:
730 /* First msg in VF teardown sequence */
92dc8769
SG		 731 if (vf >= nic->num_vf_en)
732 nic->sqs_used[vf - nic->num_vf_en] = false;
733 nic->pqs_vf[vf] = 0;
f406ce42 734 nic_enable_vf(nic, vf, false);
92dc8769
SG		 735 break;
736 case NIC_MBOX_MSG_ALLOC_SQS:
737 nic_alloc_sqs(nic, &mbx.sqs_alloc);
738 goto unlock;
739 case NIC_MBOX_MSG_NICVF_PTR:
740 nic->nicvf[vf] = mbx.nicvf.nicvf;
4863dea3 741 break;
92dc8769
SG		 742 case NIC_MBOX_MSG_PNICVF_PTR:
743 nic_send_pnicvf(nic, vf);
744 goto unlock;
745 case NIC_MBOX_MSG_SNICVF_PTR:
746 nic_send_snicvf(nic, &mbx.nicvf);
747 goto unlock;
4863dea3
SG		 748 case NIC_MBOX_MSG_BGX_STATS:
749 nic_get_bgx_stats(nic, &mbx.bgx_stats);
750 goto unlock;
d77a2384
SG		 751 case NIC_MBOX_MSG_LOOPBACK:
752 ret = nic_config_loopback(nic, &mbx.lbk);
753 break;
4863dea3
SG		 754 default:
755 dev_err(&nic->pdev->dev,
756 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
757 break;
758 }
759
760 if (!ret)
761 nic_mbx_send_ack(nic, vf);
762 else if (mbx.msg.msg != NIC_MBOX_MSG_READY)
763 nic_mbx_send_nack(nic, vf);
764unlock:
765 nic->mbx_lock[vf] = false;
766}
767
768static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
769{
770 u64 intr;
771 u8 vf, vf_per_mbx_reg = 64;
772
773 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
774 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
775 for (vf = 0; vf < vf_per_mbx_reg; vf++) {
776 if (intr & (1ULL << vf)) {
777 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
778 vf + (mbx * vf_per_mbx_reg));
92dc8769 779
4863dea3
SG		 780 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
781 nic_clear_mbx_intr(nic, vf, mbx);
782 }
783 }
784}
785
786static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq)
787{
788 struct nicpf *nic = (struct nicpf *)nic_irq;
789
790 nic_mbx_intr_handler(nic, 0);
791
792 return IRQ_HANDLED;
793}
794
795static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq)
796{
797 struct nicpf *nic = (struct nicpf *)nic_irq;
798
799 nic_mbx_intr_handler(nic, 1);
800
801 return IRQ_HANDLED;
802}
803
804static int nic_enable_msix(struct nicpf *nic)
805{
806 int i, ret;
807
808 nic->num_vec = NIC_PF_MSIX_VECTORS;
809
810 for (i = 0; i < nic->num_vec; i++)
811 nic->msix_entries[i].entry = i;
812
813 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
814 if (ret) {
815 dev_err(&nic->pdev->dev,
816 "Request for #%d msix vectors failed\n",
817 nic->num_vec);
818 return ret;
819 }
820
821 nic->msix_enabled = 1;
822 return 0;
823}
824
825static void nic_disable_msix(struct nicpf *nic)
826{
827 if (nic->msix_enabled) {
828 pci_disable_msix(nic->pdev);
829 nic->msix_enabled = 0;
830 nic->num_vec = 0;
831 }
832}
833
834static void nic_free_all_interrupts(struct nicpf *nic)
835{
836 int irq;
837
838 for (irq = 0; irq < nic->num_vec; irq++) {
839 if (nic->irq_allocated[irq])
840 free_irq(nic->msix_entries[irq].vector, nic);
841 nic->irq_allocated[irq] = false;
842 }
843}
844
845static int nic_register_interrupts(struct nicpf *nic)
846{
847 int ret;
848
849 /* Enable MSI-X */
850 ret = nic_enable_msix(nic);
851 if (ret)
852 return ret;
853
854 /* Register mailbox interrupt handlers */
855 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector,
856 nic_mbx0_intr_handler, 0, "NIC Mbox0", nic);
857 if (ret)
858 goto fail;
859
860 nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true;
861
862 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector,
863 nic_mbx1_intr_handler, 0, "NIC Mbox1", nic);
864 if (ret)
865 goto fail;
866
867 nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true;
868
869 /* Enable mailbox interrupt */
870 nic_enable_mbx_intr(nic);
871 return 0;
872
873fail:
874 dev_err(&nic->pdev->dev, "Request irq failed\n");
875 nic_free_all_interrupts(nic);
876 return ret;
877}
878
879static void nic_unregister_interrupts(struct nicpf *nic)
880{
881 nic_free_all_interrupts(nic);
882 nic_disable_msix(nic);
883}
884
92dc8769
SG		 885static int nic_num_sqs_en(struct nicpf *nic, int vf_en)
886{
887 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE;
888 u16 total_vf;
889
890 /* Check if its a multi-node environment */
891 if (nr_node_ids > 1)
892 sqs_per_vf = MAX_SQS_PER_VF;
893
894 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV);
895 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf);
896 return min(total_vf - vf_en, vf_en * sqs_per_vf);
897}
898
4863dea3
SG		 899static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
900{
901 int pos = 0;
92dc8769 902 int vf_en;
4863dea3
SG		 903 int err;
904 u16 total_vf_cnt;
905
906 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
907 if (!pos) {
908 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
909 return -ENODEV;
910 }
911
912 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
913 if (total_vf_cnt < nic->num_vf_en)
914 nic->num_vf_en = total_vf_cnt;
915
916 if (!total_vf_cnt)
917 return 0;
918
92dc8769
SG		 919 vf_en = nic->num_vf_en;
920 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en);
921 vf_en += nic->num_sqs_en;
922
923 err = pci_enable_sriov(pdev, vf_en);
4863dea3
SG		 924 if (err) {
925 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
92dc8769 926 vf_en);
4863dea3
SG		 927 nic->num_vf_en = 0;
928 return err;
929 }
930
931 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
92dc8769 932 vf_en);
4863dea3
SG		 933
934 nic->flags |= NIC_SRIOV_ENABLED;
935 return 0;
936}
937
938/* Poll for BGX LMAC link status and update corresponding VF
939 * if there is a change, valid only if internal L2 switch
940 * is not present otherwise VF link is always treated as up
941 */
942static void nic_poll_for_link(struct work_struct *work)
943{
944 union nic_mbx mbx = {};
945 struct nicpf *nic;
946 struct bgx_link_status link;
947 u8 vf, bgx, lmac;
948
949 nic = container_of(work, struct nicpf, dwork.work);
950
951 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
952
f406ce42 953 for (vf = 0; vf < nic->num_vf_en; vf++) {
4863dea3
SG		 954 /* Poll only if VF is UP */
955 if (!nic->vf_enabled[vf])
956 continue;
957
958 /* Get BGX, LMAC indices for the VF */
959 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
960 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
961 /* Get interface link status */
962 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
963
964 /* Inform VF only if link status changed */
965 if (nic->link[vf] == link.link_up)
966 continue;
967
968 if (!nic->mbx_lock[vf]) {
969 nic->link[vf] = link.link_up;
970 nic->duplex[vf] = link.duplex;
971 nic->speed[vf] = link.speed;
972
973 /* Send a mbox message to VF with current link status */
974 mbx.link_status.link_up = link.link_up;
975 mbx.link_status.duplex = link.duplex;
976 mbx.link_status.speed = link.speed;
977 nic_send_msg_to_vf(nic, vf, &mbx);
978 }
979 }
980 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2);
981}
982
983static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
984{
985 struct device *dev = &pdev->dev;
986 struct nicpf *nic;
987 int err;
988
989 BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
990
991 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
992 if (!nic)
993 return -ENOMEM;
994
995 pci_set_drvdata(pdev, nic);
996
997 nic->pdev = pdev;
998
999 err = pci_enable_device(pdev);
1000 if (err) {
1001 dev_err(dev, "Failed to enable PCI device\n");
1002 pci_set_drvdata(pdev, NULL);
1003 return err;
1004 }
1005
1006 err = pci_request_regions(pdev, DRV_NAME);
1007 if (err) {
1008 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1009 goto err_disable_device;
1010 }
1011
1012 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1013 if (err) {
1014 dev_err(dev, "Unable to get usable DMA configuration\n");
1015 goto err_release_regions;
1016 }
1017
1018 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1019 if (err) {
1020 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
1021 goto err_release_regions;
1022 }
1023
1024 /* MAP PF's configuration registers */
1025 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1026 if (!nic->reg_base) {
1027 dev_err(dev, "Cannot map config register space, aborting\n");
1028 err = -ENOMEM;
1029 goto err_release_regions;
1030 }
1031
d768b678 1032 nic->node = nic_get_node_id(pdev);
4863dea3
SG		 1033
1034 nic_set_lmac_vf_mapping(nic);
1035
1036 /* Initialize hardware */
1037 nic_init_hw(nic);
1038
1039 /* Set RSS TBL size for each VF */
1040 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
1041
1042 /* Register interrupts */
1043 err = nic_register_interrupts(nic);
1044 if (err)
1045 goto err_release_regions;
1046
1047 /* Configure SRIOV */
1048 err = nic_sriov_init(pdev, nic);
1049 if (err)
1050 goto err_unregister_interrupts;
1051
1052 /* Register a physical link status poll fn() */
1053 nic->check_link = alloc_workqueue("check_link_status",
1054 WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
1055 if (!nic->check_link) {
1056 err = -ENOMEM;
1057 goto err_disable_sriov;
1058 }
1059
1060 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link);
1061 queue_delayed_work(nic->check_link, &nic->dwork, 0);
1062
1063 return 0;
1064
1065err_disable_sriov:
1066 if (nic->flags & NIC_SRIOV_ENABLED)
1067 pci_disable_sriov(pdev);
1068err_unregister_interrupts:
1069 nic_unregister_interrupts(nic);
1070err_release_regions:
1071 pci_release_regions(pdev);
1072err_disable_device:
1073 pci_disable_device(pdev);
1074 pci_set_drvdata(pdev, NULL);
1075 return err;
1076}
1077
1078static void nic_remove(struct pci_dev *pdev)
1079{
1080 struct nicpf *nic = pci_get_drvdata(pdev);
1081
1082 if (nic->flags & NIC_SRIOV_ENABLED)
1083 pci_disable_sriov(pdev);
1084
1085 if (nic->check_link) {
1086 /* Destroy work Queue */
a7b1f535 1087 cancel_delayed_work_sync(&nic->dwork);
4863dea3
SG		 1088 destroy_workqueue(nic->check_link);
1089 }
1090
1091 nic_unregister_interrupts(nic);
1092 pci_release_regions(pdev);
1093 pci_disable_device(pdev);
1094 pci_set_drvdata(pdev, NULL);
1095}
1096
1097static struct pci_driver nic_driver = {
1098 .name = DRV_NAME,
1099 .id_table = nic_id_table,
1100 .probe = nic_probe,
1101 .remove = nic_remove,
1102};
1103
1104static int __init nic_init_module(void)
1105{
1106 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1107
1108 return pci_register_driver(&nic_driver);
1109}
1110
1111static void __exit nic_cleanup_module(void)
1112{
1113 pci_unregister_driver(&nic_driver);
1114}
1115
1116module_init(nic_init_module);
1117module_exit(nic_cleanup_module);
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