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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / cavium / thunder / nicvf_main.c
CommitLineData
4863dea3
SG
1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <linux/netdevice.h>
aa2e259b 13#include <linux/if_vlan.h>
4863dea3
SG
14#include <linux/etherdevice.h>
15#include <linux/ethtool.h>
16#include <linux/log2.h>
17#include <linux/prefetch.h>
18#include <linux/irq.h>
19
20#include "nic_reg.h"
21#include "nic.h"
22#include "nicvf_queues.h"
23#include "thunder_bgx.h"
24
25#define DRV_NAME "thunder-nicvf"
26#define DRV_VERSION "1.0"
27
28/* Supported devices */
29static const struct pci_device_id nicvf_id_table[] = {
30 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
31 PCI_DEVICE_ID_THUNDER_NIC_VF,
4e85777f 32 PCI_VENDOR_ID_CAVIUM, 0xA134) },
4863dea3
SG
33 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
34 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF,
35 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
36 { 0, } /* end of table */
37};
38
39MODULE_AUTHOR("Sunil Goutham");
40MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver");
41MODULE_LICENSE("GPL v2");
42MODULE_VERSION(DRV_VERSION);
43MODULE_DEVICE_TABLE(pci, nicvf_id_table);
44
45static int debug = 0x00;
46module_param(debug, int, 0644);
47MODULE_PARM_DESC(debug, "Debug message level bitmap");
48
49static int cpi_alg = CPI_ALG_NONE;
50module_param(cpi_alg, int, S_IRUGO);
51MODULE_PARM_DESC(cpi_alg,
52 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)");
53
92dc8769
SG
54static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx)
55{
56 if (nic->sqs_mode)
57 return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS);
58 else
59 return qidx;
60}
61
4863dea3
SG
62static inline void nicvf_set_rx_frame_cnt(struct nicvf *nic,
63 struct sk_buff *skb)
64{
65 if (skb->len <= 64)
66 nic->drv_stats.rx_frames_64++;
67 else if (skb->len <= 127)
68 nic->drv_stats.rx_frames_127++;
69 else if (skb->len <= 255)
70 nic->drv_stats.rx_frames_255++;
71 else if (skb->len <= 511)
72 nic->drv_stats.rx_frames_511++;
73 else if (skb->len <= 1023)
74 nic->drv_stats.rx_frames_1023++;
75 else if (skb->len <= 1518)
76 nic->drv_stats.rx_frames_1518++;
77 else
78 nic->drv_stats.rx_frames_jumbo++;
79}
80
81/* The Cavium ThunderX network controller can *only* be found in SoCs
82 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
83 * registers on this platform are implicitly strongly ordered with respect
84 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
85 * with no memory barriers in this driver. The readq()/writeq() functions add
86 * explicit ordering operation which in this case are redundant, and only
87 * add overhead.
88 */
89
90/* Register read/write APIs */
91void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val)
92{
93 writeq_relaxed(val, nic->reg_base + offset);
94}
95
96u64 nicvf_reg_read(struct nicvf *nic, u64 offset)
97{
98 return readq_relaxed(nic->reg_base + offset);
99}
100
101void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
102 u64 qidx, u64 val)
103{
104 void __iomem *addr = nic->reg_base + offset;
105
106 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT));
107}
108
109u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx)
110{
111 void __iomem *addr = nic->reg_base + offset;
112
113 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT));
114}
115
116/* VF -> PF mailbox communication */
2cd2a196
AM
117static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx)
118{
119 u64 *msg = (u64 *)mbx;
120
121 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]);
122 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]);
123}
124
4863dea3
SG
125int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx)
126{
127 int timeout = NIC_MBOX_MSG_TIMEOUT;
128 int sleep = 10;
4863dea3
SG
129
130 nic->pf_acked = false;
131 nic->pf_nacked = false;
132
2cd2a196 133 nicvf_write_to_mbx(nic, mbx);
4863dea3
SG
134
135 /* Wait for previous message to be acked, timeout 2sec */
136 while (!nic->pf_acked) {
137 if (nic->pf_nacked)
138 return -EINVAL;
139 msleep(sleep);
140 if (nic->pf_acked)
141 break;
142 timeout -= sleep;
143 if (!timeout) {
144 netdev_err(nic->netdev,
145 "PF didn't ack to mbox msg %d from VF%d\n",
146 (mbx->msg.msg & 0xFF), nic->vf_id);
147 return -EBUSY;
148 }
149 }
150 return 0;
151}
152
153/* Checks if VF is able to comminicate with PF
154* and also gets the VNIC number this VF is associated to.
155*/
156static int nicvf_check_pf_ready(struct nicvf *nic)
157{
2cd2a196
AM
158 union nic_mbx mbx = {};
159
160 mbx.msg.msg = NIC_MBOX_MSG_READY;
6051cba7
SG
161 if (nicvf_send_msg_to_pf(nic, &mbx)) {
162 netdev_err(nic->netdev,
163 "PF didn't respond to READY msg\n");
164 return 0;
4863dea3 165 }
6051cba7 166
4863dea3
SG
167 return 1;
168}
169
fd7ec062
AM
170static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx)
171{
172 if (bgx->rx)
173 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats;
174 else
175 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats;
176}
177
4863dea3
SG
178static void nicvf_handle_mbx_intr(struct nicvf *nic)
179{
180 union nic_mbx mbx = {};
181 u64 *mbx_data;
182 u64 mbx_addr;
183 int i;
184
185 mbx_addr = NIC_VF_PF_MAILBOX_0_1;
186 mbx_data = (u64 *)&mbx;
187
188 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
189 *mbx_data = nicvf_reg_read(nic, mbx_addr);
190 mbx_data++;
191 mbx_addr += sizeof(u64);
192 }
193
194 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg);
195 switch (mbx.msg.msg) {
196 case NIC_MBOX_MSG_READY:
6051cba7 197 nic->pf_acked = true;
4863dea3
SG
198 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F;
199 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F;
200 nic->node = mbx.nic_cfg.node_id;
bd049a90
PF
201 if (!nic->set_mac_pending)
202 ether_addr_copy(nic->netdev->dev_addr,
203 mbx.nic_cfg.mac_addr);
92dc8769 204 nic->sqs_mode = mbx.nic_cfg.sqs_mode;
d77a2384 205 nic->loopback_supported = mbx.nic_cfg.loopback_supported;
4863dea3
SG
206 nic->link_up = false;
207 nic->duplex = 0;
208 nic->speed = 0;
209 break;
210 case NIC_MBOX_MSG_ACK:
211 nic->pf_acked = true;
212 break;
213 case NIC_MBOX_MSG_NACK:
214 nic->pf_nacked = true;
215 break;
216 case NIC_MBOX_MSG_RSS_SIZE:
217 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size;
218 nic->pf_acked = true;
219 break;
220 case NIC_MBOX_MSG_BGX_STATS:
221 nicvf_read_bgx_stats(nic, &mbx.bgx_stats);
222 nic->pf_acked = true;
4863dea3
SG
223 break;
224 case NIC_MBOX_MSG_BGX_LINK_CHANGE:
225 nic->pf_acked = true;
226 nic->link_up = mbx.link_status.link_up;
227 nic->duplex = mbx.link_status.duplex;
228 nic->speed = mbx.link_status.speed;
229 if (nic->link_up) {
230 netdev_info(nic->netdev, "%s: Link is Up %d Mbps %s\n",
231 nic->netdev->name, nic->speed,
232 nic->duplex == DUPLEX_FULL ?
233 "Full duplex" : "Half duplex");
234 netif_carrier_on(nic->netdev);
b49087dd 235 netif_tx_start_all_queues(nic->netdev);
4863dea3
SG
236 } else {
237 netdev_info(nic->netdev, "%s: Link is Down\n",
238 nic->netdev->name);
239 netif_carrier_off(nic->netdev);
240 netif_tx_stop_all_queues(nic->netdev);
241 }
242 break;
92dc8769
SG
243 case NIC_MBOX_MSG_ALLOC_SQS:
244 nic->sqs_count = mbx.sqs_alloc.qs_count;
245 nic->pf_acked = true;
246 break;
247 case NIC_MBOX_MSG_SNICVF_PTR:
248 /* Primary VF: make note of secondary VF's pointer
249 * to be used while packet transmission.
250 */
251 nic->snicvf[mbx.nicvf.sqs_id] =
252 (struct nicvf *)mbx.nicvf.nicvf;
253 nic->pf_acked = true;
254 break;
255 case NIC_MBOX_MSG_PNICVF_PTR:
256 /* Secondary VF/Qset: make note of primary VF's pointer
257 * to be used while packet reception, to handover packet
258 * to primary VF's netdev.
259 */
260 nic->pnicvf = (struct nicvf *)mbx.nicvf.nicvf;
261 nic->pf_acked = true;
262 break;
4863dea3
SG
263 default:
264 netdev_err(nic->netdev,
265 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg);
266 break;
267 }
268 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0);
269}
270
271static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev)
272{
273 union nic_mbx mbx = {};
4863dea3
SG
274
275 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC;
276 mbx.mac.vf_id = nic->vf_id;
e610cb32 277 ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr);
4863dea3
SG
278
279 return nicvf_send_msg_to_pf(nic, &mbx);
280}
281
fd7ec062 282static void nicvf_config_cpi(struct nicvf *nic)
4863dea3
SG
283{
284 union nic_mbx mbx = {};
285
286 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG;
287 mbx.cpi_cfg.vf_id = nic->vf_id;
288 mbx.cpi_cfg.cpi_alg = nic->cpi_alg;
289 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt;
290
291 nicvf_send_msg_to_pf(nic, &mbx);
292}
293
fd7ec062 294static void nicvf_get_rss_size(struct nicvf *nic)
4863dea3
SG
295{
296 union nic_mbx mbx = {};
297
298 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
299 mbx.rss_size.vf_id = nic->vf_id;
300 nicvf_send_msg_to_pf(nic, &mbx);
301}
302
303void nicvf_config_rss(struct nicvf *nic)
304{
305 union nic_mbx mbx = {};
306 struct nicvf_rss_info *rss = &nic->rss_info;
307 int ind_tbl_len = rss->rss_size;
308 int i, nextq = 0;
309
310 mbx.rss_cfg.vf_id = nic->vf_id;
311 mbx.rss_cfg.hash_bits = rss->hash_bits;
312 while (ind_tbl_len) {
313 mbx.rss_cfg.tbl_offset = nextq;
314 mbx.rss_cfg.tbl_len = min(ind_tbl_len,
315 RSS_IND_TBL_LEN_PER_MBX_MSG);
316 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ?
317 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG;
318
319 for (i = 0; i < mbx.rss_cfg.tbl_len; i++)
320 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++];
321
322 nicvf_send_msg_to_pf(nic, &mbx);
323
324 ind_tbl_len -= mbx.rss_cfg.tbl_len;
325 }
326}
327
328void nicvf_set_rss_key(struct nicvf *nic)
329{
330 struct nicvf_rss_info *rss = &nic->rss_info;
331 u64 key_addr = NIC_VNIC_RSS_KEY_0_4;
332 int idx;
333
334 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
335 nicvf_reg_write(nic, key_addr, rss->key[idx]);
336 key_addr += sizeof(u64);
337 }
338}
339
340static int nicvf_rss_init(struct nicvf *nic)
341{
342 struct nicvf_rss_info *rss = &nic->rss_info;
343 int idx;
344
345 nicvf_get_rss_size(nic);
346
38bb5d4f 347 if (cpi_alg != CPI_ALG_NONE) {
4863dea3
SG
348 rss->enable = false;
349 rss->hash_bits = 0;
350 return 0;
351 }
352
353 rss->enable = true;
354
355 /* Using the HW reset value for now */
4a4f87d8
AM
356 rss->key[0] = 0xFEED0BADFEED0BADULL;
357 rss->key[1] = 0xFEED0BADFEED0BADULL;
358 rss->key[2] = 0xFEED0BADFEED0BADULL;
359 rss->key[3] = 0xFEED0BADFEED0BADULL;
360 rss->key[4] = 0xFEED0BADFEED0BADULL;
4863dea3
SG
361
362 nicvf_set_rss_key(nic);
363
364 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA;
365 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg);
366
367 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size));
368
369 for (idx = 0; idx < rss->rss_size; idx++)
370 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx,
92dc8769 371 nic->rx_queues);
4863dea3
SG
372 nicvf_config_rss(nic);
373 return 1;
374}
375
92dc8769
SG
376/* Request PF to allocate additional Qsets */
377static void nicvf_request_sqs(struct nicvf *nic)
378{
379 union nic_mbx mbx = {};
380 int sqs;
381 int sqs_count = nic->sqs_count;
382 int rx_queues = 0, tx_queues = 0;
383
384 /* Only primary VF should request */
385 if (nic->sqs_mode || !nic->sqs_count)
386 return;
387
388 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
389 mbx.sqs_alloc.vf_id = nic->vf_id;
390 mbx.sqs_alloc.qs_count = nic->sqs_count;
391 if (nicvf_send_msg_to_pf(nic, &mbx)) {
392 /* No response from PF */
393 nic->sqs_count = 0;
394 return;
395 }
396
397 /* Return if no Secondary Qsets available */
398 if (!nic->sqs_count)
399 return;
400
401 if (nic->rx_queues > MAX_RCV_QUEUES_PER_QS)
402 rx_queues = nic->rx_queues - MAX_RCV_QUEUES_PER_QS;
403 if (nic->tx_queues > MAX_SND_QUEUES_PER_QS)
404 tx_queues = nic->tx_queues - MAX_SND_QUEUES_PER_QS;
405
406 /* Set no of Rx/Tx queues in each of the SQsets */
407 for (sqs = 0; sqs < nic->sqs_count; sqs++) {
408 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
409 mbx.nicvf.vf_id = nic->vf_id;
410 mbx.nicvf.sqs_id = sqs;
411 nicvf_send_msg_to_pf(nic, &mbx);
412
413 nic->snicvf[sqs]->sqs_id = sqs;
414 if (rx_queues > MAX_RCV_QUEUES_PER_QS) {
415 nic->snicvf[sqs]->qs->rq_cnt = MAX_RCV_QUEUES_PER_QS;
416 rx_queues -= MAX_RCV_QUEUES_PER_QS;
417 } else {
418 nic->snicvf[sqs]->qs->rq_cnt = rx_queues;
419 rx_queues = 0;
420 }
421
422 if (tx_queues > MAX_SND_QUEUES_PER_QS) {
423 nic->snicvf[sqs]->qs->sq_cnt = MAX_SND_QUEUES_PER_QS;
424 tx_queues -= MAX_SND_QUEUES_PER_QS;
425 } else {
426 nic->snicvf[sqs]->qs->sq_cnt = tx_queues;
427 tx_queues = 0;
428 }
429
430 nic->snicvf[sqs]->qs->cq_cnt =
431 max(nic->snicvf[sqs]->qs->rq_cnt, nic->snicvf[sqs]->qs->sq_cnt);
432
433 /* Initialize secondary Qset's queues and its interrupts */
434 nicvf_open(nic->snicvf[sqs]->netdev);
435 }
436
437 /* Update stack with actual Rx/Tx queue count allocated */
438 if (sqs_count != nic->sqs_count)
439 nicvf_set_real_num_queues(nic->netdev,
440 nic->tx_queues, nic->rx_queues);
441}
442
443/* Send this Qset's nicvf pointer to PF.
444 * PF inturn sends primary VF's nicvf struct to secondary Qsets/VFs
445 * so that packets received by these Qsets can use primary VF's netdev
446 */
447static void nicvf_send_vf_struct(struct nicvf *nic)
448{
449 union nic_mbx mbx = {};
450
451 mbx.nicvf.msg = NIC_MBOX_MSG_NICVF_PTR;
452 mbx.nicvf.sqs_mode = nic->sqs_mode;
453 mbx.nicvf.nicvf = (u64)nic;
454 nicvf_send_msg_to_pf(nic, &mbx);
455}
456
457static void nicvf_get_primary_vf_struct(struct nicvf *nic)
458{
459 union nic_mbx mbx = {};
460
461 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
462 nicvf_send_msg_to_pf(nic, &mbx);
463}
464
4863dea3
SG
465int nicvf_set_real_num_queues(struct net_device *netdev,
466 int tx_queues, int rx_queues)
467{
468 int err = 0;
469
470 err = netif_set_real_num_tx_queues(netdev, tx_queues);
471 if (err) {
472 netdev_err(netdev,
473 "Failed to set no of Tx queues: %d\n", tx_queues);
474 return err;
475 }
476
477 err = netif_set_real_num_rx_queues(netdev, rx_queues);
478 if (err)
479 netdev_err(netdev,
480 "Failed to set no of Rx queues: %d\n", rx_queues);
481 return err;
482}
483
484static int nicvf_init_resources(struct nicvf *nic)
485{
486 int err;
2cd2a196
AM
487 union nic_mbx mbx = {};
488
489 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
4863dea3
SG
490
491 /* Enable Qset */
492 nicvf_qset_config(nic, true);
493
494 /* Initialize queues and HW for data transfer */
495 err = nicvf_config_data_transfer(nic, true);
496 if (err) {
497 netdev_err(nic->netdev,
498 "Failed to alloc/config VF's QSet resources\n");
499 return err;
500 }
501
502 /* Send VF config done msg to PF */
2cd2a196 503 nicvf_write_to_mbx(nic, &mbx);
4863dea3
SG
504
505 return 0;
506}
507
508static void nicvf_snd_pkt_handler(struct net_device *netdev,
509 struct cmp_queue *cq,
510 struct cqe_send_t *cqe_tx, int cqe_type)
511{
512 struct sk_buff *skb = NULL;
513 struct nicvf *nic = netdev_priv(netdev);
514 struct snd_queue *sq;
515 struct sq_hdr_subdesc *hdr;
516
517 sq = &nic->qs->sq[cqe_tx->sq_idx];
518
519 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr);
520 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER)
521 return;
522
523 netdev_dbg(nic->netdev,
524 "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n",
525 __func__, cqe_tx->sq_qs, cqe_tx->sq_idx,
526 cqe_tx->sqe_ptr, hdr->subdesc_cnt);
527
4863dea3
SG
528 nicvf_check_cqe_tx_errs(nic, cq, cqe_tx);
529 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];
40fb5f8a 530 /* For TSO offloaded packets only one SQE will have a valid SKB */
4863dea3 531 if (skb) {
40fb5f8a 532 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
4863dea3
SG
533 prefetch(skb);
534 dev_consume_skb_any(skb);
143ceb0b 535 sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL;
40fb5f8a
SG
536 } else {
537 /* In case of HW TSO, HW sends a CQE for each segment of a TSO
538 * packet instead of a single CQE for the whole TSO packet
539 * transmitted. Each of this CQE points to the same SQE, so
540 * avoid freeing same SQE multiple times.
541 */
542 if (!nic->hw_tso)
543 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
4863dea3
SG
544 }
545}
546
38bb5d4f
SG
547static inline void nicvf_set_rxhash(struct net_device *netdev,
548 struct cqe_rx_t *cqe_rx,
549 struct sk_buff *skb)
550{
551 u8 hash_type;
552 u32 hash;
553
554 if (!(netdev->features & NETIF_F_RXHASH))
555 return;
556
557 switch (cqe_rx->rss_alg) {
558 case RSS_ALG_TCP_IP:
559 case RSS_ALG_UDP_IP:
560 hash_type = PKT_HASH_TYPE_L4;
561 hash = cqe_rx->rss_tag;
562 break;
563 case RSS_ALG_IP:
564 hash_type = PKT_HASH_TYPE_L3;
565 hash = cqe_rx->rss_tag;
566 break;
567 default:
568 hash_type = PKT_HASH_TYPE_NONE;
569 hash = 0;
570 }
571
572 skb_set_hash(skb, hash, hash_type);
573}
574
4863dea3
SG
575static void nicvf_rcv_pkt_handler(struct net_device *netdev,
576 struct napi_struct *napi,
ad2ecebd 577 struct cqe_rx_t *cqe_rx)
4863dea3
SG
578{
579 struct sk_buff *skb;
580 struct nicvf *nic = netdev_priv(netdev);
581 int err = 0;
92dc8769
SG
582 int rq_idx;
583
584 rq_idx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx);
585
586 if (nic->sqs_mode) {
587 /* Use primary VF's 'nicvf' struct */
588 nic = nic->pnicvf;
589 netdev = nic->netdev;
590 }
4863dea3
SG
591
592 /* Check for errors */
ad2ecebd 593 err = nicvf_check_cqe_rx_errs(nic, cqe_rx);
4863dea3
SG
594 if (err && !cqe_rx->rb_cnt)
595 return;
596
597 skb = nicvf_get_rcv_skb(nic, cqe_rx);
598 if (!skb) {
599 netdev_dbg(nic->netdev, "Packet not received\n");
600 return;
601 }
602
603 if (netif_msg_pktdata(nic)) {
604 netdev_info(nic->netdev, "%s: skb 0x%p, len=%d\n", netdev->name,
605 skb, skb->len);
606 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
607 skb->data, skb->len, true);
608 }
609
a2dc5ded
SG
610 /* If error packet, drop it here */
611 if (err) {
612 dev_kfree_skb_any(skb);
613 return;
614 }
615
4863dea3
SG
616 nicvf_set_rx_frame_cnt(nic, skb);
617
38bb5d4f
SG
618 nicvf_set_rxhash(netdev, cqe_rx, skb);
619
92dc8769 620 skb_record_rx_queue(skb, rq_idx);
4863dea3
SG
621 if (netdev->hw_features & NETIF_F_RXCSUM) {
622 /* HW by default verifies TCP/UDP/SCTP checksums */
623 skb->ip_summed = CHECKSUM_UNNECESSARY;
624 } else {
625 skb_checksum_none_assert(skb);
626 }
627
628 skb->protocol = eth_type_trans(skb, netdev);
629
aa2e259b
SG
630 /* Check for stripped VLAN */
631 if (cqe_rx->vlan_found && cqe_rx->vlan_stripped)
632 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
633 ntohs((__force __be16)cqe_rx->vlan_tci));
634
4863dea3
SG
635 if (napi && (netdev->features & NETIF_F_GRO))
636 napi_gro_receive(napi, skb);
637 else
638 netif_receive_skb(skb);
639}
640
641static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
642 struct napi_struct *napi, int budget)
643{
74840b83 644 int processed_cqe, work_done = 0, tx_done = 0;
4863dea3
SG
645 int cqe_count, cqe_head;
646 struct nicvf *nic = netdev_priv(netdev);
647 struct queue_set *qs = nic->qs;
648 struct cmp_queue *cq = &qs->cq[cq_idx];
649 struct cqe_rx_t *cq_desc;
74840b83 650 struct netdev_queue *txq;
4863dea3
SG
651
652 spin_lock_bh(&cq->lock);
653loop:
654 processed_cqe = 0;
655 /* Get no of valid CQ entries to process */
656 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx);
657 cqe_count &= CQ_CQE_COUNT;
658 if (!cqe_count)
659 goto done;
660
661 /* Get head of the valid CQ entries */
662 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9;
663 cqe_head &= 0xFFFF;
664
74840b83
SG
665 netdev_dbg(nic->netdev, "%s CQ%d cqe_count %d cqe_head %d\n",
666 __func__, cq_idx, cqe_count, cqe_head);
4863dea3
SG
667 while (processed_cqe < cqe_count) {
668 /* Get the CQ descriptor */
669 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
670 cqe_head++;
671 cqe_head &= (cq->dmem.q_len - 1);
672 /* Initiate prefetch for next descriptor */
673 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head));
674
675 if ((work_done >= budget) && napi &&
676 (cq_desc->cqe_type != CQE_TYPE_SEND)) {
677 break;
678 }
679
74840b83
SG
680 netdev_dbg(nic->netdev, "CQ%d cq_desc->cqe_type %d\n",
681 cq_idx, cq_desc->cqe_type);
4863dea3
SG
682 switch (cq_desc->cqe_type) {
683 case CQE_TYPE_RX:
ad2ecebd 684 nicvf_rcv_pkt_handler(netdev, napi, cq_desc);
4863dea3
SG
685 work_done++;
686 break;
687 case CQE_TYPE_SEND:
688 nicvf_snd_pkt_handler(netdev, cq,
689 (void *)cq_desc, CQE_TYPE_SEND);
74840b83 690 tx_done++;
4863dea3
SG
691 break;
692 case CQE_TYPE_INVALID:
693 case CQE_TYPE_RX_SPLIT:
694 case CQE_TYPE_RX_TCP:
695 case CQE_TYPE_SEND_PTP:
696 /* Ignore for now */
697 break;
698 }
699 processed_cqe++;
700 }
74840b83
SG
701 netdev_dbg(nic->netdev,
702 "%s CQ%d processed_cqe %d work_done %d budget %d\n",
703 __func__, cq_idx, processed_cqe, work_done, budget);
4863dea3
SG
704
705 /* Ring doorbell to inform H/W to reuse processed CQEs */
706 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
707 cq_idx, processed_cqe);
708
709 if ((work_done < budget) && napi)
710 goto loop;
711
712done:
74840b83
SG
713 /* Wakeup TXQ if its stopped earlier due to SQ full */
714 if (tx_done) {
92dc8769
SG
715 netdev = nic->pnicvf->netdev;
716 txq = netdev_get_tx_queue(netdev,
717 nicvf_netdev_qidx(nic, cq_idx));
718 nic = nic->pnicvf;
719 if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) {
b49087dd 720 netif_tx_start_queue(txq);
74840b83
SG
721 nic->drv_stats.txq_wake++;
722 if (netif_msg_tx_err(nic))
723 netdev_warn(netdev,
724 "%s: Transmit queue wakeup SQ%d\n",
725 netdev->name, cq_idx);
726 }
727 }
728
4863dea3
SG
729 spin_unlock_bh(&cq->lock);
730 return work_done;
731}
732
733static int nicvf_poll(struct napi_struct *napi, int budget)
734{
735 u64 cq_head;
736 int work_done = 0;
737 struct net_device *netdev = napi->dev;
738 struct nicvf *nic = netdev_priv(netdev);
739 struct nicvf_cq_poll *cq;
4863dea3
SG
740
741 cq = container_of(napi, struct nicvf_cq_poll, napi);
742 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget);
743
4863dea3
SG
744 if (work_done < budget) {
745 /* Slow packet rate, exit polling */
746 napi_complete(napi);
747 /* Re-enable interrupts */
748 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD,
749 cq->cq_idx);
750 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
751 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD,
752 cq->cq_idx, cq_head);
753 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
754 }
755 return work_done;
756}
757
758/* Qset error interrupt handler
759 *
760 * As of now only CQ errors are handled
761 */
fd7ec062 762static void nicvf_handle_qs_err(unsigned long data)
4863dea3
SG
763{
764 struct nicvf *nic = (struct nicvf *)data;
765 struct queue_set *qs = nic->qs;
766 int qidx;
767 u64 status;
768
769 netif_tx_disable(nic->netdev);
770
771 /* Check if it is CQ err */
772 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
773 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS,
774 qidx);
775 if (!(status & CQ_ERR_MASK))
776 continue;
777 /* Process already queued CQEs and reconfig CQ */
778 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
779 nicvf_sq_disable(nic, qidx);
780 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0);
781 nicvf_cmp_queue_config(nic, qs, qidx, true);
782 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx);
783 nicvf_sq_enable(nic, &qs->sq[qidx], qidx);
784
785 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
786 }
787
788 netif_tx_start_all_queues(nic->netdev);
789 /* Re-enable Qset error interrupt */
790 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
791}
792
39ad6eea
SG
793static void nicvf_dump_intr_status(struct nicvf *nic)
794{
795 if (netif_msg_intr(nic))
796 netdev_info(nic->netdev, "%s: interrupt status 0x%llx\n",
797 nic->netdev->name, nicvf_reg_read(nic, NIC_VF_INT));
798}
799
4863dea3
SG
800static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq)
801{
802 struct nicvf *nic = (struct nicvf *)nicvf_irq;
803 u64 intr;
804
39ad6eea
SG
805 nicvf_dump_intr_status(nic);
806
4863dea3
SG
807 intr = nicvf_reg_read(nic, NIC_VF_INT);
808 /* Check for spurious interrupt */
809 if (!(intr & NICVF_INTR_MBOX_MASK))
810 return IRQ_HANDLED;
811
812 nicvf_handle_mbx_intr(nic);
813
814 return IRQ_HANDLED;
815}
816
39ad6eea
SG
817static irqreturn_t nicvf_intr_handler(int irq, void *cq_irq)
818{
819 struct nicvf_cq_poll *cq_poll = (struct nicvf_cq_poll *)cq_irq;
820 struct nicvf *nic = cq_poll->nicvf;
821 int qidx = cq_poll->cq_idx;
822
823 nicvf_dump_intr_status(nic);
824
825 /* Disable interrupts */
826 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
827
828 /* Schedule NAPI */
829 napi_schedule(&cq_poll->napi);
830
831 /* Clear interrupt */
832 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
833
834 return IRQ_HANDLED;
835}
836
837static irqreturn_t nicvf_rbdr_intr_handler(int irq, void *nicvf_irq)
4863dea3 838{
4863dea3 839 struct nicvf *nic = (struct nicvf *)nicvf_irq;
39ad6eea 840 u8 qidx;
4863dea3 841
4863dea3 842
39ad6eea
SG
843 nicvf_dump_intr_status(nic);
844
845 /* Disable RBDR interrupt and schedule softirq */
846 for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) {
847 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx))
4863dea3 848 continue;
39ad6eea
SG
849 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
850 tasklet_hi_schedule(&nic->rbdr_task);
851 /* Clear interrupt */
852 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
853 }
4863dea3 854
39ad6eea
SG
855 return IRQ_HANDLED;
856}
4863dea3 857
39ad6eea
SG
858static irqreturn_t nicvf_qs_err_intr_handler(int irq, void *nicvf_irq)
859{
860 struct nicvf *nic = (struct nicvf *)nicvf_irq;
4863dea3 861
39ad6eea
SG
862 nicvf_dump_intr_status(nic);
863
864 /* Disable Qset err interrupt and schedule softirq */
865 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
866 tasklet_hi_schedule(&nic->qs_err_task);
867 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
4863dea3 868
4863dea3
SG
869 return IRQ_HANDLED;
870}
871
872static int nicvf_enable_msix(struct nicvf *nic)
873{
874 int ret, vec;
875
876 nic->num_vec = NIC_VF_MSIX_VECTORS;
877
878 for (vec = 0; vec < nic->num_vec; vec++)
879 nic->msix_entries[vec].entry = vec;
880
881 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
882 if (ret) {
883 netdev_err(nic->netdev,
884 "Req for #%d msix vectors failed\n", nic->num_vec);
885 return 0;
886 }
887 nic->msix_enabled = 1;
888 return 1;
889}
890
891static void nicvf_disable_msix(struct nicvf *nic)
892{
893 if (nic->msix_enabled) {
894 pci_disable_msix(nic->pdev);
895 nic->msix_enabled = 0;
896 nic->num_vec = 0;
897 }
898}
899
900static int nicvf_register_interrupts(struct nicvf *nic)
901{
39ad6eea 902 int irq, ret = 0;
4863dea3
SG
903 int vector;
904
905 for_each_cq_irq(irq)
906 sprintf(nic->irq_name[irq], "NICVF%d CQ%d",
907 nic->vf_id, irq);
908
909 for_each_sq_irq(irq)
910 sprintf(nic->irq_name[irq], "NICVF%d SQ%d",
911 nic->vf_id, irq - NICVF_INTR_ID_SQ);
912
913 for_each_rbdr_irq(irq)
914 sprintf(nic->irq_name[irq], "NICVF%d RBDR%d",
915 nic->vf_id, irq - NICVF_INTR_ID_RBDR);
916
39ad6eea
SG
917 /* Register CQ interrupts */
918 for (irq = 0; irq < nic->qs->cq_cnt; irq++) {
4863dea3
SG
919 vector = nic->msix_entries[irq].vector;
920 ret = request_irq(vector, nicvf_intr_handler,
39ad6eea 921 0, nic->irq_name[irq], nic->napi[irq]);
4863dea3 922 if (ret)
39ad6eea 923 goto err;
4863dea3
SG
924 nic->irq_allocated[irq] = true;
925 }
926
39ad6eea
SG
927 /* Register RBDR interrupt */
928 for (irq = NICVF_INTR_ID_RBDR;
929 irq < (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt); irq++) {
4863dea3 930 vector = nic->msix_entries[irq].vector;
39ad6eea 931 ret = request_irq(vector, nicvf_rbdr_intr_handler,
4863dea3
SG
932 0, nic->irq_name[irq], nic);
933 if (ret)
39ad6eea 934 goto err;
4863dea3
SG
935 nic->irq_allocated[irq] = true;
936 }
937
39ad6eea 938 /* Register QS error interrupt */
4863dea3
SG
939 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR],
940 "NICVF%d Qset error", nic->vf_id);
39ad6eea
SG
941 irq = NICVF_INTR_ID_QS_ERR;
942 ret = request_irq(nic->msix_entries[irq].vector,
943 nicvf_qs_err_intr_handler,
944 0, nic->irq_name[irq], nic);
945 if (!ret)
946 nic->irq_allocated[irq] = true;
4863dea3 947
39ad6eea
SG
948err:
949 if (ret)
950 netdev_err(nic->netdev, "request_irq failed, vector %d\n", irq);
4863dea3 951
39ad6eea 952 return ret;
4863dea3
SG
953}
954
955static void nicvf_unregister_interrupts(struct nicvf *nic)
956{
957 int irq;
958
959 /* Free registered interrupts */
960 for (irq = 0; irq < nic->num_vec; irq++) {
39ad6eea
SG
961 if (!nic->irq_allocated[irq])
962 continue;
963
964 if (irq < NICVF_INTR_ID_SQ)
965 free_irq(nic->msix_entries[irq].vector, nic->napi[irq]);
966 else
4863dea3 967 free_irq(nic->msix_entries[irq].vector, nic);
39ad6eea 968
4863dea3
SG
969 nic->irq_allocated[irq] = false;
970 }
971
972 /* Disable MSI-X */
973 nicvf_disable_msix(nic);
974}
975
976/* Initialize MSIX vectors and register MISC interrupt.
977 * Send READY message to PF to check if its alive
978 */
979static int nicvf_register_misc_interrupt(struct nicvf *nic)
980{
981 int ret = 0;
982 int irq = NICVF_INTR_ID_MISC;
983
984 /* Return if mailbox interrupt is already registered */
985 if (nic->msix_enabled)
986 return 0;
987
988 /* Enable MSI-X */
989 if (!nicvf_enable_msix(nic))
990 return 1;
991
992 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF");
993 /* Register Misc interrupt */
994 ret = request_irq(nic->msix_entries[irq].vector,
995 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic);
996
997 if (ret)
998 return ret;
999 nic->irq_allocated[irq] = true;
1000
1001 /* Enable mailbox interrupt */
1002 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0);
1003
1004 /* Check if VF is able to communicate with PF */
1005 if (!nicvf_check_pf_ready(nic)) {
1006 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
1007 nicvf_unregister_interrupts(nic);
1008 return 1;
1009 }
1010
1011 return 0;
1012}
1013
1014static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
1015{
1016 struct nicvf *nic = netdev_priv(netdev);
1017 int qid = skb_get_queue_mapping(skb);
1018 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid);
1019
1020 /* Check for minimum packet length */
1021 if (skb->len <= ETH_HLEN) {
1022 dev_kfree_skb(skb);
1023 return NETDEV_TX_OK;
1024 }
1025
b49087dd 1026 if (!netif_tx_queue_stopped(txq) && !nicvf_sq_append_skb(nic, skb)) {
4863dea3 1027 netif_tx_stop_queue(txq);
74840b83 1028 nic->drv_stats.txq_stop++;
4863dea3
SG
1029 if (netif_msg_tx_err(nic))
1030 netdev_warn(netdev,
1031 "%s: Transmit ring full, stopping SQ%d\n",
1032 netdev->name, qid);
4863dea3
SG
1033 return NETDEV_TX_BUSY;
1034 }
1035
1036 return NETDEV_TX_OK;
1037}
1038
39ad6eea
SG
1039static inline void nicvf_free_cq_poll(struct nicvf *nic)
1040{
1041 struct nicvf_cq_poll *cq_poll;
1042 int qidx;
1043
1044 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
1045 cq_poll = nic->napi[qidx];
1046 if (!cq_poll)
1047 continue;
1048 nic->napi[qidx] = NULL;
1049 kfree(cq_poll);
1050 }
1051}
1052
4863dea3
SG
1053int nicvf_stop(struct net_device *netdev)
1054{
1055 int irq, qidx;
1056 struct nicvf *nic = netdev_priv(netdev);
1057 struct queue_set *qs = nic->qs;
1058 struct nicvf_cq_poll *cq_poll = NULL;
1059 union nic_mbx mbx = {};
1060
1061 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN;
1062 nicvf_send_msg_to_pf(nic, &mbx);
1063
1064 netif_carrier_off(netdev);
92dc8769 1065 netif_tx_stop_all_queues(nic->netdev);
0b72a9a1 1066 nic->link_up = false;
92dc8769
SG
1067
1068 /* Teardown secondary qsets first */
1069 if (!nic->sqs_mode) {
1070 for (qidx = 0; qidx < nic->sqs_count; qidx++) {
1071 if (!nic->snicvf[qidx])
1072 continue;
1073 nicvf_stop(nic->snicvf[qidx]->netdev);
1074 nic->snicvf[qidx] = NULL;
1075 }
1076 }
4863dea3
SG
1077
1078 /* Disable RBDR & QS error interrupts */
1079 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
1080 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
1081 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
1082 }
1083 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
1084 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
1085
1086 /* Wait for pending IRQ handlers to finish */
1087 for (irq = 0; irq < nic->num_vec; irq++)
1088 synchronize_irq(nic->msix_entries[irq].vector);
1089
1090 tasklet_kill(&nic->rbdr_task);
1091 tasklet_kill(&nic->qs_err_task);
1092 if (nic->rb_work_scheduled)
1093 cancel_delayed_work_sync(&nic->rbdr_work);
1094
1095 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
1096 cq_poll = nic->napi[qidx];
1097 if (!cq_poll)
1098 continue;
4863dea3
SG
1099 napi_synchronize(&cq_poll->napi);
1100 /* CQ intr is enabled while napi_complete,
1101 * so disable it now
1102 */
1103 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
1104 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
1105 napi_disable(&cq_poll->napi);
1106 netif_napi_del(&cq_poll->napi);
4863dea3
SG
1107 }
1108
b49087dd
SG
1109 netif_tx_disable(netdev);
1110
4863dea3
SG
1111 /* Free resources */
1112 nicvf_config_data_transfer(nic, false);
1113
1114 /* Disable HW Qset */
1115 nicvf_qset_config(nic, false);
1116
1117 /* disable mailbox interrupt */
1118 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
1119
1120 nicvf_unregister_interrupts(nic);
1121
39ad6eea
SG
1122 nicvf_free_cq_poll(nic);
1123
92dc8769
SG
1124 /* Clear multiqset info */
1125 nic->pnicvf = nic;
92dc8769 1126
4863dea3
SG
1127 return 0;
1128}
1129
1130int nicvf_open(struct net_device *netdev)
1131{
1132 int err, qidx;
1133 struct nicvf *nic = netdev_priv(netdev);
1134 struct queue_set *qs = nic->qs;
1135 struct nicvf_cq_poll *cq_poll = NULL;
1136
1137 nic->mtu = netdev->mtu;
1138
1139 netif_carrier_off(netdev);
1140
1141 err = nicvf_register_misc_interrupt(nic);
1142 if (err)
1143 return err;
1144
1145 /* Register NAPI handler for processing CQEs */
1146 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
1147 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL);
1148 if (!cq_poll) {
1149 err = -ENOMEM;
1150 goto napi_del;
1151 }
1152 cq_poll->cq_idx = qidx;
39ad6eea 1153 cq_poll->nicvf = nic;
4863dea3
SG
1154 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll,
1155 NAPI_POLL_WEIGHT);
1156 napi_enable(&cq_poll->napi);
1157 nic->napi[qidx] = cq_poll;
1158 }
1159
1160 /* Check if we got MAC address from PF or else generate a radom MAC */
1161 if (is_zero_ether_addr(netdev->dev_addr)) {
1162 eth_hw_addr_random(netdev);
1163 nicvf_hw_set_mac_addr(nic, netdev);
1164 }
1165
bd049a90
PF
1166 if (nic->set_mac_pending) {
1167 nic->set_mac_pending = false;
1168 nicvf_hw_set_mac_addr(nic, netdev);
1169 }
1170
4863dea3
SG
1171 /* Init tasklet for handling Qset err interrupt */
1172 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err,
1173 (unsigned long)nic);
1174
1175 /* Init RBDR tasklet which will refill RBDR */
1176 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task,
1177 (unsigned long)nic);
1178 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work);
1179
1180 /* Configure CPI alorithm */
1181 nic->cpi_alg = cpi_alg;
92dc8769
SG
1182 if (!nic->sqs_mode)
1183 nicvf_config_cpi(nic);
1184
1185 nicvf_request_sqs(nic);
1186 if (nic->sqs_mode)
1187 nicvf_get_primary_vf_struct(nic);
4863dea3
SG
1188
1189 /* Configure receive side scaling */
92dc8769
SG
1190 if (!nic->sqs_mode)
1191 nicvf_rss_init(nic);
4863dea3
SG
1192
1193 err = nicvf_register_interrupts(nic);
1194 if (err)
1195 goto cleanup;
1196
1197 /* Initialize the queues */
1198 err = nicvf_init_resources(nic);
1199 if (err)
1200 goto cleanup;
1201
1202 /* Make sure queue initialization is written */
1203 wmb();
1204
1205 nicvf_reg_write(nic, NIC_VF_INT, -1);
1206 /* Enable Qset err interrupt */
1207 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
1208
1209 /* Enable completion queue interrupt */
1210 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
1211 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
1212
1213 /* Enable RBDR threshold interrupt */
1214 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
1215 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
1216
74840b83
SG
1217 nic->drv_stats.txq_stop = 0;
1218 nic->drv_stats.txq_wake = 0;
1219
4863dea3
SG
1220 return 0;
1221cleanup:
1222 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
1223 nicvf_unregister_interrupts(nic);
39ad6eea
SG
1224 tasklet_kill(&nic->qs_err_task);
1225 tasklet_kill(&nic->rbdr_task);
4863dea3
SG
1226napi_del:
1227 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
1228 cq_poll = nic->napi[qidx];
1229 if (!cq_poll)
1230 continue;
1231 napi_disable(&cq_poll->napi);
1232 netif_napi_del(&cq_poll->napi);
4863dea3 1233 }
39ad6eea 1234 nicvf_free_cq_poll(nic);
4863dea3
SG
1235 return err;
1236}
1237
1238static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
1239{
1240 union nic_mbx mbx = {};
1241
1242 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
1243 mbx.frs.max_frs = mtu;
1244 mbx.frs.vf_id = nic->vf_id;
1245
1246 return nicvf_send_msg_to_pf(nic, &mbx);
1247}
1248
1249static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)
1250{
1251 struct nicvf *nic = netdev_priv(netdev);
1252
1253 if (new_mtu > NIC_HW_MAX_FRS)
1254 return -EINVAL;
1255
1256 if (new_mtu < NIC_HW_MIN_FRS)
1257 return -EINVAL;
1258
1259 if (nicvf_update_hw_max_frs(nic, new_mtu))
1260 return -EINVAL;
1261 netdev->mtu = new_mtu;
1262 nic->mtu = new_mtu;
1263
1264 return 0;
1265}
1266
1267static int nicvf_set_mac_address(struct net_device *netdev, void *p)
1268{
1269 struct sockaddr *addr = p;
1270 struct nicvf *nic = netdev_priv(netdev);
1271
1272 if (!is_valid_ether_addr(addr->sa_data))
1273 return -EADDRNOTAVAIL;
1274
1275 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1276
bd049a90 1277 if (nic->msix_enabled) {
4863dea3
SG
1278 if (nicvf_hw_set_mac_addr(nic, netdev))
1279 return -EBUSY;
bd049a90
PF
1280 } else {
1281 nic->set_mac_pending = true;
1282 }
4863dea3
SG
1283
1284 return 0;
1285}
1286
4863dea3
SG
1287void nicvf_update_lmac_stats(struct nicvf *nic)
1288{
1289 int stat = 0;
1290 union nic_mbx mbx = {};
4863dea3
SG
1291
1292 if (!netif_running(nic->netdev))
1293 return;
1294
1295 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
1296 mbx.bgx_stats.vf_id = nic->vf_id;
1297 /* Rx stats */
1298 mbx.bgx_stats.rx = 1;
1299 while (stat < BGX_RX_STATS_COUNT) {
4863dea3 1300 mbx.bgx_stats.idx = stat;
6051cba7
SG
1301 if (nicvf_send_msg_to_pf(nic, &mbx))
1302 return;
4863dea3
SG
1303 stat++;
1304 }
1305
1306 stat = 0;
1307
1308 /* Tx stats */
1309 mbx.bgx_stats.rx = 0;
1310 while (stat < BGX_TX_STATS_COUNT) {
4863dea3 1311 mbx.bgx_stats.idx = stat;
6051cba7
SG
1312 if (nicvf_send_msg_to_pf(nic, &mbx))
1313 return;
4863dea3
SG
1314 stat++;
1315 }
1316}
1317
1318void nicvf_update_stats(struct nicvf *nic)
1319{
1320 int qidx;
a2dc5ded 1321 struct nicvf_hw_stats *stats = &nic->hw_stats;
4863dea3
SG
1322 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1323 struct queue_set *qs = nic->qs;
1324
1325#define GET_RX_STATS(reg) \
1326 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
1327#define GET_TX_STATS(reg) \
1328 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
1329
a2dc5ded
SG
1330 stats->rx_bytes = GET_RX_STATS(RX_OCTS);
1331 stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST);
1332 stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST);
1333 stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST);
4863dea3
SG
1334 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS);
1335 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR);
1336 stats->rx_drop_red = GET_RX_STATS(RX_RED);
a2dc5ded 1337 stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS);
4863dea3 1338 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN);
a2dc5ded 1339 stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS);
4863dea3
SG
1340 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST);
1341 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST);
1342 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);
1343 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);
1344
1345 stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS);
1346 stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST);
1347 stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST);
1348 stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST);
1349 stats->tx_drops = GET_TX_STATS(TX_DROP);
1350
4863dea3
SG
1351 drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok +
1352 stats->tx_bcast_frames_ok +
1353 stats->tx_mcast_frames_ok;
ad2ecebd
SG
1354 drv_stats->rx_frames_ok = stats->rx_ucast_frames +
1355 stats->rx_bcast_frames +
1356 stats->rx_mcast_frames;
4863dea3
SG
1357 drv_stats->rx_drops = stats->rx_drop_red +
1358 stats->rx_drop_overrun;
1359 drv_stats->tx_drops = stats->tx_drops;
1360
1361 /* Update RQ and SQ stats */
1362 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
1363 nicvf_update_rq_stats(nic, qidx);
1364 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
1365 nicvf_update_sq_stats(nic, qidx);
1366}
1367
fd7ec062 1368static struct rtnl_link_stats64 *nicvf_get_stats64(struct net_device *netdev,
4863dea3
SG
1369 struct rtnl_link_stats64 *stats)
1370{
1371 struct nicvf *nic = netdev_priv(netdev);
a2dc5ded 1372 struct nicvf_hw_stats *hw_stats = &nic->hw_stats;
4863dea3
SG
1373 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1374
1375 nicvf_update_stats(nic);
1376
a2dc5ded 1377 stats->rx_bytes = hw_stats->rx_bytes;
4863dea3
SG
1378 stats->rx_packets = drv_stats->rx_frames_ok;
1379 stats->rx_dropped = drv_stats->rx_drops;
a2dc5ded 1380 stats->multicast = hw_stats->rx_mcast_frames;
4863dea3
SG
1381
1382 stats->tx_bytes = hw_stats->tx_bytes_ok;
1383 stats->tx_packets = drv_stats->tx_frames_ok;
1384 stats->tx_dropped = drv_stats->tx_drops;
1385
1386 return stats;
1387}
1388
1389static void nicvf_tx_timeout(struct net_device *dev)
1390{
1391 struct nicvf *nic = netdev_priv(dev);
1392
1393 if (netif_msg_tx_err(nic))
1394 netdev_warn(dev, "%s: Transmit timed out, resetting\n",
1395 dev->name);
1396
1397 schedule_work(&nic->reset_task);
1398}
1399
1400static void nicvf_reset_task(struct work_struct *work)
1401{
1402 struct nicvf *nic;
1403
1404 nic = container_of(work, struct nicvf, reset_task);
1405
1406 if (!netif_running(nic->netdev))
1407 return;
1408
1409 nicvf_stop(nic->netdev);
1410 nicvf_open(nic->netdev);
1411 nic->netdev->trans_start = jiffies;
1412}
1413
d77a2384
SG
1414static int nicvf_config_loopback(struct nicvf *nic,
1415 netdev_features_t features)
1416{
1417 union nic_mbx mbx = {};
1418
1419 mbx.lbk.msg = NIC_MBOX_MSG_LOOPBACK;
1420 mbx.lbk.vf_id = nic->vf_id;
1421 mbx.lbk.enable = (features & NETIF_F_LOOPBACK) != 0;
1422
1423 return nicvf_send_msg_to_pf(nic, &mbx);
1424}
1425
1426static netdev_features_t nicvf_fix_features(struct net_device *netdev,
1427 netdev_features_t features)
1428{
1429 struct nicvf *nic = netdev_priv(netdev);
1430
1431 if ((features & NETIF_F_LOOPBACK) &&
1432 netif_running(netdev) && !nic->loopback_supported)
1433 features &= ~NETIF_F_LOOPBACK;
1434
1435 return features;
1436}
1437
aa2e259b
SG
1438static int nicvf_set_features(struct net_device *netdev,
1439 netdev_features_t features)
1440{
1441 struct nicvf *nic = netdev_priv(netdev);
1442 netdev_features_t changed = features ^ netdev->features;
1443
1444 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1445 nicvf_config_vlan_stripping(nic, features);
1446
d77a2384
SG
1447 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
1448 return nicvf_config_loopback(nic, features);
1449
aa2e259b
SG
1450 return 0;
1451}
1452
4863dea3
SG
1453static const struct net_device_ops nicvf_netdev_ops = {
1454 .ndo_open = nicvf_open,
1455 .ndo_stop = nicvf_stop,
1456 .ndo_start_xmit = nicvf_xmit,
1457 .ndo_change_mtu = nicvf_change_mtu,
1458 .ndo_set_mac_address = nicvf_set_mac_address,
1459 .ndo_get_stats64 = nicvf_get_stats64,
1460 .ndo_tx_timeout = nicvf_tx_timeout,
d77a2384 1461 .ndo_fix_features = nicvf_fix_features,
aa2e259b 1462 .ndo_set_features = nicvf_set_features,
4863dea3
SG
1463};
1464
1465static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1466{
1467 struct device *dev = &pdev->dev;
1468 struct net_device *netdev;
1469 struct nicvf *nic;
92dc8769 1470 int err, qcount;
4863dea3
SG
1471
1472 err = pci_enable_device(pdev);
1473 if (err) {
1474 dev_err(dev, "Failed to enable PCI device\n");
1475 return err;
1476 }
1477
1478 err = pci_request_regions(pdev, DRV_NAME);
1479 if (err) {
1480 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1481 goto err_disable_device;
1482 }
1483
1484 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1485 if (err) {
1486 dev_err(dev, "Unable to get usable DMA configuration\n");
1487 goto err_release_regions;
1488 }
1489
1490 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1491 if (err) {
1492 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n");
1493 goto err_release_regions;
1494 }
1495
92dc8769
SG
1496 qcount = MAX_CMP_QUEUES_PER_QS;
1497
1498 /* Restrict multiqset support only for host bound VFs */
1499 if (pdev->is_virtfn) {
1500 /* Set max number of queues per VF */
1501 qcount = roundup(num_online_cpus(), MAX_CMP_QUEUES_PER_QS);
1502 qcount = min(qcount,
1503 (MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS);
1504 }
1505
1506 netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount);
4863dea3
SG
1507 if (!netdev) {
1508 err = -ENOMEM;
1509 goto err_release_regions;
1510 }
1511
1512 pci_set_drvdata(pdev, netdev);
1513
1514 SET_NETDEV_DEV(netdev, &pdev->dev);
1515
1516 nic = netdev_priv(netdev);
1517 nic->netdev = netdev;
1518 nic->pdev = pdev;
92dc8769
SG
1519 nic->pnicvf = nic;
1520 nic->max_queues = qcount;
4863dea3
SG
1521
1522 /* MAP VF's configuration registers */
1523 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1524 if (!nic->reg_base) {
1525 dev_err(dev, "Cannot map config register space, aborting\n");
1526 err = -ENOMEM;
1527 goto err_free_netdev;
1528 }
1529
1530 err = nicvf_set_qset_resources(nic);
1531 if (err)
1532 goto err_free_netdev;
1533
4863dea3
SG
1534 /* Check if PF is alive and get MAC address for this VF */
1535 err = nicvf_register_misc_interrupt(nic);
1536 if (err)
1537 goto err_free_netdev;
1538
92dc8769
SG
1539 nicvf_send_vf_struct(nic);
1540
8d210d54
SG
1541 if (!pass1_silicon(nic->pdev))
1542 nic->hw_tso = true;
1543
92dc8769
SG
1544 /* Check if this VF is in QS only mode */
1545 if (nic->sqs_mode)
1546 return 0;
1547
1548 err = nicvf_set_real_num_queues(netdev, nic->tx_queues, nic->rx_queues);
1549 if (err)
1550 goto err_unregister_interrupts;
1551
aa2e259b
SG
1552 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
1553 NETIF_F_TSO | NETIF_F_GRO |
92dc8769
SG
1554 NETIF_F_HW_VLAN_CTAG_RX);
1555
1556 netdev->hw_features |= NETIF_F_RXHASH;
aa2e259b
SG
1557
1558 netdev->features |= netdev->hw_features;
d77a2384 1559 netdev->hw_features |= NETIF_F_LOOPBACK;
38bb5d4f 1560
aa2e259b 1561 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
4863dea3
SG
1562
1563 netdev->netdev_ops = &nicvf_netdev_ops;
3d7a8aaa 1564 netdev->watchdog_timeo = NICVF_TX_TIMEOUT;
4863dea3
SG
1565
1566 INIT_WORK(&nic->reset_task, nicvf_reset_task);
1567
1568 err = register_netdev(netdev);
1569 if (err) {
1570 dev_err(dev, "Failed to register netdevice\n");
1571 goto err_unregister_interrupts;
1572 }
1573
1574 nic->msg_enable = debug;
1575
1576 nicvf_set_ethtool_ops(netdev);
1577
1578 return 0;
1579
1580err_unregister_interrupts:
1581 nicvf_unregister_interrupts(nic);
1582err_free_netdev:
1583 pci_set_drvdata(pdev, NULL);
1584 free_netdev(netdev);
1585err_release_regions:
1586 pci_release_regions(pdev);
1587err_disable_device:
1588 pci_disable_device(pdev);
1589 return err;
1590}
1591
1592static void nicvf_remove(struct pci_dev *pdev)
1593{
1594 struct net_device *netdev = pci_get_drvdata(pdev);
7750130d
PF
1595 struct nicvf *nic;
1596 struct net_device *pnetdev;
1597
1598 if (!netdev)
1599 return;
1600
1601 nic = netdev_priv(netdev);
1602 pnetdev = nic->pnicvf->netdev;
4863dea3 1603
92dc8769
SG
1604 /* Check if this Qset is assigned to different VF.
1605 * If yes, clean primary and all secondary Qsets.
1606 */
1607 if (pnetdev && (pnetdev->reg_state == NETREG_REGISTERED))
1608 unregister_netdev(pnetdev);
4863dea3
SG
1609 nicvf_unregister_interrupts(nic);
1610 pci_set_drvdata(pdev, NULL);
1611 free_netdev(netdev);
1612 pci_release_regions(pdev);
1613 pci_disable_device(pdev);
1614}
1615
4adf4351
SG
1616static void nicvf_shutdown(struct pci_dev *pdev)
1617{
1618 nicvf_remove(pdev);
1619}
1620
4863dea3
SG
1621static struct pci_driver nicvf_driver = {
1622 .name = DRV_NAME,
1623 .id_table = nicvf_id_table,
1624 .probe = nicvf_probe,
1625 .remove = nicvf_remove,
4adf4351 1626 .shutdown = nicvf_shutdown,
4863dea3
SG
1627};
1628
1629static int __init nicvf_init_module(void)
1630{
1631 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1632
1633 return pci_register_driver(&nicvf_driver);
1634}
1635
1636static void __exit nicvf_cleanup_module(void)
1637{
1638 pci_unregister_driver(&nicvf_driver);
1639}
1640
1641module_init(nicvf_init_module);
1642module_exit(nicvf_cleanup_module);