]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/ethernet/cavium/thunder/thunder_bgx.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: thunderx: Use netdev_rss_key_fill() helper
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
46b903a0 9#include <linux/acpi.h>
4863dea3
SG		 10#include <linux/module.h>
11#include <linux/interrupt.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/phy.h>
16#include <linux/of.h>
17#include <linux/of_mdio.h>
18#include <linux/of_net.h>
19
20#include "nic_reg.h"
21#include "nic.h"
22#include "thunder_bgx.h"
23
24#define DRV_NAME "thunder-BGX"
25#define DRV_VERSION "1.0"
26
27struct lmac {
28 struct bgx *bgx;
29 int dmac;
46b903a0 30 u8 mac[ETH_ALEN];
0bcb7d51
SG		 31 u8 lmac_type;
32 u8 lane_to_sds;
33 bool use_training;
4863dea3
SG		 34 bool link_up;
35 int lmacid; /* ID within BGX */
36 int lmacid_bd; /* ID on board */
37 struct net_device netdev;
38 struct phy_device *phydev;
39 unsigned int last_duplex;
40 unsigned int last_link;
41 unsigned int last_speed;
42 bool is_sgmii;
43 struct delayed_work dwork;
44 struct workqueue_struct *check_link;
0c886a1d 45};
4863dea3
SG		 46
47struct bgx {
48 u8 bgx_id;
4863dea3
SG		 49 struct lmac lmac[MAX_LMAC_PER_BGX];
50 int lmac_count;
6465859a 51 u8 max_lmac;
4863dea3
SG		 52 void __iomem *reg_base;
53 struct pci_dev *pdev;
09de3917 54 bool is_dlm;
6465859a 55 bool is_rgx;
0c886a1d 56};
4863dea3 57
fd7ec062 58static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
4863dea3
SG		 59static int lmac_count; /* Total no of LMACs in system */
60
61static int bgx_xaui_check_link(struct lmac *lmac);
62
63/* Supported devices */
64static const struct pci_device_id bgx_id_table[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
6465859a 66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
4863dea3
SG		 67 { 0, } /* end of table */
68};
69
70MODULE_AUTHOR("Cavium Inc");
71MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
72MODULE_LICENSE("GPL v2");
73MODULE_VERSION(DRV_VERSION);
74MODULE_DEVICE_TABLE(pci, bgx_id_table);
75
76/* The Cavium ThunderX network controller can *only* be found in SoCs
77 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
78 * registers on this platform are implicitly strongly ordered with respect
79 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
80 * with no memory barriers in this driver. The readq()/writeq() functions add
81 * explicit ordering operation which in this case are redundant, and only
82 * add overhead.
83 */
84
85/* Register read/write APIs */
86static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
87{
88 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
89
90 return readq_relaxed(addr);
91}
92
93static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
94{
95 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
96
97 writeq_relaxed(val, addr);
98}
99
100static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
101{
102 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
103
104 writeq_relaxed(val | readq_relaxed(addr), addr);
105}
106
107static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
108{
109 int timeout = 100;
110 u64 reg_val;
111
112 while (timeout) {
113 reg_val = bgx_reg_read(bgx, lmac, reg);
114 if (zero && !(reg_val & mask))
115 return 0;
116 if (!zero && (reg_val & mask))
117 return 0;
118 usleep_range(1000, 2000);
119 timeout--;
120 }
121 return 1;
122}
123
124/* Return number of BGX present in HW */
125unsigned bgx_get_map(int node)
126{
127 int i;
128 unsigned map = 0;
129
09de3917
SG		 130 for (i = 0; i < MAX_BGX_PER_NODE; i++) {
131 if (bgx_vnic[(node * MAX_BGX_PER_NODE) + i])
4863dea3
SG		 132 map |= (1 << i);
133 }
134
135 return map;
136}
137EXPORT_SYMBOL(bgx_get_map);
138
139/* Return number of LMAC configured for this BGX */
140int bgx_get_lmac_count(int node, int bgx_idx)
141{
142 struct bgx *bgx;
143
09de3917 144 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 145 if (bgx)
146 return bgx->lmac_count;
147
148 return 0;
149}
150EXPORT_SYMBOL(bgx_get_lmac_count);
151
152/* Returns the current link status of LMAC */
153void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
154{
155 struct bgx_link_status *link = (struct bgx_link_status *)status;
156 struct bgx *bgx;
157 struct lmac *lmac;
158
09de3917 159 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 160 if (!bgx)
161 return;
162
163 lmac = &bgx->lmac[lmacid];
164 link->link_up = lmac->link_up;
165 link->duplex = lmac->last_duplex;
166 link->speed = lmac->last_speed;
167}
168EXPORT_SYMBOL(bgx_get_lmac_link_state);
169
e610cb32 170const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
4863dea3 171{
09de3917 172 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 173
174 if (bgx)
175 return bgx->lmac[lmacid].mac;
176
177 return NULL;
178}
179EXPORT_SYMBOL(bgx_get_lmac_mac);
180
e610cb32 181void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
4863dea3 182{
09de3917 183 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 184
185 if (!bgx)
186 return;
187
188 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
189}
190EXPORT_SYMBOL(bgx_set_lmac_mac);
191
bc69fdfc
SG		 192void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
193{
09de3917 194 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
6465859a 195 struct lmac *lmac;
bc69fdfc
SG		 196 u64 cfg;
197
198 if (!bgx)
199 return;
6465859a 200 lmac = &bgx->lmac[lmacid];
bc69fdfc
SG		 201
202 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
203 if (enable)
204 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
205 else
206 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
207 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
6465859a
SG		 208
209 if (bgx->is_rgx)
210 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
bc69fdfc
SG		 211}
212EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
213
4863dea3
SG		 214static void bgx_sgmii_change_link_state(struct lmac *lmac)
215{
216 struct bgx *bgx = lmac->bgx;
217 u64 cmr_cfg;
218 u64 port_cfg = 0;
219 u64 misc_ctl = 0;
220
221 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
222 cmr_cfg &= ~CMR_EN;
223 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
224
225 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
226 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
227
228 if (lmac->link_up) {
229 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
230 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
231 port_cfg |= (lmac->last_duplex << 2);
232 } else {
233 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
234 }
235
236 switch (lmac->last_speed) {
237 case 10:
238 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
239 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
240 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
241 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
242 misc_ctl |= 50; /* samp_pt */
243 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
244 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
245 break;
246 case 100:
247 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
248 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
249 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
250 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
251 misc_ctl |= 5; /* samp_pt */
252 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
253 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
254 break;
255 case 1000:
256 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
257 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
258 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
259 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
260 misc_ctl |= 1; /* samp_pt */
261 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
262 if (lmac->last_duplex)
263 bgx_reg_write(bgx, lmac->lmacid,
264 BGX_GMP_GMI_TXX_BURST, 0);
265 else
266 bgx_reg_write(bgx, lmac->lmacid,
267 BGX_GMP_GMI_TXX_BURST, 8192);
268 break;
269 default:
270 break;
271 }
272 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
273 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
274
275 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
276
6465859a 277 /* Re-enable lmac */
4863dea3
SG		 278 cmr_cfg |= CMR_EN;
279 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
6465859a
SG		 280
281 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
282 xcv_setup_link(lmac->link_up, lmac->last_speed);
4863dea3
SG		 283}
284
fd7ec062 285static void bgx_lmac_handler(struct net_device *netdev)
4863dea3
SG		 286{
287 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
099a728d 288 struct phy_device *phydev;
4863dea3
SG		 289 int link_changed = 0;
290
291 if (!lmac)
292 return;
293
099a728d 294 phydev = lmac->phydev;
295
4863dea3
SG		 296 if (!phydev->link && lmac->last_link)
297 link_changed = -1;
298
299 if (phydev->link &&
300 (lmac->last_duplex != phydev->duplex ||
301 lmac->last_link != phydev->link ||
302 lmac->last_speed != phydev->speed)) {
303 link_changed = 1;
304 }
305
306 lmac->last_link = phydev->link;
307 lmac->last_speed = phydev->speed;
308 lmac->last_duplex = phydev->duplex;
309
310 if (!link_changed)
311 return;
312
313 if (link_changed > 0)
314 lmac->link_up = true;
315 else
316 lmac->link_up = false;
317
318 if (lmac->is_sgmii)
319 bgx_sgmii_change_link_state(lmac);
320 else
321 bgx_xaui_check_link(lmac);
322}
323
324u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
325{
326 struct bgx *bgx;
327
09de3917 328 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 329 if (!bgx)
330 return 0;
331
332 if (idx > 8)
333 lmac = 0;
334 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
335}
336EXPORT_SYMBOL(bgx_get_rx_stats);
337
338u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
339{
340 struct bgx *bgx;
341
09de3917 342 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 343 if (!bgx)
344 return 0;
345
346 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
347}
348EXPORT_SYMBOL(bgx_get_tx_stats);
349
350static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
351{
352 u64 offset;
353
354 while (bgx->lmac[lmac].dmac > 0) {
355 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
356 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
357 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
358 bgx->lmac[lmac].dmac--;
359 }
360}
361
d77a2384
SG		 362/* Configure BGX LMAC in internal loopback mode */
363void bgx_lmac_internal_loopback(int node, int bgx_idx,
364 int lmac_idx, bool enable)
365{
366 struct bgx *bgx;
367 struct lmac *lmac;
368 u64 cfg;
369
09de3917 370 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
d77a2384
SG		 371 if (!bgx)
372 return;
373
374 lmac = &bgx->lmac[lmac_idx];
375 if (lmac->is_sgmii) {
376 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
377 if (enable)
378 cfg |= PCS_MRX_CTL_LOOPBACK1;
379 else
380 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
381 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
382 } else {
383 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
384 if (enable)
385 cfg |= SPU_CTL_LOOPBACK;
386 else
387 cfg &= ~SPU_CTL_LOOPBACK;
388 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
389 }
390}
391EXPORT_SYMBOL(bgx_lmac_internal_loopback);
392
3f8057cf 393static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
4863dea3 394{
3f8057cf 395 int lmacid = lmac->lmacid;
4863dea3
SG		 396 u64 cfg;
397
398 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
399 /* max packet size */
400 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
401
402 /* Disable frame alignment if using preamble */
403 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
404 if (cfg & 1)
405 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
406
407 /* Enable lmac */
408 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
409
410 /* PCS reset */
411 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
412 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
413 PCS_MRX_CTL_RESET, true)) {
414 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
415 return -1;
416 }
417
418 /* power down, reset autoneg, autoneg enable */
419 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
420 cfg &= ~PCS_MRX_CTL_PWR_DN;
421 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
422 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
423
3f8057cf
SG		 424 if (lmac->lmac_type == BGX_MODE_QSGMII) {
425 /* Disable disparity check for QSGMII */
426 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
427 cfg &= ~PCS_MISC_CTL_DISP_EN;
428 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
429 return 0;
430 }
431
6465859a
SG		 432 if (lmac->lmac_type == BGX_MODE_SGMII) {
433 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
434 PCS_MRX_STATUS_AN_CPT, false)) {
435 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
436 return -1;
437 }
4863dea3
SG		 438 }
439
440 return 0;
441}
442
0bcb7d51 443static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
4863dea3
SG		 444{
445 u64 cfg;
0bcb7d51 446 int lmacid = lmac->lmacid;
4863dea3
SG		 447
448 /* Reset SPU */
449 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
450 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
451 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
452 return -1;
453 }
454
455 /* Disable LMAC */
456 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
457 cfg &= ~CMR_EN;
458 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
459
460 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
461 /* Set interleaved running disparity for RXAUI */
0bcb7d51 462 if (lmac->lmac_type != BGX_MODE_RXAUI)
4863dea3
SG		 463 bgx_reg_modify(bgx, lmacid,
464 BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
465 else
466 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
467 SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP);
468
469 /* clear all interrupts */
470 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
471 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
472 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
473 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
474 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
475 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
476
0bcb7d51 477 if (lmac->use_training) {
4863dea3
SG		 478 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
479 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
480 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
481 /* training enable */
482 bgx_reg_modify(bgx, lmacid,
483 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
484 }
485
486 /* Append FCS to each packet */
487 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
488
489 /* Disable forward error correction */
490 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
491 cfg &= ~SPU_FEC_CTL_FEC_EN;
492 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
493
494 /* Disable autoneg */
495 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
496 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
497 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
498
499 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
0bcb7d51 500 if (lmac->lmac_type == BGX_MODE_10G_KR)
4863dea3 501 cfg |= (1 << 23);
0bcb7d51 502 else if (lmac->lmac_type == BGX_MODE_40G_KR)
4863dea3
SG		 503 cfg |= (1 << 24);
504 else
505 cfg &= ~((1 << 23) | (1 << 24));
506 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
507 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
508
509 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
510 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
511 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
512
513 /* Enable lmac */
514 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
515
516 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
517 cfg &= ~SPU_CTL_LOW_POWER;
518 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
519
520 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
521 cfg &= ~SMU_TX_CTL_UNI_EN;
522 cfg |= SMU_TX_CTL_DIC_EN;
523 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
524
525 /* take lmac_count into account */
526 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
527 /* max packet size */
528 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
529
530 return 0;
531}
532
533static int bgx_xaui_check_link(struct lmac *lmac)
534{
535 struct bgx *bgx = lmac->bgx;
536 int lmacid = lmac->lmacid;
0bcb7d51 537 int lmac_type = lmac->lmac_type;
4863dea3
SG		 538 u64 cfg;
539
540 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
0bcb7d51 541 if (lmac->use_training) {
4863dea3
SG		 542 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
543 if (!(cfg & (1ull << 13))) {
544 cfg = (1ull << 13) | (1ull << 14);
545 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
546 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
547 cfg |= (1ull << 0);
548 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
549 return -1;
550 }
551 }
552
553 /* wait for PCS to come out of reset */
554 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
555 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
556 return -1;
557 }
558
559 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
560 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
561 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
562 SPU_BR_STATUS_BLK_LOCK, false)) {
563 dev_err(&bgx->pdev->dev,
564 "SPU_BR_STATUS_BLK_LOCK not completed\n");
565 return -1;
566 }
567 } else {
568 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
569 SPU_BX_STATUS_RX_ALIGN, false)) {
570 dev_err(&bgx->pdev->dev,
571 "SPU_BX_STATUS_RX_ALIGN not completed\n");
572 return -1;
573 }
574 }
575
576 /* Clear rcvflt bit (latching high) and read it back */
3f4c68cf
SG		 577 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
578 bgx_reg_modify(bgx, lmacid,
579 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
4863dea3
SG		 580 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
581 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
0bcb7d51 582 if (lmac->use_training) {
4863dea3
SG		 583 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
584 if (!(cfg & (1ull << 13))) {
585 cfg = (1ull << 13) | (1ull << 14);
586 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
587 cfg = bgx_reg_read(bgx, lmacid,
588 BGX_SPUX_BR_PMD_CRTL);
589 cfg |= (1ull << 0);
590 bgx_reg_write(bgx, lmacid,
591 BGX_SPUX_BR_PMD_CRTL, cfg);
592 return -1;
593 }
594 }
595 return -1;
596 }
597
4863dea3
SG		 598 /* Wait for BGX RX to be idle */
599 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
600 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
601 return -1;
602 }
603
604 /* Wait for BGX TX to be idle */
605 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
606 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
607 return -1;
608 }
609
3f4c68cf 610 /* Clear receive packet disable */
4863dea3
SG		 611 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
612 cfg &= ~SPU_MISC_CTL_RX_DIS;
613 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
3f4c68cf
SG		 614
615 /* Check for MAC RX faults */
616 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
617 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
618 cfg &= SMU_RX_CTL_STATUS;
619 if (!cfg)
620 return 0;
621
622 /* Rx local/remote fault seen.
623 * Do lmac reinit to see if condition recovers
624 */
0bcb7d51 625 bgx_lmac_xaui_init(bgx, lmac);
3f4c68cf
SG		 626
627 return -1;
4863dea3
SG		 628}
629
630static void bgx_poll_for_link(struct work_struct *work)
631{
632 struct lmac *lmac;
3f4c68cf 633 u64 spu_link, smu_link;
4863dea3
SG		 634
635 lmac = container_of(work, struct lmac, dwork.work);
636
637 /* Receive link is latching low. Force it high and verify it */
638 bgx_reg_modify(lmac->bgx, lmac->lmacid,
639 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
640 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
641 SPU_STATUS1_RCV_LNK, false);
642
3f4c68cf
SG		 643 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
644 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
645
646 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
647 !(smu_link & SMU_RX_CTL_STATUS)) {
4863dea3 648 lmac->link_up = 1;
0bcb7d51 649 if (lmac->lmac_type == BGX_MODE_XLAUI)
4863dea3
SG		 650 lmac->last_speed = 40000;
651 else
652 lmac->last_speed = 10000;
653 lmac->last_duplex = 1;
654 } else {
655 lmac->link_up = 0;
0b72a9a1
SG		 656 lmac->last_speed = SPEED_UNKNOWN;
657 lmac->last_duplex = DUPLEX_UNKNOWN;
4863dea3
SG		 658 }
659
660 if (lmac->last_link != lmac->link_up) {
3f4c68cf
SG		 661 if (lmac->link_up) {
662 if (bgx_xaui_check_link(lmac)) {
663 /* Errors, clear link_up state */
664 lmac->link_up = 0;
665 lmac->last_speed = SPEED_UNKNOWN;
666 lmac->last_duplex = DUPLEX_UNKNOWN;
667 }
668 }
4863dea3 669 lmac->last_link = lmac->link_up;
4863dea3
SG		 670 }
671
672 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
673}
674
3f8057cf
SG		 675static int phy_interface_mode(u8 lmac_type)
676{
677 if (lmac_type == BGX_MODE_QSGMII)
678 return PHY_INTERFACE_MODE_QSGMII;
6465859a
SG		 679 if (lmac_type == BGX_MODE_RGMII)
680 return PHY_INTERFACE_MODE_RGMII;
3f8057cf
SG		 681
682 return PHY_INTERFACE_MODE_SGMII;
683}
684
4863dea3
SG		 685static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
686{
687 struct lmac *lmac;
688 u64 cfg;
689
690 lmac = &bgx->lmac[lmacid];
691 lmac->bgx = bgx;
692
3f8057cf 693 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
6465859a
SG		 694 (lmac->lmac_type == BGX_MODE_QSGMII) ||
695 (lmac->lmac_type == BGX_MODE_RGMII)) {
4863dea3 696 lmac->is_sgmii = 1;
3f8057cf 697 if (bgx_lmac_sgmii_init(bgx, lmac))
4863dea3
SG		 698 return -1;
699 } else {
700 lmac->is_sgmii = 0;
0bcb7d51 701 if (bgx_lmac_xaui_init(bgx, lmac))
4863dea3
SG		 702 return -1;
703 }
704
705 if (lmac->is_sgmii) {
706 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
707 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
708 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
709 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
710 } else {
711 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
712 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
713 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
714 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
715 }
716
717 /* Enable lmac */
bc69fdfc 718 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
4863dea3
SG		 719
720 /* Restore default cfg, incase low level firmware changed it */
721 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
722
0bcb7d51
SG		 723 if ((lmac->lmac_type != BGX_MODE_XFI) &&
724 (lmac->lmac_type != BGX_MODE_XLAUI) &&
725 (lmac->lmac_type != BGX_MODE_40G_KR) &&
726 (lmac->lmac_type != BGX_MODE_10G_KR)) {
4863dea3
SG		 727 if (!lmac->phydev)
728 return -ENODEV;
729
730 lmac->phydev->dev_flags = 0;
731
732 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
733 bgx_lmac_handler,
3f8057cf 734 phy_interface_mode(lmac->lmac_type)))
4863dea3
SG		 735 return -ENODEV;
736
737 phy_start_aneg(lmac->phydev);
738 } else {
739 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
740 WQ_MEM_RECLAIM, 1);
741 if (!lmac->check_link)
742 return -ENOMEM;
743 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
744 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
745 }
746
747 return 0;
748}
749
fd7ec062 750static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 751{
752 struct lmac *lmac;
3f4c68cf 753 u64 cfg;
4863dea3
SG		 754
755 lmac = &bgx->lmac[lmacid];
756 if (lmac->check_link) {
757 /* Destroy work queue */
a7b1f535 758 cancel_delayed_work_sync(&lmac->dwork);
4863dea3
SG		 759 destroy_workqueue(lmac->check_link);
760 }
761
3f4c68cf
SG		 762 /* Disable packet reception */
763 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
764 cfg &= ~CMR_PKT_RX_EN;
765 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
766
767 /* Give chance for Rx/Tx FIFO to get drained */
768 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
769 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
770
771 /* Disable packet transmission */
772 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
773 cfg &= ~CMR_PKT_TX_EN;
774 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
775
776 /* Disable serdes lanes */
777 if (!lmac->is_sgmii)
778 bgx_reg_modify(bgx, lmacid,
779 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
780 else
781 bgx_reg_modify(bgx, lmacid,
782 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
783
784 /* Disable LMAC */
785 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
786 cfg &= ~CMR_EN;
787 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
788
4863dea3
SG		 789 bgx_flush_dmac_addrs(bgx, lmacid);
790
0bcb7d51
SG		 791 if ((lmac->lmac_type != BGX_MODE_XFI) &&
792 (lmac->lmac_type != BGX_MODE_XLAUI) &&
793 (lmac->lmac_type != BGX_MODE_40G_KR) &&
794 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
4863dea3
SG		 795 phy_disconnect(lmac->phydev);
796
797 lmac->phydev = NULL;
798}
799
4863dea3
SG		 800static void bgx_init_hw(struct bgx *bgx)
801{
802 int i;
0bcb7d51 803 struct lmac *lmac;
4863dea3
SG		 804
805 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
806 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
807 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
808
809 /* Set lmac type and lane2serdes mapping */
810 for (i = 0; i < bgx->lmac_count; i++) {
0bcb7d51 811 lmac = &bgx->lmac[i];
4863dea3 812 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
0bcb7d51 813 (lmac->lmac_type << 8) | lmac->lane_to_sds);
4863dea3
SG		 814 bgx->lmac[i].lmacid_bd = lmac_count;
815 lmac_count++;
816 }
817
818 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
819 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
820
821 /* Set the backpressure AND mask */
822 for (i = 0; i < bgx->lmac_count; i++)
823 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
824 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
825 (i * MAX_BGX_CHANS_PER_LMAC));
826
827 /* Disable all MAC filtering */
828 for (i = 0; i < RX_DMAC_COUNT; i++)
829 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
830
831 /* Disable MAC steering (NCSI traffic) */
832 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
833 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
834}
835
3f8057cf
SG		 836static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
837{
838 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
839}
840
0bcb7d51 841static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 842{
843 struct device *dev = &bgx->pdev->dev;
0bcb7d51
SG		 844 struct lmac *lmac;
845 char str[20];
57aaf63c
SG		 846 u8 dlm;
847
6465859a 848 if (lmacid > bgx->max_lmac)
57aaf63c 849 return;
4863dea3 850
0bcb7d51 851 lmac = &bgx->lmac[lmacid];
57aaf63c 852 dlm = (lmacid / 2) + (bgx->bgx_id * 2);
09de3917 853 if (!bgx->is_dlm)
57aaf63c
SG		 854 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
855 else
856 sprintf(str, "BGX%d DLM%d mode", bgx->bgx_id, dlm);
4863dea3 857
0bcb7d51 858 switch (lmac->lmac_type) {
4863dea3 859 case BGX_MODE_SGMII:
0bcb7d51 860 dev_info(dev, "%s: SGMII\n", (char *)str);
4863dea3
SG		 861 break;
862 case BGX_MODE_XAUI:
0bcb7d51 863 dev_info(dev, "%s: XAUI\n", (char *)str);
4863dea3
SG		 864 break;
865 case BGX_MODE_RXAUI:
0bcb7d51 866 dev_info(dev, "%s: RXAUI\n", (char *)str);
4863dea3
SG		 867 break;
868 case BGX_MODE_XFI:
0bcb7d51
SG		 869 if (!lmac->use_training)
870 dev_info(dev, "%s: XFI\n", (char *)str);
871 else
872 dev_info(dev, "%s: 10G_KR\n", (char *)str);
4863dea3
SG		 873 break;
874 case BGX_MODE_XLAUI:
0bcb7d51
SG		 875 if (!lmac->use_training)
876 dev_info(dev, "%s: XLAUI\n", (char *)str);
877 else
878 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
4863dea3 879 break;
3f8057cf
SG		 880 case BGX_MODE_QSGMII:
881 if ((lmacid == 0) &&
882 (bgx_get_lane2sds_cfg(bgx, lmac) != lmacid))
883 return;
884 if ((lmacid == 2) &&
885 (bgx_get_lane2sds_cfg(bgx, lmac) == lmacid))
886 return;
887 dev_info(dev, "%s: QSGMII\n", (char *)str);
888 break;
6465859a
SG		 889 case BGX_MODE_RGMII:
890 dev_info(dev, "%s: RGMII\n", (char *)str);
891 break;
3f8057cf
SG		 892 case BGX_MODE_INVALID:
893 /* Nothing to do */
894 break;
4863dea3
SG		 895 }
896}
897
3f8057cf 898static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
0bcb7d51
SG		 899{
900 switch (lmac->lmac_type) {
901 case BGX_MODE_SGMII:
902 case BGX_MODE_XFI:
903 lmac->lane_to_sds = lmac->lmacid;
904 break;
905 case BGX_MODE_XAUI:
906 case BGX_MODE_XLAUI:
6465859a 907 case BGX_MODE_RGMII:
0bcb7d51
SG		 908 lmac->lane_to_sds = 0xE4;
909 break;
910 case BGX_MODE_RXAUI:
911 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
912 break;
3f8057cf
SG		 913 case BGX_MODE_QSGMII:
914 /* There is no way to determine if DLM0/2 is QSGMII or
915 * DLM1/3 is configured to QSGMII as bootloader will
916 * configure all LMACs, so take whatever is configured
917 * by low level firmware.
918 */
919 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
920 break;
0bcb7d51
SG		 921 default:
922 lmac->lane_to_sds = 0;
923 break;
924 }
925}
926
6465859a
SG		 927static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
928{
929 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
930 (lmac->lmac_type != BGX_MODE_40G_KR)) {
931 lmac->use_training = 0;
932 return;
933 }
934
935 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
936 SPU_PMD_CRTL_TRAIN_EN;
937}
938
0bcb7d51
SG		 939static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
940{
941 struct lmac *lmac;
57aaf63c 942 struct lmac *olmac;
0bcb7d51 943 u64 cmr_cfg;
57aaf63c
SG		 944 u8 lmac_type;
945 u8 lane_to_sds;
0bcb7d51
SG		 946
947 lmac = &bgx->lmac[idx];
0bcb7d51 948
09de3917 949 if (!bgx->is_dlm || bgx->is_rgx) {
57aaf63c
SG		 950 /* Read LMAC0 type to figure out QLM mode
951 * This is configured by low level firmware
952 */
953 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
954 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
6465859a
SG		 955 if (bgx->is_rgx)
956 lmac->lmac_type = BGX_MODE_RGMII;
957 lmac_set_training(bgx, lmac, 0);
3f8057cf 958 lmac_set_lane2sds(bgx, lmac);
57aaf63c
SG		 959 return;
960 }
961
962 /* On 81xx BGX can be split across 2 DLMs
963 * firmware programs lmac_type of LMAC0 and LMAC2
0bcb7d51 964 */
57aaf63c
SG		 965 if ((idx == 0) || (idx == 2)) {
966 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
967 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
968 lane_to_sds = (u8)(cmr_cfg & 0xFF);
969 /* Check if config is not reset value */
970 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
971 lmac->lmac_type = BGX_MODE_INVALID;
972 else
973 lmac->lmac_type = lmac_type;
6465859a 974 lmac_set_training(bgx, lmac, lmac->lmacid);
3f8057cf 975 lmac_set_lane2sds(bgx, lmac);
57aaf63c
SG		 976
977 /* Set LMAC type of other lmac on same DLM i.e LMAC 1/3 */
978 olmac = &bgx->lmac[idx + 1];
979 olmac->lmac_type = lmac->lmac_type;
6465859a 980 lmac_set_training(bgx, olmac, olmac->lmacid);
3f8057cf 981 lmac_set_lane2sds(bgx, olmac);
57aaf63c
SG		 982 }
983}
984
985static bool is_dlm0_in_bgx_mode(struct bgx *bgx)
986{
987 struct lmac *lmac;
988
09de3917 989 if (!bgx->is_dlm)
57aaf63c
SG		 990 return true;
991
3f8057cf 992 lmac = &bgx->lmac[0];
57aaf63c
SG		 993 if (lmac->lmac_type == BGX_MODE_INVALID)
994 return false;
995
996 return true;
0bcb7d51
SG		 997}
998
999static void bgx_get_qlm_mode(struct bgx *bgx)
1000{
57aaf63c
SG		 1001 struct lmac *lmac;
1002 struct lmac *lmac01;
1003 struct lmac *lmac23;
0bcb7d51
SG		 1004 u8 idx;
1005
57aaf63c 1006 /* Init all LMAC's type to invalid */
6465859a 1007 for (idx = 0; idx < bgx->max_lmac; idx++) {
57aaf63c 1008 lmac = &bgx->lmac[idx];
57aaf63c 1009 lmac->lmacid = idx;
6465859a
SG		 1010 lmac->lmac_type = BGX_MODE_INVALID;
1011 lmac->use_training = false;
57aaf63c
SG		 1012 }
1013
0bcb7d51
SG		 1014 /* It is assumed that low level firmware sets this value */
1015 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
6465859a
SG		 1016 if (bgx->lmac_count > bgx->max_lmac)
1017 bgx->lmac_count = bgx->max_lmac;
0bcb7d51 1018
6465859a 1019 for (idx = 0; idx < bgx->max_lmac; idx++)
0bcb7d51 1020 bgx_set_lmac_config(bgx, idx);
57aaf63c 1021
09de3917 1022 if (!bgx->is_dlm || bgx->is_rgx) {
57aaf63c
SG		 1023 bgx_print_qlm_mode(bgx, 0);
1024 return;
1025 }
1026
1027 if (bgx->lmac_count) {
1028 bgx_print_qlm_mode(bgx, 0);
1029 bgx_print_qlm_mode(bgx, 2);
1030 }
1031
1032 /* If DLM0 is not in BGX mode then LMAC0/1 have
1033 * to be configured with serdes lanes of DLM1
1034 */
1035 if (is_dlm0_in_bgx_mode(bgx) || (bgx->lmac_count > 2))
1036 return;
1037 for (idx = 0; idx < bgx->lmac_count; idx++) {
1038 lmac01 = &bgx->lmac[idx];
1039 lmac23 = &bgx->lmac[idx + 2];
1040 lmac01->lmac_type = lmac23->lmac_type;
1041 lmac01->lane_to_sds = lmac23->lane_to_sds;
1042 }
0bcb7d51
SG		 1043}
1044
46b903a0
DD		 1045#ifdef CONFIG_ACPI
1046
1d82efac
RR		 1047static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1048 u8 *dst)
46b903a0
DD		 1049{
1050 u8 mac[ETH_ALEN];
1051 int ret;
1052
1053 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1054 "mac-address", mac, ETH_ALEN);
1055 if (ret)
1056 goto out;
1057
1058 if (!is_valid_ether_addr(mac)) {
1d82efac 1059 dev_err(dev, "MAC address invalid: %pM\n", mac);
46b903a0
DD		 1060 ret = -EINVAL;
1061 goto out;
1062 }
1063
1d82efac
RR		 1064 dev_info(dev, "MAC address set to: %pM\n", mac);
1065
46b903a0
DD		 1066 memcpy(dst, mac, ETH_ALEN);
1067out:
1068 return ret;
1069}
1070
1071/* Currently only sets the MAC address. */
1072static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1073 u32 lvl, void *context, void **rv)
1074{
1075 struct bgx *bgx = context;
1d82efac 1076 struct device *dev = &bgx->pdev->dev;
46b903a0
DD		 1077 struct acpi_device *adev;
1078
1079 if (acpi_bus_get_device(handle, &adev))
1080 goto out;
1081
1d82efac 1082 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->lmac_count].mac);
46b903a0 1083
1d82efac 1084 SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, dev);
46b903a0
DD		 1085
1086 bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
1087out:
1088 bgx->lmac_count++;
1089 return AE_OK;
1090}
1091
1092static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1093 void *context, void **ret_val)
1094{
1095 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1096 struct bgx *bgx = context;
1097 char bgx_sel[5];
1098
1099 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1100 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1101 pr_warn("Invalid link device\n");
1102 return AE_OK;
1103 }
1104
1105 if (strncmp(string.pointer, bgx_sel, 4))
1106 return AE_OK;
1107
1108 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1109 bgx_acpi_register_phy, NULL, bgx, NULL);
1110
1111 kfree(string.pointer);
1112 return AE_CTRL_TERMINATE;
1113}
1114
1115static int bgx_init_acpi_phy(struct bgx *bgx)
1116{
1117 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1118 return 0;
1119}
1120
1121#else
1122
1123static int bgx_init_acpi_phy(struct bgx *bgx)
1124{
1125 return -ENODEV;
1126}
1127
1128#endif /* CONFIG_ACPI */
1129
de387e11
RR		 1130#if IS_ENABLED(CONFIG_OF_MDIO)
1131
1132static int bgx_init_of_phy(struct bgx *bgx)
4863dea3 1133{
eee326fd 1134 struct fwnode_handle *fwn;
b7d3e3d3 1135 struct device_node *node = NULL;
4863dea3
SG		 1136 u8 lmac = 0;
1137
eee326fd 1138 device_for_each_child_node(&bgx->pdev->dev, fwn) {
5fc7cf17 1139 struct phy_device *pd;
eee326fd 1140 struct device_node *phy_np;
b7d3e3d3 1141 const char *mac;
eee326fd 1142
5fc7cf17
DD		 1143 /* Should always be an OF node. But if it is not, we
1144 * cannot handle it, so exit the loop.
eee326fd 1145 */
b7d3e3d3 1146 node = to_of_node(fwn);
eee326fd
DD		 1147 if (!node)
1148 break;
4863dea3 1149
eee326fd 1150 mac = of_get_mac_address(node);
4863dea3
SG		 1151 if (mac)
1152 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1153
1154 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1155 bgx->lmac[lmac].lmacid = lmac;
5fc7cf17
DD		 1156
1157 phy_np = of_parse_phandle(node, "phy-handle", 0);
1158 /* If there is no phy or defective firmware presents
1159 * this cortina phy, for which there is no driver
1160 * support, ignore it.
1161 */
1162 if (phy_np &&
1163 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1164 /* Wait until the phy drivers are available */
1165 pd = of_phy_find_device(phy_np);
1166 if (!pd)
b7d3e3d3 1167 goto defer;
5fc7cf17
DD		 1168 bgx->lmac[lmac].phydev = pd;
1169 }
1170
4863dea3 1171 lmac++;
6465859a 1172 if (lmac == bgx->max_lmac) {
65c66af6 1173 of_node_put(node);
4863dea3 1174 break;
65c66af6 1175 }
4863dea3 1176 }
de387e11 1177 return 0;
b7d3e3d3
DD		 1178
1179defer:
1180 /* We are bailing out, try not to leak device reference counts
1181 * for phy devices we may have already found.
1182 */
1183 while (lmac) {
1184 if (bgx->lmac[lmac].phydev) {
1185 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1186 bgx->lmac[lmac].phydev = NULL;
1187 }
1188 lmac--;
1189 }
1190 of_node_put(node);
1191 return -EPROBE_DEFER;
de387e11
RR		 1192}
1193
1194#else
1195
1196static int bgx_init_of_phy(struct bgx *bgx)
1197{
1198 return -ENODEV;
1199}
1200
1201#endif /* CONFIG_OF_MDIO */
1202
1203static int bgx_init_phy(struct bgx *bgx)
1204{
46b903a0
DD		 1205 if (!acpi_disabled)
1206 return bgx_init_acpi_phy(bgx);
1207
de387e11 1208 return bgx_init_of_phy(bgx);
4863dea3
SG		 1209}
1210
1211static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1212{
1213 int err;
1214 struct device *dev = &pdev->dev;
1215 struct bgx *bgx = NULL;
4863dea3 1216 u8 lmac;
57aaf63c 1217 u16 sdevid;
4863dea3
SG		 1218
1219 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1220 if (!bgx)
1221 return -ENOMEM;
1222 bgx->pdev = pdev;
1223
1224 pci_set_drvdata(pdev, bgx);
1225
1226 err = pci_enable_device(pdev);
1227 if (err) {
1228 dev_err(dev, "Failed to enable PCI device\n");
1229 pci_set_drvdata(pdev, NULL);
1230 return err;
1231 }
1232
1233 err = pci_request_regions(pdev, DRV_NAME);
1234 if (err) {
1235 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1236 goto err_disable_device;
1237 }
1238
1239 /* MAP configuration registers */
1240 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1241 if (!bgx->reg_base) {
1242 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1243 err = -ENOMEM;
1244 goto err_release_regions;
1245 }
d768b678 1246
6465859a
SG		 1247 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1248 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1249 bgx->bgx_id =
1250 (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1;
09de3917 1251 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;
6465859a
SG		 1252 bgx->max_lmac = MAX_LMAC_PER_BGX;
1253 bgx_vnic[bgx->bgx_id] = bgx;
1254 } else {
1255 bgx->is_rgx = true;
1256 bgx->max_lmac = 1;
1257 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1258 bgx_vnic[bgx->bgx_id] = bgx;
1259 xcv_init_hw();
1260 }
1261
09de3917
SG		 1262 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1263 * BGX i.e BGX2 can be split across 2 DLMs.
1264 */
1265 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1266 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1267 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1268 bgx->is_dlm = true;
1269
4863dea3
SG		 1270 bgx_get_qlm_mode(bgx);
1271
de387e11
RR		 1272 err = bgx_init_phy(bgx);
1273 if (err)
1274 goto err_enable;
4863dea3
SG		 1275
1276 bgx_init_hw(bgx);
1277
1278 /* Enable all LMACs */
1279 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1280 err = bgx_lmac_enable(bgx, lmac);
1281 if (err) {
1282 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1283 bgx->bgx_id, lmac);
57aaf63c
SG		 1284 while (lmac)
1285 bgx_lmac_disable(bgx, --lmac);
4863dea3
SG		 1286 goto err_enable;
1287 }
1288 }
1289
1290 return 0;
1291
1292err_enable:
1293 bgx_vnic[bgx->bgx_id] = NULL;
1294err_release_regions:
1295 pci_release_regions(pdev);
1296err_disable_device:
1297 pci_disable_device(pdev);
1298 pci_set_drvdata(pdev, NULL);
1299 return err;
1300}
1301
1302static void bgx_remove(struct pci_dev *pdev)
1303{
1304 struct bgx *bgx = pci_get_drvdata(pdev);
1305 u8 lmac;
1306
1307 /* Disable all LMACs */
1308 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1309 bgx_lmac_disable(bgx, lmac);
1310
1311 bgx_vnic[bgx->bgx_id] = NULL;
1312 pci_release_regions(pdev);
1313 pci_disable_device(pdev);
1314 pci_set_drvdata(pdev, NULL);
1315}
1316
1317static struct pci_driver bgx_driver = {
1318 .name = DRV_NAME,
1319 .id_table = bgx_id_table,
1320 .probe = bgx_probe,
1321 .remove = bgx_remove,
1322};
1323
1324static int __init bgx_init_module(void)
1325{
1326 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1327
1328 return pci_register_driver(&bgx_driver);
1329}
1330
1331static void __exit bgx_cleanup_module(void)
1332{
1333 pci_unregister_driver(&bgx_driver);
1334}
1335
1336module_init(bgx_init_module);
1337module_exit(bgx_cleanup_module);
Ubuntu Artful kernel mirror