]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/net/ethernet/cavium/thunder/thunder_bgx.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: thunderx: Switchon carrier only upon interface link up
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
46b903a0 9#include <linux/acpi.h>
4863dea3
SG		 10#include <linux/module.h>
11#include <linux/interrupt.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/phy.h>
16#include <linux/of.h>
17#include <linux/of_mdio.h>
18#include <linux/of_net.h>
19
20#include "nic_reg.h"
21#include "nic.h"
22#include "thunder_bgx.h"
23
24#define DRV_NAME "thunder-BGX"
25#define DRV_VERSION "1.0"
26
27struct lmac {
28 struct bgx *bgx;
29 int dmac;
46b903a0 30 u8 mac[ETH_ALEN];
4863dea3
SG		 31 bool link_up;
32 int lmacid; /* ID within BGX */
33 int lmacid_bd; /* ID on board */
34 struct net_device netdev;
35 struct phy_device *phydev;
36 unsigned int last_duplex;
37 unsigned int last_link;
38 unsigned int last_speed;
39 bool is_sgmii;
40 struct delayed_work dwork;
41 struct workqueue_struct *check_link;
0c886a1d 42};
4863dea3
SG		 43
44struct bgx {
45 u8 bgx_id;
46 u8 qlm_mode;
47 struct lmac lmac[MAX_LMAC_PER_BGX];
48 int lmac_count;
49 int lmac_type;
50 int lane_to_sds;
51 int use_training;
52 void __iomem *reg_base;
53 struct pci_dev *pdev;
0c886a1d 54};
4863dea3 55
fd7ec062 56static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
4863dea3
SG		 57static int lmac_count; /* Total no of LMACs in system */
58
59static int bgx_xaui_check_link(struct lmac *lmac);
60
61/* Supported devices */
62static const struct pci_device_id bgx_id_table[] = {
63 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
64 { 0, } /* end of table */
65};
66
67MODULE_AUTHOR("Cavium Inc");
68MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
69MODULE_LICENSE("GPL v2");
70MODULE_VERSION(DRV_VERSION);
71MODULE_DEVICE_TABLE(pci, bgx_id_table);
72
73/* The Cavium ThunderX network controller can *only* be found in SoCs
74 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
75 * registers on this platform are implicitly strongly ordered with respect
76 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
77 * with no memory barriers in this driver. The readq()/writeq() functions add
78 * explicit ordering operation which in this case are redundant, and only
79 * add overhead.
80 */
81
82/* Register read/write APIs */
83static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
84{
85 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
86
87 return readq_relaxed(addr);
88}
89
90static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
91{
92 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
93
94 writeq_relaxed(val, addr);
95}
96
97static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
98{
99 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
100
101 writeq_relaxed(val | readq_relaxed(addr), addr);
102}
103
104static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
105{
106 int timeout = 100;
107 u64 reg_val;
108
109 while (timeout) {
110 reg_val = bgx_reg_read(bgx, lmac, reg);
111 if (zero && !(reg_val & mask))
112 return 0;
113 if (!zero && (reg_val & mask))
114 return 0;
115 usleep_range(1000, 2000);
116 timeout--;
117 }
118 return 1;
119}
120
121/* Return number of BGX present in HW */
122unsigned bgx_get_map(int node)
123{
124 int i;
125 unsigned map = 0;
126
127 for (i = 0; i < MAX_BGX_PER_CN88XX; i++) {
128 if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i])
129 map |= (1 << i);
130 }
131
132 return map;
133}
134EXPORT_SYMBOL(bgx_get_map);
135
136/* Return number of LMAC configured for this BGX */
137int bgx_get_lmac_count(int node, int bgx_idx)
138{
139 struct bgx *bgx;
140
141 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
142 if (bgx)
143 return bgx->lmac_count;
144
145 return 0;
146}
147EXPORT_SYMBOL(bgx_get_lmac_count);
148
149/* Returns the current link status of LMAC */
150void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
151{
152 struct bgx_link_status *link = (struct bgx_link_status *)status;
153 struct bgx *bgx;
154 struct lmac *lmac;
155
156 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
157 if (!bgx)
158 return;
159
160 lmac = &bgx->lmac[lmacid];
161 link->link_up = lmac->link_up;
162 link->duplex = lmac->last_duplex;
163 link->speed = lmac->last_speed;
164}
165EXPORT_SYMBOL(bgx_get_lmac_link_state);
166
e610cb32 167const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
4863dea3
SG		 168{
169 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
170
171 if (bgx)
172 return bgx->lmac[lmacid].mac;
173
174 return NULL;
175}
176EXPORT_SYMBOL(bgx_get_lmac_mac);
177
e610cb32 178void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
4863dea3
SG		 179{
180 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
181
182 if (!bgx)
183 return;
184
185 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
186}
187EXPORT_SYMBOL(bgx_set_lmac_mac);
188
189static void bgx_sgmii_change_link_state(struct lmac *lmac)
190{
191 struct bgx *bgx = lmac->bgx;
192 u64 cmr_cfg;
193 u64 port_cfg = 0;
194 u64 misc_ctl = 0;
195
196 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
197 cmr_cfg &= ~CMR_EN;
198 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
199
200 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
201 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
202
203 if (lmac->link_up) {
204 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
205 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
206 port_cfg |= (lmac->last_duplex << 2);
207 } else {
208 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
209 }
210
211 switch (lmac->last_speed) {
212 case 10:
213 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
214 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
215 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
216 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
217 misc_ctl |= 50; /* samp_pt */
218 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
219 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
220 break;
221 case 100:
222 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
223 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
224 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
225 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
226 misc_ctl |= 5; /* samp_pt */
227 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
228 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
229 break;
230 case 1000:
231 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
232 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
233 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
234 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
235 misc_ctl |= 1; /* samp_pt */
236 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
237 if (lmac->last_duplex)
238 bgx_reg_write(bgx, lmac->lmacid,
239 BGX_GMP_GMI_TXX_BURST, 0);
240 else
241 bgx_reg_write(bgx, lmac->lmacid,
242 BGX_GMP_GMI_TXX_BURST, 8192);
243 break;
244 default:
245 break;
246 }
247 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
248 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
249
250 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
251
252 /* renable lmac */
253 cmr_cfg |= CMR_EN;
254 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
255}
256
fd7ec062 257static void bgx_lmac_handler(struct net_device *netdev)
4863dea3
SG		 258{
259 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
260 struct phy_device *phydev = lmac->phydev;
261 int link_changed = 0;
262
263 if (!lmac)
264 return;
265
266 if (!phydev->link && lmac->last_link)
267 link_changed = -1;
268
269 if (phydev->link &&
270 (lmac->last_duplex != phydev->duplex ||
271 lmac->last_link != phydev->link ||
272 lmac->last_speed != phydev->speed)) {
273 link_changed = 1;
274 }
275
276 lmac->last_link = phydev->link;
277 lmac->last_speed = phydev->speed;
278 lmac->last_duplex = phydev->duplex;
279
280 if (!link_changed)
281 return;
282
283 if (link_changed > 0)
284 lmac->link_up = true;
285 else
286 lmac->link_up = false;
287
288 if (lmac->is_sgmii)
289 bgx_sgmii_change_link_state(lmac);
290 else
291 bgx_xaui_check_link(lmac);
292}
293
294u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
295{
296 struct bgx *bgx;
297
298 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
299 if (!bgx)
300 return 0;
301
302 if (idx > 8)
303 lmac = 0;
304 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
305}
306EXPORT_SYMBOL(bgx_get_rx_stats);
307
308u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
309{
310 struct bgx *bgx;
311
312 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
313 if (!bgx)
314 return 0;
315
316 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
317}
318EXPORT_SYMBOL(bgx_get_tx_stats);
319
320static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
321{
322 u64 offset;
323
324 while (bgx->lmac[lmac].dmac > 0) {
325 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
326 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
327 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
328 bgx->lmac[lmac].dmac--;
329 }
330}
331
d77a2384
SG		 332/* Configure BGX LMAC in internal loopback mode */
333void bgx_lmac_internal_loopback(int node, int bgx_idx,
334 int lmac_idx, bool enable)
335{
336 struct bgx *bgx;
337 struct lmac *lmac;
338 u64 cfg;
339
340 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
341 if (!bgx)
342 return;
343
344 lmac = &bgx->lmac[lmac_idx];
345 if (lmac->is_sgmii) {
346 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
347 if (enable)
348 cfg |= PCS_MRX_CTL_LOOPBACK1;
349 else
350 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
351 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
352 } else {
353 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
354 if (enable)
355 cfg |= SPU_CTL_LOOPBACK;
356 else
357 cfg &= ~SPU_CTL_LOOPBACK;
358 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
359 }
360}
361EXPORT_SYMBOL(bgx_lmac_internal_loopback);
362
4863dea3
SG		 363static int bgx_lmac_sgmii_init(struct bgx *bgx, int lmacid)
364{
365 u64 cfg;
366
367 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
368 /* max packet size */
369 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
370
371 /* Disable frame alignment if using preamble */
372 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
373 if (cfg & 1)
374 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
375
376 /* Enable lmac */
377 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
378
379 /* PCS reset */
380 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
381 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
382 PCS_MRX_CTL_RESET, true)) {
383 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
384 return -1;
385 }
386
387 /* power down, reset autoneg, autoneg enable */
388 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
389 cfg &= ~PCS_MRX_CTL_PWR_DN;
390 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
391 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
392
393 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
394 PCS_MRX_STATUS_AN_CPT, false)) {
395 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
396 return -1;
397 }
398
399 return 0;
400}
401
402static int bgx_lmac_xaui_init(struct bgx *bgx, int lmacid, int lmac_type)
403{
404 u64 cfg;
405
406 /* Reset SPU */
407 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
408 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
409 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
410 return -1;
411 }
412
413 /* Disable LMAC */
414 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
415 cfg &= ~CMR_EN;
416 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
417
418 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
419 /* Set interleaved running disparity for RXAUI */
420 if (bgx->lmac_type != BGX_MODE_RXAUI)
421 bgx_reg_modify(bgx, lmacid,
422 BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
423 else
424 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
425 SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP);
426
427 /* clear all interrupts */
428 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
429 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
430 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
431 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
432 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
433 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
434
435 if (bgx->use_training) {
436 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
437 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
438 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
439 /* training enable */
440 bgx_reg_modify(bgx, lmacid,
441 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
442 }
443
444 /* Append FCS to each packet */
445 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
446
447 /* Disable forward error correction */
448 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
449 cfg &= ~SPU_FEC_CTL_FEC_EN;
450 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
451
452 /* Disable autoneg */
453 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
454 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
455 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
456
457 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
458 if (bgx->lmac_type == BGX_MODE_10G_KR)
459 cfg |= (1 << 23);
460 else if (bgx->lmac_type == BGX_MODE_40G_KR)
461 cfg |= (1 << 24);
462 else
463 cfg &= ~((1 << 23) | (1 << 24));
464 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
465 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
466
467 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
468 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
469 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
470
471 /* Enable lmac */
472 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
473
474 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
475 cfg &= ~SPU_CTL_LOW_POWER;
476 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
477
478 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
479 cfg &= ~SMU_TX_CTL_UNI_EN;
480 cfg |= SMU_TX_CTL_DIC_EN;
481 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
482
483 /* take lmac_count into account */
484 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
485 /* max packet size */
486 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
487
488 return 0;
489}
490
491static int bgx_xaui_check_link(struct lmac *lmac)
492{
493 struct bgx *bgx = lmac->bgx;
494 int lmacid = lmac->lmacid;
495 int lmac_type = bgx->lmac_type;
496 u64 cfg;
497
498 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
499 if (bgx->use_training) {
500 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
501 if (!(cfg & (1ull << 13))) {
502 cfg = (1ull << 13) | (1ull << 14);
503 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
504 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
505 cfg |= (1ull << 0);
506 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
507 return -1;
508 }
509 }
510
511 /* wait for PCS to come out of reset */
512 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
513 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
514 return -1;
515 }
516
517 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
518 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
519 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
520 SPU_BR_STATUS_BLK_LOCK, false)) {
521 dev_err(&bgx->pdev->dev,
522 "SPU_BR_STATUS_BLK_LOCK not completed\n");
523 return -1;
524 }
525 } else {
526 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
527 SPU_BX_STATUS_RX_ALIGN, false)) {
528 dev_err(&bgx->pdev->dev,
529 "SPU_BX_STATUS_RX_ALIGN not completed\n");
530 return -1;
531 }
532 }
533
534 /* Clear rcvflt bit (latching high) and read it back */
535 bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
536 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
537 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
538 if (bgx->use_training) {
539 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
540 if (!(cfg & (1ull << 13))) {
541 cfg = (1ull << 13) | (1ull << 14);
542 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
543 cfg = bgx_reg_read(bgx, lmacid,
544 BGX_SPUX_BR_PMD_CRTL);
545 cfg |= (1ull << 0);
546 bgx_reg_write(bgx, lmacid,
547 BGX_SPUX_BR_PMD_CRTL, cfg);
548 return -1;
549 }
550 }
551 return -1;
552 }
553
554 /* Wait for MAC RX to be ready */
555 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_RX_CTL,
556 SMU_RX_CTL_STATUS, true)) {
557 dev_err(&bgx->pdev->dev, "SMU RX link not okay\n");
558 return -1;
559 }
560
561 /* Wait for BGX RX to be idle */
562 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
563 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
564 return -1;
565 }
566
567 /* Wait for BGX TX to be idle */
568 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
569 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
570 return -1;
571 }
572
573 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
574 dev_err(&bgx->pdev->dev, "Receive fault\n");
575 return -1;
576 }
577
578 /* Receive link is latching low. Force it high and verify it */
579 bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
580 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_STATUS1,
581 SPU_STATUS1_RCV_LNK, false)) {
582 dev_err(&bgx->pdev->dev, "SPU receive link down\n");
583 return -1;
584 }
585
586 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
587 cfg &= ~SPU_MISC_CTL_RX_DIS;
588 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
589 return 0;
590}
591
592static void bgx_poll_for_link(struct work_struct *work)
593{
594 struct lmac *lmac;
595 u64 link;
596
597 lmac = container_of(work, struct lmac, dwork.work);
598
599 /* Receive link is latching low. Force it high and verify it */
600 bgx_reg_modify(lmac->bgx, lmac->lmacid,
601 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
602 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
603 SPU_STATUS1_RCV_LNK, false);
604
605 link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
606 if (link & SPU_STATUS1_RCV_LNK) {
607 lmac->link_up = 1;
608 if (lmac->bgx->lmac_type == BGX_MODE_XLAUI)
609 lmac->last_speed = 40000;
610 else
611 lmac->last_speed = 10000;
612 lmac->last_duplex = 1;
613 } else {
614 lmac->link_up = 0;
0b72a9a1
SG		 615 lmac->last_speed = SPEED_UNKNOWN;
616 lmac->last_duplex = DUPLEX_UNKNOWN;
4863dea3
SG		 617 }
618
619 if (lmac->last_link != lmac->link_up) {
620 lmac->last_link = lmac->link_up;
621 if (lmac->link_up)
622 bgx_xaui_check_link(lmac);
623 }
624
625 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
626}
627
628static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
629{
630 struct lmac *lmac;
631 u64 cfg;
632
633 lmac = &bgx->lmac[lmacid];
634 lmac->bgx = bgx;
635
636 if (bgx->lmac_type == BGX_MODE_SGMII) {
637 lmac->is_sgmii = 1;
638 if (bgx_lmac_sgmii_init(bgx, lmacid))
639 return -1;
640 } else {
641 lmac->is_sgmii = 0;
642 if (bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type))
643 return -1;
644 }
645
646 if (lmac->is_sgmii) {
647 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
648 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
649 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
650 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
651 } else {
652 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
653 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
654 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
655 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
656 }
657
658 /* Enable lmac */
659 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG,
660 CMR_EN | CMR_PKT_RX_EN | CMR_PKT_TX_EN);
661
662 /* Restore default cfg, incase low level firmware changed it */
663 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
664
665 if ((bgx->lmac_type != BGX_MODE_XFI) &&
666 (bgx->lmac_type != BGX_MODE_XLAUI) &&
667 (bgx->lmac_type != BGX_MODE_40G_KR) &&
668 (bgx->lmac_type != BGX_MODE_10G_KR)) {
669 if (!lmac->phydev)
670 return -ENODEV;
671
672 lmac->phydev->dev_flags = 0;
673
674 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
675 bgx_lmac_handler,
676 PHY_INTERFACE_MODE_SGMII))
677 return -ENODEV;
678
679 phy_start_aneg(lmac->phydev);
680 } else {
681 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
682 WQ_MEM_RECLAIM, 1);
683 if (!lmac->check_link)
684 return -ENOMEM;
685 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
686 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
687 }
688
689 return 0;
690}
691
fd7ec062 692static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 693{
694 struct lmac *lmac;
695 u64 cmrx_cfg;
696
697 lmac = &bgx->lmac[lmacid];
698 if (lmac->check_link) {
699 /* Destroy work queue */
a7b1f535 700 cancel_delayed_work_sync(&lmac->dwork);
4863dea3
SG		 701 destroy_workqueue(lmac->check_link);
702 }
703
704 cmrx_cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
705 cmrx_cfg &= ~(1 << 15);
706 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cmrx_cfg);
707 bgx_flush_dmac_addrs(bgx, lmacid);
708
60f83c89
TS		 709 if ((bgx->lmac_type != BGX_MODE_XFI) &&
710 (bgx->lmac_type != BGX_MODE_XLAUI) &&
711 (bgx->lmac_type != BGX_MODE_40G_KR) &&
712 (bgx->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
4863dea3
SG		 713 phy_disconnect(lmac->phydev);
714
715 lmac->phydev = NULL;
716}
717
718static void bgx_set_num_ports(struct bgx *bgx)
719{
720 u64 lmac_count;
721
722 switch (bgx->qlm_mode) {
723 case QLM_MODE_SGMII:
724 bgx->lmac_count = 4;
725 bgx->lmac_type = BGX_MODE_SGMII;
726 bgx->lane_to_sds = 0;
727 break;
728 case QLM_MODE_XAUI_1X4:
729 bgx->lmac_count = 1;
730 bgx->lmac_type = BGX_MODE_XAUI;
731 bgx->lane_to_sds = 0xE4;
732 break;
733 case QLM_MODE_RXAUI_2X2:
734 bgx->lmac_count = 2;
735 bgx->lmac_type = BGX_MODE_RXAUI;
736 bgx->lane_to_sds = 0xE4;
737 break;
738 case QLM_MODE_XFI_4X1:
739 bgx->lmac_count = 4;
740 bgx->lmac_type = BGX_MODE_XFI;
741 bgx->lane_to_sds = 0;
742 break;
743 case QLM_MODE_XLAUI_1X4:
744 bgx->lmac_count = 1;
745 bgx->lmac_type = BGX_MODE_XLAUI;
746 bgx->lane_to_sds = 0xE4;
747 break;
748 case QLM_MODE_10G_KR_4X1:
749 bgx->lmac_count = 4;
750 bgx->lmac_type = BGX_MODE_10G_KR;
751 bgx->lane_to_sds = 0;
752 bgx->use_training = 1;
753 break;
754 case QLM_MODE_40G_KR4_1X4:
755 bgx->lmac_count = 1;
756 bgx->lmac_type = BGX_MODE_40G_KR;
757 bgx->lane_to_sds = 0xE4;
758 bgx->use_training = 1;
759 break;
760 default:
761 bgx->lmac_count = 0;
762 break;
763 }
764
765 /* Check if low level firmware has programmed LMAC count
766 * based on board type, if yes consider that otherwise
767 * the default static values
768 */
769 lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
770 if (lmac_count != 4)
771 bgx->lmac_count = lmac_count;
772}
773
774static void bgx_init_hw(struct bgx *bgx)
775{
776 int i;
777
778 bgx_set_num_ports(bgx);
779
780 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
781 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
782 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
783
784 /* Set lmac type and lane2serdes mapping */
785 for (i = 0; i < bgx->lmac_count; i++) {
786 if (bgx->lmac_type == BGX_MODE_RXAUI) {
787 if (i)
788 bgx->lane_to_sds = 0x0e;
789 else
790 bgx->lane_to_sds = 0x04;
791 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
792 (bgx->lmac_type << 8) | bgx->lane_to_sds);
793 continue;
794 }
795 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
796 (bgx->lmac_type << 8) | (bgx->lane_to_sds + i));
797 bgx->lmac[i].lmacid_bd = lmac_count;
798 lmac_count++;
799 }
800
801 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
802 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
803
804 /* Set the backpressure AND mask */
805 for (i = 0; i < bgx->lmac_count; i++)
806 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
807 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
808 (i * MAX_BGX_CHANS_PER_LMAC));
809
810 /* Disable all MAC filtering */
811 for (i = 0; i < RX_DMAC_COUNT; i++)
812 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
813
814 /* Disable MAC steering (NCSI traffic) */
815 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
816 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
817}
818
819static void bgx_get_qlm_mode(struct bgx *bgx)
820{
821 struct device *dev = &bgx->pdev->dev;
822 int lmac_type;
823 int train_en;
824
825 /* Read LMAC0 type to figure out QLM mode
826 * This is configured by low level firmware
827 */
828 lmac_type = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
829 lmac_type = (lmac_type >> 8) & 0x07;
830
831 train_en = bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) &
832 SPU_PMD_CRTL_TRAIN_EN;
833
834 switch (lmac_type) {
835 case BGX_MODE_SGMII:
836 bgx->qlm_mode = QLM_MODE_SGMII;
837 dev_info(dev, "BGX%d QLM mode: SGMII\n", bgx->bgx_id);
838 break;
839 case BGX_MODE_XAUI:
840 bgx->qlm_mode = QLM_MODE_XAUI_1X4;
841 dev_info(dev, "BGX%d QLM mode: XAUI\n", bgx->bgx_id);
842 break;
843 case BGX_MODE_RXAUI:
844 bgx->qlm_mode = QLM_MODE_RXAUI_2X2;
845 dev_info(dev, "BGX%d QLM mode: RXAUI\n", bgx->bgx_id);
846 break;
847 case BGX_MODE_XFI:
848 if (!train_en) {
849 bgx->qlm_mode = QLM_MODE_XFI_4X1;
850 dev_info(dev, "BGX%d QLM mode: XFI\n", bgx->bgx_id);
851 } else {
852 bgx->qlm_mode = QLM_MODE_10G_KR_4X1;
853 dev_info(dev, "BGX%d QLM mode: 10G_KR\n", bgx->bgx_id);
854 }
855 break;
856 case BGX_MODE_XLAUI:
857 if (!train_en) {
858 bgx->qlm_mode = QLM_MODE_XLAUI_1X4;
859 dev_info(dev, "BGX%d QLM mode: XLAUI\n", bgx->bgx_id);
860 } else {
861 bgx->qlm_mode = QLM_MODE_40G_KR4_1X4;
862 dev_info(dev, "BGX%d QLM mode: 40G_KR4\n", bgx->bgx_id);
863 }
864 break;
865 default:
866 bgx->qlm_mode = QLM_MODE_SGMII;
867 dev_info(dev, "BGX%d QLM default mode: SGMII\n", bgx->bgx_id);
868 }
869}
870
46b903a0
DD		 871#ifdef CONFIG_ACPI
872
873static int acpi_get_mac_address(struct acpi_device *adev, u8 *dst)
874{
875 u8 mac[ETH_ALEN];
876 int ret;
877
878 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
879 "mac-address", mac, ETH_ALEN);
880 if (ret)
881 goto out;
882
883 if (!is_valid_ether_addr(mac)) {
884 ret = -EINVAL;
885 goto out;
886 }
887
888 memcpy(dst, mac, ETH_ALEN);
889out:
890 return ret;
891}
892
893/* Currently only sets the MAC address. */
894static acpi_status bgx_acpi_register_phy(acpi_handle handle,
895 u32 lvl, void *context, void **rv)
896{
897 struct bgx *bgx = context;
898 struct acpi_device *adev;
899
900 if (acpi_bus_get_device(handle, &adev))
901 goto out;
902
903 acpi_get_mac_address(adev, bgx->lmac[bgx->lmac_count].mac);
904
905 SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, &bgx->pdev->dev);
906
907 bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
908out:
909 bgx->lmac_count++;
910 return AE_OK;
911}
912
913static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
914 void *context, void **ret_val)
915{
916 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
917 struct bgx *bgx = context;
918 char bgx_sel[5];
919
920 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
921 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
922 pr_warn("Invalid link device\n");
923 return AE_OK;
924 }
925
926 if (strncmp(string.pointer, bgx_sel, 4))
927 return AE_OK;
928
929 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
930 bgx_acpi_register_phy, NULL, bgx, NULL);
931
932 kfree(string.pointer);
933 return AE_CTRL_TERMINATE;
934}
935
936static int bgx_init_acpi_phy(struct bgx *bgx)
937{
938 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
939 return 0;
940}
941
942#else
943
944static int bgx_init_acpi_phy(struct bgx *bgx)
945{
946 return -ENODEV;
947}
948
949#endif /* CONFIG_ACPI */
950
de387e11
RR		 951#if IS_ENABLED(CONFIG_OF_MDIO)
952
953static int bgx_init_of_phy(struct bgx *bgx)
4863dea3 954{
de387e11 955 struct device_node *np;
4863dea3
SG		 956 struct device_node *np_child;
957 u8 lmac = 0;
de387e11
RR		 958 char bgx_sel[5];
959 const char *mac;
4863dea3 960
de387e11
RR		 961 /* Get BGX node from DT */
962 snprintf(bgx_sel, 5, "bgx%d", bgx->bgx_id);
963 np = of_find_node_by_name(NULL, bgx_sel);
964 if (!np)
965 return -ENODEV;
4863dea3 966
de387e11
RR		 967 for_each_child_of_node(np, np_child) {
968 struct device_node *phy_np = of_parse_phandle(np_child,
969 "phy-handle", 0);
970 if (!phy_np)
971 continue;
972 bgx->lmac[lmac].phydev = of_phy_find_device(phy_np);
4863dea3
SG		 973
974 mac = of_get_mac_address(np_child);
975 if (mac)
976 ether_addr_copy(bgx->lmac[lmac].mac, mac);
977
978 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
979 bgx->lmac[lmac].lmacid = lmac;
980 lmac++;
8c387ebb
JL		 981 if (lmac == MAX_LMAC_PER_BGX) {
982 of_node_put(np_child);
4863dea3 983 break;
8c387ebb 984 }
4863dea3 985 }
de387e11
RR		 986 return 0;
987}
988
989#else
990
991static int bgx_init_of_phy(struct bgx *bgx)
992{
993 return -ENODEV;
994}
995
996#endif /* CONFIG_OF_MDIO */
997
998static int bgx_init_phy(struct bgx *bgx)
999{
46b903a0
DD		 1000 if (!acpi_disabled)
1001 return bgx_init_acpi_phy(bgx);
1002
de387e11 1003 return bgx_init_of_phy(bgx);
4863dea3
SG		 1004}
1005
1006static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1007{
1008 int err;
1009 struct device *dev = &pdev->dev;
1010 struct bgx *bgx = NULL;
4863dea3
SG		 1011 u8 lmac;
1012
723cda5b
TS		 1013 /* Load octeon mdio driver */
1014 octeon_mdiobus_force_mod_depencency();
1015
4863dea3
SG		 1016 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1017 if (!bgx)
1018 return -ENOMEM;
1019 bgx->pdev = pdev;
1020
1021 pci_set_drvdata(pdev, bgx);
1022
1023 err = pci_enable_device(pdev);
1024 if (err) {
1025 dev_err(dev, "Failed to enable PCI device\n");
1026 pci_set_drvdata(pdev, NULL);
1027 return err;
1028 }
1029
1030 err = pci_request_regions(pdev, DRV_NAME);
1031 if (err) {
1032 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1033 goto err_disable_device;
1034 }
1035
1036 /* MAP configuration registers */
1037 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1038 if (!bgx->reg_base) {
1039 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1040 err = -ENOMEM;
1041 goto err_release_regions;
1042 }
1043 bgx->bgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1;
d768b678
RR		 1044 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_CN88XX;
1045
4863dea3
SG		 1046 bgx_vnic[bgx->bgx_id] = bgx;
1047 bgx_get_qlm_mode(bgx);
1048
de387e11
RR		 1049 err = bgx_init_phy(bgx);
1050 if (err)
1051 goto err_enable;
4863dea3
SG		 1052
1053 bgx_init_hw(bgx);
1054
1055 /* Enable all LMACs */
1056 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1057 err = bgx_lmac_enable(bgx, lmac);
1058 if (err) {
1059 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1060 bgx->bgx_id, lmac);
1061 goto err_enable;
1062 }
1063 }
1064
1065 return 0;
1066
1067err_enable:
1068 bgx_vnic[bgx->bgx_id] = NULL;
1069err_release_regions:
1070 pci_release_regions(pdev);
1071err_disable_device:
1072 pci_disable_device(pdev);
1073 pci_set_drvdata(pdev, NULL);
1074 return err;
1075}
1076
1077static void bgx_remove(struct pci_dev *pdev)
1078{
1079 struct bgx *bgx = pci_get_drvdata(pdev);
1080 u8 lmac;
1081
1082 /* Disable all LMACs */
1083 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1084 bgx_lmac_disable(bgx, lmac);
1085
1086 bgx_vnic[bgx->bgx_id] = NULL;
1087 pci_release_regions(pdev);
1088 pci_disable_device(pdev);
1089 pci_set_drvdata(pdev, NULL);
1090}
1091
1092static struct pci_driver bgx_driver = {
1093 .name = DRV_NAME,
1094 .id_table = bgx_id_table,
1095 .probe = bgx_probe,
1096 .remove = bgx_remove,
1097};
1098
1099static int __init bgx_init_module(void)
1100{
1101 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1102
1103 return pci_register_driver(&bgx_driver);
1104}
1105
1106static void __exit bgx_cleanup_module(void)
1107{
1108 pci_unregister_driver(&bgx_driver);
1109}
1110
1111module_init(bgx_init_module);
1112module_exit(bgx_cleanup_module);
Ubuntu Hirsute Linux kernel mirror