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net: thunderx: Fix LMAC mode debug prints for QSGMII mode
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
46b903a0 9#include <linux/acpi.h>
4863dea3
SG		 10#include <linux/module.h>
11#include <linux/interrupt.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/phy.h>
16#include <linux/of.h>
17#include <linux/of_mdio.h>
18#include <linux/of_net.h>
19
20#include "nic_reg.h"
21#include "nic.h"
22#include "thunder_bgx.h"
23
24#define DRV_NAME "thunder-BGX"
25#define DRV_VERSION "1.0"
26
27struct lmac {
28 struct bgx *bgx;
29 int dmac;
46b903a0 30 u8 mac[ETH_ALEN];
0bcb7d51
SG		 31 u8 lmac_type;
32 u8 lane_to_sds;
33 bool use_training;
075ad765 34 bool autoneg;
4863dea3
SG		 35 bool link_up;
36 int lmacid; /* ID within BGX */
37 int lmacid_bd; /* ID on board */
38 struct net_device netdev;
39 struct phy_device *phydev;
40 unsigned int last_duplex;
41 unsigned int last_link;
42 unsigned int last_speed;
43 bool is_sgmii;
44 struct delayed_work dwork;
45 struct workqueue_struct *check_link;
0c886a1d 46};
4863dea3
SG		 47
48struct bgx {
49 u8 bgx_id;
4863dea3 50 struct lmac lmac[MAX_LMAC_PER_BGX];
7aa48655 51 u8 lmac_count;
6465859a 52 u8 max_lmac;
7aa48655 53 u8 acpi_lmac_idx;
4863dea3
SG		 54 void __iomem *reg_base;
55 struct pci_dev *pdev;
09de3917 56 bool is_dlm;
6465859a 57 bool is_rgx;
0c886a1d 58};
4863dea3 59
fd7ec062 60static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
4863dea3
SG		 61static int lmac_count; /* Total no of LMACs in system */
62
63static int bgx_xaui_check_link(struct lmac *lmac);
64
65/* Supported devices */
66static const struct pci_device_id bgx_id_table[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
6465859a 68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
4863dea3
SG		 69 { 0, } /* end of table */
70};
71
72MODULE_AUTHOR("Cavium Inc");
73MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
74MODULE_LICENSE("GPL v2");
75MODULE_VERSION(DRV_VERSION);
76MODULE_DEVICE_TABLE(pci, bgx_id_table);
77
78/* The Cavium ThunderX network controller can *only* be found in SoCs
79 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
80 * registers on this platform are implicitly strongly ordered with respect
81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
82 * with no memory barriers in this driver. The readq()/writeq() functions add
83 * explicit ordering operation which in this case are redundant, and only
84 * add overhead.
85 */
86
87/* Register read/write APIs */
88static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
89{
90 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
91
92 return readq_relaxed(addr);
93}
94
95static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
96{
97 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
98
99 writeq_relaxed(val, addr);
100}
101
102static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
103{
104 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
105
106 writeq_relaxed(val | readq_relaxed(addr), addr);
107}
108
109static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
110{
111 int timeout = 100;
112 u64 reg_val;
113
114 while (timeout) {
115 reg_val = bgx_reg_read(bgx, lmac, reg);
116 if (zero && !(reg_val & mask))
117 return 0;
118 if (!zero && (reg_val & mask))
119 return 0;
120 usleep_range(1000, 2000);
121 timeout--;
122 }
123 return 1;
124}
125
126/* Return number of BGX present in HW */
127unsigned bgx_get_map(int node)
128{
129 int i;
130 unsigned map = 0;
131
09de3917
SG		 132 for (i = 0; i < MAX_BGX_PER_NODE; i++) {
133 if (bgx_vnic[(node * MAX_BGX_PER_NODE) + i])
4863dea3
SG		 134 map |= (1 << i);
135 }
136
137 return map;
138}
139EXPORT_SYMBOL(bgx_get_map);
140
141/* Return number of LMAC configured for this BGX */
142int bgx_get_lmac_count(int node, int bgx_idx)
143{
144 struct bgx *bgx;
145
09de3917 146 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 147 if (bgx)
148 return bgx->lmac_count;
149
150 return 0;
151}
152EXPORT_SYMBOL(bgx_get_lmac_count);
153
154/* Returns the current link status of LMAC */
155void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
156{
157 struct bgx_link_status *link = (struct bgx_link_status *)status;
158 struct bgx *bgx;
159 struct lmac *lmac;
160
09de3917 161 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 162 if (!bgx)
163 return;
164
165 lmac = &bgx->lmac[lmacid];
1cc70259 166 link->mac_type = lmac->lmac_type;
4863dea3
SG		 167 link->link_up = lmac->link_up;
168 link->duplex = lmac->last_duplex;
169 link->speed = lmac->last_speed;
170}
171EXPORT_SYMBOL(bgx_get_lmac_link_state);
172
e610cb32 173const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
4863dea3 174{
09de3917 175 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 176
177 if (bgx)
178 return bgx->lmac[lmacid].mac;
179
180 return NULL;
181}
182EXPORT_SYMBOL(bgx_get_lmac_mac);
183
e610cb32 184void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
4863dea3 185{
09de3917 186 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 187
188 if (!bgx)
189 return;
190
191 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
192}
193EXPORT_SYMBOL(bgx_set_lmac_mac);
194
bc69fdfc
SG		 195void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
196{
09de3917 197 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
6465859a 198 struct lmac *lmac;
bc69fdfc
SG		 199 u64 cfg;
200
201 if (!bgx)
202 return;
6465859a 203 lmac = &bgx->lmac[lmacid];
bc69fdfc
SG		 204
205 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
206 if (enable)
207 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
208 else
209 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
210 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
6465859a
SG		 211
212 if (bgx->is_rgx)
213 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
bc69fdfc
SG		 214}
215EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
216
430da208
SG		 217void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
218{
219 struct pfc *pfc = (struct pfc *)pause;
220 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
221 struct lmac *lmac;
222 u64 cfg;
223
224 if (!bgx)
225 return;
226 lmac = &bgx->lmac[lmacid];
227 if (lmac->is_sgmii)
228 return;
229
230 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
231 pfc->fc_rx = cfg & RX_EN;
232 pfc->fc_tx = cfg & TX_EN;
233 pfc->autoneg = 0;
234}
235EXPORT_SYMBOL(bgx_lmac_get_pfc);
236
237void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
238{
239 struct pfc *pfc = (struct pfc *)pause;
240 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
241 struct lmac *lmac;
242 u64 cfg;
243
244 if (!bgx)
245 return;
246 lmac = &bgx->lmac[lmacid];
247 if (lmac->is_sgmii)
248 return;
249
250 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
251 cfg &= ~(RX_EN | TX_EN);
252 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
253 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
254 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
255}
256EXPORT_SYMBOL(bgx_lmac_set_pfc);
257
4863dea3
SG		 258static void bgx_sgmii_change_link_state(struct lmac *lmac)
259{
260 struct bgx *bgx = lmac->bgx;
261 u64 cmr_cfg;
262 u64 port_cfg = 0;
263 u64 misc_ctl = 0;
264
265 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
266 cmr_cfg &= ~CMR_EN;
267 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
268
269 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
270 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
271
272 if (lmac->link_up) {
273 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
274 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
275 port_cfg |= (lmac->last_duplex << 2);
276 } else {
277 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
278 }
279
280 switch (lmac->last_speed) {
281 case 10:
282 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
283 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
284 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
285 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
286 misc_ctl |= 50; /* samp_pt */
287 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
288 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
289 break;
290 case 100:
291 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
292 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
293 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
294 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
295 misc_ctl |= 5; /* samp_pt */
296 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
297 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
298 break;
299 case 1000:
300 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
301 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
302 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
303 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
304 misc_ctl |= 1; /* samp_pt */
305 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
306 if (lmac->last_duplex)
307 bgx_reg_write(bgx, lmac->lmacid,
308 BGX_GMP_GMI_TXX_BURST, 0);
309 else
310 bgx_reg_write(bgx, lmac->lmacid,
311 BGX_GMP_GMI_TXX_BURST, 8192);
312 break;
313 default:
314 break;
315 }
316 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
317 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
318
319 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
320
6465859a 321 /* Re-enable lmac */
4863dea3
SG		 322 cmr_cfg |= CMR_EN;
323 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
6465859a
SG		 324
325 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
326 xcv_setup_link(lmac->link_up, lmac->last_speed);
4863dea3
SG		 327}
328
fd7ec062 329static void bgx_lmac_handler(struct net_device *netdev)
4863dea3
SG		 330{
331 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
099a728d 332 struct phy_device *phydev;
4863dea3
SG		 333 int link_changed = 0;
334
335 if (!lmac)
336 return;
337
099a728d 338 phydev = lmac->phydev;
339
4863dea3
SG		 340 if (!phydev->link && lmac->last_link)
341 link_changed = -1;
342
343 if (phydev->link &&
344 (lmac->last_duplex != phydev->duplex ||
345 lmac->last_link != phydev->link ||
346 lmac->last_speed != phydev->speed)) {
347 link_changed = 1;
348 }
349
350 lmac->last_link = phydev->link;
351 lmac->last_speed = phydev->speed;
352 lmac->last_duplex = phydev->duplex;
353
354 if (!link_changed)
355 return;
356
357 if (link_changed > 0)
358 lmac->link_up = true;
359 else
360 lmac->link_up = false;
361
362 if (lmac->is_sgmii)
363 bgx_sgmii_change_link_state(lmac);
364 else
365 bgx_xaui_check_link(lmac);
366}
367
368u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
369{
370 struct bgx *bgx;
371
09de3917 372 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 373 if (!bgx)
374 return 0;
375
376 if (idx > 8)
377 lmac = 0;
378 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
379}
380EXPORT_SYMBOL(bgx_get_rx_stats);
381
382u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
383{
384 struct bgx *bgx;
385
09de3917 386 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
4863dea3
SG		 387 if (!bgx)
388 return 0;
389
390 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
391}
392EXPORT_SYMBOL(bgx_get_tx_stats);
393
394static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
395{
396 u64 offset;
397
398 while (bgx->lmac[lmac].dmac > 0) {
399 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
400 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
401 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
402 bgx->lmac[lmac].dmac--;
403 }
404}
405
d77a2384
SG		 406/* Configure BGX LMAC in internal loopback mode */
407void bgx_lmac_internal_loopback(int node, int bgx_idx,
408 int lmac_idx, bool enable)
409{
410 struct bgx *bgx;
411 struct lmac *lmac;
412 u64 cfg;
413
09de3917 414 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
d77a2384
SG		 415 if (!bgx)
416 return;
417
418 lmac = &bgx->lmac[lmac_idx];
419 if (lmac->is_sgmii) {
420 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
421 if (enable)
422 cfg |= PCS_MRX_CTL_LOOPBACK1;
423 else
424 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
425 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
426 } else {
427 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
428 if (enable)
429 cfg |= SPU_CTL_LOOPBACK;
430 else
431 cfg &= ~SPU_CTL_LOOPBACK;
432 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
433 }
434}
435EXPORT_SYMBOL(bgx_lmac_internal_loopback);
436
3f8057cf 437static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
4863dea3 438{
3f8057cf 439 int lmacid = lmac->lmacid;
4863dea3
SG		 440 u64 cfg;
441
442 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
443 /* max packet size */
444 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
445
446 /* Disable frame alignment if using preamble */
447 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
448 if (cfg & 1)
449 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
450
451 /* Enable lmac */
452 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
453
454 /* PCS reset */
455 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
456 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
457 PCS_MRX_CTL_RESET, true)) {
458 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
459 return -1;
460 }
461
462 /* power down, reset autoneg, autoneg enable */
463 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
464 cfg &= ~PCS_MRX_CTL_PWR_DN;
075ad765
TS		 465 cfg |= PCS_MRX_CTL_RST_AN;
466 if (lmac->phydev) {
467 cfg |= PCS_MRX_CTL_AN_EN;
468 } else {
469 /* In scenarios where PHY driver is not present or it's a
470 * non-standard PHY, FW sets AN_EN to inform Linux driver
471 * to do auto-neg and link polling or not.
472 */
473 if (cfg & PCS_MRX_CTL_AN_EN)
474 lmac->autoneg = true;
475 }
4863dea3
SG		 476 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
477
3f8057cf
SG		 478 if (lmac->lmac_type == BGX_MODE_QSGMII) {
479 /* Disable disparity check for QSGMII */
480 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
481 cfg &= ~PCS_MISC_CTL_DISP_EN;
482 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
483 return 0;
484 }
485
075ad765 486 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
6465859a
SG		 487 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
488 PCS_MRX_STATUS_AN_CPT, false)) {
489 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
490 return -1;
491 }
4863dea3
SG		 492 }
493
494 return 0;
495}
496
0bcb7d51 497static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
4863dea3
SG		 498{
499 u64 cfg;
0bcb7d51 500 int lmacid = lmac->lmacid;
4863dea3
SG		 501
502 /* Reset SPU */
503 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
504 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
505 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
506 return -1;
507 }
508
509 /* Disable LMAC */
510 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
511 cfg &= ~CMR_EN;
512 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
513
514 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
515 /* Set interleaved running disparity for RXAUI */
93db2cf8 516 if (lmac->lmac_type == BGX_MODE_RXAUI)
4863dea3 517 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
93db2cf8
SG		 518 SPU_MISC_CTL_INTLV_RDISP);
519
520 /* Clear receive packet disable */
521 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
522 cfg &= ~SPU_MISC_CTL_RX_DIS;
523 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
4863dea3
SG		 524
525 /* clear all interrupts */
526 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
527 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
528 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
529 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
530 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
531 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
532
0bcb7d51 533 if (lmac->use_training) {
4863dea3
SG		 534 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
535 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
536 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
537 /* training enable */
538 bgx_reg_modify(bgx, lmacid,
539 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
540 }
541
542 /* Append FCS to each packet */
543 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
544
545 /* Disable forward error correction */
546 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
547 cfg &= ~SPU_FEC_CTL_FEC_EN;
548 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
549
550 /* Disable autoneg */
551 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
552 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
553 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
554
555 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
0bcb7d51 556 if (lmac->lmac_type == BGX_MODE_10G_KR)
4863dea3 557 cfg |= (1 << 23);
0bcb7d51 558 else if (lmac->lmac_type == BGX_MODE_40G_KR)
4863dea3
SG		 559 cfg |= (1 << 24);
560 else
561 cfg &= ~((1 << 23) | (1 << 24));
562 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
563 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
564
565 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
566 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
567 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
568
569 /* Enable lmac */
570 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
571
572 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
573 cfg &= ~SPU_CTL_LOW_POWER;
574 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
575
576 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
577 cfg &= ~SMU_TX_CTL_UNI_EN;
578 cfg |= SMU_TX_CTL_DIC_EN;
579 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
580
430da208
SG		 581 /* Enable receive and transmission of pause frames */
582 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
583 BCK_EN | DRP_EN | TX_EN | RX_EN));
584 /* Configure pause time and interval */
585 bgx_reg_write(bgx, lmacid,
586 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
587 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
588 cfg &= ~0xFFFFull;
589 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
590 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
591 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
592
4863dea3
SG		 593 /* take lmac_count into account */
594 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
595 /* max packet size */
596 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
597
598 return 0;
599}
600
601static int bgx_xaui_check_link(struct lmac *lmac)
602{
603 struct bgx *bgx = lmac->bgx;
604 int lmacid = lmac->lmacid;
0bcb7d51 605 int lmac_type = lmac->lmac_type;
4863dea3
SG		 606 u64 cfg;
607
0bcb7d51 608 if (lmac->use_training) {
4863dea3
SG		 609 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
610 if (!(cfg & (1ull << 13))) {
611 cfg = (1ull << 13) | (1ull << 14);
612 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
613 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
614 cfg |= (1ull << 0);
615 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
616 return -1;
617 }
618 }
619
620 /* wait for PCS to come out of reset */
621 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
622 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
623 return -1;
624 }
625
626 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
627 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
628 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
629 SPU_BR_STATUS_BLK_LOCK, false)) {
630 dev_err(&bgx->pdev->dev,
631 "SPU_BR_STATUS_BLK_LOCK not completed\n");
632 return -1;
633 }
634 } else {
635 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
636 SPU_BX_STATUS_RX_ALIGN, false)) {
637 dev_err(&bgx->pdev->dev,
638 "SPU_BX_STATUS_RX_ALIGN not completed\n");
639 return -1;
640 }
641 }
642
643 /* Clear rcvflt bit (latching high) and read it back */
3f4c68cf
SG		 644 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
645 bgx_reg_modify(bgx, lmacid,
646 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
4863dea3
SG		 647 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
648 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
0bcb7d51 649 if (lmac->use_training) {
4863dea3
SG		 650 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
651 if (!(cfg & (1ull << 13))) {
652 cfg = (1ull << 13) | (1ull << 14);
653 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
654 cfg = bgx_reg_read(bgx, lmacid,
655 BGX_SPUX_BR_PMD_CRTL);
656 cfg |= (1ull << 0);
657 bgx_reg_write(bgx, lmacid,
658 BGX_SPUX_BR_PMD_CRTL, cfg);
659 return -1;
660 }
661 }
662 return -1;
663 }
664
4863dea3
SG		 665 /* Wait for BGX RX to be idle */
666 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
667 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
668 return -1;
669 }
670
671 /* Wait for BGX TX to be idle */
672 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
673 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
674 return -1;
675 }
676
3f4c68cf
SG		 677 /* Check for MAC RX faults */
678 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
679 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
680 cfg &= SMU_RX_CTL_STATUS;
681 if (!cfg)
682 return 0;
683
684 /* Rx local/remote fault seen.
685 * Do lmac reinit to see if condition recovers
686 */
0bcb7d51 687 bgx_lmac_xaui_init(bgx, lmac);
3f4c68cf
SG		 688
689 return -1;
4863dea3
SG		 690}
691
075ad765
TS		 692static void bgx_poll_for_sgmii_link(struct lmac *lmac)
693{
694 u64 pcs_link, an_result;
695 u8 speed;
696
697 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
698 BGX_GMP_PCS_MRX_STATUS);
699
700 /*Link state bit is sticky, read it again*/
701 if (!(pcs_link & PCS_MRX_STATUS_LINK))
702 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
703 BGX_GMP_PCS_MRX_STATUS);
704
705 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
706 PCS_MRX_STATUS_AN_CPT, false)) {
707 lmac->link_up = false;
708 lmac->last_speed = SPEED_UNKNOWN;
709 lmac->last_duplex = DUPLEX_UNKNOWN;
710 goto next_poll;
711 }
712
713 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
714 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
715 BGX_GMP_PCS_ANX_AN_RESULTS);
716
717 speed = (an_result >> 3) & 0x3;
718 lmac->last_duplex = (an_result >> 1) & 0x1;
719 switch (speed) {
720 case 0:
721 lmac->last_speed = 10;
722 break;
723 case 1:
724 lmac->last_speed = 100;
725 break;
726 case 2:
727 lmac->last_speed = 1000;
728 break;
729 default:
730 lmac->link_up = false;
731 lmac->last_speed = SPEED_UNKNOWN;
732 lmac->last_duplex = DUPLEX_UNKNOWN;
733 break;
734 }
735
736next_poll:
737
738 if (lmac->last_link != lmac->link_up) {
739 if (lmac->link_up)
740 bgx_sgmii_change_link_state(lmac);
741 lmac->last_link = lmac->link_up;
742 }
743
744 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
745}
746
4863dea3
SG		 747static void bgx_poll_for_link(struct work_struct *work)
748{
749 struct lmac *lmac;
3f4c68cf 750 u64 spu_link, smu_link;
4863dea3
SG		 751
752 lmac = container_of(work, struct lmac, dwork.work);
075ad765
TS		 753 if (lmac->is_sgmii) {
754 bgx_poll_for_sgmii_link(lmac);
755 return;
756 }
4863dea3
SG		 757
758 /* Receive link is latching low. Force it high and verify it */
759 bgx_reg_modify(lmac->bgx, lmac->lmacid,
760 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
761 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
762 SPU_STATUS1_RCV_LNK, false);
763
3f4c68cf
SG		 764 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
765 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
766
767 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
768 !(smu_link & SMU_RX_CTL_STATUS)) {
4863dea3 769 lmac->link_up = 1;
0bcb7d51 770 if (lmac->lmac_type == BGX_MODE_XLAUI)
4863dea3
SG		 771 lmac->last_speed = 40000;
772 else
773 lmac->last_speed = 10000;
774 lmac->last_duplex = 1;
775 } else {
776 lmac->link_up = 0;
0b72a9a1
SG		 777 lmac->last_speed = SPEED_UNKNOWN;
778 lmac->last_duplex = DUPLEX_UNKNOWN;
4863dea3
SG		 779 }
780
781 if (lmac->last_link != lmac->link_up) {
3f4c68cf
SG		 782 if (lmac->link_up) {
783 if (bgx_xaui_check_link(lmac)) {
784 /* Errors, clear link_up state */
785 lmac->link_up = 0;
786 lmac->last_speed = SPEED_UNKNOWN;
787 lmac->last_duplex = DUPLEX_UNKNOWN;
788 }
789 }
4863dea3 790 lmac->last_link = lmac->link_up;
4863dea3
SG		 791 }
792
793 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
794}
795
3f8057cf
SG		 796static int phy_interface_mode(u8 lmac_type)
797{
798 if (lmac_type == BGX_MODE_QSGMII)
799 return PHY_INTERFACE_MODE_QSGMII;
6465859a
SG		 800 if (lmac_type == BGX_MODE_RGMII)
801 return PHY_INTERFACE_MODE_RGMII;
3f8057cf
SG		 802
803 return PHY_INTERFACE_MODE_SGMII;
804}
805
4863dea3
SG		 806static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
807{
808 struct lmac *lmac;
809 u64 cfg;
810
811 lmac = &bgx->lmac[lmacid];
812 lmac->bgx = bgx;
813
3f8057cf 814 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
6465859a
SG		 815 (lmac->lmac_type == BGX_MODE_QSGMII) ||
816 (lmac->lmac_type == BGX_MODE_RGMII)) {
4863dea3 817 lmac->is_sgmii = 1;
3f8057cf 818 if (bgx_lmac_sgmii_init(bgx, lmac))
4863dea3
SG		 819 return -1;
820 } else {
821 lmac->is_sgmii = 0;
0bcb7d51 822 if (bgx_lmac_xaui_init(bgx, lmac))
4863dea3
SG		 823 return -1;
824 }
825
826 if (lmac->is_sgmii) {
827 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
828 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
829 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
830 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
831 } else {
832 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
833 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
834 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
835 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
836 }
837
838 /* Enable lmac */
bc69fdfc 839 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
4863dea3
SG		 840
841 /* Restore default cfg, incase low level firmware changed it */
842 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
843
0bcb7d51
SG		 844 if ((lmac->lmac_type != BGX_MODE_XFI) &&
845 (lmac->lmac_type != BGX_MODE_XLAUI) &&
846 (lmac->lmac_type != BGX_MODE_40G_KR) &&
847 (lmac->lmac_type != BGX_MODE_10G_KR)) {
075ad765
TS		 848 if (!lmac->phydev) {
849 if (lmac->autoneg) {
850 bgx_reg_write(bgx, lmacid,
851 BGX_GMP_PCS_LINKX_TIMER,
852 PCS_LINKX_TIMER_COUNT);
853 goto poll;
854 } else {
855 /* Default to below link speed and duplex */
856 lmac->link_up = true;
857 lmac->last_speed = 1000;
858 lmac->last_duplex = 1;
859 bgx_sgmii_change_link_state(lmac);
860 return 0;
861 }
862 }
4863dea3
SG		 863 lmac->phydev->dev_flags = 0;
864
865 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
866 bgx_lmac_handler,
3f8057cf 867 phy_interface_mode(lmac->lmac_type)))
4863dea3
SG		 868 return -ENODEV;
869
870 phy_start_aneg(lmac->phydev);
075ad765 871 return 0;
4863dea3
SG		 872 }
873
075ad765
TS		 874poll:
875 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
876 WQ_MEM_RECLAIM, 1);
877 if (!lmac->check_link)
878 return -ENOMEM;
879 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
880 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
881
4863dea3
SG		 882 return 0;
883}
884
fd7ec062 885static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 886{
887 struct lmac *lmac;
3f4c68cf 888 u64 cfg;
4863dea3
SG		 889
890 lmac = &bgx->lmac[lmacid];
891 if (lmac->check_link) {
892 /* Destroy work queue */
a7b1f535 893 cancel_delayed_work_sync(&lmac->dwork);
4863dea3
SG		 894 destroy_workqueue(lmac->check_link);
895 }
896
3f4c68cf
SG		 897 /* Disable packet reception */
898 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
899 cfg &= ~CMR_PKT_RX_EN;
900 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
901
902 /* Give chance for Rx/Tx FIFO to get drained */
903 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
904 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
905
906 /* Disable packet transmission */
907 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
908 cfg &= ~CMR_PKT_TX_EN;
909 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
910
911 /* Disable serdes lanes */
912 if (!lmac->is_sgmii)
913 bgx_reg_modify(bgx, lmacid,
914 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
915 else
916 bgx_reg_modify(bgx, lmacid,
917 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
918
919 /* Disable LMAC */
920 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
921 cfg &= ~CMR_EN;
922 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
923
4863dea3
SG		 924 bgx_flush_dmac_addrs(bgx, lmacid);
925
0bcb7d51
SG		 926 if ((lmac->lmac_type != BGX_MODE_XFI) &&
927 (lmac->lmac_type != BGX_MODE_XLAUI) &&
928 (lmac->lmac_type != BGX_MODE_40G_KR) &&
929 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
4863dea3
SG		 930 phy_disconnect(lmac->phydev);
931
932 lmac->phydev = NULL;
933}
934
4863dea3
SG		 935static void bgx_init_hw(struct bgx *bgx)
936{
937 int i;
0bcb7d51 938 struct lmac *lmac;
4863dea3
SG		 939
940 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
941 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
942 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
943
944 /* Set lmac type and lane2serdes mapping */
945 for (i = 0; i < bgx->lmac_count; i++) {
0bcb7d51 946 lmac = &bgx->lmac[i];
4863dea3 947 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
0bcb7d51 948 (lmac->lmac_type << 8) | lmac->lane_to_sds);
4863dea3
SG		 949 bgx->lmac[i].lmacid_bd = lmac_count;
950 lmac_count++;
951 }
952
953 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
954 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
955
956 /* Set the backpressure AND mask */
957 for (i = 0; i < bgx->lmac_count; i++)
958 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
959 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
960 (i * MAX_BGX_CHANS_PER_LMAC));
961
962 /* Disable all MAC filtering */
963 for (i = 0; i < RX_DMAC_COUNT; i++)
964 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
965
966 /* Disable MAC steering (NCSI traffic) */
967 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
968 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
969}
970
3f8057cf
SG		 971static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
972{
973 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
974}
975
0bcb7d51 976static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 977{
978 struct device *dev = &bgx->pdev->dev;
0bcb7d51
SG		 979 struct lmac *lmac;
980 char str[20];
57aaf63c 981
fff37fda 982 if (!bgx->is_dlm && lmacid)
57aaf63c 983 return;
4863dea3 984
0bcb7d51 985 lmac = &bgx->lmac[lmacid];
09de3917 986 if (!bgx->is_dlm)
57aaf63c
SG		 987 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
988 else
fff37fda 989 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid);
4863dea3 990
0bcb7d51 991 switch (lmac->lmac_type) {
4863dea3 992 case BGX_MODE_SGMII:
0bcb7d51 993 dev_info(dev, "%s: SGMII\n", (char *)str);
4863dea3
SG		 994 break;
995 case BGX_MODE_XAUI:
0bcb7d51 996 dev_info(dev, "%s: XAUI\n", (char *)str);
4863dea3
SG		 997 break;
998 case BGX_MODE_RXAUI:
0bcb7d51 999 dev_info(dev, "%s: RXAUI\n", (char *)str);
4863dea3
SG		 1000 break;
1001 case BGX_MODE_XFI:
0bcb7d51
SG		 1002 if (!lmac->use_training)
1003 dev_info(dev, "%s: XFI\n", (char *)str);
1004 else
1005 dev_info(dev, "%s: 10G_KR\n", (char *)str);
4863dea3
SG		 1006 break;
1007 case BGX_MODE_XLAUI:
0bcb7d51
SG		 1008 if (!lmac->use_training)
1009 dev_info(dev, "%s: XLAUI\n", (char *)str);
1010 else
1011 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
4863dea3 1012 break;
3f8057cf 1013 case BGX_MODE_QSGMII:
3f8057cf
SG		 1014 dev_info(dev, "%s: QSGMII\n", (char *)str);
1015 break;
6465859a
SG		 1016 case BGX_MODE_RGMII:
1017 dev_info(dev, "%s: RGMII\n", (char *)str);
1018 break;
3f8057cf
SG		 1019 case BGX_MODE_INVALID:
1020 /* Nothing to do */
1021 break;
4863dea3
SG		 1022 }
1023}
1024
3f8057cf 1025static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
0bcb7d51
SG		 1026{
1027 switch (lmac->lmac_type) {
1028 case BGX_MODE_SGMII:
1029 case BGX_MODE_XFI:
1030 lmac->lane_to_sds = lmac->lmacid;
1031 break;
1032 case BGX_MODE_XAUI:
1033 case BGX_MODE_XLAUI:
6465859a 1034 case BGX_MODE_RGMII:
0bcb7d51
SG		 1035 lmac->lane_to_sds = 0xE4;
1036 break;
1037 case BGX_MODE_RXAUI:
1038 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
1039 break;
3f8057cf
SG		 1040 case BGX_MODE_QSGMII:
1041 /* There is no way to determine if DLM0/2 is QSGMII or
1042 * DLM1/3 is configured to QSGMII as bootloader will
1043 * configure all LMACs, so take whatever is configured
1044 * by low level firmware.
1045 */
1046 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1047 break;
0bcb7d51
SG		 1048 default:
1049 lmac->lane_to_sds = 0;
1050 break;
1051 }
1052}
1053
6465859a
SG		 1054static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1055{
1056 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1057 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1058 lmac->use_training = 0;
1059 return;
1060 }
1061
1062 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1063 SPU_PMD_CRTL_TRAIN_EN;
1064}
1065
0bcb7d51
SG		 1066static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1067{
1068 struct lmac *lmac;
1069 u64 cmr_cfg;
57aaf63c
SG		 1070 u8 lmac_type;
1071 u8 lane_to_sds;
0bcb7d51
SG		 1072
1073 lmac = &bgx->lmac[idx];
0bcb7d51 1074
09de3917 1075 if (!bgx->is_dlm || bgx->is_rgx) {
57aaf63c
SG		 1076 /* Read LMAC0 type to figure out QLM mode
1077 * This is configured by low level firmware
1078 */
1079 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1080 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
6465859a
SG		 1081 if (bgx->is_rgx)
1082 lmac->lmac_type = BGX_MODE_RGMII;
1083 lmac_set_training(bgx, lmac, 0);
3f8057cf 1084 lmac_set_lane2sds(bgx, lmac);
57aaf63c
SG		 1085 return;
1086 }
1087
fff37fda
SG		 1088 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1089 * are possible and vary across boards. Also Kernel doesn't have
1090 * any way to identify board type/info and since firmware does,
1091 * just take lmac type and serdes lane config as is.
0bcb7d51 1092 */
fff37fda
SG		 1093 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1094 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1095 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1096 /* Check if config is reset value */
1097 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1098 lmac->lmac_type = BGX_MODE_INVALID;
1099 else
1100 lmac->lmac_type = lmac_type;
1101 lmac->lane_to_sds = lane_to_sds;
1102 lmac_set_training(bgx, lmac, lmac->lmacid);
0bcb7d51
SG		 1103}
1104
1105static void bgx_get_qlm_mode(struct bgx *bgx)
1106{
57aaf63c 1107 struct lmac *lmac;
0bcb7d51
SG		 1108 u8 idx;
1109
57aaf63c 1110 /* Init all LMAC's type to invalid */
6465859a 1111 for (idx = 0; idx < bgx->max_lmac; idx++) {
57aaf63c 1112 lmac = &bgx->lmac[idx];
57aaf63c 1113 lmac->lmacid = idx;
6465859a
SG		 1114 lmac->lmac_type = BGX_MODE_INVALID;
1115 lmac->use_training = false;
57aaf63c
SG		 1116 }
1117
0bcb7d51
SG		 1118 /* It is assumed that low level firmware sets this value */
1119 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
6465859a
SG		 1120 if (bgx->lmac_count > bgx->max_lmac)
1121 bgx->lmac_count = bgx->max_lmac;
0bcb7d51 1122
57aaf63c 1123 for (idx = 0; idx < bgx->lmac_count; idx++) {
fff37fda
SG		 1124 bgx_set_lmac_config(bgx, idx);
1125 bgx_print_qlm_mode(bgx, idx);
57aaf63c 1126 }
0bcb7d51
SG		 1127}
1128
46b903a0
DD		 1129#ifdef CONFIG_ACPI
1130
1d82efac
RR		 1131static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1132 u8 *dst)
46b903a0
DD		 1133{
1134 u8 mac[ETH_ALEN];
1135 int ret;
1136
1137 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1138 "mac-address", mac, ETH_ALEN);
1139 if (ret)
1140 goto out;
1141
1142 if (!is_valid_ether_addr(mac)) {
1d82efac 1143 dev_err(dev, "MAC address invalid: %pM\n", mac);
46b903a0
DD		 1144 ret = -EINVAL;
1145 goto out;
1146 }
1147
1d82efac
RR		 1148 dev_info(dev, "MAC address set to: %pM\n", mac);
1149
46b903a0
DD		 1150 memcpy(dst, mac, ETH_ALEN);
1151out:
1152 return ret;
1153}
1154
1155/* Currently only sets the MAC address. */
1156static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1157 u32 lvl, void *context, void **rv)
1158{
1159 struct bgx *bgx = context;
1d82efac 1160 struct device *dev = &bgx->pdev->dev;
46b903a0
DD		 1161 struct acpi_device *adev;
1162
1163 if (acpi_bus_get_device(handle, &adev))
1164 goto out;
1165
7aa48655 1166 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
46b903a0 1167
7aa48655 1168 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
46b903a0 1169
7aa48655
VL		 1170 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1171 bgx->acpi_lmac_idx++; /* move to next LMAC */
46b903a0 1172out:
46b903a0
DD		 1173 return AE_OK;
1174}
1175
1176static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1177 void *context, void **ret_val)
1178{
1179 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1180 struct bgx *bgx = context;
1181 char bgx_sel[5];
1182
1183 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1184 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1185 pr_warn("Invalid link device\n");
1186 return AE_OK;
1187 }
1188
1189 if (strncmp(string.pointer, bgx_sel, 4))
1190 return AE_OK;
1191
1192 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1193 bgx_acpi_register_phy, NULL, bgx, NULL);
1194
1195 kfree(string.pointer);
1196 return AE_CTRL_TERMINATE;
1197}
1198
1199static int bgx_init_acpi_phy(struct bgx *bgx)
1200{
1201 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1202 return 0;
1203}
1204
1205#else
1206
1207static int bgx_init_acpi_phy(struct bgx *bgx)
1208{
1209 return -ENODEV;
1210}
1211
1212#endif /* CONFIG_ACPI */
1213
de387e11
RR		 1214#if IS_ENABLED(CONFIG_OF_MDIO)
1215
1216static int bgx_init_of_phy(struct bgx *bgx)
4863dea3 1217{
eee326fd 1218 struct fwnode_handle *fwn;
b7d3e3d3 1219 struct device_node *node = NULL;
4863dea3
SG		 1220 u8 lmac = 0;
1221
eee326fd 1222 device_for_each_child_node(&bgx->pdev->dev, fwn) {
5fc7cf17 1223 struct phy_device *pd;
eee326fd 1224 struct device_node *phy_np;
b7d3e3d3 1225 const char *mac;
eee326fd 1226
5fc7cf17
DD		 1227 /* Should always be an OF node. But if it is not, we
1228 * cannot handle it, so exit the loop.
eee326fd 1229 */
b7d3e3d3 1230 node = to_of_node(fwn);
eee326fd
DD		 1231 if (!node)
1232 break;
4863dea3 1233
eee326fd 1234 mac = of_get_mac_address(node);
4863dea3
SG		 1235 if (mac)
1236 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1237
1238 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1239 bgx->lmac[lmac].lmacid = lmac;
5fc7cf17
DD		 1240
1241 phy_np = of_parse_phandle(node, "phy-handle", 0);
1242 /* If there is no phy or defective firmware presents
1243 * this cortina phy, for which there is no driver
1244 * support, ignore it.
1245 */
1246 if (phy_np &&
1247 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1248 /* Wait until the phy drivers are available */
1249 pd = of_phy_find_device(phy_np);
1250 if (!pd)
b7d3e3d3 1251 goto defer;
5fc7cf17
DD		 1252 bgx->lmac[lmac].phydev = pd;
1253 }
1254
4863dea3 1255 lmac++;
6465859a 1256 if (lmac == bgx->max_lmac) {
65c66af6 1257 of_node_put(node);
4863dea3 1258 break;
65c66af6 1259 }
4863dea3 1260 }
de387e11 1261 return 0;
b7d3e3d3
DD		 1262
1263defer:
1264 /* We are bailing out, try not to leak device reference counts
1265 * for phy devices we may have already found.
1266 */
1267 while (lmac) {
1268 if (bgx->lmac[lmac].phydev) {
1269 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1270 bgx->lmac[lmac].phydev = NULL;
1271 }
1272 lmac--;
1273 }
1274 of_node_put(node);
1275 return -EPROBE_DEFER;
de387e11
RR		 1276}
1277
1278#else
1279
1280static int bgx_init_of_phy(struct bgx *bgx)
1281{
1282 return -ENODEV;
1283}
1284
1285#endif /* CONFIG_OF_MDIO */
1286
1287static int bgx_init_phy(struct bgx *bgx)
1288{
46b903a0
DD		 1289 if (!acpi_disabled)
1290 return bgx_init_acpi_phy(bgx);
1291
de387e11 1292 return bgx_init_of_phy(bgx);
4863dea3
SG		 1293}
1294
1295static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1296{
1297 int err;
1298 struct device *dev = &pdev->dev;
1299 struct bgx *bgx = NULL;
4863dea3 1300 u8 lmac;
57aaf63c 1301 u16 sdevid;
4863dea3
SG		 1302
1303 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1304 if (!bgx)
1305 return -ENOMEM;
1306 bgx->pdev = pdev;
1307
1308 pci_set_drvdata(pdev, bgx);
1309
1310 err = pci_enable_device(pdev);
1311 if (err) {
1312 dev_err(dev, "Failed to enable PCI device\n");
1313 pci_set_drvdata(pdev, NULL);
1314 return err;
1315 }
1316
1317 err = pci_request_regions(pdev, DRV_NAME);
1318 if (err) {
1319 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1320 goto err_disable_device;
1321 }
1322
1323 /* MAP configuration registers */
1324 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1325 if (!bgx->reg_base) {
1326 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1327 err = -ENOMEM;
1328 goto err_release_regions;
1329 }
d768b678 1330
6465859a
SG		 1331 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1332 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
612e94bd
RMC		 1333 bgx->bgx_id = (pci_resource_start(pdev,
1334 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
09de3917 1335 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;
6465859a
SG		 1336 bgx->max_lmac = MAX_LMAC_PER_BGX;
1337 bgx_vnic[bgx->bgx_id] = bgx;
1338 } else {
1339 bgx->is_rgx = true;
1340 bgx->max_lmac = 1;
1341 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1342 bgx_vnic[bgx->bgx_id] = bgx;
1343 xcv_init_hw();
1344 }
1345
09de3917
SG		 1346 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1347 * BGX i.e BGX2 can be split across 2 DLMs.
1348 */
1349 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1350 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1351 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1352 bgx->is_dlm = true;
1353
4863dea3
SG		 1354 bgx_get_qlm_mode(bgx);
1355
de387e11
RR		 1356 err = bgx_init_phy(bgx);
1357 if (err)
1358 goto err_enable;
4863dea3
SG		 1359
1360 bgx_init_hw(bgx);
1361
1362 /* Enable all LMACs */
1363 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1364 err = bgx_lmac_enable(bgx, lmac);
1365 if (err) {
1366 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1367 bgx->bgx_id, lmac);
57aaf63c
SG		 1368 while (lmac)
1369 bgx_lmac_disable(bgx, --lmac);
4863dea3
SG		 1370 goto err_enable;
1371 }
1372 }
1373
1374 return 0;
1375
1376err_enable:
1377 bgx_vnic[bgx->bgx_id] = NULL;
1378err_release_regions:
1379 pci_release_regions(pdev);
1380err_disable_device:
1381 pci_disable_device(pdev);
1382 pci_set_drvdata(pdev, NULL);
1383 return err;
1384}
1385
1386static void bgx_remove(struct pci_dev *pdev)
1387{
1388 struct bgx *bgx = pci_get_drvdata(pdev);
1389 u8 lmac;
1390
1391 /* Disable all LMACs */
1392 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1393 bgx_lmac_disable(bgx, lmac);
1394
1395 bgx_vnic[bgx->bgx_id] = NULL;
1396 pci_release_regions(pdev);
1397 pci_disable_device(pdev);
1398 pci_set_drvdata(pdev, NULL);
1399}
1400
1401static struct pci_driver bgx_driver = {
1402 .name = DRV_NAME,
1403 .id_table = bgx_id_table,
1404 .probe = bgx_probe,
1405 .remove = bgx_remove,
1406};
1407
1408static int __init bgx_init_module(void)
1409{
1410 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1411
1412 return pci_register_driver(&bgx_driver);
1413}
1414
1415static void __exit bgx_cleanup_module(void)
1416{
1417 pci_unregister_driver(&bgx_driver);
1418}
1419
1420module_init(bgx_init_module);
1421module_exit(bgx_cleanup_module);
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