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Replace <asm/uaccess.h> with <linux/uaccess.h> globally
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / chelsio / cxgb3 / cxgb3_main.c
CommitLineData
4d22de3e 1/*
a02d44a0 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
428ac43f
JP		 32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
4d22de3e
DLR		 35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/if_vlan.h>
0f07c4ee 43#include <linux/mdio.h>
4d22de3e
DLR		 44#include <linux/sockios.h>
45#include <linux/workqueue.h>
46#include <linux/proc_fs.h>
47#include <linux/rtnetlink.h>
2e283962 48#include <linux/firmware.h>
d9da466a 49#include <linux/log2.h>
34336ec0 50#include <linux/stringify.h>
e998f245 51#include <linux/sched.h>
5a0e3ad6 52#include <linux/slab.h>
7c0f6ba6 53#include <linux/uaccess.h>
4d22de3e
DLR		 54
55#include "common.h"
56#include "cxgb3_ioctl.h"
57#include "regs.h"
58#include "cxgb3_offload.h"
59#include "version.h"
60
61#include "cxgb3_ctl_defs.h"
62#include "t3_cpl.h"
63#include "firmware_exports.h"
64
65enum {
66 MAX_TXQ_ENTRIES = 16384,
67 MAX_CTRL_TXQ_ENTRIES = 1024,
68 MAX_RSPQ_ENTRIES = 16384,
69 MAX_RX_BUFFERS = 16384,
70 MAX_RX_JUMBO_BUFFERS = 16384,
71 MIN_TXQ_ENTRIES = 4,
72 MIN_CTRL_TXQ_ENTRIES = 4,
73 MIN_RSPQ_ENTRIES = 32,
74 MIN_FL_ENTRIES = 32
75};
76
77#define PORT_MASK ((1 << MAX_NPORTS) - 1)
78
79#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
80 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
81 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
82
83#define EEPROM_MAGIC 0x38E2F10C
84
678771d6
DLR		 85#define CH_DEVICE(devid, idx) \
86 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
4d22de3e 87
9baa3c34 88static const struct pci_device_id cxgb3_pci_tbl[] = {
678771d6
DLR		 89 CH_DEVICE(0x20, 0), /* PE9000 */
90 CH_DEVICE(0x21, 1), /* T302E */
91 CH_DEVICE(0x22, 2), /* T310E */
92 CH_DEVICE(0x23, 3), /* T320X */
93 CH_DEVICE(0x24, 1), /* T302X */
94 CH_DEVICE(0x25, 3), /* T320E */
95 CH_DEVICE(0x26, 2), /* T310X */
96 CH_DEVICE(0x30, 2), /* T3B10 */
97 CH_DEVICE(0x31, 3), /* T3B20 */
98 CH_DEVICE(0x32, 1), /* T3B02 */
ce03aadd 99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
74451424
DLR		 100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
4d22de3e
DLR		 102 {0,}
103};
104
105MODULE_DESCRIPTION(DRV_DESC);
106MODULE_AUTHOR("Chelsio Communications");
1d68e93d 107MODULE_LICENSE("Dual BSD/GPL");
4d22de3e
DLR		 108MODULE_VERSION(DRV_VERSION);
109MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
110
111static int dflt_msg_enable = DFLT_MSG_ENABLE;
112
113module_param(dflt_msg_enable, int, 0644);
114MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
115
116/*
117 * The driver uses the best interrupt scheme available on a platform in the
118 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
119 * of these schemes the driver may consider as follows:
120 *
121 * msi = 2: choose from among all three options
122 * msi = 1: only consider MSI and pin interrupts
123 * msi = 0: force pin interrupts
124 */
125static int msi = 2;
126
127module_param(msi, int, 0644);
128MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
129
130/*
131 * The driver enables offload as a default.
132 * To disable it, use ofld_disable = 1.
133 */
134
135static int ofld_disable = 0;
136
137module_param(ofld_disable, int, 0644);
138MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
139
140/*
141 * We have work elements that we need to cancel when an interface is taken
142 * down. Normally the work elements would be executed by keventd but that
143 * can deadlock because of linkwatch. If our close method takes the rtnl
144 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
145 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
146 * for our work to complete. Get our own work queue to solve this.
147 */
e998f245 148struct workqueue_struct *cxgb3_wq;
4d22de3e
DLR		 149
150/**
151 * link_report - show link status and link speed/duplex
152 * @p: the port whose settings are to be reported
153 *
154 * Shows the link status, speed, and duplex of a port.
155 */
156static void link_report(struct net_device *dev)
157{
158 if (!netif_carrier_ok(dev))
428ac43f 159 netdev_info(dev, "link down\n");
4d22de3e
DLR		 160 else {
161 const char *s = "10Mbps";
162 const struct port_info *p = netdev_priv(dev);
163
164 switch (p->link_config.speed) {
165 case SPEED_10000:
166 s = "10Gbps";
167 break;
168 case SPEED_1000:
169 s = "1000Mbps";
170 break;
171 case SPEED_100:
172 s = "100Mbps";
173 break;
174 }
175
428ac43f
JP		 176 netdev_info(dev, "link up, %s, %s-duplex\n",
177 s, p->link_config.duplex == DUPLEX_FULL
178 ? "full" : "half");
4d22de3e
DLR		 179 }
180}
181
34701fde
DLR		 182static void enable_tx_fifo_drain(struct adapter *adapter,
183 struct port_info *pi)
184{
185 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 0,
186 F_ENDROPPKT);
187 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0);
188 t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN);
189 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN);
190}
191
192static void disable_tx_fifo_drain(struct adapter *adapter,
193 struct port_info *pi)
194{
195 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset,
196 F_ENDROPPKT, 0);
197}
198
bf792094
DLR		 199void t3_os_link_fault(struct adapter *adap, int port_id, int state)
200{
201 struct net_device *dev = adap->port[port_id];
202 struct port_info *pi = netdev_priv(dev);
203
204 if (state == netif_carrier_ok(dev))
205 return;
206
207 if (state) {
208 struct cmac *mac = &pi->mac;
209
210 netif_carrier_on(dev);
211
34701fde
DLR		 212 disable_tx_fifo_drain(adap, pi);
213
bf792094
DLR		 214 /* Clear local faults */
215 t3_xgm_intr_disable(adap, pi->port_id);
216 t3_read_reg(adap, A_XGM_INT_STATUS +
217 pi->mac.offset);
218 t3_write_reg(adap,
219 A_XGM_INT_CAUSE + pi->mac.offset,
220 F_XGM_INT);
221
222 t3_set_reg_field(adap,
223 A_XGM_INT_ENABLE +
224 pi->mac.offset,
225 F_XGM_INT, F_XGM_INT);
226 t3_xgm_intr_enable(adap, pi->port_id);
227
228 t3_mac_enable(mac, MAC_DIRECTION_TX);
34701fde 229 } else {
bf792094
DLR		 230 netif_carrier_off(dev);
231
34701fde
DLR		 232 /* Flush TX FIFO */
233 enable_tx_fifo_drain(adap, pi);
234 }
bf792094
DLR		 235 link_report(dev);
236}
237
4d22de3e
DLR		 238/**
239 * t3_os_link_changed - handle link status changes
240 * @adapter: the adapter associated with the link change
241 * @port_id: the port index whose limk status has changed
242 * @link_stat: the new status of the link
243 * @speed: the new speed setting
244 * @duplex: the new duplex setting
245 * @pause: the new flow-control setting
246 *
247 * This is the OS-dependent handler for link status changes. The OS
248 * neutral handler takes care of most of the processing for these events,
249 * then calls this handler for any OS-specific processing.
250 */
251void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
252 int speed, int duplex, int pause)
253{
254 struct net_device *dev = adapter->port[port_id];
6d6dabac
DLR		 255 struct port_info *pi = netdev_priv(dev);
256 struct cmac *mac = &pi->mac;
4d22de3e
DLR		 257
258 /* Skip changes from disabled ports. */
259 if (!netif_running(dev))
260 return;
261
262 if (link_stat != netif_carrier_ok(dev)) {
6d6dabac 263 if (link_stat) {
34701fde
DLR		 264 disable_tx_fifo_drain(adapter, pi);
265
59cf8107 266 t3_mac_enable(mac, MAC_DIRECTION_RX);
bf792094
DLR		 267
268 /* Clear local faults */
269 t3_xgm_intr_disable(adapter, pi->port_id);
270 t3_read_reg(adapter, A_XGM_INT_STATUS +
271 pi->mac.offset);
272 t3_write_reg(adapter,
273 A_XGM_INT_CAUSE + pi->mac.offset,
274 F_XGM_INT);
275
276 t3_set_reg_field(adapter,
277 A_XGM_INT_ENABLE + pi->mac.offset,
278 F_XGM_INT, F_XGM_INT);
279 t3_xgm_intr_enable(adapter, pi->port_id);
280
4d22de3e 281 netif_carrier_on(dev);
6d6dabac 282 } else {
4d22de3e 283 netif_carrier_off(dev);
bf792094
DLR		 284
285 t3_xgm_intr_disable(adapter, pi->port_id);
286 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
287 t3_set_reg_field(adapter,
288 A_XGM_INT_ENABLE + pi->mac.offset,
289 F_XGM_INT, 0);
290
291 if (is_10G(adapter))
292 pi->phy.ops->power_down(&pi->phy, 1);
293
294 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
59cf8107
DLR		 295 t3_mac_disable(mac, MAC_DIRECTION_RX);
296 t3_link_start(&pi->phy, mac, &pi->link_config);
34701fde
DLR		 297
298 /* Flush TX FIFO */
299 enable_tx_fifo_drain(adapter, pi);
6d6dabac
DLR		 300 }
301
4d22de3e
DLR		 302 link_report(dev);
303 }
304}
305
1e882025
DLR		 306/**
307 * t3_os_phymod_changed - handle PHY module changes
308 * @phy: the PHY reporting the module change
309 * @mod_type: new module type
310 *
311 * This is the OS-dependent handler for PHY module changes. It is
312 * invoked when a PHY module is removed or inserted for any OS-specific
313 * processing.
314 */
315void t3_os_phymod_changed(struct adapter *adap, int port_id)
316{
317 static const char *mod_str[] = {
318 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
319 };
320
321 const struct net_device *dev = adap->port[port_id];
322 const struct port_info *pi = netdev_priv(dev);
323
324 if (pi->phy.modtype == phy_modtype_none)
428ac43f 325 netdev_info(dev, "PHY module unplugged\n");
1e882025 326 else
428ac43f
JP		 327 netdev_info(dev, "%s PHY module inserted\n",
328 mod_str[pi->phy.modtype]);
1e882025
DLR		 329}
330
4d22de3e
DLR		 331static void cxgb_set_rxmode(struct net_device *dev)
332{
4d22de3e
DLR		 333 struct port_info *pi = netdev_priv(dev);
334
0988d269 335 t3_mac_set_rx_mode(&pi->mac, dev);
4d22de3e
DLR		 336}
337
338/**
339 * link_start - enable a port
340 * @dev: the device to enable
341 *
342 * Performs the MAC and PHY actions needed to enable a port.
343 */
344static void link_start(struct net_device *dev)
345{
4d22de3e
DLR		 346 struct port_info *pi = netdev_priv(dev);
347 struct cmac *mac = &pi->mac;
348
4d22de3e 349 t3_mac_reset(mac);
f14d42f3 350 t3_mac_set_num_ucast(mac, MAX_MAC_IDX);
4d22de3e 351 t3_mac_set_mtu(mac, dev->mtu);
f14d42f3
KX		 352 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
353 t3_mac_set_address(mac, SAN_MAC_IDX, pi->iscsic.mac_addr);
0988d269 354 t3_mac_set_rx_mode(mac, dev);
4d22de3e
DLR		 355 t3_link_start(&pi->phy, mac, &pi->link_config);
356 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
357}
358
359static inline void cxgb_disable_msi(struct adapter *adapter)
360{
361 if (adapter->flags & USING_MSIX) {
362 pci_disable_msix(adapter->pdev);
363 adapter->flags &= ~USING_MSIX;
364 } else if (adapter->flags & USING_MSI) {
365 pci_disable_msi(adapter->pdev);
366 adapter->flags &= ~USING_MSI;
367 }
368}
369
370/*
371 * Interrupt handler for asynchronous events used with MSI-X.
372 */
373static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
374{
375 t3_slow_intr_handler(cookie);
376 return IRQ_HANDLED;
377}
378
379/*
380 * Name the MSI-X interrupts.
381 */
382static void name_msix_vecs(struct adapter *adap)
383{
384 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
385
386 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
387 adap->msix_info[0].desc[n] = 0;
388
389 for_each_port(adap, j) {
390 struct net_device *d = adap->port[j];
391 const struct port_info *pi = netdev_priv(d);
392
393 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
394 snprintf(adap->msix_info[msi_idx].desc, n,
8c263761 395 "%s-%d", d->name, pi->first_qset + i);
4d22de3e
DLR		 396 adap->msix_info[msi_idx].desc[n] = 0;
397 }
8c263761 398 }
4d22de3e
DLR		 399}
400
401static int request_msix_data_irqs(struct adapter *adap)
402{
403 int i, j, err, qidx = 0;
404
405 for_each_port(adap, i) {
406 int nqsets = adap2pinfo(adap, i)->nqsets;
407
408 for (j = 0; j < nqsets; ++j) {
409 err = request_irq(adap->msix_info[qidx + 1].vec,
410 t3_intr_handler(adap,
411 adap->sge.qs[qidx].
412 rspq.polling), 0,
413 adap->msix_info[qidx + 1].desc,
414 &adap->sge.qs[qidx]);
415 if (err) {
416 while (--qidx >= 0)
417 free_irq(adap->msix_info[qidx + 1].vec,
418 &adap->sge.qs[qidx]);
419 return err;
420 }
421 qidx++;
422 }
423 }
424 return 0;
425}
426
8c263761
DLR		 427static void free_irq_resources(struct adapter *adapter)
428{
429 if (adapter->flags & USING_MSIX) {
430 int i, n = 0;
431
432 free_irq(adapter->msix_info[0].vec, adapter);
433 for_each_port(adapter, i)
5cda9364 434 n += adap2pinfo(adapter, i)->nqsets;
8c263761
DLR		 435
436 for (i = 0; i < n; ++i)
437 free_irq(adapter->msix_info[i + 1].vec,
438 &adapter->sge.qs[i]);
439 } else
440 free_irq(adapter->pdev->irq, adapter);
441}
442
b881955b
DLR		 443static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
444 unsigned long n)
445{
e95ef5d3 446 int attempts = 10;
b881955b
DLR		 447
448 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
449 if (!--attempts)
450 return -ETIMEDOUT;
451 msleep(10);
452 }
453 return 0;
454}
455
456static int init_tp_parity(struct adapter *adap)
457{
458 int i;
459 struct sk_buff *skb;
460 struct cpl_set_tcb_field *greq;
461 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
462
463 t3_tp_set_offload_mode(adap, 1);
464
465 for (i = 0; i < 16; i++) {
466 struct cpl_smt_write_req *req;
467
74b793e1
DLR		 468 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
469 if (!skb)
470 skb = adap->nofail_skb;
471 if (!skb)
472 goto alloc_skb_fail;
473
b881955b
DLR		 474 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
475 memset(req, 0, sizeof(*req));
476 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
477 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
dce7d1d0 478 req->mtu_idx = NMTUS - 1;
b881955b
DLR		 479 req->iff = i;
480 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 481 if (skb == adap->nofail_skb) {
482 await_mgmt_replies(adap, cnt, i + 1);
483 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
484 if (!adap->nofail_skb)
485 goto alloc_skb_fail;
486 }
b881955b
DLR		 487 }
488
489 for (i = 0; i < 2048; i++) {
490 struct cpl_l2t_write_req *req;
491
74b793e1
DLR		 492 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
493 if (!skb)
494 skb = adap->nofail_skb;
495 if (!skb)
496 goto alloc_skb_fail;
497
b881955b
DLR		 498 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
499 memset(req, 0, sizeof(*req));
500 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
501 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
502 req->params = htonl(V_L2T_W_IDX(i));
503 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 504 if (skb == adap->nofail_skb) {
505 await_mgmt_replies(adap, cnt, 16 + i + 1);
506 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
507 if (!adap->nofail_skb)
508 goto alloc_skb_fail;
509 }
b881955b
DLR		 510 }
511
512 for (i = 0; i < 2048; i++) {
513 struct cpl_rte_write_req *req;
514
74b793e1
DLR		 515 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
516 if (!skb)
517 skb = adap->nofail_skb;
518 if (!skb)
519 goto alloc_skb_fail;
520
b881955b
DLR		 521 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
522 memset(req, 0, sizeof(*req));
523 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
524 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
525 req->l2t_idx = htonl(V_L2T_W_IDX(i));
526 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 527 if (skb == adap->nofail_skb) {
528 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
529 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
530 if (!adap->nofail_skb)
531 goto alloc_skb_fail;
532 }
b881955b
DLR		 533 }
534
74b793e1
DLR		 535 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
536 if (!skb)
537 skb = adap->nofail_skb;
538 if (!skb)
539 goto alloc_skb_fail;
540
b881955b
DLR		 541 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
542 memset(greq, 0, sizeof(*greq));
543 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
544 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
545 greq->mask = cpu_to_be64(1);
546 t3_mgmt_tx(adap, skb);
547
548 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
74b793e1
DLR		 549 if (skb == adap->nofail_skb) {
550 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
551 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
552 }
553
b881955b
DLR		 554 t3_tp_set_offload_mode(adap, 0);
555 return i;
74b793e1
DLR		 556
557alloc_skb_fail:
558 t3_tp_set_offload_mode(adap, 0);
559 return -ENOMEM;
b881955b
DLR		 560}
561
4d22de3e
DLR		 562/**
563 * setup_rss - configure RSS
564 * @adap: the adapter
565 *
566 * Sets up RSS to distribute packets to multiple receive queues. We
567 * configure the RSS CPU lookup table to distribute to the number of HW
568 * receive queues, and the response queue lookup table to narrow that
569 * down to the response queues actually configured for each port.
570 * We always configure the RSS mapping for two ports since the mapping
571 * table has plenty of entries.
572 */
573static void setup_rss(struct adapter *adap)
574{
575 int i;
576 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
577 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
578 u8 cpus[SGE_QSETS + 1];
0b86a2a1 579 u16 rspq_map[RSS_TABLE_SIZE + 1];
4d22de3e
DLR		 580
581 for (i = 0; i < SGE_QSETS; ++i)
582 cpus[i] = i;
583 cpus[SGE_QSETS] = 0xff; /* terminator */
584
585 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
586 rspq_map[i] = i % nq0;
587 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
588 }
0b86a2a1 589 rspq_map[RSS_TABLE_SIZE] = 0xffff; /* terminator */
4d22de3e
DLR		 590
591 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
592 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
a2604be5 593 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
4d22de3e
DLR		 594}
595
e998f245
SW		 596static void ring_dbs(struct adapter *adap)
597{
598 int i, j;
599
600 for (i = 0; i < SGE_QSETS; i++) {
601 struct sge_qset *qs = &adap->sge.qs[i];
602
603 if (qs->adap)
604 for (j = 0; j < SGE_TXQ_PER_SET; j++)
605 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(qs->txq[j].cntxt_id));
606 }
607}
608
bea3348e 609static void init_napi(struct adapter *adap)
4d22de3e 610{
bea3348e 611 int i;
4d22de3e 612
bea3348e
SH		 613 for (i = 0; i < SGE_QSETS; i++) {
614 struct sge_qset *qs = &adap->sge.qs[i];
4d22de3e 615
bea3348e
SH		 616 if (qs->adap)
617 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
618 64);
4d22de3e 619 }
48c4b6db
DLR		 620
621 /*
622 * netif_napi_add() can be called only once per napi_struct because it
623 * adds each new napi_struct to a list. Be careful not to call it a
624 * second time, e.g., during EEH recovery, by making a note of it.
625 */
626 adap->flags |= NAPI_INIT;
4d22de3e
DLR		 627}
628
629/*
630 * Wait until all NAPI handlers are descheduled. This includes the handlers of
631 * both netdevices representing interfaces and the dummy ones for the extra
632 * queues.
633 */
634static void quiesce_rx(struct adapter *adap)
635{
636 int i;
4d22de3e 637
bea3348e
SH		 638 for (i = 0; i < SGE_QSETS; i++)
639 if (adap->sge.qs[i].adap)
640 napi_disable(&adap->sge.qs[i].napi);
641}
4d22de3e 642
bea3348e
SH		 643static void enable_all_napi(struct adapter *adap)
644{
645 int i;
646 for (i = 0; i < SGE_QSETS; i++)
647 if (adap->sge.qs[i].adap)
648 napi_enable(&adap->sge.qs[i].napi);
4d22de3e
DLR		 649}
650
651/**
652 * setup_sge_qsets - configure SGE Tx/Rx/response queues
653 * @adap: the adapter
654 *
655 * Determines how many sets of SGE queues to use and initializes them.
656 * We support multiple queue sets per port if we have MSI-X, otherwise
657 * just one queue set per port.
658 */
659static int setup_sge_qsets(struct adapter *adap)
660{
bea3348e 661 int i, j, err, irq_idx = 0, qset_idx = 0;
8ac3ba68 662 unsigned int ntxq = SGE_TXQ_PER_SET;
4d22de3e
DLR		 663
664 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
665 irq_idx = -1;
666
667 for_each_port(adap, i) {
668 struct net_device *dev = adap->port[i];
bea3348e 669 struct port_info *pi = netdev_priv(dev);
4d22de3e 670
bea3348e 671 pi->qs = &adap->sge.qs[pi->first_qset];
e594e96e 672 for (j = 0; j < pi->nqsets; ++j, ++qset_idx) {
4d22de3e
DLR		 673 err = t3_sge_alloc_qset(adap, qset_idx, 1,
674 (adap->flags & USING_MSIX) ? qset_idx + 1 :
675 irq_idx,
82ad3329
DLR		 676 &adap->params.sge.qset[qset_idx], ntxq, dev,
677 netdev_get_tx_queue(dev, j));
4d22de3e
DLR		 678 if (err) {
679 t3_free_sge_resources(adap);
680 return err;
681 }
682 }
683 }
684
685 return 0;
686}
687
3e5192ee 688static ssize_t attr_show(struct device *d, char *buf,
896392ef 689 ssize_t(*format) (struct net_device *, char *))
4d22de3e
DLR		 690{
691 ssize_t len;
4d22de3e
DLR		 692
693 /* Synchronize with ioctls that may shut down the device */
694 rtnl_lock();
896392ef 695 len = (*format) (to_net_dev(d), buf);
4d22de3e
DLR		 696 rtnl_unlock();
697 return len;
698}
699
3e5192ee 700static ssize_t attr_store(struct device *d,
0ee8d33c 701 const char *buf, size_t len,
896392ef 702 ssize_t(*set) (struct net_device *, unsigned int),
4d22de3e
DLR		 703 unsigned int min_val, unsigned int max_val)
704{
4d22de3e
DLR		 705 ssize_t ret;
706 unsigned int val;
4d22de3e
DLR		 707
708 if (!capable(CAP_NET_ADMIN))
709 return -EPERM;
710
e72c932d
LC		 711 ret = kstrtouint(buf, 0, &val);
712 if (ret)
713 return ret;
714 if (val < min_val || val > max_val)
4d22de3e
DLR		 715 return -EINVAL;
716
717 rtnl_lock();
896392ef 718 ret = (*set) (to_net_dev(d), val);
4d22de3e
DLR		 719 if (!ret)
720 ret = len;
721 rtnl_unlock();
722 return ret;
723}
724
725#define CXGB3_SHOW(name, val_expr) \
896392ef 726static ssize_t format_##name(struct net_device *dev, char *buf) \
4d22de3e 727{ \
5fbf816f
DLR		 728 struct port_info *pi = netdev_priv(dev); \
729 struct adapter *adap = pi->adapter; \
4d22de3e
DLR		 730 return sprintf(buf, "%u\n", val_expr); \
731} \
0ee8d33c
DLR		 732static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
733 char *buf) \
4d22de3e 734{ \
3e5192ee 735 return attr_show(d, buf, format_##name); \
4d22de3e
DLR		 736}
737
896392ef 738static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
4d22de3e 739{
5fbf816f
DLR		 740 struct port_info *pi = netdev_priv(dev);
741 struct adapter *adap = pi->adapter;
9f238486 742 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
896392ef 743
4d22de3e
DLR		 744 if (adap->flags & FULL_INIT_DONE)
745 return -EBUSY;
746 if (val && adap->params.rev == 0)
747 return -EINVAL;
9f238486
DLR		 748 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
749 min_tids)
4d22de3e
DLR		 750 return -EINVAL;
751 adap->params.mc5.nfilters = val;
752 return 0;
753}
754
0ee8d33c
DLR		 755static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
756 const char *buf, size_t len)
4d22de3e 757{
3e5192ee 758 return attr_store(d, buf, len, set_nfilters, 0, ~0);
4d22de3e
DLR		 759}
760
896392ef 761static ssize_t set_nservers(struct net_device *dev, unsigned int val)
4d22de3e 762{
5fbf816f
DLR		 763 struct port_info *pi = netdev_priv(dev);
764 struct adapter *adap = pi->adapter;
896392ef 765
4d22de3e
DLR		 766 if (adap->flags & FULL_INIT_DONE)
767 return -EBUSY;
9f238486
DLR		 768 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
769 MC5_MIN_TIDS)
4d22de3e
DLR		 770 return -EINVAL;
771 adap->params.mc5.nservers = val;
772 return 0;
773}
774
0ee8d33c
DLR		 775static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
776 const char *buf, size_t len)
4d22de3e 777{
3e5192ee 778 return attr_store(d, buf, len, set_nservers, 0, ~0);
4d22de3e
DLR		 779}
780
781#define CXGB3_ATTR_R(name, val_expr) \
782CXGB3_SHOW(name, val_expr) \
0ee8d33c 783static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
4d22de3e
DLR		 784
785#define CXGB3_ATTR_RW(name, val_expr, store_method) \
786CXGB3_SHOW(name, val_expr) \
0ee8d33c 787static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
4d22de3e
DLR		 788
789CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
790CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
791CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
792
793static struct attribute *cxgb3_attrs[] = {
0ee8d33c
DLR		 794 &dev_attr_cam_size.attr,
795 &dev_attr_nfilters.attr,
796 &dev_attr_nservers.attr,
4d22de3e
DLR		 797 NULL
798};
799
800static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
801
3e5192ee 802static ssize_t tm_attr_show(struct device *d,
0ee8d33c 803 char *buf, int sched)
4d22de3e 804{
5fbf816f
DLR		 805 struct port_info *pi = netdev_priv(to_net_dev(d));
806 struct adapter *adap = pi->adapter;
4d22de3e 807 unsigned int v, addr, bpt, cpt;
5fbf816f 808 ssize_t len;
4d22de3e
DLR		 809
810 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
811 rtnl_lock();
812 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
813 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
814 if (sched & 1)
815 v >>= 16;
816 bpt = (v >> 8) & 0xff;
817 cpt = v & 0xff;
818 if (!cpt)
819 len = sprintf(buf, "disabled\n");
820 else {
821 v = (adap->params.vpd.cclk * 1000) / cpt;
822 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
823 }
824 rtnl_unlock();
825 return len;
826}
827
3e5192ee 828static ssize_t tm_attr_store(struct device *d,
0ee8d33c 829 const char *buf, size_t len, int sched)
4d22de3e 830{
5fbf816f
DLR		 831 struct port_info *pi = netdev_priv(to_net_dev(d));
832 struct adapter *adap = pi->adapter;
833 unsigned int val;
4d22de3e 834 ssize_t ret;
4d22de3e
DLR		 835
836 if (!capable(CAP_NET_ADMIN))
837 return -EPERM;
838
e72c932d
LC		 839 ret = kstrtouint(buf, 0, &val);
840 if (ret)
841 return ret;
842 if (val > 10000000)
4d22de3e
DLR		 843 return -EINVAL;
844
845 rtnl_lock();
846 ret = t3_config_sched(adap, val, sched);
847 if (!ret)
848 ret = len;
849 rtnl_unlock();
850 return ret;
851}
852
853#define TM_ATTR(name, sched) \
0ee8d33c
DLR		 854static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
855 char *buf) \
4d22de3e 856{ \
3e5192ee 857 return tm_attr_show(d, buf, sched); \
4d22de3e 858} \
0ee8d33c
DLR		 859static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
860 const char *buf, size_t len) \
4d22de3e 861{ \
3e5192ee 862 return tm_attr_store(d, buf, len, sched); \
4d22de3e 863} \
0ee8d33c 864static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
4d22de3e
DLR		 865
866TM_ATTR(sched0, 0);
867TM_ATTR(sched1, 1);
868TM_ATTR(sched2, 2);
869TM_ATTR(sched3, 3);
870TM_ATTR(sched4, 4);
871TM_ATTR(sched5, 5);
872TM_ATTR(sched6, 6);
873TM_ATTR(sched7, 7);
874
875static struct attribute *offload_attrs[] = {
0ee8d33c
DLR		 876 &dev_attr_sched0.attr,
877 &dev_attr_sched1.attr,
878 &dev_attr_sched2.attr,
879 &dev_attr_sched3.attr,
880 &dev_attr_sched4.attr,
881 &dev_attr_sched5.attr,
882 &dev_attr_sched6.attr,
883 &dev_attr_sched7.attr,
4d22de3e
DLR		 884 NULL
885};
886
887static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
888
889/*
890 * Sends an sk_buff to an offload queue driver
891 * after dealing with any active network taps.
892 */
893static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
894{
895 int ret;
896
897 local_bh_disable();
898 ret = t3_offload_tx(tdev, skb);
899 local_bh_enable();
900 return ret;
901}
902
903static int write_smt_entry(struct adapter *adapter, int idx)
904{
905 struct cpl_smt_write_req *req;
f14d42f3 906 struct port_info *pi = netdev_priv(adapter->port[idx]);
4d22de3e
DLR		 907 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
908
909 if (!skb)
910 return -ENOMEM;
911
912 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
913 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
914 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
915 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
916 req->iff = idx;
4d22de3e 917 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
f14d42f3 918 memcpy(req->src_mac1, pi->iscsic.mac_addr, ETH_ALEN);
4d22de3e
DLR		 919 skb->priority = 1;
920 offload_tx(&adapter->tdev, skb);
921 return 0;
922}
923
924static int init_smt(struct adapter *adapter)
925{
926 int i;
927
928 for_each_port(adapter, i)
929 write_smt_entry(adapter, i);
930 return 0;
931}
932
933static void init_port_mtus(struct adapter *adapter)
934{
935 unsigned int mtus = adapter->port[0]->mtu;
936
937 if (adapter->port[1])
938 mtus |= adapter->port[1]->mtu << 16;
939 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
940}
941
8c263761 942static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
14ab9892
DLR		 943 int hi, int port)
944{
945 struct sk_buff *skb;
946 struct mngt_pktsched_wr *req;
8c263761 947 int ret;
14ab9892 948
74b793e1
DLR		 949 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
950 if (!skb)
951 skb = adap->nofail_skb;
952 if (!skb)
953 return -ENOMEM;
954
14ab9892
DLR		 955 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
956 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
957 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
958 req->sched = sched;
959 req->idx = qidx;
960 req->min = lo;
961 req->max = hi;
962 req->binding = port;
8c263761 963 ret = t3_mgmt_tx(adap, skb);
74b793e1
DLR		 964 if (skb == adap->nofail_skb) {
965 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
966 GFP_KERNEL);
967 if (!adap->nofail_skb)
968 ret = -ENOMEM;
969 }
8c263761
DLR		 970
971 return ret;
14ab9892
DLR		 972}
973
8c263761 974static int bind_qsets(struct adapter *adap)
14ab9892 975{
8c263761 976 int i, j, err = 0;
14ab9892
DLR		 977
978 for_each_port(adap, i) {
979 const struct port_info *pi = adap2pinfo(adap, i);
980
8c263761
DLR		 981 for (j = 0; j < pi->nqsets; ++j) {
982 int ret = send_pktsched_cmd(adap, 1,
983 pi->first_qset + j, -1,
984 -1, i);
985 if (ret)
986 err = ret;
987 }
14ab9892 988 }
8c263761
DLR		 989
990 return err;
14ab9892
DLR		 991}
992
34336ec0
BH		 993#define FW_VERSION __stringify(FW_VERSION_MAJOR) "." \
994 __stringify(FW_VERSION_MINOR) "." __stringify(FW_VERSION_MICRO)
995#define FW_FNAME "cxgb3/t3fw-" FW_VERSION ".bin"
996#define TPSRAM_VERSION __stringify(TP_VERSION_MAJOR) "." \
997 __stringify(TP_VERSION_MINOR) "." __stringify(TP_VERSION_MICRO)
998#define TPSRAM_NAME "cxgb3/t3%c_psram-" TPSRAM_VERSION ".bin"
2e8c07c3
DLR		 999#define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
1000#define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
9450526a 1001#define AEL2020_TWX_EDC_NAME "cxgb3/ael2020_twx_edc.bin"
34336ec0
BH		 1002MODULE_FIRMWARE(FW_FNAME);
1003MODULE_FIRMWARE("cxgb3/t3b_psram-" TPSRAM_VERSION ".bin");
1004MODULE_FIRMWARE("cxgb3/t3c_psram-" TPSRAM_VERSION ".bin");
1005MODULE_FIRMWARE(AEL2005_OPT_EDC_NAME);
1006MODULE_FIRMWARE(AEL2005_TWX_EDC_NAME);
1007MODULE_FIRMWARE(AEL2020_TWX_EDC_NAME);
2e8c07c3
DLR		 1008
1009static inline const char *get_edc_fw_name(int edc_idx)
1010{
1011 const char *fw_name = NULL;
1012
1013 switch (edc_idx) {
1014 case EDC_OPT_AEL2005:
1015 fw_name = AEL2005_OPT_EDC_NAME;
1016 break;
1017 case EDC_TWX_AEL2005:
1018 fw_name = AEL2005_TWX_EDC_NAME;
1019 break;
1020 case EDC_TWX_AEL2020:
1021 fw_name = AEL2020_TWX_EDC_NAME;
1022 break;
1023 }
1024 return fw_name;
1025}
1026
1027int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
1028{
1029 struct adapter *adapter = phy->adapter;
1030 const struct firmware *fw;
92a486ca 1031 const char *fw_name;
2e8c07c3
DLR		 1032 u32 csum;
1033 const __be32 *p;
1034 u16 *cache = phy->phy_cache;
92a486ca 1035 int i, ret = -EINVAL;
2e8c07c3 1036
92a486ca
KC		 1037 fw_name = get_edc_fw_name(edc_idx);
1038 if (fw_name)
1039 ret = request_firmware(&fw, fw_name, &adapter->pdev->dev);
2e8c07c3
DLR		 1040 if (ret < 0) {
1041 dev_err(&adapter->pdev->dev,
1042 "could not upgrade firmware: unable to load %s\n",
92a486ca 1043 fw_name);
2e8c07c3
DLR		 1044 return ret;
1045 }
1046
1047 /* check size, take checksum in account */
1048 if (fw->size > size + 4) {
1049 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1050 (unsigned int)fw->size, size + 4);
1051 ret = -EINVAL;
1052 }
1053
1054 /* compute checksum */
1055 p = (const __be32 *)fw->data;
1056 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1057 csum += ntohl(p[i]);
1058
1059 if (csum != 0xffffffff) {
1060 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1061 csum);
1062 ret = -EINVAL;
1063 }
1064
1065 for (i = 0; i < size / 4 ; i++) {
1066 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1067 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1068 }
1069
1070 release_firmware(fw);
1071
1072 return ret;
1073}
2e283962
DLR		 1074
1075static int upgrade_fw(struct adapter *adap)
1076{
1077 int ret;
2e283962
DLR		 1078 const struct firmware *fw;
1079 struct device *dev = &adap->pdev->dev;
1080
34336ec0 1081 ret = request_firmware(&fw, FW_FNAME, dev);
2e283962
DLR		 1082 if (ret < 0) {
1083 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
34336ec0 1084 FW_FNAME);
2e283962
DLR		 1085 return ret;
1086 }
1087 ret = t3_load_fw(adap, fw->data, fw->size);
1088 release_firmware(fw);
47330077
DLR		 1089
1090 if (ret == 0)
1091 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
1092 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1093 else
1094 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
1095 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
2eab17ab 1096
47330077
DLR		 1097 return ret;
1098}
1099
1100static inline char t3rev2char(struct adapter *adapter)
1101{
1102 char rev = 0;
1103
1104 switch(adapter->params.rev) {
1105 case T3_REV_B:
1106 case T3_REV_B2:
1107 rev = 'b';
1108 break;
1aafee26
DLR		 1109 case T3_REV_C:
1110 rev = 'c';
1111 break;
47330077
DLR		 1112 }
1113 return rev;
1114}
1115
9265fabf 1116static int update_tpsram(struct adapter *adap)
47330077
DLR		 1117{
1118 const struct firmware *tpsram;
1119 char buf[64];
1120 struct device *dev = &adap->pdev->dev;
1121 int ret;
1122 char rev;
2eab17ab 1123
47330077
DLR		 1124 rev = t3rev2char(adap);
1125 if (!rev)
1126 return 0;
1127
34336ec0 1128 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev);
47330077
DLR		 1129
1130 ret = request_firmware(&tpsram, buf, dev);
1131 if (ret < 0) {
1132 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1133 buf);
1134 return ret;
1135 }
2eab17ab 1136
47330077
DLR		 1137 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1138 if (ret)
2eab17ab 1139 goto release_tpsram;
47330077
DLR		 1140
1141 ret = t3_set_proto_sram(adap, tpsram->data);
1142 if (ret == 0)
1143 dev_info(dev,
1144 "successful update of protocol engine "
1145 "to %d.%d.%d\n",
1146 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1147 else
1148 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1149 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1150 if (ret)
1151 dev_err(dev, "loading protocol SRAM failed\n");
1152
1153release_tpsram:
1154 release_firmware(tpsram);
2eab17ab 1155
2e283962
DLR		 1156 return ret;
1157}
1158
60158e64
RD		 1159/**
1160 * t3_synchronize_rx - wait for current Rx processing on a port to complete
1161 * @adap: the adapter
1162 * @p: the port
1163 *
1164 * Ensures that current Rx processing on any of the queues associated with
1165 * the given port completes before returning. We do this by acquiring and
1166 * releasing the locks of the response queues associated with the port.
1167 */
1168static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
1169{
1170 int i;
1171
1172 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
1173 struct sge_rspq *q = &adap->sge.qs[i].rspq;
1174
1175 spin_lock_irq(&q->lock);
1176 spin_unlock_irq(&q->lock);
1177 }
1178}
1179
1180static void cxgb_vlan_mode(struct net_device *dev, netdev_features_t features)
1181{
1182 struct port_info *pi = netdev_priv(dev);
1183 struct adapter *adapter = pi->adapter;
1184
1185 if (adapter->params.rev > 0) {
1186 t3_set_vlan_accel(adapter, 1 << pi->port_id,
f646968f 1187 features & NETIF_F_HW_VLAN_CTAG_RX);
60158e64
RD		 1188 } else {
1189 /* single control for all ports */
f646968f 1190 unsigned int i, have_vlans = features & NETIF_F_HW_VLAN_CTAG_RX;
60158e64
RD		 1191
1192 for_each_port(adapter, i)
1193 have_vlans |=
f646968f
PM		 1194 adapter->port[i]->features &
1195 NETIF_F_HW_VLAN_CTAG_RX;
60158e64
RD		 1196
1197 t3_set_vlan_accel(adapter, 1, have_vlans);
1198 }
1199 t3_synchronize_rx(adapter, pi);
1200}
1201
4d22de3e
DLR		 1202/**
1203 * cxgb_up - enable the adapter
1204 * @adapter: adapter being enabled
1205 *
1206 * Called when the first port is enabled, this function performs the
1207 * actions necessary to make an adapter operational, such as completing
1208 * the initialization of HW modules, and enabling interrupts.
1209 *
1210 * Must be called with the rtnl lock held.
1211 */
1212static int cxgb_up(struct adapter *adap)
1213{
60158e64 1214 int i, err;
4d22de3e
DLR		 1215
1216 if (!(adap->flags & FULL_INIT_DONE)) {
8207befa 1217 err = t3_check_fw_version(adap);
a5a3b460 1218 if (err == -EINVAL) {
2e283962 1219 err = upgrade_fw(adap);
8207befa
DLR		 1220 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1221 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1222 FW_VERSION_MICRO, err ? "failed" : "succeeded");
a5a3b460 1223 }
4d22de3e 1224
8207befa 1225 err = t3_check_tpsram_version(adap);
47330077
DLR		 1226 if (err == -EINVAL) {
1227 err = update_tpsram(adap);
8207befa
DLR		 1228 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1229 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1230 TP_VERSION_MICRO, err ? "failed" : "succeeded");
47330077
DLR		 1231 }
1232
20d3fc11
DLR		 1233 /*
1234 * Clear interrupts now to catch errors if t3_init_hw fails.
1235 * We clear them again later as initialization may trigger
1236 * conditions that can interrupt.
1237 */
1238 t3_intr_clear(adap);
1239
4d22de3e
DLR		 1240 err = t3_init_hw(adap, 0);
1241 if (err)
1242 goto out;
1243
b881955b 1244 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
6cdbd77e 1245 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
bea3348e 1246
4d22de3e
DLR		 1247 err = setup_sge_qsets(adap);
1248 if (err)
1249 goto out;
1250
60158e64
RD		 1251 for_each_port(adap, i)
1252 cxgb_vlan_mode(adap->port[i], adap->port[i]->features);
1253
4d22de3e 1254 setup_rss(adap);
48c4b6db
DLR		 1255 if (!(adap->flags & NAPI_INIT))
1256 init_napi(adap);
31563789
DLR		 1257
1258 t3_start_sge_timers(adap);
4d22de3e
DLR		 1259 adap->flags |= FULL_INIT_DONE;
1260 }
1261
1262 t3_intr_clear(adap);
1263
1264 if (adap->flags & USING_MSIX) {
1265 name_msix_vecs(adap);
1266 err = request_irq(adap->msix_info[0].vec,
1267 t3_async_intr_handler, 0,
1268 adap->msix_info[0].desc, adap);
1269 if (err)
1270 goto irq_err;
1271
42256f57
DLR		 1272 err = request_msix_data_irqs(adap);
1273 if (err) {
4d22de3e
DLR		 1274 free_irq(adap->msix_info[0].vec, adap);
1275 goto irq_err;
1276 }
1277 } else if ((err = request_irq(adap->pdev->irq,
1278 t3_intr_handler(adap,
1279 adap->sge.qs[0].rspq.
1280 polling),
2db6346f
TG		 1281 (adap->flags & USING_MSI) ?
1282 0 : IRQF_SHARED,
4d22de3e
DLR		 1283 adap->name, adap)))
1284 goto irq_err;
1285
bea3348e 1286 enable_all_napi(adap);
4d22de3e
DLR		 1287 t3_sge_start(adap);
1288 t3_intr_enable(adap);
14ab9892 1289
b881955b
DLR		 1290 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1291 is_offload(adap) && init_tp_parity(adap) == 0)
1292 adap->flags |= TP_PARITY_INIT;
1293
1294 if (adap->flags & TP_PARITY_INIT) {
1295 t3_write_reg(adap, A_TP_INT_CAUSE,
1296 F_CMCACHEPERR | F_ARPLUTPERR);
1297 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1298 }
1299
8c263761 1300 if (!(adap->flags & QUEUES_BOUND)) {
18edc84c
DLR		 1301 int ret = bind_qsets(adap);
1302
1303 if (ret < 0) {
1304 CH_ERR(adap, "failed to bind qsets, err %d\n", ret);
8c263761
DLR		 1305 t3_intr_disable(adap);
1306 free_irq_resources(adap);
18edc84c 1307 err = ret;
8c263761
DLR		 1308 goto out;
1309 }
1310 adap->flags |= QUEUES_BOUND;
1311 }
14ab9892 1312
4d22de3e
DLR		 1313out:
1314 return err;
1315irq_err:
1316 CH_ERR(adap, "request_irq failed, err %d\n", err);
1317 goto out;
1318}
1319
1320/*
1321 * Release resources when all the ports and offloading have been stopped.
1322 */
55bc3228 1323static void cxgb_down(struct adapter *adapter, int on_wq)
4d22de3e
DLR		 1324{
1325 t3_sge_stop(adapter);
1326 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1327 t3_intr_disable(adapter);
1328 spin_unlock_irq(&adapter->work_lock);
1329
8c263761 1330 free_irq_resources(adapter);
4d22de3e 1331 quiesce_rx(adapter);
a6f018e3 1332 t3_sge_stop(adapter);
55bc3228
CL		 1333 if (!on_wq)
1334 flush_workqueue(cxgb3_wq);/* wait for external IRQ handler */
4d22de3e
DLR		 1335}
1336
1337static void schedule_chk_task(struct adapter *adap)
1338{
1339 unsigned int timeo;
1340
1341 timeo = adap->params.linkpoll_period ?
1342 (HZ * adap->params.linkpoll_period) / 10 :
1343 adap->params.stats_update_period * HZ;
1344 if (timeo)
1345 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1346}
1347
1348static int offload_open(struct net_device *dev)
1349{
5fbf816f
DLR		 1350 struct port_info *pi = netdev_priv(dev);
1351 struct adapter *adapter = pi->adapter;
1352 struct t3cdev *tdev = dev2t3cdev(dev);
4d22de3e 1353 int adap_up = adapter->open_device_map & PORT_MASK;
c54f5c24 1354 int err;
4d22de3e
DLR		 1355
1356 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1357 return 0;
1358
1359 if (!adap_up && (err = cxgb_up(adapter)) < 0)
48c4b6db 1360 goto out;
4d22de3e
DLR		 1361
1362 t3_tp_set_offload_mode(adapter, 1);
1363 tdev->lldev = adapter->port[0];
1364 err = cxgb3_offload_activate(adapter);
1365 if (err)
1366 goto out;
1367
1368 init_port_mtus(adapter);
1369 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1370 adapter->params.b_wnd,
1371 adapter->params.rev == 0 ?
1372 adapter->port[0]->mtu : 0xffff);
1373 init_smt(adapter);
1374
d96a51f6
DN		 1375 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1376 dev_dbg(&dev->dev, "cannot create sysfs group\n");
4d22de3e
DLR		 1377
1378 /* Call back all registered clients */
1379 cxgb3_add_clients(tdev);
1380
1381out:
1382 /* restore them in case the offload module has changed them */
1383 if (err) {
1384 t3_tp_set_offload_mode(adapter, 0);
1385 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1386 cxgb3_set_dummy_ops(tdev);
1387 }
1388 return err;
1389}
1390
1391static int offload_close(struct t3cdev *tdev)
1392{
1393 struct adapter *adapter = tdev2adap(tdev);
23f333a2 1394 struct t3c_data *td = T3C_DATA(tdev);
4d22de3e
DLR		 1395
1396 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1397 return 0;
1398
1399 /* Call back all registered clients */
1400 cxgb3_remove_clients(tdev);
1401
0ee8d33c 1402 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
4d22de3e 1403
c80b0c28 1404 /* Flush work scheduled while releasing TIDs */
43829731 1405 flush_work(&td->tid_release_task);
c80b0c28 1406
4d22de3e
DLR		 1407 tdev->lldev = NULL;
1408 cxgb3_set_dummy_ops(tdev);
1409 t3_tp_set_offload_mode(adapter, 0);
1410 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1411
1412 if (!adapter->open_device_map)
55bc3228 1413 cxgb_down(adapter, 0);
4d22de3e
DLR		 1414
1415 cxgb3_offload_deactivate(adapter);
1416 return 0;
1417}
1418
1419static int cxgb_open(struct net_device *dev)
1420{
4d22de3e 1421 struct port_info *pi = netdev_priv(dev);
5fbf816f 1422 struct adapter *adapter = pi->adapter;
4d22de3e 1423 int other_ports = adapter->open_device_map & PORT_MASK;
5fbf816f 1424 int err;
4d22de3e 1425
48c4b6db 1426 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
4d22de3e
DLR		 1427 return err;
1428
1429 set_bit(pi->port_id, &adapter->open_device_map);
8ac3ba68 1430 if (is_offload(adapter) && !ofld_disable) {
4d22de3e
DLR		 1431 err = offload_open(dev);
1432 if (err)
428ac43f 1433 pr_warn("Could not initialize offload capabilities\n");
4d22de3e
DLR		 1434 }
1435
19221e75
BH		 1436 netif_set_real_num_tx_queues(dev, pi->nqsets);
1437 err = netif_set_real_num_rx_queues(dev, pi->nqsets);
1438 if (err)
1439 return err;
4d22de3e
DLR		 1440 link_start(dev);
1441 t3_port_intr_enable(adapter, pi->port_id);
82ad3329 1442 netif_tx_start_all_queues(dev);
4d22de3e
DLR		 1443 if (!other_ports)
1444 schedule_chk_task(adapter);
1445
fa0d4c11 1446 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_UP, pi->port_id);
4d22de3e
DLR		 1447 return 0;
1448}
1449
55bc3228 1450static int __cxgb_close(struct net_device *dev, int on_wq)
4d22de3e 1451{
5fbf816f
DLR		 1452 struct port_info *pi = netdev_priv(dev);
1453 struct adapter *adapter = pi->adapter;
4d22de3e 1454
e8d19370
DLR		 1455
1456 if (!adapter->open_device_map)
1457 return 0;
1458
bf792094
DLR		 1459 /* Stop link fault interrupts */
1460 t3_xgm_intr_disable(adapter, pi->port_id);
1461 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1462
5fbf816f 1463 t3_port_intr_disable(adapter, pi->port_id);
82ad3329 1464 netif_tx_stop_all_queues(dev);
5fbf816f 1465 pi->phy.ops->power_down(&pi->phy, 1);
4d22de3e 1466 netif_carrier_off(dev);
5fbf816f 1467 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
4d22de3e 1468
20d3fc11 1469 spin_lock_irq(&adapter->work_lock); /* sync with update task */
5fbf816f 1470 clear_bit(pi->port_id, &adapter->open_device_map);
20d3fc11 1471 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 1472
1473 if (!(adapter->open_device_map & PORT_MASK))
c80b0c28 1474 cancel_delayed_work_sync(&adapter->adap_check_task);
4d22de3e
DLR		 1475
1476 if (!adapter->open_device_map)
55bc3228 1477 cxgb_down(adapter, on_wq);
4d22de3e 1478
fa0d4c11 1479 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_DOWN, pi->port_id);
4d22de3e
DLR		 1480 return 0;
1481}
1482
55bc3228
CL		 1483static int cxgb_close(struct net_device *dev)
1484{
1485 return __cxgb_close(dev, 0);
1486}
1487
4d22de3e
DLR		 1488static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1489{
5fbf816f
DLR		 1490 struct port_info *pi = netdev_priv(dev);
1491 struct adapter *adapter = pi->adapter;
1492 struct net_device_stats *ns = &pi->netstats;
4d22de3e
DLR		 1493 const struct mac_stats *pstats;
1494
1495 spin_lock(&adapter->stats_lock);
5fbf816f 1496 pstats = t3_mac_update_stats(&pi->mac);
4d22de3e
DLR		 1497 spin_unlock(&adapter->stats_lock);
1498
1499 ns->tx_bytes = pstats->tx_octets;
1500 ns->tx_packets = pstats->tx_frames;
1501 ns->rx_bytes = pstats->rx_octets;
1502 ns->rx_packets = pstats->rx_frames;
1503 ns->multicast = pstats->rx_mcast_frames;
1504
1505 ns->tx_errors = pstats->tx_underrun;
1506 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1507 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1508 pstats->rx_fifo_ovfl;
1509
1510 /* detailed rx_errors */
1511 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1512 ns->rx_over_errors = 0;
1513 ns->rx_crc_errors = pstats->rx_fcs_errs;
1514 ns->rx_frame_errors = pstats->rx_symbol_errs;
1515 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1516 ns->rx_missed_errors = pstats->rx_cong_drops;
1517
1518 /* detailed tx_errors */
1519 ns->tx_aborted_errors = 0;
1520 ns->tx_carrier_errors = 0;
1521 ns->tx_fifo_errors = pstats->tx_underrun;
1522 ns->tx_heartbeat_errors = 0;
1523 ns->tx_window_errors = 0;
1524 return ns;
1525}
1526
1527static u32 get_msglevel(struct net_device *dev)
1528{
5fbf816f
DLR		 1529 struct port_info *pi = netdev_priv(dev);
1530 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1531
1532 return adapter->msg_enable;
1533}
1534
1535static void set_msglevel(struct net_device *dev, u32 val)
1536{
5fbf816f
DLR		 1537 struct port_info *pi = netdev_priv(dev);
1538 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1539
1540 adapter->msg_enable = val;
1541}
1542
9ca683c6 1543static const char stats_strings[][ETH_GSTRING_LEN] = {
4d22de3e
DLR		 1544 "TxOctetsOK ",
1545 "TxFramesOK ",
1546 "TxMulticastFramesOK",
1547 "TxBroadcastFramesOK",
1548 "TxPauseFrames ",
1549 "TxUnderrun ",
1550 "TxExtUnderrun ",
1551
1552 "TxFrames64 ",
1553 "TxFrames65To127 ",
1554 "TxFrames128To255 ",
1555 "TxFrames256To511 ",
1556 "TxFrames512To1023 ",
1557 "TxFrames1024To1518 ",
1558 "TxFrames1519ToMax ",
1559
1560 "RxOctetsOK ",
1561 "RxFramesOK ",
1562 "RxMulticastFramesOK",
1563 "RxBroadcastFramesOK",
1564 "RxPauseFrames ",
1565 "RxFCSErrors ",
1566 "RxSymbolErrors ",
1567 "RxShortErrors ",
1568 "RxJabberErrors ",
1569 "RxLengthErrors ",
1570 "RxFIFOoverflow ",
1571
1572 "RxFrames64 ",
1573 "RxFrames65To127 ",
1574 "RxFrames128To255 ",
1575 "RxFrames256To511 ",
1576 "RxFrames512To1023 ",
1577 "RxFrames1024To1518 ",
1578 "RxFrames1519ToMax ",
1579
1580 "PhyFIFOErrors ",
1581 "TSO ",
1582 "VLANextractions ",
1583 "VLANinsertions ",
1584 "TxCsumOffload ",
1585 "RxCsumGood ",
b47385bd
DLR		 1586 "LroAggregated ",
1587 "LroFlushed ",
1588 "LroNoDesc ",
fc90664e
DLR		 1589 "RxDrops ",
1590
1591 "CheckTXEnToggled ",
1592 "CheckResets ",
1593
bf792094 1594 "LinkFaults ",
4d22de3e
DLR		 1595};
1596
b9f2c044 1597static int get_sset_count(struct net_device *dev, int sset)
4d22de3e 1598{
b9f2c044
JG		 1599 switch (sset) {
1600 case ETH_SS_STATS:
1601 return ARRAY_SIZE(stats_strings);
1602 default:
1603 return -EOPNOTSUPP;
1604 }
4d22de3e
DLR		 1605}
1606
1607#define T3_REGMAP_SIZE (3 * 1024)
1608
1609static int get_regs_len(struct net_device *dev)
1610{
1611 return T3_REGMAP_SIZE;
1612}
1613
1614static int get_eeprom_len(struct net_device *dev)
1615{
1616 return EEPROMSIZE;
1617}
1618
1619static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1620{
5fbf816f
DLR		 1621 struct port_info *pi = netdev_priv(dev);
1622 struct adapter *adapter = pi->adapter;
4d22de3e 1623 u32 fw_vers = 0;
47330077 1624 u32 tp_vers = 0;
4d22de3e 1625
cf3760da 1626 spin_lock(&adapter->stats_lock);
4d22de3e 1627 t3_get_fw_version(adapter, &fw_vers);
47330077 1628 t3_get_tp_version(adapter, &tp_vers);
cf3760da 1629 spin_unlock(&adapter->stats_lock);
4d22de3e 1630
23020ab3
RJ		 1631 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1632 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1633 strlcpy(info->bus_info, pci_name(adapter->pdev),
1634 sizeof(info->bus_info));
84b40501 1635 if (fw_vers)
4d22de3e 1636 snprintf(info->fw_version, sizeof(info->fw_version),
47330077 1637 "%s %u.%u.%u TP %u.%u.%u",
4aac3899
DLR		 1638 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1639 G_FW_VERSION_MAJOR(fw_vers),
1640 G_FW_VERSION_MINOR(fw_vers),
47330077
DLR		 1641 G_FW_VERSION_MICRO(fw_vers),
1642 G_TP_VERSION_MAJOR(tp_vers),
1643 G_TP_VERSION_MINOR(tp_vers),
1644 G_TP_VERSION_MICRO(tp_vers));
4d22de3e
DLR		 1645}
1646
1647static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1648{
1649 if (stringset == ETH_SS_STATS)
1650 memcpy(data, stats_strings, sizeof(stats_strings));
1651}
1652
1653static unsigned long collect_sge_port_stats(struct adapter *adapter,
1654 struct port_info *p, int idx)
1655{
1656 int i;
1657 unsigned long tot = 0;
1658
8c263761
DLR		 1659 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1660 tot += adapter->sge.qs[i].port_stats[idx];
4d22de3e
DLR		 1661 return tot;
1662}
1663
1664static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1665 u64 *data)
1666{
4d22de3e 1667 struct port_info *pi = netdev_priv(dev);
5fbf816f 1668 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1669 const struct mac_stats *s;
1670
1671 spin_lock(&adapter->stats_lock);
1672 s = t3_mac_update_stats(&pi->mac);
1673 spin_unlock(&adapter->stats_lock);
1674
1675 *data++ = s->tx_octets;
1676 *data++ = s->tx_frames;
1677 *data++ = s->tx_mcast_frames;
1678 *data++ = s->tx_bcast_frames;
1679 *data++ = s->tx_pause;
1680 *data++ = s->tx_underrun;
1681 *data++ = s->tx_fifo_urun;
1682
1683 *data++ = s->tx_frames_64;
1684 *data++ = s->tx_frames_65_127;
1685 *data++ = s->tx_frames_128_255;
1686 *data++ = s->tx_frames_256_511;
1687 *data++ = s->tx_frames_512_1023;
1688 *data++ = s->tx_frames_1024_1518;
1689 *data++ = s->tx_frames_1519_max;
1690
1691 *data++ = s->rx_octets;
1692 *data++ = s->rx_frames;
1693 *data++ = s->rx_mcast_frames;
1694 *data++ = s->rx_bcast_frames;
1695 *data++ = s->rx_pause;
1696 *data++ = s->rx_fcs_errs;
1697 *data++ = s->rx_symbol_errs;
1698 *data++ = s->rx_short;
1699 *data++ = s->rx_jabber;
1700 *data++ = s->rx_too_long;
1701 *data++ = s->rx_fifo_ovfl;
1702
1703 *data++ = s->rx_frames_64;
1704 *data++ = s->rx_frames_65_127;
1705 *data++ = s->rx_frames_128_255;
1706 *data++ = s->rx_frames_256_511;
1707 *data++ = s->rx_frames_512_1023;
1708 *data++ = s->rx_frames_1024_1518;
1709 *data++ = s->rx_frames_1519_max;
1710
1711 *data++ = pi->phy.fifo_errors;
1712
1713 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1714 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1715 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1716 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1717 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
7be2df45
HX		 1718 *data++ = 0;
1719 *data++ = 0;
1720 *data++ = 0;
4d22de3e 1721 *data++ = s->rx_cong_drops;
fc90664e
DLR		 1722
1723 *data++ = s->num_toggled;
1724 *data++ = s->num_resets;
bf792094
DLR		 1725
1726 *data++ = s->link_faults;
4d22de3e
DLR		 1727}
1728
1729static inline void reg_block_dump(struct adapter *ap, void *buf,
1730 unsigned int start, unsigned int end)
1731{
1732 u32 *p = buf + start;
1733
1734 for (; start <= end; start += sizeof(u32))
1735 *p++ = t3_read_reg(ap, start);
1736}
1737
1738static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1739 void *buf)
1740{
5fbf816f
DLR		 1741 struct port_info *pi = netdev_priv(dev);
1742 struct adapter *ap = pi->adapter;
4d22de3e
DLR		 1743
1744 /*
1745 * Version scheme:
1746 * bits 0..9: chip version
1747 * bits 10..15: chip revision
1748 * bit 31: set for PCIe cards
1749 */
1750 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1751
1752 /*
1753 * We skip the MAC statistics registers because they are clear-on-read.
1754 * Also reading multi-register stats would need to synchronize with the
1755 * periodic mac stats accumulation. Hard to justify the complexity.
1756 */
1757 memset(buf, 0, T3_REGMAP_SIZE);
1758 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1759 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1760 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1761 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1762 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1763 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1764 XGM_REG(A_XGM_SERDES_STAT3, 1));
1765 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1766 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1767}
1768
1769static int restart_autoneg(struct net_device *dev)
1770{
1771 struct port_info *p = netdev_priv(dev);
1772
1773 if (!netif_running(dev))
1774 return -EAGAIN;
1775 if (p->link_config.autoneg != AUTONEG_ENABLE)
1776 return -EINVAL;
1777 p->phy.ops->autoneg_restart(&p->phy);
1778 return 0;
1779}
1780
12fcf941 1781static int set_phys_id(struct net_device *dev,
1782 enum ethtool_phys_id_state state)
4d22de3e 1783{
5fbf816f
DLR		 1784 struct port_info *pi = netdev_priv(dev);
1785 struct adapter *adapter = pi->adapter;
4d22de3e 1786
12fcf941 1787 switch (state) {
1788 case ETHTOOL_ID_ACTIVE:
fce55922 1789 return 1; /* cycle on/off once per second */
12fcf941 1790
1791 case ETHTOOL_ID_OFF:
1792 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, 0);
1793 break;
4d22de3e 1794
12fcf941 1795 case ETHTOOL_ID_ON:
1796 case ETHTOOL_ID_INACTIVE:
4d22de3e 1797 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
4d22de3e 1798 F_GPIO0_OUT_VAL);
12fcf941 1799 }
1800
4d22de3e
DLR		 1801 return 0;
1802}
1803
b7b44fd2
PR		 1804static int get_link_ksettings(struct net_device *dev,
1805 struct ethtool_link_ksettings *cmd)
4d22de3e
DLR		 1806{
1807 struct port_info *p = netdev_priv(dev);
b7b44fd2 1808 u32 supported;
4d22de3e 1809
b7b44fd2
PR		 1810 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1811 p->link_config.supported);
1812 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1813 p->link_config.advertising);
4d22de3e
DLR		 1814
1815 if (netif_carrier_ok(dev)) {
b7b44fd2
PR		 1816 cmd->base.speed = p->link_config.speed;
1817 cmd->base.duplex = p->link_config.duplex;
4d22de3e 1818 } else {
b7b44fd2
PR		 1819 cmd->base.speed = SPEED_UNKNOWN;
1820 cmd->base.duplex = DUPLEX_UNKNOWN;
4d22de3e
DLR		 1821 }
1822
b7b44fd2
PR		 1823 ethtool_convert_link_mode_to_legacy_u32(&supported,
1824 cmd->link_modes.supported);
1825
1826 cmd->base.port = (supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
1827 cmd->base.phy_address = p->phy.mdio.prtad;
1828 cmd->base.autoneg = p->link_config.autoneg;
4d22de3e
DLR		 1829 return 0;
1830}
1831
1832static int speed_duplex_to_caps(int speed, int duplex)
1833{
1834 int cap = 0;
1835
1836 switch (speed) {
1837 case SPEED_10:
1838 if (duplex == DUPLEX_FULL)
1839 cap = SUPPORTED_10baseT_Full;
1840 else
1841 cap = SUPPORTED_10baseT_Half;
1842 break;
1843 case SPEED_100:
1844 if (duplex == DUPLEX_FULL)
1845 cap = SUPPORTED_100baseT_Full;
1846 else
1847 cap = SUPPORTED_100baseT_Half;
1848 break;
1849 case SPEED_1000:
1850 if (duplex == DUPLEX_FULL)
1851 cap = SUPPORTED_1000baseT_Full;
1852 else
1853 cap = SUPPORTED_1000baseT_Half;
1854 break;
1855 case SPEED_10000:
1856 if (duplex == DUPLEX_FULL)
1857 cap = SUPPORTED_10000baseT_Full;
1858 }
1859 return cap;
1860}
1861
1862#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1863 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1864 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1865 ADVERTISED_10000baseT_Full)
1866
b7b44fd2
PR		 1867static int set_link_ksettings(struct net_device *dev,
1868 const struct ethtool_link_ksettings *cmd)
4d22de3e
DLR		 1869{
1870 struct port_info *p = netdev_priv(dev);
1871 struct link_config *lc = &p->link_config;
b7b44fd2
PR		 1872 u32 advertising;
1873
1874 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1875 cmd->link_modes.advertising);
4d22de3e 1876
9b1e3656
DLR		 1877 if (!(lc->supported & SUPPORTED_Autoneg)) {
1878 /*
1879 * PHY offers a single speed/duplex. See if that's what's
1880 * being requested.
1881 */
b7b44fd2
PR		 1882 if (cmd->base.autoneg == AUTONEG_DISABLE) {
1883 u32 speed = cmd->base.speed;
1884 int cap = speed_duplex_to_caps(speed, cmd->base.duplex);
9b1e3656
DLR		 1885 if (lc->supported & cap)
1886 return 0;
1887 }
1888 return -EINVAL;
1889 }
4d22de3e 1890
b7b44fd2
PR		 1891 if (cmd->base.autoneg == AUTONEG_DISABLE) {
1892 u32 speed = cmd->base.speed;
1893 int cap = speed_duplex_to_caps(speed, cmd->base.duplex);
4d22de3e 1894
25db0338 1895 if (!(lc->supported & cap) || (speed == SPEED_1000))
4d22de3e 1896 return -EINVAL;
25db0338 1897 lc->requested_speed = speed;
b7b44fd2 1898 lc->requested_duplex = cmd->base.duplex;
4d22de3e
DLR		 1899 lc->advertising = 0;
1900 } else {
b7b44fd2
PR		 1901 advertising &= ADVERTISED_MASK;
1902 advertising &= lc->supported;
1903 if (!advertising)
4d22de3e
DLR		 1904 return -EINVAL;
1905 lc->requested_speed = SPEED_INVALID;
1906 lc->requested_duplex = DUPLEX_INVALID;
b7b44fd2 1907 lc->advertising = advertising | ADVERTISED_Autoneg;
4d22de3e 1908 }
b7b44fd2 1909 lc->autoneg = cmd->base.autoneg;
4d22de3e
DLR		 1910 if (netif_running(dev))
1911 t3_link_start(&p->phy, &p->mac, lc);
1912 return 0;
1913}
1914
1915static void get_pauseparam(struct net_device *dev,
1916 struct ethtool_pauseparam *epause)
1917{
1918 struct port_info *p = netdev_priv(dev);
1919
1920 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1921 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1922 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1923}
1924
1925static int set_pauseparam(struct net_device *dev,
1926 struct ethtool_pauseparam *epause)
1927{
1928 struct port_info *p = netdev_priv(dev);
1929 struct link_config *lc = &p->link_config;
1930
1931 if (epause->autoneg == AUTONEG_DISABLE)
1932 lc->requested_fc = 0;
1933 else if (lc->supported & SUPPORTED_Autoneg)
1934 lc->requested_fc = PAUSE_AUTONEG;
1935 else
1936 return -EINVAL;
1937
1938 if (epause->rx_pause)
1939 lc->requested_fc |= PAUSE_RX;
1940 if (epause->tx_pause)
1941 lc->requested_fc |= PAUSE_TX;
1942 if (lc->autoneg == AUTONEG_ENABLE) {
1943 if (netif_running(dev))
1944 t3_link_start(&p->phy, &p->mac, lc);
1945 } else {
1946 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1947 if (netif_running(dev))
1948 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1949 }
1950 return 0;
1951}
1952
4d22de3e
DLR		 1953static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1954{
5fbf816f
DLR		 1955 struct port_info *pi = netdev_priv(dev);
1956 struct adapter *adapter = pi->adapter;
05b97b30 1957 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
4d22de3e
DLR		 1958
1959 e->rx_max_pending = MAX_RX_BUFFERS;
4d22de3e
DLR		 1960 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1961 e->tx_max_pending = MAX_TXQ_ENTRIES;
1962
05b97b30
DLR		 1963 e->rx_pending = q->fl_size;
1964 e->rx_mini_pending = q->rspq_size;
1965 e->rx_jumbo_pending = q->jumbo_size;
1966 e->tx_pending = q->txq_size[0];
4d22de3e
DLR		 1967}
1968
1969static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1970{
5fbf816f
DLR		 1971 struct port_info *pi = netdev_priv(dev);
1972 struct adapter *adapter = pi->adapter;
05b97b30 1973 struct qset_params *q;
5fbf816f 1974 int i;
4d22de3e
DLR		 1975
1976 if (e->rx_pending > MAX_RX_BUFFERS ||
1977 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1978 e->tx_pending > MAX_TXQ_ENTRIES ||
1979 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1980 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1981 e->rx_pending < MIN_FL_ENTRIES ||
1982 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1983 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1984 return -EINVAL;
1985
1986 if (adapter->flags & FULL_INIT_DONE)
1987 return -EBUSY;
1988
05b97b30
DLR		 1989 q = &adapter->params.sge.qset[pi->first_qset];
1990 for (i = 0; i < pi->nqsets; ++i, ++q) {
4d22de3e
DLR		 1991 q->rspq_size = e->rx_mini_pending;
1992 q->fl_size = e->rx_pending;
1993 q->jumbo_size = e->rx_jumbo_pending;
1994 q->txq_size[0] = e->tx_pending;
1995 q->txq_size[1] = e->tx_pending;
1996 q->txq_size[2] = e->tx_pending;
1997 }
1998 return 0;
1999}
2000
2001static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2002{
5fbf816f
DLR		 2003 struct port_info *pi = netdev_priv(dev);
2004 struct adapter *adapter = pi->adapter;
c211c969
AB		 2005 struct qset_params *qsp;
2006 struct sge_qset *qs;
2007 int i;
4d22de3e
DLR		 2008
2009 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
2010 return -EINVAL;
2011
c211c969
AB		 2012 for (i = 0; i < pi->nqsets; i++) {
2013 qsp = &adapter->params.sge.qset[i];
2014 qs = &adapter->sge.qs[i];
2015 qsp->coalesce_usecs = c->rx_coalesce_usecs;
2016 t3_update_qset_coalesce(qs, qsp);
2017 }
2018
4d22de3e
DLR		 2019 return 0;
2020}
2021
2022static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2023{
5fbf816f
DLR		 2024 struct port_info *pi = netdev_priv(dev);
2025 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2026 struct qset_params *q = adapter->params.sge.qset;
2027
2028 c->rx_coalesce_usecs = q->coalesce_usecs;
2029 return 0;
2030}
2031
2032static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2033 u8 * data)
2034{
5fbf816f
DLR		 2035 struct port_info *pi = netdev_priv(dev);
2036 struct adapter *adapter = pi->adapter;
4d22de3e 2037 int i, err = 0;
4d22de3e
DLR		 2038
2039 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2040 if (!buf)
2041 return -ENOMEM;
2042
2043 e->magic = EEPROM_MAGIC;
2044 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
05e5c116 2045 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
4d22de3e
DLR		 2046
2047 if (!err)
2048 memcpy(data, buf + e->offset, e->len);
2049 kfree(buf);
2050 return err;
2051}
2052
2053static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2054 u8 * data)
2055{
5fbf816f
DLR		 2056 struct port_info *pi = netdev_priv(dev);
2057 struct adapter *adapter = pi->adapter;
05e5c116
AV		 2058 u32 aligned_offset, aligned_len;
2059 __le32 *p;
4d22de3e 2060 u8 *buf;
c54f5c24 2061 int err;
4d22de3e
DLR		 2062
2063 if (eeprom->magic != EEPROM_MAGIC)
2064 return -EINVAL;
2065
2066 aligned_offset = eeprom->offset & ~3;
2067 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2068
2069 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2070 buf = kmalloc(aligned_len, GFP_KERNEL);
2071 if (!buf)
2072 return -ENOMEM;
05e5c116 2073 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
4d22de3e
DLR		 2074 if (!err && aligned_len > 4)
2075 err = t3_seeprom_read(adapter,
2076 aligned_offset + aligned_len - 4,
05e5c116 2077 (__le32 *) & buf[aligned_len - 4]);
4d22de3e
DLR		 2078 if (err)
2079 goto out;
2080 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2081 } else
2082 buf = data;
2083
2084 err = t3_seeprom_wp(adapter, 0);
2085 if (err)
2086 goto out;
2087
05e5c116 2088 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
4d22de3e
DLR		 2089 err = t3_seeprom_write(adapter, aligned_offset, *p);
2090 aligned_offset += 4;
2091 }
2092
2093 if (!err)
2094 err = t3_seeprom_wp(adapter, 1);
2095out:
2096 if (buf != data)
2097 kfree(buf);
2098 return err;
2099}
2100
2101static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2102{
2103 wol->supported = 0;
2104 wol->wolopts = 0;
2105 memset(&wol->sopass, 0, sizeof(wol->sopass));
2106}
2107
2108static const struct ethtool_ops cxgb_ethtool_ops = {
4d22de3e
DLR		 2109 .get_drvinfo = get_drvinfo,
2110 .get_msglevel = get_msglevel,
2111 .set_msglevel = set_msglevel,
2112 .get_ringparam = get_sge_param,
2113 .set_ringparam = set_sge_param,
2114 .get_coalesce = get_coalesce,
2115 .set_coalesce = set_coalesce,
2116 .get_eeprom_len = get_eeprom_len,
2117 .get_eeprom = get_eeprom,
2118 .set_eeprom = set_eeprom,
2119 .get_pauseparam = get_pauseparam,
2120 .set_pauseparam = set_pauseparam,
4d22de3e
DLR		 2121 .get_link = ethtool_op_get_link,
2122 .get_strings = get_strings,
12fcf941 2123 .set_phys_id = set_phys_id,
4d22de3e 2124 .nway_reset = restart_autoneg,
b9f2c044 2125 .get_sset_count = get_sset_count,
4d22de3e
DLR		 2126 .get_ethtool_stats = get_stats,
2127 .get_regs_len = get_regs_len,
2128 .get_regs = get_regs,
2129 .get_wol = get_wol,
b7b44fd2
PR		 2130 .get_link_ksettings = get_link_ksettings,
2131 .set_link_ksettings = set_link_ksettings,
4d22de3e
DLR		 2132};
2133
2134static int in_range(int val, int lo, int hi)
2135{
2136 return val < 0 || (val <= hi && val >= lo);
2137}
2138
2139static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
2140{
5fbf816f
DLR		 2141 struct port_info *pi = netdev_priv(dev);
2142 struct adapter *adapter = pi->adapter;
4d22de3e 2143 u32 cmd;
5fbf816f 2144 int ret;
4d22de3e
DLR		 2145
2146 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
2147 return -EFAULT;
2148
2149 switch (cmd) {
4d22de3e
DLR		 2150 case CHELSIO_SET_QSET_PARAMS:{
2151 int i;
2152 struct qset_params *q;
2153 struct ch_qset_params t;
8c263761
DLR		 2154 int q1 = pi->first_qset;
2155 int nqsets = pi->nqsets;
4d22de3e
DLR		 2156
2157 if (!capable(CAP_NET_ADMIN))
2158 return -EPERM;
2159 if (copy_from_user(&t, useraddr, sizeof(t)))
2160 return -EFAULT;
2161 if (t.qset_idx >= SGE_QSETS)
2162 return -EINVAL;
2163 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
8e95a202
JP		 2164 !in_range(t.cong_thres, 0, 255) ||
2165 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2166 MAX_TXQ_ENTRIES) ||
2167 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2168 MAX_TXQ_ENTRIES) ||
2169 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2170 MAX_CTRL_TXQ_ENTRIES) ||
2171 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2172 MAX_RX_BUFFERS) ||
2173 !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2174 MAX_RX_JUMBO_BUFFERS) ||
2175 !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2176 MAX_RSPQ_ENTRIES))
4d22de3e 2177 return -EINVAL;
8c263761 2178
4d22de3e
DLR		 2179 if ((adapter->flags & FULL_INIT_DONE) &&
2180 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2181 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2182 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2183 t.polling >= 0 || t.cong_thres >= 0))
2184 return -EBUSY;
2185
8c263761
DLR		 2186 /* Allow setting of any available qset when offload enabled */
2187 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2188 q1 = 0;
2189 for_each_port(adapter, i) {
2190 pi = adap2pinfo(adapter, i);
2191 nqsets += pi->first_qset + pi->nqsets;
2192 }
2193 }
2194
2195 if (t.qset_idx < q1)
2196 return -EINVAL;
2197 if (t.qset_idx > q1 + nqsets - 1)
2198 return -EINVAL;
2199
4d22de3e
DLR		 2200 q = &adapter->params.sge.qset[t.qset_idx];
2201
2202 if (t.rspq_size >= 0)
2203 q->rspq_size = t.rspq_size;
2204 if (t.fl_size[0] >= 0)
2205 q->fl_size = t.fl_size[0];
2206 if (t.fl_size[1] >= 0)
2207 q->jumbo_size = t.fl_size[1];
2208 if (t.txq_size[0] >= 0)
2209 q->txq_size[0] = t.txq_size[0];
2210 if (t.txq_size[1] >= 0)
2211 q->txq_size[1] = t.txq_size[1];
2212 if (t.txq_size[2] >= 0)
2213 q->txq_size[2] = t.txq_size[2];
2214 if (t.cong_thres >= 0)
2215 q->cong_thres = t.cong_thres;
2216 if (t.intr_lat >= 0) {
2217 struct sge_qset *qs =
2218 &adapter->sge.qs[t.qset_idx];
2219
2220 q->coalesce_usecs = t.intr_lat;
2221 t3_update_qset_coalesce(qs, q);
2222 }
2223 if (t.polling >= 0) {
2224 if (adapter->flags & USING_MSIX)
2225 q->polling = t.polling;
2226 else {
2227 /* No polling with INTx for T3A */
2228 if (adapter->params.rev == 0 &&
2229 !(adapter->flags & USING_MSI))
2230 t.polling = 0;
2231
2232 for (i = 0; i < SGE_QSETS; i++) {
2233 q = &adapter->params.sge.
2234 qset[i];
2235 q->polling = t.polling;
2236 }
2237 }
2238 }
d2fe2755
MM		 2239
2240 if (t.lro >= 0) {
2241 if (t.lro)
2242 dev->wanted_features |= NETIF_F_GRO;
2243 else
2244 dev->wanted_features &= ~NETIF_F_GRO;
2245 netdev_update_features(dev);
2246 }
04ecb072 2247
4d22de3e
DLR		 2248 break;
2249 }
2250 case CHELSIO_GET_QSET_PARAMS:{
2251 struct qset_params *q;
2252 struct ch_qset_params t;
8c263761
DLR		 2253 int q1 = pi->first_qset;
2254 int nqsets = pi->nqsets;
2255 int i;
4d22de3e
DLR		 2256
2257 if (copy_from_user(&t, useraddr, sizeof(t)))
2258 return -EFAULT;
8c263761
DLR		 2259
2260 /* Display qsets for all ports when offload enabled */
2261 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2262 q1 = 0;
2263 for_each_port(adapter, i) {
2264 pi = adap2pinfo(adapter, i);
2265 nqsets = pi->first_qset + pi->nqsets;
2266 }
2267 }
2268
2269 if (t.qset_idx >= nqsets)
4d22de3e
DLR		 2270 return -EINVAL;
2271
8c263761 2272 q = &adapter->params.sge.qset[q1 + t.qset_idx];
4d22de3e
DLR		 2273 t.rspq_size = q->rspq_size;
2274 t.txq_size[0] = q->txq_size[0];
2275 t.txq_size[1] = q->txq_size[1];
2276 t.txq_size[2] = q->txq_size[2];
2277 t.fl_size[0] = q->fl_size;
2278 t.fl_size[1] = q->jumbo_size;
2279 t.polling = q->polling;
d2fe2755 2280 t.lro = !!(dev->features & NETIF_F_GRO);
4d22de3e
DLR		 2281 t.intr_lat = q->coalesce_usecs;
2282 t.cong_thres = q->cong_thres;
8c263761
DLR		 2283 t.qnum = q1;
2284
2285 if (adapter->flags & USING_MSIX)
2286 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2287 else
2288 t.vector = adapter->pdev->irq;
4d22de3e
DLR		 2289
2290 if (copy_to_user(useraddr, &t, sizeof(t)))
2291 return -EFAULT;
2292 break;
2293 }
2294 case CHELSIO_SET_QSET_NUM:{
2295 struct ch_reg edata;
4d22de3e
DLR		 2296 unsigned int i, first_qset = 0, other_qsets = 0;
2297
2298 if (!capable(CAP_NET_ADMIN))
2299 return -EPERM;
2300 if (adapter->flags & FULL_INIT_DONE)
2301 return -EBUSY;
2302 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2303 return -EFAULT;
2304 if (edata.val < 1 ||
2305 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2306 return -EINVAL;
2307
2308 for_each_port(adapter, i)
2309 if (adapter->port[i] && adapter->port[i] != dev)
2310 other_qsets += adap2pinfo(adapter, i)->nqsets;
2311
2312 if (edata.val + other_qsets > SGE_QSETS)
2313 return -EINVAL;
2314
2315 pi->nqsets = edata.val;
2316
2317 for_each_port(adapter, i)
2318 if (adapter->port[i]) {
2319 pi = adap2pinfo(adapter, i);
2320 pi->first_qset = first_qset;
2321 first_qset += pi->nqsets;
2322 }
2323 break;
2324 }
2325 case CHELSIO_GET_QSET_NUM:{
2326 struct ch_reg edata;
4d22de3e 2327
49c37c03
DR		 2328 memset(&edata, 0, sizeof(struct ch_reg));
2329
4d22de3e
DLR		 2330 edata.cmd = CHELSIO_GET_QSET_NUM;
2331 edata.val = pi->nqsets;
2332 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2333 return -EFAULT;
2334 break;
2335 }
2336 case CHELSIO_LOAD_FW:{
2337 u8 *fw_data;
2338 struct ch_mem_range t;
2339
1b3aa7af 2340 if (!capable(CAP_SYS_RAWIO))
4d22de3e
DLR		 2341 return -EPERM;
2342 if (copy_from_user(&t, useraddr, sizeof(t)))
2343 return -EFAULT;
1b3aa7af 2344 /* Check t.len sanity ? */
c5dc9a35
JL		 2345 fw_data = memdup_user(useraddr + sizeof(t), t.len);
2346 if (IS_ERR(fw_data))
2347 return PTR_ERR(fw_data);
4d22de3e
DLR		 2348
2349 ret = t3_load_fw(adapter, fw_data, t.len);
2350 kfree(fw_data);
2351 if (ret)
2352 return ret;
2353 break;
2354 }
2355 case CHELSIO_SETMTUTAB:{
2356 struct ch_mtus m;
2357 int i;
2358
2359 if (!is_offload(adapter))
2360 return -EOPNOTSUPP;
2361 if (!capable(CAP_NET_ADMIN))
2362 return -EPERM;
2363 if (offload_running(adapter))
2364 return -EBUSY;
2365 if (copy_from_user(&m, useraddr, sizeof(m)))
2366 return -EFAULT;
2367 if (m.nmtus != NMTUS)
2368 return -EINVAL;
2369 if (m.mtus[0] < 81) /* accommodate SACK */
2370 return -EINVAL;
2371
2372 /* MTUs must be in ascending order */
2373 for (i = 1; i < NMTUS; ++i)
2374 if (m.mtus[i] < m.mtus[i - 1])
2375 return -EINVAL;
2376
2377 memcpy(adapter->params.mtus, m.mtus,
2378 sizeof(adapter->params.mtus));
2379 break;
2380 }
2381 case CHELSIO_GET_PM:{
2382 struct tp_params *p = &adapter->params.tp;
2383 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2384
2385 if (!is_offload(adapter))
2386 return -EOPNOTSUPP;
2387 m.tx_pg_sz = p->tx_pg_size;
2388 m.tx_num_pg = p->tx_num_pgs;
2389 m.rx_pg_sz = p->rx_pg_size;
2390 m.rx_num_pg = p->rx_num_pgs;
2391 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2392 if (copy_to_user(useraddr, &m, sizeof(m)))
2393 return -EFAULT;
2394 break;
2395 }
2396 case CHELSIO_SET_PM:{
2397 struct ch_pm m;
2398 struct tp_params *p = &adapter->params.tp;
2399
2400 if (!is_offload(adapter))
2401 return -EOPNOTSUPP;
2402 if (!capable(CAP_NET_ADMIN))
2403 return -EPERM;
2404 if (adapter->flags & FULL_INIT_DONE)
2405 return -EBUSY;
2406 if (copy_from_user(&m, useraddr, sizeof(m)))
2407 return -EFAULT;
d9da466a 2408 if (!is_power_of_2(m.rx_pg_sz) ||
2409 !is_power_of_2(m.tx_pg_sz))
4d22de3e
DLR		 2410 return -EINVAL; /* not power of 2 */
2411 if (!(m.rx_pg_sz & 0x14000))
2412 return -EINVAL; /* not 16KB or 64KB */
2413 if (!(m.tx_pg_sz & 0x1554000))
2414 return -EINVAL;
2415 if (m.tx_num_pg == -1)
2416 m.tx_num_pg = p->tx_num_pgs;
2417 if (m.rx_num_pg == -1)
2418 m.rx_num_pg = p->rx_num_pgs;
2419 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2420 return -EINVAL;
2421 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2422 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2423 return -EINVAL;
2424 p->rx_pg_size = m.rx_pg_sz;
2425 p->tx_pg_size = m.tx_pg_sz;
2426 p->rx_num_pgs = m.rx_num_pg;
2427 p->tx_num_pgs = m.tx_num_pg;
2428 break;
2429 }
2430 case CHELSIO_GET_MEM:{
2431 struct ch_mem_range t;
2432 struct mc7 *mem;
2433 u64 buf[32];
2434
2435 if (!is_offload(adapter))
2436 return -EOPNOTSUPP;
2437 if (!(adapter->flags & FULL_INIT_DONE))
2438 return -EIO; /* need the memory controllers */
2439 if (copy_from_user(&t, useraddr, sizeof(t)))
2440 return -EFAULT;
2441 if ((t.addr & 7) || (t.len & 7))
2442 return -EINVAL;
2443 if (t.mem_id == MEM_CM)
2444 mem = &adapter->cm;
2445 else if (t.mem_id == MEM_PMRX)
2446 mem = &adapter->pmrx;
2447 else if (t.mem_id == MEM_PMTX)
2448 mem = &adapter->pmtx;
2449 else
2450 return -EINVAL;
2451
2452 /*
1825494a
DLR		 2453 * Version scheme:
2454 * bits 0..9: chip version
2455 * bits 10..15: chip revision
2456 */
4d22de3e
DLR		 2457 t.version = 3 | (adapter->params.rev << 10);
2458 if (copy_to_user(useraddr, &t, sizeof(t)))
2459 return -EFAULT;
2460
2461 /*
2462 * Read 256 bytes at a time as len can be large and we don't
2463 * want to use huge intermediate buffers.
2464 */
2465 useraddr += sizeof(t); /* advance to start of buffer */
2466 while (t.len) {
2467 unsigned int chunk =
2468 min_t(unsigned int, t.len, sizeof(buf));
2469
2470 ret =
2471 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2472 buf);
2473 if (ret)
2474 return ret;
2475 if (copy_to_user(useraddr, buf, chunk))
2476 return -EFAULT;
2477 useraddr += chunk;
2478 t.addr += chunk;
2479 t.len -= chunk;
2480 }
2481 break;
2482 }
2483 case CHELSIO_SET_TRACE_FILTER:{
2484 struct ch_trace t;
2485 const struct trace_params *tp;
2486
2487 if (!capable(CAP_NET_ADMIN))
2488 return -EPERM;
2489 if (!offload_running(adapter))
2490 return -EAGAIN;
2491 if (copy_from_user(&t, useraddr, sizeof(t)))
2492 return -EFAULT;
2493
2494 tp = (const struct trace_params *)&t.sip;
2495 if (t.config_tx)
2496 t3_config_trace_filter(adapter, tp, 0,
2497 t.invert_match,
2498 t.trace_tx);
2499 if (t.config_rx)
2500 t3_config_trace_filter(adapter, tp, 1,
2501 t.invert_match,
2502 t.trace_rx);
2503 break;
2504 }
4d22de3e
DLR		 2505 default:
2506 return -EOPNOTSUPP;
2507 }
2508 return 0;
2509}
2510
2511static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2512{
4d22de3e 2513 struct mii_ioctl_data *data = if_mii(req);
5fbf816f
DLR		 2514 struct port_info *pi = netdev_priv(dev);
2515 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2516
2517 switch (cmd) {
0f07c4ee
BH		 2518 case SIOCGMIIREG:
2519 case SIOCSMIIREG:
2520 /* Convert phy_id from older PRTAD/DEVAD format */
2521 if (is_10G(adapter) &&
2522 !mdio_phy_id_is_c45(data->phy_id) &&
2523 (data->phy_id & 0x1f00) &&
2524 !(data->phy_id & 0xe0e0))
2525 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2526 data->phy_id & 0x1f);
4d22de3e 2527 /* FALLTHRU */
0f07c4ee
BH		 2528 case SIOCGMIIPHY:
2529 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
4d22de3e
DLR		 2530 case SIOCCHIOCTL:
2531 return cxgb_extension_ioctl(dev, req->ifr_data);
2532 default:
2533 return -EOPNOTSUPP;
2534 }
4d22de3e
DLR		 2535}
2536
2537static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2538{
4d22de3e 2539 struct port_info *pi = netdev_priv(dev);
5fbf816f
DLR		 2540 struct adapter *adapter = pi->adapter;
2541 int ret;
4d22de3e 2542
4d22de3e
DLR		 2543 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2544 return ret;
2545 dev->mtu = new_mtu;
2546 init_port_mtus(adapter);
2547 if (adapter->params.rev == 0 && offload_running(adapter))
2548 t3_load_mtus(adapter, adapter->params.mtus,
2549 adapter->params.a_wnd, adapter->params.b_wnd,
2550 adapter->port[0]->mtu);
2551 return 0;
2552}
2553
2554static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2555{
4d22de3e 2556 struct port_info *pi = netdev_priv(dev);
5fbf816f 2557 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2558 struct sockaddr *addr = p;
2559
2560 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 2561 return -EADDRNOTAVAIL;
4d22de3e
DLR		 2562
2563 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
f14d42f3 2564 t3_mac_set_address(&pi->mac, LAN_MAC_IDX, dev->dev_addr);
4d22de3e
DLR		 2565 if (offload_running(adapter))
2566 write_smt_entry(adapter, pi->port_id);
2567 return 0;
2568}
2569
c8f44aff
MM		 2570static netdev_features_t cxgb_fix_features(struct net_device *dev,
2571 netdev_features_t features)
892ef5d8
JP		 2572{
2573 /*
2574 * Since there is no support for separate rx/tx vlan accel
2575 * enable/disable make sure tx flag is always in same state as rx.
2576 */
f646968f
PM		 2577 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2578 features |= NETIF_F_HW_VLAN_CTAG_TX;
892ef5d8 2579 else
f646968f 2580 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
892ef5d8
JP		 2581
2582 return features;
2583}
2584
c8f44aff 2585static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
892ef5d8 2586{
c8f44aff 2587 netdev_features_t changed = dev->features ^ features;
892ef5d8 2588
f646968f 2589 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
892ef5d8
JP		 2590 cxgb_vlan_mode(dev, features);
2591
2592 return 0;
2593}
2594
4d22de3e
DLR		 2595#ifdef CONFIG_NET_POLL_CONTROLLER
2596static void cxgb_netpoll(struct net_device *dev)
2597{
890de332 2598 struct port_info *pi = netdev_priv(dev);
5fbf816f 2599 struct adapter *adapter = pi->adapter;
890de332 2600 int qidx;
4d22de3e 2601
890de332
DLR		 2602 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2603 struct sge_qset *qs = &adapter->sge.qs[qidx];
2604 void *source;
2eab17ab 2605
890de332
DLR		 2606 if (adapter->flags & USING_MSIX)
2607 source = qs;
2608 else
2609 source = adapter;
2610
2611 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2612 }
4d22de3e
DLR		 2613}
2614#endif
2615
2616/*
2617 * Periodic accumulation of MAC statistics.
2618 */
2619static void mac_stats_update(struct adapter *adapter)
2620{
2621 int i;
2622
2623 for_each_port(adapter, i) {
2624 struct net_device *dev = adapter->port[i];
2625 struct port_info *p = netdev_priv(dev);
2626
2627 if (netif_running(dev)) {
2628 spin_lock(&adapter->stats_lock);
2629 t3_mac_update_stats(&p->mac);
2630 spin_unlock(&adapter->stats_lock);
2631 }
2632 }
2633}
2634
2635static void check_link_status(struct adapter *adapter)
2636{
2637 int i;
2638
2639 for_each_port(adapter, i) {
2640 struct net_device *dev = adapter->port[i];
2641 struct port_info *p = netdev_priv(dev);
c22c8149 2642 int link_fault;
4d22de3e 2643
bf792094 2644 spin_lock_irq(&adapter->work_lock);
c22c8149
DLR		 2645 link_fault = p->link_fault;
2646 spin_unlock_irq(&adapter->work_lock);
2647
2648 if (link_fault) {
3851c66c 2649 t3_link_fault(adapter, i);
bf792094
DLR		 2650 continue;
2651 }
bf792094
DLR		 2652
2653 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2654 t3_xgm_intr_disable(adapter, i);
2655 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2656
4d22de3e 2657 t3_link_changed(adapter, i);
bf792094
DLR		 2658 t3_xgm_intr_enable(adapter, i);
2659 }
4d22de3e
DLR		 2660 }
2661}
2662
fc90664e
DLR		 2663static void check_t3b2_mac(struct adapter *adapter)
2664{
2665 int i;
2666
f2d961c9
DLR		 2667 if (!rtnl_trylock()) /* synchronize with ifdown */
2668 return;
2669
fc90664e
DLR		 2670 for_each_port(adapter, i) {
2671 struct net_device *dev = adapter->port[i];
2672 struct port_info *p = netdev_priv(dev);
2673 int status;
2674
2675 if (!netif_running(dev))
2676 continue;
2677
2678 status = 0;
6d6dabac 2679 if (netif_running(dev) && netif_carrier_ok(dev))
fc90664e
DLR		 2680 status = t3b2_mac_watchdog_task(&p->mac);
2681 if (status == 1)
2682 p->mac.stats.num_toggled++;
2683 else if (status == 2) {
2684 struct cmac *mac = &p->mac;
2685
2686 t3_mac_set_mtu(mac, dev->mtu);
f14d42f3 2687 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
fc90664e
DLR		 2688 cxgb_set_rxmode(dev);
2689 t3_link_start(&p->phy, mac, &p->link_config);
2690 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2691 t3_port_intr_enable(adapter, p->port_id);
2692 p->mac.stats.num_resets++;
2693 }
2694 }
2695 rtnl_unlock();
2696}
2697
2698
4d22de3e
DLR		 2699static void t3_adap_check_task(struct work_struct *work)
2700{
2701 struct adapter *adapter = container_of(work, struct adapter,
2702 adap_check_task.work);
2703 const struct adapter_params *p = &adapter->params;
fc882196
DLR		 2704 int port;
2705 unsigned int v, status, reset;
4d22de3e
DLR		 2706
2707 adapter->check_task_cnt++;
2708
3851c66c 2709 check_link_status(adapter);
4d22de3e
DLR		 2710
2711 /* Accumulate MAC stats if needed */
2712 if (!p->linkpoll_period ||
2713 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2714 p->stats_update_period) {
2715 mac_stats_update(adapter);
2716 adapter->check_task_cnt = 0;
2717 }
2718
fc90664e
DLR		 2719 if (p->rev == T3_REV_B2)
2720 check_t3b2_mac(adapter);
2721
fc882196
DLR		 2722 /*
2723 * Scan the XGMAC's to check for various conditions which we want to
2724 * monitor in a periodic polling manner rather than via an interrupt
2725 * condition. This is used for conditions which would otherwise flood
2726 * the system with interrupts and we only really need to know that the
2727 * conditions are "happening" ... For each condition we count the
2728 * detection of the condition and reset it for the next polling loop.
2729 */
2730 for_each_port(adapter, port) {
2731 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2732 u32 cause;
2733
2734 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2735 reset = 0;
2736 if (cause & F_RXFIFO_OVERFLOW) {
2737 mac->stats.rx_fifo_ovfl++;
2738 reset |= F_RXFIFO_OVERFLOW;
2739 }
2740
2741 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2742 }
2743
2744 /*
2745 * We do the same as above for FL_EMPTY interrupts.
2746 */
2747 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2748 reset = 0;
2749
2750 if (status & F_FLEMPTY) {
2751 struct sge_qset *qs = &adapter->sge.qs[0];
2752 int i = 0;
2753
2754 reset |= F_FLEMPTY;
2755
2756 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2757 0xffff;
2758
2759 while (v) {
2760 qs->fl[i].empty += (v & 1);
2761 if (i)
2762 qs++;
2763 i ^= 1;
2764 v >>= 1;
2765 }
2766 }
2767
2768 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2769
4d22de3e 2770 /* Schedule the next check update if any port is active. */
20d3fc11 2771 spin_lock_irq(&adapter->work_lock);
4d22de3e
DLR		 2772 if (adapter->open_device_map & PORT_MASK)
2773 schedule_chk_task(adapter);
20d3fc11 2774 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 2775}
2776
e998f245
SW		 2777static void db_full_task(struct work_struct *work)
2778{
2779 struct adapter *adapter = container_of(work, struct adapter,
2780 db_full_task);
2781
2782 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_FULL, 0);
2783}
2784
2785static void db_empty_task(struct work_struct *work)
2786{
2787 struct adapter *adapter = container_of(work, struct adapter,
2788 db_empty_task);
2789
2790 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_EMPTY, 0);
2791}
2792
2793static void db_drop_task(struct work_struct *work)
2794{
2795 struct adapter *adapter = container_of(work, struct adapter,
2796 db_drop_task);
2797 unsigned long delay = 1000;
2798 unsigned short r;
2799
2800 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_DROP, 0);
2801
2802 /*
2803 * Sleep a while before ringing the driver qset dbs.
2804 * The delay is between 1000-2023 usecs.
2805 */
2806 get_random_bytes(&r, 2);
2807 delay += r & 1023;
2808 set_current_state(TASK_UNINTERRUPTIBLE);
2809 schedule_timeout(usecs_to_jiffies(delay));
2810 ring_dbs(adapter);
2811}
2812
4d22de3e
DLR		 2813/*
2814 * Processes external (PHY) interrupts in process context.
2815 */
2816static void ext_intr_task(struct work_struct *work)
2817{
2818 struct adapter *adapter = container_of(work, struct adapter,
2819 ext_intr_handler_task);
bf792094
DLR		 2820 int i;
2821
2822 /* Disable link fault interrupts */
2823 for_each_port(adapter, i) {
2824 struct net_device *dev = adapter->port[i];
2825 struct port_info *p = netdev_priv(dev);
2826
2827 t3_xgm_intr_disable(adapter, i);
2828 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2829 }
4d22de3e 2830
bf792094 2831 /* Re-enable link fault interrupts */
4d22de3e
DLR		 2832 t3_phy_intr_handler(adapter);
2833
bf792094
DLR		 2834 for_each_port(adapter, i)
2835 t3_xgm_intr_enable(adapter, i);
2836
4d22de3e
DLR		 2837 /* Now reenable external interrupts */
2838 spin_lock_irq(&adapter->work_lock);
2839 if (adapter->slow_intr_mask) {
2840 adapter->slow_intr_mask |= F_T3DBG;
2841 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2842 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2843 adapter->slow_intr_mask);
2844 }
2845 spin_unlock_irq(&adapter->work_lock);
2846}
2847
2848/*
2849 * Interrupt-context handler for external (PHY) interrupts.
2850 */
2851void t3_os_ext_intr_handler(struct adapter *adapter)
2852{
2853 /*
2854 * Schedule a task to handle external interrupts as they may be slow
2855 * and we use a mutex to protect MDIO registers. We disable PHY
2856 * interrupts in the meantime and let the task reenable them when
2857 * it's done.
2858 */
2859 spin_lock(&adapter->work_lock);
2860 if (adapter->slow_intr_mask) {
2861 adapter->slow_intr_mask &= ~F_T3DBG;
2862 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2863 adapter->slow_intr_mask);
2864 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2865 }
2866 spin_unlock(&adapter->work_lock);
2867}
2868
bf792094
DLR		 2869void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2870{
2871 struct net_device *netdev = adapter->port[port_id];
2872 struct port_info *pi = netdev_priv(netdev);
2873
2874 spin_lock(&adapter->work_lock);
2875 pi->link_fault = 1;
bf792094
DLR		 2876 spin_unlock(&adapter->work_lock);
2877}
2878
55bc3228 2879static int t3_adapter_error(struct adapter *adapter, int reset, int on_wq)
20d3fc11
DLR		 2880{
2881 int i, ret = 0;
2882
cb0bc205
DLR		 2883 if (is_offload(adapter) &&
2884 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
fa0d4c11 2885 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
cb0bc205
DLR		 2886 offload_close(&adapter->tdev);
2887 }
2888
20d3fc11
DLR		 2889 /* Stop all ports */
2890 for_each_port(adapter, i) {
2891 struct net_device *netdev = adapter->port[i];
2892
2893 if (netif_running(netdev))
55bc3228 2894 __cxgb_close(netdev, on_wq);
20d3fc11
DLR		 2895 }
2896
20d3fc11
DLR		 2897 /* Stop SGE timers */
2898 t3_stop_sge_timers(adapter);
2899
2900 adapter->flags &= ~FULL_INIT_DONE;
2901
2902 if (reset)
2903 ret = t3_reset_adapter(adapter);
2904
2905 pci_disable_device(adapter->pdev);
2906
2907 return ret;
2908}
2909
2910static int t3_reenable_adapter(struct adapter *adapter)
2911{
2912 if (pci_enable_device(adapter->pdev)) {
2913 dev_err(&adapter->pdev->dev,
2914 "Cannot re-enable PCI device after reset.\n");
2915 goto err;
2916 }
2917 pci_set_master(adapter->pdev);
2918 pci_restore_state(adapter->pdev);
ccdddf50 2919 pci_save_state(adapter->pdev);
20d3fc11
DLR		 2920
2921 /* Free sge resources */
2922 t3_free_sge_resources(adapter);
2923
2924 if (t3_replay_prep_adapter(adapter))
2925 goto err;
2926
2927 return 0;
2928err:
2929 return -1;
2930}
2931
2932static void t3_resume_ports(struct adapter *adapter)
2933{
2934 int i;
2935
2936 /* Restart the ports */
2937 for_each_port(adapter, i) {
2938 struct net_device *netdev = adapter->port[i];
2939
2940 if (netif_running(netdev)) {
2941 if (cxgb_open(netdev)) {
2942 dev_err(&adapter->pdev->dev,
2943 "can't bring device back up"
2944 " after reset\n");
2945 continue;
2946 }
2947 }
2948 }
cb0bc205
DLR		 2949
2950 if (is_offload(adapter) && !ofld_disable)
fa0d4c11 2951 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
20d3fc11
DLR		 2952}
2953
2954/*
2955 * processes a fatal error.
2956 * Bring the ports down, reset the chip, bring the ports back up.
2957 */
2958static void fatal_error_task(struct work_struct *work)
2959{
2960 struct adapter *adapter = container_of(work, struct adapter,
2961 fatal_error_handler_task);
2962 int err = 0;
2963
2964 rtnl_lock();
55bc3228 2965 err = t3_adapter_error(adapter, 1, 1);
20d3fc11
DLR		 2966 if (!err)
2967 err = t3_reenable_adapter(adapter);
2968 if (!err)
2969 t3_resume_ports(adapter);
2970
2971 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2972 rtnl_unlock();
2973}
2974
4d22de3e
DLR		 2975void t3_fatal_err(struct adapter *adapter)
2976{
2977 unsigned int fw_status[4];
2978
2979 if (adapter->flags & FULL_INIT_DONE) {
2980 t3_sge_stop(adapter);
c64c2eae
DLR		 2981 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2982 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2983 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2984 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
20d3fc11
DLR		 2985
2986 spin_lock(&adapter->work_lock);
4d22de3e 2987 t3_intr_disable(adapter);
20d3fc11
DLR		 2988 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2989 spin_unlock(&adapter->work_lock);
4d22de3e
DLR		 2990 }
2991 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2992 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2993 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2994 fw_status[0], fw_status[1],
2995 fw_status[2], fw_status[3]);
4d22de3e
DLR		 2996}
2997
91a6b50c
DLR		 2998/**
2999 * t3_io_error_detected - called when PCI error is detected
3000 * @pdev: Pointer to PCI device
3001 * @state: The current pci connection state
3002 *
3003 * This function is called after a PCI bus error affecting
3004 * this device has been detected.
3005 */
3006static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
3007 pci_channel_state_t state)
3008{
bc4b6b52 3009 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 3010
e8d19370
DLR		 3011 if (state == pci_channel_io_perm_failure)
3012 return PCI_ERS_RESULT_DISCONNECT;
3013
c661c4a2 3014 t3_adapter_error(adapter, 0, 0);
91a6b50c 3015
48c4b6db 3016 /* Request a slot reset. */
91a6b50c
DLR		 3017 return PCI_ERS_RESULT_NEED_RESET;
3018}
3019
3020/**
3021 * t3_io_slot_reset - called after the pci bus has been reset.
3022 * @pdev: Pointer to PCI device
3023 *
3024 * Restart the card from scratch, as if from a cold-boot.
3025 */
3026static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
3027{
bc4b6b52 3028 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 3029
20d3fc11
DLR		 3030 if (!t3_reenable_adapter(adapter))
3031 return PCI_ERS_RESULT_RECOVERED;
91a6b50c 3032
48c4b6db 3033 return PCI_ERS_RESULT_DISCONNECT;
91a6b50c
DLR		 3034}
3035
3036/**
3037 * t3_io_resume - called when traffic can start flowing again.
3038 * @pdev: Pointer to PCI device
3039 *
3040 * This callback is called when the error recovery driver tells us that
3041 * its OK to resume normal operation.
3042 */
3043static void t3_io_resume(struct pci_dev *pdev)
3044{
bc4b6b52 3045 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 3046
68f40c10
DLR		 3047 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
3048 t3_read_reg(adapter, A_PCIE_PEX_ERR));
3049
7cc47d13 3050 rtnl_lock();
20d3fc11 3051 t3_resume_ports(adapter);
7cc47d13 3052 rtnl_unlock();
91a6b50c
DLR		 3053}
3054
3646f0e5 3055static const struct pci_error_handlers t3_err_handler = {
91a6b50c
DLR		 3056 .error_detected = t3_io_error_detected,
3057 .slot_reset = t3_io_slot_reset,
3058 .resume = t3_io_resume,
3059};
3060
8c263761
DLR		 3061/*
3062 * Set the number of qsets based on the number of CPUs and the number of ports,
3063 * not to exceed the number of available qsets, assuming there are enough qsets
3064 * per port in HW.
3065 */
3066static void set_nqsets(struct adapter *adap)
3067{
3068 int i, j = 0;
dbfa6001 3069 int num_cpus = netif_get_num_default_rss_queues();
8c263761 3070 int hwports = adap->params.nports;
5cda9364 3071 int nqsets = adap->msix_nvectors - 1;
8c263761 3072
f9ee3882 3073 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
8c263761
DLR		 3074 if (hwports == 2 &&
3075 (hwports * nqsets > SGE_QSETS ||
3076 num_cpus >= nqsets / hwports))
3077 nqsets /= hwports;
3078 if (nqsets > num_cpus)
3079 nqsets = num_cpus;
3080 if (nqsets < 1 || hwports == 4)
3081 nqsets = 1;
3082 } else
3083 nqsets = 1;
3084
3085 for_each_port(adap, i) {
3086 struct port_info *pi = adap2pinfo(adap, i);
3087
3088 pi->first_qset = j;
3089 pi->nqsets = nqsets;
3090 j = pi->first_qset + nqsets;
3091
3092 dev_info(&adap->pdev->dev,
3093 "Port %d using %d queue sets.\n", i, nqsets);
3094 }
3095}
3096
2109eaab 3097static int cxgb_enable_msix(struct adapter *adap)
4d22de3e
DLR		 3098{
3099 struct msix_entry entries[SGE_QSETS + 1];
5cda9364 3100 int vectors;
fc1d0bf1 3101 int i;
4d22de3e 3102
5cda9364
DLR		 3103 vectors = ARRAY_SIZE(entries);
3104 for (i = 0; i < vectors; ++i)
4d22de3e
DLR		 3105 entries[i].entry = i;
3106
fc1d0bf1
AG		 3107 vectors = pci_enable_msix_range(adap->pdev, entries,
3108 adap->params.nports + 1, vectors);
3109 if (vectors < 0)
3110 return vectors;
5cda9364 3111
fc1d0bf1
AG		 3112 for (i = 0; i < vectors; ++i)
3113 adap->msix_info[i].vec = entries[i].vector;
3114 adap->msix_nvectors = vectors;
5cda9364 3115
fc1d0bf1 3116 return 0;
4d22de3e
DLR		 3117}
3118
1dd06ae8 3119static void print_port_info(struct adapter *adap, const struct adapter_info *ai)
4d22de3e
DLR		 3120{
3121 static const char *pci_variant[] = {
3122 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
3123 };
3124
3125 int i;
3126 char buf[80];
3127
3128 if (is_pcie(adap))
3129 snprintf(buf, sizeof(buf), "%s x%d",
3130 pci_variant[adap->params.pci.variant],
3131 adap->params.pci.width);
3132 else
3133 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
3134 pci_variant[adap->params.pci.variant],
3135 adap->params.pci.speed, adap->params.pci.width);
3136
3137 for_each_port(adap, i) {
3138 struct net_device *dev = adap->port[i];
3139 const struct port_info *pi = netdev_priv(dev);
3140
3141 if (!test_bit(i, &adap->registered_device_map))
3142 continue;
428ac43f
JP		 3143 netdev_info(dev, "%s %s %sNIC (rev %d) %s%s\n",
3144 ai->desc, pi->phy.desc,
3145 is_offload(adap) ? "R" : "", adap->params.rev, buf,
3146 (adap->flags & USING_MSIX) ? " MSI-X" :
3147 (adap->flags & USING_MSI) ? " MSI" : "");
4d22de3e 3148 if (adap->name == dev->name && adap->params.vpd.mclk)
428ac43f 3149 pr_info("%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
4d22de3e
DLR		 3150 adap->name, t3_mc7_size(&adap->cm) >> 20,
3151 t3_mc7_size(&adap->pmtx) >> 20,
167cdf5f
DLR		 3152 t3_mc7_size(&adap->pmrx) >> 20,
3153 adap->params.vpd.sn);
4d22de3e
DLR		 3154 }
3155}
3156
dd752696
SH		 3157static const struct net_device_ops cxgb_netdev_ops = {
3158 .ndo_open = cxgb_open,
3159 .ndo_stop = cxgb_close,
43a944f3 3160 .ndo_start_xmit = t3_eth_xmit,
dd752696
SH		 3161 .ndo_get_stats = cxgb_get_stats,
3162 .ndo_validate_addr = eth_validate_addr,
afc4b13d 3163 .ndo_set_rx_mode = cxgb_set_rxmode,
dd752696
SH		 3164 .ndo_do_ioctl = cxgb_ioctl,
3165 .ndo_change_mtu = cxgb_change_mtu,
3166 .ndo_set_mac_address = cxgb_set_mac_addr,
892ef5d8
JP		 3167 .ndo_fix_features = cxgb_fix_features,
3168 .ndo_set_features = cxgb_set_features,
dd752696
SH		 3169#ifdef CONFIG_NET_POLL_CONTROLLER
3170 .ndo_poll_controller = cxgb_netpoll,
3171#endif
3172};
3173
2109eaab 3174static void cxgb3_init_iscsi_mac(struct net_device *dev)
f14d42f3
KX		 3175{
3176 struct port_info *pi = netdev_priv(dev);
3177
3178 memcpy(pi->iscsic.mac_addr, dev->dev_addr, ETH_ALEN);
3179 pi->iscsic.mac_addr[3] |= 0x80;
3180}
3181
1d962ecf 3182#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
3183#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
3184 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
1dd06ae8 3185static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4d22de3e 3186{
4d22de3e 3187 int i, err, pci_using_dac = 0;
68f40c10 3188 resource_size_t mmio_start, mmio_len;
4d22de3e
DLR		 3189 const struct adapter_info *ai;
3190 struct adapter *adapter = NULL;
3191 struct port_info *pi;
3192
428ac43f 3193 pr_info_once("%s - version %s\n", DRV_DESC, DRV_VERSION);
4d22de3e
DLR		 3194
3195 if (!cxgb3_wq) {
3196 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3197 if (!cxgb3_wq) {
428ac43f 3198 pr_err("cannot initialize work queue\n");
4d22de3e
DLR		 3199 return -ENOMEM;
3200 }
3201 }
3202
7aaaaa1e 3203 err = pci_enable_device(pdev);
4d22de3e 3204 if (err) {
7aaaaa1e
KV		 3205 dev_err(&pdev->dev, "cannot enable PCI device\n");
3206 goto out;
4d22de3e
DLR		 3207 }
3208
7aaaaa1e 3209 err = pci_request_regions(pdev, DRV_NAME);
4d22de3e 3210 if (err) {
7aaaaa1e
KV		 3211 /* Just info, some other driver may have claimed the device. */
3212 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3213 goto out_disable_device;
4d22de3e
DLR		 3214 }
3215
6a35528a 3216 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4d22de3e 3217 pci_using_dac = 1;
6a35528a 3218 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4d22de3e
DLR		 3219 if (err) {
3220 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3221 "coherent allocations\n");
7aaaaa1e 3222 goto out_release_regions;
4d22de3e 3223 }
284901a9 3224 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
4d22de3e 3225 dev_err(&pdev->dev, "no usable DMA configuration\n");
7aaaaa1e 3226 goto out_release_regions;
4d22de3e
DLR		 3227 }
3228
3229 pci_set_master(pdev);
204e2f98 3230 pci_save_state(pdev);
4d22de3e
DLR		 3231
3232 mmio_start = pci_resource_start(pdev, 0);
3233 mmio_len = pci_resource_len(pdev, 0);
3234 ai = t3_get_adapter_info(ent->driver_data);
3235
3236 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3237 if (!adapter) {
3238 err = -ENOMEM;
7aaaaa1e 3239 goto out_release_regions;
4d22de3e
DLR		 3240 }
3241
74b793e1
DLR		 3242 adapter->nofail_skb =
3243 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3244 if (!adapter->nofail_skb) {
3245 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3246 err = -ENOMEM;
3247 goto out_free_adapter;
3248 }
3249
4d22de3e
DLR		 3250 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3251 if (!adapter->regs) {
3252 dev_err(&pdev->dev, "cannot map device registers\n");
3253 err = -ENOMEM;
3254 goto out_free_adapter;
3255 }
3256
3257 adapter->pdev = pdev;
3258 adapter->name = pci_name(pdev);
3259 adapter->msg_enable = dflt_msg_enable;
3260 adapter->mmio_len = mmio_len;
3261
3262 mutex_init(&adapter->mdio_lock);
3263 spin_lock_init(&adapter->work_lock);
3264 spin_lock_init(&adapter->stats_lock);
3265
3266 INIT_LIST_HEAD(&adapter->adapter_list);
3267 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
20d3fc11 3268 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
e998f245
SW		 3269
3270 INIT_WORK(&adapter->db_full_task, db_full_task);
3271 INIT_WORK(&adapter->db_empty_task, db_empty_task);
3272 INIT_WORK(&adapter->db_drop_task, db_drop_task);
3273
4d22de3e
DLR		 3274 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3275
952cdf33 3276 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
4d22de3e
DLR		 3277 struct net_device *netdev;
3278
82ad3329 3279 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
4d22de3e
DLR		 3280 if (!netdev) {
3281 err = -ENOMEM;
3282 goto out_free_dev;
3283 }
3284
4d22de3e
DLR		 3285 SET_NETDEV_DEV(netdev, &pdev->dev);
3286
3287 adapter->port[i] = netdev;
3288 pi = netdev_priv(netdev);
5fbf816f 3289 pi->adapter = adapter;
4d22de3e
DLR		 3290 pi->port_id = i;
3291 netif_carrier_off(netdev);
3292 netdev->irq = pdev->irq;
3293 netdev->mem_start = mmio_start;
3294 netdev->mem_end = mmio_start + mmio_len - 1;
d2fe2755 3295 netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
f646968f
PM		 3296 NETIF_F_TSO | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
3297 netdev->features |= netdev->hw_features |
3298 NETIF_F_HW_VLAN_CTAG_TX;
1d962ecf 3299 netdev->vlan_features |= netdev->features & VLAN_FEAT;
4d22de3e
DLR		 3300 if (pci_using_dac)
3301 netdev->features |= NETIF_F_HIGHDMA;
3302
dd752696 3303 netdev->netdev_ops = &cxgb_netdev_ops;
7ad24ea4 3304 netdev->ethtool_ops = &cxgb_ethtool_ops;
d894be57
JW		 3305 netdev->min_mtu = 81;
3306 netdev->max_mtu = ETH_MAX_MTU;
4d22de3e
DLR		 3307 }
3308
5fbf816f 3309 pci_set_drvdata(pdev, adapter);
4d22de3e
DLR		 3310 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3311 err = -ENODEV;
3312 goto out_free_dev;
3313 }
2eab17ab 3314
4d22de3e
DLR		 3315 /*
3316 * The card is now ready to go. If any errors occur during device
3317 * registration we do not fail the whole card but rather proceed only
3318 * with the ports we manage to register successfully. However we must
3319 * register at least one net device.
3320 */
3321 for_each_port(adapter, i) {
3322 err = register_netdev(adapter->port[i]);
3323 if (err)
3324 dev_warn(&pdev->dev,
3325 "cannot register net device %s, skipping\n",
3326 adapter->port[i]->name);
3327 else {
3328 /*
3329 * Change the name we use for messages to the name of
3330 * the first successfully registered interface.
3331 */
3332 if (!adapter->registered_device_map)
3333 adapter->name = adapter->port[i]->name;
3334
3335 __set_bit(i, &adapter->registered_device_map);
3336 }
3337 }
3338 if (!adapter->registered_device_map) {
3339 dev_err(&pdev->dev, "could not register any net devices\n");
3340 goto out_free_dev;
3341 }
3342
f14d42f3
KX		 3343 for_each_port(adapter, i)
3344 cxgb3_init_iscsi_mac(adapter->port[i]);
3345
4d22de3e
DLR		 3346 /* Driver's ready. Reflect it on LEDs */
3347 t3_led_ready(adapter);
3348
3349 if (is_offload(adapter)) {
3350 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3351 cxgb3_adapter_ofld(adapter);
3352 }
3353
3354 /* See what interrupts we'll be using */
3355 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3356 adapter->flags |= USING_MSIX;
3357 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3358 adapter->flags |= USING_MSI;
3359
8c263761
DLR		 3360 set_nqsets(adapter);
3361
0ee8d33c 3362 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3363 &cxgb3_attr_group);
3364
3365 print_port_info(adapter, ai);
3366 return 0;
3367
3368out_free_dev:
3369 iounmap(adapter->regs);
952cdf33 3370 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
4d22de3e
DLR		 3371 if (adapter->port[i])
3372 free_netdev(adapter->port[i]);
3373
3374out_free_adapter:
3375 kfree(adapter);
3376
4d22de3e
DLR		 3377out_release_regions:
3378 pci_release_regions(pdev);
7aaaaa1e
KV		 3379out_disable_device:
3380 pci_disable_device(pdev);
7aaaaa1e 3381out:
4d22de3e
DLR		 3382 return err;
3383}
3384
2109eaab 3385static void remove_one(struct pci_dev *pdev)
4d22de3e 3386{
5fbf816f 3387 struct adapter *adapter = pci_get_drvdata(pdev);
4d22de3e 3388
5fbf816f 3389 if (adapter) {
4d22de3e 3390 int i;
4d22de3e
DLR		 3391
3392 t3_sge_stop(adapter);
0ee8d33c 3393 sysfs_remove_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3394 &cxgb3_attr_group);
3395
4d22de3e
DLR		 3396 if (is_offload(adapter)) {
3397 cxgb3_adapter_unofld(adapter);
3398 if (test_bit(OFFLOAD_DEVMAP_BIT,
3399 &adapter->open_device_map))
3400 offload_close(&adapter->tdev);
3401 }
3402
67d92ab7
DLR		 3403 for_each_port(adapter, i)
3404 if (test_bit(i, &adapter->registered_device_map))
3405 unregister_netdev(adapter->port[i]);
3406
0ca41c04 3407 t3_stop_sge_timers(adapter);
4d22de3e
DLR		 3408 t3_free_sge_resources(adapter);
3409 cxgb_disable_msi(adapter);
3410
4d22de3e
DLR		 3411 for_each_port(adapter, i)
3412 if (adapter->port[i])
3413 free_netdev(adapter->port[i]);
3414
3415 iounmap(adapter->regs);
74b793e1
DLR		 3416 if (adapter->nofail_skb)
3417 kfree_skb(adapter->nofail_skb);
4d22de3e
DLR		 3418 kfree(adapter);
3419 pci_release_regions(pdev);
3420 pci_disable_device(pdev);
4d22de3e
DLR		 3421 }
3422}
3423
3424static struct pci_driver driver = {
3425 .name = DRV_NAME,
3426 .id_table = cxgb3_pci_tbl,
3427 .probe = init_one,
2109eaab 3428 .remove = remove_one,
91a6b50c 3429 .err_handler = &t3_err_handler,
4d22de3e
DLR		 3430};
3431
3432static int __init cxgb3_init_module(void)
3433{
3434 int ret;
3435
3436 cxgb3_offload_init();
3437
3438 ret = pci_register_driver(&driver);
3439 return ret;
3440}
3441
3442static void __exit cxgb3_cleanup_module(void)
3443{
3444 pci_unregister_driver(&driver);
3445 if (cxgb3_wq)
3446 destroy_workqueue(cxgb3_wq);
3447}
3448
3449module_init(cxgb3_init_module);
3450module_exit(cxgb3_cleanup_module);
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