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625ba2c2 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
b72a32da | 4 | * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. |
625ba2c2 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #ifndef __CXGB4_H__ | |
36 | #define __CXGB4_H__ | |
37 | ||
dca4faeb VP |
38 | #include "t4_hw.h" |
39 | ||
625ba2c2 DM |
40 | #include <linux/bitops.h> |
41 | #include <linux/cache.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/list.h> | |
44 | #include <linux/netdevice.h> | |
45 | #include <linux/pci.h> | |
46 | #include <linux/spinlock.h> | |
47 | #include <linux/timer.h> | |
c0b8b992 | 48 | #include <linux/vmalloc.h> |
0eb71a9d | 49 | #include <linux/rhashtable.h> |
098ef6c2 | 50 | #include <linux/etherdevice.h> |
5e2a5ebc | 51 | #include <linux/net_tstamp.h> |
a4569504 AG |
52 | #include <linux/ptp_clock_kernel.h> |
53 | #include <linux/ptp_classify.h> | |
1dde532d | 54 | #include <linux/crash_dump.h> |
b1871915 | 55 | #include <linux/thermal.h> |
625ba2c2 | 56 | #include <asm/io.h> |
27999805 | 57 | #include "t4_chip_type.h" |
625ba2c2 | 58 | #include "cxgb4_uld.h" |
625ba2c2 | 59 | |
3069ee9b | 60 | #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) |
94cdb8bb HS |
61 | extern struct list_head adapter_list; |
62 | extern struct mutex uld_mutex; | |
3069ee9b | 63 | |
a6ec572b AG |
64 | /* Suspend an Ethernet Tx queue with fewer available descriptors than this. |
65 | * This is the same as calc_tx_descs() for a TSO packet with | |
66 | * nr_frags == MAX_SKB_FRAGS. | |
67 | */ | |
68 | #define ETHTXQ_STOP_THRES \ | |
69 | (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) | |
70 | ||
625ba2c2 | 71 | enum { |
098ef6c2 HS |
72 | MAX_NPORTS = 4, /* max # of ports */ |
73 | SERNUM_LEN = 24, /* Serial # length */ | |
74 | EC_LEN = 16, /* E/C length */ | |
75 | ID_LEN = 16, /* ID length */ | |
76 | PN_LEN = 16, /* Part Number length */ | |
77 | MACADDR_LEN = 12, /* MAC Address length */ | |
625ba2c2 DM |
78 | }; |
79 | ||
812034f1 HS |
80 | enum { |
81 | T4_REGMAP_SIZE = (160 * 1024), | |
82 | T5_REGMAP_SIZE = (332 * 1024), | |
83 | }; | |
84 | ||
625ba2c2 DM |
85 | enum { |
86 | MEM_EDC0, | |
87 | MEM_EDC1, | |
2422d9a3 SR |
88 | MEM_MC, |
89 | MEM_MC0 = MEM_MC, | |
4db0401f RL |
90 | MEM_MC1, |
91 | MEM_HMA, | |
625ba2c2 DM |
92 | }; |
93 | ||
3069ee9b | 94 | enum { |
3eb4afbf VP |
95 | MEMWIN0_APERTURE = 2048, |
96 | MEMWIN0_BASE = 0x1b800, | |
3069ee9b VP |
97 | MEMWIN1_APERTURE = 32768, |
98 | MEMWIN1_BASE = 0x28000, | |
2422d9a3 | 99 | MEMWIN1_BASE_T5 = 0x52000, |
3eb4afbf VP |
100 | MEMWIN2_APERTURE = 65536, |
101 | MEMWIN2_BASE = 0x30000, | |
0abfd152 HS |
102 | MEMWIN2_APERTURE_T5 = 131072, |
103 | MEMWIN2_BASE_T5 = 0x60000, | |
3069ee9b VP |
104 | }; |
105 | ||
625ba2c2 DM |
106 | enum dev_master { |
107 | MASTER_CANT, | |
108 | MASTER_MAY, | |
109 | MASTER_MUST | |
110 | }; | |
111 | ||
112 | enum dev_state { | |
113 | DEV_STATE_UNINIT, | |
114 | DEV_STATE_INIT, | |
115 | DEV_STATE_ERR | |
116 | }; | |
117 | ||
c3168cab | 118 | enum cc_pause { |
625ba2c2 DM |
119 | PAUSE_RX = 1 << 0, |
120 | PAUSE_TX = 1 << 1, | |
121 | PAUSE_AUTONEG = 1 << 2 | |
122 | }; | |
123 | ||
c3168cab | 124 | enum cc_fec { |
3bb4858f GG |
125 | FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ |
126 | FEC_RS = 1 << 1, /* Reed-Solomon */ | |
127 | FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ | |
128 | }; | |
129 | ||
625ba2c2 DM |
130 | struct port_stats { |
131 | u64 tx_octets; /* total # of octets in good frames */ | |
132 | u64 tx_frames; /* all good frames */ | |
133 | u64 tx_bcast_frames; /* all broadcast frames */ | |
134 | u64 tx_mcast_frames; /* all multicast frames */ | |
135 | u64 tx_ucast_frames; /* all unicast frames */ | |
136 | u64 tx_error_frames; /* all error frames */ | |
137 | ||
138 | u64 tx_frames_64; /* # of Tx frames in a particular range */ | |
139 | u64 tx_frames_65_127; | |
140 | u64 tx_frames_128_255; | |
141 | u64 tx_frames_256_511; | |
142 | u64 tx_frames_512_1023; | |
143 | u64 tx_frames_1024_1518; | |
144 | u64 tx_frames_1519_max; | |
145 | ||
146 | u64 tx_drop; /* # of dropped Tx frames */ | |
147 | u64 tx_pause; /* # of transmitted pause frames */ | |
148 | u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ | |
149 | u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ | |
150 | u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ | |
151 | u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ | |
152 | u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ | |
153 | u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ | |
154 | u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ | |
155 | u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ | |
156 | ||
157 | u64 rx_octets; /* total # of octets in good frames */ | |
158 | u64 rx_frames; /* all good frames */ | |
159 | u64 rx_bcast_frames; /* all broadcast frames */ | |
160 | u64 rx_mcast_frames; /* all multicast frames */ | |
161 | u64 rx_ucast_frames; /* all unicast frames */ | |
162 | u64 rx_too_long; /* # of frames exceeding MTU */ | |
163 | u64 rx_jabber; /* # of jabber frames */ | |
164 | u64 rx_fcs_err; /* # of received frames with bad FCS */ | |
165 | u64 rx_len_err; /* # of received frames with length error */ | |
166 | u64 rx_symbol_err; /* symbol errors */ | |
167 | u64 rx_runt; /* # of short frames */ | |
168 | ||
169 | u64 rx_frames_64; /* # of Rx frames in a particular range */ | |
170 | u64 rx_frames_65_127; | |
171 | u64 rx_frames_128_255; | |
172 | u64 rx_frames_256_511; | |
173 | u64 rx_frames_512_1023; | |
174 | u64 rx_frames_1024_1518; | |
175 | u64 rx_frames_1519_max; | |
176 | ||
177 | u64 rx_pause; /* # of received pause frames */ | |
178 | u64 rx_ppp0; /* # of received PPP prio 0 frames */ | |
179 | u64 rx_ppp1; /* # of received PPP prio 1 frames */ | |
180 | u64 rx_ppp2; /* # of received PPP prio 2 frames */ | |
181 | u64 rx_ppp3; /* # of received PPP prio 3 frames */ | |
182 | u64 rx_ppp4; /* # of received PPP prio 4 frames */ | |
183 | u64 rx_ppp5; /* # of received PPP prio 5 frames */ | |
184 | u64 rx_ppp6; /* # of received PPP prio 6 frames */ | |
185 | u64 rx_ppp7; /* # of received PPP prio 7 frames */ | |
186 | ||
187 | u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ | |
188 | u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ | |
189 | u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ | |
190 | u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ | |
191 | u64 rx_trunc0; /* buffer-group 0 truncated packets */ | |
192 | u64 rx_trunc1; /* buffer-group 1 truncated packets */ | |
193 | u64 rx_trunc2; /* buffer-group 2 truncated packets */ | |
194 | u64 rx_trunc3; /* buffer-group 3 truncated packets */ | |
195 | }; | |
196 | ||
197 | struct lb_port_stats { | |
198 | u64 octets; | |
199 | u64 frames; | |
200 | u64 bcast_frames; | |
201 | u64 mcast_frames; | |
202 | u64 ucast_frames; | |
203 | u64 error_frames; | |
204 | ||
205 | u64 frames_64; | |
206 | u64 frames_65_127; | |
207 | u64 frames_128_255; | |
208 | u64 frames_256_511; | |
209 | u64 frames_512_1023; | |
210 | u64 frames_1024_1518; | |
211 | u64 frames_1519_max; | |
212 | ||
213 | u64 drop; | |
214 | ||
215 | u64 ovflow0; | |
216 | u64 ovflow1; | |
217 | u64 ovflow2; | |
218 | u64 ovflow3; | |
219 | u64 trunc0; | |
220 | u64 trunc1; | |
221 | u64 trunc2; | |
222 | u64 trunc3; | |
223 | }; | |
224 | ||
225 | struct tp_tcp_stats { | |
a4cfd929 HS |
226 | u32 tcp_out_rsts; |
227 | u64 tcp_in_segs; | |
228 | u64 tcp_out_segs; | |
229 | u64 tcp_retrans_segs; | |
230 | }; | |
231 | ||
232 | struct tp_usm_stats { | |
233 | u32 frames; | |
234 | u32 drops; | |
235 | u64 octets; | |
625ba2c2 DM |
236 | }; |
237 | ||
a6222975 HS |
238 | struct tp_fcoe_stats { |
239 | u32 frames_ddp; | |
240 | u32 frames_drop; | |
241 | u64 octets_ddp; | |
625ba2c2 DM |
242 | }; |
243 | ||
244 | struct tp_err_stats { | |
a4cfd929 HS |
245 | u32 mac_in_errs[4]; |
246 | u32 hdr_in_errs[4]; | |
247 | u32 tcp_in_errs[4]; | |
248 | u32 tnl_cong_drops[4]; | |
249 | u32 ofld_chan_drops[4]; | |
250 | u32 tnl_tx_drops[4]; | |
251 | u32 ofld_vlan_drops[4]; | |
252 | u32 tcp6_in_errs[4]; | |
253 | u32 ofld_no_neigh; | |
254 | u32 ofld_cong_defer; | |
255 | }; | |
256 | ||
a6222975 HS |
257 | struct tp_cpl_stats { |
258 | u32 req[4]; | |
259 | u32 rsp[4]; | |
260 | }; | |
261 | ||
a4cfd929 HS |
262 | struct tp_rdma_stats { |
263 | u32 rqe_dfr_pkt; | |
264 | u32 rqe_dfr_mod; | |
625ba2c2 DM |
265 | }; |
266 | ||
e85c9a7a HS |
267 | struct sge_params { |
268 | u32 hps; /* host page size for our PF/VF */ | |
269 | u32 eq_qpp; /* egress queues/page for our PF/VF */ | |
270 | u32 iq_qpp; /* egress queues/page for our PF/VF */ | |
271 | }; | |
272 | ||
625ba2c2 | 273 | struct tp_params { |
625ba2c2 | 274 | unsigned int tre; /* log2 of core clocks per TP tick */ |
2d277b3b | 275 | unsigned int la_mask; /* what events are recorded by TP LA */ |
dca4faeb VP |
276 | unsigned short tx_modq_map; /* TX modulation scheduler queue to */ |
277 | /* channel map */ | |
636f9d37 VP |
278 | |
279 | uint32_t dack_re; /* DACK timer resolution */ | |
280 | unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ | |
dcf7b6f5 KS |
281 | |
282 | u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ | |
dcf10ec7 | 283 | u32 filter_mask; |
dcf7b6f5 KS |
284 | u32 ingress_config; /* cached TP_INGRESS_CONFIG */ |
285 | ||
8eb9f2f9 A |
286 | /* cached TP_OUT_CONFIG compressed error vector |
287 | * and passing outer header info for encapsulated packets. | |
288 | */ | |
289 | int rx_pkt_encap; | |
290 | ||
dcf7b6f5 KS |
291 | /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a |
292 | * subset of the set of fields which may be present in the Compressed | |
293 | * Filter Tuple portion of filters and TCP TCB connections. The | |
294 | * fields which are present are controlled by the TP_VLAN_PRI_MAP. | |
295 | * Since a variable number of fields may or may not be present, their | |
296 | * shifted field positions within the Compressed Filter Tuple may | |
297 | * vary, or not even be present if the field isn't selected in | |
298 | * TP_VLAN_PRI_MAP. Since some of these fields are needed in various | |
299 | * places we store their offsets here, or a -1 if the field isn't | |
300 | * present. | |
301 | */ | |
0ba9a3b6 | 302 | int fcoe_shift; |
dcf7b6f5 | 303 | int port_shift; |
0ba9a3b6 KS |
304 | int vnic_shift; |
305 | int vlan_shift; | |
306 | int tos_shift; | |
dcf7b6f5 | 307 | int protocol_shift; |
0ba9a3b6 KS |
308 | int ethertype_shift; |
309 | int macmatch_shift; | |
310 | int matchtype_shift; | |
311 | int frag_shift; | |
312 | ||
313 | u64 hash_filter_mask; | |
625ba2c2 DM |
314 | }; |
315 | ||
316 | struct vpd_params { | |
317 | unsigned int cclk; | |
318 | u8 ec[EC_LEN + 1]; | |
319 | u8 sn[SERNUM_LEN + 1]; | |
320 | u8 id[ID_LEN + 1]; | |
a94cd705 | 321 | u8 pn[PN_LEN + 1]; |
098ef6c2 | 322 | u8 na[MACADDR_LEN + 1]; |
625ba2c2 DM |
323 | }; |
324 | ||
0eaec62a CL |
325 | /* Maximum resources provisioned for a PCI PF. |
326 | */ | |
327 | struct pf_resources { | |
328 | unsigned int nvi; /* N virtual interfaces */ | |
329 | unsigned int neq; /* N egress Qs */ | |
330 | unsigned int nethctrl; /* N egress ETH or CTRL Qs */ | |
331 | unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ | |
332 | unsigned int niq; /* N ingress Qs */ | |
333 | unsigned int tc; /* PCI-E traffic class */ | |
334 | unsigned int pmask; /* port access rights mask */ | |
335 | unsigned int nexactf; /* N exact MPS filters */ | |
336 | unsigned int r_caps; /* read capabilities */ | |
337 | unsigned int wx_caps; /* write/execute capabilities */ | |
338 | }; | |
339 | ||
625ba2c2 | 340 | struct pci_params { |
baf50868 | 341 | unsigned int vpd_cap_addr; |
625ba2c2 DM |
342 | unsigned char speed; |
343 | unsigned char width; | |
344 | }; | |
345 | ||
49aa284f HS |
346 | struct devlog_params { |
347 | u32 memtype; /* which memory (EDC0, EDC1, MC) */ | |
348 | u32 start; /* start of log in firmware memory */ | |
349 | u32 size; /* size of log */ | |
350 | }; | |
351 | ||
3ccc6cf7 HS |
352 | /* Stores chip specific parameters */ |
353 | struct arch_specific_params { | |
354 | u8 nchan; | |
44588560 | 355 | u8 pm_stats_cnt; |
2216d014 | 356 | u8 cng_ch_bits_log; /* congestion channel map bits width */ |
3ccc6cf7 HS |
357 | u16 mps_rplc_size; |
358 | u16 vfcount; | |
359 | u32 sge_fl_db; | |
360 | u16 mps_tcam_size; | |
361 | }; | |
362 | ||
625ba2c2 | 363 | struct adapter_params { |
e85c9a7a | 364 | struct sge_params sge; |
625ba2c2 DM |
365 | struct tp_params tp; |
366 | struct vpd_params vpd; | |
0eaec62a | 367 | struct pf_resources pfres; |
625ba2c2 | 368 | struct pci_params pci; |
49aa284f HS |
369 | struct devlog_params devlog; |
370 | enum pcie_memwin drv_memwin; | |
625ba2c2 | 371 | |
f1ff24aa HS |
372 | unsigned int cim_la_size; |
373 | ||
900a6596 DM |
374 | unsigned int sf_size; /* serial flash size in bytes */ |
375 | unsigned int sf_nsec; /* # of flash sectors */ | |
900a6596 | 376 | |
760446f9 GG |
377 | unsigned int fw_vers; /* firmware version */ |
378 | unsigned int bs_vers; /* bootstrap version */ | |
379 | unsigned int tp_vers; /* TP microcode version */ | |
380 | unsigned int er_vers; /* expansion ROM version */ | |
381 | unsigned int scfg_vers; /* Serial Configuration version */ | |
382 | unsigned int vpd_vers; /* VPD Version */ | |
625ba2c2 DM |
383 | u8 api_vers[7]; |
384 | ||
385 | unsigned short mtus[NMTUS]; | |
386 | unsigned short a_wnd[NCCTRL_WIN]; | |
387 | unsigned short b_wnd[NCCTRL_WIN]; | |
388 | ||
389 | unsigned char nports; /* # of ethernet ports */ | |
390 | unsigned char portvec; | |
d14807dd | 391 | enum chip_type chip; /* chip code */ |
3ccc6cf7 | 392 | struct arch_specific_params arch; /* chip specific params */ |
625ba2c2 | 393 | unsigned char offload; |
94cdb8bb | 394 | unsigned char crypto; /* HW capability for crypto */ |
ab0367ea | 395 | unsigned char ethofld; /* QoS support */ |
625ba2c2 | 396 | |
9a4da2cd | 397 | unsigned char bypass; |
5c31254e | 398 | unsigned char hash_filter; |
9a4da2cd | 399 | |
625ba2c2 | 400 | unsigned int ofldq_wr_cred; |
1ac0f095 | 401 | bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ |
4c2c5763 | 402 | |
b72a32da | 403 | unsigned int nsched_cls; /* number of traffic classes */ |
4c2c5763 HS |
404 | unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ |
405 | unsigned int max_ird_adapter; /* Max read depth per adapter */ | |
086de575 | 406 | bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ |
c3168cab | 407 | u8 fw_caps_support; /* 32-bit Port Capabilities */ |
0ff90994 | 408 | bool filter2_wr_support; /* FW support for FILTER2_WR */ |
02d805dc | 409 | unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ |
8f46d467 AV |
410 | |
411 | /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is | |
412 | * used by the Port | |
413 | */ | |
414 | u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ | |
43db9296 | 415 | bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ |
f3910c62 | 416 | bool write_cmpl_support; /* FW supports WRITE_CMPL */ |
625ba2c2 DM |
417 | }; |
418 | ||
a3bfb617 HS |
419 | /* State needed to monitor the forward progress of SGE Ingress DMA activities |
420 | * and possible hangs. | |
421 | */ | |
422 | struct sge_idma_monitor_state { | |
423 | unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ | |
424 | unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ | |
425 | unsigned int idma_state[2]; /* IDMA Hang detect state */ | |
426 | unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ | |
427 | unsigned int idma_warn[2]; /* time to warning in HZ */ | |
428 | }; | |
429 | ||
7f080c3f HS |
430 | /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. |
431 | * The access and execute times are signed in order to accommodate negative | |
432 | * error returns. | |
433 | */ | |
434 | struct mbox_cmd { | |
435 | u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ | |
436 | u64 timestamp; /* OS-dependent timestamp */ | |
437 | u32 seqno; /* sequence number */ | |
438 | s16 access; /* time (ms) to access mailbox */ | |
439 | s16 execute; /* time (ms) to execute */ | |
440 | }; | |
441 | ||
442 | struct mbox_cmd_log { | |
443 | unsigned int size; /* number of entries in the log */ | |
444 | unsigned int cursor; /* next position in the log to write */ | |
445 | u32 seqno; /* next sequence number */ | |
446 | /* variable length mailbox command log starts here */ | |
447 | }; | |
448 | ||
449 | /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, | |
450 | * return a pointer to the specified entry. | |
451 | */ | |
452 | static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, | |
453 | unsigned int entry_idx) | |
454 | { | |
455 | return &((struct mbox_cmd *)&(log)[1])[entry_idx]; | |
456 | } | |
457 | ||
16e47624 HS |
458 | #include "t4fw_api.h" |
459 | ||
460 | #define FW_VERSION(chip) ( \ | |
b2e1a3f0 HS |
461 | FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ |
462 | FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ | |
463 | FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ | |
464 | FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) | |
16e47624 HS |
465 | #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) |
466 | ||
467 | struct fw_info { | |
468 | u8 chip; | |
469 | char *fs_name; | |
470 | char *fw_mod_name; | |
471 | struct fw_hdr fw_hdr; | |
472 | }; | |
473 | ||
625ba2c2 DM |
474 | struct trace_params { |
475 | u32 data[TRACE_LEN / 4]; | |
476 | u32 mask[TRACE_LEN / 4]; | |
477 | unsigned short snap_len; | |
478 | unsigned short min_len; | |
479 | unsigned char skip_ofst; | |
480 | unsigned char skip_len; | |
481 | unsigned char invert; | |
482 | unsigned char port; | |
483 | }; | |
484 | ||
c3168cab GG |
485 | /* Firmware Port Capabilities types. */ |
486 | ||
487 | typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ | |
488 | typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ | |
489 | ||
490 | enum fw_caps { | |
491 | FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ | |
492 | FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ | |
493 | FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ | |
494 | }; | |
495 | ||
625ba2c2 | 496 | struct link_config { |
c3168cab GG |
497 | fw_port_cap32_t pcaps; /* link capabilities */ |
498 | fw_port_cap32_t def_acaps; /* default advertised capabilities */ | |
499 | fw_port_cap32_t acaps; /* advertised capabilities */ | |
500 | fw_port_cap32_t lpacaps; /* peer advertised capabilities */ | |
501 | ||
502 | fw_port_cap32_t speed_caps; /* speed(s) user has requested */ | |
503 | unsigned int speed; /* actual link speed (Mb/s) */ | |
504 | ||
505 | enum cc_pause requested_fc; /* flow control user has requested */ | |
506 | enum cc_pause fc; /* actual link flow control */ | |
507 | ||
508 | enum cc_fec requested_fec; /* Forward Error Correction: */ | |
509 | enum cc_fec fec; /* requested and actual in use */ | |
510 | ||
625ba2c2 | 511 | unsigned char autoneg; /* autonegotiating? */ |
c3168cab | 512 | |
625ba2c2 | 513 | unsigned char link_ok; /* link up? */ |
ddc7740d | 514 | unsigned char link_down_rc; /* link down reason */ |
8156b0ba GG |
515 | |
516 | bool new_module; /* ->OS Transceiver Module inserted */ | |
517 | bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ | |
625ba2c2 DM |
518 | }; |
519 | ||
e2ac9628 | 520 | #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) |
625ba2c2 DM |
521 | |
522 | enum { | |
523 | MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ | |
f90ce561 | 524 | MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ |
625ba2c2 | 525 | MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ |
625ba2c2 DM |
526 | }; |
527 | ||
812034f1 HS |
528 | enum { |
529 | MAX_TXQ_ENTRIES = 16384, | |
530 | MAX_CTRL_TXQ_ENTRIES = 1024, | |
531 | MAX_RSPQ_ENTRIES = 16384, | |
532 | MAX_RX_BUFFERS = 16384, | |
533 | MIN_TXQ_ENTRIES = 32, | |
534 | MIN_CTRL_TXQ_ENTRIES = 32, | |
535 | MIN_RSPQ_ENTRIES = 128, | |
536 | MIN_FL_ENTRIES = 16 | |
537 | }; | |
538 | ||
68ddc82a RL |
539 | enum { |
540 | MAX_TXQ_DESC_SIZE = 64, | |
541 | MAX_RXQ_DESC_SIZE = 128, | |
542 | MAX_FL_DESC_SIZE = 8, | |
543 | MAX_CTRL_TXQ_DESC_SIZE = 64, | |
544 | }; | |
545 | ||
625ba2c2 | 546 | enum { |
cf38be6d HS |
547 | INGQ_EXTRAS = 2, /* firmware event queue and */ |
548 | /* forwarded interrupts */ | |
0fbc81b3 | 549 | MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, |
625ba2c2 DM |
550 | }; |
551 | ||
d5fbda61 AV |
552 | enum { |
553 | PRIV_FLAG_PORT_TX_VM_BIT, | |
554 | }; | |
555 | ||
556 | #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) | |
557 | ||
558 | #define PRIV_FLAGS_ADAP 0 | |
559 | #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM | |
560 | ||
625ba2c2 | 561 | struct adapter; |
625ba2c2 DM |
562 | struct sge_rspq; |
563 | ||
688848b1 AB |
564 | #include "cxgb4_dcb.h" |
565 | ||
76fed8a9 VP |
566 | #ifdef CONFIG_CHELSIO_T4_FCOE |
567 | #include "cxgb4_fcoe.h" | |
568 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
569 | ||
625ba2c2 DM |
570 | struct port_info { |
571 | struct adapter *adapter; | |
625ba2c2 | 572 | u16 viid; |
3f8cfd0d | 573 | int xact_addr_filt; /* index of exact MAC address filter */ |
625ba2c2 DM |
574 | u16 rss_size; /* size of VI's RSS table slice */ |
575 | s8 mdio_addr; | |
40e9de4b | 576 | enum fw_port_type port_type; |
625ba2c2 DM |
577 | u8 mod_type; |
578 | u8 port_id; | |
579 | u8 tx_chan; | |
580 | u8 lport; /* associated offload logical port */ | |
625ba2c2 DM |
581 | u8 nqsets; /* # of qsets */ |
582 | u8 first_qset; /* index of first qset */ | |
f796564a | 583 | u8 rss_mode; |
625ba2c2 | 584 | struct link_config link_cfg; |
671b0060 | 585 | u16 *rss; |
a4cfd929 | 586 | struct port_stats stats_base; |
688848b1 AB |
587 | #ifdef CONFIG_CHELSIO_T4_DCB |
588 | struct port_dcb_info dcb; /* Data Center Bridging support */ | |
589 | #endif | |
76fed8a9 VP |
590 | #ifdef CONFIG_CHELSIO_T4_FCOE |
591 | struct cxgb_fcoe fcoe; | |
592 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
5e2a5ebc HS |
593 | bool rxtstamp; /* Enable TS */ |
594 | struct hwtstamp_config tstamp_config; | |
a4569504 | 595 | bool ptp_enable; |
b72a32da | 596 | struct sched_table *sched_tbl; |
d5fbda61 | 597 | u32 eth_flags; |
02d805dc SR |
598 | |
599 | /* viid and smt fields either returned by fw | |
600 | * or decoded by parsing viid by driver. | |
601 | */ | |
602 | u8 vin; | |
603 | u8 vivld; | |
604 | u8 smt_idx; | |
74dd5aa1 | 605 | u8 rx_cchan; |
4ec4762d RL |
606 | |
607 | bool tc_block_shared; | |
625ba2c2 DM |
608 | }; |
609 | ||
625ba2c2 DM |
610 | struct dentry; |
611 | struct work_struct; | |
612 | ||
613 | enum { /* adapter flags */ | |
80f61f19 AV |
614 | CXGB4_FULL_INIT_DONE = (1 << 0), |
615 | CXGB4_DEV_ENABLED = (1 << 1), | |
616 | CXGB4_USING_MSI = (1 << 2), | |
617 | CXGB4_USING_MSIX = (1 << 3), | |
618 | CXGB4_FW_OK = (1 << 4), | |
619 | CXGB4_RSS_TNLALLLOOKUP = (1 << 5), | |
620 | CXGB4_USING_SOFT_PARAMS = (1 << 6), | |
621 | CXGB4_MASTER_PF = (1 << 7), | |
622 | CXGB4_FW_OFLD_CONN = (1 << 9), | |
623 | CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), | |
624 | CXGB4_SHUTTING_DOWN = (1 << 11), | |
625 | CXGB4_SGE_DBQ_TIMER = (1 << 12), | |
625ba2c2 DM |
626 | }; |
627 | ||
94cdb8bb HS |
628 | enum { |
629 | ULP_CRYPTO_LOOKASIDE = 1 << 0, | |
a6ec572b | 630 | ULP_CRYPTO_IPSEC_INLINE = 1 << 1, |
94cdb8bb HS |
631 | }; |
632 | ||
625ba2c2 DM |
633 | struct rx_sw_desc; |
634 | ||
635 | struct sge_fl { /* SGE free-buffer queue state */ | |
636 | unsigned int avail; /* # of available Rx buffers */ | |
637 | unsigned int pend_cred; /* new buffers since last FL DB ring */ | |
638 | unsigned int cidx; /* consumer index */ | |
639 | unsigned int pidx; /* producer index */ | |
640 | unsigned long alloc_failed; /* # of times buffer allocation failed */ | |
641 | unsigned long large_alloc_failed; | |
70055dd0 HS |
642 | unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ |
643 | unsigned long low; /* # of times momentarily starving */ | |
625ba2c2 DM |
644 | unsigned long starving; |
645 | /* RO fields */ | |
646 | unsigned int cntxt_id; /* SGE context id for the free list */ | |
647 | unsigned int size; /* capacity of free list */ | |
648 | struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ | |
649 | __be64 *desc; /* address of HW Rx descriptor ring */ | |
650 | dma_addr_t addr; /* bus address of HW ring start */ | |
df64e4d3 HS |
651 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ |
652 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
625ba2c2 DM |
653 | }; |
654 | ||
655 | /* A packet gather list */ | |
656 | struct pkt_gl { | |
5e2a5ebc | 657 | u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ |
e91b0f24 | 658 | struct page_frag frags[MAX_SKB_FRAGS]; |
625ba2c2 DM |
659 | void *va; /* virtual address of first byte */ |
660 | unsigned int nfrags; /* # of fragments */ | |
661 | unsigned int tot_len; /* total length of fragments */ | |
662 | }; | |
663 | ||
664 | typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, | |
665 | const struct pkt_gl *gl); | |
2337ba42 VP |
666 | typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); |
667 | /* LRO related declarations for ULD */ | |
668 | struct t4_lro_mgr { | |
669 | #define MAX_LRO_SESSIONS 64 | |
670 | u8 lro_session_cnt; /* # of sessions to aggregate */ | |
671 | unsigned long lro_pkts; /* # of LRO super packets */ | |
672 | unsigned long lro_merged; /* # of wire packets merged by LRO */ | |
673 | struct sk_buff_head lroq; /* list of aggregated sessions */ | |
674 | }; | |
625ba2c2 DM |
675 | |
676 | struct sge_rspq { /* state for an SGE response queue */ | |
677 | struct napi_struct napi; | |
678 | const __be64 *cur_desc; /* current descriptor in queue */ | |
679 | unsigned int cidx; /* consumer index */ | |
680 | u8 gen; /* current generation bit */ | |
681 | u8 intr_params; /* interrupt holdoff parameters */ | |
682 | u8 next_intr_params; /* holdoff params for next interrupt */ | |
e553ec3f | 683 | u8 adaptive_rx; |
625ba2c2 DM |
684 | u8 pktcnt_idx; /* interrupt packet threshold */ |
685 | u8 uld; /* ULD handling this queue */ | |
686 | u8 idx; /* queue index within its group */ | |
687 | int offset; /* offset into current Rx buffer */ | |
688 | u16 cntxt_id; /* SGE context id for the response q */ | |
689 | u16 abs_id; /* absolute SGE id for the response q */ | |
690 | __be64 *desc; /* address of HW response ring */ | |
691 | dma_addr_t phys_addr; /* physical address of the ring */ | |
df64e4d3 HS |
692 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ |
693 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
625ba2c2 DM |
694 | unsigned int iqe_len; /* entry size */ |
695 | unsigned int size; /* capacity of response queue */ | |
696 | struct adapter *adap; | |
697 | struct net_device *netdev; /* associated net device */ | |
698 | rspq_handler_t handler; | |
2337ba42 VP |
699 | rspq_flush_handler_t flush_handler; |
700 | struct t4_lro_mgr lro_mgr; | |
625ba2c2 DM |
701 | }; |
702 | ||
703 | struct sge_eth_stats { /* Ethernet queue statistics */ | |
704 | unsigned long pkts; /* # of ethernet packets */ | |
705 | unsigned long lro_pkts; /* # of LRO super packets */ | |
706 | unsigned long lro_merged; /* # of wire packets merged by LRO */ | |
707 | unsigned long rx_cso; /* # of Rx checksum offloads */ | |
708 | unsigned long vlan_ex; /* # of Rx VLAN extractions */ | |
709 | unsigned long rx_drops; /* # of packets dropped due to no mem */ | |
992bea8e | 710 | unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ |
625ba2c2 DM |
711 | }; |
712 | ||
713 | struct sge_eth_rxq { /* SW Ethernet Rx queue */ | |
714 | struct sge_rspq rspq; | |
715 | struct sge_fl fl; | |
716 | struct sge_eth_stats stats; | |
76c3a552 | 717 | struct msix_info *msix; |
625ba2c2 DM |
718 | } ____cacheline_aligned_in_smp; |
719 | ||
720 | struct sge_ofld_stats { /* offload queue statistics */ | |
721 | unsigned long pkts; /* # of packets */ | |
722 | unsigned long imm; /* # of immediate-data packets */ | |
723 | unsigned long an; /* # of asynchronous notifications */ | |
724 | unsigned long nomem; /* # of responses deferred due to no mem */ | |
725 | }; | |
726 | ||
727 | struct sge_ofld_rxq { /* SW offload Rx queue */ | |
728 | struct sge_rspq rspq; | |
729 | struct sge_fl fl; | |
730 | struct sge_ofld_stats stats; | |
76c3a552 | 731 | struct msix_info *msix; |
625ba2c2 DM |
732 | } ____cacheline_aligned_in_smp; |
733 | ||
734 | struct tx_desc { | |
735 | __be64 flit[8]; | |
736 | }; | |
737 | ||
0ed96b46 RL |
738 | struct ulptx_sgl; |
739 | ||
740 | struct tx_sw_desc { | |
741 | struct sk_buff *skb; /* SKB to free after getting completion */ | |
742 | dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ | |
743 | }; | |
625ba2c2 DM |
744 | |
745 | struct sge_txq { | |
746 | unsigned int in_use; /* # of in-use Tx descriptors */ | |
ab677ff4 | 747 | unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ |
625ba2c2 DM |
748 | unsigned int size; /* # of descriptors */ |
749 | unsigned int cidx; /* SW consumer index */ | |
750 | unsigned int pidx; /* producer index */ | |
751 | unsigned long stops; /* # of times q has been stopped */ | |
752 | unsigned long restarts; /* # of queue restarts */ | |
753 | unsigned int cntxt_id; /* SGE context id for the Tx q */ | |
754 | struct tx_desc *desc; /* address of HW Tx descriptor ring */ | |
755 | struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ | |
756 | struct sge_qstat *stat; /* queue status entry */ | |
757 | dma_addr_t phys_addr; /* physical address of the ring */ | |
3069ee9b VP |
758 | spinlock_t db_lock; |
759 | int db_disabled; | |
760 | unsigned short db_pidx; | |
05eb2389 | 761 | unsigned short db_pidx_inc; |
df64e4d3 HS |
762 | void __iomem *bar2_addr; /* address of BAR2 Queue registers */ |
763 | unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ | |
625ba2c2 DM |
764 | }; |
765 | ||
766 | struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ | |
767 | struct sge_txq q; | |
768 | struct netdev_queue *txq; /* associated netdev TX queue */ | |
10b00466 AB |
769 | #ifdef CONFIG_CHELSIO_T4_DCB |
770 | u8 dcb_prio; /* DCB Priority bound to queue */ | |
771 | #endif | |
d429005f VK |
772 | u8 dbqt; /* SGE Doorbell Queue Timer in use */ |
773 | unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ | |
625ba2c2 | 774 | unsigned long tso; /* # of TSO requests */ |
1a2a14fb | 775 | unsigned long uso; /* # of USO requests */ |
625ba2c2 DM |
776 | unsigned long tx_cso; /* # of Tx checksum offloads */ |
777 | unsigned long vlan_ins; /* # of Tx VLAN insertions */ | |
778 | unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ | |
779 | } ____cacheline_aligned_in_smp; | |
780 | ||
ab677ff4 | 781 | struct sge_uld_txq { /* state for an SGE offload Tx queue */ |
625ba2c2 DM |
782 | struct sge_txq q; |
783 | struct adapter *adap; | |
784 | struct sk_buff_head sendq; /* list of backpressured packets */ | |
785 | struct tasklet_struct qresume_tsk; /* restarts the queue */ | |
126fca64 | 786 | bool service_ofldq_running; /* service_ofldq() is processing sendq */ |
625ba2c2 DM |
787 | u8 full; /* the Tx ring is full */ |
788 | unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ | |
789 | } ____cacheline_aligned_in_smp; | |
790 | ||
791 | struct sge_ctrl_txq { /* state for an SGE control Tx queue */ | |
792 | struct sge_txq q; | |
793 | struct adapter *adap; | |
794 | struct sk_buff_head sendq; /* list of backpressured packets */ | |
795 | struct tasklet_struct qresume_tsk; /* restarts the queue */ | |
796 | u8 full; /* the Tx ring is full */ | |
797 | } ____cacheline_aligned_in_smp; | |
798 | ||
94cdb8bb HS |
799 | struct sge_uld_rxq_info { |
800 | char name[IFNAMSIZ]; /* name of ULD driver */ | |
801 | struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ | |
94cdb8bb HS |
802 | u16 *rspq_id; /* response queue id's of rxq */ |
803 | u16 nrxq; /* # of ingress uld queues */ | |
804 | u16 nciq; /* # of completion queues */ | |
805 | u8 uld; /* uld type */ | |
806 | }; | |
807 | ||
ab677ff4 HS |
808 | struct sge_uld_txq_info { |
809 | struct sge_uld_txq *uldtxq; /* Txq's for ULD */ | |
810 | atomic_t users; /* num users */ | |
811 | u16 ntxq; /* # of egress uld queues */ | |
812 | }; | |
813 | ||
b1396c2b RL |
814 | enum sge_eosw_state { |
815 | CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ | |
0e395b3c RL |
816 | CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ |
817 | CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ | |
4846d533 | 818 | CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ |
0e395b3c RL |
819 | CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ |
820 | CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ | |
b1396c2b RL |
821 | }; |
822 | ||
b1396c2b RL |
823 | struct sge_eosw_txq { |
824 | spinlock_t lock; /* Per queue lock to synchronize completions */ | |
825 | enum sge_eosw_state state; /* Current ETHOFLD State */ | |
0ed96b46 | 826 | struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ |
b1396c2b RL |
827 | u32 ndesc; /* Number of descriptors */ |
828 | u32 pidx; /* Current Producer Index */ | |
829 | u32 last_pidx; /* Last successfully transmitted Producer Index */ | |
830 | u32 cidx; /* Current Consumer Index */ | |
831 | u32 last_cidx; /* Last successfully reclaimed Consumer Index */ | |
0e395b3c | 832 | u32 flowc_idx; /* Descriptor containing a FLOWC request */ |
b1396c2b RL |
833 | u32 inuse; /* Number of packets held in ring */ |
834 | ||
835 | u32 cred; /* Current available credits */ | |
836 | u32 ncompl; /* # of completions posted */ | |
837 | u32 last_compl; /* # of credits consumed since last completion req */ | |
838 | ||
839 | u32 eotid; /* Index into EOTID table in software */ | |
840 | u32 hwtid; /* Hardware EOTID index */ | |
841 | ||
842 | u32 hwqid; /* Underlying hardware queue index */ | |
843 | struct net_device *netdev; /* Pointer to netdevice */ | |
844 | struct tasklet_struct qresume_tsk; /* Restarts the queue */ | |
0e395b3c | 845 | struct completion completion; /* completion for FLOWC rendezvous */ |
b1396c2b RL |
846 | }; |
847 | ||
2d0cb84d RL |
848 | struct sge_eohw_txq { |
849 | spinlock_t lock; /* Per queue lock */ | |
850 | struct sge_txq q; /* HW Txq */ | |
851 | struct adapter *adap; /* Backpointer to adapter */ | |
852 | unsigned long tso; /* # of TSO requests */ | |
8311f0be | 853 | unsigned long uso; /* # of USO requests */ |
2d0cb84d RL |
854 | unsigned long tx_cso; /* # of Tx checksum offloads */ |
855 | unsigned long vlan_ins; /* # of Tx VLAN insertions */ | |
856 | unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ | |
857 | }; | |
858 | ||
625ba2c2 DM |
859 | struct sge { |
860 | struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; | |
a4569504 | 861 | struct sge_eth_txq ptptxq; |
625ba2c2 DM |
862 | struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; |
863 | ||
864 | struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; | |
625ba2c2 | 865 | struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; |
94cdb8bb | 866 | struct sge_uld_rxq_info **uld_rxq_info; |
ab677ff4 | 867 | struct sge_uld_txq_info **uld_txq_info; |
625ba2c2 DM |
868 | |
869 | struct sge_rspq intrq ____cacheline_aligned_in_smp; | |
870 | spinlock_t intrq_lock; | |
871 | ||
2d0cb84d RL |
872 | struct sge_eohw_txq *eohw_txq; |
873 | struct sge_ofld_rxq *eohw_rxq; | |
874 | ||
625ba2c2 DM |
875 | u16 max_ethqsets; /* # of available Ethernet queue sets */ |
876 | u16 ethqsets; /* # of active Ethernet queue sets */ | |
877 | u16 ethtxq_rover; /* Tx queue to clean up next */ | |
0fbc81b3 | 878 | u16 ofldqsets; /* # of active ofld queue sets */ |
94cdb8bb | 879 | u16 nqs_per_uld; /* # of Rx queues per ULD */ |
2d0cb84d RL |
880 | u16 eoqsets; /* # of ETHOFLD queues */ |
881 | ||
625ba2c2 DM |
882 | u16 timer_val[SGE_NTIMERS]; |
883 | u8 counter_val[SGE_NCOUNTERS]; | |
543a1b85 | 884 | u16 dbqtimer_tick; |
d429005f | 885 | u16 dbqtimer_val[SGE_NDBQTIMERS]; |
52367a76 VP |
886 | u32 fl_pg_order; /* large page allocation size */ |
887 | u32 stat_len; /* length of status page at ring end */ | |
888 | u32 pktshift; /* padding between CPL & packet data */ | |
889 | u32 fl_align; /* response queue message alignment */ | |
890 | u32 fl_starve_thres; /* Free List starvation threshold */ | |
0f4d201f | 891 | |
a3bfb617 | 892 | struct sge_idma_monitor_state idma_monitor; |
e46dab4d | 893 | unsigned int egr_start; |
4b8e27a8 | 894 | unsigned int egr_sz; |
e46dab4d | 895 | unsigned int ingr_start; |
4b8e27a8 HS |
896 | unsigned int ingr_sz; |
897 | void **egr_map; /* qid->queue egress queue map */ | |
898 | struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ | |
899 | unsigned long *starving_fl; | |
900 | unsigned long *txq_maperr; | |
5b377d11 | 901 | unsigned long *blocked_fl; |
625ba2c2 DM |
902 | struct timer_list rx_timer; /* refills starving FLs */ |
903 | struct timer_list tx_timer; /* checks Tx queues */ | |
76c3a552 RL |
904 | |
905 | int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ | |
906 | int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ | |
625ba2c2 DM |
907 | }; |
908 | ||
909 | #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) | |
0fbc81b3 | 910 | #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) |
625ba2c2 DM |
911 | |
912 | struct l2t_data; | |
913 | ||
2422d9a3 SR |
914 | #ifdef CONFIG_PCI_IOV |
915 | ||
7d6727cf SR |
916 | /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial |
917 | * Configuration initialization for T5 only has SR-IOV functionality enabled | |
918 | * on PF0-3 in order to simplify everything. | |
2422d9a3 | 919 | */ |
7d6727cf | 920 | #define NUM_OF_PF_WITH_SRIOV 4 |
2422d9a3 SR |
921 | |
922 | #endif | |
923 | ||
a4cfd929 HS |
924 | struct doorbell_stats { |
925 | u32 db_drop; | |
926 | u32 db_empty; | |
927 | u32 db_full; | |
928 | }; | |
929 | ||
fc08a01a HS |
930 | struct hash_mac_addr { |
931 | struct list_head list; | |
932 | u8 addr[ETH_ALEN]; | |
3f8cfd0d | 933 | unsigned int iface_mac; |
fc08a01a HS |
934 | }; |
935 | ||
76c3a552 | 936 | struct msix_bmap { |
94cdb8bb HS |
937 | unsigned long *msix_bmap; |
938 | unsigned int mapsize; | |
939 | spinlock_t lock; /* lock for acquiring bitmap */ | |
940 | }; | |
941 | ||
76c3a552 | 942 | struct msix_info { |
94cdb8bb HS |
943 | unsigned short vec; |
944 | char desc[IFNAMSIZ + 10]; | |
0fbc81b3 | 945 | unsigned int idx; |
c9765074 | 946 | cpumask_var_t aff_mask; |
94cdb8bb HS |
947 | }; |
948 | ||
661dbeb9 HS |
949 | struct vf_info { |
950 | unsigned char vf_mac_addr[ETH_ALEN]; | |
8ea4fae9 | 951 | unsigned int tx_rate; |
661dbeb9 | 952 | bool pf_set_mac; |
9d5fd927 | 953 | u16 vlan; |
8b965f3f | 954 | int link_state; |
661dbeb9 HS |
955 | }; |
956 | ||
8b4e6b3c AV |
957 | enum { |
958 | HMA_DMA_MAPPED_FLAG = 1 | |
959 | }; | |
960 | ||
961 | struct hma_data { | |
962 | unsigned char flags; | |
963 | struct sg_table *sgt; | |
964 | dma_addr_t *phy_addr; /* physical address of the page */ | |
965 | }; | |
966 | ||
4055ae5e HS |
967 | struct mbox_list { |
968 | struct list_head list; | |
969 | }; | |
970 | ||
e70a57fa | 971 | #if IS_ENABLED(CONFIG_THERMAL) |
b1871915 GG |
972 | struct ch_thermal { |
973 | struct thermal_zone_device *tzdev; | |
974 | int trip_temp; | |
975 | int trip_type; | |
976 | }; | |
977 | #endif | |
978 | ||
28b38705 RR |
979 | struct mps_entries_ref { |
980 | struct list_head list; | |
981 | u8 addr[ETH_ALEN]; | |
982 | u8 mask[ETH_ALEN]; | |
983 | u16 idx; | |
984 | refcount_t refcnt; | |
985 | }; | |
986 | ||
625ba2c2 DM |
987 | struct adapter { |
988 | void __iomem *regs; | |
22adfe0a | 989 | void __iomem *bar2; |
0abfd152 | 990 | u32 t4_bar0; |
625ba2c2 DM |
991 | struct pci_dev *pdev; |
992 | struct device *pdev_dev; | |
0de72738 | 993 | const char *name; |
3069ee9b | 994 | unsigned int mbox; |
b2612722 | 995 | unsigned int pf; |
060e0c75 | 996 | unsigned int flags; |
e7b48a32 | 997 | unsigned int adap_idx; |
2422d9a3 | 998 | enum chip_type chip; |
d5fbda61 | 999 | u32 eth_flags; |
625ba2c2 | 1000 | |
625ba2c2 | 1001 | int msg_enable; |
846eac3f GG |
1002 | __be16 vxlan_port; |
1003 | u8 vxlan_port_cnt; | |
c746fc0e GG |
1004 | __be16 geneve_port; |
1005 | u8 geneve_port_cnt; | |
625ba2c2 DM |
1006 | |
1007 | struct adapter_params params; | |
1008 | struct cxgb4_virt_res vres; | |
1009 | unsigned int swintr; | |
1010 | ||
76c3a552 RL |
1011 | /* MSI-X Info for NIC and OFLD queues */ |
1012 | struct msix_info *msix_info; | |
1013 | struct msix_bmap msix_bmap; | |
625ba2c2 | 1014 | |
a4cfd929 | 1015 | struct doorbell_stats db_stats; |
625ba2c2 DM |
1016 | struct sge sge; |
1017 | ||
1018 | struct net_device *port[MAX_NPORTS]; | |
1019 | u8 chan_map[NCHAN]; /* channel -> port map */ | |
1020 | ||
661dbeb9 HS |
1021 | struct vf_info *vfinfo; |
1022 | u8 num_vfs; | |
1023 | ||
793dad94 | 1024 | u32 filter_mode; |
636f9d37 VP |
1025 | unsigned int l2t_start; |
1026 | unsigned int l2t_end; | |
625ba2c2 | 1027 | struct l2t_data *l2t; |
b5a02f50 AB |
1028 | unsigned int clipt_start; |
1029 | unsigned int clipt_end; | |
1030 | struct clip_tbl *clipt; | |
846eac3f GG |
1031 | unsigned int rawf_start; |
1032 | unsigned int rawf_cnt; | |
3bdb376e | 1033 | struct smt_data *smt; |
0fbc81b3 | 1034 | struct cxgb4_uld_info *uld; |
625ba2c2 | 1035 | void *uld_handle[CXGB4_ULD_MAX]; |
94cdb8bb | 1036 | unsigned int num_uld; |
0fbc81b3 | 1037 | unsigned int num_ofld_uld; |
625ba2c2 | 1038 | struct list_head list_node; |
01bcca68 | 1039 | struct list_head rcu_node; |
fc08a01a | 1040 | struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ |
28b38705 RR |
1041 | struct list_head mps_ref; |
1042 | spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ | |
625ba2c2 | 1043 | |
7714cb9e VP |
1044 | void *iscsi_ppm; |
1045 | ||
625ba2c2 DM |
1046 | struct tid_info tids; |
1047 | void **tid_release_head; | |
1048 | spinlock_t tid_release_lock; | |
29aaee65 | 1049 | struct workqueue_struct *workq; |
625ba2c2 | 1050 | struct work_struct tid_release_task; |
881806bc VP |
1051 | struct work_struct db_full_task; |
1052 | struct work_struct db_drop_task; | |
8b7372c1 | 1053 | struct work_struct fatal_err_notify_task; |
625ba2c2 DM |
1054 | bool tid_release_task_busy; |
1055 | ||
4055ae5e HS |
1056 | /* lock for mailbox cmd list */ |
1057 | spinlock_t mbox_lock; | |
1058 | struct mbox_list mlist; | |
1059 | ||
7f080c3f HS |
1060 | /* support for mailbox command/reply logging */ |
1061 | #define T4_OS_LOG_MBOX_CMDS 256 | |
1062 | struct mbox_cmd_log *mbox_log; | |
1063 | ||
0fbc81b3 HS |
1064 | struct mutex uld_mutex; |
1065 | ||
625ba2c2 | 1066 | struct dentry *debugfs_root; |
621a5f7a VK |
1067 | bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ |
1068 | bool trace_rss; /* 1 implies that different RSS flit per filter is | |
8e3d04fd HS |
1069 | * used per filter else if 0 default RSS flit is |
1070 | * used for all 4 filters. | |
1071 | */ | |
625ba2c2 | 1072 | |
a4569504 AG |
1073 | struct ptp_clock *ptp_clock; |
1074 | struct ptp_clock_info ptp_clock_info; | |
1075 | struct sk_buff *ptp_tx_skb; | |
1076 | /* ptp lock */ | |
1077 | spinlock_t ptp_lock; | |
625ba2c2 | 1078 | spinlock_t stats_lock; |
fc5ab020 | 1079 | spinlock_t win0_lock ____cacheline_aligned_in_smp; |
d8931847 RL |
1080 | |
1081 | /* TC u32 offload */ | |
1082 | struct cxgb4_tc_u32_table *tc_u32; | |
ee0863ba | 1083 | struct chcr_stats_debug chcr_stats; |
62488e4b KS |
1084 | |
1085 | /* TC flower offload */ | |
a081e115 | 1086 | bool tc_flower_initialized; |
79e6d46a KS |
1087 | struct rhashtable flower_tbl; |
1088 | struct rhashtable_params flower_ht_params; | |
e0f911c8 | 1089 | struct timer_list flower_stats_timer; |
79e6d46a | 1090 | struct work_struct flower_stats_work; |
ad75b7d3 RL |
1091 | |
1092 | /* Ethtool Dump */ | |
1093 | struct ethtool_dump eth_dump; | |
8b4e6b3c AV |
1094 | |
1095 | /* HMA */ | |
1096 | struct hma_data hma; | |
e4709475 RR |
1097 | |
1098 | struct srq_data *srq; | |
1dde532d RL |
1099 | |
1100 | /* Dump buffer for collecting logs in kdump kernel */ | |
1101 | struct vmcoredd_data vmcoredd; | |
e70a57fa | 1102 | #if IS_ENABLED(CONFIG_THERMAL) |
b1871915 GG |
1103 | struct ch_thermal ch_thermal; |
1104 | #endif | |
b1396c2b RL |
1105 | |
1106 | /* TC MQPRIO offload */ | |
1107 | struct cxgb4_tc_mqprio *tc_mqprio; | |
4ec4762d RL |
1108 | |
1109 | /* TC MATCHALL classifier offload */ | |
1110 | struct cxgb4_tc_matchall *tc_matchall; | |
625ba2c2 DM |
1111 | }; |
1112 | ||
b72a32da RL |
1113 | /* Support for "sched-class" command to allow a TX Scheduling Class to be |
1114 | * programmed with various parameters. | |
1115 | */ | |
1116 | struct ch_sched_params { | |
1117 | s8 type; /* packet or flow */ | |
1118 | union { | |
1119 | struct { | |
1120 | s8 level; /* scheduler hierarchy level */ | |
1121 | s8 mode; /* per-class or per-flow */ | |
1122 | s8 rateunit; /* bit or packet rate */ | |
1123 | s8 ratemode; /* %port relative or kbps absolute */ | |
1124 | s8 channel; /* scheduler channel [0..N] */ | |
1125 | s8 class; /* scheduler class [0..N] */ | |
1126 | s32 minrate; /* minimum rate */ | |
1127 | s32 maxrate; /* maximum rate */ | |
1128 | s16 weight; /* percent weight */ | |
1129 | s16 pktsize; /* average packet size */ | |
1130 | } params; | |
1131 | } u; | |
6cede1f1 RL |
1132 | }; |
1133 | ||
10a2604e RL |
1134 | enum { |
1135 | SCHED_CLASS_TYPE_PACKET = 0, /* class type */ | |
1136 | }; | |
1137 | ||
1138 | enum { | |
1139 | SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ | |
4ec4762d | 1140 | SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ |
10a2604e RL |
1141 | }; |
1142 | ||
1143 | enum { | |
1144 | SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ | |
0e395b3c | 1145 | SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ |
10a2604e RL |
1146 | }; |
1147 | ||
1148 | enum { | |
1149 | SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ | |
1150 | }; | |
1151 | ||
1152 | enum { | |
1153 | SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ | |
1154 | }; | |
1155 | ||
6cede1f1 RL |
1156 | /* Support for "sched_queue" command to allow one or more NIC TX Queues |
1157 | * to be bound to a TX Scheduling Class. | |
1158 | */ | |
1159 | struct ch_sched_queue { | |
1160 | s8 queue; /* queue index */ | |
1161 | s8 class; /* class index */ | |
b72a32da RL |
1162 | }; |
1163 | ||
0e395b3c RL |
1164 | /* Support for "sched_flowc" command to allow one or more FLOWC |
1165 | * to be bound to a TX Scheduling Class. | |
1166 | */ | |
1167 | struct ch_sched_flowc { | |
1168 | s32 tid; /* TID to bind */ | |
1169 | s8 class; /* class index */ | |
1170 | }; | |
1171 | ||
f2b7e78d VP |
1172 | /* Defined bit width of user definable filter tuples |
1173 | */ | |
1174 | #define ETHTYPE_BITWIDTH 16 | |
1175 | #define FRAG_BITWIDTH 1 | |
1176 | #define MACIDX_BITWIDTH 9 | |
1177 | #define FCOE_BITWIDTH 1 | |
1178 | #define IPORT_BITWIDTH 3 | |
1179 | #define MATCHTYPE_BITWIDTH 3 | |
1180 | #define PROTO_BITWIDTH 8 | |
1181 | #define TOS_BITWIDTH 8 | |
1182 | #define PF_BITWIDTH 8 | |
1183 | #define VF_BITWIDTH 8 | |
1184 | #define IVLAN_BITWIDTH 16 | |
1185 | #define OVLAN_BITWIDTH 16 | |
98f3697f | 1186 | #define ENCAP_VNI_BITWIDTH 24 |
f2b7e78d VP |
1187 | |
1188 | /* Filter matching rules. These consist of a set of ingress packet field | |
1189 | * (value, mask) tuples. The associated ingress packet field matches the | |
1190 | * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field | |
1191 | * rule can be constructed by specifying a tuple of (0, 0).) A filter rule | |
1192 | * matches an ingress packet when all of the individual individual field | |
1193 | * matching rules are true. | |
1194 | * | |
1195 | * Partial field masks are always valid, however, while it may be easy to | |
1196 | * understand their meanings for some fields (e.g. IP address to match a | |
1197 | * subnet), for others making sensible partial masks is less intuitive (e.g. | |
1198 | * MPS match type) ... | |
1199 | * | |
1200 | * Most of the following data structures are modeled on T4 capabilities. | |
1201 | * Drivers for earlier chips use the subsets which make sense for those chips. | |
1202 | * We really need to come up with a hardware-independent mechanism to | |
1203 | * represent hardware filter capabilities ... | |
1204 | */ | |
1205 | struct ch_filter_tuple { | |
1206 | /* Compressed header matching field rules. The TP_VLAN_PRI_MAP | |
1207 | * register selects which of these fields will participate in the | |
1208 | * filter match rules -- up to a maximum of 36 bits. Because | |
1209 | * TP_VLAN_PRI_MAP is a global register, all filters must use the same | |
1210 | * set of fields. | |
1211 | */ | |
1212 | uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ | |
1213 | uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ | |
1214 | uint32_t ivlan_vld:1; /* inner VLAN valid */ | |
1215 | uint32_t ovlan_vld:1; /* outer VLAN valid */ | |
1216 | uint32_t pfvf_vld:1; /* PF/VF valid */ | |
98f3697f | 1217 | uint32_t encap_vld:1; /* Encapsulation valid */ |
f2b7e78d VP |
1218 | uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ |
1219 | uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ | |
1220 | uint32_t iport:IPORT_BITWIDTH; /* ingress port */ | |
1221 | uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ | |
1222 | uint32_t proto:PROTO_BITWIDTH; /* protocol type */ | |
1223 | uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ | |
1224 | uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ | |
1225 | uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ | |
1226 | uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ | |
1227 | uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ | |
98f3697f | 1228 | uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ |
f2b7e78d VP |
1229 | |
1230 | /* Uncompressed header matching field rules. These are always | |
1231 | * available for field rules. | |
1232 | */ | |
1233 | uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ | |
1234 | uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ | |
1235 | uint16_t lport; /* local port */ | |
1236 | uint16_t fport; /* foreign port */ | |
1237 | }; | |
1238 | ||
1239 | /* A filter ioctl command. | |
1240 | */ | |
1241 | struct ch_filter_specification { | |
1242 | /* Administrative fields for filter. | |
1243 | */ | |
1244 | uint32_t hitcnts:1; /* count filter hits in TCB */ | |
1245 | uint32_t prio:1; /* filter has priority over active/server */ | |
1246 | ||
1247 | /* Fundamental filter typing. This is the one element of filter | |
1248 | * matching that doesn't exist as a (value, mask) tuple. | |
1249 | */ | |
1250 | uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ | |
12b276fb | 1251 | u32 hash:1; /* 0 => wild-card, 1 => exact-match */ |
f2b7e78d VP |
1252 | |
1253 | /* Packet dispatch information. Ingress packets which match the | |
1254 | * filter rules will be dropped, passed to the host or switched back | |
1255 | * out as egress packets. | |
1256 | */ | |
1257 | uint32_t action:2; /* drop, pass, switch */ | |
1258 | ||
1259 | uint32_t rpttid:1; /* report TID in RSS hash field */ | |
1260 | ||
1261 | uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ | |
1262 | uint32_t iq:10; /* ingress queue */ | |
1263 | ||
1264 | uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ | |
1265 | uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ | |
1266 | /* 1 => TCB contains IQ ID */ | |
1267 | ||
1268 | /* Switch proxy/rewrite fields. An ingress packet which matches a | |
1269 | * filter with "switch" set will be looped back out as an egress | |
1270 | * packet -- potentially with some Ethernet header rewriting. | |
1271 | */ | |
1272 | uint32_t eport:2; /* egress port to switch packet out */ | |
1273 | uint32_t newdmac:1; /* rewrite destination MAC address */ | |
1274 | uint32_t newsmac:1; /* rewrite source MAC address */ | |
1275 | uint32_t newvlan:2; /* rewrite VLAN Tag */ | |
0ff90994 | 1276 | uint32_t nat_mode:3; /* specify NAT operation mode */ |
f2b7e78d VP |
1277 | uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ |
1278 | uint8_t smac[ETH_ALEN]; /* new source MAC address */ | |
1279 | uint16_t vlan; /* VLAN Tag to insert */ | |
1280 | ||
0ff90994 KS |
1281 | u8 nat_lip[16]; /* local IP to use after NAT'ing */ |
1282 | u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ | |
1283 | u16 nat_lport; /* local port to use after NAT'ing */ | |
1284 | u16 nat_fport; /* foreign port to use after NAT'ing */ | |
1285 | ||
41ec03e5 RL |
1286 | u32 tc_prio; /* TC's filter priority index */ |
1287 | u64 tc_cookie; /* Unique cookie identifying TC rules */ | |
1288 | ||
0ff90994 | 1289 | /* reservation for future additions */ |
41ec03e5 | 1290 | u8 rsvd[12]; |
0ff90994 | 1291 | |
f2b7e78d VP |
1292 | /* Filter rule value/mask pairs. |
1293 | */ | |
1294 | struct ch_filter_tuple val; | |
1295 | struct ch_filter_tuple mask; | |
1296 | }; | |
1297 | ||
1298 | enum { | |
1299 | FILTER_PASS = 0, /* default */ | |
1300 | FILTER_DROP, | |
1301 | FILTER_SWITCH | |
1302 | }; | |
1303 | ||
1304 | enum { | |
1305 | VLAN_NOCHANGE = 0, /* default */ | |
1306 | VLAN_REMOVE, | |
1307 | VLAN_INSERT, | |
1308 | VLAN_REWRITE | |
1309 | }; | |
1310 | ||
557ccbf9 | 1311 | enum { |
12b276fb KS |
1312 | NAT_MODE_NONE = 0, /* No NAT performed */ |
1313 | NAT_MODE_DIP, /* NAT on Dst IP */ | |
1314 | NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ | |
1315 | NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ | |
1316 | NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ | |
1317 | NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ | |
1318 | NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ | |
1319 | NAT_MODE_ALL /* NAT on entire 4-tuple */ | |
557ccbf9 KS |
1320 | }; |
1321 | ||
d57fd6ca RL |
1322 | /* Host shadow copy of ingress filter entry. This is in host native format |
1323 | * and doesn't match the ordering or bit order, etc. of the hardware of the | |
1324 | * firmware command. The use of bit-field structure elements is purely to | |
1325 | * remind ourselves of the field size limitations and save memory in the case | |
1326 | * where the filter table is large. | |
1327 | */ | |
1328 | struct filter_entry { | |
1329 | /* Administrative fields for filter. */ | |
1330 | u32 valid:1; /* filter allocated and valid */ | |
1331 | u32 locked:1; /* filter is administratively locked */ | |
1332 | ||
1333 | u32 pending:1; /* filter action is pending firmware reply */ | |
578b46b9 | 1334 | struct filter_ctx *ctx; /* Caller's completion hook */ |
d57fd6ca | 1335 | struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ |
3bdb376e | 1336 | struct smt_entry *smt; /* Source Mac Table entry for smac */ |
578b46b9 RL |
1337 | struct net_device *dev; /* Associated net device */ |
1338 | u32 tid; /* This will store the actual tid */ | |
d57fd6ca RL |
1339 | |
1340 | /* The filter itself. Most of this is a straight copy of information | |
1341 | * provided by the extended ioctl(). Some fields are translated to | |
1342 | * internal forms -- for instance the Ingress Queue ID passed in from | |
1343 | * the ioctl() is translated into the Absolute Ingress Queue ID. | |
1344 | */ | |
1345 | struct ch_filter_specification fs; | |
1346 | }; | |
1347 | ||
a4cfd929 HS |
1348 | static inline int is_offload(const struct adapter *adap) |
1349 | { | |
1350 | return adap->params.offload; | |
1351 | } | |
1352 | ||
5c31254e KS |
1353 | static inline int is_hashfilter(const struct adapter *adap) |
1354 | { | |
1355 | return adap->params.hash_filter; | |
1356 | } | |
1357 | ||
94cdb8bb HS |
1358 | static inline int is_pci_uld(const struct adapter *adap) |
1359 | { | |
1360 | return adap->params.crypto; | |
1361 | } | |
1362 | ||
0fbc81b3 HS |
1363 | static inline int is_uld(const struct adapter *adap) |
1364 | { | |
1365 | return (adap->params.offload || adap->params.crypto); | |
1366 | } | |
1367 | ||
ab0367ea RL |
1368 | static inline int is_ethofld(const struct adapter *adap) |
1369 | { | |
1370 | return adap->params.ethofld; | |
1371 | } | |
1372 | ||
625ba2c2 DM |
1373 | static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) |
1374 | { | |
1375 | return readl(adap->regs + reg_addr); | |
1376 | } | |
1377 | ||
1378 | static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) | |
1379 | { | |
1380 | writel(val, adap->regs + reg_addr); | |
1381 | } | |
1382 | ||
1383 | #ifndef readq | |
1384 | static inline u64 readq(const volatile void __iomem *addr) | |
1385 | { | |
1386 | return readl(addr) + ((u64)readl(addr + 4) << 32); | |
1387 | } | |
1388 | ||
1389 | static inline void writeq(u64 val, volatile void __iomem *addr) | |
1390 | { | |
1391 | writel(val, addr); | |
1392 | writel(val >> 32, addr + 4); | |
1393 | } | |
1394 | #endif | |
1395 | ||
1396 | static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) | |
1397 | { | |
1398 | return readq(adap->regs + reg_addr); | |
1399 | } | |
1400 | ||
1401 | static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) | |
1402 | { | |
1403 | writeq(val, adap->regs + reg_addr); | |
1404 | } | |
1405 | ||
098ef6c2 HS |
1406 | /** |
1407 | * t4_set_hw_addr - store a port's MAC address in SW | |
1408 | * @adapter: the adapter | |
1409 | * @port_idx: the port index | |
1410 | * @hw_addr: the Ethernet address | |
1411 | * | |
1412 | * Store the Ethernet address of the given port in SW. Called by the common | |
1413 | * code when it retrieves a port's Ethernet address from EEPROM. | |
1414 | */ | |
1415 | static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, | |
1416 | u8 hw_addr[]) | |
1417 | { | |
1418 | ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); | |
1419 | ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); | |
1420 | } | |
1421 | ||
625ba2c2 DM |
1422 | /** |
1423 | * netdev2pinfo - return the port_info structure associated with a net_device | |
1424 | * @dev: the netdev | |
1425 | * | |
1426 | * Return the struct port_info associated with a net_device | |
1427 | */ | |
1428 | static inline struct port_info *netdev2pinfo(const struct net_device *dev) | |
1429 | { | |
1430 | return netdev_priv(dev); | |
1431 | } | |
1432 | ||
1433 | /** | |
1434 | * adap2pinfo - return the port_info of a port | |
1435 | * @adap: the adapter | |
1436 | * @idx: the port index | |
1437 | * | |
1438 | * Return the port_info structure for the port of the given index. | |
1439 | */ | |
1440 | static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) | |
1441 | { | |
1442 | return netdev_priv(adap->port[idx]); | |
1443 | } | |
1444 | ||
1445 | /** | |
1446 | * netdev2adap - return the adapter structure associated with a net_device | |
1447 | * @dev: the netdev | |
1448 | * | |
1449 | * Return the struct adapter associated with a net_device | |
1450 | */ | |
1451 | static inline struct adapter *netdev2adap(const struct net_device *dev) | |
1452 | { | |
1453 | return netdev2pinfo(dev)->adapter; | |
1454 | } | |
1455 | ||
812034f1 HS |
1456 | /* Return a version number to identify the type of adapter. The scheme is: |
1457 | * - bits 0..9: chip version | |
1458 | * - bits 10..15: chip revision | |
1459 | * - bits 16..23: register dump version | |
1460 | */ | |
1461 | static inline unsigned int mk_adap_vers(struct adapter *ap) | |
1462 | { | |
1463 | return CHELSIO_CHIP_VERSION(ap->params.chip) | | |
1464 | (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); | |
1465 | } | |
1466 | ||
1467 | /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ | |
1468 | static inline unsigned int qtimer_val(const struct adapter *adap, | |
1469 | const struct sge_rspq *q) | |
1470 | { | |
1471 | unsigned int idx = q->intr_params >> 1; | |
1472 | ||
1473 | return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; | |
1474 | } | |
1475 | ||
1476 | /* driver version & name used for ethtool_drvinfo */ | |
1477 | extern char cxgb4_driver_name[]; | |
1478 | extern const char cxgb4_driver_version[]; | |
1479 | ||
8156b0ba | 1480 | void t4_os_portmod_changed(struct adapter *adap, int port_id); |
625ba2c2 DM |
1481 | void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); |
1482 | ||
625ba2c2 | 1483 | void t4_free_sge_resources(struct adapter *adap); |
5fa76694 | 1484 | void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); |
625ba2c2 | 1485 | irq_handler_t t4_intr_handler(struct adapter *adap); |
d5fbda61 | 1486 | netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); |
625ba2c2 DM |
1487 | int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, |
1488 | const struct pkt_gl *gl); | |
1489 | int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); | |
1490 | int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); | |
1491 | int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, | |
1492 | struct net_device *dev, int intr_idx, | |
2337ba42 VP |
1493 | struct sge_fl *fl, rspq_handler_t hnd, |
1494 | rspq_flush_handler_t flush_handler, int cong); | |
625ba2c2 DM |
1495 | int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, |
1496 | struct net_device *dev, struct netdev_queue *netdevq, | |
d429005f | 1497 | unsigned int iqid, u8 dbqt); |
625ba2c2 DM |
1498 | int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, |
1499 | struct net_device *dev, unsigned int iqid, | |
1500 | unsigned int cmplqid); | |
0fbc81b3 HS |
1501 | int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, |
1502 | unsigned int cmplqid); | |
ab677ff4 HS |
1503 | int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, |
1504 | struct net_device *dev, unsigned int iqid, | |
1505 | unsigned int uld_type); | |
2d0cb84d RL |
1506 | int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, |
1507 | struct net_device *dev, u32 iqid); | |
1508 | void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); | |
625ba2c2 | 1509 | irqreturn_t t4_sge_intr_msix(int irq, void *cookie); |
52367a76 | 1510 | int t4_sge_init(struct adapter *adap); |
625ba2c2 DM |
1511 | void t4_sge_start(struct adapter *adap); |
1512 | void t4_sge_stop(struct adapter *adap); | |
d429005f VK |
1513 | int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, |
1514 | int maxreclaim); | |
812034f1 HS |
1515 | void cxgb4_set_ethtool_ops(struct net_device *netdev); |
1516 | int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); | |
d0a1299c | 1517 | enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); |
3069ee9b | 1518 | extern int dbfifo_int_thresh; |
625ba2c2 DM |
1519 | |
1520 | #define for_each_port(adapter, iter) \ | |
1521 | for (iter = 0; iter < (adapter)->params.nports; ++iter) | |
1522 | ||
9a4da2cd VP |
1523 | static inline int is_bypass(struct adapter *adap) |
1524 | { | |
1525 | return adap->params.bypass; | |
1526 | } | |
1527 | ||
1528 | static inline int is_bypass_device(int device) | |
1529 | { | |
1530 | /* this should be set based upon device capabilities */ | |
1531 | switch (device) { | |
1532 | case 0x440b: | |
1533 | case 0x440c: | |
1534 | return 1; | |
1535 | default: | |
1536 | return 0; | |
1537 | } | |
1538 | } | |
1539 | ||
01b69614 HS |
1540 | static inline int is_10gbt_device(int device) |
1541 | { | |
1542 | /* this should be set based upon device capabilities */ | |
1543 | switch (device) { | |
1544 | case 0x4409: | |
1545 | case 0x4486: | |
1546 | return 1; | |
1547 | ||
1548 | default: | |
1549 | return 0; | |
1550 | } | |
1551 | } | |
1552 | ||
625ba2c2 DM |
1553 | static inline unsigned int core_ticks_per_usec(const struct adapter *adap) |
1554 | { | |
1555 | return adap->params.vpd.cclk / 1000; | |
1556 | } | |
1557 | ||
1558 | static inline unsigned int us_to_core_ticks(const struct adapter *adap, | |
1559 | unsigned int us) | |
1560 | { | |
1561 | return (us * adap->params.vpd.cclk) / 1000; | |
1562 | } | |
1563 | ||
52367a76 VP |
1564 | static inline unsigned int core_ticks_to_us(const struct adapter *adapter, |
1565 | unsigned int ticks) | |
1566 | { | |
1567 | /* add Core Clock / 2 to round ticks to nearest uS */ | |
1568 | return ((ticks * 1000 + adapter->params.vpd.cclk/2) / | |
1569 | adapter->params.vpd.cclk); | |
1570 | } | |
1571 | ||
08c4901b RL |
1572 | static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, |
1573 | unsigned int ticks) | |
1574 | { | |
1575 | return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); | |
1576 | } | |
1577 | ||
625ba2c2 DM |
1578 | void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, |
1579 | u32 val); | |
1580 | ||
01b69614 HS |
1581 | int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, |
1582 | int size, void *rpl, bool sleep_ok, int timeout); | |
625ba2c2 DM |
1583 | int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, |
1584 | void *rpl, bool sleep_ok); | |
1585 | ||
01b69614 HS |
1586 | static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, |
1587 | const void *cmd, int size, void *rpl, | |
1588 | int timeout) | |
1589 | { | |
1590 | return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, | |
1591 | timeout); | |
1592 | } | |
1593 | ||
625ba2c2 DM |
1594 | static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, |
1595 | int size, void *rpl) | |
1596 | { | |
1597 | return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); | |
1598 | } | |
1599 | ||
1600 | static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, | |
1601 | int size, void *rpl) | |
1602 | { | |
1603 | return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); | |
1604 | } | |
1605 | ||
fc08a01a HS |
1606 | /** |
1607 | * hash_mac_addr - return the hash value of a MAC address | |
1608 | * @addr: the 48-bit Ethernet MAC address | |
1609 | * | |
1610 | * Hashes a MAC address according to the hash function used by HW inexact | |
1611 | * (hash) address matching. | |
1612 | */ | |
1613 | static inline int hash_mac_addr(const u8 *addr) | |
1614 | { | |
1615 | u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; | |
1616 | u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; | |
1617 | ||
1618 | a ^= b; | |
1619 | a ^= (a >> 12); | |
1620 | a ^= (a >> 6); | |
1621 | return a & 0x3f; | |
1622 | } | |
1623 | ||
94cdb8bb HS |
1624 | int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, |
1625 | unsigned int cnt); | |
1626 | static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, | |
1627 | unsigned int us, unsigned int cnt, | |
1628 | unsigned int size, unsigned int iqe_size) | |
1629 | { | |
1630 | q->adap = adap; | |
1631 | cxgb4_set_rspq_intr_params(q, us, cnt); | |
1632 | q->iqe_len = iqe_size; | |
1633 | q->size = size; | |
1634 | } | |
1635 | ||
f56ec676 AV |
1636 | /** |
1637 | * t4_is_inserted_mod_type - is a plugged in Firmware Module Type | |
1638 | * @fw_mod_type: the Firmware Mofule Type | |
1639 | * | |
1640 | * Return whether the Firmware Module Type represents a real Transceiver | |
1641 | * Module/Cable Module Type which has been inserted. | |
1642 | */ | |
1643 | static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) | |
1644 | { | |
1645 | return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && | |
1646 | fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && | |
1647 | fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && | |
1648 | fw_mod_type != FW_PORT_MOD_TYPE_ERROR); | |
1649 | } | |
1650 | ||
13ee15d3 VP |
1651 | void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, |
1652 | unsigned int data_reg, const u32 *vals, | |
1653 | unsigned int nregs, unsigned int start_idx); | |
f2b7e78d VP |
1654 | void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, |
1655 | unsigned int data_reg, u32 *vals, unsigned int nregs, | |
1656 | unsigned int start_idx); | |
0abfd152 | 1657 | void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); |
f2b7e78d VP |
1658 | |
1659 | struct fw_filter_wr; | |
1660 | ||
625ba2c2 DM |
1661 | void t4_intr_enable(struct adapter *adapter); |
1662 | void t4_intr_disable(struct adapter *adapter); | |
625ba2c2 DM |
1663 | int t4_slow_intr_handler(struct adapter *adapter); |
1664 | ||
8203b509 | 1665 | int t4_wait_dev_ready(void __iomem *regs); |
8156b0ba | 1666 | |
9f764898 VK |
1667 | fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, |
1668 | struct link_config *lc); | |
8156b0ba GG |
1669 | int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, |
1670 | unsigned int port, struct link_config *lc, | |
9f764898 | 1671 | u8 sleep_ok, int timeout); |
8156b0ba GG |
1672 | |
1673 | static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, | |
1674 | unsigned int port, struct link_config *lc) | |
1675 | { | |
1676 | return t4_link_l1cfg_core(adapter, mbox, port, lc, | |
1677 | true, FW_CMD_MAX_TIMEOUT); | |
1678 | } | |
1679 | ||
1680 | static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, | |
1681 | unsigned int port, struct link_config *lc) | |
1682 | { | |
1683 | return t4_link_l1cfg_core(adapter, mbox, port, lc, | |
1684 | false, FW_CMD_MAX_TIMEOUT); | |
1685 | } | |
1686 | ||
625ba2c2 | 1687 | int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); |
fc5ab020 | 1688 | |
b562fc37 HS |
1689 | u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); |
1690 | u32 t4_get_util_window(struct adapter *adap); | |
1691 | void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); | |
1692 | ||
1a4330cd RL |
1693 | int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, |
1694 | u32 *mem_base, u32 *mem_aperture); | |
1695 | void t4_memory_update_win(struct adapter *adap, int win, u32 addr); | |
1696 | void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, | |
1697 | int dir); | |
fc5ab020 HS |
1698 | #define T4_MEMORY_WRITE 0 |
1699 | #define T4_MEMORY_READ 1 | |
1700 | int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, | |
f01aa633 | 1701 | void *buf, int dir); |
fc5ab020 HS |
1702 | static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, |
1703 | u32 len, __be32 *buf) | |
1704 | { | |
1705 | return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); | |
1706 | } | |
1707 | ||
812034f1 HS |
1708 | unsigned int t4_get_regs_len(struct adapter *adapter); |
1709 | void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); | |
1710 | ||
940c9c45 | 1711 | int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); |
625ba2c2 | 1712 | int t4_seeprom_wp(struct adapter *adapter, bool enable); |
098ef6c2 HS |
1713 | int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); |
1714 | int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); | |
0eaec62a | 1715 | int t4_get_pfres(struct adapter *adapter); |
49216c1c HS |
1716 | int t4_read_flash(struct adapter *adapter, unsigned int addr, |
1717 | unsigned int nwords, u32 *data, int byte_oriented); | |
625ba2c2 | 1718 | int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); |
01b69614 HS |
1719 | int t4_load_phy_fw(struct adapter *adap, |
1720 | int win, spinlock_t *lock, | |
1721 | int (*phy_fw_version)(const u8 *, size_t), | |
1722 | const u8 *phy_fw_data, size_t phy_fw_size); | |
1723 | int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); | |
49216c1c | 1724 | int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); |
22c0b963 HS |
1725 | int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, |
1726 | const u8 *fw_data, unsigned int size, int force); | |
acac5962 | 1727 | int t4_fl_pkt_align(struct adapter *adap); |
636f9d37 | 1728 | unsigned int t4_flash_cfg_addr(struct adapter *adapter); |
a69265e9 | 1729 | int t4_check_fw_version(struct adapter *adap); |
4da18741 | 1730 | int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); |
16e47624 | 1731 | int t4_get_fw_version(struct adapter *adapter, u32 *vers); |
0de72738 | 1732 | int t4_get_bs_version(struct adapter *adapter, u32 *vers); |
16e47624 | 1733 | int t4_get_tp_version(struct adapter *adapter, u32 *vers); |
ba3f8cd5 | 1734 | int t4_get_exprom_version(struct adapter *adapter, u32 *vers); |
760446f9 GG |
1735 | int t4_get_scfg_version(struct adapter *adapter, u32 *vers); |
1736 | int t4_get_vpd_version(struct adapter *adapter, u32 *vers); | |
1737 | int t4_get_version_info(struct adapter *adapter); | |
1738 | void t4_dump_version_info(struct adapter *adapter); | |
16e47624 HS |
1739 | int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, |
1740 | const u8 *fw_data, unsigned int fw_size, | |
1741 | struct fw_hdr *card_fw, enum dev_state state, int *reset); | |
625ba2c2 | 1742 | int t4_prep_adapter(struct adapter *adapter); |
3be0679b | 1743 | int t4_shutdown_adapter(struct adapter *adapter); |
e85c9a7a HS |
1744 | |
1745 | enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; | |
b2612722 | 1746 | int t4_bar2_sge_qregs(struct adapter *adapter, |
e85c9a7a HS |
1747 | unsigned int qid, |
1748 | enum t4_bar2_qtype qtype, | |
66cf188e | 1749 | int user, |
e85c9a7a HS |
1750 | u64 *pbar2_qoffset, |
1751 | unsigned int *pbar2_qid); | |
1752 | ||
dc9daab2 HS |
1753 | unsigned int qtimer_val(const struct adapter *adap, |
1754 | const struct sge_rspq *q); | |
ae469b68 HS |
1755 | |
1756 | int t4_init_devlog_params(struct adapter *adapter); | |
e85c9a7a | 1757 | int t4_init_sge_params(struct adapter *adapter); |
5ccf9d04 | 1758 | int t4_init_tp_params(struct adapter *adap, bool sleep_ok); |
dcf7b6f5 | 1759 | int t4_filter_field_shift(const struct adapter *adap, int filter_sel); |
c035e183 | 1760 | int t4_init_rss_mode(struct adapter *adap, int mbox); |
c3e324e3 HS |
1761 | int t4_init_portinfo(struct port_info *pi, int mbox, |
1762 | int port, int pf, int vf, u8 mac[]); | |
625ba2c2 DM |
1763 | int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); |
1764 | void t4_fatal_err(struct adapter *adapter); | |
f988008a | 1765 | unsigned int t4_chip_rss_size(struct adapter *adapter); |
625ba2c2 DM |
1766 | int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, |
1767 | int start, int n, const u16 *rspq, unsigned int nrspq); | |
1768 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, | |
1769 | unsigned int flags); | |
c035e183 HS |
1770 | int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, |
1771 | unsigned int flags, unsigned int defq); | |
688ea5fe | 1772 | int t4_read_rss(struct adapter *adapter, u16 *entries); |
5ccf9d04 RL |
1773 | void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); |
1774 | void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, | |
1775 | bool sleep_ok); | |
688ea5fe | 1776 | void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, |
5ccf9d04 | 1777 | u32 *valp, bool sleep_ok); |
688ea5fe | 1778 | void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, |
5ccf9d04 RL |
1779 | u32 *vfl, u32 *vfh, bool sleep_ok); |
1780 | u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); | |
1781 | u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); | |
688ea5fe | 1782 | |
193c4c28 AV |
1783 | unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); |
1784 | unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); | |
b3bbe36a HS |
1785 | void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); |
1786 | void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); | |
e5f0e43b HS |
1787 | int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, |
1788 | size_t n); | |
c778af7d HS |
1789 | int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, |
1790 | size_t n); | |
f1ff24aa HS |
1791 | int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, |
1792 | unsigned int *valp); | |
1793 | int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, | |
1794 | const unsigned int *valp); | |
1795 | int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); | |
19689609 HS |
1796 | void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, |
1797 | unsigned int *pif_req_wrptr, | |
1798 | unsigned int *pif_rsp_wrptr); | |
26fae93f | 1799 | void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); |
74b3092c | 1800 | void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); |
72aca4bf | 1801 | const char *t4_get_port_type_description(enum fw_port_type port_type); |
625ba2c2 | 1802 | void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); |
a4cfd929 HS |
1803 | void t4_get_port_stats_offset(struct adapter *adap, int idx, |
1804 | struct port_stats *stats, | |
1805 | struct port_stats *offset); | |
65046e84 | 1806 | void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); |
625ba2c2 | 1807 | void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); |
bad43792 | 1808 | void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); |
636f9d37 VP |
1809 | void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, |
1810 | unsigned int mask, unsigned int val); | |
2d277b3b | 1811 | void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); |
5ccf9d04 RL |
1812 | void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, |
1813 | bool sleep_ok); | |
1814 | void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, | |
1815 | bool sleep_ok); | |
1816 | void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, | |
1817 | bool sleep_ok); | |
1818 | void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, | |
1819 | bool sleep_ok); | |
625ba2c2 | 1820 | void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, |
5ccf9d04 | 1821 | struct tp_tcp_stats *v6, bool sleep_ok); |
a6222975 | 1822 | void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, |
5ccf9d04 | 1823 | struct tp_fcoe_stats *st, bool sleep_ok); |
625ba2c2 DM |
1824 | void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, |
1825 | const unsigned short *alpha, const unsigned short *beta); | |
1826 | ||
797ff0f5 HS |
1827 | void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); |
1828 | ||
7864026b | 1829 | void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); |
f2b7e78d VP |
1830 | void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); |
1831 | ||
625ba2c2 DM |
1832 | void t4_wol_magic_enable(struct adapter *adap, unsigned int port, |
1833 | const u8 *addr); | |
1834 | int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, | |
1835 | u64 mask0, u64 mask1, unsigned int crc, bool enable); | |
1836 | ||
1837 | int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, | |
1838 | enum dev_master master, enum dev_state *state); | |
1839 | int t4_fw_bye(struct adapter *adap, unsigned int mbox); | |
1840 | int t4_early_init(struct adapter *adap, unsigned int mbox); | |
1841 | int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); | |
636f9d37 VP |
1842 | int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, |
1843 | unsigned int cache_line_size); | |
1844 | int t4_fw_initialize(struct adapter *adap, unsigned int mbox); | |
625ba2c2 DM |
1845 | int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1846 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1847 | u32 *val); | |
8f46d467 AV |
1848 | int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1849 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1850 | u32 *val); | |
01b69614 HS |
1851 | int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1852 | unsigned int vf, unsigned int nparams, const u32 *params, | |
8f46d467 | 1853 | u32 *val, int rw, bool sleep_ok); |
01b69614 HS |
1854 | int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, |
1855 | unsigned int pf, unsigned int vf, | |
1856 | unsigned int nparams, const u32 *params, | |
1857 | const u32 *val, int timeout); | |
625ba2c2 DM |
1858 | int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1859 | unsigned int vf, unsigned int nparams, const u32 *params, | |
1860 | const u32 *val); | |
1861 | int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1862 | unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, | |
1863 | unsigned int rxqi, unsigned int rxq, unsigned int tc, | |
1864 | unsigned int vi, unsigned int cmask, unsigned int pmask, | |
1865 | unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); | |
1866 | int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, | |
1867 | unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, | |
02d805dc | 1868 | unsigned int *rss_size, u8 *vivld, u8 *vin); |
4f3a0fcf HS |
1869 | int t4_free_vi(struct adapter *adap, unsigned int mbox, |
1870 | unsigned int pf, unsigned int vf, | |
1871 | unsigned int viid); | |
625ba2c2 | 1872 | int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, |
f8f5aafa DM |
1873 | int mtu, int promisc, int all_multi, int bcast, int vlanex, |
1874 | bool sleep_ok); | |
846eac3f GG |
1875 | int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, |
1876 | const u8 *addr, const u8 *mask, unsigned int idx, | |
1877 | u8 lookup_type, u8 port_id, bool sleep_ok); | |
98f3697f KS |
1878 | int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, |
1879 | bool sleep_ok); | |
1880 | int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, | |
1881 | const u8 *addr, const u8 *mask, unsigned int vni, | |
1882 | unsigned int vni_mask, u8 dip_hit, u8 lookup_type, | |
1883 | bool sleep_ok); | |
846eac3f GG |
1884 | int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, |
1885 | const u8 *addr, const u8 *mask, unsigned int idx, | |
1886 | u8 lookup_type, u8 port_id, bool sleep_ok); | |
625ba2c2 DM |
1887 | int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, |
1888 | unsigned int viid, bool free, unsigned int naddr, | |
1889 | const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); | |
fc08a01a HS |
1890 | int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, |
1891 | unsigned int viid, unsigned int naddr, | |
1892 | const u8 **addr, bool sleep_ok); | |
625ba2c2 | 1893 | int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, |
02d805dc | 1894 | int idx, const u8 *addr, bool persist, u8 *smt_idx); |
625ba2c2 DM |
1895 | int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, |
1896 | bool ucast, u64 vec, bool sleep_ok); | |
688848b1 AB |
1897 | int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, |
1898 | unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); | |
e2f4f4e9 AV |
1899 | int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, |
1900 | struct port_info *pi, | |
1901 | bool rx_en, bool tx_en, bool dcb_en); | |
625ba2c2 DM |
1902 | int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, |
1903 | bool rx_en, bool tx_en); | |
1904 | int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
1905 | unsigned int nblinks); | |
1906 | int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
1907 | unsigned int mmd, unsigned int reg, u16 *valp); | |
1908 | int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
1909 | unsigned int mmd, unsigned int reg, u16 val); | |
ebf4dc2b HS |
1910 | int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1911 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | |
1912 | unsigned int fl0id, unsigned int fl1id); | |
625ba2c2 DM |
1913 | int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, |
1914 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | |
1915 | unsigned int fl0id, unsigned int fl1id); | |
1916 | int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1917 | unsigned int vf, unsigned int eqid); | |
1918 | int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1919 | unsigned int vf, unsigned int eqid); | |
1920 | int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
1921 | unsigned int vf, unsigned int eqid); | |
736c3b94 | 1922 | int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); |
d429005f VK |
1923 | int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, |
1924 | u16 *dbqtimers); | |
23853a0a | 1925 | void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); |
2061ec3f | 1926 | int t4_update_port_info(struct port_info *pi); |
c3168cab GG |
1927 | int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, |
1928 | unsigned int *speedp, unsigned int *mtup); | |
625ba2c2 | 1929 | int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); |
881806bc VP |
1930 | void t4_db_full(struct adapter *adapter); |
1931 | void t4_db_dropped(struct adapter *adapter); | |
8e3d04fd HS |
1932 | int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, |
1933 | int filter_index, int enable); | |
1934 | void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, | |
1935 | int filter_index, int *enabled); | |
8caa1e84 VP |
1936 | int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, |
1937 | u32 addr, u32 val); | |
08c4901b RL |
1938 | void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); |
1939 | void t4_get_tx_sched(struct adapter *adap, unsigned int sched, | |
1940 | unsigned int *kbps, unsigned int *ipg, bool sleep_ok); | |
9e5c598c RL |
1941 | int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, |
1942 | enum ctxt_type ctype, u32 *data); | |
1943 | int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, | |
1944 | enum ctxt_type ctype, u32 *data); | |
b72a32da RL |
1945 | int t4_sched_params(struct adapter *adapter, int type, int level, int mode, |
1946 | int rateunit, int ratemode, int channel, int class, | |
1947 | int minrate, int maxrate, int weight, int pktsize); | |
68bce192 | 1948 | void t4_sge_decode_idma_state(struct adapter *adapter, int state); |
a3bfb617 HS |
1949 | void t4_idma_monitor_init(struct adapter *adapter, |
1950 | struct sge_idma_monitor_state *idma); | |
1951 | void t4_idma_monitor(struct adapter *adapter, | |
1952 | struct sge_idma_monitor_state *idma, | |
1953 | int hz, int ticks); | |
858aa65c HS |
1954 | int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, |
1955 | unsigned int naddr, u8 *addr); | |
5ccf9d04 RL |
1956 | void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, |
1957 | u32 start_index, bool sleep_ok); | |
4359cf33 RL |
1958 | void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, |
1959 | u32 start_index, bool sleep_ok); | |
5ccf9d04 RL |
1960 | void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, |
1961 | u32 start_index, bool sleep_ok); | |
1962 | ||
0fbc81b3 HS |
1963 | void t4_uld_mem_free(struct adapter *adap); |
1964 | int t4_uld_mem_alloc(struct adapter *adap); | |
1965 | void t4_uld_clean_up(struct adapter *adap); | |
1966 | void t4_register_netevent_notifier(void); | |
f56ec676 AV |
1967 | int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, |
1968 | unsigned int devid, unsigned int offset, | |
1969 | unsigned int len, u8 *buf); | |
94cdb8bb | 1970 | void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); |
ab677ff4 HS |
1971 | void free_tx_desc(struct adapter *adap, struct sge_txq *q, |
1972 | unsigned int n, bool unmap); | |
b1396c2b RL |
1973 | void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, |
1974 | u32 ndesc); | |
0e395b3c | 1975 | int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); |
b1396c2b | 1976 | void cxgb4_ethofld_restart(unsigned long data); |
4846d533 RL |
1977 | int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, |
1978 | const struct pkt_gl *si); | |
ab677ff4 | 1979 | void free_txq(struct adapter *adap, struct sge_txq *q); |
a6ec572b AG |
1980 | void cxgb4_reclaim_completed_tx(struct adapter *adap, |
1981 | struct sge_txq *q, bool unmap); | |
1982 | int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, | |
1983 | dma_addr_t *addr); | |
1984 | void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, | |
1985 | void *pos); | |
1986 | void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, | |
1987 | struct ulptx_sgl *sgl, u64 *end, unsigned int start, | |
1988 | const dma_addr_t *addr); | |
1989 | void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); | |
9d5fd927 GG |
1990 | int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, |
1991 | u16 vlan); | |
ebddd97a | 1992 | int cxgb4_dcb_enabled(const struct net_device *dev); |
b1871915 | 1993 | |
b1871915 GG |
1994 | int cxgb4_thermal_init(struct adapter *adap); |
1995 | int cxgb4_thermal_remove(struct adapter *adap); | |
c9765074 NK |
1996 | int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, |
1997 | cpumask_var_t *aff_mask, int idx); | |
1998 | void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); | |
b1871915 | 1999 | |
2f0b9406 RR |
2000 | int cxgb4_change_mac(struct port_info *pi, unsigned int viid, |
2001 | int *tcam_idx, const u8 *addr, | |
2002 | bool persistent, u8 *smt_idx); | |
2003 | ||
f9f329ad RR |
2004 | int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, |
2005 | bool free, unsigned int naddr, | |
2006 | const u8 **addr, u16 *idx, | |
2007 | u64 *hash, bool sleep_ok); | |
2008 | int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, | |
2009 | unsigned int naddr, const u8 **addr, bool sleep_ok); | |
28b38705 RR |
2010 | int cxgb4_init_mps_ref_entries(struct adapter *adap); |
2011 | void cxgb4_free_mps_ref_entries(struct adapter *adap); | |
2012 | int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, | |
2013 | const u8 *addr, const u8 *mask, | |
2014 | unsigned int vni, unsigned int vni_mask, | |
2015 | u8 dip_hit, u8 lookup_type, bool sleep_ok); | |
2016 | int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, | |
2017 | int idx, bool sleep_ok); | |
5fab5158 RR |
2018 | int cxgb4_free_raw_mac_filt(struct adapter *adap, |
2019 | unsigned int viid, | |
2020 | const u8 *addr, | |
2021 | const u8 *mask, | |
2022 | unsigned int idx, | |
2023 | u8 lookup_type, | |
2024 | u8 port_id, | |
2025 | bool sleep_ok); | |
2026 | int cxgb4_alloc_raw_mac_filt(struct adapter *adap, | |
2027 | unsigned int viid, | |
2028 | const u8 *addr, | |
2029 | const u8 *mask, | |
2030 | unsigned int idx, | |
2031 | u8 lookup_type, | |
2032 | u8 port_id, | |
2033 | bool sleep_ok); | |
2f0b9406 RR |
2034 | int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, |
2035 | int *tcam_idx, const u8 *addr, | |
2036 | bool persistent, u8 *smt_idx); | |
76c3a552 RL |
2037 | int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); |
2038 | void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); | |
b1396c2b RL |
2039 | int cxgb_open(struct net_device *dev); |
2040 | int cxgb_close(struct net_device *dev); | |
2d0cb84d RL |
2041 | void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); |
2042 | void cxgb4_quiesce_rx(struct sge_rspq *q); | |
625ba2c2 | 2043 | #endif /* __CXGB4_H__ */ |