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net: reduce USB network driver config options.
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
b8ff05a9
DM		 64#include <asm/uaccess.h>
65
66#include "cxgb4.h"
67#include "t4_regs.h"
68#include "t4_msg.h"
69#include "t4fw_api.h"
688848b1 70#include "cxgb4_dcb.h"
b8ff05a9
DM		 71#include "l2t.h"
72
01bcca68
VP		 73#include <../drivers/net/bonding/bonding.h>
74
75#ifdef DRV_VERSION
76#undef DRV_VERSION
77#endif
3a7f8554
SR		 78#define DRV_VERSION "2.0.0-ko"
79#define DRV_DESC "Chelsio T4/T5 Network Driver"
b8ff05a9
DM		 80
81/*
82 * Max interrupt hold-off timer value in us. Queues fall back to this value
83 * under extreme memory pressure so it's largish to give the system time to
84 * recover.
85 */
86#define MAX_SGE_TIMERVAL 200U
87
7ee9ff94 88enum {
13ee15d3
VP		 89 /*
90 * Physical Function provisioning constants.
91 */
92 PFRES_NVI = 4, /* # of Virtual Interfaces */
93 PFRES_NETHCTRL = 128, /* # of EQs used for ETH or CTRL Qs */
94 PFRES_NIQFLINT = 128, /* # of ingress Qs/w Free List(s)/intr
95 */
96 PFRES_NEQ = 256, /* # of egress queues */
97 PFRES_NIQ = 0, /* # of ingress queues */
98 PFRES_TC = 0, /* PCI-E traffic class */
99 PFRES_NEXACTF = 128, /* # of exact MPS filters */
100
101 PFRES_R_CAPS = FW_CMD_CAP_PF,
102 PFRES_WX_CAPS = FW_CMD_CAP_PF,
103
104#ifdef CONFIG_PCI_IOV
105 /*
106 * Virtual Function provisioning constants. We need two extra Ingress
107 * Queues with Interrupt capability to serve as the VF's Firmware
108 * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
109 * neither will have Free Lists associated with them). For each
110 * Ethernet/Control Egress Queue and for each Free List, we need an
111 * Egress Context.
112 */
7ee9ff94
CL		 113 VFRES_NPORTS = 1, /* # of "ports" per VF */
114 VFRES_NQSETS = 2, /* # of "Queue Sets" per VF */
115
116 VFRES_NVI = VFRES_NPORTS, /* # of Virtual Interfaces */
117 VFRES_NETHCTRL = VFRES_NQSETS, /* # of EQs used for ETH or CTRL Qs */
118 VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
7ee9ff94 119 VFRES_NEQ = VFRES_NQSETS*2, /* # of egress queues */
13ee15d3 120 VFRES_NIQ = 0, /* # of non-fl/int ingress queues */
7ee9ff94
CL		 121 VFRES_TC = 0, /* PCI-E traffic class */
122 VFRES_NEXACTF = 16, /* # of exact MPS filters */
123
124 VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
125 VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
13ee15d3 126#endif
7ee9ff94
CL		 127};
128
129/*
130 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
131 * static and likely not to be useful in the long run. We really need to
132 * implement some form of persistent configuration which the firmware
133 * controls.
134 */
135static unsigned int pfvfres_pmask(struct adapter *adapter,
136 unsigned int pf, unsigned int vf)
137{
138 unsigned int portn, portvec;
139
140 /*
141 * Give PF's access to all of the ports.
142 */
143 if (vf == 0)
144 return FW_PFVF_CMD_PMASK_MASK;
145
146 /*
147 * For VFs, we'll assign them access to the ports based purely on the
148 * PF. We assign active ports in order, wrapping around if there are
149 * fewer active ports than PFs: e.g. active port[pf % nports].
150 * Unfortunately the adapter's port_info structs haven't been
151 * initialized yet so we have to compute this.
152 */
153 if (adapter->params.nports == 0)
154 return 0;
155
156 portn = pf % adapter->params.nports;
157 portvec = adapter->params.portvec;
158 for (;;) {
159 /*
160 * Isolate the lowest set bit in the port vector. If we're at
161 * the port number that we want, return that as the pmask.
162 * otherwise mask that bit out of the port vector and
163 * decrement our port number ...
164 */
165 unsigned int pmask = portvec ^ (portvec & (portvec-1));
166 if (portn == 0)
167 return pmask;
168 portn--;
169 portvec &= ~pmask;
170 }
171 /*NOTREACHED*/
172}
7ee9ff94 173
b8ff05a9
DM		 174enum {
175 MAX_TXQ_ENTRIES = 16384,
176 MAX_CTRL_TXQ_ENTRIES = 1024,
177 MAX_RSPQ_ENTRIES = 16384,
178 MAX_RX_BUFFERS = 16384,
179 MIN_TXQ_ENTRIES = 32,
180 MIN_CTRL_TXQ_ENTRIES = 32,
181 MIN_RSPQ_ENTRIES = 128,
182 MIN_FL_ENTRIES = 16
183};
184
f2b7e78d
VP		 185/* Host shadow copy of ingress filter entry. This is in host native format
186 * and doesn't match the ordering or bit order, etc. of the hardware of the
187 * firmware command. The use of bit-field structure elements is purely to
188 * remind ourselves of the field size limitations and save memory in the case
189 * where the filter table is large.
190 */
191struct filter_entry {
192 /* Administrative fields for filter.
193 */
194 u32 valid:1; /* filter allocated and valid */
195 u32 locked:1; /* filter is administratively locked */
196
197 u32 pending:1; /* filter action is pending firmware reply */
198 u32 smtidx:8; /* Source MAC Table index for smac */
199 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
200
201 /* The filter itself. Most of this is a straight copy of information
202 * provided by the extended ioctl(). Some fields are translated to
203 * internal forms -- for instance the Ingress Queue ID passed in from
204 * the ioctl() is translated into the Absolute Ingress Queue ID.
205 */
206 struct ch_filter_specification fs;
207};
208
b8ff05a9
DM		 209#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
210 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
211 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
212
060e0c75 213#define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
b8ff05a9
DM		 214
215static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
060e0c75 216 CH_DEVICE(0xa000, 0), /* PE10K */
ccea790e
DM		 217 CH_DEVICE(0x4001, -1),
218 CH_DEVICE(0x4002, -1),
219 CH_DEVICE(0x4003, -1),
220 CH_DEVICE(0x4004, -1),
221 CH_DEVICE(0x4005, -1),
222 CH_DEVICE(0x4006, -1),
223 CH_DEVICE(0x4007, -1),
224 CH_DEVICE(0x4008, -1),
225 CH_DEVICE(0x4009, -1),
226 CH_DEVICE(0x400a, -1),
fb1e933d
HS		 227 CH_DEVICE(0x400d, -1),
228 CH_DEVICE(0x400e, -1),
229 CH_DEVICE(0x4080, -1),
230 CH_DEVICE(0x4081, -1),
231 CH_DEVICE(0x4082, -1),
232 CH_DEVICE(0x4083, -1),
233 CH_DEVICE(0x4084, -1),
234 CH_DEVICE(0x4085, -1),
235 CH_DEVICE(0x4086, -1),
236 CH_DEVICE(0x4087, -1),
237 CH_DEVICE(0x4088, -1),
ccea790e
DM		 238 CH_DEVICE(0x4401, 4),
239 CH_DEVICE(0x4402, 4),
240 CH_DEVICE(0x4403, 4),
241 CH_DEVICE(0x4404, 4),
242 CH_DEVICE(0x4405, 4),
243 CH_DEVICE(0x4406, 4),
244 CH_DEVICE(0x4407, 4),
245 CH_DEVICE(0x4408, 4),
246 CH_DEVICE(0x4409, 4),
247 CH_DEVICE(0x440a, 4),
f637d577
VP		 248 CH_DEVICE(0x440d, 4),
249 CH_DEVICE(0x440e, 4),
fb1e933d
HS		 250 CH_DEVICE(0x4480, 4),
251 CH_DEVICE(0x4481, 4),
252 CH_DEVICE(0x4482, 4),
253 CH_DEVICE(0x4483, 4),
254 CH_DEVICE(0x4484, 4),
255 CH_DEVICE(0x4485, 4),
256 CH_DEVICE(0x4486, 4),
257 CH_DEVICE(0x4487, 4),
258 CH_DEVICE(0x4488, 4),
9ef603a0
VP		 259 CH_DEVICE(0x5001, 4),
260 CH_DEVICE(0x5002, 4),
261 CH_DEVICE(0x5003, 4),
262 CH_DEVICE(0x5004, 4),
263 CH_DEVICE(0x5005, 4),
264 CH_DEVICE(0x5006, 4),
265 CH_DEVICE(0x5007, 4),
266 CH_DEVICE(0x5008, 4),
267 CH_DEVICE(0x5009, 4),
268 CH_DEVICE(0x500A, 4),
269 CH_DEVICE(0x500B, 4),
270 CH_DEVICE(0x500C, 4),
271 CH_DEVICE(0x500D, 4),
272 CH_DEVICE(0x500E, 4),
273 CH_DEVICE(0x500F, 4),
274 CH_DEVICE(0x5010, 4),
275 CH_DEVICE(0x5011, 4),
276 CH_DEVICE(0x5012, 4),
277 CH_DEVICE(0x5013, 4),
f0a8e6de
HS		 278 CH_DEVICE(0x5014, 4),
279 CH_DEVICE(0x5015, 4),
0183aa62
HS		 280 CH_DEVICE(0x5080, 4),
281 CH_DEVICE(0x5081, 4),
282 CH_DEVICE(0x5082, 4),
283 CH_DEVICE(0x5083, 4),
284 CH_DEVICE(0x5084, 4),
285 CH_DEVICE(0x5085, 4),
9ef603a0
VP		 286 CH_DEVICE(0x5401, 4),
287 CH_DEVICE(0x5402, 4),
288 CH_DEVICE(0x5403, 4),
289 CH_DEVICE(0x5404, 4),
290 CH_DEVICE(0x5405, 4),
291 CH_DEVICE(0x5406, 4),
292 CH_DEVICE(0x5407, 4),
293 CH_DEVICE(0x5408, 4),
294 CH_DEVICE(0x5409, 4),
295 CH_DEVICE(0x540A, 4),
296 CH_DEVICE(0x540B, 4),
297 CH_DEVICE(0x540C, 4),
298 CH_DEVICE(0x540D, 4),
299 CH_DEVICE(0x540E, 4),
300 CH_DEVICE(0x540F, 4),
301 CH_DEVICE(0x5410, 4),
302 CH_DEVICE(0x5411, 4),
303 CH_DEVICE(0x5412, 4),
304 CH_DEVICE(0x5413, 4),
f0a8e6de
HS		 305 CH_DEVICE(0x5414, 4),
306 CH_DEVICE(0x5415, 4),
0183aa62
HS		 307 CH_DEVICE(0x5480, 4),
308 CH_DEVICE(0x5481, 4),
309 CH_DEVICE(0x5482, 4),
310 CH_DEVICE(0x5483, 4),
311 CH_DEVICE(0x5484, 4),
312 CH_DEVICE(0x5485, 4),
b8ff05a9
DM		 313 { 0, }
314};
315
16e47624 316#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 317#define FW5_FNAME "cxgb4/t5fw.bin"
16e47624 318#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 319#define FW5_CFNAME "cxgb4/t5-config.txt"
b8ff05a9
DM		 320
321MODULE_DESCRIPTION(DRV_DESC);
322MODULE_AUTHOR("Chelsio Communications");
323MODULE_LICENSE("Dual BSD/GPL");
324MODULE_VERSION(DRV_VERSION);
325MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 326MODULE_FIRMWARE(FW4_FNAME);
0a57a536 327MODULE_FIRMWARE(FW5_FNAME);
b8ff05a9 328
636f9d37
VP		 329/*
330 * Normally we're willing to become the firmware's Master PF but will be happy
331 * if another PF has already become the Master and initialized the adapter.
332 * Setting "force_init" will cause this driver to forcibly establish itself as
333 * the Master PF and initialize the adapter.
334 */
335static uint force_init;
336
337module_param(force_init, uint, 0644);
338MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
339
13ee15d3
VP		 340/*
341 * Normally if the firmware we connect to has Configuration File support, we
342 * use that and only fall back to the old Driver-based initialization if the
343 * Configuration File fails for some reason. If force_old_init is set, then
344 * we'll always use the old Driver-based initialization sequence.
345 */
346static uint force_old_init;
347
348module_param(force_old_init, uint, 0644);
349MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
350
b8ff05a9
DM		 351static int dflt_msg_enable = DFLT_MSG_ENABLE;
352
353module_param(dflt_msg_enable, int, 0644);
354MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
355
356/*
357 * The driver uses the best interrupt scheme available on a platform in the
358 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
359 * of these schemes the driver may consider as follows:
360 *
361 * msi = 2: choose from among all three options
362 * msi = 1: only consider MSI and INTx interrupts
363 * msi = 0: force INTx interrupts
364 */
365static int msi = 2;
366
367module_param(msi, int, 0644);
368MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
369
370/*
371 * Queue interrupt hold-off timer values. Queues default to the first of these
372 * upon creation.
373 */
374static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
375
376module_param_array(intr_holdoff, uint, NULL, 0644);
377MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
378 "0..4 in microseconds");
379
380static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
381
382module_param_array(intr_cnt, uint, NULL, 0644);
383MODULE_PARM_DESC(intr_cnt,
384 "thresholds 1..3 for queue interrupt packet counters");
385
636f9d37
VP		 386/*
387 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
388 * offset by 2 bytes in order to have the IP headers line up on 4-byte
389 * boundaries. This is a requirement for many architectures which will throw
390 * a machine check fault if an attempt is made to access one of the 4-byte IP
391 * header fields on a non-4-byte boundary. And it's a major performance issue
392 * even on some architectures which allow it like some implementations of the
393 * x86 ISA. However, some architectures don't mind this and for some very
394 * edge-case performance sensitive applications (like forwarding large volumes
395 * of small packets), setting this DMA offset to 0 will decrease the number of
396 * PCI-E Bus transfers enough to measurably affect performance.
397 */
398static int rx_dma_offset = 2;
399
eb939922 400static bool vf_acls;
b8ff05a9
DM		 401
402#ifdef CONFIG_PCI_IOV
403module_param(vf_acls, bool, 0644);
404MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
405
7d6727cf
SR		 406/* Configure the number of PCI-E Virtual Function which are to be instantiated
407 * on SR-IOV Capable Physical Functions.
0a57a536 408 */
7d6727cf 409static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
b8ff05a9
DM		 410
411module_param_array(num_vf, uint, NULL, 0644);
7d6727cf 412MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
b8ff05a9
DM		 413#endif
414
688848b1
AB		 415/* TX Queue select used to determine what algorithm to use for selecting TX
416 * queue. Select between the kernel provided function (select_queue=0) or user
417 * cxgb_select_queue function (select_queue=1)
418 *
419 * Default: select_queue=0
420 */
421static int select_queue;
422module_param(select_queue, int, 0644);
423MODULE_PARM_DESC(select_queue,
424 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
425
13ee15d3
VP		 426/*
427 * The filter TCAM has a fixed portion and a variable portion. The fixed
428 * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
429 * ports. The variable portion is 36 bits which can include things like Exact
430 * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
431 * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
432 * far exceed the 36-bit budget for this "compressed" header portion of the
433 * filter. Thus, we have a scarce resource which must be carefully managed.
434 *
435 * By default we set this up to mostly match the set of filter matching
436 * capabilities of T3 but with accommodations for some of T4's more
437 * interesting features:
438 *
439 * { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
440 * [Inner] VLAN (17), Port (3), FCoE (1) }
441 */
442enum {
443 TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
444 TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
445 TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
446};
447
448static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
449
f2b7e78d
VP		 450module_param(tp_vlan_pri_map, uint, 0644);
451MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
452
b8ff05a9
DM		 453static struct dentry *cxgb4_debugfs_root;
454
455static LIST_HEAD(adapter_list);
456static DEFINE_MUTEX(uld_mutex);
01bcca68
VP		 457/* Adapter list to be accessed from atomic context */
458static LIST_HEAD(adap_rcu_list);
459static DEFINE_SPINLOCK(adap_rcu_lock);
b8ff05a9
DM		 460static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
461static const char *uld_str[] = { "RDMA", "iSCSI" };
462
463static void link_report(struct net_device *dev)
464{
465 if (!netif_carrier_ok(dev))
466 netdev_info(dev, "link down\n");
467 else {
468 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
469
470 const char *s = "10Mbps";
471 const struct port_info *p = netdev_priv(dev);
472
473 switch (p->link_cfg.speed) {
e8b39015 474 case 10000:
b8ff05a9
DM		 475 s = "10Gbps";
476 break;
e8b39015 477 case 1000:
b8ff05a9
DM		 478 s = "1000Mbps";
479 break;
e8b39015 480 case 100:
b8ff05a9
DM		 481 s = "100Mbps";
482 break;
e8b39015 483 case 40000:
72aca4bf
KS		 484 s = "40Gbps";
485 break;
b8ff05a9
DM		 486 }
487
488 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
489 fc[p->link_cfg.fc]);
490 }
491}
492
688848b1
AB		 493#ifdef CONFIG_CHELSIO_T4_DCB
494/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
495static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
496{
497 struct port_info *pi = netdev_priv(dev);
498 struct adapter *adap = pi->adapter;
499 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
500 int i;
501
502 /* We use a simple mapping of Port TX Queue Index to DCB
503 * Priority when we're enabling DCB.
504 */
505 for (i = 0; i < pi->nqsets; i++, txq++) {
506 u32 name, value;
507 int err;
508
509 name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
510 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
511 FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
512 value = enable ? i : 0xffffffff;
513
514 /* Since we can be called while atomic (from "interrupt
515 * level") we need to issue the Set Parameters Commannd
516 * without sleeping (timeout < 0).
517 */
518 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
519 &name, &value);
520
521 if (err)
522 dev_err(adap->pdev_dev,
523 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
524 enable ? "set" : "unset", pi->port_id, i, -err);
525 }
526}
527#endif /* CONFIG_CHELSIO_T4_DCB */
528
b8ff05a9
DM		 529void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
530{
531 struct net_device *dev = adapter->port[port_id];
532
533 /* Skip changes from disabled ports. */
534 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
535 if (link_stat)
536 netif_carrier_on(dev);
688848b1
AB		 537 else {
538#ifdef CONFIG_CHELSIO_T4_DCB
539 cxgb4_dcb_state_init(dev);
540 dcb_tx_queue_prio_enable(dev, false);
541#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 542 netif_carrier_off(dev);
688848b1 543 }
b8ff05a9
DM		 544
545 link_report(dev);
546 }
547}
548
549void t4_os_portmod_changed(const struct adapter *adap, int port_id)
550{
551 static const char *mod_str[] = {
a0881cab 552 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 553 };
554
555 const struct net_device *dev = adap->port[port_id];
556 const struct port_info *pi = netdev_priv(dev);
557
558 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
559 netdev_info(dev, "port module unplugged\n");
a0881cab 560 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9
DM		 561 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
562}
563
564/*
565 * Configure the exact and hash address filters to handle a port's multicast
566 * and secondary unicast MAC addresses.
567 */
568static int set_addr_filters(const struct net_device *dev, bool sleep)
569{
570 u64 mhash = 0;
571 u64 uhash = 0;
572 bool free = true;
573 u16 filt_idx[7];
574 const u8 *addr[7];
575 int ret, naddr = 0;
b8ff05a9
DM		 576 const struct netdev_hw_addr *ha;
577 int uc_cnt = netdev_uc_count(dev);
4a35ecf8 578 int mc_cnt = netdev_mc_count(dev);
b8ff05a9 579 const struct port_info *pi = netdev_priv(dev);
060e0c75 580 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM		 581
582 /* first do the secondary unicast addresses */
583 netdev_for_each_uc_addr(ha, dev) {
584 addr[naddr++] = ha->addr;
585 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 586 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 587 naddr, addr, filt_idx, &uhash, sleep);
588 if (ret < 0)
589 return ret;
590
591 free = false;
592 naddr = 0;
593 }
594 }
595
596 /* next set up the multicast addresses */
4a35ecf8
DM		 597 netdev_for_each_mc_addr(ha, dev) {
598 addr[naddr++] = ha->addr;
599 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 600 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM		 601 naddr, addr, filt_idx, &mhash, sleep);
602 if (ret < 0)
603 return ret;
604
605 free = false;
606 naddr = 0;
607 }
608 }
609
060e0c75 610 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
b8ff05a9
DM		 611 uhash | mhash, sleep);
612}
613
3069ee9b
VP		 614int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
615module_param(dbfifo_int_thresh, int, 0644);
616MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
617
404d9e3f
VP		 618/*
619 * usecs to sleep while draining the dbfifo
620 */
621static int dbfifo_drain_delay = 1000;
3069ee9b
VP		 622module_param(dbfifo_drain_delay, int, 0644);
623MODULE_PARM_DESC(dbfifo_drain_delay,
624 "usecs to sleep while draining the dbfifo");
625
b8ff05a9
DM		 626/*
627 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
628 * If @mtu is -1 it is left unchanged.
629 */
630static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
631{
632 int ret;
633 struct port_info *pi = netdev_priv(dev);
634
635 ret = set_addr_filters(dev, sleep_ok);
636 if (ret == 0)
060e0c75 637 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
b8ff05a9 638 (dev->flags & IFF_PROMISC) ? 1 : 0,
f8f5aafa 639 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
b8ff05a9
DM		 640 sleep_ok);
641 return ret;
642}
643
3069ee9b
VP		 644static struct workqueue_struct *workq;
645
b8ff05a9
DM		 646/**
647 * link_start - enable a port
648 * @dev: the port to enable
649 *
650 * Performs the MAC and PHY actions needed to enable a port.
651 */
652static int link_start(struct net_device *dev)
653{
654 int ret;
655 struct port_info *pi = netdev_priv(dev);
060e0c75 656 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM		 657
658 /*
659 * We do not set address filters and promiscuity here, the stack does
660 * that step explicitly.
661 */
060e0c75 662 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 663 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 664 if (ret == 0) {
060e0c75 665 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 666 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 667 true);
b8ff05a9
DM		 668 if (ret >= 0) {
669 pi->xact_addr_filt = ret;
670 ret = 0;
671 }
672 }
673 if (ret == 0)
060e0c75
DM		 674 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
675 &pi->link_cfg);
b8ff05a9 676 if (ret == 0)
688848b1
AB		 677 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
678 true, CXGB4_DCB_ENABLED);
679
b8ff05a9
DM		 680 return ret;
681}
682
688848b1
AB		 683int cxgb4_dcb_enabled(const struct net_device *dev)
684{
685#ifdef CONFIG_CHELSIO_T4_DCB
686 struct port_info *pi = netdev_priv(dev);
687
688 return pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED;
689#else
690 return 0;
691#endif
692}
693EXPORT_SYMBOL(cxgb4_dcb_enabled);
694
695#ifdef CONFIG_CHELSIO_T4_DCB
696/* Handle a Data Center Bridging update message from the firmware. */
697static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
698{
699 int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
700 struct net_device *dev = adap->port[port];
701 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
702 int new_dcb_enabled;
703
704 cxgb4_dcb_handle_fw_update(adap, pcmd);
705 new_dcb_enabled = cxgb4_dcb_enabled(dev);
706
707 /* If the DCB has become enabled or disabled on the port then we're
708 * going to need to set up/tear down DCB Priority parameters for the
709 * TX Queues associated with the port.
710 */
711 if (new_dcb_enabled != old_dcb_enabled)
712 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
713}
714#endif /* CONFIG_CHELSIO_T4_DCB */
715
f2b7e78d
VP		 716/* Clear a filter and release any of its resources that we own. This also
717 * clears the filter's "pending" status.
718 */
719static void clear_filter(struct adapter *adap, struct filter_entry *f)
720{
721 /* If the new or old filter have loopback rewriteing rules then we'll
722 * need to free any existing Layer Two Table (L2T) entries of the old
723 * filter rule. The firmware will handle freeing up any Source MAC
724 * Table (SMT) entries used for rewriting Source MAC Addresses in
725 * loopback rules.
726 */
727 if (f->l2t)
728 cxgb4_l2t_release(f->l2t);
729
730 /* The zeroing of the filter rule below clears the filter valid,
731 * pending, locked flags, l2t pointer, etc. so it's all we need for
732 * this operation.
733 */
734 memset(f, 0, sizeof(*f));
735}
736
737/* Handle a filter write/deletion reply.
738 */
739static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
740{
741 unsigned int idx = GET_TID(rpl);
742 unsigned int nidx = idx - adap->tids.ftid_base;
743 unsigned int ret;
744 struct filter_entry *f;
745
746 if (idx >= adap->tids.ftid_base && nidx <
747 (adap->tids.nftids + adap->tids.nsftids)) {
748 idx = nidx;
749 ret = GET_TCB_COOKIE(rpl->cookie);
750 f = &adap->tids.ftid_tab[idx];
751
752 if (ret == FW_FILTER_WR_FLT_DELETED) {
753 /* Clear the filter when we get confirmation from the
754 * hardware that the filter has been deleted.
755 */
756 clear_filter(adap, f);
757 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
758 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
759 idx);
760 clear_filter(adap, f);
761 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
762 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
763 f->pending = 0; /* asynchronous setup completed */
764 f->valid = 1;
765 } else {
766 /* Something went wrong. Issue a warning about the
767 * problem and clear everything out.
768 */
769 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
770 idx, ret);
771 clear_filter(adap, f);
772 }
773 }
774}
775
776/* Response queue handler for the FW event queue.
b8ff05a9
DM		 777 */
778static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
779 const struct pkt_gl *gl)
780{
781 u8 opcode = ((const struct rss_header *)rsp)->opcode;
782
783 rsp++; /* skip RSS header */
b407a4a9
VP		 784
785 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
786 */
787 if (unlikely(opcode == CPL_FW4_MSG &&
788 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
789 rsp++;
790 opcode = ((const struct rss_header *)rsp)->opcode;
791 rsp++;
792 if (opcode != CPL_SGE_EGR_UPDATE) {
793 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
794 , opcode);
795 goto out;
796 }
797 }
798
b8ff05a9
DM		 799 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
800 const struct cpl_sge_egr_update *p = (void *)rsp;
801 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
e46dab4d 802 struct sge_txq *txq;
b8ff05a9 803
e46dab4d 804 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 805 txq->restarts++;
e46dab4d 806 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
b8ff05a9
DM		 807 struct sge_eth_txq *eq;
808
809 eq = container_of(txq, struct sge_eth_txq, q);
810 netif_tx_wake_queue(eq->txq);
811 } else {
812 struct sge_ofld_txq *oq;
813
814 oq = container_of(txq, struct sge_ofld_txq, q);
815 tasklet_schedule(&oq->qresume_tsk);
816 }
817 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
818 const struct cpl_fw6_msg *p = (void *)rsp;
819
688848b1
AB		 820#ifdef CONFIG_CHELSIO_T4_DCB
821 const struct fw_port_cmd *pcmd = (const void *)p->data;
822 unsigned int cmd = FW_CMD_OP_GET(ntohl(pcmd->op_to_portid));
823 unsigned int action =
824 FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
825
826 if (cmd == FW_PORT_CMD &&
827 action == FW_PORT_ACTION_GET_PORT_INFO) {
828 int port = FW_PORT_CMD_PORTID_GET(
829 be32_to_cpu(pcmd->op_to_portid));
830 struct net_device *dev = q->adap->port[port];
831 int state_input = ((pcmd->u.info.dcbxdis_pkd &
832 FW_PORT_CMD_DCBXDIS)
833 ? CXGB4_DCB_INPUT_FW_DISABLED
834 : CXGB4_DCB_INPUT_FW_ENABLED);
835
836 cxgb4_dcb_state_fsm(dev, state_input);
837 }
838
839 if (cmd == FW_PORT_CMD &&
840 action == FW_PORT_ACTION_L2_DCB_CFG)
841 dcb_rpl(q->adap, pcmd);
842 else
843#endif
844 if (p->type == 0)
845 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 846 } else if (opcode == CPL_L2T_WRITE_RPL) {
847 const struct cpl_l2t_write_rpl *p = (void *)rsp;
848
849 do_l2t_write_rpl(q->adap, p);
f2b7e78d
VP		 850 } else if (opcode == CPL_SET_TCB_RPL) {
851 const struct cpl_set_tcb_rpl *p = (void *)rsp;
852
853 filter_rpl(q->adap, p);
b8ff05a9
DM		 854 } else
855 dev_err(q->adap->pdev_dev,
856 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 857out:
b8ff05a9
DM		 858 return 0;
859}
860
861/**
862 * uldrx_handler - response queue handler for ULD queues
863 * @q: the response queue that received the packet
864 * @rsp: the response queue descriptor holding the offload message
865 * @gl: the gather list of packet fragments
866 *
867 * Deliver an ingress offload packet to a ULD. All processing is done by
868 * the ULD, we just maintain statistics.
869 */
870static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
871 const struct pkt_gl *gl)
872{
873 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
874
b407a4a9
VP		 875 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
876 */
877 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
878 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
879 rsp += 2;
880
b8ff05a9
DM		 881 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
882 rxq->stats.nomem++;
883 return -1;
884 }
885 if (gl == NULL)
886 rxq->stats.imm++;
887 else if (gl == CXGB4_MSG_AN)
888 rxq->stats.an++;
889 else
890 rxq->stats.pkts++;
891 return 0;
892}
893
894static void disable_msi(struct adapter *adapter)
895{
896 if (adapter->flags & USING_MSIX) {
897 pci_disable_msix(adapter->pdev);
898 adapter->flags &= ~USING_MSIX;
899 } else if (adapter->flags & USING_MSI) {
900 pci_disable_msi(adapter->pdev);
901 adapter->flags &= ~USING_MSI;
902 }
903}
904
905/*
906 * Interrupt handler for non-data events used with MSI-X.
907 */
908static irqreturn_t t4_nondata_intr(int irq, void *cookie)
909{
910 struct adapter *adap = cookie;
911
912 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
913 if (v & PFSW) {
914 adap->swintr = 1;
915 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
916 }
917 t4_slow_intr_handler(adap);
918 return IRQ_HANDLED;
919}
920
921/*
922 * Name the MSI-X interrupts.
923 */
924static void name_msix_vecs(struct adapter *adap)
925{
ba27816c 926 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 927
928 /* non-data interrupts */
b1a3c2b6 929 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 930
931 /* FW events */
b1a3c2b6
DM		 932 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
933 adap->port[0]->name);
b8ff05a9
DM		 934
935 /* Ethernet queues */
936 for_each_port(adap, j) {
937 struct net_device *d = adap->port[j];
938 const struct port_info *pi = netdev_priv(d);
939
ba27816c 940 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 941 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
942 d->name, i);
b8ff05a9
DM		 943 }
944
945 /* offload queues */
ba27816c
DM		 946 for_each_ofldrxq(&adap->sge, i)
947 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
b1a3c2b6 948 adap->port[0]->name, i);
ba27816c
DM		 949
950 for_each_rdmarxq(&adap->sge, i)
951 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
b1a3c2b6 952 adap->port[0]->name, i);
cf38be6d
HS		 953
954 for_each_rdmaciq(&adap->sge, i)
955 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
956 adap->port[0]->name, i);
b8ff05a9
DM		 957}
958
959static int request_msix_queue_irqs(struct adapter *adap)
960{
961 struct sge *s = &adap->sge;
cf38be6d
HS		 962 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
963 int msi_index = 2;
b8ff05a9
DM		 964
965 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
966 adap->msix_info[1].desc, &s->fw_evtq);
967 if (err)
968 return err;
969
970 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 971 err = request_irq(adap->msix_info[msi_index].vec,
972 t4_sge_intr_msix, 0,
973 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 974 &s->ethrxq[ethqidx].rspq);
975 if (err)
976 goto unwind;
404d9e3f 977 msi_index++;
b8ff05a9
DM		 978 }
979 for_each_ofldrxq(s, ofldqidx) {
404d9e3f
VP		 980 err = request_irq(adap->msix_info[msi_index].vec,
981 t4_sge_intr_msix, 0,
982 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 983 &s->ofldrxq[ofldqidx].rspq);
984 if (err)
985 goto unwind;
404d9e3f 986 msi_index++;
b8ff05a9
DM		 987 }
988 for_each_rdmarxq(s, rdmaqidx) {
404d9e3f
VP		 989 err = request_irq(adap->msix_info[msi_index].vec,
990 t4_sge_intr_msix, 0,
991 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 992 &s->rdmarxq[rdmaqidx].rspq);
993 if (err)
994 goto unwind;
404d9e3f 995 msi_index++;
b8ff05a9 996 }
cf38be6d
HS		 997 for_each_rdmaciq(s, rdmaciqqidx) {
998 err = request_irq(adap->msix_info[msi_index].vec,
999 t4_sge_intr_msix, 0,
1000 adap->msix_info[msi_index].desc,
1001 &s->rdmaciq[rdmaciqqidx].rspq);
1002 if (err)
1003 goto unwind;
1004 msi_index++;
1005 }
b8ff05a9
DM		 1006 return 0;
1007
1008unwind:
cf38be6d
HS		 1009 while (--rdmaciqqidx >= 0)
1010 free_irq(adap->msix_info[--msi_index].vec,
1011 &s->rdmaciq[rdmaciqqidx].rspq);
b8ff05a9 1012 while (--rdmaqidx >= 0)
404d9e3f 1013 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 1014 &s->rdmarxq[rdmaqidx].rspq);
1015 while (--ofldqidx >= 0)
404d9e3f 1016 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM		 1017 &s->ofldrxq[ofldqidx].rspq);
1018 while (--ethqidx >= 0)
404d9e3f
VP		 1019 free_irq(adap->msix_info[--msi_index].vec,
1020 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 1021 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1022 return err;
1023}
1024
1025static void free_msix_queue_irqs(struct adapter *adap)
1026{
404d9e3f 1027 int i, msi_index = 2;
b8ff05a9
DM		 1028 struct sge *s = &adap->sge;
1029
1030 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1031 for_each_ethrxq(s, i)
404d9e3f 1032 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9 1033 for_each_ofldrxq(s, i)
404d9e3f 1034 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
b8ff05a9 1035 for_each_rdmarxq(s, i)
404d9e3f 1036 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
cf38be6d
HS		 1037 for_each_rdmaciq(s, i)
1038 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
b8ff05a9
DM		 1039}
1040
671b0060
DM		 1041/**
1042 * write_rss - write the RSS table for a given port
1043 * @pi: the port
1044 * @queues: array of queue indices for RSS
1045 *
1046 * Sets up the portion of the HW RSS table for the port's VI to distribute
1047 * packets to the Rx queues in @queues.
1048 */
1049static int write_rss(const struct port_info *pi, const u16 *queues)
1050{
1051 u16 *rss;
1052 int i, err;
1053 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
1054
1055 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
1056 if (!rss)
1057 return -ENOMEM;
1058
1059 /* map the queue indices to queue ids */
1060 for (i = 0; i < pi->rss_size; i++, queues++)
1061 rss[i] = q[*queues].rspq.abs_id;
1062
060e0c75
DM		 1063 err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
1064 pi->rss_size, rss, pi->rss_size);
671b0060
DM		 1065 kfree(rss);
1066 return err;
1067}
1068
b8ff05a9
DM		 1069/**
1070 * setup_rss - configure RSS
1071 * @adap: the adapter
1072 *
671b0060 1073 * Sets up RSS for each port.
b8ff05a9
DM		 1074 */
1075static int setup_rss(struct adapter *adap)
1076{
671b0060 1077 int i, err;
b8ff05a9
DM		 1078
1079 for_each_port(adap, i) {
1080 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 1081
671b0060 1082 err = write_rss(pi, pi->rss);
b8ff05a9
DM		 1083 if (err)
1084 return err;
1085 }
1086 return 0;
1087}
1088
e46dab4d
DM		 1089/*
1090 * Return the channel of the ingress queue with the given qid.
1091 */
1092static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1093{
1094 qid -= p->ingr_start;
1095 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1096}
1097
b8ff05a9
DM		 1098/*
1099 * Wait until all NAPI handlers are descheduled.
1100 */
1101static void quiesce_rx(struct adapter *adap)
1102{
1103 int i;
1104
1105 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1106 struct sge_rspq *q = adap->sge.ingr_map[i];
1107
1108 if (q && q->handler)
1109 napi_disable(&q->napi);
1110 }
1111}
1112
1113/*
1114 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1115 */
1116static void enable_rx(struct adapter *adap)
1117{
1118 int i;
1119
1120 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1121 struct sge_rspq *q = adap->sge.ingr_map[i];
1122
1123 if (!q)
1124 continue;
1125 if (q->handler)
1126 napi_enable(&q->napi);
1127 /* 0-increment GTS to start the timer and enable interrupts */
1128 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1129 SEINTARM(q->intr_params) |
1130 INGRESSQID(q->cntxt_id));
1131 }
1132}
1133
1134/**
1135 * setup_sge_queues - configure SGE Tx/Rx/response queues
1136 * @adap: the adapter
1137 *
1138 * Determines how many sets of SGE queues to use and initializes them.
1139 * We support multiple queue sets per port if we have MSI-X, otherwise
1140 * just one queue set per port.
1141 */
1142static int setup_sge_queues(struct adapter *adap)
1143{
1144 int err, msi_idx, i, j;
1145 struct sge *s = &adap->sge;
1146
1147 bitmap_zero(s->starving_fl, MAX_EGRQ);
1148 bitmap_zero(s->txq_maperr, MAX_EGRQ);
1149
1150 if (adap->flags & USING_MSIX)
1151 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1152 else {
1153 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1154 NULL, NULL);
1155 if (err)
1156 return err;
1157 msi_idx = -((int)s->intrq.abs_id + 1);
1158 }
1159
1160 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1161 msi_idx, NULL, fwevtq_handler);
1162 if (err) {
1163freeout: t4_free_sge_resources(adap);
1164 return err;
1165 }
1166
1167 for_each_port(adap, i) {
1168 struct net_device *dev = adap->port[i];
1169 struct port_info *pi = netdev_priv(dev);
1170 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1171 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1172
1173 for (j = 0; j < pi->nqsets; j++, q++) {
1174 if (msi_idx > 0)
1175 msi_idx++;
1176 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1177 msi_idx, &q->fl,
1178 t4_ethrx_handler);
1179 if (err)
1180 goto freeout;
1181 q->rspq.idx = j;
1182 memset(&q->stats, 0, sizeof(q->stats));
1183 }
1184 for (j = 0; j < pi->nqsets; j++, t++) {
1185 err = t4_sge_alloc_eth_txq(adap, t, dev,
1186 netdev_get_tx_queue(dev, j),
1187 s->fw_evtq.cntxt_id);
1188 if (err)
1189 goto freeout;
1190 }
1191 }
1192
1193 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1194 for_each_ofldrxq(s, i) {
1195 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1196 struct net_device *dev = adap->port[i / j];
1197
1198 if (msi_idx > 0)
1199 msi_idx++;
1200 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
cf38be6d
HS		 1201 q->fl.size ? &q->fl : NULL,
1202 uldrx_handler);
b8ff05a9
DM		 1203 if (err)
1204 goto freeout;
1205 memset(&q->stats, 0, sizeof(q->stats));
1206 s->ofld_rxq[i] = q->rspq.abs_id;
1207 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1208 s->fw_evtq.cntxt_id);
1209 if (err)
1210 goto freeout;
1211 }
1212
1213 for_each_rdmarxq(s, i) {
1214 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1215
1216 if (msi_idx > 0)
1217 msi_idx++;
1218 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
cf38be6d
HS		 1219 msi_idx, q->fl.size ? &q->fl : NULL,
1220 uldrx_handler);
b8ff05a9
DM		 1221 if (err)
1222 goto freeout;
1223 memset(&q->stats, 0, sizeof(q->stats));
1224 s->rdma_rxq[i] = q->rspq.abs_id;
1225 }
1226
cf38be6d
HS		 1227 for_each_rdmaciq(s, i) {
1228 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1229
1230 if (msi_idx > 0)
1231 msi_idx++;
1232 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1233 msi_idx, q->fl.size ? &q->fl : NULL,
1234 uldrx_handler);
1235 if (err)
1236 goto freeout;
1237 memset(&q->stats, 0, sizeof(q->stats));
1238 s->rdma_ciq[i] = q->rspq.abs_id;
1239 }
1240
b8ff05a9
DM		 1241 for_each_port(adap, i) {
1242 /*
1243 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1244 * have RDMA queues, and that's the right value.
1245 */
1246 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1247 s->fw_evtq.cntxt_id,
1248 s->rdmarxq[i].rspq.cntxt_id);
1249 if (err)
1250 goto freeout;
1251 }
1252
1253 t4_write_reg(adap, MPS_TRC_RSS_CONTROL,
1254 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1255 QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1256 return 0;
1257}
1258
b8ff05a9
DM		 1259/*
1260 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1261 * The allocated memory is cleared.
1262 */
1263void *t4_alloc_mem(size_t size)
1264{
8be04b93 1265 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
b8ff05a9
DM		 1266
1267 if (!p)
89bf67f1 1268 p = vzalloc(size);
b8ff05a9
DM		 1269 return p;
1270}
1271
1272/*
1273 * Free memory allocated through alloc_mem().
1274 */
31b9c19b 1275static void t4_free_mem(void *addr)
b8ff05a9
DM		 1276{
1277 if (is_vmalloc_addr(addr))
1278 vfree(addr);
1279 else
1280 kfree(addr);
1281}
1282
f2b7e78d
VP		 1283/* Send a Work Request to write the filter at a specified index. We construct
1284 * a Firmware Filter Work Request to have the work done and put the indicated
1285 * filter into "pending" mode which will prevent any further actions against
1286 * it till we get a reply from the firmware on the completion status of the
1287 * request.
1288 */
1289static int set_filter_wr(struct adapter *adapter, int fidx)
1290{
1291 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1292 struct sk_buff *skb;
1293 struct fw_filter_wr *fwr;
1294 unsigned int ftid;
1295
1296 /* If the new filter requires loopback Destination MAC and/or VLAN
1297 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1298 * the filter.
1299 */
1300 if (f->fs.newdmac || f->fs.newvlan) {
1301 /* allocate L2T entry for new filter */
1302 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1303 if (f->l2t == NULL)
1304 return -EAGAIN;
1305 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1306 f->fs.eport, f->fs.dmac)) {
1307 cxgb4_l2t_release(f->l2t);
1308 f->l2t = NULL;
1309 return -ENOMEM;
1310 }
1311 }
1312
1313 ftid = adapter->tids.ftid_base + fidx;
1314
1315 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1316 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1317 memset(fwr, 0, sizeof(*fwr));
1318
1319 /* It would be nice to put most of the following in t4_hw.c but most
1320 * of the work is translating the cxgbtool ch_filter_specification
1321 * into the Work Request and the definition of that structure is
1322 * currently in cxgbtool.h which isn't appropriate to pull into the
1323 * common code. We may eventually try to come up with a more neutral
1324 * filter specification structure but for now it's easiest to simply
1325 * put this fairly direct code in line ...
1326 */
1327 fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1328 fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1329 fwr->tid_to_iq =
1330 htonl(V_FW_FILTER_WR_TID(ftid) |
1331 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1332 V_FW_FILTER_WR_NOREPLY(0) |
1333 V_FW_FILTER_WR_IQ(f->fs.iq));
1334 fwr->del_filter_to_l2tix =
1335 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1336 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1337 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1338 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1339 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1340 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1341 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1342 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1343 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1344 f->fs.newvlan == VLAN_REWRITE) |
1345 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1346 f->fs.newvlan == VLAN_REWRITE) |
1347 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1348 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1349 V_FW_FILTER_WR_PRIO(f->fs.prio) |
1350 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1351 fwr->ethtype = htons(f->fs.val.ethtype);
1352 fwr->ethtypem = htons(f->fs.mask.ethtype);
1353 fwr->frag_to_ovlan_vldm =
1354 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1355 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1356 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1357 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1358 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1359 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1360 fwr->smac_sel = 0;
1361 fwr->rx_chan_rx_rpl_iq =
1362 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1363 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1364 fwr->maci_to_matchtypem =
1365 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1366 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1367 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1368 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1369 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1370 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1371 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1372 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1373 fwr->ptcl = f->fs.val.proto;
1374 fwr->ptclm = f->fs.mask.proto;
1375 fwr->ttyp = f->fs.val.tos;
1376 fwr->ttypm = f->fs.mask.tos;
1377 fwr->ivlan = htons(f->fs.val.ivlan);
1378 fwr->ivlanm = htons(f->fs.mask.ivlan);
1379 fwr->ovlan = htons(f->fs.val.ovlan);
1380 fwr->ovlanm = htons(f->fs.mask.ovlan);
1381 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1382 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1383 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1384 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1385 fwr->lp = htons(f->fs.val.lport);
1386 fwr->lpm = htons(f->fs.mask.lport);
1387 fwr->fp = htons(f->fs.val.fport);
1388 fwr->fpm = htons(f->fs.mask.fport);
1389 if (f->fs.newsmac)
1390 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1391
1392 /* Mark the filter as "pending" and ship off the Filter Work Request.
1393 * When we get the Work Request Reply we'll clear the pending status.
1394 */
1395 f->pending = 1;
1396 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1397 t4_ofld_send(adapter, skb);
1398 return 0;
1399}
1400
1401/* Delete the filter at a specified index.
1402 */
1403static int del_filter_wr(struct adapter *adapter, int fidx)
1404{
1405 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1406 struct sk_buff *skb;
1407 struct fw_filter_wr *fwr;
1408 unsigned int len, ftid;
1409
1410 len = sizeof(*fwr);
1411 ftid = adapter->tids.ftid_base + fidx;
1412
1413 skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1414 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1415 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1416
1417 /* Mark the filter as "pending" and ship off the Filter Work Request.
1418 * When we get the Work Request Reply we'll clear the pending status.
1419 */
1420 f->pending = 1;
1421 t4_mgmt_tx(adapter, skb);
1422 return 0;
1423}
1424
688848b1
AB		 1425static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1426 void *accel_priv, select_queue_fallback_t fallback)
1427{
1428 int txq;
1429
1430#ifdef CONFIG_CHELSIO_T4_DCB
1431 /* If a Data Center Bridging has been successfully negotiated on this
1432 * link then we'll use the skb's priority to map it to a TX Queue.
1433 * The skb's priority is determined via the VLAN Tag Priority Code
1434 * Point field.
1435 */
1436 if (cxgb4_dcb_enabled(dev)) {
1437 u16 vlan_tci;
1438 int err;
1439
1440 err = vlan_get_tag(skb, &vlan_tci);
1441 if (unlikely(err)) {
1442 if (net_ratelimit())
1443 netdev_warn(dev,
1444 "TX Packet without VLAN Tag on DCB Link\n");
1445 txq = 0;
1446 } else {
1447 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1448 }
1449 return txq;
1450 }
1451#endif /* CONFIG_CHELSIO_T4_DCB */
1452
1453 if (select_queue) {
1454 txq = (skb_rx_queue_recorded(skb)
1455 ? skb_get_rx_queue(skb)
1456 : smp_processor_id());
1457
1458 while (unlikely(txq >= dev->real_num_tx_queues))
1459 txq -= dev->real_num_tx_queues;
1460
1461 return txq;
1462 }
1463
1464 return fallback(dev, skb) % dev->real_num_tx_queues;
1465}
1466
b8ff05a9
DM		 1467static inline int is_offload(const struct adapter *adap)
1468{
1469 return adap->params.offload;
1470}
1471
1472/*
1473 * Implementation of ethtool operations.
1474 */
1475
1476static u32 get_msglevel(struct net_device *dev)
1477{
1478 return netdev2adap(dev)->msg_enable;
1479}
1480
1481static void set_msglevel(struct net_device *dev, u32 val)
1482{
1483 netdev2adap(dev)->msg_enable = val;
1484}
1485
1486static char stats_strings[][ETH_GSTRING_LEN] = {
1487 "TxOctetsOK ",
1488 "TxFramesOK ",
1489 "TxBroadcastFrames ",
1490 "TxMulticastFrames ",
1491 "TxUnicastFrames ",
1492 "TxErrorFrames ",
1493
1494 "TxFrames64 ",
1495 "TxFrames65To127 ",
1496 "TxFrames128To255 ",
1497 "TxFrames256To511 ",
1498 "TxFrames512To1023 ",
1499 "TxFrames1024To1518 ",
1500 "TxFrames1519ToMax ",
1501
1502 "TxFramesDropped ",
1503 "TxPauseFrames ",
1504 "TxPPP0Frames ",
1505 "TxPPP1Frames ",
1506 "TxPPP2Frames ",
1507 "TxPPP3Frames ",
1508 "TxPPP4Frames ",
1509 "TxPPP5Frames ",
1510 "TxPPP6Frames ",
1511 "TxPPP7Frames ",
1512
1513 "RxOctetsOK ",
1514 "RxFramesOK ",
1515 "RxBroadcastFrames ",
1516 "RxMulticastFrames ",
1517 "RxUnicastFrames ",
1518
1519 "RxFramesTooLong ",
1520 "RxJabberErrors ",
1521 "RxFCSErrors ",
1522 "RxLengthErrors ",
1523 "RxSymbolErrors ",
1524 "RxRuntFrames ",
1525
1526 "RxFrames64 ",
1527 "RxFrames65To127 ",
1528 "RxFrames128To255 ",
1529 "RxFrames256To511 ",
1530 "RxFrames512To1023 ",
1531 "RxFrames1024To1518 ",
1532 "RxFrames1519ToMax ",
1533
1534 "RxPauseFrames ",
1535 "RxPPP0Frames ",
1536 "RxPPP1Frames ",
1537 "RxPPP2Frames ",
1538 "RxPPP3Frames ",
1539 "RxPPP4Frames ",
1540 "RxPPP5Frames ",
1541 "RxPPP6Frames ",
1542 "RxPPP7Frames ",
1543
1544 "RxBG0FramesDropped ",
1545 "RxBG1FramesDropped ",
1546 "RxBG2FramesDropped ",
1547 "RxBG3FramesDropped ",
1548 "RxBG0FramesTrunc ",
1549 "RxBG1FramesTrunc ",
1550 "RxBG2FramesTrunc ",
1551 "RxBG3FramesTrunc ",
1552
1553 "TSO ",
1554 "TxCsumOffload ",
1555 "RxCsumGood ",
1556 "VLANextractions ",
1557 "VLANinsertions ",
4a6346d4
DM		 1558 "GROpackets ",
1559 "GROmerged ",
22adfe0a
SR		 1560 "WriteCoalSuccess ",
1561 "WriteCoalFail ",
b8ff05a9
DM		 1562};
1563
1564static int get_sset_count(struct net_device *dev, int sset)
1565{
1566 switch (sset) {
1567 case ETH_SS_STATS:
1568 return ARRAY_SIZE(stats_strings);
1569 default:
1570 return -EOPNOTSUPP;
1571 }
1572}
1573
1574#define T4_REGMAP_SIZE (160 * 1024)
251f9e88 1575#define T5_REGMAP_SIZE (332 * 1024)
b8ff05a9
DM		 1576
1577static int get_regs_len(struct net_device *dev)
1578{
251f9e88 1579 struct adapter *adap = netdev2adap(dev);
d14807dd 1580 if (is_t4(adap->params.chip))
251f9e88
SR		 1581 return T4_REGMAP_SIZE;
1582 else
1583 return T5_REGMAP_SIZE;
b8ff05a9
DM		 1584}
1585
1586static int get_eeprom_len(struct net_device *dev)
1587{
1588 return EEPROMSIZE;
1589}
1590
1591static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1592{
1593 struct adapter *adapter = netdev2adap(dev);
1594
23020ab3
RJ		 1595 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1596 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1597 strlcpy(info->bus_info, pci_name(adapter->pdev),
1598 sizeof(info->bus_info));
b8ff05a9 1599
84b40501 1600 if (adapter->params.fw_vers)
b8ff05a9
DM		 1601 snprintf(info->fw_version, sizeof(info->fw_version),
1602 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1603 FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1604 FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1605 FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1606 FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1607 FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1608 FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1609 FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1610 FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1611}
1612
1613static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1614{
1615 if (stringset == ETH_SS_STATS)
1616 memcpy(data, stats_strings, sizeof(stats_strings));
1617}
1618
1619/*
1620 * port stats maintained per queue of the port. They should be in the same
1621 * order as in stats_strings above.
1622 */
1623struct queue_port_stats {
1624 u64 tso;
1625 u64 tx_csum;
1626 u64 rx_csum;
1627 u64 vlan_ex;
1628 u64 vlan_ins;
4a6346d4
DM		 1629 u64 gro_pkts;
1630 u64 gro_merged;
b8ff05a9
DM		 1631};
1632
1633static void collect_sge_port_stats(const struct adapter *adap,
1634 const struct port_info *p, struct queue_port_stats *s)
1635{
1636 int i;
1637 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1638 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1639
1640 memset(s, 0, sizeof(*s));
1641 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1642 s->tso += tx->tso;
1643 s->tx_csum += tx->tx_cso;
1644 s->rx_csum += rx->stats.rx_cso;
1645 s->vlan_ex += rx->stats.vlan_ex;
1646 s->vlan_ins += tx->vlan_ins;
4a6346d4
DM		 1647 s->gro_pkts += rx->stats.lro_pkts;
1648 s->gro_merged += rx->stats.lro_merged;
b8ff05a9
DM		 1649 }
1650}
1651
1652static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1653 u64 *data)
1654{
1655 struct port_info *pi = netdev_priv(dev);
1656 struct adapter *adapter = pi->adapter;
22adfe0a 1657 u32 val1, val2;
b8ff05a9
DM		 1658
1659 t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1660
1661 data += sizeof(struct port_stats) / sizeof(u64);
1662 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
22adfe0a 1663 data += sizeof(struct queue_port_stats) / sizeof(u64);
d14807dd 1664 if (!is_t4(adapter->params.chip)) {
22adfe0a
SR		 1665 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1666 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1667 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1668 *data = val1 - val2;
1669 data++;
1670 *data = val2;
1671 data++;
1672 } else {
1673 memset(data, 0, 2 * sizeof(u64));
1674 *data += 2;
1675 }
b8ff05a9
DM		 1676}
1677
1678/*
1679 * Return a version number to identify the type of adapter. The scheme is:
1680 * - bits 0..9: chip version
1681 * - bits 10..15: chip revision
835bb606 1682 * - bits 16..23: register dump version
b8ff05a9
DM		 1683 */
1684static inline unsigned int mk_adap_vers(const struct adapter *ap)
1685{
d14807dd
HS		 1686 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1687 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
b8ff05a9
DM		 1688}
1689
1690static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1691 unsigned int end)
1692{
1693 u32 *p = buf + start;
1694
1695 for ( ; start <= end; start += sizeof(u32))
1696 *p++ = t4_read_reg(ap, start);
1697}
1698
1699static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1700 void *buf)
1701{
251f9e88 1702 static const unsigned int t4_reg_ranges[] = {
b8ff05a9
DM		 1703 0x1008, 0x1108,
1704 0x1180, 0x11b4,
1705 0x11fc, 0x123c,
1706 0x1300, 0x173c,
1707 0x1800, 0x18fc,
1708 0x3000, 0x30d8,
1709 0x30e0, 0x5924,
1710 0x5960, 0x59d4,
1711 0x5a00, 0x5af8,
1712 0x6000, 0x6098,
1713 0x6100, 0x6150,
1714 0x6200, 0x6208,
1715 0x6240, 0x6248,
1716 0x6280, 0x6338,
1717 0x6370, 0x638c,
1718 0x6400, 0x643c,
1719 0x6500, 0x6524,
1720 0x6a00, 0x6a38,
1721 0x6a60, 0x6a78,
1722 0x6b00, 0x6b84,
1723 0x6bf0, 0x6c84,
1724 0x6cf0, 0x6d84,
1725 0x6df0, 0x6e84,
1726 0x6ef0, 0x6f84,
1727 0x6ff0, 0x7084,
1728 0x70f0, 0x7184,
1729 0x71f0, 0x7284,
1730 0x72f0, 0x7384,
1731 0x73f0, 0x7450,
1732 0x7500, 0x7530,
1733 0x7600, 0x761c,
1734 0x7680, 0x76cc,
1735 0x7700, 0x7798,
1736 0x77c0, 0x77fc,
1737 0x7900, 0x79fc,
1738 0x7b00, 0x7c38,
1739 0x7d00, 0x7efc,
1740 0x8dc0, 0x8e1c,
1741 0x8e30, 0x8e78,
1742 0x8ea0, 0x8f6c,
1743 0x8fc0, 0x9074,
1744 0x90fc, 0x90fc,
1745 0x9400, 0x9458,
1746 0x9600, 0x96bc,
1747 0x9800, 0x9808,
1748 0x9820, 0x983c,
1749 0x9850, 0x9864,
1750 0x9c00, 0x9c6c,
1751 0x9c80, 0x9cec,
1752 0x9d00, 0x9d6c,
1753 0x9d80, 0x9dec,
1754 0x9e00, 0x9e6c,
1755 0x9e80, 0x9eec,
1756 0x9f00, 0x9f6c,
1757 0x9f80, 0x9fec,
1758 0xd004, 0xd03c,
1759 0xdfc0, 0xdfe0,
1760 0xe000, 0xea7c,
1761 0xf000, 0x11190,
835bb606
DM		 1762 0x19040, 0x1906c,
1763 0x19078, 0x19080,
1764 0x1908c, 0x19124,
b8ff05a9
DM		 1765 0x19150, 0x191b0,
1766 0x191d0, 0x191e8,
1767 0x19238, 0x1924c,
1768 0x193f8, 0x19474,
1769 0x19490, 0x194f8,
1770 0x19800, 0x19f30,
1771 0x1a000, 0x1a06c,
1772 0x1a0b0, 0x1a120,
1773 0x1a128, 0x1a138,
1774 0x1a190, 0x1a1c4,
1775 0x1a1fc, 0x1a1fc,
1776 0x1e040, 0x1e04c,
835bb606 1777 0x1e284, 0x1e28c,
b8ff05a9
DM		 1778 0x1e2c0, 0x1e2c0,
1779 0x1e2e0, 0x1e2e0,
1780 0x1e300, 0x1e384,
1781 0x1e3c0, 0x1e3c8,
1782 0x1e440, 0x1e44c,
835bb606 1783 0x1e684, 0x1e68c,
b8ff05a9
DM		 1784 0x1e6c0, 0x1e6c0,
1785 0x1e6e0, 0x1e6e0,
1786 0x1e700, 0x1e784,
1787 0x1e7c0, 0x1e7c8,
1788 0x1e840, 0x1e84c,
835bb606 1789 0x1ea84, 0x1ea8c,
b8ff05a9
DM		 1790 0x1eac0, 0x1eac0,
1791 0x1eae0, 0x1eae0,
1792 0x1eb00, 0x1eb84,
1793 0x1ebc0, 0x1ebc8,
1794 0x1ec40, 0x1ec4c,
835bb606 1795 0x1ee84, 0x1ee8c,
b8ff05a9
DM		 1796 0x1eec0, 0x1eec0,
1797 0x1eee0, 0x1eee0,
1798 0x1ef00, 0x1ef84,
1799 0x1efc0, 0x1efc8,
1800 0x1f040, 0x1f04c,
835bb606 1801 0x1f284, 0x1f28c,
b8ff05a9
DM		 1802 0x1f2c0, 0x1f2c0,
1803 0x1f2e0, 0x1f2e0,
1804 0x1f300, 0x1f384,
1805 0x1f3c0, 0x1f3c8,
1806 0x1f440, 0x1f44c,
835bb606 1807 0x1f684, 0x1f68c,
b8ff05a9
DM		 1808 0x1f6c0, 0x1f6c0,
1809 0x1f6e0, 0x1f6e0,
1810 0x1f700, 0x1f784,
1811 0x1f7c0, 0x1f7c8,
1812 0x1f840, 0x1f84c,
835bb606 1813 0x1fa84, 0x1fa8c,
b8ff05a9
DM		 1814 0x1fac0, 0x1fac0,
1815 0x1fae0, 0x1fae0,
1816 0x1fb00, 0x1fb84,
1817 0x1fbc0, 0x1fbc8,
1818 0x1fc40, 0x1fc4c,
835bb606 1819 0x1fe84, 0x1fe8c,
b8ff05a9
DM		 1820 0x1fec0, 0x1fec0,
1821 0x1fee0, 0x1fee0,
1822 0x1ff00, 0x1ff84,
1823 0x1ffc0, 0x1ffc8,
1824 0x20000, 0x2002c,
1825 0x20100, 0x2013c,
1826 0x20190, 0x201c8,
1827 0x20200, 0x20318,
1828 0x20400, 0x20528,
1829 0x20540, 0x20614,
1830 0x21000, 0x21040,
1831 0x2104c, 0x21060,
1832 0x210c0, 0x210ec,
1833 0x21200, 0x21268,
1834 0x21270, 0x21284,
1835 0x212fc, 0x21388,
1836 0x21400, 0x21404,
1837 0x21500, 0x21518,
1838 0x2152c, 0x2153c,
1839 0x21550, 0x21554,
1840 0x21600, 0x21600,
1841 0x21608, 0x21628,
1842 0x21630, 0x2163c,
1843 0x21700, 0x2171c,
1844 0x21780, 0x2178c,
1845 0x21800, 0x21c38,
1846 0x21c80, 0x21d7c,
1847 0x21e00, 0x21e04,
1848 0x22000, 0x2202c,
1849 0x22100, 0x2213c,
1850 0x22190, 0x221c8,
1851 0x22200, 0x22318,
1852 0x22400, 0x22528,
1853 0x22540, 0x22614,
1854 0x23000, 0x23040,
1855 0x2304c, 0x23060,
1856 0x230c0, 0x230ec,
1857 0x23200, 0x23268,
1858 0x23270, 0x23284,
1859 0x232fc, 0x23388,
1860 0x23400, 0x23404,
1861 0x23500, 0x23518,
1862 0x2352c, 0x2353c,
1863 0x23550, 0x23554,
1864 0x23600, 0x23600,
1865 0x23608, 0x23628,
1866 0x23630, 0x2363c,
1867 0x23700, 0x2371c,
1868 0x23780, 0x2378c,
1869 0x23800, 0x23c38,
1870 0x23c80, 0x23d7c,
1871 0x23e00, 0x23e04,
1872 0x24000, 0x2402c,
1873 0x24100, 0x2413c,
1874 0x24190, 0x241c8,
1875 0x24200, 0x24318,
1876 0x24400, 0x24528,
1877 0x24540, 0x24614,
1878 0x25000, 0x25040,
1879 0x2504c, 0x25060,
1880 0x250c0, 0x250ec,
1881 0x25200, 0x25268,
1882 0x25270, 0x25284,
1883 0x252fc, 0x25388,
1884 0x25400, 0x25404,
1885 0x25500, 0x25518,
1886 0x2552c, 0x2553c,
1887 0x25550, 0x25554,
1888 0x25600, 0x25600,
1889 0x25608, 0x25628,
1890 0x25630, 0x2563c,
1891 0x25700, 0x2571c,
1892 0x25780, 0x2578c,
1893 0x25800, 0x25c38,
1894 0x25c80, 0x25d7c,
1895 0x25e00, 0x25e04,
1896 0x26000, 0x2602c,
1897 0x26100, 0x2613c,
1898 0x26190, 0x261c8,
1899 0x26200, 0x26318,
1900 0x26400, 0x26528,
1901 0x26540, 0x26614,
1902 0x27000, 0x27040,
1903 0x2704c, 0x27060,
1904 0x270c0, 0x270ec,
1905 0x27200, 0x27268,
1906 0x27270, 0x27284,
1907 0x272fc, 0x27388,
1908 0x27400, 0x27404,
1909 0x27500, 0x27518,
1910 0x2752c, 0x2753c,
1911 0x27550, 0x27554,
1912 0x27600, 0x27600,
1913 0x27608, 0x27628,
1914 0x27630, 0x2763c,
1915 0x27700, 0x2771c,
1916 0x27780, 0x2778c,
1917 0x27800, 0x27c38,
1918 0x27c80, 0x27d7c,
1919 0x27e00, 0x27e04
1920 };
1921
251f9e88
SR		 1922 static const unsigned int t5_reg_ranges[] = {
1923 0x1008, 0x1148,
1924 0x1180, 0x11b4,
1925 0x11fc, 0x123c,
1926 0x1280, 0x173c,
1927 0x1800, 0x18fc,
1928 0x3000, 0x3028,
1929 0x3060, 0x30d8,
1930 0x30e0, 0x30fc,
1931 0x3140, 0x357c,
1932 0x35a8, 0x35cc,
1933 0x35ec, 0x35ec,
1934 0x3600, 0x5624,
1935 0x56cc, 0x575c,
1936 0x580c, 0x5814,
1937 0x5890, 0x58bc,
1938 0x5940, 0x59dc,
1939 0x59fc, 0x5a18,
1940 0x5a60, 0x5a9c,
1941 0x5b9c, 0x5bfc,
1942 0x6000, 0x6040,
1943 0x6058, 0x614c,
1944 0x7700, 0x7798,
1945 0x77c0, 0x78fc,
1946 0x7b00, 0x7c54,
1947 0x7d00, 0x7efc,
1948 0x8dc0, 0x8de0,
1949 0x8df8, 0x8e84,
1950 0x8ea0, 0x8f84,
1951 0x8fc0, 0x90f8,
1952 0x9400, 0x9470,
1953 0x9600, 0x96f4,
1954 0x9800, 0x9808,
1955 0x9820, 0x983c,
1956 0x9850, 0x9864,
1957 0x9c00, 0x9c6c,
1958 0x9c80, 0x9cec,
1959 0x9d00, 0x9d6c,
1960 0x9d80, 0x9dec,
1961 0x9e00, 0x9e6c,
1962 0x9e80, 0x9eec,
1963 0x9f00, 0x9f6c,
1964 0x9f80, 0xa020,
1965 0xd004, 0xd03c,
1966 0xdfc0, 0xdfe0,
1967 0xe000, 0x11088,
1968 0x1109c, 0x1117c,
1969 0x11190, 0x11204,
1970 0x19040, 0x1906c,
1971 0x19078, 0x19080,
1972 0x1908c, 0x19124,
1973 0x19150, 0x191b0,
1974 0x191d0, 0x191e8,
1975 0x19238, 0x19290,
1976 0x193f8, 0x19474,
1977 0x19490, 0x194cc,
1978 0x194f0, 0x194f8,
1979 0x19c00, 0x19c60,
1980 0x19c94, 0x19e10,
1981 0x19e50, 0x19f34,
1982 0x19f40, 0x19f50,
1983 0x19f90, 0x19fe4,
1984 0x1a000, 0x1a06c,
1985 0x1a0b0, 0x1a120,
1986 0x1a128, 0x1a138,
1987 0x1a190, 0x1a1c4,
1988 0x1a1fc, 0x1a1fc,
1989 0x1e008, 0x1e00c,
1990 0x1e040, 0x1e04c,
1991 0x1e284, 0x1e290,
1992 0x1e2c0, 0x1e2c0,
1993 0x1e2e0, 0x1e2e0,
1994 0x1e300, 0x1e384,
1995 0x1e3c0, 0x1e3c8,
1996 0x1e408, 0x1e40c,
1997 0x1e440, 0x1e44c,
1998 0x1e684, 0x1e690,
1999 0x1e6c0, 0x1e6c0,
2000 0x1e6e0, 0x1e6e0,
2001 0x1e700, 0x1e784,
2002 0x1e7c0, 0x1e7c8,
2003 0x1e808, 0x1e80c,
2004 0x1e840, 0x1e84c,
2005 0x1ea84, 0x1ea90,
2006 0x1eac0, 0x1eac0,
2007 0x1eae0, 0x1eae0,
2008 0x1eb00, 0x1eb84,
2009 0x1ebc0, 0x1ebc8,
2010 0x1ec08, 0x1ec0c,
2011 0x1ec40, 0x1ec4c,
2012 0x1ee84, 0x1ee90,
2013 0x1eec0, 0x1eec0,
2014 0x1eee0, 0x1eee0,
2015 0x1ef00, 0x1ef84,
2016 0x1efc0, 0x1efc8,
2017 0x1f008, 0x1f00c,
2018 0x1f040, 0x1f04c,
2019 0x1f284, 0x1f290,
2020 0x1f2c0, 0x1f2c0,
2021 0x1f2e0, 0x1f2e0,
2022 0x1f300, 0x1f384,
2023 0x1f3c0, 0x1f3c8,
2024 0x1f408, 0x1f40c,
2025 0x1f440, 0x1f44c,
2026 0x1f684, 0x1f690,
2027 0x1f6c0, 0x1f6c0,
2028 0x1f6e0, 0x1f6e0,
2029 0x1f700, 0x1f784,
2030 0x1f7c0, 0x1f7c8,
2031 0x1f808, 0x1f80c,
2032 0x1f840, 0x1f84c,
2033 0x1fa84, 0x1fa90,
2034 0x1fac0, 0x1fac0,
2035 0x1fae0, 0x1fae0,
2036 0x1fb00, 0x1fb84,
2037 0x1fbc0, 0x1fbc8,
2038 0x1fc08, 0x1fc0c,
2039 0x1fc40, 0x1fc4c,
2040 0x1fe84, 0x1fe90,
2041 0x1fec0, 0x1fec0,
2042 0x1fee0, 0x1fee0,
2043 0x1ff00, 0x1ff84,
2044 0x1ffc0, 0x1ffc8,
2045 0x30000, 0x30030,
2046 0x30100, 0x30144,
2047 0x30190, 0x301d0,
2048 0x30200, 0x30318,
2049 0x30400, 0x3052c,
2050 0x30540, 0x3061c,
2051 0x30800, 0x30834,
2052 0x308c0, 0x30908,
2053 0x30910, 0x309ac,
2054 0x30a00, 0x30a04,
2055 0x30a0c, 0x30a2c,
2056 0x30a44, 0x30a50,
2057 0x30a74, 0x30c24,
2058 0x30d08, 0x30d14,
2059 0x30d1c, 0x30d20,
2060 0x30d3c, 0x30d50,
2061 0x31200, 0x3120c,
2062 0x31220, 0x31220,
2063 0x31240, 0x31240,
2064 0x31600, 0x31600,
2065 0x31608, 0x3160c,
2066 0x31a00, 0x31a1c,
2067 0x31e04, 0x31e20,
2068 0x31e38, 0x31e3c,
2069 0x31e80, 0x31e80,
2070 0x31e88, 0x31ea8,
2071 0x31eb0, 0x31eb4,
2072 0x31ec8, 0x31ed4,
2073 0x31fb8, 0x32004,
2074 0x32208, 0x3223c,
2075 0x32600, 0x32630,
2076 0x32a00, 0x32abc,
2077 0x32b00, 0x32b70,
2078 0x33000, 0x33048,
2079 0x33060, 0x3309c,
2080 0x330f0, 0x33148,
2081 0x33160, 0x3319c,
2082 0x331f0, 0x332e4,
2083 0x332f8, 0x333e4,
2084 0x333f8, 0x33448,
2085 0x33460, 0x3349c,
2086 0x334f0, 0x33548,
2087 0x33560, 0x3359c,
2088 0x335f0, 0x336e4,
2089 0x336f8, 0x337e4,
2090 0x337f8, 0x337fc,
2091 0x33814, 0x33814,
2092 0x3382c, 0x3382c,
2093 0x33880, 0x3388c,
2094 0x338e8, 0x338ec,
2095 0x33900, 0x33948,
2096 0x33960, 0x3399c,
2097 0x339f0, 0x33ae4,
2098 0x33af8, 0x33b10,
2099 0x33b28, 0x33b28,
2100 0x33b3c, 0x33b50,
2101 0x33bf0, 0x33c10,
2102 0x33c28, 0x33c28,
2103 0x33c3c, 0x33c50,
2104 0x33cf0, 0x33cfc,
2105 0x34000, 0x34030,
2106 0x34100, 0x34144,
2107 0x34190, 0x341d0,
2108 0x34200, 0x34318,
2109 0x34400, 0x3452c,
2110 0x34540, 0x3461c,
2111 0x34800, 0x34834,
2112 0x348c0, 0x34908,
2113 0x34910, 0x349ac,
2114 0x34a00, 0x34a04,
2115 0x34a0c, 0x34a2c,
2116 0x34a44, 0x34a50,
2117 0x34a74, 0x34c24,
2118 0x34d08, 0x34d14,
2119 0x34d1c, 0x34d20,
2120 0x34d3c, 0x34d50,
2121 0x35200, 0x3520c,
2122 0x35220, 0x35220,
2123 0x35240, 0x35240,
2124 0x35600, 0x35600,
2125 0x35608, 0x3560c,
2126 0x35a00, 0x35a1c,
2127 0x35e04, 0x35e20,
2128 0x35e38, 0x35e3c,
2129 0x35e80, 0x35e80,
2130 0x35e88, 0x35ea8,
2131 0x35eb0, 0x35eb4,
2132 0x35ec8, 0x35ed4,
2133 0x35fb8, 0x36004,
2134 0x36208, 0x3623c,
2135 0x36600, 0x36630,
2136 0x36a00, 0x36abc,
2137 0x36b00, 0x36b70,
2138 0x37000, 0x37048,
2139 0x37060, 0x3709c,
2140 0x370f0, 0x37148,
2141 0x37160, 0x3719c,
2142 0x371f0, 0x372e4,
2143 0x372f8, 0x373e4,
2144 0x373f8, 0x37448,
2145 0x37460, 0x3749c,
2146 0x374f0, 0x37548,
2147 0x37560, 0x3759c,
2148 0x375f0, 0x376e4,
2149 0x376f8, 0x377e4,
2150 0x377f8, 0x377fc,
2151 0x37814, 0x37814,
2152 0x3782c, 0x3782c,
2153 0x37880, 0x3788c,
2154 0x378e8, 0x378ec,
2155 0x37900, 0x37948,
2156 0x37960, 0x3799c,
2157 0x379f0, 0x37ae4,
2158 0x37af8, 0x37b10,
2159 0x37b28, 0x37b28,
2160 0x37b3c, 0x37b50,
2161 0x37bf0, 0x37c10,
2162 0x37c28, 0x37c28,
2163 0x37c3c, 0x37c50,
2164 0x37cf0, 0x37cfc,
2165 0x38000, 0x38030,
2166 0x38100, 0x38144,
2167 0x38190, 0x381d0,
2168 0x38200, 0x38318,
2169 0x38400, 0x3852c,
2170 0x38540, 0x3861c,
2171 0x38800, 0x38834,
2172 0x388c0, 0x38908,
2173 0x38910, 0x389ac,
2174 0x38a00, 0x38a04,
2175 0x38a0c, 0x38a2c,
2176 0x38a44, 0x38a50,
2177 0x38a74, 0x38c24,
2178 0x38d08, 0x38d14,
2179 0x38d1c, 0x38d20,
2180 0x38d3c, 0x38d50,
2181 0x39200, 0x3920c,
2182 0x39220, 0x39220,
2183 0x39240, 0x39240,
2184 0x39600, 0x39600,
2185 0x39608, 0x3960c,
2186 0x39a00, 0x39a1c,
2187 0x39e04, 0x39e20,
2188 0x39e38, 0x39e3c,
2189 0x39e80, 0x39e80,
2190 0x39e88, 0x39ea8,
2191 0x39eb0, 0x39eb4,
2192 0x39ec8, 0x39ed4,
2193 0x39fb8, 0x3a004,
2194 0x3a208, 0x3a23c,
2195 0x3a600, 0x3a630,
2196 0x3aa00, 0x3aabc,
2197 0x3ab00, 0x3ab70,
2198 0x3b000, 0x3b048,
2199 0x3b060, 0x3b09c,
2200 0x3b0f0, 0x3b148,
2201 0x3b160, 0x3b19c,
2202 0x3b1f0, 0x3b2e4,
2203 0x3b2f8, 0x3b3e4,
2204 0x3b3f8, 0x3b448,
2205 0x3b460, 0x3b49c,
2206 0x3b4f0, 0x3b548,
2207 0x3b560, 0x3b59c,
2208 0x3b5f0, 0x3b6e4,
2209 0x3b6f8, 0x3b7e4,
2210 0x3b7f8, 0x3b7fc,
2211 0x3b814, 0x3b814,
2212 0x3b82c, 0x3b82c,
2213 0x3b880, 0x3b88c,
2214 0x3b8e8, 0x3b8ec,
2215 0x3b900, 0x3b948,
2216 0x3b960, 0x3b99c,
2217 0x3b9f0, 0x3bae4,
2218 0x3baf8, 0x3bb10,
2219 0x3bb28, 0x3bb28,
2220 0x3bb3c, 0x3bb50,
2221 0x3bbf0, 0x3bc10,
2222 0x3bc28, 0x3bc28,
2223 0x3bc3c, 0x3bc50,
2224 0x3bcf0, 0x3bcfc,
2225 0x3c000, 0x3c030,
2226 0x3c100, 0x3c144,
2227 0x3c190, 0x3c1d0,
2228 0x3c200, 0x3c318,
2229 0x3c400, 0x3c52c,
2230 0x3c540, 0x3c61c,
2231 0x3c800, 0x3c834,
2232 0x3c8c0, 0x3c908,
2233 0x3c910, 0x3c9ac,
2234 0x3ca00, 0x3ca04,
2235 0x3ca0c, 0x3ca2c,
2236 0x3ca44, 0x3ca50,
2237 0x3ca74, 0x3cc24,
2238 0x3cd08, 0x3cd14,
2239 0x3cd1c, 0x3cd20,
2240 0x3cd3c, 0x3cd50,
2241 0x3d200, 0x3d20c,
2242 0x3d220, 0x3d220,
2243 0x3d240, 0x3d240,
2244 0x3d600, 0x3d600,
2245 0x3d608, 0x3d60c,
2246 0x3da00, 0x3da1c,
2247 0x3de04, 0x3de20,
2248 0x3de38, 0x3de3c,
2249 0x3de80, 0x3de80,
2250 0x3de88, 0x3dea8,
2251 0x3deb0, 0x3deb4,
2252 0x3dec8, 0x3ded4,
2253 0x3dfb8, 0x3e004,
2254 0x3e208, 0x3e23c,
2255 0x3e600, 0x3e630,
2256 0x3ea00, 0x3eabc,
2257 0x3eb00, 0x3eb70,
2258 0x3f000, 0x3f048,
2259 0x3f060, 0x3f09c,
2260 0x3f0f0, 0x3f148,
2261 0x3f160, 0x3f19c,
2262 0x3f1f0, 0x3f2e4,
2263 0x3f2f8, 0x3f3e4,
2264 0x3f3f8, 0x3f448,
2265 0x3f460, 0x3f49c,
2266 0x3f4f0, 0x3f548,
2267 0x3f560, 0x3f59c,
2268 0x3f5f0, 0x3f6e4,
2269 0x3f6f8, 0x3f7e4,
2270 0x3f7f8, 0x3f7fc,
2271 0x3f814, 0x3f814,
2272 0x3f82c, 0x3f82c,
2273 0x3f880, 0x3f88c,
2274 0x3f8e8, 0x3f8ec,
2275 0x3f900, 0x3f948,
2276 0x3f960, 0x3f99c,
2277 0x3f9f0, 0x3fae4,
2278 0x3faf8, 0x3fb10,
2279 0x3fb28, 0x3fb28,
2280 0x3fb3c, 0x3fb50,
2281 0x3fbf0, 0x3fc10,
2282 0x3fc28, 0x3fc28,
2283 0x3fc3c, 0x3fc50,
2284 0x3fcf0, 0x3fcfc,
2285 0x40000, 0x4000c,
2286 0x40040, 0x40068,
2287 0x40080, 0x40144,
2288 0x40180, 0x4018c,
2289 0x40200, 0x40298,
2290 0x402ac, 0x4033c,
2291 0x403f8, 0x403fc,
c1f49e3e 2292 0x41304, 0x413c4,
251f9e88
SR		 2293 0x41400, 0x4141c,
2294 0x41480, 0x414d0,
2295 0x44000, 0x44078,
2296 0x440c0, 0x44278,
2297 0x442c0, 0x44478,
2298 0x444c0, 0x44678,
2299 0x446c0, 0x44878,
2300 0x448c0, 0x449fc,
2301 0x45000, 0x45068,
2302 0x45080, 0x45084,
2303 0x450a0, 0x450b0,
2304 0x45200, 0x45268,
2305 0x45280, 0x45284,
2306 0x452a0, 0x452b0,
2307 0x460c0, 0x460e4,
2308 0x47000, 0x4708c,
2309 0x47200, 0x47250,
2310 0x47400, 0x47420,
2311 0x47600, 0x47618,
2312 0x47800, 0x47814,
2313 0x48000, 0x4800c,
2314 0x48040, 0x48068,
2315 0x48080, 0x48144,
2316 0x48180, 0x4818c,
2317 0x48200, 0x48298,
2318 0x482ac, 0x4833c,
2319 0x483f8, 0x483fc,
c1f49e3e 2320 0x49304, 0x493c4,
251f9e88
SR		 2321 0x49400, 0x4941c,
2322 0x49480, 0x494d0,
2323 0x4c000, 0x4c078,
2324 0x4c0c0, 0x4c278,
2325 0x4c2c0, 0x4c478,
2326 0x4c4c0, 0x4c678,
2327 0x4c6c0, 0x4c878,
2328 0x4c8c0, 0x4c9fc,
2329 0x4d000, 0x4d068,
2330 0x4d080, 0x4d084,
2331 0x4d0a0, 0x4d0b0,
2332 0x4d200, 0x4d268,
2333 0x4d280, 0x4d284,
2334 0x4d2a0, 0x4d2b0,
2335 0x4e0c0, 0x4e0e4,
2336 0x4f000, 0x4f08c,
2337 0x4f200, 0x4f250,
2338 0x4f400, 0x4f420,
2339 0x4f600, 0x4f618,
2340 0x4f800, 0x4f814,
2341 0x50000, 0x500cc,
2342 0x50400, 0x50400,
2343 0x50800, 0x508cc,
2344 0x50c00, 0x50c00,
2345 0x51000, 0x5101c,
2346 0x51300, 0x51308,
2347 };
2348
b8ff05a9
DM		 2349 int i;
2350 struct adapter *ap = netdev2adap(dev);
251f9e88
SR		 2351 static const unsigned int *reg_ranges;
2352 int arr_size = 0, buf_size = 0;
2353
d14807dd 2354 if (is_t4(ap->params.chip)) {
251f9e88
SR		 2355 reg_ranges = &t4_reg_ranges[0];
2356 arr_size = ARRAY_SIZE(t4_reg_ranges);
2357 buf_size = T4_REGMAP_SIZE;
2358 } else {
2359 reg_ranges = &t5_reg_ranges[0];
2360 arr_size = ARRAY_SIZE(t5_reg_ranges);
2361 buf_size = T5_REGMAP_SIZE;
2362 }
b8ff05a9
DM		 2363
2364 regs->version = mk_adap_vers(ap);
2365
251f9e88
SR		 2366 memset(buf, 0, buf_size);
2367 for (i = 0; i < arr_size; i += 2)
b8ff05a9
DM		 2368 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2369}
2370
2371static int restart_autoneg(struct net_device *dev)
2372{
2373 struct port_info *p = netdev_priv(dev);
2374
2375 if (!netif_running(dev))
2376 return -EAGAIN;
2377 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2378 return -EINVAL;
060e0c75 2379 t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
b8ff05a9
DM		 2380 return 0;
2381}
2382
c5e06360
DM		 2383static int identify_port(struct net_device *dev,
2384 enum ethtool_phys_id_state state)
b8ff05a9 2385{
c5e06360 2386 unsigned int val;
060e0c75
DM		 2387 struct adapter *adap = netdev2adap(dev);
2388
c5e06360
DM		 2389 if (state == ETHTOOL_ID_ACTIVE)
2390 val = 0xffff;
2391 else if (state == ETHTOOL_ID_INACTIVE)
2392 val = 0;
2393 else
2394 return -EINVAL;
b8ff05a9 2395
c5e06360 2396 return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
b8ff05a9
DM		 2397}
2398
2399static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2400{
2401 unsigned int v = 0;
2402
a0881cab
DM		 2403 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2404 type == FW_PORT_TYPE_BT_XAUI) {
b8ff05a9
DM		 2405 v |= SUPPORTED_TP;
2406 if (caps & FW_PORT_CAP_SPEED_100M)
2407 v |= SUPPORTED_100baseT_Full;
2408 if (caps & FW_PORT_CAP_SPEED_1G)
2409 v |= SUPPORTED_1000baseT_Full;
2410 if (caps & FW_PORT_CAP_SPEED_10G)
2411 v |= SUPPORTED_10000baseT_Full;
2412 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2413 v |= SUPPORTED_Backplane;
2414 if (caps & FW_PORT_CAP_SPEED_1G)
2415 v |= SUPPORTED_1000baseKX_Full;
2416 if (caps & FW_PORT_CAP_SPEED_10G)
2417 v |= SUPPORTED_10000baseKX4_Full;
2418 } else if (type == FW_PORT_TYPE_KR)
2419 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
a0881cab 2420 else if (type == FW_PORT_TYPE_BP_AP)
7d5e77aa
DM		 2421 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2422 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2423 else if (type == FW_PORT_TYPE_BP4_AP)
2424 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2425 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2426 SUPPORTED_10000baseKX4_Full;
a0881cab
DM		 2427 else if (type == FW_PORT_TYPE_FIBER_XFI ||
2428 type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
b8ff05a9 2429 v |= SUPPORTED_FIBRE;
72aca4bf
KS		 2430 else if (type == FW_PORT_TYPE_BP40_BA)
2431 v |= SUPPORTED_40000baseSR4_Full;
b8ff05a9
DM		 2432
2433 if (caps & FW_PORT_CAP_ANEG)
2434 v |= SUPPORTED_Autoneg;
2435 return v;
2436}
2437
2438static unsigned int to_fw_linkcaps(unsigned int caps)
2439{
2440 unsigned int v = 0;
2441
2442 if (caps & ADVERTISED_100baseT_Full)
2443 v |= FW_PORT_CAP_SPEED_100M;
2444 if (caps & ADVERTISED_1000baseT_Full)
2445 v |= FW_PORT_CAP_SPEED_1G;
2446 if (caps & ADVERTISED_10000baseT_Full)
2447 v |= FW_PORT_CAP_SPEED_10G;
72aca4bf
KS		 2448 if (caps & ADVERTISED_40000baseSR4_Full)
2449 v |= FW_PORT_CAP_SPEED_40G;
b8ff05a9
DM		 2450 return v;
2451}
2452
2453static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2454{
2455 const struct port_info *p = netdev_priv(dev);
2456
2457 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
a0881cab 2458 p->port_type == FW_PORT_TYPE_BT_XFI ||
b8ff05a9
DM		 2459 p->port_type == FW_PORT_TYPE_BT_XAUI)
2460 cmd->port = PORT_TP;
a0881cab
DM		 2461 else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2462 p->port_type == FW_PORT_TYPE_FIBER_XAUI)
b8ff05a9 2463 cmd->port = PORT_FIBRE;
3e00a509
HS		 2464 else if (p->port_type == FW_PORT_TYPE_SFP ||
2465 p->port_type == FW_PORT_TYPE_QSFP_10G ||
2466 p->port_type == FW_PORT_TYPE_QSFP) {
2467 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2468 p->mod_type == FW_PORT_MOD_TYPE_SR ||
2469 p->mod_type == FW_PORT_MOD_TYPE_ER ||
2470 p->mod_type == FW_PORT_MOD_TYPE_LRM)
2471 cmd->port = PORT_FIBRE;
2472 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2473 p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
a0881cab
DM		 2474 cmd->port = PORT_DA;
2475 else
3e00a509 2476 cmd->port = PORT_OTHER;
a0881cab 2477 } else
b8ff05a9
DM		 2478 cmd->port = PORT_OTHER;
2479
2480 if (p->mdio_addr >= 0) {
2481 cmd->phy_address = p->mdio_addr;
2482 cmd->transceiver = XCVR_EXTERNAL;
2483 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2484 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2485 } else {
2486 cmd->phy_address = 0; /* not really, but no better option */
2487 cmd->transceiver = XCVR_INTERNAL;
2488 cmd->mdio_support = 0;
2489 }
2490
2491 cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2492 cmd->advertising = from_fw_linkcaps(p->port_type,
2493 p->link_cfg.advertising);
70739497
DD		 2494 ethtool_cmd_speed_set(cmd,
2495 netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
b8ff05a9
DM		 2496 cmd->duplex = DUPLEX_FULL;
2497 cmd->autoneg = p->link_cfg.autoneg;
2498 cmd->maxtxpkt = 0;
2499 cmd->maxrxpkt = 0;
2500 return 0;
2501}
2502
2503static unsigned int speed_to_caps(int speed)
2504{
e8b39015 2505 if (speed == 100)
b8ff05a9 2506 return FW_PORT_CAP_SPEED_100M;
e8b39015 2507 if (speed == 1000)
b8ff05a9 2508 return FW_PORT_CAP_SPEED_1G;
e8b39015 2509 if (speed == 10000)
b8ff05a9 2510 return FW_PORT_CAP_SPEED_10G;
e8b39015 2511 if (speed == 40000)
72aca4bf 2512 return FW_PORT_CAP_SPEED_40G;
b8ff05a9
DM		 2513 return 0;
2514}
2515
2516static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2517{
2518 unsigned int cap;
2519 struct port_info *p = netdev_priv(dev);
2520 struct link_config *lc = &p->link_cfg;
25db0338 2521 u32 speed = ethtool_cmd_speed(cmd);
b8ff05a9
DM		 2522
2523 if (cmd->duplex != DUPLEX_FULL) /* only full-duplex supported */
2524 return -EINVAL;
2525
2526 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2527 /*
2528 * PHY offers a single speed. See if that's what's
2529 * being requested.
2530 */
2531 if (cmd->autoneg == AUTONEG_DISABLE &&
25db0338
DD		 2532 (lc->supported & speed_to_caps(speed)))
2533 return 0;
b8ff05a9
DM		 2534 return -EINVAL;
2535 }
2536
2537 if (cmd->autoneg == AUTONEG_DISABLE) {
25db0338 2538 cap = speed_to_caps(speed);
b8ff05a9 2539
72aca4bf 2540 if (!(lc->supported & cap) ||
e8b39015
BH		 2541 (speed == 1000) ||
2542 (speed == 10000) ||
72aca4bf 2543 (speed == 40000))
b8ff05a9
DM		 2544 return -EINVAL;
2545 lc->requested_speed = cap;
2546 lc->advertising = 0;
2547 } else {
2548 cap = to_fw_linkcaps(cmd->advertising);
2549 if (!(lc->supported & cap))
2550 return -EINVAL;
2551 lc->requested_speed = 0;
2552 lc->advertising = cap | FW_PORT_CAP_ANEG;
2553 }
2554 lc->autoneg = cmd->autoneg;
2555
2556 if (netif_running(dev))
060e0c75
DM		 2557 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2558 lc);
b8ff05a9
DM		 2559 return 0;
2560}
2561
2562static void get_pauseparam(struct net_device *dev,
2563 struct ethtool_pauseparam *epause)
2564{
2565 struct port_info *p = netdev_priv(dev);
2566
2567 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2568 epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2569 epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2570}
2571
2572static int set_pauseparam(struct net_device *dev,
2573 struct ethtool_pauseparam *epause)
2574{
2575 struct port_info *p = netdev_priv(dev);
2576 struct link_config *lc = &p->link_cfg;
2577
2578 if (epause->autoneg == AUTONEG_DISABLE)
2579 lc->requested_fc = 0;
2580 else if (lc->supported & FW_PORT_CAP_ANEG)
2581 lc->requested_fc = PAUSE_AUTONEG;
2582 else
2583 return -EINVAL;
2584
2585 if (epause->rx_pause)
2586 lc->requested_fc |= PAUSE_RX;
2587 if (epause->tx_pause)
2588 lc->requested_fc |= PAUSE_TX;
2589 if (netif_running(dev))
060e0c75
DM		 2590 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2591 lc);
b8ff05a9
DM		 2592 return 0;
2593}
2594
b8ff05a9
DM		 2595static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2596{
2597 const struct port_info *pi = netdev_priv(dev);
2598 const struct sge *s = &pi->adapter->sge;
2599
2600 e->rx_max_pending = MAX_RX_BUFFERS;
2601 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2602 e->rx_jumbo_max_pending = 0;
2603 e->tx_max_pending = MAX_TXQ_ENTRIES;
2604
2605 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2606 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2607 e->rx_jumbo_pending = 0;
2608 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2609}
2610
2611static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2612{
2613 int i;
2614 const struct port_info *pi = netdev_priv(dev);
2615 struct adapter *adapter = pi->adapter;
2616 struct sge *s = &adapter->sge;
2617
2618 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2619 e->tx_pending > MAX_TXQ_ENTRIES ||
2620 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2621 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2622 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2623 return -EINVAL;
2624
2625 if (adapter->flags & FULL_INIT_DONE)
2626 return -EBUSY;
2627
2628 for (i = 0; i < pi->nqsets; ++i) {
2629 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2630 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2631 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2632 }
2633 return 0;
2634}
2635
2636static int closest_timer(const struct sge *s, int time)
2637{
2638 int i, delta, match = 0, min_delta = INT_MAX;
2639
2640 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2641 delta = time - s->timer_val[i];
2642 if (delta < 0)
2643 delta = -delta;
2644 if (delta < min_delta) {
2645 min_delta = delta;
2646 match = i;
2647 }
2648 }
2649 return match;
2650}
2651
2652static int closest_thres(const struct sge *s, int thres)
2653{
2654 int i, delta, match = 0, min_delta = INT_MAX;
2655
2656 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2657 delta = thres - s->counter_val[i];
2658 if (delta < 0)
2659 delta = -delta;
2660 if (delta < min_delta) {
2661 min_delta = delta;
2662 match = i;
2663 }
2664 }
2665 return match;
2666}
2667
2668/*
2669 * Return a queue's interrupt hold-off time in us. 0 means no timer.
2670 */
2671static unsigned int qtimer_val(const struct adapter *adap,
2672 const struct sge_rspq *q)
2673{
2674 unsigned int idx = q->intr_params >> 1;
2675
2676 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2677}
2678
2679/**
c887ad0e 2680 * set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 2681 * @q: the Rx queue
2682 * @us: the hold-off time in us, or 0 to disable timer
2683 * @cnt: the hold-off packet count, or 0 to disable counter
2684 *
2685 * Sets an Rx queue's interrupt hold-off time and packet count. At least
2686 * one of the two needs to be enabled for the queue to generate interrupts.
2687 */
c887ad0e
HS		 2688static int set_rspq_intr_params(struct sge_rspq *q,
2689 unsigned int us, unsigned int cnt)
b8ff05a9 2690{
c887ad0e
HS		 2691 struct adapter *adap = q->adap;
2692
b8ff05a9
DM		 2693 if ((us | cnt) == 0)
2694 cnt = 1;
2695
2696 if (cnt) {
2697 int err;
2698 u32 v, new_idx;
2699
2700 new_idx = closest_thres(&adap->sge, cnt);
2701 if (q->desc && q->pktcnt_idx != new_idx) {
2702 /* the queue has already been created, update it */
2703 v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2704 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2705 FW_PARAMS_PARAM_YZ(q->cntxt_id);
060e0c75
DM		 2706 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2707 &new_idx);
b8ff05a9
DM		 2708 if (err)
2709 return err;
2710 }
2711 q->pktcnt_idx = new_idx;
2712 }
2713
2714 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2715 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2716 return 0;
2717}
2718
c887ad0e
HS		 2719/**
2720 * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2721 * @dev: the network device
2722 * @us: the hold-off time in us, or 0 to disable timer
2723 * @cnt: the hold-off packet count, or 0 to disable counter
2724 *
2725 * Set the RX interrupt hold-off parameters for a network device.
2726 */
2727static int set_rx_intr_params(struct net_device *dev,
2728 unsigned int us, unsigned int cnt)
b8ff05a9 2729{
c887ad0e
HS		 2730 int i, err;
2731 struct port_info *pi = netdev_priv(dev);
b8ff05a9 2732 struct adapter *adap = pi->adapter;
c887ad0e
HS		 2733 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2734
2735 for (i = 0; i < pi->nqsets; i++, q++) {
2736 err = set_rspq_intr_params(&q->rspq, us, cnt);
2737 if (err)
2738 return err;
d4fc9dc2 2739 }
c887ad0e
HS		 2740 return 0;
2741}
2742
2743static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2744{
2745 return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2746 c->rx_max_coalesced_frames);
b8ff05a9
DM		 2747}
2748
2749static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2750{
2751 const struct port_info *pi = netdev_priv(dev);
2752 const struct adapter *adap = pi->adapter;
2753 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2754
2755 c->rx_coalesce_usecs = qtimer_val(adap, rq);
2756 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2757 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2758 return 0;
2759}
2760
1478b3ee
DM		 2761/**
2762 * eeprom_ptov - translate a physical EEPROM address to virtual
2763 * @phys_addr: the physical EEPROM address
2764 * @fn: the PCI function number
2765 * @sz: size of function-specific area
2766 *
2767 * Translate a physical EEPROM address to virtual. The first 1K is
2768 * accessed through virtual addresses starting at 31K, the rest is
2769 * accessed through virtual addresses starting at 0.
2770 *
2771 * The mapping is as follows:
2772 * [0..1K) -> [31K..32K)
2773 * [1K..1K+A) -> [31K-A..31K)
2774 * [1K+A..ES) -> [0..ES-A-1K)
2775 *
2776 * where A = @fn * @sz, and ES = EEPROM size.
b8ff05a9 2777 */
1478b3ee 2778static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
b8ff05a9 2779{
1478b3ee 2780 fn *= sz;
b8ff05a9
DM		 2781 if (phys_addr < 1024)
2782 return phys_addr + (31 << 10);
1478b3ee
DM		 2783 if (phys_addr < 1024 + fn)
2784 return 31744 - fn + phys_addr - 1024;
b8ff05a9 2785 if (phys_addr < EEPROMSIZE)
1478b3ee 2786 return phys_addr - 1024 - fn;
b8ff05a9
DM		 2787 return -EINVAL;
2788}
2789
2790/*
2791 * The next two routines implement eeprom read/write from physical addresses.
b8ff05a9
DM		 2792 */
2793static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2794{
1478b3ee 2795 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
b8ff05a9
DM		 2796
2797 if (vaddr >= 0)
2798 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2799 return vaddr < 0 ? vaddr : 0;
2800}
2801
2802static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2803{
1478b3ee 2804 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
b8ff05a9
DM		 2805
2806 if (vaddr >= 0)
2807 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2808 return vaddr < 0 ? vaddr : 0;
2809}
2810
2811#define EEPROM_MAGIC 0x38E2F10C
2812
2813static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2814 u8 *data)
2815{
2816 int i, err = 0;
2817 struct adapter *adapter = netdev2adap(dev);
2818
2819 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2820 if (!buf)
2821 return -ENOMEM;
2822
2823 e->magic = EEPROM_MAGIC;
2824 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2825 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2826
2827 if (!err)
2828 memcpy(data, buf + e->offset, e->len);
2829 kfree(buf);
2830 return err;
2831}
2832
2833static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2834 u8 *data)
2835{
2836 u8 *buf;
2837 int err = 0;
2838 u32 aligned_offset, aligned_len, *p;
2839 struct adapter *adapter = netdev2adap(dev);
2840
2841 if (eeprom->magic != EEPROM_MAGIC)
2842 return -EINVAL;
2843
2844 aligned_offset = eeprom->offset & ~3;
2845 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2846
1478b3ee
DM		 2847 if (adapter->fn > 0) {
2848 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2849
2850 if (aligned_offset < start ||
2851 aligned_offset + aligned_len > start + EEPROMPFSIZE)
2852 return -EPERM;
2853 }
2854
b8ff05a9
DM		 2855 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2856 /*
2857 * RMW possibly needed for first or last words.
2858 */
2859 buf = kmalloc(aligned_len, GFP_KERNEL);
2860 if (!buf)
2861 return -ENOMEM;
2862 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2863 if (!err && aligned_len > 4)
2864 err = eeprom_rd_phys(adapter,
2865 aligned_offset + aligned_len - 4,
2866 (u32 *)&buf[aligned_len - 4]);
2867 if (err)
2868 goto out;
2869 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2870 } else
2871 buf = data;
2872
2873 err = t4_seeprom_wp(adapter, false);
2874 if (err)
2875 goto out;
2876
2877 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2878 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2879 aligned_offset += 4;
2880 }
2881
2882 if (!err)
2883 err = t4_seeprom_wp(adapter, true);
2884out:
2885 if (buf != data)
2886 kfree(buf);
2887 return err;
2888}
2889
2890static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2891{
2892 int ret;
2893 const struct firmware *fw;
2894 struct adapter *adap = netdev2adap(netdev);
2895
2896 ef->data[sizeof(ef->data) - 1] = '\0';
2897 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2898 if (ret < 0)
2899 return ret;
2900
2901 ret = t4_load_fw(adap, fw->data, fw->size);
2902 release_firmware(fw);
2903 if (!ret)
2904 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
2905 return ret;
2906}
2907
2908#define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2909#define BCAST_CRC 0xa0ccc1a6
2910
2911static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2912{
2913 wol->supported = WAKE_BCAST | WAKE_MAGIC;
2914 wol->wolopts = netdev2adap(dev)->wol;
2915 memset(&wol->sopass, 0, sizeof(wol->sopass));
2916}
2917
2918static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2919{
2920 int err = 0;
2921 struct port_info *pi = netdev_priv(dev);
2922
2923 if (wol->wolopts & ~WOL_SUPPORTED)
2924 return -EINVAL;
2925 t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2926 (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2927 if (wol->wolopts & WAKE_BCAST) {
2928 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2929 ~0ULL, 0, false);
2930 if (!err)
2931 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2932 ~6ULL, ~0ULL, BCAST_CRC, true);
2933 } else
2934 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2935 return err;
2936}
2937
c8f44aff 2938static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 2939{
2ed28baa 2940 const struct port_info *pi = netdev_priv(dev);
c8f44aff 2941 netdev_features_t changed = dev->features ^ features;
19ecae2c 2942 int err;
19ecae2c 2943
f646968f 2944 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 2945 return 0;
19ecae2c 2946
2ed28baa
MM		 2947 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2948 -1, -1, -1,
f646968f 2949 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 2950 if (unlikely(err))
f646968f 2951 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 2952 return err;
87b6cf51
DM		 2953}
2954
7850f63f 2955static u32 get_rss_table_size(struct net_device *dev)
671b0060
DM		 2956{
2957 const struct port_info *pi = netdev_priv(dev);
671b0060 2958
7850f63f
BH		 2959 return pi->rss_size;
2960}
2961
fe62d001 2962static int get_rss_table(struct net_device *dev, u32 *p, u8 *key)
7850f63f
BH		 2963{
2964 const struct port_info *pi = netdev_priv(dev);
2965 unsigned int n = pi->rss_size;
2966
671b0060 2967 while (n--)
7850f63f 2968 p[n] = pi->rss[n];
671b0060
DM		 2969 return 0;
2970}
2971
fe62d001 2972static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key)
671b0060
DM		 2973{
2974 unsigned int i;
2975 struct port_info *pi = netdev_priv(dev);
2976
7850f63f
BH		 2977 for (i = 0; i < pi->rss_size; i++)
2978 pi->rss[i] = p[i];
671b0060
DM		 2979 if (pi->adapter->flags & FULL_INIT_DONE)
2980 return write_rss(pi, pi->rss);
2981 return 0;
2982}
2983
2984static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2985 u32 *rules)
671b0060 2986{
f796564a
DM		 2987 const struct port_info *pi = netdev_priv(dev);
2988
671b0060 2989 switch (info->cmd) {
f796564a
DM		 2990 case ETHTOOL_GRXFH: {
2991 unsigned int v = pi->rss_mode;
2992
2993 info->data = 0;
2994 switch (info->flow_type) {
2995 case TCP_V4_FLOW:
2996 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2997 info->data = RXH_IP_SRC | RXH_IP_DST |
2998 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2999 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3000 info->data = RXH_IP_SRC | RXH_IP_DST;
3001 break;
3002 case UDP_V4_FLOW:
3003 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
3004 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3005 info->data = RXH_IP_SRC | RXH_IP_DST |
3006 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3007 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3008 info->data = RXH_IP_SRC | RXH_IP_DST;
3009 break;
3010 case SCTP_V4_FLOW:
3011 case AH_ESP_V4_FLOW:
3012 case IPV4_FLOW:
3013 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3014 info->data = RXH_IP_SRC | RXH_IP_DST;
3015 break;
3016 case TCP_V6_FLOW:
3017 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3018 info->data = RXH_IP_SRC | RXH_IP_DST |
3019 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3020 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3021 info->data = RXH_IP_SRC | RXH_IP_DST;
3022 break;
3023 case UDP_V6_FLOW:
3024 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
3025 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3026 info->data = RXH_IP_SRC | RXH_IP_DST |
3027 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3028 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3029 info->data = RXH_IP_SRC | RXH_IP_DST;
3030 break;
3031 case SCTP_V6_FLOW:
3032 case AH_ESP_V6_FLOW:
3033 case IPV6_FLOW:
3034 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3035 info->data = RXH_IP_SRC | RXH_IP_DST;
3036 break;
3037 }
3038 return 0;
3039 }
671b0060 3040 case ETHTOOL_GRXRINGS:
f796564a 3041 info->data = pi->nqsets;
671b0060
DM		 3042 return 0;
3043 }
3044 return -EOPNOTSUPP;
3045}
3046
9b07be4b 3047static const struct ethtool_ops cxgb_ethtool_ops = {
b8ff05a9
DM		 3048 .get_settings = get_settings,
3049 .set_settings = set_settings,
3050 .get_drvinfo = get_drvinfo,
3051 .get_msglevel = get_msglevel,
3052 .set_msglevel = set_msglevel,
3053 .get_ringparam = get_sge_param,
3054 .set_ringparam = set_sge_param,
3055 .get_coalesce = get_coalesce,
3056 .set_coalesce = set_coalesce,
3057 .get_eeprom_len = get_eeprom_len,
3058 .get_eeprom = get_eeprom,
3059 .set_eeprom = set_eeprom,
3060 .get_pauseparam = get_pauseparam,
3061 .set_pauseparam = set_pauseparam,
b8ff05a9
DM		 3062 .get_link = ethtool_op_get_link,
3063 .get_strings = get_strings,
c5e06360 3064 .set_phys_id = identify_port,
b8ff05a9
DM		 3065 .nway_reset = restart_autoneg,
3066 .get_sset_count = get_sset_count,
3067 .get_ethtool_stats = get_stats,
3068 .get_regs_len = get_regs_len,
3069 .get_regs = get_regs,
3070 .get_wol = get_wol,
3071 .set_wol = set_wol,
671b0060 3072 .get_rxnfc = get_rxnfc,
7850f63f 3073 .get_rxfh_indir_size = get_rss_table_size,
fe62d001
BH		 3074 .get_rxfh = get_rss_table,
3075 .set_rxfh = set_rss_table,
b8ff05a9
DM		 3076 .flash_device = set_flash,
3077};
3078
3079/*
3080 * debugfs support
3081 */
b8ff05a9
DM		 3082static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
3083 loff_t *ppos)
3084{
3085 loff_t pos = *ppos;
496ad9aa 3086 loff_t avail = file_inode(file)->i_size;
b8ff05a9
DM		 3087 unsigned int mem = (uintptr_t)file->private_data & 3;
3088 struct adapter *adap = file->private_data - mem;
fc5ab020
HS		 3089 __be32 *data;
3090 int ret;
b8ff05a9
DM		 3091
3092 if (pos < 0)
3093 return -EINVAL;
3094 if (pos >= avail)
3095 return 0;
3096 if (count > avail - pos)
3097 count = avail - pos;
3098
fc5ab020
HS		 3099 data = t4_alloc_mem(count);
3100 if (!data)
3101 return -ENOMEM;
b8ff05a9 3102
fc5ab020
HS		 3103 spin_lock(&adap->win0_lock);
3104 ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);
3105 spin_unlock(&adap->win0_lock);
3106 if (ret) {
3107 t4_free_mem(data);
3108 return ret;
3109 }
3110 ret = copy_to_user(buf, data, count);
b8ff05a9 3111
fc5ab020
HS		 3112 t4_free_mem(data);
3113 if (ret)
3114 return -EFAULT;
b8ff05a9 3115
fc5ab020 3116 *ppos = pos + count;
b8ff05a9
DM		 3117 return count;
3118}
3119
3120static const struct file_operations mem_debugfs_fops = {
3121 .owner = THIS_MODULE,
234e3405 3122 .open = simple_open,
b8ff05a9 3123 .read = mem_read,
6038f373 3124 .llseek = default_llseek,
b8ff05a9
DM		 3125};
3126
91744948 3127static void add_debugfs_mem(struct adapter *adap, const char *name,
1dd06ae8 3128 unsigned int idx, unsigned int size_mb)
b8ff05a9
DM		 3129{
3130 struct dentry *de;
3131
3132 de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
3133 (void *)adap + idx, &mem_debugfs_fops);
3134 if (de && de->d_inode)
3135 de->d_inode->i_size = size_mb << 20;
3136}
3137
91744948 3138static int setup_debugfs(struct adapter *adap)
b8ff05a9
DM		 3139{
3140 int i;
19dd37ba 3141 u32 size;
b8ff05a9
DM		 3142
3143 if (IS_ERR_OR_NULL(adap->debugfs_root))
3144 return -1;
3145
3146 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
19dd37ba
SR		 3147 if (i & EDRAM0_ENABLE) {
3148 size = t4_read_reg(adap, MA_EDRAM0_BAR);
3149 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM_SIZE_GET(size));
3150 }
3151 if (i & EDRAM1_ENABLE) {
3152 size = t4_read_reg(adap, MA_EDRAM1_BAR);
3153 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM_SIZE_GET(size));
3154 }
d14807dd 3155 if (is_t4(adap->params.chip)) {
19dd37ba
SR		 3156 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3157 if (i & EXT_MEM_ENABLE)
3158 add_debugfs_mem(adap, "mc", MEM_MC,
3159 EXT_MEM_SIZE_GET(size));
3160 } else {
3161 if (i & EXT_MEM_ENABLE) {
3162 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3163 add_debugfs_mem(adap, "mc0", MEM_MC0,
3164 EXT_MEM_SIZE_GET(size));
3165 }
3166 if (i & EXT_MEM1_ENABLE) {
3167 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR);
3168 add_debugfs_mem(adap, "mc1", MEM_MC1,
3169 EXT_MEM_SIZE_GET(size));
3170 }
3171 }
b8ff05a9
DM		 3172 if (adap->l2t)
3173 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
3174 &t4_l2t_fops);
3175 return 0;
3176}
3177
3178/*
3179 * upper-layer driver support
3180 */
3181
3182/*
3183 * Allocate an active-open TID and set it to the supplied value.
3184 */
3185int cxgb4_alloc_atid(struct tid_info *t, void *data)
3186{
3187 int atid = -1;
3188
3189 spin_lock_bh(&t->atid_lock);
3190 if (t->afree) {
3191 union aopen_entry *p = t->afree;
3192
f2b7e78d 3193 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 3194 t->afree = p->next;
3195 p->data = data;
3196 t->atids_in_use++;
3197 }
3198 spin_unlock_bh(&t->atid_lock);
3199 return atid;
3200}
3201EXPORT_SYMBOL(cxgb4_alloc_atid);
3202
3203/*
3204 * Release an active-open TID.
3205 */
3206void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3207{
f2b7e78d 3208 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 3209
3210 spin_lock_bh(&t->atid_lock);
3211 p->next = t->afree;
3212 t->afree = p;
3213 t->atids_in_use--;
3214 spin_unlock_bh(&t->atid_lock);
3215}
3216EXPORT_SYMBOL(cxgb4_free_atid);
3217
3218/*
3219 * Allocate a server TID and set it to the supplied value.
3220 */
3221int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3222{
3223 int stid;
3224
3225 spin_lock_bh(&t->stid_lock);
3226 if (family == PF_INET) {
3227 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3228 if (stid < t->nstids)
3229 __set_bit(stid, t->stid_bmap);
3230 else
3231 stid = -1;
3232 } else {
3233 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3234 if (stid < 0)
3235 stid = -1;
3236 }
3237 if (stid >= 0) {
3238 t->stid_tab[stid].data = data;
3239 stid += t->stid_base;
15f63b74
KS		 3240 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3241 * This is equivalent to 4 TIDs. With CLIP enabled it
3242 * needs 2 TIDs.
3243 */
3244 if (family == PF_INET)
3245 t->stids_in_use++;
3246 else
3247 t->stids_in_use += 4;
b8ff05a9
DM		 3248 }
3249 spin_unlock_bh(&t->stid_lock);
3250 return stid;
3251}
3252EXPORT_SYMBOL(cxgb4_alloc_stid);
3253
dca4faeb
VP		 3254/* Allocate a server filter TID and set it to the supplied value.
3255 */
3256int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3257{
3258 int stid;
3259
3260 spin_lock_bh(&t->stid_lock);
3261 if (family == PF_INET) {
3262 stid = find_next_zero_bit(t->stid_bmap,
3263 t->nstids + t->nsftids, t->nstids);
3264 if (stid < (t->nstids + t->nsftids))
3265 __set_bit(stid, t->stid_bmap);
3266 else
3267 stid = -1;
3268 } else {
3269 stid = -1;
3270 }
3271 if (stid >= 0) {
3272 t->stid_tab[stid].data = data;
470c60c4
KS		 3273 stid -= t->nstids;
3274 stid += t->sftid_base;
dca4faeb
VP		 3275 t->stids_in_use++;
3276 }
3277 spin_unlock_bh(&t->stid_lock);
3278 return stid;
3279}
3280EXPORT_SYMBOL(cxgb4_alloc_sftid);
3281
3282/* Release a server TID.
b8ff05a9
DM		 3283 */
3284void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3285{
470c60c4
KS		 3286 /* Is it a server filter TID? */
3287 if (t->nsftids && (stid >= t->sftid_base)) {
3288 stid -= t->sftid_base;
3289 stid += t->nstids;
3290 } else {
3291 stid -= t->stid_base;
3292 }
3293
b8ff05a9
DM		 3294 spin_lock_bh(&t->stid_lock);
3295 if (family == PF_INET)
3296 __clear_bit(stid, t->stid_bmap);
3297 else
3298 bitmap_release_region(t->stid_bmap, stid, 2);
3299 t->stid_tab[stid].data = NULL;
15f63b74
KS		 3300 if (family == PF_INET)
3301 t->stids_in_use--;
3302 else
3303 t->stids_in_use -= 4;
b8ff05a9
DM		 3304 spin_unlock_bh(&t->stid_lock);
3305}
3306EXPORT_SYMBOL(cxgb4_free_stid);
3307
3308/*
3309 * Populate a TID_RELEASE WR. Caller must properly size the skb.
3310 */
3311static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3312 unsigned int tid)
3313{
3314 struct cpl_tid_release *req;
3315
3316 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3317 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3318 INIT_TP_WR(req, tid);
3319 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3320}
3321
3322/*
3323 * Queue a TID release request and if necessary schedule a work queue to
3324 * process it.
3325 */
31b9c19b 3326static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3327 unsigned int tid)
b8ff05a9
DM		 3328{
3329 void **p = &t->tid_tab[tid];
3330 struct adapter *adap = container_of(t, struct adapter, tids);
3331
3332 spin_lock_bh(&adap->tid_release_lock);
3333 *p = adap->tid_release_head;
3334 /* Low 2 bits encode the Tx channel number */
3335 adap->tid_release_head = (void **)((uintptr_t)p | chan);
3336 if (!adap->tid_release_task_busy) {
3337 adap->tid_release_task_busy = true;
3069ee9b 3338 queue_work(workq, &adap->tid_release_task);
b8ff05a9
DM		 3339 }
3340 spin_unlock_bh(&adap->tid_release_lock);
3341}
b8ff05a9
DM		 3342
3343/*
3344 * Process the list of pending TID release requests.
3345 */
3346static void process_tid_release_list(struct work_struct *work)
3347{
3348 struct sk_buff *skb;
3349 struct adapter *adap;
3350
3351 adap = container_of(work, struct adapter, tid_release_task);
3352
3353 spin_lock_bh(&adap->tid_release_lock);
3354 while (adap->tid_release_head) {
3355 void **p = adap->tid_release_head;
3356 unsigned int chan = (uintptr_t)p & 3;
3357 p = (void *)p - chan;
3358
3359 adap->tid_release_head = *p;
3360 *p = NULL;
3361 spin_unlock_bh(&adap->tid_release_lock);
3362
3363 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3364 GFP_KERNEL)))
3365 schedule_timeout_uninterruptible(1);
3366
3367 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3368 t4_ofld_send(adap, skb);
3369 spin_lock_bh(&adap->tid_release_lock);
3370 }
3371 adap->tid_release_task_busy = false;
3372 spin_unlock_bh(&adap->tid_release_lock);
3373}
3374
3375/*
3376 * Release a TID and inform HW. If we are unable to allocate the release
3377 * message we defer to a work queue.
3378 */
3379void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3380{
3381 void *old;
3382 struct sk_buff *skb;
3383 struct adapter *adap = container_of(t, struct adapter, tids);
3384
3385 old = t->tid_tab[tid];
3386 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3387 if (likely(skb)) {
3388 t->tid_tab[tid] = NULL;
3389 mk_tid_release(skb, chan, tid);
3390 t4_ofld_send(adap, skb);
3391 } else
3392 cxgb4_queue_tid_release(t, chan, tid);
3393 if (old)
3394 atomic_dec(&t->tids_in_use);
3395}
3396EXPORT_SYMBOL(cxgb4_remove_tid);
3397
3398/*
3399 * Allocate and initialize the TID tables. Returns 0 on success.
3400 */
3401static int tid_init(struct tid_info *t)
3402{
3403 size_t size;
f2b7e78d 3404 unsigned int stid_bmap_size;
b8ff05a9 3405 unsigned int natids = t->natids;
b6f8eaec 3406 struct adapter *adap = container_of(t, struct adapter, tids);
b8ff05a9 3407
dca4faeb 3408 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
f2b7e78d
VP		 3409 size = t->ntids * sizeof(*t->tid_tab) +
3410 natids * sizeof(*t->atid_tab) +
b8ff05a9 3411 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 3412 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 3413 stid_bmap_size * sizeof(long) +
dca4faeb
VP		 3414 t->nftids * sizeof(*t->ftid_tab) +
3415 t->nsftids * sizeof(*t->ftid_tab);
f2b7e78d 3416
b8ff05a9
DM		 3417 t->tid_tab = t4_alloc_mem(size);
3418 if (!t->tid_tab)
3419 return -ENOMEM;
3420
3421 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3422 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 3423 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 3424 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
b8ff05a9
DM		 3425 spin_lock_init(&t->stid_lock);
3426 spin_lock_init(&t->atid_lock);
3427
3428 t->stids_in_use = 0;
3429 t->afree = NULL;
3430 t->atids_in_use = 0;
3431 atomic_set(&t->tids_in_use, 0);
3432
3433 /* Setup the free list for atid_tab and clear the stid bitmap. */
3434 if (natids) {
3435 while (--natids)
3436 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3437 t->afree = t->atid_tab;
3438 }
dca4faeb 3439 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
b6f8eaec
KS		 3440 /* Reserve stid 0 for T4/T5 adapters */
3441 if (!t->stid_base &&
3442 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3443 __set_bit(0, t->stid_bmap);
3444
b8ff05a9
DM		 3445 return 0;
3446}
3447
a3e3b285
AB		 3448int cxgb4_clip_get(const struct net_device *dev,
3449 const struct in6_addr *lip)
01bcca68
VP		 3450{
3451 struct adapter *adap;
3452 struct fw_clip_cmd c;
3453
3454 adap = netdev2adap(dev);
3455 memset(&c, 0, sizeof(c));
3456 c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3457 FW_CMD_REQUEST | FW_CMD_WRITE);
3458 c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_ALLOC | FW_LEN16(c));
12f2a479
JP		 3459 c.ip_hi = *(__be64 *)(lip->s6_addr);
3460 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
01bcca68
VP		 3461 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3462}
a3e3b285 3463EXPORT_SYMBOL(cxgb4_clip_get);
01bcca68 3464
a3e3b285
AB		 3465int cxgb4_clip_release(const struct net_device *dev,
3466 const struct in6_addr *lip)
01bcca68
VP		 3467{
3468 struct adapter *adap;
3469 struct fw_clip_cmd c;
3470
3471 adap = netdev2adap(dev);
3472 memset(&c, 0, sizeof(c));
3473 c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3474 FW_CMD_REQUEST | FW_CMD_READ);
3475 c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_FREE | FW_LEN16(c));
12f2a479
JP		 3476 c.ip_hi = *(__be64 *)(lip->s6_addr);
3477 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
01bcca68
VP		 3478 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3479}
a3e3b285 3480EXPORT_SYMBOL(cxgb4_clip_release);
01bcca68 3481
b8ff05a9
DM		 3482/**
3483 * cxgb4_create_server - create an IP server
3484 * @dev: the device
3485 * @stid: the server TID
3486 * @sip: local IP address to bind server to
3487 * @sport: the server's TCP port
3488 * @queue: queue to direct messages from this server to
3489 *
3490 * Create an IP server for the given port and address.
3491 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3492 */
3493int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 3494 __be32 sip, __be16 sport, __be16 vlan,
3495 unsigned int queue)
b8ff05a9
DM		 3496{
3497 unsigned int chan;
3498 struct sk_buff *skb;
3499 struct adapter *adap;
3500 struct cpl_pass_open_req *req;
80f40c1f 3501 int ret;
b8ff05a9
DM		 3502
3503 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3504 if (!skb)
3505 return -ENOMEM;
3506
3507 adap = netdev2adap(dev);
3508 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3509 INIT_TP_WR(req, 0);
3510 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3511 req->local_port = sport;
3512 req->peer_port = htons(0);
3513 req->local_ip = sip;
3514 req->peer_ip = htonl(0);
e46dab4d 3515 chan = rxq_to_chan(&adap->sge, queue);
b8ff05a9
DM		 3516 req->opt0 = cpu_to_be64(TX_CHAN(chan));
3517 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3518 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
80f40c1f
VP		 3519 ret = t4_mgmt_tx(adap, skb);
3520 return net_xmit_eval(ret);
b8ff05a9
DM		 3521}
3522EXPORT_SYMBOL(cxgb4_create_server);
3523
80f40c1f
VP		 3524/* cxgb4_create_server6 - create an IPv6 server
3525 * @dev: the device
3526 * @stid: the server TID
3527 * @sip: local IPv6 address to bind server to
3528 * @sport: the server's TCP port
3529 * @queue: queue to direct messages from this server to
3530 *
3531 * Create an IPv6 server for the given port and address.
3532 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3533 */
3534int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3535 const struct in6_addr *sip, __be16 sport,
3536 unsigned int queue)
3537{
3538 unsigned int chan;
3539 struct sk_buff *skb;
3540 struct adapter *adap;
3541 struct cpl_pass_open_req6 *req;
3542 int ret;
3543
3544 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3545 if (!skb)
3546 return -ENOMEM;
3547
3548 adap = netdev2adap(dev);
3549 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3550 INIT_TP_WR(req, 0);
3551 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3552 req->local_port = sport;
3553 req->peer_port = htons(0);
3554 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3555 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3556 req->peer_ip_hi = cpu_to_be64(0);
3557 req->peer_ip_lo = cpu_to_be64(0);
3558 chan = rxq_to_chan(&adap->sge, queue);
3559 req->opt0 = cpu_to_be64(TX_CHAN(chan));
3560 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3561 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3562 ret = t4_mgmt_tx(adap, skb);
3563 return net_xmit_eval(ret);
3564}
3565EXPORT_SYMBOL(cxgb4_create_server6);
3566
3567int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3568 unsigned int queue, bool ipv6)
3569{
3570 struct sk_buff *skb;
3571 struct adapter *adap;
3572 struct cpl_close_listsvr_req *req;
3573 int ret;
3574
3575 adap = netdev2adap(dev);
3576
3577 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3578 if (!skb)
3579 return -ENOMEM;
3580
3581 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3582 INIT_TP_WR(req, 0);
3583 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3584 req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3585 LISTSVR_IPV6(0)) | QUEUENO(queue));
3586 ret = t4_mgmt_tx(adap, skb);
3587 return net_xmit_eval(ret);
3588}
3589EXPORT_SYMBOL(cxgb4_remove_server);
3590
b8ff05a9
DM		 3591/**
3592 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3593 * @mtus: the HW MTU table
3594 * @mtu: the target MTU
3595 * @idx: index of selected entry in the MTU table
3596 *
3597 * Returns the index and the value in the HW MTU table that is closest to
3598 * but does not exceed @mtu, unless @mtu is smaller than any value in the
3599 * table, in which case that smallest available value is selected.
3600 */
3601unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3602 unsigned int *idx)
3603{
3604 unsigned int i = 0;
3605
3606 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3607 ++i;
3608 if (idx)
3609 *idx = i;
3610 return mtus[i];
3611}
3612EXPORT_SYMBOL(cxgb4_best_mtu);
3613
92e7ae71
HS		 3614/**
3615 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3616 * @mtus: the HW MTU table
3617 * @header_size: Header Size
3618 * @data_size_max: maximum Data Segment Size
3619 * @data_size_align: desired Data Segment Size Alignment (2^N)
3620 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3621 *
3622 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
3623 * MTU Table based solely on a Maximum MTU parameter, we break that
3624 * parameter up into a Header Size and Maximum Data Segment Size, and
3625 * provide a desired Data Segment Size Alignment. If we find an MTU in
3626 * the Hardware MTU Table which will result in a Data Segment Size with
3627 * the requested alignment _and_ that MTU isn't "too far" from the
3628 * closest MTU, then we'll return that rather than the closest MTU.
3629 */
3630unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3631 unsigned short header_size,
3632 unsigned short data_size_max,
3633 unsigned short data_size_align,
3634 unsigned int *mtu_idxp)
3635{
3636 unsigned short max_mtu = header_size + data_size_max;
3637 unsigned short data_size_align_mask = data_size_align - 1;
3638 int mtu_idx, aligned_mtu_idx;
3639
3640 /* Scan the MTU Table till we find an MTU which is larger than our
3641 * Maximum MTU or we reach the end of the table. Along the way,
3642 * record the last MTU found, if any, which will result in a Data
3643 * Segment Length matching the requested alignment.
3644 */
3645 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3646 unsigned short data_size = mtus[mtu_idx] - header_size;
3647
3648 /* If this MTU minus the Header Size would result in a
3649 * Data Segment Size of the desired alignment, remember it.
3650 */
3651 if ((data_size & data_size_align_mask) == 0)
3652 aligned_mtu_idx = mtu_idx;
3653
3654 /* If we're not at the end of the Hardware MTU Table and the
3655 * next element is larger than our Maximum MTU, drop out of
3656 * the loop.
3657 */
3658 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3659 break;
3660 }
3661
3662 /* If we fell out of the loop because we ran to the end of the table,
3663 * then we just have to use the last [largest] entry.
3664 */
3665 if (mtu_idx == NMTUS)
3666 mtu_idx--;
3667
3668 /* If we found an MTU which resulted in the requested Data Segment
3669 * Length alignment and that's "not far" from the largest MTU which is
3670 * less than or equal to the maximum MTU, then use that.
3671 */
3672 if (aligned_mtu_idx >= 0 &&
3673 mtu_idx - aligned_mtu_idx <= 1)
3674 mtu_idx = aligned_mtu_idx;
3675
3676 /* If the caller has passed in an MTU Index pointer, pass the
3677 * MTU Index back. Return the MTU value.
3678 */
3679 if (mtu_idxp)
3680 *mtu_idxp = mtu_idx;
3681 return mtus[mtu_idx];
3682}
3683EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3684
b8ff05a9
DM		 3685/**
3686 * cxgb4_port_chan - get the HW channel of a port
3687 * @dev: the net device for the port
3688 *
3689 * Return the HW Tx channel of the given port.
3690 */
3691unsigned int cxgb4_port_chan(const struct net_device *dev)
3692{
3693 return netdev2pinfo(dev)->tx_chan;
3694}
3695EXPORT_SYMBOL(cxgb4_port_chan);
3696
881806bc
VP		 3697unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3698{
3699 struct adapter *adap = netdev2adap(dev);
2cc301d2 3700 u32 v1, v2, lp_count, hp_count;
881806bc 3701
2cc301d2
SR		 3702 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3703 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
d14807dd 3704 if (is_t4(adap->params.chip)) {
2cc301d2
SR		 3705 lp_count = G_LP_COUNT(v1);
3706 hp_count = G_HP_COUNT(v1);
3707 } else {
3708 lp_count = G_LP_COUNT_T5(v1);
3709 hp_count = G_HP_COUNT_T5(v2);
3710 }
3711 return lpfifo ? lp_count : hp_count;
881806bc
VP		 3712}
3713EXPORT_SYMBOL(cxgb4_dbfifo_count);
3714
b8ff05a9
DM		 3715/**
3716 * cxgb4_port_viid - get the VI id of a port
3717 * @dev: the net device for the port
3718 *
3719 * Return the VI id of the given port.
3720 */
3721unsigned int cxgb4_port_viid(const struct net_device *dev)
3722{
3723 return netdev2pinfo(dev)->viid;
3724}
3725EXPORT_SYMBOL(cxgb4_port_viid);
3726
3727/**
3728 * cxgb4_port_idx - get the index of a port
3729 * @dev: the net device for the port
3730 *
3731 * Return the index of the given port.
3732 */
3733unsigned int cxgb4_port_idx(const struct net_device *dev)
3734{
3735 return netdev2pinfo(dev)->port_id;
3736}
3737EXPORT_SYMBOL(cxgb4_port_idx);
3738
b8ff05a9
DM		 3739void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3740 struct tp_tcp_stats *v6)
3741{
3742 struct adapter *adap = pci_get_drvdata(pdev);
3743
3744 spin_lock(&adap->stats_lock);
3745 t4_tp_get_tcp_stats(adap, v4, v6);
3746 spin_unlock(&adap->stats_lock);
3747}
3748EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3749
3750void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3751 const unsigned int *pgsz_order)
3752{
3753 struct adapter *adap = netdev2adap(dev);
3754
3755 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3756 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3757 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3758 HPZ3(pgsz_order[3]));
3759}
3760EXPORT_SYMBOL(cxgb4_iscsi_init);
3761
3069ee9b
VP		 3762int cxgb4_flush_eq_cache(struct net_device *dev)
3763{
3764 struct adapter *adap = netdev2adap(dev);
3765 int ret;
3766
3767 ret = t4_fwaddrspace_write(adap, adap->mbox,
3768 0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3769 return ret;
3770}
3771EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3772
3773static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3774{
3775 u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3776 __be64 indices;
3777 int ret;
3778
fc5ab020
HS		 3779 spin_lock(&adap->win0_lock);
3780 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3781 sizeof(indices), (__be32 *)&indices,
3782 T4_MEMORY_READ);
3783 spin_unlock(&adap->win0_lock);
3069ee9b 3784 if (!ret) {
404d9e3f
VP		 3785 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3786 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 3787 }
3788 return ret;
3789}
3790
3791int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3792 u16 size)
3793{
3794 struct adapter *adap = netdev2adap(dev);
3795 u16 hw_pidx, hw_cidx;
3796 int ret;
3797
3798 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3799 if (ret)
3800 goto out;
3801
3802 if (pidx != hw_pidx) {
3803 u16 delta;
3804
3805 if (pidx >= hw_pidx)
3806 delta = pidx - hw_pidx;
3807 else
3808 delta = size - hw_pidx + pidx;
3809 wmb();
840f3000
VP		 3810 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3811 QID(qid) | PIDX(delta));
3069ee9b
VP		 3812 }
3813out:
3814 return ret;
3815}
3816EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3817
3cbdb928
VP		 3818void cxgb4_disable_db_coalescing(struct net_device *dev)
3819{
3820 struct adapter *adap;
3821
3822 adap = netdev2adap(dev);
3823 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3824 F_NOCOALESCE);
3825}
3826EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3827
3828void cxgb4_enable_db_coalescing(struct net_device *dev)
3829{
3830 struct adapter *adap;
3831
3832 adap = netdev2adap(dev);
3833 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3834}
3835EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3836
031cf476
HS		 3837int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
3838{
3839 struct adapter *adap;
3840 u32 offset, memtype, memaddr;
3841 u32 edc0_size, edc1_size, mc0_size, mc1_size;
3842 u32 edc0_end, edc1_end, mc0_end, mc1_end;
3843 int ret;
3844
3845 adap = netdev2adap(dev);
3846
3847 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
3848
3849 /* Figure out where the offset lands in the Memory Type/Address scheme.
3850 * This code assumes that the memory is laid out starting at offset 0
3851 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3852 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
3853 * MC0, and some have both MC0 and MC1.
3854 */
3855 edc0_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM0_BAR)) << 20;
3856 edc1_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM1_BAR)) << 20;
3857 mc0_size = EXT_MEM_SIZE_GET(t4_read_reg(adap, MA_EXT_MEMORY_BAR)) << 20;
3858
3859 edc0_end = edc0_size;
3860 edc1_end = edc0_end + edc1_size;
3861 mc0_end = edc1_end + mc0_size;
3862
3863 if (offset < edc0_end) {
3864 memtype = MEM_EDC0;
3865 memaddr = offset;
3866 } else if (offset < edc1_end) {
3867 memtype = MEM_EDC1;
3868 memaddr = offset - edc0_end;
3869 } else {
3870 if (offset < mc0_end) {
3871 memtype = MEM_MC0;
3872 memaddr = offset - edc1_end;
3873 } else if (is_t4(adap->params.chip)) {
3874 /* T4 only has a single memory channel */
3875 goto err;
3876 } else {
3877 mc1_size = EXT_MEM_SIZE_GET(
3878 t4_read_reg(adap,
3879 MA_EXT_MEMORY1_BAR)) << 20;
3880 mc1_end = mc0_end + mc1_size;
3881 if (offset < mc1_end) {
3882 memtype = MEM_MC1;
3883 memaddr = offset - mc0_end;
3884 } else {
3885 /* offset beyond the end of any memory */
3886 goto err;
3887 }
3888 }
3889 }
3890
3891 spin_lock(&adap->win0_lock);
3892 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
3893 spin_unlock(&adap->win0_lock);
3894 return ret;
3895
3896err:
3897 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
3898 stag, offset);
3899 return -EINVAL;
3900}
3901EXPORT_SYMBOL(cxgb4_read_tpte);
3902
7730b4c7
HS		 3903u64 cxgb4_read_sge_timestamp(struct net_device *dev)
3904{
3905 u32 hi, lo;
3906 struct adapter *adap;
3907
3908 adap = netdev2adap(dev);
3909 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);
3910 hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));
3911
3912 return ((u64)hi << 32) | (u64)lo;
3913}
3914EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
3915
b8ff05a9
DM		 3916static struct pci_driver cxgb4_driver;
3917
3918static void check_neigh_update(struct neighbour *neigh)
3919{
3920 const struct device *parent;
3921 const struct net_device *netdev = neigh->dev;
3922
3923 if (netdev->priv_flags & IFF_802_1Q_VLAN)
3924 netdev = vlan_dev_real_dev(netdev);
3925 parent = netdev->dev.parent;
3926 if (parent && parent->driver == &cxgb4_driver.driver)
3927 t4_l2t_update(dev_get_drvdata(parent), neigh);
3928}
3929
3930static int netevent_cb(struct notifier_block *nb, unsigned long event,
3931 void *data)
3932{
3933 switch (event) {
3934 case NETEVENT_NEIGH_UPDATE:
3935 check_neigh_update(data);
3936 break;
b8ff05a9
DM		 3937 case NETEVENT_REDIRECT:
3938 default:
3939 break;
3940 }
3941 return 0;
3942}
3943
3944static bool netevent_registered;
3945static struct notifier_block cxgb4_netevent_nb = {
3946 .notifier_call = netevent_cb
3947};
3948
3069ee9b
VP		 3949static void drain_db_fifo(struct adapter *adap, int usecs)
3950{
2cc301d2 3951 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 3952
3953 do {
2cc301d2
SR		 3954 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3955 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
d14807dd 3956 if (is_t4(adap->params.chip)) {
2cc301d2
SR		 3957 lp_count = G_LP_COUNT(v1);
3958 hp_count = G_HP_COUNT(v1);
3959 } else {
3960 lp_count = G_LP_COUNT_T5(v1);
3961 hp_count = G_HP_COUNT_T5(v2);
3962 }
3963
3964 if (lp_count == 0 && hp_count == 0)
3965 break;
3069ee9b
VP		 3966 set_current_state(TASK_UNINTERRUPTIBLE);
3967 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 3968 } while (1);
3969}
3970
3971static void disable_txq_db(struct sge_txq *q)
3972{
05eb2389
SW		 3973 unsigned long flags;
3974
3975 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 3976 q->db_disabled = 1;
05eb2389 3977 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 3978}
3979
05eb2389 3980static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 3981{
3982 spin_lock_irq(&q->db_lock);
05eb2389
SW		 3983 if (q->db_pidx_inc) {
3984 /* Make sure that all writes to the TX descriptors
3985 * are committed before we tell HW about them.
3986 */
3987 wmb();
3988 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3989 QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3990 q->db_pidx_inc = 0;
3991 }
3069ee9b
VP		 3992 q->db_disabled = 0;
3993 spin_unlock_irq(&q->db_lock);
3994}
3995
3996static void disable_dbs(struct adapter *adap)
3997{
3998 int i;
3999
4000 for_each_ethrxq(&adap->sge, i)
4001 disable_txq_db(&adap->sge.ethtxq[i].q);
4002 for_each_ofldrxq(&adap->sge, i)
4003 disable_txq_db(&adap->sge.ofldtxq[i].q);
4004 for_each_port(adap, i)
4005 disable_txq_db(&adap->sge.ctrlq[i].q);
4006}
4007
4008static void enable_dbs(struct adapter *adap)
4009{
4010 int i;
4011
4012 for_each_ethrxq(&adap->sge, i)
05eb2389 4013 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3069ee9b 4014 for_each_ofldrxq(&adap->sge, i)
05eb2389 4015 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3069ee9b 4016 for_each_port(adap, i)
05eb2389
SW		 4017 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
4018}
4019
4020static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
4021{
4022 if (adap->uld_handle[CXGB4_ULD_RDMA])
4023 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
4024 cmd);
4025}
4026
4027static void process_db_full(struct work_struct *work)
4028{
4029 struct adapter *adap;
4030
4031 adap = container_of(work, struct adapter, db_full_task);
4032
4033 drain_db_fifo(adap, dbfifo_drain_delay);
4034 enable_dbs(adap);
4035 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
4036 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4037 DBFIFO_HP_INT | DBFIFO_LP_INT,
4038 DBFIFO_HP_INT | DBFIFO_LP_INT);
3069ee9b
VP		 4039}
4040
4041static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
4042{
4043 u16 hw_pidx, hw_cidx;
4044 int ret;
4045
05eb2389 4046 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 4047 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
4048 if (ret)
4049 goto out;
4050 if (q->db_pidx != hw_pidx) {
4051 u16 delta;
4052
4053 if (q->db_pidx >= hw_pidx)
4054 delta = q->db_pidx - hw_pidx;
4055 else
4056 delta = q->size - hw_pidx + q->db_pidx;
4057 wmb();
840f3000
VP		 4058 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
4059 QID(q->cntxt_id) | PIDX(delta));
3069ee9b
VP		 4060 }
4061out:
4062 q->db_disabled = 0;
05eb2389
SW		 4063 q->db_pidx_inc = 0;
4064 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 4065 if (ret)
4066 CH_WARN(adap, "DB drop recovery failed.\n");
4067}
4068static void recover_all_queues(struct adapter *adap)
4069{
4070 int i;
4071
4072 for_each_ethrxq(&adap->sge, i)
4073 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
4074 for_each_ofldrxq(&adap->sge, i)
4075 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
4076 for_each_port(adap, i)
4077 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
4078}
4079
881806bc
VP		 4080static void process_db_drop(struct work_struct *work)
4081{
4082 struct adapter *adap;
881806bc 4083
3069ee9b 4084 adap = container_of(work, struct adapter, db_drop_task);
881806bc 4085
d14807dd 4086 if (is_t4(adap->params.chip)) {
05eb2389 4087 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4088 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 4089 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4090 recover_all_queues(adap);
05eb2389 4091 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4092 enable_dbs(adap);
05eb2389 4093 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2cc301d2
SR		 4094 } else {
4095 u32 dropped_db = t4_read_reg(adap, 0x010ac);
4096 u16 qid = (dropped_db >> 15) & 0x1ffff;
4097 u16 pidx_inc = dropped_db & 0x1fff;
4098 unsigned int s_qpp;
4099 unsigned short udb_density;
4100 unsigned long qpshift;
4101 int page;
4102 u32 udb;
4103
4104 dev_warn(adap->pdev_dev,
4105 "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4106 dropped_db, qid,
4107 (dropped_db >> 14) & 1,
4108 (dropped_db >> 13) & 1,
4109 pidx_inc);
4110
4111 drain_db_fifo(adap, 1);
4112
4113 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
4114 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
4115 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
4116 qpshift = PAGE_SHIFT - ilog2(udb_density);
4117 udb = qid << qpshift;
4118 udb &= PAGE_MASK;
4119 page = udb / PAGE_SIZE;
4120 udb += (qid - (page * udb_density)) * 128;
4121
4122 writel(PIDX(pidx_inc), adap->bar2 + udb + 8);
4123
4124 /* Re-enable BAR2 WC */
4125 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4126 }
4127
3069ee9b 4128 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
881806bc
VP		 4129}
4130
4131void t4_db_full(struct adapter *adap)
4132{
d14807dd 4133 if (is_t4(adap->params.chip)) {
05eb2389
SW		 4134 disable_dbs(adap);
4135 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2cc301d2
SR		 4136 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4137 DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4138 queue_work(workq, &adap->db_full_task);
4139 }
881806bc
VP		 4140}
4141
4142void t4_db_dropped(struct adapter *adap)
4143{
05eb2389
SW		 4144 if (is_t4(adap->params.chip)) {
4145 disable_dbs(adap);
4146 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4147 }
4148 queue_work(workq, &adap->db_drop_task);
881806bc
VP		 4149}
4150
b8ff05a9
DM		 4151static void uld_attach(struct adapter *adap, unsigned int uld)
4152{
4153 void *handle;
4154 struct cxgb4_lld_info lli;
dca4faeb 4155 unsigned short i;
b8ff05a9
DM		 4156
4157 lli.pdev = adap->pdev;
35b1de55 4158 lli.pf = adap->fn;
b8ff05a9
DM		 4159 lli.l2t = adap->l2t;
4160 lli.tids = &adap->tids;
4161 lli.ports = adap->port;
4162 lli.vr = &adap->vres;
4163 lli.mtus = adap->params.mtus;
4164 if (uld == CXGB4_ULD_RDMA) {
4165 lli.rxq_ids = adap->sge.rdma_rxq;
cf38be6d 4166 lli.ciq_ids = adap->sge.rdma_ciq;
b8ff05a9 4167 lli.nrxq = adap->sge.rdmaqs;
cf38be6d 4168 lli.nciq = adap->sge.rdmaciqs;
b8ff05a9
DM		 4169 } else if (uld == CXGB4_ULD_ISCSI) {
4170 lli.rxq_ids = adap->sge.ofld_rxq;
4171 lli.nrxq = adap->sge.ofldqsets;
4172 }
4173 lli.ntxq = adap->sge.ofldqsets;
4174 lli.nchan = adap->params.nports;
4175 lli.nports = adap->params.nports;
4176 lli.wr_cred = adap->params.ofldq_wr_cred;
d14807dd 4177 lli.adapter_type = adap->params.chip;
b8ff05a9 4178 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
7730b4c7 4179 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
b8ff05a9 4180 lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
060e0c75
DM		 4181 t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4182 (adap->fn * 4));
b8ff05a9 4183 lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
060e0c75
DM		 4184 t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4185 (adap->fn * 4));
dcf7b6f5 4186 lli.filt_mode = adap->params.tp.vlan_pri_map;
dca4faeb
VP		 4187 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4188 for (i = 0; i < NCHAN; i++)
4189 lli.tx_modq[i] = i;
b8ff05a9
DM		 4190 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4191 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4192 lli.fw_vers = adap->params.fw_vers;
3069ee9b 4193 lli.dbfifo_int_thresh = dbfifo_int_thresh;
04e10e21
HS		 4194 lli.sge_ingpadboundary = adap->sge.fl_align;
4195 lli.sge_egrstatuspagesize = adap->sge.stat_len;
dca4faeb
VP		 4196 lli.sge_pktshift = adap->sge.pktshift;
4197 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4c2c5763
HS		 4198 lli.max_ordird_qp = adap->params.max_ordird_qp;
4199 lli.max_ird_adapter = adap->params.max_ird_adapter;
1ac0f095 4200 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
b8ff05a9
DM		 4201
4202 handle = ulds[uld].add(&lli);
4203 if (IS_ERR(handle)) {
4204 dev_warn(adap->pdev_dev,
4205 "could not attach to the %s driver, error %ld\n",
4206 uld_str[uld], PTR_ERR(handle));
4207 return;
4208 }
4209
4210 adap->uld_handle[uld] = handle;
4211
4212 if (!netevent_registered) {
4213 register_netevent_notifier(&cxgb4_netevent_nb);
4214 netevent_registered = true;
4215 }
e29f5dbc
DM		 4216
4217 if (adap->flags & FULL_INIT_DONE)
4218 ulds[uld].state_change(handle, CXGB4_STATE_UP);
b8ff05a9
DM		 4219}
4220
4221static void attach_ulds(struct adapter *adap)
4222{
4223 unsigned int i;
4224
01bcca68
VP		 4225 spin_lock(&adap_rcu_lock);
4226 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4227 spin_unlock(&adap_rcu_lock);
4228
b8ff05a9
DM		 4229 mutex_lock(&uld_mutex);
4230 list_add_tail(&adap->list_node, &adapter_list);
4231 for (i = 0; i < CXGB4_ULD_MAX; i++)
4232 if (ulds[i].add)
4233 uld_attach(adap, i);
4234 mutex_unlock(&uld_mutex);
4235}
4236
4237static void detach_ulds(struct adapter *adap)
4238{
4239 unsigned int i;
4240
4241 mutex_lock(&uld_mutex);
4242 list_del(&adap->list_node);
4243 for (i = 0; i < CXGB4_ULD_MAX; i++)
4244 if (adap->uld_handle[i]) {
4245 ulds[i].state_change(adap->uld_handle[i],
4246 CXGB4_STATE_DETACH);
4247 adap->uld_handle[i] = NULL;
4248 }
4249 if (netevent_registered && list_empty(&adapter_list)) {
4250 unregister_netevent_notifier(&cxgb4_netevent_nb);
4251 netevent_registered = false;
4252 }
4253 mutex_unlock(&uld_mutex);
01bcca68
VP		 4254
4255 spin_lock(&adap_rcu_lock);
4256 list_del_rcu(&adap->rcu_node);
4257 spin_unlock(&adap_rcu_lock);
b8ff05a9
DM		 4258}
4259
4260static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4261{
4262 unsigned int i;
4263
4264 mutex_lock(&uld_mutex);
4265 for (i = 0; i < CXGB4_ULD_MAX; i++)
4266 if (adap->uld_handle[i])
4267 ulds[i].state_change(adap->uld_handle[i], new_state);
4268 mutex_unlock(&uld_mutex);
4269}
4270
4271/**
4272 * cxgb4_register_uld - register an upper-layer driver
4273 * @type: the ULD type
4274 * @p: the ULD methods
4275 *
4276 * Registers an upper-layer driver with this driver and notifies the ULD
4277 * about any presently available devices that support its type. Returns
4278 * %-EBUSY if a ULD of the same type is already registered.
4279 */
4280int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4281{
4282 int ret = 0;
4283 struct adapter *adap;
4284
4285 if (type >= CXGB4_ULD_MAX)
4286 return -EINVAL;
4287 mutex_lock(&uld_mutex);
4288 if (ulds[type].add) {
4289 ret = -EBUSY;
4290 goto out;
4291 }
4292 ulds[type] = *p;
4293 list_for_each_entry(adap, &adapter_list, list_node)
4294 uld_attach(adap, type);
4295out: mutex_unlock(&uld_mutex);
4296 return ret;
4297}
4298EXPORT_SYMBOL(cxgb4_register_uld);
4299
4300/**
4301 * cxgb4_unregister_uld - unregister an upper-layer driver
4302 * @type: the ULD type
4303 *
4304 * Unregisters an existing upper-layer driver.
4305 */
4306int cxgb4_unregister_uld(enum cxgb4_uld type)
4307{
4308 struct adapter *adap;
4309
4310 if (type >= CXGB4_ULD_MAX)
4311 return -EINVAL;
4312 mutex_lock(&uld_mutex);
4313 list_for_each_entry(adap, &adapter_list, list_node)
4314 adap->uld_handle[type] = NULL;
4315 ulds[type].add = NULL;
4316 mutex_unlock(&uld_mutex);
4317 return 0;
4318}
4319EXPORT_SYMBOL(cxgb4_unregister_uld);
4320
01bcca68 4321/* Check if netdev on which event is occured belongs to us or not. Return
ee9a33b2
LR		 4322 * success (true) if it belongs otherwise failure (false).
4323 * Called with rcu_read_lock() held.
01bcca68 4324 */
ee9a33b2 4325static bool cxgb4_netdev(const struct net_device *netdev)
01bcca68
VP		 4326{
4327 struct adapter *adap;
4328 int i;
4329
01bcca68
VP		 4330 list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4331 for (i = 0; i < MAX_NPORTS; i++)
ee9a33b2
LR		 4332 if (adap->port[i] == netdev)
4333 return true;
4334 return false;
01bcca68
VP		 4335}
4336
4337static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4338 unsigned long event)
4339{
4340 int ret = NOTIFY_DONE;
4341
4342 rcu_read_lock();
4343 if (cxgb4_netdev(event_dev)) {
4344 switch (event) {
4345 case NETDEV_UP:
4346 ret = cxgb4_clip_get(event_dev,
4347 (const struct in6_addr *)ifa->addr.s6_addr);
4348 if (ret < 0) {
4349 rcu_read_unlock();
4350 return ret;
4351 }
4352 ret = NOTIFY_OK;
4353 break;
4354 case NETDEV_DOWN:
4355 cxgb4_clip_release(event_dev,
4356 (const struct in6_addr *)ifa->addr.s6_addr);
4357 ret = NOTIFY_OK;
4358 break;
4359 default:
4360 break;
4361 }
4362 }
4363 rcu_read_unlock();
4364 return ret;
4365}
4366
4367static int cxgb4_inet6addr_handler(struct notifier_block *this,
4368 unsigned long event, void *data)
4369{
4370 struct inet6_ifaddr *ifa = data;
4371 struct net_device *event_dev;
4372 int ret = NOTIFY_DONE;
01bcca68 4373 struct bonding *bond = netdev_priv(ifa->idev->dev);
9caff1e7 4374 struct list_head *iter;
01bcca68
VP		 4375 struct slave *slave;
4376 struct pci_dev *first_pdev = NULL;
4377
4378 if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4379 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4380 ret = clip_add(event_dev, ifa, event);
4381 } else if (ifa->idev->dev->flags & IFF_MASTER) {
4382 /* It is possible that two different adapters are bonded in one
4383 * bond. We need to find such different adapters and add clip
4384 * in all of them only once.
4385 */
4386 read_lock(&bond->lock);
9caff1e7 4387 bond_for_each_slave(bond, slave, iter) {
01bcca68
VP		 4388 if (!first_pdev) {
4389 ret = clip_add(slave->dev, ifa, event);
4390 /* If clip_add is success then only initialize
4391 * first_pdev since it means it is our device
4392 */
4393 if (ret == NOTIFY_OK)
4394 first_pdev = to_pci_dev(
4395 slave->dev->dev.parent);
4396 } else if (first_pdev !=
4397 to_pci_dev(slave->dev->dev.parent))
4398 ret = clip_add(slave->dev, ifa, event);
4399 }
4400 read_unlock(&bond->lock);
4401 } else
4402 ret = clip_add(ifa->idev->dev, ifa, event);
4403
4404 return ret;
4405}
4406
4407static struct notifier_block cxgb4_inet6addr_notifier = {
4408 .notifier_call = cxgb4_inet6addr_handler
4409};
4410
4411/* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4412 * a physical device.
4413 * The physical device reference is needed to send the actul CLIP command.
4414 */
4415static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4416{
4417 struct inet6_dev *idev = NULL;
4418 struct inet6_ifaddr *ifa;
4419 int ret = 0;
4420
4421 idev = __in6_dev_get(root_dev);
4422 if (!idev)
4423 return ret;
4424
4425 read_lock_bh(&idev->lock);
4426 list_for_each_entry(ifa, &idev->addr_list, if_list) {
4427 ret = cxgb4_clip_get(dev,
4428 (const struct in6_addr *)ifa->addr.s6_addr);
4429 if (ret < 0)
4430 break;
4431 }
4432 read_unlock_bh(&idev->lock);
4433
4434 return ret;
4435}
4436
4437static int update_root_dev_clip(struct net_device *dev)
4438{
4439 struct net_device *root_dev = NULL;
4440 int i, ret = 0;
4441
4442 /* First populate the real net device's IPv6 addresses */
4443 ret = update_dev_clip(dev, dev);
4444 if (ret)
4445 return ret;
4446
4447 /* Parse all bond and vlan devices layered on top of the physical dev */
4448 for (i = 0; i < VLAN_N_VID; i++) {
f06c7f9f 4449 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
01bcca68
VP		 4450 if (!root_dev)
4451 continue;
4452
4453 ret = update_dev_clip(root_dev, dev);
4454 if (ret)
4455 break;
4456 }
4457 return ret;
4458}
4459
4460static void update_clip(const struct adapter *adap)
4461{
4462 int i;
4463 struct net_device *dev;
4464 int ret;
4465
4466 rcu_read_lock();
4467
4468 for (i = 0; i < MAX_NPORTS; i++) {
4469 dev = adap->port[i];
4470 ret = 0;
4471
4472 if (dev)
4473 ret = update_root_dev_clip(dev);
4474
4475 if (ret < 0)
4476 break;
4477 }
4478 rcu_read_unlock();
4479}
4480
b8ff05a9
DM		 4481/**
4482 * cxgb_up - enable the adapter
4483 * @adap: adapter being enabled
4484 *
4485 * Called when the first port is enabled, this function performs the
4486 * actions necessary to make an adapter operational, such as completing
4487 * the initialization of HW modules, and enabling interrupts.
4488 *
4489 * Must be called with the rtnl lock held.
4490 */
4491static int cxgb_up(struct adapter *adap)
4492{
aaefae9b 4493 int err;
b8ff05a9 4494
aaefae9b
DM		 4495 err = setup_sge_queues(adap);
4496 if (err)
4497 goto out;
4498 err = setup_rss(adap);
4499 if (err)
4500 goto freeq;
b8ff05a9
DM		 4501
4502 if (adap->flags & USING_MSIX) {
aaefae9b 4503 name_msix_vecs(adap);
b8ff05a9
DM		 4504 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4505 adap->msix_info[0].desc, adap);
4506 if (err)
4507 goto irq_err;
4508
4509 err = request_msix_queue_irqs(adap);
4510 if (err) {
4511 free_irq(adap->msix_info[0].vec, adap);
4512 goto irq_err;
4513 }
4514 } else {
4515 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4516 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 4517 adap->port[0]->name, adap);
b8ff05a9
DM		 4518 if (err)
4519 goto irq_err;
4520 }
4521 enable_rx(adap);
4522 t4_sge_start(adap);
4523 t4_intr_enable(adap);
aaefae9b 4524 adap->flags |= FULL_INIT_DONE;
b8ff05a9 4525 notify_ulds(adap, CXGB4_STATE_UP);
01bcca68 4526 update_clip(adap);
b8ff05a9
DM		 4527 out:
4528 return err;
4529 irq_err:
4530 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 4531 freeq:
4532 t4_free_sge_resources(adap);
b8ff05a9
DM		 4533 goto out;
4534}
4535
4536static void cxgb_down(struct adapter *adapter)
4537{
4538 t4_intr_disable(adapter);
4539 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 4540 cancel_work_sync(&adapter->db_full_task);
4541 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 4542 adapter->tid_release_task_busy = false;
204dc3c0 4543 adapter->tid_release_head = NULL;
b8ff05a9
DM		 4544
4545 if (adapter->flags & USING_MSIX) {
4546 free_msix_queue_irqs(adapter);
4547 free_irq(adapter->msix_info[0].vec, adapter);
4548 } else
4549 free_irq(adapter->pdev->irq, adapter);
4550 quiesce_rx(adapter);
aaefae9b
DM		 4551 t4_sge_stop(adapter);
4552 t4_free_sge_resources(adapter);
4553 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 4554}
4555
4556/*
4557 * net_device operations
4558 */
4559static int cxgb_open(struct net_device *dev)
4560{
4561 int err;
4562 struct port_info *pi = netdev_priv(dev);
4563 struct adapter *adapter = pi->adapter;
4564
6a3c869a
DM		 4565 netif_carrier_off(dev);
4566
aaefae9b
DM		 4567 if (!(adapter->flags & FULL_INIT_DONE)) {
4568 err = cxgb_up(adapter);
4569 if (err < 0)
4570 return err;
4571 }
b8ff05a9 4572
f68707b8
DM		 4573 err = link_start(dev);
4574 if (!err)
4575 netif_tx_start_all_queues(dev);
4576 return err;
b8ff05a9
DM		 4577}
4578
4579static int cxgb_close(struct net_device *dev)
4580{
b8ff05a9
DM		 4581 struct port_info *pi = netdev_priv(dev);
4582 struct adapter *adapter = pi->adapter;
4583
4584 netif_tx_stop_all_queues(dev);
4585 netif_carrier_off(dev);
060e0c75 4586 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
b8ff05a9
DM		 4587}
4588
f2b7e78d
VP		 4589/* Return an error number if the indicated filter isn't writable ...
4590 */
4591static int writable_filter(struct filter_entry *f)
4592{
4593 if (f->locked)
4594 return -EPERM;
4595 if (f->pending)
4596 return -EBUSY;
4597
4598 return 0;
4599}
4600
4601/* Delete the filter at the specified index (if valid). The checks for all
4602 * the common problems with doing this like the filter being locked, currently
4603 * pending in another operation, etc.
4604 */
4605static int delete_filter(struct adapter *adapter, unsigned int fidx)
4606{
4607 struct filter_entry *f;
4608 int ret;
4609
dca4faeb 4610 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
f2b7e78d
VP		 4611 return -EINVAL;
4612
4613 f = &adapter->tids.ftid_tab[fidx];
4614 ret = writable_filter(f);
4615 if (ret)
4616 return ret;
4617 if (f->valid)
4618 return del_filter_wr(adapter, fidx);
4619
4620 return 0;
4621}
4622
dca4faeb 4623int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 4624 __be32 sip, __be16 sport, __be16 vlan,
4625 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 4626{
4627 int ret;
4628 struct filter_entry *f;
4629 struct adapter *adap;
4630 int i;
4631 u8 *val;
4632
4633 adap = netdev2adap(dev);
4634
1cab775c 4635 /* Adjust stid to correct filter index */
470c60c4 4636 stid -= adap->tids.sftid_base;
1cab775c
VP		 4637 stid += adap->tids.nftids;
4638
dca4faeb
VP		 4639 /* Check to make sure the filter requested is writable ...
4640 */
4641 f = &adap->tids.ftid_tab[stid];
4642 ret = writable_filter(f);
4643 if (ret)
4644 return ret;
4645
4646 /* Clear out any old resources being used by the filter before
4647 * we start constructing the new filter.
4648 */
4649 if (f->valid)
4650 clear_filter(adap, f);
4651
4652 /* Clear out filter specifications */
4653 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4654 f->fs.val.lport = cpu_to_be16(sport);
4655 f->fs.mask.lport = ~0;
4656 val = (u8 *)&sip;
793dad94 4657 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 4658 for (i = 0; i < 4; i++) {
4659 f->fs.val.lip[i] = val[i];
4660 f->fs.mask.lip[i] = ~0;
4661 }
dcf7b6f5 4662 if (adap->params.tp.vlan_pri_map & F_PORT) {
793dad94
VP		 4663 f->fs.val.iport = port;
4664 f->fs.mask.iport = mask;
4665 }
4666 }
dca4faeb 4667
dcf7b6f5 4668 if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
7c89e555
KS		 4669 f->fs.val.proto = IPPROTO_TCP;
4670 f->fs.mask.proto = ~0;
4671 }
4672
dca4faeb
VP		 4673 f->fs.dirsteer = 1;
4674 f->fs.iq = queue;
4675 /* Mark filter as locked */
4676 f->locked = 1;
4677 f->fs.rpttid = 1;
4678
4679 ret = set_filter_wr(adap, stid);
4680 if (ret) {
4681 clear_filter(adap, f);
4682 return ret;
4683 }
4684
4685 return 0;
4686}
4687EXPORT_SYMBOL(cxgb4_create_server_filter);
4688
4689int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4690 unsigned int queue, bool ipv6)
4691{
4692 int ret;
4693 struct filter_entry *f;
4694 struct adapter *adap;
4695
4696 adap = netdev2adap(dev);
1cab775c
VP		 4697
4698 /* Adjust stid to correct filter index */
470c60c4 4699 stid -= adap->tids.sftid_base;
1cab775c
VP		 4700 stid += adap->tids.nftids;
4701
dca4faeb
VP		 4702 f = &adap->tids.ftid_tab[stid];
4703 /* Unlock the filter */
4704 f->locked = 0;
4705
4706 ret = delete_filter(adap, stid);
4707 if (ret)
4708 return ret;
4709
4710 return 0;
4711}
4712EXPORT_SYMBOL(cxgb4_remove_server_filter);
4713
f5152c90
DM		 4714static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4715 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 4716{
4717 struct port_stats stats;
4718 struct port_info *p = netdev_priv(dev);
4719 struct adapter *adapter = p->adapter;
b8ff05a9 4720
9fe6cb58
GS		 4721 /* Block retrieving statistics during EEH error
4722 * recovery. Otherwise, the recovery might fail
4723 * and the PCI device will be removed permanently
4724 */
b8ff05a9 4725 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 4726 if (!netif_device_present(dev)) {
4727 spin_unlock(&adapter->stats_lock);
4728 return ns;
4729 }
b8ff05a9
DM		 4730 t4_get_port_stats(adapter, p->tx_chan, &stats);
4731 spin_unlock(&adapter->stats_lock);
4732
4733 ns->tx_bytes = stats.tx_octets;
4734 ns->tx_packets = stats.tx_frames;
4735 ns->rx_bytes = stats.rx_octets;
4736 ns->rx_packets = stats.rx_frames;
4737 ns->multicast = stats.rx_mcast_frames;
4738
4739 /* detailed rx_errors */
4740 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4741 stats.rx_runt;
4742 ns->rx_over_errors = 0;
4743 ns->rx_crc_errors = stats.rx_fcs_err;
4744 ns->rx_frame_errors = stats.rx_symbol_err;
4745 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
4746 stats.rx_ovflow2 + stats.rx_ovflow3 +
4747 stats.rx_trunc0 + stats.rx_trunc1 +
4748 stats.rx_trunc2 + stats.rx_trunc3;
4749 ns->rx_missed_errors = 0;
4750
4751 /* detailed tx_errors */
4752 ns->tx_aborted_errors = 0;
4753 ns->tx_carrier_errors = 0;
4754 ns->tx_fifo_errors = 0;
4755 ns->tx_heartbeat_errors = 0;
4756 ns->tx_window_errors = 0;
4757
4758 ns->tx_errors = stats.tx_error_frames;
4759 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4760 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4761 return ns;
4762}
4763
4764static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4765{
060e0c75 4766 unsigned int mbox;
b8ff05a9
DM		 4767 int ret = 0, prtad, devad;
4768 struct port_info *pi = netdev_priv(dev);
4769 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4770
4771 switch (cmd) {
4772 case SIOCGMIIPHY:
4773 if (pi->mdio_addr < 0)
4774 return -EOPNOTSUPP;
4775 data->phy_id = pi->mdio_addr;
4776 break;
4777 case SIOCGMIIREG:
4778 case SIOCSMIIREG:
4779 if (mdio_phy_id_is_c45(data->phy_id)) {
4780 prtad = mdio_phy_id_prtad(data->phy_id);
4781 devad = mdio_phy_id_devad(data->phy_id);
4782 } else if (data->phy_id < 32) {
4783 prtad = data->phy_id;
4784 devad = 0;
4785 data->reg_num &= 0x1f;
4786 } else
4787 return -EINVAL;
4788
060e0c75 4789 mbox = pi->adapter->fn;
b8ff05a9 4790 if (cmd == SIOCGMIIREG)
060e0c75 4791 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 4792 data->reg_num, &data->val_out);
4793 else
060e0c75 4794 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 4795 data->reg_num, data->val_in);
4796 break;
4797 default:
4798 return -EOPNOTSUPP;
4799 }
4800 return ret;
4801}
4802
4803static void cxgb_set_rxmode(struct net_device *dev)
4804{
4805 /* unfortunately we can't return errors to the stack */
4806 set_rxmode(dev, -1, false);
4807}
4808
4809static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4810{
4811 int ret;
4812 struct port_info *pi = netdev_priv(dev);
4813
4814 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
4815 return -EINVAL;
060e0c75
DM		 4816 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4817 -1, -1, -1, true);
b8ff05a9
DM		 4818 if (!ret)
4819 dev->mtu = new_mtu;
4820 return ret;
4821}
4822
4823static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4824{
4825 int ret;
4826 struct sockaddr *addr = p;
4827 struct port_info *pi = netdev_priv(dev);
4828
4829 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 4830 return -EADDRNOTAVAIL;
b8ff05a9 4831
060e0c75
DM		 4832 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4833 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM		 4834 if (ret < 0)
4835 return ret;
4836
4837 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4838 pi->xact_addr_filt = ret;
4839 return 0;
4840}
4841
b8ff05a9
DM		 4842#ifdef CONFIG_NET_POLL_CONTROLLER
4843static void cxgb_netpoll(struct net_device *dev)
4844{
4845 struct port_info *pi = netdev_priv(dev);
4846 struct adapter *adap = pi->adapter;
4847
4848 if (adap->flags & USING_MSIX) {
4849 int i;
4850 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4851
4852 for (i = pi->nqsets; i; i--, rx++)
4853 t4_sge_intr_msix(0, &rx->rspq);
4854 } else
4855 t4_intr_handler(adap)(0, adap);
4856}
4857#endif
4858
4859static const struct net_device_ops cxgb4_netdev_ops = {
4860 .ndo_open = cxgb_open,
4861 .ndo_stop = cxgb_close,
4862 .ndo_start_xmit = t4_eth_xmit,
688848b1 4863 .ndo_select_queue = cxgb_select_queue,
9be793bf 4864 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 4865 .ndo_set_rx_mode = cxgb_set_rxmode,
4866 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 4867 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 4868 .ndo_validate_addr = eth_validate_addr,
4869 .ndo_do_ioctl = cxgb_ioctl,
4870 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 4871#ifdef CONFIG_NET_POLL_CONTROLLER
4872 .ndo_poll_controller = cxgb_netpoll,
4873#endif
4874};
4875
4876void t4_fatal_err(struct adapter *adap)
4877{
4878 t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4879 t4_intr_disable(adap);
4880 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4881}
4882
0abfd152
HS		 4883/* Return the specified PCI-E Configuration Space register from our Physical
4884 * Function. We try first via a Firmware LDST Command since we prefer to let
4885 * the firmware own all of these registers, but if that fails we go for it
4886 * directly ourselves.
4887 */
4888static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4889{
4890 struct fw_ldst_cmd ldst_cmd;
4891 u32 val;
4892 int ret;
4893
4894 /* Construct and send the Firmware LDST Command to retrieve the
4895 * specified PCI-E Configuration Space register.
4896 */
4897 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4898 ldst_cmd.op_to_addrspace =
4899 htonl(FW_CMD_OP(FW_LDST_CMD) |
4900 FW_CMD_REQUEST |
4901 FW_CMD_READ |
4902 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
4903 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4904 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
4905 ldst_cmd.u.pcie.ctrl_to_fn =
4906 (FW_LDST_CMD_LC | FW_LDST_CMD_FN(adap->fn));
4907 ldst_cmd.u.pcie.r = reg;
4908 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4909 &ldst_cmd);
4910
4911 /* If the LDST Command suucceeded, exctract the returned register
4912 * value. Otherwise read it directly ourself.
4913 */
4914 if (ret == 0)
4915 val = ntohl(ldst_cmd.u.pcie.data[0]);
4916 else
4917 t4_hw_pci_read_cfg4(adap, reg, &val);
4918
4919 return val;
4920}
4921
b8ff05a9
DM		 4922static void setup_memwin(struct adapter *adap)
4923{
0abfd152 4924 u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
b8ff05a9 4925
d14807dd 4926 if (is_t4(adap->params.chip)) {
0abfd152
HS		 4927 u32 bar0;
4928
4929 /* Truncation intentional: we only read the bottom 32-bits of
4930 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
4931 * mechanism to read BAR0 instead of using
4932 * pci_resource_start() because we could be operating from
4933 * within a Virtual Machine which is trapping our accesses to
4934 * our Configuration Space and we need to set up the PCI-E
4935 * Memory Window decoders with the actual addresses which will
4936 * be coming across the PCI-E link.
4937 */
4938 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4939 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4940 adap->t4_bar0 = bar0;
4941
19dd37ba
SR		 4942 mem_win0_base = bar0 + MEMWIN0_BASE;
4943 mem_win1_base = bar0 + MEMWIN1_BASE;
4944 mem_win2_base = bar0 + MEMWIN2_BASE;
0abfd152 4945 mem_win2_aperture = MEMWIN2_APERTURE;
19dd37ba
SR		 4946 } else {
4947 /* For T5, only relative offset inside the PCIe BAR is passed */
4948 mem_win0_base = MEMWIN0_BASE;
0abfd152 4949 mem_win1_base = MEMWIN1_BASE;
19dd37ba 4950 mem_win2_base = MEMWIN2_BASE_T5;
0abfd152 4951 mem_win2_aperture = MEMWIN2_APERTURE_T5;
19dd37ba 4952 }
b8ff05a9 4953 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
19dd37ba 4954 mem_win0_base | BIR(0) |
b8ff05a9
DM		 4955 WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4956 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
19dd37ba 4957 mem_win1_base | BIR(0) |
b8ff05a9
DM		 4958 WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4959 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
19dd37ba 4960 mem_win2_base | BIR(0) |
0abfd152
HS		 4961 WINDOW(ilog2(mem_win2_aperture) - 10));
4962 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
636f9d37
VP		 4963}
4964
4965static void setup_memwin_rdma(struct adapter *adap)
4966{
1ae970e0 4967 if (adap->vres.ocq.size) {
0abfd152
HS		 4968 u32 start;
4969 unsigned int sz_kb;
1ae970e0 4970
0abfd152
HS		 4971 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4972 start &= PCI_BASE_ADDRESS_MEM_MASK;
4973 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 4974 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4975 t4_write_reg(adap,
4976 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4977 start | BIR(1) | WINDOW(ilog2(sz_kb)));
4978 t4_write_reg(adap,
4979 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4980 adap->vres.ocq.start);
4981 t4_read_reg(adap,
4982 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4983 }
b8ff05a9
DM		 4984}
4985
02b5fb8e
DM		 4986static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4987{
4988 u32 v;
4989 int ret;
4990
4991 /* get device capabilities */
4992 memset(c, 0, sizeof(*c));
4993 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4994 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 4995 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
060e0c75 4996 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
02b5fb8e
DM		 4997 if (ret < 0)
4998 return ret;
4999
5000 /* select capabilities we'll be using */
5001 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5002 if (!vf_acls)
5003 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5004 else
5005 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5006 } else if (vf_acls) {
5007 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
5008 return ret;
5009 }
5010 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5011 FW_CMD_REQUEST | FW_CMD_WRITE);
060e0c75 5012 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
02b5fb8e
DM		 5013 if (ret < 0)
5014 return ret;
5015
060e0c75 5016 ret = t4_config_glbl_rss(adap, adap->fn,
02b5fb8e
DM		 5017 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5018 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5019 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
5020 if (ret < 0)
5021 return ret;
5022
060e0c75
DM		 5023 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
5024 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
02b5fb8e
DM		 5025 if (ret < 0)
5026 return ret;
5027
5028 t4_sge_init(adap);
5029
02b5fb8e
DM		 5030 /* tweak some settings */
5031 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
5032 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
5033 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
5034 v = t4_read_reg(adap, TP_PIO_DATA);
5035 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
060e0c75 5036
dca4faeb
VP		 5037 /* first 4 Tx modulation queues point to consecutive Tx channels */
5038 adap->params.tp.tx_modq_map = 0xE4;
5039 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
5040 V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
5041
5042 /* associate each Tx modulation queue with consecutive Tx channels */
5043 v = 0x84218421;
5044 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5045 &v, 1, A_TP_TX_SCHED_HDR);
5046 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5047 &v, 1, A_TP_TX_SCHED_FIFO);
5048 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5049 &v, 1, A_TP_TX_SCHED_PCMD);
5050
5051#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
5052 if (is_offload(adap)) {
5053 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
5054 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5055 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5056 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5057 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
5058 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
5059 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5060 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5061 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5062 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
5063 }
5064
060e0c75
DM		 5065 /* get basic stuff going */
5066 return t4_early_init(adap, adap->fn);
02b5fb8e
DM		 5067}
5068
b8ff05a9
DM		 5069/*
5070 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
5071 */
5072#define MAX_ATIDS 8192U
5073
636f9d37
VP		 5074/*
5075 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5076 *
5077 * If the firmware we're dealing with has Configuration File support, then
5078 * we use that to perform all configuration
5079 */
5080
5081/*
5082 * Tweak configuration based on module parameters, etc. Most of these have
5083 * defaults assigned to them by Firmware Configuration Files (if we're using
5084 * them) but need to be explicitly set if we're using hard-coded
5085 * initialization. But even in the case of using Firmware Configuration
5086 * Files, we'd like to expose the ability to change these via module
5087 * parameters so these are essentially common tweaks/settings for
5088 * Configuration Files and hard-coded initialization ...
5089 */
5090static int adap_init0_tweaks(struct adapter *adapter)
5091{
5092 /*
5093 * Fix up various Host-Dependent Parameters like Page Size, Cache
5094 * Line Size, etc. The firmware default is for a 4KB Page Size and
5095 * 64B Cache Line Size ...
5096 */
5097 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
5098
5099 /*
5100 * Process module parameters which affect early initialization.
5101 */
5102 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
5103 dev_err(&adapter->pdev->dev,
5104 "Ignoring illegal rx_dma_offset=%d, using 2\n",
5105 rx_dma_offset);
5106 rx_dma_offset = 2;
5107 }
5108 t4_set_reg_field(adapter, SGE_CONTROL,
5109 PKTSHIFT_MASK,
5110 PKTSHIFT(rx_dma_offset));
5111
5112 /*
5113 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5114 * adds the pseudo header itself.
5115 */
5116 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5117 CSUM_HAS_PSEUDO_HDR, 0);
5118
5119 return 0;
5120}
5121
5122/*
5123 * Attempt to initialize the adapter via a Firmware Configuration File.
5124 */
5125static int adap_init0_config(struct adapter *adapter, int reset)
5126{
5127 struct fw_caps_config_cmd caps_cmd;
5128 const struct firmware *cf;
5129 unsigned long mtype = 0, maddr = 0;
5130 u32 finiver, finicsum, cfcsum;
16e47624
HS		 5131 int ret;
5132 int config_issued = 0;
0a57a536 5133 char *fw_config_file, fw_config_file_path[256];
16e47624 5134 char *config_name = NULL;
636f9d37
VP		 5135
5136 /*
5137 * Reset device if necessary.
5138 */
5139 if (reset) {
5140 ret = t4_fw_reset(adapter, adapter->mbox,
5141 PIORSTMODE | PIORST);
5142 if (ret < 0)
5143 goto bye;
5144 }
5145
5146 /*
5147 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5148 * then use that. Otherwise, use the configuration file stored
5149 * in the adapter flash ...
5150 */
d14807dd 5151 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 5152 case CHELSIO_T4:
16e47624 5153 fw_config_file = FW4_CFNAME;
0a57a536
SR		 5154 break;
5155 case CHELSIO_T5:
5156 fw_config_file = FW5_CFNAME;
5157 break;
5158 default:
5159 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5160 adapter->pdev->device);
5161 ret = -EINVAL;
5162 goto bye;
5163 }
5164
5165 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 5166 if (ret < 0) {
16e47624 5167 config_name = "On FLASH";
636f9d37
VP		 5168 mtype = FW_MEMTYPE_CF_FLASH;
5169 maddr = t4_flash_cfg_addr(adapter);
5170 } else {
5171 u32 params[7], val[7];
5172
16e47624
HS		 5173 sprintf(fw_config_file_path,
5174 "/lib/firmware/%s", fw_config_file);
5175 config_name = fw_config_file_path;
5176
636f9d37
VP		 5177 if (cf->size >= FLASH_CFG_MAX_SIZE)
5178 ret = -ENOMEM;
5179 else {
5180 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5181 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5182 ret = t4_query_params(adapter, adapter->mbox,
5183 adapter->fn, 0, 1, params, val);
5184 if (ret == 0) {
5185 /*
fc5ab020 5186 * For t4_memory_rw() below addresses and
636f9d37
VP		 5187 * sizes have to be in terms of multiples of 4
5188 * bytes. So, if the Configuration File isn't
5189 * a multiple of 4 bytes in length we'll have
5190 * to write that out separately since we can't
5191 * guarantee that the bytes following the
5192 * residual byte in the buffer returned by
5193 * request_firmware() are zeroed out ...
5194 */
5195 size_t resid = cf->size & 0x3;
5196 size_t size = cf->size & ~0x3;
5197 __be32 *data = (__be32 *)cf->data;
5198
5199 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
5200 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
5201
fc5ab020
HS		 5202 spin_lock(&adapter->win0_lock);
5203 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5204 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 5205 if (ret == 0 && resid != 0) {
5206 union {
5207 __be32 word;
5208 char buf[4];
5209 } last;
5210 int i;
5211
5212 last.word = data[size >> 2];
5213 for (i = resid; i < 4; i++)
5214 last.buf[i] = 0;
fc5ab020
HS		 5215 ret = t4_memory_rw(adapter, 0, mtype,
5216 maddr + size,
5217 4, &last.word,
5218 T4_MEMORY_WRITE);
636f9d37 5219 }
fc5ab020 5220 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 5221 }
5222 }
5223
5224 release_firmware(cf);
5225 if (ret)
5226 goto bye;
5227 }
5228
5229 /*
5230 * Issue a Capability Configuration command to the firmware to get it
5231 * to parse the Configuration File. We don't use t4_fw_config_file()
5232 * because we want the ability to modify various features after we've
5233 * processed the configuration file ...
5234 */
5235 memset(&caps_cmd, 0, sizeof(caps_cmd));
5236 caps_cmd.op_to_write =
5237 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5238 FW_CMD_REQUEST |
5239 FW_CMD_READ);
ce91a923 5240 caps_cmd.cfvalid_to_len16 =
636f9d37
VP		 5241 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
5242 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5243 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
5244 FW_LEN16(caps_cmd));
5245 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5246 &caps_cmd);
16e47624
HS		 5247
5248 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5249 * Configuration File in FLASH), our last gasp effort is to use the
5250 * Firmware Configuration File which is embedded in the firmware. A
5251 * very few early versions of the firmware didn't have one embedded
5252 * but we can ignore those.
5253 */
5254 if (ret == -ENOENT) {
5255 memset(&caps_cmd, 0, sizeof(caps_cmd));
5256 caps_cmd.op_to_write =
5257 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5258 FW_CMD_REQUEST |
5259 FW_CMD_READ);
5260 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5261 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5262 sizeof(caps_cmd), &caps_cmd);
5263 config_name = "Firmware Default";
5264 }
5265
5266 config_issued = 1;
636f9d37
VP		 5267 if (ret < 0)
5268 goto bye;
5269
5270 finiver = ntohl(caps_cmd.finiver);
5271 finicsum = ntohl(caps_cmd.finicsum);
5272 cfcsum = ntohl(caps_cmd.cfcsum);
5273 if (finicsum != cfcsum)
5274 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5275 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5276 finicsum, cfcsum);
5277
636f9d37
VP		 5278 /*
5279 * And now tell the firmware to use the configuration we just loaded.
5280 */
5281 caps_cmd.op_to_write =
5282 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5283 FW_CMD_REQUEST |
5284 FW_CMD_WRITE);
ce91a923 5285 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 5286 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5287 NULL);
5288 if (ret < 0)
5289 goto bye;
5290
5291 /*
5292 * Tweak configuration based on system architecture, module
5293 * parameters, etc.
5294 */
5295 ret = adap_init0_tweaks(adapter);
5296 if (ret < 0)
5297 goto bye;
5298
5299 /*
5300 * And finally tell the firmware to initialize itself using the
5301 * parameters from the Configuration File.
5302 */
5303 ret = t4_fw_initialize(adapter, adapter->mbox);
5304 if (ret < 0)
5305 goto bye;
5306
5307 /*
5308 * Return successfully and note that we're operating with parameters
5309 * not supplied by the driver, rather than from hard-wired
5310 * initialization constants burried in the driver.
5311 */
5312 adapter->flags |= USING_SOFT_PARAMS;
5313 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 5314 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5315 config_name, finiver, cfcsum);
636f9d37
VP		 5316 return 0;
5317
5318 /*
5319 * Something bad happened. Return the error ... (If the "error"
5320 * is that there's no Configuration File on the adapter we don't
5321 * want to issue a warning since this is fairly common.)
5322 */
5323bye:
16e47624
HS		 5324 if (config_issued && ret != -ENOENT)
5325 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5326 config_name, -ret);
636f9d37
VP		 5327 return ret;
5328}
5329
13ee15d3
VP		 5330/*
5331 * Attempt to initialize the adapter via hard-coded, driver supplied
5332 * parameters ...
5333 */
5334static int adap_init0_no_config(struct adapter *adapter, int reset)
5335{
5336 struct sge *s = &adapter->sge;
5337 struct fw_caps_config_cmd caps_cmd;
5338 u32 v;
5339 int i, ret;
5340
5341 /*
5342 * Reset device if necessary
5343 */
5344 if (reset) {
5345 ret = t4_fw_reset(adapter, adapter->mbox,
5346 PIORSTMODE | PIORST);
5347 if (ret < 0)
5348 goto bye;
5349 }
5350
5351 /*
5352 * Get device capabilities and select which we'll be using.
5353 */
5354 memset(&caps_cmd, 0, sizeof(caps_cmd));
5355 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5356 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5357 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
13ee15d3
VP		 5358 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5359 &caps_cmd);
5360 if (ret < 0)
5361 goto bye;
5362
13ee15d3
VP		 5363 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5364 if (!vf_acls)
5365 caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5366 else
5367 caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5368 } else if (vf_acls) {
5369 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5370 goto bye;
5371 }
5372 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5373 FW_CMD_REQUEST | FW_CMD_WRITE);
5374 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5375 NULL);
5376 if (ret < 0)
5377 goto bye;
5378
5379 /*
5380 * Tweak configuration based on system architecture, module
5381 * parameters, etc.
5382 */
5383 ret = adap_init0_tweaks(adapter);
5384 if (ret < 0)
5385 goto bye;
5386
5387 /*
5388 * Select RSS Global Mode we want to use. We use "Basic Virtual"
5389 * mode which maps each Virtual Interface to its own section of
5390 * the RSS Table and we turn on all map and hash enables ...
5391 */
5392 adapter->flags |= RSS_TNLALLLOOKUP;
5393 ret = t4_config_glbl_rss(adapter, adapter->mbox,
5394 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5395 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5396 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
5397 ((adapter->flags & RSS_TNLALLLOOKUP) ?
5398 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
5399 if (ret < 0)
5400 goto bye;
5401
5402 /*
5403 * Set up our own fundamental resource provisioning ...
5404 */
5405 ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5406 PFRES_NEQ, PFRES_NETHCTRL,
5407 PFRES_NIQFLINT, PFRES_NIQ,
5408 PFRES_TC, PFRES_NVI,
5409 FW_PFVF_CMD_CMASK_MASK,
5410 pfvfres_pmask(adapter, adapter->fn, 0),
5411 PFRES_NEXACTF,
5412 PFRES_R_CAPS, PFRES_WX_CAPS);
5413 if (ret < 0)
5414 goto bye;
5415
5416 /*
5417 * Perform low level SGE initialization. We need to do this before we
5418 * send the firmware the INITIALIZE command because that will cause
5419 * any other PF Drivers which are waiting for the Master
5420 * Initialization to proceed forward.
5421 */
5422 for (i = 0; i < SGE_NTIMERS - 1; i++)
5423 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5424 s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5425 s->counter_val[0] = 1;
5426 for (i = 1; i < SGE_NCOUNTERS; i++)
5427 s->counter_val[i] = min(intr_cnt[i - 1],
5428 THRESHOLD_0_GET(THRESHOLD_0_MASK));
5429 t4_sge_init(adapter);
5430
5431#ifdef CONFIG_PCI_IOV
5432 /*
5433 * Provision resource limits for Virtual Functions. We currently
5434 * grant them all the same static resource limits except for the Port
5435 * Access Rights Mask which we're assigning based on the PF. All of
5436 * the static provisioning stuff for both the PF and VF really needs
5437 * to be managed in a persistent manner for each device which the
5438 * firmware controls.
5439 */
5440 {
5441 int pf, vf;
5442
7d6727cf 5443 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
13ee15d3
VP		 5444 if (num_vf[pf] <= 0)
5445 continue;
5446
5447 /* VF numbering starts at 1! */
5448 for (vf = 1; vf <= num_vf[pf]; vf++) {
5449 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5450 pf, vf,
5451 VFRES_NEQ, VFRES_NETHCTRL,
5452 VFRES_NIQFLINT, VFRES_NIQ,
5453 VFRES_TC, VFRES_NVI,
1f1e4958 5454 FW_PFVF_CMD_CMASK_MASK,
13ee15d3
VP		 5455 pfvfres_pmask(
5456 adapter, pf, vf),
5457 VFRES_NEXACTF,
5458 VFRES_R_CAPS, VFRES_WX_CAPS);
5459 if (ret < 0)
5460 dev_warn(adapter->pdev_dev,
5461 "failed to "\
5462 "provision pf/vf=%d/%d; "
5463 "err=%d\n", pf, vf, ret);
5464 }
5465 }
5466 }
5467#endif
5468
5469 /*
5470 * Set up the default filter mode. Later we'll want to implement this
5471 * via a firmware command, etc. ... This needs to be done before the
5472 * firmare initialization command ... If the selected set of fields
5473 * isn't equal to the default value, we'll need to make sure that the
5474 * field selections will fit in the 36-bit budget.
5475 */
5476 if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
404d9e3f 5477 int j, bits = 0;
13ee15d3 5478
404d9e3f
VP		 5479 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5480 switch (tp_vlan_pri_map & (1 << j)) {
13ee15d3
VP		 5481 case 0:
5482 /* compressed filter field not enabled */
5483 break;
5484 case FCOE_MASK:
5485 bits += 1;
5486 break;
5487 case PORT_MASK:
5488 bits += 3;
5489 break;
5490 case VNIC_ID_MASK:
5491 bits += 17;
5492 break;
5493 case VLAN_MASK:
5494 bits += 17;
5495 break;
5496 case TOS_MASK:
5497 bits += 8;
5498 break;
5499 case PROTOCOL_MASK:
5500 bits += 8;
5501 break;
5502 case ETHERTYPE_MASK:
5503 bits += 16;
5504 break;
5505 case MACMATCH_MASK:
5506 bits += 9;
5507 break;
5508 case MPSHITTYPE_MASK:
5509 bits += 3;
5510 break;
5511 case FRAGMENTATION_MASK:
5512 bits += 1;
5513 break;
5514 }
5515
5516 if (bits > 36) {
5517 dev_err(adapter->pdev_dev,
5518 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5519 " using %#x\n", tp_vlan_pri_map, bits,
5520 TP_VLAN_PRI_MAP_DEFAULT);
5521 tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5522 }
5523 }
5524 v = tp_vlan_pri_map;
5525 t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5526 &v, 1, TP_VLAN_PRI_MAP);
5527
5528 /*
5529 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5530 * to support any of the compressed filter fields above. Newer
5531 * versions of the firmware do this automatically but it doesn't hurt
5532 * to set it here. Meanwhile, we do _not_ need to set Lookup Every
5533 * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5534 * since the firmware automatically turns this on and off when we have
5535 * a non-zero number of filters active (since it does have a
5536 * performance impact).
5537 */
5538 if (tp_vlan_pri_map)
5539 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5540 FIVETUPLELOOKUP_MASK,
5541 FIVETUPLELOOKUP_MASK);
5542
5543 /*
5544 * Tweak some settings.
5545 */
5546 t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5547 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5548 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5549 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5550
5551 /*
5552 * Get basic stuff going by issuing the Firmware Initialize command.
5553 * Note that this _must_ be after all PFVF commands ...
5554 */
5555 ret = t4_fw_initialize(adapter, adapter->mbox);
5556 if (ret < 0)
5557 goto bye;
5558
5559 /*
5560 * Return successfully!
5561 */
5562 dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5563 "driver parameters\n");
5564 return 0;
5565
5566 /*
5567 * Something bad happened. Return the error ...
5568 */
5569bye:
5570 return ret;
5571}
5572
16e47624
HS		 5573static struct fw_info fw_info_array[] = {
5574 {
5575 .chip = CHELSIO_T4,
5576 .fs_name = FW4_CFNAME,
5577 .fw_mod_name = FW4_FNAME,
5578 .fw_hdr = {
5579 .chip = FW_HDR_CHIP_T4,
5580 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5581 .intfver_nic = FW_INTFVER(T4, NIC),
5582 .intfver_vnic = FW_INTFVER(T4, VNIC),
5583 .intfver_ri = FW_INTFVER(T4, RI),
5584 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5585 .intfver_fcoe = FW_INTFVER(T4, FCOE),
5586 },
5587 }, {
5588 .chip = CHELSIO_T5,
5589 .fs_name = FW5_CFNAME,
5590 .fw_mod_name = FW5_FNAME,
5591 .fw_hdr = {
5592 .chip = FW_HDR_CHIP_T5,
5593 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5594 .intfver_nic = FW_INTFVER(T5, NIC),
5595 .intfver_vnic = FW_INTFVER(T5, VNIC),
5596 .intfver_ri = FW_INTFVER(T5, RI),
5597 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5598 .intfver_fcoe = FW_INTFVER(T5, FCOE),
5599 },
5600 }
5601};
5602
5603static struct fw_info *find_fw_info(int chip)
5604{
5605 int i;
5606
5607 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5608 if (fw_info_array[i].chip == chip)
5609 return &fw_info_array[i];
5610 }
5611 return NULL;
5612}
5613
b8ff05a9
DM		 5614/*
5615 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5616 */
5617static int adap_init0(struct adapter *adap)
5618{
5619 int ret;
5620 u32 v, port_vec;
5621 enum dev_state state;
5622 u32 params[7], val[7];
9a4da2cd 5623 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 5624 int reset = 1;
b8ff05a9 5625
636f9d37
VP		 5626 /*
5627 * Contact FW, advertising Master capability (and potentially forcing
5628 * ourselves as the Master PF if our module parameter force_init is
5629 * set).
5630 */
5631 ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5632 force_init ? MASTER_MUST : MASTER_MAY,
5633 &state);
b8ff05a9
DM		 5634 if (ret < 0) {
5635 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5636 ret);
5637 return ret;
5638 }
636f9d37
VP		 5639 if (ret == adap->mbox)
5640 adap->flags |= MASTER_PF;
5641 if (force_init && state == DEV_STATE_INIT)
5642 state = DEV_STATE_UNINIT;
b8ff05a9 5643
636f9d37
VP		 5644 /*
5645 * If we're the Master PF Driver and the device is uninitialized,
5646 * then let's consider upgrading the firmware ... (We always want
5647 * to check the firmware version number in order to A. get it for
5648 * later reporting and B. to warn if the currently loaded firmware
5649 * is excessively mismatched relative to the driver.)
5650 */
16e47624
HS		 5651 t4_get_fw_version(adap, &adap->params.fw_vers);
5652 t4_get_tp_version(adap, &adap->params.tp_vers);
636f9d37 5653 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 5654 struct fw_info *fw_info;
5655 struct fw_hdr *card_fw;
5656 const struct firmware *fw;
5657 const u8 *fw_data = NULL;
5658 unsigned int fw_size = 0;
5659
5660 /* This is the firmware whose headers the driver was compiled
5661 * against
5662 */
5663 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5664 if (fw_info == NULL) {
5665 dev_err(adap->pdev_dev,
5666 "unable to get firmware info for chip %d.\n",
5667 CHELSIO_CHIP_VERSION(adap->params.chip));
5668 return -EINVAL;
636f9d37 5669 }
16e47624
HS		 5670
5671 /* allocate memory to read the header of the firmware on the
5672 * card
5673 */
5674 card_fw = t4_alloc_mem(sizeof(*card_fw));
5675
5676 /* Get FW from from /lib/firmware/ */
5677 ret = request_firmware(&fw, fw_info->fw_mod_name,
5678 adap->pdev_dev);
5679 if (ret < 0) {
5680 dev_err(adap->pdev_dev,
5681 "unable to load firmware image %s, error %d\n",
5682 fw_info->fw_mod_name, ret);
5683 } else {
5684 fw_data = fw->data;
5685 fw_size = fw->size;
5686 }
5687
5688 /* upgrade FW logic */
5689 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5690 state, &reset);
5691
5692 /* Cleaning up */
5693 if (fw != NULL)
5694 release_firmware(fw);
5695 t4_free_mem(card_fw);
5696
636f9d37 5697 if (ret < 0)
16e47624 5698 goto bye;
636f9d37 5699 }
b8ff05a9 5700
636f9d37
VP		 5701 /*
5702 * Grab VPD parameters. This should be done after we establish a
5703 * connection to the firmware since some of the VPD parameters
5704 * (notably the Core Clock frequency) are retrieved via requests to
5705 * the firmware. On the other hand, we need these fairly early on
5706 * so we do this right after getting ahold of the firmware.
5707 */
5708 ret = get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM		 5709 if (ret < 0)
5710 goto bye;
a0881cab 5711
636f9d37 5712 /*
13ee15d3
VP		 5713 * Find out what ports are available to us. Note that we need to do
5714 * this before calling adap_init0_no_config() since it needs nports
5715 * and portvec ...
636f9d37
VP		 5716 */
5717 v =
5718 FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5719 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
5720 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
a0881cab
DM		 5721 if (ret < 0)
5722 goto bye;
5723
636f9d37
VP		 5724 adap->params.nports = hweight32(port_vec);
5725 adap->params.portvec = port_vec;
5726
5727 /*
5728 * If the firmware is initialized already (and we're not forcing a
5729 * master initialization), note that we're living with existing
5730 * adapter parameters. Otherwise, it's time to try initializing the
5731 * adapter ...
5732 */
5733 if (state == DEV_STATE_INIT) {
5734 dev_info(adap->pdev_dev, "Coming up as %s: "\
5735 "Adapter already initialized\n",
5736 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5737 adap->flags |= USING_SOFT_PARAMS;
5738 } else {
5739 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5740 "Initializing adapter\n");
636f9d37
VP		 5741
5742 /*
5743 * If the firmware doesn't support Configuration
5744 * Files warn user and exit,
5745 */
5746 if (ret < 0)
13ee15d3 5747 dev_warn(adap->pdev_dev, "Firmware doesn't support "
636f9d37 5748 "configuration file.\n");
13ee15d3
VP		 5749 if (force_old_init)
5750 ret = adap_init0_no_config(adap, reset);
636f9d37
VP		 5751 else {
5752 /*
13ee15d3
VP		 5753 * Find out whether we're dealing with a version of
5754 * the firmware which has configuration file support.
636f9d37 5755 */
13ee15d3
VP		 5756 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5757 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5758 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5759 params, val);
636f9d37 5760
13ee15d3
VP		 5761 /*
5762 * If the firmware doesn't support Configuration
5763 * Files, use the old Driver-based, hard-wired
5764 * initialization. Otherwise, try using the
5765 * Configuration File support and fall back to the
5766 * Driver-based initialization if there's no
5767 * Configuration File found.
5768 */
5769 if (ret < 0)
5770 ret = adap_init0_no_config(adap, reset);
5771 else {
5772 /*
5773 * The firmware provides us with a memory
5774 * buffer where we can load a Configuration
5775 * File from the host if we want to override
5776 * the Configuration File in flash.
5777 */
5778
5779 ret = adap_init0_config(adap, reset);
5780 if (ret == -ENOENT) {
5781 dev_info(adap->pdev_dev,
5782 "No Configuration File present "
16e47624 5783 "on adapter. Using hard-wired "
13ee15d3
VP		 5784 "configuration parameters.\n");
5785 ret = adap_init0_no_config(adap, reset);
5786 }
636f9d37
VP		 5787 }
5788 }
5789 if (ret < 0) {
5790 dev_err(adap->pdev_dev,
5791 "could not initialize adapter, error %d\n",
5792 -ret);
5793 goto bye;
5794 }
5795 }
5796
5797 /*
5798 * If we're living with non-hard-coded parameters (either from a
5799 * Firmware Configuration File or values programmed by a different PF
5800 * Driver), give the SGE code a chance to pull in anything that it
5801 * needs ... Note that this must be called after we retrieve our VPD
5802 * parameters in order to know how to convert core ticks to seconds.
5803 */
5804 if (adap->flags & USING_SOFT_PARAMS) {
5805 ret = t4_sge_init(adap);
5806 if (ret < 0)
5807 goto bye;
5808 }
5809
9a4da2cd
VP		 5810 if (is_bypass_device(adap->pdev->device))
5811 adap->params.bypass = 1;
5812
636f9d37
VP		 5813 /*
5814 * Grab some of our basic fundamental operating parameters.
5815 */
5816#define FW_PARAM_DEV(param) \
5817 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5818 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5819
b8ff05a9 5820#define FW_PARAM_PFVF(param) \
636f9d37
VP		 5821 FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5822 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
5823 FW_PARAMS_PARAM_Y(0) | \
5824 FW_PARAMS_PARAM_Z(0)
b8ff05a9 5825
636f9d37 5826 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 5827 params[1] = FW_PARAM_PFVF(L2T_START);
5828 params[2] = FW_PARAM_PFVF(L2T_END);
5829 params[3] = FW_PARAM_PFVF(FILTER_START);
5830 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 5831 params[5] = FW_PARAM_PFVF(IQFLINT_START);
636f9d37 5832 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
b8ff05a9
DM		 5833 if (ret < 0)
5834 goto bye;
636f9d37
VP		 5835 adap->sge.egr_start = val[0];
5836 adap->l2t_start = val[1];
5837 adap->l2t_end = val[2];
b8ff05a9
DM		 5838 adap->tids.ftid_base = val[3];
5839 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 5840 adap->sge.ingr_start = val[5];
b8ff05a9 5841
636f9d37
VP		 5842 /* query params related to active filter region */
5843 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5844 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5845 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5846 /* If Active filter size is set we enable establishing
5847 * offload connection through firmware work request
5848 */
5849 if ((val[0] != val[1]) && (ret >= 0)) {
5850 adap->flags |= FW_OFLD_CONN;
5851 adap->tids.aftid_base = val[0];
5852 adap->tids.aftid_end = val[1];
5853 }
5854
b407a4a9
VP		 5855 /* If we're running on newer firmware, let it know that we're
5856 * prepared to deal with encapsulated CPL messages. Older
5857 * firmware won't understand this and we'll just get
5858 * unencapsulated messages ...
5859 */
5860 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5861 val[0] = 1;
5862 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5863
1ac0f095
KS		 5864 /*
5865 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5866 * capability. Earlier versions of the firmware didn't have the
5867 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5868 * permission to use ULPTX MEMWRITE DSGL.
5869 */
5870 if (is_t4(adap->params.chip)) {
5871 adap->params.ulptx_memwrite_dsgl = false;
5872 } else {
5873 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5874 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5875 1, params, val);
5876 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5877 }
5878
636f9d37
VP		 5879 /*
5880 * Get device capabilities so we can determine what resources we need
5881 * to manage.
5882 */
5883 memset(&caps_cmd, 0, sizeof(caps_cmd));
9a4da2cd 5884 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
13ee15d3 5885 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5886 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 5887 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5888 &caps_cmd);
5889 if (ret < 0)
5890 goto bye;
5891
13ee15d3 5892 if (caps_cmd.ofldcaps) {
b8ff05a9
DM		 5893 /* query offload-related parameters */
5894 params[0] = FW_PARAM_DEV(NTID);
5895 params[1] = FW_PARAM_PFVF(SERVER_START);
5896 params[2] = FW_PARAM_PFVF(SERVER_END);
5897 params[3] = FW_PARAM_PFVF(TDDP_START);
5898 params[4] = FW_PARAM_PFVF(TDDP_END);
5899 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
636f9d37
VP		 5900 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5901 params, val);
b8ff05a9
DM		 5902 if (ret < 0)
5903 goto bye;
5904 adap->tids.ntids = val[0];
5905 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5906 adap->tids.stid_base = val[1];
5907 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37
VP		 5908 /*
5909 * Setup server filter region. Divide the availble filter
5910 * region into two parts. Regular filters get 1/3rd and server
5911 * filters get 2/3rd part. This is only enabled if workarond
5912 * path is enabled.
5913 * 1. For regular filters.
5914 * 2. Server filter: This are special filters which are used
5915 * to redirect SYN packets to offload queue.
5916 */
5917 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5918 adap->tids.sftid_base = adap->tids.ftid_base +
5919 DIV_ROUND_UP(adap->tids.nftids, 3);
5920 adap->tids.nsftids = adap->tids.nftids -
5921 DIV_ROUND_UP(adap->tids.nftids, 3);
5922 adap->tids.nftids = adap->tids.sftid_base -
5923 adap->tids.ftid_base;
5924 }
b8ff05a9
DM		 5925 adap->vres.ddp.start = val[3];
5926 adap->vres.ddp.size = val[4] - val[3] + 1;
5927 adap->params.ofldq_wr_cred = val[5];
636f9d37 5928
b8ff05a9
DM		 5929 adap->params.offload = 1;
5930 }
636f9d37 5931 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 5932 params[0] = FW_PARAM_PFVF(STAG_START);
5933 params[1] = FW_PARAM_PFVF(STAG_END);
5934 params[2] = FW_PARAM_PFVF(RQ_START);
5935 params[3] = FW_PARAM_PFVF(RQ_END);
5936 params[4] = FW_PARAM_PFVF(PBL_START);
5937 params[5] = FW_PARAM_PFVF(PBL_END);
636f9d37
VP		 5938 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5939 params, val);
b8ff05a9
DM		 5940 if (ret < 0)
5941 goto bye;
5942 adap->vres.stag.start = val[0];
5943 adap->vres.stag.size = val[1] - val[0] + 1;
5944 adap->vres.rq.start = val[2];
5945 adap->vres.rq.size = val[3] - val[2] + 1;
5946 adap->vres.pbl.start = val[4];
5947 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab
DM		 5948
5949 params[0] = FW_PARAM_PFVF(SQRQ_START);
5950 params[1] = FW_PARAM_PFVF(SQRQ_END);
5951 params[2] = FW_PARAM_PFVF(CQ_START);
5952 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 5953 params[4] = FW_PARAM_PFVF(OCQ_START);
5954 params[5] = FW_PARAM_PFVF(OCQ_END);
636f9d37 5955 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
a0881cab
DM		 5956 if (ret < 0)
5957 goto bye;
5958 adap->vres.qp.start = val[0];
5959 adap->vres.qp.size = val[1] - val[0] + 1;
5960 adap->vres.cq.start = val[2];
5961 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 5962 adap->vres.ocq.start = val[4];
5963 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 5964
5965 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5966 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5967 ret = t4_query_params(adap, 0, 0, 0, 2, params, val);
5968 if (ret < 0) {
5969 adap->params.max_ordird_qp = 8;
5970 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5971 ret = 0;
5972 } else {
5973 adap->params.max_ordird_qp = val[0];
5974 adap->params.max_ird_adapter = val[1];
5975 }
5976 dev_info(adap->pdev_dev,
5977 "max_ordird_qp %d max_ird_adapter %d\n",
5978 adap->params.max_ordird_qp,
5979 adap->params.max_ird_adapter);
b8ff05a9 5980 }
636f9d37 5981 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 5982 params[0] = FW_PARAM_PFVF(ISCSI_START);
5983 params[1] = FW_PARAM_PFVF(ISCSI_END);
636f9d37
VP		 5984 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5985 params, val);
b8ff05a9
DM		 5986 if (ret < 0)
5987 goto bye;
5988 adap->vres.iscsi.start = val[0];
5989 adap->vres.iscsi.size = val[1] - val[0] + 1;
5990 }
5991#undef FW_PARAM_PFVF
5992#undef FW_PARAM_DEV
5993
92e7ae71
HS		 5994 /* The MTU/MSS Table is initialized by now, so load their values. If
5995 * we're initializing the adapter, then we'll make any modifications
5996 * we want to the MTU/MSS Table and also initialize the congestion
5997 * parameters.
636f9d37 5998 */
b8ff05a9 5999 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 6000 if (state != DEV_STATE_INIT) {
6001 int i;
6002
6003 /* The default MTU Table contains values 1492 and 1500.
6004 * However, for TCP, it's better to have two values which are
6005 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
6006 * This allows us to have a TCP Data Payload which is a
6007 * multiple of 8 regardless of what combination of TCP Options
6008 * are in use (always a multiple of 4 bytes) which is
6009 * important for performance reasons. For instance, if no
6010 * options are in use, then we have a 20-byte IP header and a
6011 * 20-byte TCP header. In this case, a 1500-byte MSS would
6012 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
6013 * which is not a multiple of 8. So using an MSS of 1488 in
6014 * this case results in a TCP Data Payload of 1448 bytes which
6015 * is a multiple of 8. On the other hand, if 12-byte TCP Time
6016 * Stamps have been negotiated, then an MTU of 1500 bytes
6017 * results in a TCP Data Payload of 1448 bytes which, as
6018 * above, is a multiple of 8 bytes ...
6019 */
6020 for (i = 0; i < NMTUS; i++)
6021 if (adap->params.mtus[i] == 1492) {
6022 adap->params.mtus[i] = 1488;
6023 break;
6024 }
7ee9ff94 6025
92e7ae71
HS		 6026 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6027 adap->params.b_wnd);
6028 }
dcf7b6f5 6029 t4_init_tp_params(adap);
636f9d37 6030 adap->flags |= FW_OK;
b8ff05a9
DM		 6031 return 0;
6032
6033 /*
636f9d37
VP		 6034 * Something bad happened. If a command timed out or failed with EIO
6035 * FW does not operate within its spec or something catastrophic
6036 * happened to HW/FW, stop issuing commands.
b8ff05a9 6037 */
636f9d37
VP		 6038bye:
6039 if (ret != -ETIMEDOUT && ret != -EIO)
6040 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 6041 return ret;
6042}
6043
204dc3c0
DM		 6044/* EEH callbacks */
6045
6046static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
6047 pci_channel_state_t state)
6048{
6049 int i;
6050 struct adapter *adap = pci_get_drvdata(pdev);
6051
6052 if (!adap)
6053 goto out;
6054
6055 rtnl_lock();
6056 adap->flags &= ~FW_OK;
6057 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 6058 spin_lock(&adap->stats_lock);
204dc3c0
DM		 6059 for_each_port(adap, i) {
6060 struct net_device *dev = adap->port[i];
6061
6062 netif_device_detach(dev);
6063 netif_carrier_off(dev);
6064 }
9fe6cb58 6065 spin_unlock(&adap->stats_lock);
204dc3c0
DM		 6066 if (adap->flags & FULL_INIT_DONE)
6067 cxgb_down(adap);
6068 rtnl_unlock();
144be3d9
GS		 6069 if ((adap->flags & DEV_ENABLED)) {
6070 pci_disable_device(pdev);
6071 adap->flags &= ~DEV_ENABLED;
6072 }
204dc3c0
DM		 6073out: return state == pci_channel_io_perm_failure ?
6074 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
6075}
6076
6077static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
6078{
6079 int i, ret;
6080 struct fw_caps_config_cmd c;
6081 struct adapter *adap = pci_get_drvdata(pdev);
6082
6083 if (!adap) {
6084 pci_restore_state(pdev);
6085 pci_save_state(pdev);
6086 return PCI_ERS_RESULT_RECOVERED;
6087 }
6088
144be3d9
GS		 6089 if (!(adap->flags & DEV_ENABLED)) {
6090 if (pci_enable_device(pdev)) {
6091 dev_err(&pdev->dev, "Cannot reenable PCI "
6092 "device after reset\n");
6093 return PCI_ERS_RESULT_DISCONNECT;
6094 }
6095 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 6096 }
6097
6098 pci_set_master(pdev);
6099 pci_restore_state(pdev);
6100 pci_save_state(pdev);
6101 pci_cleanup_aer_uncorrect_error_status(pdev);
6102
6103 if (t4_wait_dev_ready(adap) < 0)
6104 return PCI_ERS_RESULT_DISCONNECT;
777c2300 6105 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 6106 return PCI_ERS_RESULT_DISCONNECT;
6107 adap->flags |= FW_OK;
6108 if (adap_init1(adap, &c))
6109 return PCI_ERS_RESULT_DISCONNECT;
6110
6111 for_each_port(adap, i) {
6112 struct port_info *p = adap2pinfo(adap, i);
6113
060e0c75
DM		 6114 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
6115 NULL, NULL);
204dc3c0
DM		 6116 if (ret < 0)
6117 return PCI_ERS_RESULT_DISCONNECT;
6118 p->viid = ret;
6119 p->xact_addr_filt = -1;
6120 }
6121
6122 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6123 adap->params.b_wnd);
1ae970e0 6124 setup_memwin(adap);
204dc3c0
DM		 6125 if (cxgb_up(adap))
6126 return PCI_ERS_RESULT_DISCONNECT;
6127 return PCI_ERS_RESULT_RECOVERED;
6128}
6129
6130static void eeh_resume(struct pci_dev *pdev)
6131{
6132 int i;
6133 struct adapter *adap = pci_get_drvdata(pdev);
6134
6135 if (!adap)
6136 return;
6137
6138 rtnl_lock();
6139 for_each_port(adap, i) {
6140 struct net_device *dev = adap->port[i];
6141
6142 if (netif_running(dev)) {
6143 link_start(dev);
6144 cxgb_set_rxmode(dev);
6145 }
6146 netif_device_attach(dev);
6147 }
6148 rtnl_unlock();
6149}
6150
3646f0e5 6151static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 6152 .error_detected = eeh_err_detected,
6153 .slot_reset = eeh_slot_reset,
6154 .resume = eeh_resume,
6155};
6156
57d8b764 6157static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 6158{
57d8b764
KS		 6159 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6160 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
b8ff05a9
DM		 6161}
6162
c887ad0e
HS		 6163static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6164 unsigned int us, unsigned int cnt,
b8ff05a9
DM		 6165 unsigned int size, unsigned int iqe_size)
6166{
c887ad0e
HS		 6167 q->adap = adap;
6168 set_rspq_intr_params(q, us, cnt);
b8ff05a9
DM		 6169 q->iqe_len = iqe_size;
6170 q->size = size;
6171}
6172
6173/*
6174 * Perform default configuration of DMA queues depending on the number and type
6175 * of ports we found and the number of available CPUs. Most settings can be
6176 * modified by the admin prior to actual use.
6177 */
91744948 6178static void cfg_queues(struct adapter *adap)
b8ff05a9
DM		 6179{
6180 struct sge *s = &adap->sge;
688848b1
AB		 6181 int i, n10g = 0, qidx = 0;
6182#ifndef CONFIG_CHELSIO_T4_DCB
6183 int q10g = 0;
6184#endif
cf38be6d 6185 int ciq_size;
b8ff05a9
DM		 6186
6187 for_each_port(adap, i)
57d8b764 6188 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB		 6189#ifdef CONFIG_CHELSIO_T4_DCB
6190 /* For Data Center Bridging support we need to be able to support up
6191 * to 8 Traffic Priorities; each of which will be assigned to its
6192 * own TX Queue in order to prevent Head-Of-Line Blocking.
6193 */
6194 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6195 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6196 MAX_ETH_QSETS, adap->params.nports * 8);
6197 BUG_ON(1);
6198 }
b8ff05a9 6199
688848b1
AB		 6200 for_each_port(adap, i) {
6201 struct port_info *pi = adap2pinfo(adap, i);
6202
6203 pi->first_qset = qidx;
6204 pi->nqsets = 8;
6205 qidx += pi->nqsets;
6206 }
6207#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 6208 /*
6209 * We default to 1 queue per non-10G port and up to # of cores queues
6210 * per 10G port.
6211 */
6212 if (n10g)
6213 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 6214 if (q10g > netif_get_num_default_rss_queues())
6215 q10g = netif_get_num_default_rss_queues();
b8ff05a9
DM		 6216
6217 for_each_port(adap, i) {
6218 struct port_info *pi = adap2pinfo(adap, i);
6219
6220 pi->first_qset = qidx;
57d8b764 6221 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 6222 qidx += pi->nqsets;
6223 }
688848b1 6224#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 6225
6226 s->ethqsets = qidx;
6227 s->max_ethqsets = qidx; /* MSI-X may lower it later */
6228
6229 if (is_offload(adap)) {
6230 /*
6231 * For offload we use 1 queue/channel if all ports are up to 1G,
6232 * otherwise we divide all available queues amongst the channels
6233 * capped by the number of available cores.
6234 */
6235 if (n10g) {
6236 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6237 num_online_cpus());
6238 s->ofldqsets = roundup(i, adap->params.nports);
6239 } else
6240 s->ofldqsets = adap->params.nports;
6241 /* For RDMA one Rx queue per channel suffices */
6242 s->rdmaqs = adap->params.nports;
cf38be6d 6243 s->rdmaciqs = adap->params.nports;
b8ff05a9
DM		 6244 }
6245
6246 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6247 struct sge_eth_rxq *r = &s->ethrxq[i];
6248
c887ad0e 6249 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 6250 r->fl.size = 72;
6251 }
6252
6253 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6254 s->ethtxq[i].q.size = 1024;
6255
6256 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6257 s->ctrlq[i].q.size = 512;
6258
6259 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6260 s->ofldtxq[i].q.size = 1024;
6261
6262 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6263 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6264
c887ad0e 6265 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
b8ff05a9
DM		 6266 r->rspq.uld = CXGB4_ULD_ISCSI;
6267 r->fl.size = 72;
6268 }
6269
6270 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6271 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6272
c887ad0e 6273 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
b8ff05a9
DM		 6274 r->rspq.uld = CXGB4_ULD_RDMA;
6275 r->fl.size = 72;
6276 }
6277
cf38be6d
HS		 6278 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6279 if (ciq_size > SGE_MAX_IQ_SIZE) {
6280 CH_WARN(adap, "CIQ size too small for available IQs\n");
6281 ciq_size = SGE_MAX_IQ_SIZE;
6282 }
6283
6284 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6285 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6286
c887ad0e 6287 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
cf38be6d
HS		 6288 r->rspq.uld = CXGB4_ULD_RDMA;
6289 }
6290
c887ad0e
HS		 6291 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6292 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
b8ff05a9
DM		 6293}
6294
6295/*
6296 * Reduce the number of Ethernet queues across all ports to at most n.
6297 * n provides at least one queue per port.
6298 */
91744948 6299static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 6300{
6301 int i;
6302 struct port_info *pi;
6303
6304 while (n < adap->sge.ethqsets)
6305 for_each_port(adap, i) {
6306 pi = adap2pinfo(adap, i);
6307 if (pi->nqsets > 1) {
6308 pi->nqsets--;
6309 adap->sge.ethqsets--;
6310 if (adap->sge.ethqsets <= n)
6311 break;
6312 }
6313 }
6314
6315 n = 0;
6316 for_each_port(adap, i) {
6317 pi = adap2pinfo(adap, i);
6318 pi->first_qset = n;
6319 n += pi->nqsets;
6320 }
6321}
6322
6323/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6324#define EXTRA_VECS 2
6325
91744948 6326static int enable_msix(struct adapter *adap)
b8ff05a9
DM		 6327{
6328 int ofld_need = 0;
c32ad224 6329 int i, want, need;
b8ff05a9
DM		 6330 struct sge *s = &adap->sge;
6331 unsigned int nchan = adap->params.nports;
6332 struct msix_entry entries[MAX_INGQ + 1];
6333
6334 for (i = 0; i < ARRAY_SIZE(entries); ++i)
6335 entries[i].entry = i;
6336
6337 want = s->max_ethqsets + EXTRA_VECS;
6338 if (is_offload(adap)) {
cf38be6d 6339 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
b8ff05a9 6340 /* need nchan for each possible ULD */
cf38be6d 6341 ofld_need = 3 * nchan;
b8ff05a9 6342 }
688848b1
AB		 6343#ifdef CONFIG_CHELSIO_T4_DCB
6344 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6345 * each port.
6346 */
6347 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6348#else
b8ff05a9 6349 need = adap->params.nports + EXTRA_VECS + ofld_need;
688848b1 6350#endif
c32ad224
AG		 6351 want = pci_enable_msix_range(adap->pdev, entries, need, want);
6352 if (want < 0)
6353 return want;
b8ff05a9 6354
c32ad224
AG		 6355 /*
6356 * Distribute available vectors to the various queue groups.
6357 * Every group gets its minimum requirement and NIC gets top
6358 * priority for leftovers.
6359 */
6360 i = want - EXTRA_VECS - ofld_need;
6361 if (i < s->max_ethqsets) {
6362 s->max_ethqsets = i;
6363 if (i < s->ethqsets)
6364 reduce_ethqs(adap, i);
6365 }
6366 if (is_offload(adap)) {
6367 i = want - EXTRA_VECS - s->max_ethqsets;
6368 i -= ofld_need - nchan;
6369 s->ofldqsets = (i / nchan) * nchan; /* round down */
6370 }
6371 for (i = 0; i < want; ++i)
6372 adap->msix_info[i].vec = entries[i].vector;
6373
6374 return 0;
b8ff05a9
DM		 6375}
6376
6377#undef EXTRA_VECS
6378
91744948 6379static int init_rss(struct adapter *adap)
671b0060
DM		 6380{
6381 unsigned int i, j;
6382
6383 for_each_port(adap, i) {
6384 struct port_info *pi = adap2pinfo(adap, i);
6385
6386 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6387 if (!pi->rss)
6388 return -ENOMEM;
6389 for (j = 0; j < pi->rss_size; j++)
278bc429 6390 pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
671b0060
DM		 6391 }
6392 return 0;
6393}
6394
91744948 6395static void print_port_info(const struct net_device *dev)
b8ff05a9 6396{
b8ff05a9 6397 char buf[80];
118969ed 6398 char *bufp = buf;
f1a051b9 6399 const char *spd = "";
118969ed
DM		 6400 const struct port_info *pi = netdev_priv(dev);
6401 const struct adapter *adap = pi->adapter;
f1a051b9
DM		 6402
6403 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6404 spd = " 2.5 GT/s";
6405 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6406 spd = " 5 GT/s";
d2e752db
RD		 6407 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6408 spd = " 8 GT/s";
b8ff05a9 6409
118969ed
DM		 6410 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6411 bufp += sprintf(bufp, "100/");
6412 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6413 bufp += sprintf(bufp, "1000/");
6414 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6415 bufp += sprintf(bufp, "10G/");
72aca4bf
KS		 6416 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6417 bufp += sprintf(bufp, "40G/");
118969ed
DM		 6418 if (bufp != buf)
6419 --bufp;
72aca4bf 6420 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed
DM		 6421
6422 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
0a57a536 6423 adap->params.vpd.id,
d14807dd 6424 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
118969ed
DM		 6425 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6426 (adap->flags & USING_MSIX) ? " MSI-X" :
6427 (adap->flags & USING_MSI) ? " MSI" : "");
a94cd705
KS		 6428 netdev_info(dev, "S/N: %s, P/N: %s\n",
6429 adap->params.vpd.sn, adap->params.vpd.pn);
b8ff05a9
DM		 6430}
6431
91744948 6432static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
ef306b50 6433{
e5c8ae5f 6434 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
ef306b50
DM		 6435}
6436
06546391
DM		 6437/*
6438 * Free the following resources:
6439 * - memory used for tables
6440 * - MSI/MSI-X
6441 * - net devices
6442 * - resources FW is holding for us
6443 */
6444static void free_some_resources(struct adapter *adapter)
6445{
6446 unsigned int i;
6447
6448 t4_free_mem(adapter->l2t);
6449 t4_free_mem(adapter->tids.tid_tab);
6450 disable_msi(adapter);
6451
6452 for_each_port(adapter, i)
671b0060
DM		 6453 if (adapter->port[i]) {
6454 kfree(adap2pinfo(adapter, i)->rss);
06546391 6455 free_netdev(adapter->port[i]);
671b0060 6456 }
06546391 6457 if (adapter->flags & FW_OK)
060e0c75 6458 t4_fw_bye(adapter, adapter->fn);
06546391
DM		 6459}
6460
2ed28baa 6461#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 6462#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 6463 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 6464#define SEGMENT_SIZE 128
b8ff05a9 6465
1dd06ae8 6466static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 6467{
22adfe0a 6468 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 6469 struct port_info *pi;
c8f44aff 6470 bool highdma = false;
b8ff05a9
DM		 6471 struct adapter *adapter = NULL;
6472
6473 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6474
6475 err = pci_request_regions(pdev, KBUILD_MODNAME);
6476 if (err) {
6477 /* Just info, some other driver may have claimed the device. */
6478 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6479 return err;
6480 }
6481
b8ff05a9
DM		 6482 err = pci_enable_device(pdev);
6483 if (err) {
6484 dev_err(&pdev->dev, "cannot enable PCI device\n");
6485 goto out_release_regions;
6486 }
6487
6488 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 6489 highdma = true;
b8ff05a9
DM		 6490 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6491 if (err) {
6492 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6493 "coherent allocations\n");
6494 goto out_disable_device;
6495 }
6496 } else {
6497 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6498 if (err) {
6499 dev_err(&pdev->dev, "no usable DMA configuration\n");
6500 goto out_disable_device;
6501 }
6502 }
6503
6504 pci_enable_pcie_error_reporting(pdev);
ef306b50 6505 enable_pcie_relaxed_ordering(pdev);
b8ff05a9
DM		 6506 pci_set_master(pdev);
6507 pci_save_state(pdev);
6508
6509 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6510 if (!adapter) {
6511 err = -ENOMEM;
6512 goto out_disable_device;
6513 }
6514
144be3d9
GS		 6515 /* PCI device has been enabled */
6516 adapter->flags |= DEV_ENABLED;
6517
b8ff05a9
DM		 6518 adapter->regs = pci_ioremap_bar(pdev, 0);
6519 if (!adapter->regs) {
6520 dev_err(&pdev->dev, "cannot map device registers\n");
6521 err = -ENOMEM;
6522 goto out_free_adapter;
6523 }
6524
35b1de55
HS		 6525 /* We control everything through one PF */
6526 func = SOURCEPF_GET(readl(adapter->regs + PL_WHOAMI));
6527 if ((pdev->device == 0xa000 && func != 0) ||
6528 func != ent->driver_data) {
6529 pci_save_state(pdev); /* to restore SR-IOV later */
6530 err = 0;
6531 goto out_unmap_bar0;
6532 }
6533
b8ff05a9
DM		 6534 adapter->pdev = pdev;
6535 adapter->pdev_dev = &pdev->dev;
3069ee9b 6536 adapter->mbox = func;
060e0c75 6537 adapter->fn = func;
b8ff05a9
DM		 6538 adapter->msg_enable = dflt_msg_enable;
6539 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6540
6541 spin_lock_init(&adapter->stats_lock);
6542 spin_lock_init(&adapter->tid_release_lock);
6543
6544 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 6545 INIT_WORK(&adapter->db_full_task, process_db_full);
6546 INIT_WORK(&adapter->db_drop_task, process_db_drop);
b8ff05a9
DM		 6547
6548 err = t4_prep_adapter(adapter);
6549 if (err)
22adfe0a
SR		 6550 goto out_unmap_bar0;
6551
d14807dd 6552 if (!is_t4(adapter->params.chip)) {
22adfe0a
SR		 6553 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6554 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6555 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6556 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6557
6558 /* Each segment size is 128B. Write coalescing is enabled only
6559 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6560 * queue is less no of segments that can be accommodated in
6561 * a page size.
6562 */
6563 if (qpp > num_seg) {
6564 dev_err(&pdev->dev,
6565 "Incorrect number of egress queues per page\n");
6566 err = -EINVAL;
6567 goto out_unmap_bar0;
6568 }
6569 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6570 pci_resource_len(pdev, 2));
6571 if (!adapter->bar2) {
6572 dev_err(&pdev->dev, "cannot map device bar2 region\n");
6573 err = -ENOMEM;
6574 goto out_unmap_bar0;
6575 }
6576 }
6577
636f9d37 6578 setup_memwin(adapter);
b8ff05a9 6579 err = adap_init0(adapter);
636f9d37 6580 setup_memwin_rdma(adapter);
b8ff05a9
DM		 6581 if (err)
6582 goto out_unmap_bar;
6583
6584 for_each_port(adapter, i) {
6585 struct net_device *netdev;
6586
6587 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6588 MAX_ETH_QSETS);
6589 if (!netdev) {
6590 err = -ENOMEM;
6591 goto out_free_dev;
6592 }
6593
6594 SET_NETDEV_DEV(netdev, &pdev->dev);
6595
6596 adapter->port[i] = netdev;
6597 pi = netdev_priv(netdev);
6598 pi->adapter = adapter;
6599 pi->xact_addr_filt = -1;
b8ff05a9 6600 pi->port_id = i;
b8ff05a9
DM		 6601 netdev->irq = pdev->irq;
6602
2ed28baa
MM		 6603 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6604 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6605 NETIF_F_RXCSUM | NETIF_F_RXHASH |
f646968f 6606 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c8f44aff
MM		 6607 if (highdma)
6608 netdev->hw_features |= NETIF_F_HIGHDMA;
6609 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 6610 netdev->vlan_features = netdev->features & VLAN_FEAT;
6611
01789349
JP		 6612 netdev->priv_flags |= IFF_UNICAST_FLT;
6613
b8ff05a9 6614 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 6615#ifdef CONFIG_CHELSIO_T4_DCB
6616 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6617 cxgb4_dcb_state_init(netdev);
6618#endif
7ad24ea4 6619 netdev->ethtool_ops = &cxgb_ethtool_ops;
b8ff05a9
DM		 6620 }
6621
6622 pci_set_drvdata(pdev, adapter);
6623
6624 if (adapter->flags & FW_OK) {
060e0c75 6625 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 6626 if (err)
6627 goto out_free_dev;
6628 }
6629
6630 /*
6631 * Configure queues and allocate tables now, they can be needed as
6632 * soon as the first register_netdev completes.
6633 */
6634 cfg_queues(adapter);
6635
6636 adapter->l2t = t4_init_l2t();
6637 if (!adapter->l2t) {
6638 /* We tolerate a lack of L2T, giving up some functionality */
6639 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6640 adapter->params.offload = 0;
6641 }
6642
6643 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6644 dev_warn(&pdev->dev, "could not allocate TID table, "
6645 "continuing\n");
6646 adapter->params.offload = 0;
6647 }
6648
f7cabcdd
DM		 6649 /* See what interrupts we'll be using */
6650 if (msi > 1 && enable_msix(adapter) == 0)
6651 adapter->flags |= USING_MSIX;
6652 else if (msi > 0 && pci_enable_msi(pdev) == 0)
6653 adapter->flags |= USING_MSI;
6654
671b0060
DM		 6655 err = init_rss(adapter);
6656 if (err)
6657 goto out_free_dev;
6658
b8ff05a9
DM		 6659 /*
6660 * The card is now ready to go. If any errors occur during device
6661 * registration we do not fail the whole card but rather proceed only
6662 * with the ports we manage to register successfully. However we must
6663 * register at least one net device.
6664 */
6665 for_each_port(adapter, i) {
a57cabe0
DM		 6666 pi = adap2pinfo(adapter, i);
6667 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6668 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6669
b8ff05a9
DM		 6670 err = register_netdev(adapter->port[i]);
6671 if (err)
b1a3c2b6 6672 break;
b1a3c2b6
DM		 6673 adapter->chan_map[pi->tx_chan] = i;
6674 print_port_info(adapter->port[i]);
b8ff05a9 6675 }
b1a3c2b6 6676 if (i == 0) {
b8ff05a9
DM		 6677 dev_err(&pdev->dev, "could not register any net devices\n");
6678 goto out_free_dev;
6679 }
b1a3c2b6
DM		 6680 if (err) {
6681 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6682 err = 0;
6403eab1 6683 }
b8ff05a9
DM		 6684
6685 if (cxgb4_debugfs_root) {
6686 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6687 cxgb4_debugfs_root);
6688 setup_debugfs(adapter);
6689 }
6690
6482aa7c
DLR		 6691 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6692 pdev->needs_freset = 1;
6693
b8ff05a9
DM		 6694 if (is_offload(adapter))
6695 attach_ulds(adapter);
6696
b8ff05a9 6697#ifdef CONFIG_PCI_IOV
7d6727cf 6698 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
b8ff05a9
DM		 6699 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6700 dev_info(&pdev->dev,
6701 "instantiated %u virtual functions\n",
6702 num_vf[func]);
6703#endif
6704 return 0;
6705
6706 out_free_dev:
06546391 6707 free_some_resources(adapter);
b8ff05a9 6708 out_unmap_bar:
d14807dd 6709 if (!is_t4(adapter->params.chip))
22adfe0a
SR		 6710 iounmap(adapter->bar2);
6711 out_unmap_bar0:
b8ff05a9
DM		 6712 iounmap(adapter->regs);
6713 out_free_adapter:
6714 kfree(adapter);
6715 out_disable_device:
6716 pci_disable_pcie_error_reporting(pdev);
6717 pci_disable_device(pdev);
6718 out_release_regions:
6719 pci_release_regions(pdev);
b8ff05a9
DM		 6720 return err;
6721}
6722
91744948 6723static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 6724{
6725 struct adapter *adapter = pci_get_drvdata(pdev);
6726
636f9d37 6727#ifdef CONFIG_PCI_IOV
b8ff05a9
DM		 6728 pci_disable_sriov(pdev);
6729
636f9d37
VP		 6730#endif
6731
b8ff05a9
DM		 6732 if (adapter) {
6733 int i;
6734
6735 if (is_offload(adapter))
6736 detach_ulds(adapter);
6737
6738 for_each_port(adapter, i)
8f3a7676 6739 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 6740 unregister_netdev(adapter->port[i]);
6741
9f16dc2e 6742 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 6743
f2b7e78d
VP		 6744 /* If we allocated filters, free up state associated with any
6745 * valid filters ...
6746 */
6747 if (adapter->tids.ftid_tab) {
6748 struct filter_entry *f = &adapter->tids.ftid_tab[0];
dca4faeb
VP		 6749 for (i = 0; i < (adapter->tids.nftids +
6750 adapter->tids.nsftids); i++, f++)
f2b7e78d
VP		 6751 if (f->valid)
6752 clear_filter(adapter, f);
6753 }
6754
aaefae9b
DM		 6755 if (adapter->flags & FULL_INIT_DONE)
6756 cxgb_down(adapter);
b8ff05a9 6757
06546391 6758 free_some_resources(adapter);
b8ff05a9 6759 iounmap(adapter->regs);
d14807dd 6760 if (!is_t4(adapter->params.chip))
22adfe0a 6761 iounmap(adapter->bar2);
b8ff05a9 6762 pci_disable_pcie_error_reporting(pdev);
144be3d9
GS		 6763 if ((adapter->flags & DEV_ENABLED)) {
6764 pci_disable_device(pdev);
6765 adapter->flags &= ~DEV_ENABLED;
6766 }
b8ff05a9 6767 pci_release_regions(pdev);
ee9a33b2 6768 synchronize_rcu();
8b662fe7 6769 kfree(adapter);
a069ec91 6770 } else
b8ff05a9
DM		 6771 pci_release_regions(pdev);
6772}
6773
6774static struct pci_driver cxgb4_driver = {
6775 .name = KBUILD_MODNAME,
6776 .id_table = cxgb4_pci_tbl,
6777 .probe = init_one,
91744948 6778 .remove = remove_one,
687d705c 6779 .shutdown = remove_one,
204dc3c0 6780 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 6781};
6782
6783static int __init cxgb4_init_module(void)
6784{
6785 int ret;
6786
3069ee9b
VP		 6787 workq = create_singlethread_workqueue("cxgb4");
6788 if (!workq)
6789 return -ENOMEM;
6790
b8ff05a9
DM		 6791 /* Debugfs support is optional, just warn if this fails */
6792 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6793 if (!cxgb4_debugfs_root)
428ac43f 6794 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 6795
6796 ret = pci_register_driver(&cxgb4_driver);
73a695f8 6797 if (ret < 0) {
b8ff05a9 6798 debugfs_remove(cxgb4_debugfs_root);
73a695f8
WY		 6799 destroy_workqueue(workq);
6800 }
01bcca68
VP		 6801
6802 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6803
b8ff05a9
DM		 6804 return ret;
6805}
6806
6807static void __exit cxgb4_cleanup_module(void)
6808{
01bcca68 6809 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
b8ff05a9
DM		 6810 pci_unregister_driver(&cxgb4_driver);
6811 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
3069ee9b
VP		 6812 flush_workqueue(workq);
6813 destroy_workqueue(workq);
b8ff05a9
DM		 6814}
6815
6816module_init(cxgb4_init_module);
6817module_exit(cxgb4_cleanup_module);
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