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cxgb4/iw_cxgb4: use firmware ord/ird resource limits
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
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1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
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5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
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45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
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64#include <asm/uaccess.h>
65
66#include "cxgb4.h"
67#include "t4_regs.h"
68#include "t4_msg.h"
69#include "t4fw_api.h"
688848b1 70#include "cxgb4_dcb.h"
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71#include "l2t.h"
72
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73#include <../drivers/net/bonding/bonding.h>
74
75#ifdef DRV_VERSION
76#undef DRV_VERSION
77#endif
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78#define DRV_VERSION "2.0.0-ko"
79#define DRV_DESC "Chelsio T4/T5 Network Driver"
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80
81/*
82 * Max interrupt hold-off timer value in us. Queues fall back to this value
83 * under extreme memory pressure so it's largish to give the system time to
84 * recover.
85 */
86#define MAX_SGE_TIMERVAL 200U
87
7ee9ff94 88enum {
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89 /*
90 * Physical Function provisioning constants.
91 */
92 PFRES_NVI = 4, /* # of Virtual Interfaces */
93 PFRES_NETHCTRL = 128, /* # of EQs used for ETH or CTRL Qs */
94 PFRES_NIQFLINT = 128, /* # of ingress Qs/w Free List(s)/intr
95 */
96 PFRES_NEQ = 256, /* # of egress queues */
97 PFRES_NIQ = 0, /* # of ingress queues */
98 PFRES_TC = 0, /* PCI-E traffic class */
99 PFRES_NEXACTF = 128, /* # of exact MPS filters */
100
101 PFRES_R_CAPS = FW_CMD_CAP_PF,
102 PFRES_WX_CAPS = FW_CMD_CAP_PF,
103
104#ifdef CONFIG_PCI_IOV
105 /*
106 * Virtual Function provisioning constants. We need two extra Ingress
107 * Queues with Interrupt capability to serve as the VF's Firmware
108 * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
109 * neither will have Free Lists associated with them). For each
110 * Ethernet/Control Egress Queue and for each Free List, we need an
111 * Egress Context.
112 */
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113 VFRES_NPORTS = 1, /* # of "ports" per VF */
114 VFRES_NQSETS = 2, /* # of "Queue Sets" per VF */
115
116 VFRES_NVI = VFRES_NPORTS, /* # of Virtual Interfaces */
117 VFRES_NETHCTRL = VFRES_NQSETS, /* # of EQs used for ETH or CTRL Qs */
118 VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
7ee9ff94 119 VFRES_NEQ = VFRES_NQSETS*2, /* # of egress queues */
13ee15d3 120 VFRES_NIQ = 0, /* # of non-fl/int ingress queues */
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121 VFRES_TC = 0, /* PCI-E traffic class */
122 VFRES_NEXACTF = 16, /* # of exact MPS filters */
123
124 VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
125 VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
13ee15d3 126#endif
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127};
128
129/*
130 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
131 * static and likely not to be useful in the long run. We really need to
132 * implement some form of persistent configuration which the firmware
133 * controls.
134 */
135static unsigned int pfvfres_pmask(struct adapter *adapter,
136 unsigned int pf, unsigned int vf)
137{
138 unsigned int portn, portvec;
139
140 /*
141 * Give PF's access to all of the ports.
142 */
143 if (vf == 0)
144 return FW_PFVF_CMD_PMASK_MASK;
145
146 /*
147 * For VFs, we'll assign them access to the ports based purely on the
148 * PF. We assign active ports in order, wrapping around if there are
149 * fewer active ports than PFs: e.g. active port[pf % nports].
150 * Unfortunately the adapter's port_info structs haven't been
151 * initialized yet so we have to compute this.
152 */
153 if (adapter->params.nports == 0)
154 return 0;
155
156 portn = pf % adapter->params.nports;
157 portvec = adapter->params.portvec;
158 for (;;) {
159 /*
160 * Isolate the lowest set bit in the port vector. If we're at
161 * the port number that we want, return that as the pmask.
162 * otherwise mask that bit out of the port vector and
163 * decrement our port number ...
164 */
165 unsigned int pmask = portvec ^ (portvec & (portvec-1));
166 if (portn == 0)
167 return pmask;
168 portn--;
169 portvec &= ~pmask;
170 }
171 /*NOTREACHED*/
172}
7ee9ff94 173
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174enum {
175 MAX_TXQ_ENTRIES = 16384,
176 MAX_CTRL_TXQ_ENTRIES = 1024,
177 MAX_RSPQ_ENTRIES = 16384,
178 MAX_RX_BUFFERS = 16384,
179 MIN_TXQ_ENTRIES = 32,
180 MIN_CTRL_TXQ_ENTRIES = 32,
181 MIN_RSPQ_ENTRIES = 128,
182 MIN_FL_ENTRIES = 16
183};
184
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185/* Host shadow copy of ingress filter entry. This is in host native format
186 * and doesn't match the ordering or bit order, etc. of the hardware of the
187 * firmware command. The use of bit-field structure elements is purely to
188 * remind ourselves of the field size limitations and save memory in the case
189 * where the filter table is large.
190 */
191struct filter_entry {
192 /* Administrative fields for filter.
193 */
194 u32 valid:1; /* filter allocated and valid */
195 u32 locked:1; /* filter is administratively locked */
196
197 u32 pending:1; /* filter action is pending firmware reply */
198 u32 smtidx:8; /* Source MAC Table index for smac */
199 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
200
201 /* The filter itself. Most of this is a straight copy of information
202 * provided by the extended ioctl(). Some fields are translated to
203 * internal forms -- for instance the Ingress Queue ID passed in from
204 * the ioctl() is translated into the Absolute Ingress Queue ID.
205 */
206 struct ch_filter_specification fs;
207};
208
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209#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
210 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
211 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
212
060e0c75 213#define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
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214
215static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
060e0c75 216 CH_DEVICE(0xa000, 0), /* PE10K */
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217 CH_DEVICE(0x4001, -1),
218 CH_DEVICE(0x4002, -1),
219 CH_DEVICE(0x4003, -1),
220 CH_DEVICE(0x4004, -1),
221 CH_DEVICE(0x4005, -1),
222 CH_DEVICE(0x4006, -1),
223 CH_DEVICE(0x4007, -1),
224 CH_DEVICE(0x4008, -1),
225 CH_DEVICE(0x4009, -1),
226 CH_DEVICE(0x400a, -1),
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227 CH_DEVICE(0x400d, -1),
228 CH_DEVICE(0x400e, -1),
229 CH_DEVICE(0x4080, -1),
230 CH_DEVICE(0x4081, -1),
231 CH_DEVICE(0x4082, -1),
232 CH_DEVICE(0x4083, -1),
233 CH_DEVICE(0x4084, -1),
234 CH_DEVICE(0x4085, -1),
235 CH_DEVICE(0x4086, -1),
236 CH_DEVICE(0x4087, -1),
237 CH_DEVICE(0x4088, -1),
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238 CH_DEVICE(0x4401, 4),
239 CH_DEVICE(0x4402, 4),
240 CH_DEVICE(0x4403, 4),
241 CH_DEVICE(0x4404, 4),
242 CH_DEVICE(0x4405, 4),
243 CH_DEVICE(0x4406, 4),
244 CH_DEVICE(0x4407, 4),
245 CH_DEVICE(0x4408, 4),
246 CH_DEVICE(0x4409, 4),
247 CH_DEVICE(0x440a, 4),
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248 CH_DEVICE(0x440d, 4),
249 CH_DEVICE(0x440e, 4),
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250 CH_DEVICE(0x4480, 4),
251 CH_DEVICE(0x4481, 4),
252 CH_DEVICE(0x4482, 4),
253 CH_DEVICE(0x4483, 4),
254 CH_DEVICE(0x4484, 4),
255 CH_DEVICE(0x4485, 4),
256 CH_DEVICE(0x4486, 4),
257 CH_DEVICE(0x4487, 4),
258 CH_DEVICE(0x4488, 4),
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259 CH_DEVICE(0x5001, 4),
260 CH_DEVICE(0x5002, 4),
261 CH_DEVICE(0x5003, 4),
262 CH_DEVICE(0x5004, 4),
263 CH_DEVICE(0x5005, 4),
264 CH_DEVICE(0x5006, 4),
265 CH_DEVICE(0x5007, 4),
266 CH_DEVICE(0x5008, 4),
267 CH_DEVICE(0x5009, 4),
268 CH_DEVICE(0x500A, 4),
269 CH_DEVICE(0x500B, 4),
270 CH_DEVICE(0x500C, 4),
271 CH_DEVICE(0x500D, 4),
272 CH_DEVICE(0x500E, 4),
273 CH_DEVICE(0x500F, 4),
274 CH_DEVICE(0x5010, 4),
275 CH_DEVICE(0x5011, 4),
276 CH_DEVICE(0x5012, 4),
277 CH_DEVICE(0x5013, 4),
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278 CH_DEVICE(0x5014, 4),
279 CH_DEVICE(0x5015, 4),
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280 CH_DEVICE(0x5080, 4),
281 CH_DEVICE(0x5081, 4),
282 CH_DEVICE(0x5082, 4),
283 CH_DEVICE(0x5083, 4),
284 CH_DEVICE(0x5084, 4),
285 CH_DEVICE(0x5085, 4),
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286 CH_DEVICE(0x5401, 4),
287 CH_DEVICE(0x5402, 4),
288 CH_DEVICE(0x5403, 4),
289 CH_DEVICE(0x5404, 4),
290 CH_DEVICE(0x5405, 4),
291 CH_DEVICE(0x5406, 4),
292 CH_DEVICE(0x5407, 4),
293 CH_DEVICE(0x5408, 4),
294 CH_DEVICE(0x5409, 4),
295 CH_DEVICE(0x540A, 4),
296 CH_DEVICE(0x540B, 4),
297 CH_DEVICE(0x540C, 4),
298 CH_DEVICE(0x540D, 4),
299 CH_DEVICE(0x540E, 4),
300 CH_DEVICE(0x540F, 4),
301 CH_DEVICE(0x5410, 4),
302 CH_DEVICE(0x5411, 4),
303 CH_DEVICE(0x5412, 4),
304 CH_DEVICE(0x5413, 4),
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305 CH_DEVICE(0x5414, 4),
306 CH_DEVICE(0x5415, 4),
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307 CH_DEVICE(0x5480, 4),
308 CH_DEVICE(0x5481, 4),
309 CH_DEVICE(0x5482, 4),
310 CH_DEVICE(0x5483, 4),
311 CH_DEVICE(0x5484, 4),
312 CH_DEVICE(0x5485, 4),
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313 { 0, }
314};
315
16e47624 316#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 317#define FW5_FNAME "cxgb4/t5fw.bin"
16e47624 318#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 319#define FW5_CFNAME "cxgb4/t5-config.txt"
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320
321MODULE_DESCRIPTION(DRV_DESC);
322MODULE_AUTHOR("Chelsio Communications");
323MODULE_LICENSE("Dual BSD/GPL");
324MODULE_VERSION(DRV_VERSION);
325MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 326MODULE_FIRMWARE(FW4_FNAME);
0a57a536 327MODULE_FIRMWARE(FW5_FNAME);
b8ff05a9 328
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329/*
330 * Normally we're willing to become the firmware's Master PF but will be happy
331 * if another PF has already become the Master and initialized the adapter.
332 * Setting "force_init" will cause this driver to forcibly establish itself as
333 * the Master PF and initialize the adapter.
334 */
335static uint force_init;
336
337module_param(force_init, uint, 0644);
338MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
339
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340/*
341 * Normally if the firmware we connect to has Configuration File support, we
342 * use that and only fall back to the old Driver-based initialization if the
343 * Configuration File fails for some reason. If force_old_init is set, then
344 * we'll always use the old Driver-based initialization sequence.
345 */
346static uint force_old_init;
347
348module_param(force_old_init, uint, 0644);
349MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
350
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351static int dflt_msg_enable = DFLT_MSG_ENABLE;
352
353module_param(dflt_msg_enable, int, 0644);
354MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
355
356/*
357 * The driver uses the best interrupt scheme available on a platform in the
358 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
359 * of these schemes the driver may consider as follows:
360 *
361 * msi = 2: choose from among all three options
362 * msi = 1: only consider MSI and INTx interrupts
363 * msi = 0: force INTx interrupts
364 */
365static int msi = 2;
366
367module_param(msi, int, 0644);
368MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
369
370/*
371 * Queue interrupt hold-off timer values. Queues default to the first of these
372 * upon creation.
373 */
374static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
375
376module_param_array(intr_holdoff, uint, NULL, 0644);
377MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
378 "0..4 in microseconds");
379
380static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
381
382module_param_array(intr_cnt, uint, NULL, 0644);
383MODULE_PARM_DESC(intr_cnt,
384 "thresholds 1..3 for queue interrupt packet counters");
385
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386/*
387 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
388 * offset by 2 bytes in order to have the IP headers line up on 4-byte
389 * boundaries. This is a requirement for many architectures which will throw
390 * a machine check fault if an attempt is made to access one of the 4-byte IP
391 * header fields on a non-4-byte boundary. And it's a major performance issue
392 * even on some architectures which allow it like some implementations of the
393 * x86 ISA. However, some architectures don't mind this and for some very
394 * edge-case performance sensitive applications (like forwarding large volumes
395 * of small packets), setting this DMA offset to 0 will decrease the number of
396 * PCI-E Bus transfers enough to measurably affect performance.
397 */
398static int rx_dma_offset = 2;
399
eb939922 400static bool vf_acls;
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401
402#ifdef CONFIG_PCI_IOV
403module_param(vf_acls, bool, 0644);
404MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
405
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SR
406/* Configure the number of PCI-E Virtual Function which are to be instantiated
407 * on SR-IOV Capable Physical Functions.
0a57a536 408 */
7d6727cf 409static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
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410
411module_param_array(num_vf, uint, NULL, 0644);
7d6727cf 412MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
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413#endif
414
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415/* TX Queue select used to determine what algorithm to use for selecting TX
416 * queue. Select between the kernel provided function (select_queue=0) or user
417 * cxgb_select_queue function (select_queue=1)
418 *
419 * Default: select_queue=0
420 */
421static int select_queue;
422module_param(select_queue, int, 0644);
423MODULE_PARM_DESC(select_queue,
424 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
425
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426/*
427 * The filter TCAM has a fixed portion and a variable portion. The fixed
428 * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
429 * ports. The variable portion is 36 bits which can include things like Exact
430 * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
431 * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
432 * far exceed the 36-bit budget for this "compressed" header portion of the
433 * filter. Thus, we have a scarce resource which must be carefully managed.
434 *
435 * By default we set this up to mostly match the set of filter matching
436 * capabilities of T3 but with accommodations for some of T4's more
437 * interesting features:
438 *
439 * { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
440 * [Inner] VLAN (17), Port (3), FCoE (1) }
441 */
442enum {
443 TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
444 TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
445 TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
446};
447
448static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
449
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450module_param(tp_vlan_pri_map, uint, 0644);
451MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
452
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453static struct dentry *cxgb4_debugfs_root;
454
455static LIST_HEAD(adapter_list);
456static DEFINE_MUTEX(uld_mutex);
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457/* Adapter list to be accessed from atomic context */
458static LIST_HEAD(adap_rcu_list);
459static DEFINE_SPINLOCK(adap_rcu_lock);
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460static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
461static const char *uld_str[] = { "RDMA", "iSCSI" };
462
463static void link_report(struct net_device *dev)
464{
465 if (!netif_carrier_ok(dev))
466 netdev_info(dev, "link down\n");
467 else {
468 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
469
470 const char *s = "10Mbps";
471 const struct port_info *p = netdev_priv(dev);
472
473 switch (p->link_cfg.speed) {
e8b39015 474 case 10000:
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475 s = "10Gbps";
476 break;
e8b39015 477 case 1000:
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478 s = "1000Mbps";
479 break;
e8b39015 480 case 100:
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481 s = "100Mbps";
482 break;
e8b39015 483 case 40000:
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484 s = "40Gbps";
485 break;
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486 }
487
488 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
489 fc[p->link_cfg.fc]);
490 }
491}
492
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493#ifdef CONFIG_CHELSIO_T4_DCB
494/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
495static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
496{
497 struct port_info *pi = netdev_priv(dev);
498 struct adapter *adap = pi->adapter;
499 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
500 int i;
501
502 /* We use a simple mapping of Port TX Queue Index to DCB
503 * Priority when we're enabling DCB.
504 */
505 for (i = 0; i < pi->nqsets; i++, txq++) {
506 u32 name, value;
507 int err;
508
509 name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
510 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
511 FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
512 value = enable ? i : 0xffffffff;
513
514 /* Since we can be called while atomic (from "interrupt
515 * level") we need to issue the Set Parameters Commannd
516 * without sleeping (timeout < 0).
517 */
518 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
519 &name, &value);
520
521 if (err)
522 dev_err(adap->pdev_dev,
523 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
524 enable ? "set" : "unset", pi->port_id, i, -err);
525 }
526}
527#endif /* CONFIG_CHELSIO_T4_DCB */
528
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529void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
530{
531 struct net_device *dev = adapter->port[port_id];
532
533 /* Skip changes from disabled ports. */
534 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
535 if (link_stat)
536 netif_carrier_on(dev);
688848b1
AB
537 else {
538#ifdef CONFIG_CHELSIO_T4_DCB
539 cxgb4_dcb_state_init(dev);
540 dcb_tx_queue_prio_enable(dev, false);
541#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 542 netif_carrier_off(dev);
688848b1 543 }
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544
545 link_report(dev);
546 }
547}
548
549void t4_os_portmod_changed(const struct adapter *adap, int port_id)
550{
551 static const char *mod_str[] = {
a0881cab 552 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
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553 };
554
555 const struct net_device *dev = adap->port[port_id];
556 const struct port_info *pi = netdev_priv(dev);
557
558 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
559 netdev_info(dev, "port module unplugged\n");
a0881cab 560 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9
DM
561 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
562}
563
564/*
565 * Configure the exact and hash address filters to handle a port's multicast
566 * and secondary unicast MAC addresses.
567 */
568static int set_addr_filters(const struct net_device *dev, bool sleep)
569{
570 u64 mhash = 0;
571 u64 uhash = 0;
572 bool free = true;
573 u16 filt_idx[7];
574 const u8 *addr[7];
575 int ret, naddr = 0;
b8ff05a9
DM
576 const struct netdev_hw_addr *ha;
577 int uc_cnt = netdev_uc_count(dev);
4a35ecf8 578 int mc_cnt = netdev_mc_count(dev);
b8ff05a9 579 const struct port_info *pi = netdev_priv(dev);
060e0c75 580 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM
581
582 /* first do the secondary unicast addresses */
583 netdev_for_each_uc_addr(ha, dev) {
584 addr[naddr++] = ha->addr;
585 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 586 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM
587 naddr, addr, filt_idx, &uhash, sleep);
588 if (ret < 0)
589 return ret;
590
591 free = false;
592 naddr = 0;
593 }
594 }
595
596 /* next set up the multicast addresses */
4a35ecf8
DM
597 netdev_for_each_mc_addr(ha, dev) {
598 addr[naddr++] = ha->addr;
599 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
060e0c75 600 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
b8ff05a9
DM
601 naddr, addr, filt_idx, &mhash, sleep);
602 if (ret < 0)
603 return ret;
604
605 free = false;
606 naddr = 0;
607 }
608 }
609
060e0c75 610 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
b8ff05a9
DM
611 uhash | mhash, sleep);
612}
613
3069ee9b
VP
614int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
615module_param(dbfifo_int_thresh, int, 0644);
616MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
617
404d9e3f
VP
618/*
619 * usecs to sleep while draining the dbfifo
620 */
621static int dbfifo_drain_delay = 1000;
3069ee9b
VP
622module_param(dbfifo_drain_delay, int, 0644);
623MODULE_PARM_DESC(dbfifo_drain_delay,
624 "usecs to sleep while draining the dbfifo");
625
b8ff05a9
DM
626/*
627 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
628 * If @mtu is -1 it is left unchanged.
629 */
630static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
631{
632 int ret;
633 struct port_info *pi = netdev_priv(dev);
634
635 ret = set_addr_filters(dev, sleep_ok);
636 if (ret == 0)
060e0c75 637 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
b8ff05a9 638 (dev->flags & IFF_PROMISC) ? 1 : 0,
f8f5aafa 639 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
b8ff05a9
DM
640 sleep_ok);
641 return ret;
642}
643
3069ee9b
VP
644static struct workqueue_struct *workq;
645
b8ff05a9
DM
646/**
647 * link_start - enable a port
648 * @dev: the port to enable
649 *
650 * Performs the MAC and PHY actions needed to enable a port.
651 */
652static int link_start(struct net_device *dev)
653{
654 int ret;
655 struct port_info *pi = netdev_priv(dev);
060e0c75 656 unsigned int mb = pi->adapter->fn;
b8ff05a9
DM
657
658 /*
659 * We do not set address filters and promiscuity here, the stack does
660 * that step explicitly.
661 */
060e0c75 662 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 663 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 664 if (ret == 0) {
060e0c75 665 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 666 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 667 true);
b8ff05a9
DM
668 if (ret >= 0) {
669 pi->xact_addr_filt = ret;
670 ret = 0;
671 }
672 }
673 if (ret == 0)
060e0c75
DM
674 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
675 &pi->link_cfg);
b8ff05a9 676 if (ret == 0)
688848b1
AB
677 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
678 true, CXGB4_DCB_ENABLED);
679
b8ff05a9
DM
680 return ret;
681}
682
688848b1
AB
683int cxgb4_dcb_enabled(const struct net_device *dev)
684{
685#ifdef CONFIG_CHELSIO_T4_DCB
686 struct port_info *pi = netdev_priv(dev);
687
688 return pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED;
689#else
690 return 0;
691#endif
692}
693EXPORT_SYMBOL(cxgb4_dcb_enabled);
694
695#ifdef CONFIG_CHELSIO_T4_DCB
696/* Handle a Data Center Bridging update message from the firmware. */
697static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
698{
699 int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
700 struct net_device *dev = adap->port[port];
701 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
702 int new_dcb_enabled;
703
704 cxgb4_dcb_handle_fw_update(adap, pcmd);
705 new_dcb_enabled = cxgb4_dcb_enabled(dev);
706
707 /* If the DCB has become enabled or disabled on the port then we're
708 * going to need to set up/tear down DCB Priority parameters for the
709 * TX Queues associated with the port.
710 */
711 if (new_dcb_enabled != old_dcb_enabled)
712 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
713}
714#endif /* CONFIG_CHELSIO_T4_DCB */
715
f2b7e78d
VP
716/* Clear a filter and release any of its resources that we own. This also
717 * clears the filter's "pending" status.
718 */
719static void clear_filter(struct adapter *adap, struct filter_entry *f)
720{
721 /* If the new or old filter have loopback rewriteing rules then we'll
722 * need to free any existing Layer Two Table (L2T) entries of the old
723 * filter rule. The firmware will handle freeing up any Source MAC
724 * Table (SMT) entries used for rewriting Source MAC Addresses in
725 * loopback rules.
726 */
727 if (f->l2t)
728 cxgb4_l2t_release(f->l2t);
729
730 /* The zeroing of the filter rule below clears the filter valid,
731 * pending, locked flags, l2t pointer, etc. so it's all we need for
732 * this operation.
733 */
734 memset(f, 0, sizeof(*f));
735}
736
737/* Handle a filter write/deletion reply.
738 */
739static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
740{
741 unsigned int idx = GET_TID(rpl);
742 unsigned int nidx = idx - adap->tids.ftid_base;
743 unsigned int ret;
744 struct filter_entry *f;
745
746 if (idx >= adap->tids.ftid_base && nidx <
747 (adap->tids.nftids + adap->tids.nsftids)) {
748 idx = nidx;
749 ret = GET_TCB_COOKIE(rpl->cookie);
750 f = &adap->tids.ftid_tab[idx];
751
752 if (ret == FW_FILTER_WR_FLT_DELETED) {
753 /* Clear the filter when we get confirmation from the
754 * hardware that the filter has been deleted.
755 */
756 clear_filter(adap, f);
757 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
758 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
759 idx);
760 clear_filter(adap, f);
761 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
762 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
763 f->pending = 0; /* asynchronous setup completed */
764 f->valid = 1;
765 } else {
766 /* Something went wrong. Issue a warning about the
767 * problem and clear everything out.
768 */
769 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
770 idx, ret);
771 clear_filter(adap, f);
772 }
773 }
774}
775
776/* Response queue handler for the FW event queue.
b8ff05a9
DM
777 */
778static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
779 const struct pkt_gl *gl)
780{
781 u8 opcode = ((const struct rss_header *)rsp)->opcode;
782
783 rsp++; /* skip RSS header */
b407a4a9
VP
784
785 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
786 */
787 if (unlikely(opcode == CPL_FW4_MSG &&
788 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
789 rsp++;
790 opcode = ((const struct rss_header *)rsp)->opcode;
791 rsp++;
792 if (opcode != CPL_SGE_EGR_UPDATE) {
793 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
794 , opcode);
795 goto out;
796 }
797 }
798
b8ff05a9
DM
799 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
800 const struct cpl_sge_egr_update *p = (void *)rsp;
801 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
e46dab4d 802 struct sge_txq *txq;
b8ff05a9 803
e46dab4d 804 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 805 txq->restarts++;
e46dab4d 806 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
b8ff05a9
DM
807 struct sge_eth_txq *eq;
808
809 eq = container_of(txq, struct sge_eth_txq, q);
810 netif_tx_wake_queue(eq->txq);
811 } else {
812 struct sge_ofld_txq *oq;
813
814 oq = container_of(txq, struct sge_ofld_txq, q);
815 tasklet_schedule(&oq->qresume_tsk);
816 }
817 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
818 const struct cpl_fw6_msg *p = (void *)rsp;
819
688848b1
AB
820#ifdef CONFIG_CHELSIO_T4_DCB
821 const struct fw_port_cmd *pcmd = (const void *)p->data;
822 unsigned int cmd = FW_CMD_OP_GET(ntohl(pcmd->op_to_portid));
823 unsigned int action =
824 FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
825
826 if (cmd == FW_PORT_CMD &&
827 action == FW_PORT_ACTION_GET_PORT_INFO) {
828 int port = FW_PORT_CMD_PORTID_GET(
829 be32_to_cpu(pcmd->op_to_portid));
830 struct net_device *dev = q->adap->port[port];
831 int state_input = ((pcmd->u.info.dcbxdis_pkd &
832 FW_PORT_CMD_DCBXDIS)
833 ? CXGB4_DCB_INPUT_FW_DISABLED
834 : CXGB4_DCB_INPUT_FW_ENABLED);
835
836 cxgb4_dcb_state_fsm(dev, state_input);
837 }
838
839 if (cmd == FW_PORT_CMD &&
840 action == FW_PORT_ACTION_L2_DCB_CFG)
841 dcb_rpl(q->adap, pcmd);
842 else
843#endif
844 if (p->type == 0)
845 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM
846 } else if (opcode == CPL_L2T_WRITE_RPL) {
847 const struct cpl_l2t_write_rpl *p = (void *)rsp;
848
849 do_l2t_write_rpl(q->adap, p);
f2b7e78d
VP
850 } else if (opcode == CPL_SET_TCB_RPL) {
851 const struct cpl_set_tcb_rpl *p = (void *)rsp;
852
853 filter_rpl(q->adap, p);
b8ff05a9
DM
854 } else
855 dev_err(q->adap->pdev_dev,
856 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 857out:
b8ff05a9
DM
858 return 0;
859}
860
861/**
862 * uldrx_handler - response queue handler for ULD queues
863 * @q: the response queue that received the packet
864 * @rsp: the response queue descriptor holding the offload message
865 * @gl: the gather list of packet fragments
866 *
867 * Deliver an ingress offload packet to a ULD. All processing is done by
868 * the ULD, we just maintain statistics.
869 */
870static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
871 const struct pkt_gl *gl)
872{
873 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
874
b407a4a9
VP
875 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
876 */
877 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
878 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
879 rsp += 2;
880
b8ff05a9
DM
881 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
882 rxq->stats.nomem++;
883 return -1;
884 }
885 if (gl == NULL)
886 rxq->stats.imm++;
887 else if (gl == CXGB4_MSG_AN)
888 rxq->stats.an++;
889 else
890 rxq->stats.pkts++;
891 return 0;
892}
893
894static void disable_msi(struct adapter *adapter)
895{
896 if (adapter->flags & USING_MSIX) {
897 pci_disable_msix(adapter->pdev);
898 adapter->flags &= ~USING_MSIX;
899 } else if (adapter->flags & USING_MSI) {
900 pci_disable_msi(adapter->pdev);
901 adapter->flags &= ~USING_MSI;
902 }
903}
904
905/*
906 * Interrupt handler for non-data events used with MSI-X.
907 */
908static irqreturn_t t4_nondata_intr(int irq, void *cookie)
909{
910 struct adapter *adap = cookie;
911
912 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
913 if (v & PFSW) {
914 adap->swintr = 1;
915 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
916 }
917 t4_slow_intr_handler(adap);
918 return IRQ_HANDLED;
919}
920
921/*
922 * Name the MSI-X interrupts.
923 */
924static void name_msix_vecs(struct adapter *adap)
925{
ba27816c 926 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM
927
928 /* non-data interrupts */
b1a3c2b6 929 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM
930
931 /* FW events */
b1a3c2b6
DM
932 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
933 adap->port[0]->name);
b8ff05a9
DM
934
935 /* Ethernet queues */
936 for_each_port(adap, j) {
937 struct net_device *d = adap->port[j];
938 const struct port_info *pi = netdev_priv(d);
939
ba27816c 940 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM
941 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
942 d->name, i);
b8ff05a9
DM
943 }
944
945 /* offload queues */
ba27816c
DM
946 for_each_ofldrxq(&adap->sge, i)
947 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
b1a3c2b6 948 adap->port[0]->name, i);
ba27816c
DM
949
950 for_each_rdmarxq(&adap->sge, i)
951 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
b1a3c2b6 952 adap->port[0]->name, i);
cf38be6d
HS
953
954 for_each_rdmaciq(&adap->sge, i)
955 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
956 adap->port[0]->name, i);
b8ff05a9
DM
957}
958
959static int request_msix_queue_irqs(struct adapter *adap)
960{
961 struct sge *s = &adap->sge;
cf38be6d
HS
962 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
963 int msi_index = 2;
b8ff05a9
DM
964
965 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
966 adap->msix_info[1].desc, &s->fw_evtq);
967 if (err)
968 return err;
969
970 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP
971 err = request_irq(adap->msix_info[msi_index].vec,
972 t4_sge_intr_msix, 0,
973 adap->msix_info[msi_index].desc,
b8ff05a9
DM
974 &s->ethrxq[ethqidx].rspq);
975 if (err)
976 goto unwind;
404d9e3f 977 msi_index++;
b8ff05a9
DM
978 }
979 for_each_ofldrxq(s, ofldqidx) {
404d9e3f
VP
980 err = request_irq(adap->msix_info[msi_index].vec,
981 t4_sge_intr_msix, 0,
982 adap->msix_info[msi_index].desc,
b8ff05a9
DM
983 &s->ofldrxq[ofldqidx].rspq);
984 if (err)
985 goto unwind;
404d9e3f 986 msi_index++;
b8ff05a9
DM
987 }
988 for_each_rdmarxq(s, rdmaqidx) {
404d9e3f
VP
989 err = request_irq(adap->msix_info[msi_index].vec,
990 t4_sge_intr_msix, 0,
991 adap->msix_info[msi_index].desc,
b8ff05a9
DM
992 &s->rdmarxq[rdmaqidx].rspq);
993 if (err)
994 goto unwind;
404d9e3f 995 msi_index++;
b8ff05a9 996 }
cf38be6d
HS
997 for_each_rdmaciq(s, rdmaciqqidx) {
998 err = request_irq(adap->msix_info[msi_index].vec,
999 t4_sge_intr_msix, 0,
1000 adap->msix_info[msi_index].desc,
1001 &s->rdmaciq[rdmaciqqidx].rspq);
1002 if (err)
1003 goto unwind;
1004 msi_index++;
1005 }
b8ff05a9
DM
1006 return 0;
1007
1008unwind:
cf38be6d
HS
1009 while (--rdmaciqqidx >= 0)
1010 free_irq(adap->msix_info[--msi_index].vec,
1011 &s->rdmaciq[rdmaciqqidx].rspq);
b8ff05a9 1012 while (--rdmaqidx >= 0)
404d9e3f 1013 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM
1014 &s->rdmarxq[rdmaqidx].rspq);
1015 while (--ofldqidx >= 0)
404d9e3f 1016 free_irq(adap->msix_info[--msi_index].vec,
b8ff05a9
DM
1017 &s->ofldrxq[ofldqidx].rspq);
1018 while (--ethqidx >= 0)
404d9e3f
VP
1019 free_irq(adap->msix_info[--msi_index].vec,
1020 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM
1021 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1022 return err;
1023}
1024
1025static void free_msix_queue_irqs(struct adapter *adap)
1026{
404d9e3f 1027 int i, msi_index = 2;
b8ff05a9
DM
1028 struct sge *s = &adap->sge;
1029
1030 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1031 for_each_ethrxq(s, i)
404d9e3f 1032 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9 1033 for_each_ofldrxq(s, i)
404d9e3f 1034 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
b8ff05a9 1035 for_each_rdmarxq(s, i)
404d9e3f 1036 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
cf38be6d
HS
1037 for_each_rdmaciq(s, i)
1038 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
b8ff05a9
DM
1039}
1040
671b0060
DM
1041/**
1042 * write_rss - write the RSS table for a given port
1043 * @pi: the port
1044 * @queues: array of queue indices for RSS
1045 *
1046 * Sets up the portion of the HW RSS table for the port's VI to distribute
1047 * packets to the Rx queues in @queues.
1048 */
1049static int write_rss(const struct port_info *pi, const u16 *queues)
1050{
1051 u16 *rss;
1052 int i, err;
1053 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
1054
1055 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
1056 if (!rss)
1057 return -ENOMEM;
1058
1059 /* map the queue indices to queue ids */
1060 for (i = 0; i < pi->rss_size; i++, queues++)
1061 rss[i] = q[*queues].rspq.abs_id;
1062
060e0c75
DM
1063 err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
1064 pi->rss_size, rss, pi->rss_size);
671b0060
DM
1065 kfree(rss);
1066 return err;
1067}
1068
b8ff05a9
DM
1069/**
1070 * setup_rss - configure RSS
1071 * @adap: the adapter
1072 *
671b0060 1073 * Sets up RSS for each port.
b8ff05a9
DM
1074 */
1075static int setup_rss(struct adapter *adap)
1076{
671b0060 1077 int i, err;
b8ff05a9
DM
1078
1079 for_each_port(adap, i) {
1080 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 1081
671b0060 1082 err = write_rss(pi, pi->rss);
b8ff05a9
DM
1083 if (err)
1084 return err;
1085 }
1086 return 0;
1087}
1088
e46dab4d
DM
1089/*
1090 * Return the channel of the ingress queue with the given qid.
1091 */
1092static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1093{
1094 qid -= p->ingr_start;
1095 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1096}
1097
b8ff05a9
DM
1098/*
1099 * Wait until all NAPI handlers are descheduled.
1100 */
1101static void quiesce_rx(struct adapter *adap)
1102{
1103 int i;
1104
1105 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1106 struct sge_rspq *q = adap->sge.ingr_map[i];
1107
1108 if (q && q->handler)
1109 napi_disable(&q->napi);
1110 }
1111}
1112
1113/*
1114 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1115 */
1116static void enable_rx(struct adapter *adap)
1117{
1118 int i;
1119
1120 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1121 struct sge_rspq *q = adap->sge.ingr_map[i];
1122
1123 if (!q)
1124 continue;
1125 if (q->handler)
1126 napi_enable(&q->napi);
1127 /* 0-increment GTS to start the timer and enable interrupts */
1128 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1129 SEINTARM(q->intr_params) |
1130 INGRESSQID(q->cntxt_id));
1131 }
1132}
1133
1134/**
1135 * setup_sge_queues - configure SGE Tx/Rx/response queues
1136 * @adap: the adapter
1137 *
1138 * Determines how many sets of SGE queues to use and initializes them.
1139 * We support multiple queue sets per port if we have MSI-X, otherwise
1140 * just one queue set per port.
1141 */
1142static int setup_sge_queues(struct adapter *adap)
1143{
1144 int err, msi_idx, i, j;
1145 struct sge *s = &adap->sge;
1146
1147 bitmap_zero(s->starving_fl, MAX_EGRQ);
1148 bitmap_zero(s->txq_maperr, MAX_EGRQ);
1149
1150 if (adap->flags & USING_MSIX)
1151 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1152 else {
1153 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1154 NULL, NULL);
1155 if (err)
1156 return err;
1157 msi_idx = -((int)s->intrq.abs_id + 1);
1158 }
1159
1160 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1161 msi_idx, NULL, fwevtq_handler);
1162 if (err) {
1163freeout: t4_free_sge_resources(adap);
1164 return err;
1165 }
1166
1167 for_each_port(adap, i) {
1168 struct net_device *dev = adap->port[i];
1169 struct port_info *pi = netdev_priv(dev);
1170 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1171 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1172
1173 for (j = 0; j < pi->nqsets; j++, q++) {
1174 if (msi_idx > 0)
1175 msi_idx++;
1176 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1177 msi_idx, &q->fl,
1178 t4_ethrx_handler);
1179 if (err)
1180 goto freeout;
1181 q->rspq.idx = j;
1182 memset(&q->stats, 0, sizeof(q->stats));
1183 }
1184 for (j = 0; j < pi->nqsets; j++, t++) {
1185 err = t4_sge_alloc_eth_txq(adap, t, dev,
1186 netdev_get_tx_queue(dev, j),
1187 s->fw_evtq.cntxt_id);
1188 if (err)
1189 goto freeout;
1190 }
1191 }
1192
1193 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1194 for_each_ofldrxq(s, i) {
1195 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1196 struct net_device *dev = adap->port[i / j];
1197
1198 if (msi_idx > 0)
1199 msi_idx++;
1200 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
cf38be6d
HS
1201 q->fl.size ? &q->fl : NULL,
1202 uldrx_handler);
b8ff05a9
DM
1203 if (err)
1204 goto freeout;
1205 memset(&q->stats, 0, sizeof(q->stats));
1206 s->ofld_rxq[i] = q->rspq.abs_id;
1207 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1208 s->fw_evtq.cntxt_id);
1209 if (err)
1210 goto freeout;
1211 }
1212
1213 for_each_rdmarxq(s, i) {
1214 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1215
1216 if (msi_idx > 0)
1217 msi_idx++;
1218 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
cf38be6d
HS
1219 msi_idx, q->fl.size ? &q->fl : NULL,
1220 uldrx_handler);
b8ff05a9
DM
1221 if (err)
1222 goto freeout;
1223 memset(&q->stats, 0, sizeof(q->stats));
1224 s->rdma_rxq[i] = q->rspq.abs_id;
1225 }
1226
cf38be6d
HS
1227 for_each_rdmaciq(s, i) {
1228 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1229
1230 if (msi_idx > 0)
1231 msi_idx++;
1232 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1233 msi_idx, q->fl.size ? &q->fl : NULL,
1234 uldrx_handler);
1235 if (err)
1236 goto freeout;
1237 memset(&q->stats, 0, sizeof(q->stats));
1238 s->rdma_ciq[i] = q->rspq.abs_id;
1239 }
1240
b8ff05a9
DM
1241 for_each_port(adap, i) {
1242 /*
1243 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1244 * have RDMA queues, and that's the right value.
1245 */
1246 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1247 s->fw_evtq.cntxt_id,
1248 s->rdmarxq[i].rspq.cntxt_id);
1249 if (err)
1250 goto freeout;
1251 }
1252
1253 t4_write_reg(adap, MPS_TRC_RSS_CONTROL,
1254 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1255 QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1256 return 0;
1257}
1258
b8ff05a9
DM
1259/*
1260 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1261 * The allocated memory is cleared.
1262 */
1263void *t4_alloc_mem(size_t size)
1264{
8be04b93 1265 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
b8ff05a9
DM
1266
1267 if (!p)
89bf67f1 1268 p = vzalloc(size);
b8ff05a9
DM
1269 return p;
1270}
1271
1272/*
1273 * Free memory allocated through alloc_mem().
1274 */
31b9c19b 1275static void t4_free_mem(void *addr)
b8ff05a9
DM
1276{
1277 if (is_vmalloc_addr(addr))
1278 vfree(addr);
1279 else
1280 kfree(addr);
1281}
1282
f2b7e78d
VP
1283/* Send a Work Request to write the filter at a specified index. We construct
1284 * a Firmware Filter Work Request to have the work done and put the indicated
1285 * filter into "pending" mode which will prevent any further actions against
1286 * it till we get a reply from the firmware on the completion status of the
1287 * request.
1288 */
1289static int set_filter_wr(struct adapter *adapter, int fidx)
1290{
1291 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1292 struct sk_buff *skb;
1293 struct fw_filter_wr *fwr;
1294 unsigned int ftid;
1295
1296 /* If the new filter requires loopback Destination MAC and/or VLAN
1297 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1298 * the filter.
1299 */
1300 if (f->fs.newdmac || f->fs.newvlan) {
1301 /* allocate L2T entry for new filter */
1302 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1303 if (f->l2t == NULL)
1304 return -EAGAIN;
1305 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1306 f->fs.eport, f->fs.dmac)) {
1307 cxgb4_l2t_release(f->l2t);
1308 f->l2t = NULL;
1309 return -ENOMEM;
1310 }
1311 }
1312
1313 ftid = adapter->tids.ftid_base + fidx;
1314
1315 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1316 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1317 memset(fwr, 0, sizeof(*fwr));
1318
1319 /* It would be nice to put most of the following in t4_hw.c but most
1320 * of the work is translating the cxgbtool ch_filter_specification
1321 * into the Work Request and the definition of that structure is
1322 * currently in cxgbtool.h which isn't appropriate to pull into the
1323 * common code. We may eventually try to come up with a more neutral
1324 * filter specification structure but for now it's easiest to simply
1325 * put this fairly direct code in line ...
1326 */
1327 fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1328 fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1329 fwr->tid_to_iq =
1330 htonl(V_FW_FILTER_WR_TID(ftid) |
1331 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1332 V_FW_FILTER_WR_NOREPLY(0) |
1333 V_FW_FILTER_WR_IQ(f->fs.iq));
1334 fwr->del_filter_to_l2tix =
1335 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1336 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1337 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1338 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1339 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1340 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1341 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1342 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1343 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1344 f->fs.newvlan == VLAN_REWRITE) |
1345 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1346 f->fs.newvlan == VLAN_REWRITE) |
1347 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1348 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1349 V_FW_FILTER_WR_PRIO(f->fs.prio) |
1350 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1351 fwr->ethtype = htons(f->fs.val.ethtype);
1352 fwr->ethtypem = htons(f->fs.mask.ethtype);
1353 fwr->frag_to_ovlan_vldm =
1354 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1355 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1356 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1357 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1358 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1359 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1360 fwr->smac_sel = 0;
1361 fwr->rx_chan_rx_rpl_iq =
1362 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1363 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1364 fwr->maci_to_matchtypem =
1365 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1366 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1367 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1368 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1369 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1370 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1371 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1372 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1373 fwr->ptcl = f->fs.val.proto;
1374 fwr->ptclm = f->fs.mask.proto;
1375 fwr->ttyp = f->fs.val.tos;
1376 fwr->ttypm = f->fs.mask.tos;
1377 fwr->ivlan = htons(f->fs.val.ivlan);
1378 fwr->ivlanm = htons(f->fs.mask.ivlan);
1379 fwr->ovlan = htons(f->fs.val.ovlan);
1380 fwr->ovlanm = htons(f->fs.mask.ovlan);
1381 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1382 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1383 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1384 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1385 fwr->lp = htons(f->fs.val.lport);
1386 fwr->lpm = htons(f->fs.mask.lport);
1387 fwr->fp = htons(f->fs.val.fport);
1388 fwr->fpm = htons(f->fs.mask.fport);
1389 if (f->fs.newsmac)
1390 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1391
1392 /* Mark the filter as "pending" and ship off the Filter Work Request.
1393 * When we get the Work Request Reply we'll clear the pending status.
1394 */
1395 f->pending = 1;
1396 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1397 t4_ofld_send(adapter, skb);
1398 return 0;
1399}
1400
1401/* Delete the filter at a specified index.
1402 */
1403static int del_filter_wr(struct adapter *adapter, int fidx)
1404{
1405 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1406 struct sk_buff *skb;
1407 struct fw_filter_wr *fwr;
1408 unsigned int len, ftid;
1409
1410 len = sizeof(*fwr);
1411 ftid = adapter->tids.ftid_base + fidx;
1412
1413 skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1414 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1415 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1416
1417 /* Mark the filter as "pending" and ship off the Filter Work Request.
1418 * When we get the Work Request Reply we'll clear the pending status.
1419 */
1420 f->pending = 1;
1421 t4_mgmt_tx(adapter, skb);
1422 return 0;
1423}
1424
688848b1
AB
1425static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1426 void *accel_priv, select_queue_fallback_t fallback)
1427{
1428 int txq;
1429
1430#ifdef CONFIG_CHELSIO_T4_DCB
1431 /* If a Data Center Bridging has been successfully negotiated on this
1432 * link then we'll use the skb's priority to map it to a TX Queue.
1433 * The skb's priority is determined via the VLAN Tag Priority Code
1434 * Point field.
1435 */
1436 if (cxgb4_dcb_enabled(dev)) {
1437 u16 vlan_tci;
1438 int err;
1439
1440 err = vlan_get_tag(skb, &vlan_tci);
1441 if (unlikely(err)) {
1442 if (net_ratelimit())
1443 netdev_warn(dev,
1444 "TX Packet without VLAN Tag on DCB Link\n");
1445 txq = 0;
1446 } else {
1447 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1448 }
1449 return txq;
1450 }
1451#endif /* CONFIG_CHELSIO_T4_DCB */
1452
1453 if (select_queue) {
1454 txq = (skb_rx_queue_recorded(skb)
1455 ? skb_get_rx_queue(skb)
1456 : smp_processor_id());
1457
1458 while (unlikely(txq >= dev->real_num_tx_queues))
1459 txq -= dev->real_num_tx_queues;
1460
1461 return txq;
1462 }
1463
1464 return fallback(dev, skb) % dev->real_num_tx_queues;
1465}
1466
b8ff05a9
DM
1467static inline int is_offload(const struct adapter *adap)
1468{
1469 return adap->params.offload;
1470}
1471
1472/*
1473 * Implementation of ethtool operations.
1474 */
1475
1476static u32 get_msglevel(struct net_device *dev)
1477{
1478 return netdev2adap(dev)->msg_enable;
1479}
1480
1481static void set_msglevel(struct net_device *dev, u32 val)
1482{
1483 netdev2adap(dev)->msg_enable = val;
1484}
1485
1486static char stats_strings[][ETH_GSTRING_LEN] = {
1487 "TxOctetsOK ",
1488 "TxFramesOK ",
1489 "TxBroadcastFrames ",
1490 "TxMulticastFrames ",
1491 "TxUnicastFrames ",
1492 "TxErrorFrames ",
1493
1494 "TxFrames64 ",
1495 "TxFrames65To127 ",
1496 "TxFrames128To255 ",
1497 "TxFrames256To511 ",
1498 "TxFrames512To1023 ",
1499 "TxFrames1024To1518 ",
1500 "TxFrames1519ToMax ",
1501
1502 "TxFramesDropped ",
1503 "TxPauseFrames ",
1504 "TxPPP0Frames ",
1505 "TxPPP1Frames ",
1506 "TxPPP2Frames ",
1507 "TxPPP3Frames ",
1508 "TxPPP4Frames ",
1509 "TxPPP5Frames ",
1510 "TxPPP6Frames ",
1511 "TxPPP7Frames ",
1512
1513 "RxOctetsOK ",
1514 "RxFramesOK ",
1515 "RxBroadcastFrames ",
1516 "RxMulticastFrames ",
1517 "RxUnicastFrames ",
1518
1519 "RxFramesTooLong ",
1520 "RxJabberErrors ",
1521 "RxFCSErrors ",
1522 "RxLengthErrors ",
1523 "RxSymbolErrors ",
1524 "RxRuntFrames ",
1525
1526 "RxFrames64 ",
1527 "RxFrames65To127 ",
1528 "RxFrames128To255 ",
1529 "RxFrames256To511 ",
1530 "RxFrames512To1023 ",
1531 "RxFrames1024To1518 ",
1532 "RxFrames1519ToMax ",
1533
1534 "RxPauseFrames ",
1535 "RxPPP0Frames ",
1536 "RxPPP1Frames ",
1537 "RxPPP2Frames ",
1538 "RxPPP3Frames ",
1539 "RxPPP4Frames ",
1540 "RxPPP5Frames ",
1541 "RxPPP6Frames ",
1542 "RxPPP7Frames ",
1543
1544 "RxBG0FramesDropped ",
1545 "RxBG1FramesDropped ",
1546 "RxBG2FramesDropped ",
1547 "RxBG3FramesDropped ",
1548 "RxBG0FramesTrunc ",
1549 "RxBG1FramesTrunc ",
1550 "RxBG2FramesTrunc ",
1551 "RxBG3FramesTrunc ",
1552
1553 "TSO ",
1554 "TxCsumOffload ",
1555 "RxCsumGood ",
1556 "VLANextractions ",
1557 "VLANinsertions ",
4a6346d4
DM
1558 "GROpackets ",
1559 "GROmerged ",
22adfe0a
SR
1560 "WriteCoalSuccess ",
1561 "WriteCoalFail ",
b8ff05a9
DM
1562};
1563
1564static int get_sset_count(struct net_device *dev, int sset)
1565{
1566 switch (sset) {
1567 case ETH_SS_STATS:
1568 return ARRAY_SIZE(stats_strings);
1569 default:
1570 return -EOPNOTSUPP;
1571 }
1572}
1573
1574#define T4_REGMAP_SIZE (160 * 1024)
251f9e88 1575#define T5_REGMAP_SIZE (332 * 1024)
b8ff05a9
DM
1576
1577static int get_regs_len(struct net_device *dev)
1578{
251f9e88 1579 struct adapter *adap = netdev2adap(dev);
d14807dd 1580 if (is_t4(adap->params.chip))
251f9e88
SR
1581 return T4_REGMAP_SIZE;
1582 else
1583 return T5_REGMAP_SIZE;
b8ff05a9
DM
1584}
1585
1586static int get_eeprom_len(struct net_device *dev)
1587{
1588 return EEPROMSIZE;
1589}
1590
1591static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1592{
1593 struct adapter *adapter = netdev2adap(dev);
1594
23020ab3
RJ
1595 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1596 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1597 strlcpy(info->bus_info, pci_name(adapter->pdev),
1598 sizeof(info->bus_info));
b8ff05a9 1599
84b40501 1600 if (adapter->params.fw_vers)
b8ff05a9
DM
1601 snprintf(info->fw_version, sizeof(info->fw_version),
1602 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1603 FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1604 FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1605 FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1606 FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1607 FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1608 FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1609 FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1610 FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1611}
1612
1613static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1614{
1615 if (stringset == ETH_SS_STATS)
1616 memcpy(data, stats_strings, sizeof(stats_strings));
1617}
1618
1619/*
1620 * port stats maintained per queue of the port. They should be in the same
1621 * order as in stats_strings above.
1622 */
1623struct queue_port_stats {
1624 u64 tso;
1625 u64 tx_csum;
1626 u64 rx_csum;
1627 u64 vlan_ex;
1628 u64 vlan_ins;
4a6346d4
DM
1629 u64 gro_pkts;
1630 u64 gro_merged;
b8ff05a9
DM
1631};
1632
1633static void collect_sge_port_stats(const struct adapter *adap,
1634 const struct port_info *p, struct queue_port_stats *s)
1635{
1636 int i;
1637 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1638 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1639
1640 memset(s, 0, sizeof(*s));
1641 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1642 s->tso += tx->tso;
1643 s->tx_csum += tx->tx_cso;
1644 s->rx_csum += rx->stats.rx_cso;
1645 s->vlan_ex += rx->stats.vlan_ex;
1646 s->vlan_ins += tx->vlan_ins;
4a6346d4
DM
1647 s->gro_pkts += rx->stats.lro_pkts;
1648 s->gro_merged += rx->stats.lro_merged;
b8ff05a9
DM
1649 }
1650}
1651
1652static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1653 u64 *data)
1654{
1655 struct port_info *pi = netdev_priv(dev);
1656 struct adapter *adapter = pi->adapter;
22adfe0a 1657 u32 val1, val2;
b8ff05a9
DM
1658
1659 t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1660
1661 data += sizeof(struct port_stats) / sizeof(u64);
1662 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
22adfe0a 1663 data += sizeof(struct queue_port_stats) / sizeof(u64);
d14807dd 1664 if (!is_t4(adapter->params.chip)) {
22adfe0a
SR
1665 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1666 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1667 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1668 *data = val1 - val2;
1669 data++;
1670 *data = val2;
1671 data++;
1672 } else {
1673 memset(data, 0, 2 * sizeof(u64));
1674 *data += 2;
1675 }
b8ff05a9
DM
1676}
1677
1678/*
1679 * Return a version number to identify the type of adapter. The scheme is:
1680 * - bits 0..9: chip version
1681 * - bits 10..15: chip revision
835bb606 1682 * - bits 16..23: register dump version
b8ff05a9
DM
1683 */
1684static inline unsigned int mk_adap_vers(const struct adapter *ap)
1685{
d14807dd
HS
1686 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1687 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
b8ff05a9
DM
1688}
1689
1690static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1691 unsigned int end)
1692{
1693 u32 *p = buf + start;
1694
1695 for ( ; start <= end; start += sizeof(u32))
1696 *p++ = t4_read_reg(ap, start);
1697}
1698
1699static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1700 void *buf)
1701{
251f9e88 1702 static const unsigned int t4_reg_ranges[] = {
b8ff05a9
DM
1703 0x1008, 0x1108,
1704 0x1180, 0x11b4,
1705 0x11fc, 0x123c,
1706 0x1300, 0x173c,
1707 0x1800, 0x18fc,
1708 0x3000, 0x30d8,
1709 0x30e0, 0x5924,
1710 0x5960, 0x59d4,
1711 0x5a00, 0x5af8,
1712 0x6000, 0x6098,
1713 0x6100, 0x6150,
1714 0x6200, 0x6208,
1715 0x6240, 0x6248,
1716 0x6280, 0x6338,
1717 0x6370, 0x638c,
1718 0x6400, 0x643c,
1719 0x6500, 0x6524,
1720 0x6a00, 0x6a38,
1721 0x6a60, 0x6a78,
1722 0x6b00, 0x6b84,
1723 0x6bf0, 0x6c84,
1724 0x6cf0, 0x6d84,
1725 0x6df0, 0x6e84,
1726 0x6ef0, 0x6f84,
1727 0x6ff0, 0x7084,
1728 0x70f0, 0x7184,
1729 0x71f0, 0x7284,
1730 0x72f0, 0x7384,
1731 0x73f0, 0x7450,
1732 0x7500, 0x7530,
1733 0x7600, 0x761c,
1734 0x7680, 0x76cc,
1735 0x7700, 0x7798,
1736 0x77c0, 0x77fc,
1737 0x7900, 0x79fc,
1738 0x7b00, 0x7c38,
1739 0x7d00, 0x7efc,
1740 0x8dc0, 0x8e1c,
1741 0x8e30, 0x8e78,
1742 0x8ea0, 0x8f6c,
1743 0x8fc0, 0x9074,
1744 0x90fc, 0x90fc,
1745 0x9400, 0x9458,
1746 0x9600, 0x96bc,
1747 0x9800, 0x9808,
1748 0x9820, 0x983c,
1749 0x9850, 0x9864,
1750 0x9c00, 0x9c6c,
1751 0x9c80, 0x9cec,
1752 0x9d00, 0x9d6c,
1753 0x9d80, 0x9dec,
1754 0x9e00, 0x9e6c,
1755 0x9e80, 0x9eec,
1756 0x9f00, 0x9f6c,
1757 0x9f80, 0x9fec,
1758 0xd004, 0xd03c,
1759 0xdfc0, 0xdfe0,
1760 0xe000, 0xea7c,
1761 0xf000, 0x11190,
835bb606
DM
1762 0x19040, 0x1906c,
1763 0x19078, 0x19080,
1764 0x1908c, 0x19124,
b8ff05a9
DM
1765 0x19150, 0x191b0,
1766 0x191d0, 0x191e8,
1767 0x19238, 0x1924c,
1768 0x193f8, 0x19474,
1769 0x19490, 0x194f8,
1770 0x19800, 0x19f30,
1771 0x1a000, 0x1a06c,
1772 0x1a0b0, 0x1a120,
1773 0x1a128, 0x1a138,
1774 0x1a190, 0x1a1c4,
1775 0x1a1fc, 0x1a1fc,
1776 0x1e040, 0x1e04c,
835bb606 1777 0x1e284, 0x1e28c,
b8ff05a9
DM
1778 0x1e2c0, 0x1e2c0,
1779 0x1e2e0, 0x1e2e0,
1780 0x1e300, 0x1e384,
1781 0x1e3c0, 0x1e3c8,
1782 0x1e440, 0x1e44c,
835bb606 1783 0x1e684, 0x1e68c,
b8ff05a9
DM
1784 0x1e6c0, 0x1e6c0,
1785 0x1e6e0, 0x1e6e0,
1786 0x1e700, 0x1e784,
1787 0x1e7c0, 0x1e7c8,
1788 0x1e840, 0x1e84c,
835bb606 1789 0x1ea84, 0x1ea8c,
b8ff05a9
DM
1790 0x1eac0, 0x1eac0,
1791 0x1eae0, 0x1eae0,
1792 0x1eb00, 0x1eb84,
1793 0x1ebc0, 0x1ebc8,
1794 0x1ec40, 0x1ec4c,
835bb606 1795 0x1ee84, 0x1ee8c,
b8ff05a9
DM
1796 0x1eec0, 0x1eec0,
1797 0x1eee0, 0x1eee0,
1798 0x1ef00, 0x1ef84,
1799 0x1efc0, 0x1efc8,
1800 0x1f040, 0x1f04c,
835bb606 1801 0x1f284, 0x1f28c,
b8ff05a9
DM
1802 0x1f2c0, 0x1f2c0,
1803 0x1f2e0, 0x1f2e0,
1804 0x1f300, 0x1f384,
1805 0x1f3c0, 0x1f3c8,
1806 0x1f440, 0x1f44c,
835bb606 1807 0x1f684, 0x1f68c,
b8ff05a9
DM
1808 0x1f6c0, 0x1f6c0,
1809 0x1f6e0, 0x1f6e0,
1810 0x1f700, 0x1f784,
1811 0x1f7c0, 0x1f7c8,
1812 0x1f840, 0x1f84c,
835bb606 1813 0x1fa84, 0x1fa8c,
b8ff05a9
DM
1814 0x1fac0, 0x1fac0,
1815 0x1fae0, 0x1fae0,
1816 0x1fb00, 0x1fb84,
1817 0x1fbc0, 0x1fbc8,
1818 0x1fc40, 0x1fc4c,
835bb606 1819 0x1fe84, 0x1fe8c,
b8ff05a9
DM
1820 0x1fec0, 0x1fec0,
1821 0x1fee0, 0x1fee0,
1822 0x1ff00, 0x1ff84,
1823 0x1ffc0, 0x1ffc8,
1824 0x20000, 0x2002c,
1825 0x20100, 0x2013c,
1826 0x20190, 0x201c8,
1827 0x20200, 0x20318,
1828 0x20400, 0x20528,
1829 0x20540, 0x20614,
1830 0x21000, 0x21040,
1831 0x2104c, 0x21060,
1832 0x210c0, 0x210ec,
1833 0x21200, 0x21268,
1834 0x21270, 0x21284,
1835 0x212fc, 0x21388,
1836 0x21400, 0x21404,
1837 0x21500, 0x21518,
1838 0x2152c, 0x2153c,
1839 0x21550, 0x21554,
1840 0x21600, 0x21600,
1841 0x21608, 0x21628,
1842 0x21630, 0x2163c,
1843 0x21700, 0x2171c,
1844 0x21780, 0x2178c,
1845 0x21800, 0x21c38,
1846 0x21c80, 0x21d7c,
1847 0x21e00, 0x21e04,
1848 0x22000, 0x2202c,
1849 0x22100, 0x2213c,
1850 0x22190, 0x221c8,
1851 0x22200, 0x22318,
1852 0x22400, 0x22528,
1853 0x22540, 0x22614,
1854 0x23000, 0x23040,
1855 0x2304c, 0x23060,
1856 0x230c0, 0x230ec,
1857 0x23200, 0x23268,
1858 0x23270, 0x23284,
1859 0x232fc, 0x23388,
1860 0x23400, 0x23404,
1861 0x23500, 0x23518,
1862 0x2352c, 0x2353c,
1863 0x23550, 0x23554,
1864 0x23600, 0x23600,
1865 0x23608, 0x23628,
1866 0x23630, 0x2363c,
1867 0x23700, 0x2371c,
1868 0x23780, 0x2378c,
1869 0x23800, 0x23c38,
1870 0x23c80, 0x23d7c,
1871 0x23e00, 0x23e04,
1872 0x24000, 0x2402c,
1873 0x24100, 0x2413c,
1874 0x24190, 0x241c8,
1875 0x24200, 0x24318,
1876 0x24400, 0x24528,
1877 0x24540, 0x24614,
1878 0x25000, 0x25040,
1879 0x2504c, 0x25060,
1880 0x250c0, 0x250ec,
1881 0x25200, 0x25268,
1882 0x25270, 0x25284,
1883 0x252fc, 0x25388,
1884 0x25400, 0x25404,
1885 0x25500, 0x25518,
1886 0x2552c, 0x2553c,
1887 0x25550, 0x25554,
1888 0x25600, 0x25600,
1889 0x25608, 0x25628,
1890 0x25630, 0x2563c,
1891 0x25700, 0x2571c,
1892 0x25780, 0x2578c,
1893 0x25800, 0x25c38,
1894 0x25c80, 0x25d7c,
1895 0x25e00, 0x25e04,
1896 0x26000, 0x2602c,
1897 0x26100, 0x2613c,
1898 0x26190, 0x261c8,
1899 0x26200, 0x26318,
1900 0x26400, 0x26528,
1901 0x26540, 0x26614,
1902 0x27000, 0x27040,
1903 0x2704c, 0x27060,
1904 0x270c0, 0x270ec,
1905 0x27200, 0x27268,
1906 0x27270, 0x27284,
1907 0x272fc, 0x27388,
1908 0x27400, 0x27404,
1909 0x27500, 0x27518,
1910 0x2752c, 0x2753c,
1911 0x27550, 0x27554,
1912 0x27600, 0x27600,
1913 0x27608, 0x27628,
1914 0x27630, 0x2763c,
1915 0x27700, 0x2771c,
1916 0x27780, 0x2778c,
1917 0x27800, 0x27c38,
1918 0x27c80, 0x27d7c,
1919 0x27e00, 0x27e04
1920 };
1921
251f9e88
SR
1922 static const unsigned int t5_reg_ranges[] = {
1923 0x1008, 0x1148,
1924 0x1180, 0x11b4,
1925 0x11fc, 0x123c,
1926 0x1280, 0x173c,
1927 0x1800, 0x18fc,
1928 0x3000, 0x3028,
1929 0x3060, 0x30d8,
1930 0x30e0, 0x30fc,
1931 0x3140, 0x357c,
1932 0x35a8, 0x35cc,
1933 0x35ec, 0x35ec,
1934 0x3600, 0x5624,
1935 0x56cc, 0x575c,
1936 0x580c, 0x5814,
1937 0x5890, 0x58bc,
1938 0x5940, 0x59dc,
1939 0x59fc, 0x5a18,
1940 0x5a60, 0x5a9c,
1941 0x5b9c, 0x5bfc,
1942 0x6000, 0x6040,
1943 0x6058, 0x614c,
1944 0x7700, 0x7798,
1945 0x77c0, 0x78fc,
1946 0x7b00, 0x7c54,
1947 0x7d00, 0x7efc,
1948 0x8dc0, 0x8de0,
1949 0x8df8, 0x8e84,
1950 0x8ea0, 0x8f84,
1951 0x8fc0, 0x90f8,
1952 0x9400, 0x9470,
1953 0x9600, 0x96f4,
1954 0x9800, 0x9808,
1955 0x9820, 0x983c,
1956 0x9850, 0x9864,
1957 0x9c00, 0x9c6c,
1958 0x9c80, 0x9cec,
1959 0x9d00, 0x9d6c,
1960 0x9d80, 0x9dec,
1961 0x9e00, 0x9e6c,
1962 0x9e80, 0x9eec,
1963 0x9f00, 0x9f6c,
1964 0x9f80, 0xa020,
1965 0xd004, 0xd03c,
1966 0xdfc0, 0xdfe0,
1967 0xe000, 0x11088,
1968 0x1109c, 0x1117c,
1969 0x11190, 0x11204,
1970 0x19040, 0x1906c,
1971 0x19078, 0x19080,
1972 0x1908c, 0x19124,
1973 0x19150, 0x191b0,
1974 0x191d0, 0x191e8,
1975 0x19238, 0x19290,
1976 0x193f8, 0x19474,
1977 0x19490, 0x194cc,
1978 0x194f0, 0x194f8,
1979 0x19c00, 0x19c60,
1980 0x19c94, 0x19e10,
1981 0x19e50, 0x19f34,
1982 0x19f40, 0x19f50,
1983 0x19f90, 0x19fe4,
1984 0x1a000, 0x1a06c,
1985 0x1a0b0, 0x1a120,
1986 0x1a128, 0x1a138,
1987 0x1a190, 0x1a1c4,
1988 0x1a1fc, 0x1a1fc,
1989 0x1e008, 0x1e00c,
1990 0x1e040, 0x1e04c,
1991 0x1e284, 0x1e290,
1992 0x1e2c0, 0x1e2c0,
1993 0x1e2e0, 0x1e2e0,
1994 0x1e300, 0x1e384,
1995 0x1e3c0, 0x1e3c8,
1996 0x1e408, 0x1e40c,
1997 0x1e440, 0x1e44c,
1998 0x1e684, 0x1e690,
1999 0x1e6c0, 0x1e6c0,
2000 0x1e6e0, 0x1e6e0,
2001 0x1e700, 0x1e784,
2002 0x1e7c0, 0x1e7c8,
2003 0x1e808, 0x1e80c,
2004 0x1e840, 0x1e84c,
2005 0x1ea84, 0x1ea90,
2006 0x1eac0, 0x1eac0,
2007 0x1eae0, 0x1eae0,
2008 0x1eb00, 0x1eb84,
2009 0x1ebc0, 0x1ebc8,
2010 0x1ec08, 0x1ec0c,
2011 0x1ec40, 0x1ec4c,
2012 0x1ee84, 0x1ee90,
2013 0x1eec0, 0x1eec0,
2014 0x1eee0, 0x1eee0,
2015 0x1ef00, 0x1ef84,
2016 0x1efc0, 0x1efc8,
2017 0x1f008, 0x1f00c,
2018 0x1f040, 0x1f04c,
2019 0x1f284, 0x1f290,
2020 0x1f2c0, 0x1f2c0,
2021 0x1f2e0, 0x1f2e0,
2022 0x1f300, 0x1f384,
2023 0x1f3c0, 0x1f3c8,
2024 0x1f408, 0x1f40c,
2025 0x1f440, 0x1f44c,
2026 0x1f684, 0x1f690,
2027 0x1f6c0, 0x1f6c0,
2028 0x1f6e0, 0x1f6e0,
2029 0x1f700, 0x1f784,
2030 0x1f7c0, 0x1f7c8,
2031 0x1f808, 0x1f80c,
2032 0x1f840, 0x1f84c,
2033 0x1fa84, 0x1fa90,
2034 0x1fac0, 0x1fac0,
2035 0x1fae0, 0x1fae0,
2036 0x1fb00, 0x1fb84,
2037 0x1fbc0, 0x1fbc8,
2038 0x1fc08, 0x1fc0c,
2039 0x1fc40, 0x1fc4c,
2040 0x1fe84, 0x1fe90,
2041 0x1fec0, 0x1fec0,
2042 0x1fee0, 0x1fee0,
2043 0x1ff00, 0x1ff84,
2044 0x1ffc0, 0x1ffc8,
2045 0x30000, 0x30030,
2046 0x30100, 0x30144,
2047 0x30190, 0x301d0,
2048 0x30200, 0x30318,
2049 0x30400, 0x3052c,
2050 0x30540, 0x3061c,
2051 0x30800, 0x30834,
2052 0x308c0, 0x30908,
2053 0x30910, 0x309ac,
2054 0x30a00, 0x30a04,
2055 0x30a0c, 0x30a2c,
2056 0x30a44, 0x30a50,
2057 0x30a74, 0x30c24,
2058 0x30d08, 0x30d14,
2059 0x30d1c, 0x30d20,
2060 0x30d3c, 0x30d50,
2061 0x31200, 0x3120c,
2062 0x31220, 0x31220,
2063 0x31240, 0x31240,
2064 0x31600, 0x31600,
2065 0x31608, 0x3160c,
2066 0x31a00, 0x31a1c,
2067 0x31e04, 0x31e20,
2068 0x31e38, 0x31e3c,
2069 0x31e80, 0x31e80,
2070 0x31e88, 0x31ea8,
2071 0x31eb0, 0x31eb4,
2072 0x31ec8, 0x31ed4,
2073 0x31fb8, 0x32004,
2074 0x32208, 0x3223c,
2075 0x32600, 0x32630,
2076 0x32a00, 0x32abc,
2077 0x32b00, 0x32b70,
2078 0x33000, 0x33048,
2079 0x33060, 0x3309c,
2080 0x330f0, 0x33148,
2081 0x33160, 0x3319c,
2082 0x331f0, 0x332e4,
2083 0x332f8, 0x333e4,
2084 0x333f8, 0x33448,
2085 0x33460, 0x3349c,
2086 0x334f0, 0x33548,
2087 0x33560, 0x3359c,
2088 0x335f0, 0x336e4,
2089 0x336f8, 0x337e4,
2090 0x337f8, 0x337fc,
2091 0x33814, 0x33814,
2092 0x3382c, 0x3382c,
2093 0x33880, 0x3388c,
2094 0x338e8, 0x338ec,
2095 0x33900, 0x33948,
2096 0x33960, 0x3399c,
2097 0x339f0, 0x33ae4,
2098 0x33af8, 0x33b10,
2099 0x33b28, 0x33b28,
2100 0x33b3c, 0x33b50,
2101 0x33bf0, 0x33c10,
2102 0x33c28, 0x33c28,
2103 0x33c3c, 0x33c50,
2104 0x33cf0, 0x33cfc,
2105 0x34000, 0x34030,
2106 0x34100, 0x34144,
2107 0x34190, 0x341d0,
2108 0x34200, 0x34318,
2109 0x34400, 0x3452c,
2110 0x34540, 0x3461c,
2111 0x34800, 0x34834,
2112 0x348c0, 0x34908,
2113 0x34910, 0x349ac,
2114 0x34a00, 0x34a04,
2115 0x34a0c, 0x34a2c,
2116 0x34a44, 0x34a50,
2117 0x34a74, 0x34c24,
2118 0x34d08, 0x34d14,
2119 0x34d1c, 0x34d20,
2120 0x34d3c, 0x34d50,
2121 0x35200, 0x3520c,
2122 0x35220, 0x35220,
2123 0x35240, 0x35240,
2124 0x35600, 0x35600,
2125 0x35608, 0x3560c,
2126 0x35a00, 0x35a1c,
2127 0x35e04, 0x35e20,
2128 0x35e38, 0x35e3c,
2129 0x35e80, 0x35e80,
2130 0x35e88, 0x35ea8,
2131 0x35eb0, 0x35eb4,
2132 0x35ec8, 0x35ed4,
2133 0x35fb8, 0x36004,
2134 0x36208, 0x3623c,
2135 0x36600, 0x36630,
2136 0x36a00, 0x36abc,
2137 0x36b00, 0x36b70,
2138 0x37000, 0x37048,
2139 0x37060, 0x3709c,
2140 0x370f0, 0x37148,
2141 0x37160, 0x3719c,
2142 0x371f0, 0x372e4,
2143 0x372f8, 0x373e4,
2144 0x373f8, 0x37448,
2145 0x37460, 0x3749c,
2146 0x374f0, 0x37548,
2147 0x37560, 0x3759c,
2148 0x375f0, 0x376e4,
2149 0x376f8, 0x377e4,
2150 0x377f8, 0x377fc,
2151 0x37814, 0x37814,
2152 0x3782c, 0x3782c,
2153 0x37880, 0x3788c,
2154 0x378e8, 0x378ec,
2155 0x37900, 0x37948,
2156 0x37960, 0x3799c,
2157 0x379f0, 0x37ae4,
2158 0x37af8, 0x37b10,
2159 0x37b28, 0x37b28,
2160 0x37b3c, 0x37b50,
2161 0x37bf0, 0x37c10,
2162 0x37c28, 0x37c28,
2163 0x37c3c, 0x37c50,
2164 0x37cf0, 0x37cfc,
2165 0x38000, 0x38030,
2166 0x38100, 0x38144,
2167 0x38190, 0x381d0,
2168 0x38200, 0x38318,
2169 0x38400, 0x3852c,
2170 0x38540, 0x3861c,
2171 0x38800, 0x38834,
2172 0x388c0, 0x38908,
2173 0x38910, 0x389ac,
2174 0x38a00, 0x38a04,
2175 0x38a0c, 0x38a2c,
2176 0x38a44, 0x38a50,
2177 0x38a74, 0x38c24,
2178 0x38d08, 0x38d14,
2179 0x38d1c, 0x38d20,
2180 0x38d3c, 0x38d50,
2181 0x39200, 0x3920c,
2182 0x39220, 0x39220,
2183 0x39240, 0x39240,
2184 0x39600, 0x39600,
2185 0x39608, 0x3960c,
2186 0x39a00, 0x39a1c,
2187 0x39e04, 0x39e20,
2188 0x39e38, 0x39e3c,
2189 0x39e80, 0x39e80,
2190 0x39e88, 0x39ea8,
2191 0x39eb0, 0x39eb4,
2192 0x39ec8, 0x39ed4,
2193 0x39fb8, 0x3a004,
2194 0x3a208, 0x3a23c,
2195 0x3a600, 0x3a630,
2196 0x3aa00, 0x3aabc,
2197 0x3ab00, 0x3ab70,
2198 0x3b000, 0x3b048,
2199 0x3b060, 0x3b09c,
2200 0x3b0f0, 0x3b148,
2201 0x3b160, 0x3b19c,
2202 0x3b1f0, 0x3b2e4,
2203 0x3b2f8, 0x3b3e4,
2204 0x3b3f8, 0x3b448,
2205 0x3b460, 0x3b49c,
2206 0x3b4f0, 0x3b548,
2207 0x3b560, 0x3b59c,
2208 0x3b5f0, 0x3b6e4,
2209 0x3b6f8, 0x3b7e4,
2210 0x3b7f8, 0x3b7fc,
2211 0x3b814, 0x3b814,
2212 0x3b82c, 0x3b82c,
2213 0x3b880, 0x3b88c,
2214 0x3b8e8, 0x3b8ec,
2215 0x3b900, 0x3b948,
2216 0x3b960, 0x3b99c,
2217 0x3b9f0, 0x3bae4,
2218 0x3baf8, 0x3bb10,
2219 0x3bb28, 0x3bb28,
2220 0x3bb3c, 0x3bb50,
2221 0x3bbf0, 0x3bc10,
2222 0x3bc28, 0x3bc28,
2223 0x3bc3c, 0x3bc50,
2224 0x3bcf0, 0x3bcfc,
2225 0x3c000, 0x3c030,
2226 0x3c100, 0x3c144,
2227 0x3c190, 0x3c1d0,
2228 0x3c200, 0x3c318,
2229 0x3c400, 0x3c52c,
2230 0x3c540, 0x3c61c,
2231 0x3c800, 0x3c834,
2232 0x3c8c0, 0x3c908,
2233 0x3c910, 0x3c9ac,
2234 0x3ca00, 0x3ca04,
2235 0x3ca0c, 0x3ca2c,
2236 0x3ca44, 0x3ca50,
2237 0x3ca74, 0x3cc24,
2238 0x3cd08, 0x3cd14,
2239 0x3cd1c, 0x3cd20,
2240 0x3cd3c, 0x3cd50,
2241 0x3d200, 0x3d20c,
2242 0x3d220, 0x3d220,
2243 0x3d240, 0x3d240,
2244 0x3d600, 0x3d600,
2245 0x3d608, 0x3d60c,
2246 0x3da00, 0x3da1c,
2247 0x3de04, 0x3de20,
2248 0x3de38, 0x3de3c,
2249 0x3de80, 0x3de80,
2250 0x3de88, 0x3dea8,
2251 0x3deb0, 0x3deb4,
2252 0x3dec8, 0x3ded4,
2253 0x3dfb8, 0x3e004,
2254 0x3e208, 0x3e23c,
2255 0x3e600, 0x3e630,
2256 0x3ea00, 0x3eabc,
2257 0x3eb00, 0x3eb70,
2258 0x3f000, 0x3f048,
2259 0x3f060, 0x3f09c,
2260 0x3f0f0, 0x3f148,
2261 0x3f160, 0x3f19c,
2262 0x3f1f0, 0x3f2e4,
2263 0x3f2f8, 0x3f3e4,
2264 0x3f3f8, 0x3f448,
2265 0x3f460, 0x3f49c,
2266 0x3f4f0, 0x3f548,
2267 0x3f560, 0x3f59c,
2268 0x3f5f0, 0x3f6e4,
2269 0x3f6f8, 0x3f7e4,
2270 0x3f7f8, 0x3f7fc,
2271 0x3f814, 0x3f814,
2272 0x3f82c, 0x3f82c,
2273 0x3f880, 0x3f88c,
2274 0x3f8e8, 0x3f8ec,
2275 0x3f900, 0x3f948,
2276 0x3f960, 0x3f99c,
2277 0x3f9f0, 0x3fae4,
2278 0x3faf8, 0x3fb10,
2279 0x3fb28, 0x3fb28,
2280 0x3fb3c, 0x3fb50,
2281 0x3fbf0, 0x3fc10,
2282 0x3fc28, 0x3fc28,
2283 0x3fc3c, 0x3fc50,
2284 0x3fcf0, 0x3fcfc,
2285 0x40000, 0x4000c,
2286 0x40040, 0x40068,
2287 0x40080, 0x40144,
2288 0x40180, 0x4018c,
2289 0x40200, 0x40298,
2290 0x402ac, 0x4033c,
2291 0x403f8, 0x403fc,
c1f49e3e 2292 0x41304, 0x413c4,
251f9e88
SR
2293 0x41400, 0x4141c,
2294 0x41480, 0x414d0,
2295 0x44000, 0x44078,
2296 0x440c0, 0x44278,
2297 0x442c0, 0x44478,
2298 0x444c0, 0x44678,
2299 0x446c0, 0x44878,
2300 0x448c0, 0x449fc,
2301 0x45000, 0x45068,
2302 0x45080, 0x45084,
2303 0x450a0, 0x450b0,
2304 0x45200, 0x45268,
2305 0x45280, 0x45284,
2306 0x452a0, 0x452b0,
2307 0x460c0, 0x460e4,
2308 0x47000, 0x4708c,
2309 0x47200, 0x47250,
2310 0x47400, 0x47420,
2311 0x47600, 0x47618,
2312 0x47800, 0x47814,
2313 0x48000, 0x4800c,
2314 0x48040, 0x48068,
2315 0x48080, 0x48144,
2316 0x48180, 0x4818c,
2317 0x48200, 0x48298,
2318 0x482ac, 0x4833c,
2319 0x483f8, 0x483fc,
c1f49e3e 2320 0x49304, 0x493c4,
251f9e88
SR
2321 0x49400, 0x4941c,
2322 0x49480, 0x494d0,
2323 0x4c000, 0x4c078,
2324 0x4c0c0, 0x4c278,
2325 0x4c2c0, 0x4c478,
2326 0x4c4c0, 0x4c678,
2327 0x4c6c0, 0x4c878,
2328 0x4c8c0, 0x4c9fc,
2329 0x4d000, 0x4d068,
2330 0x4d080, 0x4d084,
2331 0x4d0a0, 0x4d0b0,
2332 0x4d200, 0x4d268,
2333 0x4d280, 0x4d284,
2334 0x4d2a0, 0x4d2b0,
2335 0x4e0c0, 0x4e0e4,
2336 0x4f000, 0x4f08c,
2337 0x4f200, 0x4f250,
2338 0x4f400, 0x4f420,
2339 0x4f600, 0x4f618,
2340 0x4f800, 0x4f814,
2341 0x50000, 0x500cc,
2342 0x50400, 0x50400,
2343 0x50800, 0x508cc,
2344 0x50c00, 0x50c00,
2345 0x51000, 0x5101c,
2346 0x51300, 0x51308,
2347 };
2348
b8ff05a9
DM
2349 int i;
2350 struct adapter *ap = netdev2adap(dev);
251f9e88
SR
2351 static const unsigned int *reg_ranges;
2352 int arr_size = 0, buf_size = 0;
2353
d14807dd 2354 if (is_t4(ap->params.chip)) {
251f9e88
SR
2355 reg_ranges = &t4_reg_ranges[0];
2356 arr_size = ARRAY_SIZE(t4_reg_ranges);
2357 buf_size = T4_REGMAP_SIZE;
2358 } else {
2359 reg_ranges = &t5_reg_ranges[0];
2360 arr_size = ARRAY_SIZE(t5_reg_ranges);
2361 buf_size = T5_REGMAP_SIZE;
2362 }
b8ff05a9
DM
2363
2364 regs->version = mk_adap_vers(ap);
2365
251f9e88
SR
2366 memset(buf, 0, buf_size);
2367 for (i = 0; i < arr_size; i += 2)
b8ff05a9
DM
2368 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2369}
2370
2371static int restart_autoneg(struct net_device *dev)
2372{
2373 struct port_info *p = netdev_priv(dev);
2374
2375 if (!netif_running(dev))
2376 return -EAGAIN;
2377 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2378 return -EINVAL;
060e0c75 2379 t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
b8ff05a9
DM
2380 return 0;
2381}
2382
c5e06360
DM
2383static int identify_port(struct net_device *dev,
2384 enum ethtool_phys_id_state state)
b8ff05a9 2385{
c5e06360 2386 unsigned int val;
060e0c75
DM
2387 struct adapter *adap = netdev2adap(dev);
2388
c5e06360
DM
2389 if (state == ETHTOOL_ID_ACTIVE)
2390 val = 0xffff;
2391 else if (state == ETHTOOL_ID_INACTIVE)
2392 val = 0;
2393 else
2394 return -EINVAL;
b8ff05a9 2395
c5e06360 2396 return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
b8ff05a9
DM
2397}
2398
2399static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2400{
2401 unsigned int v = 0;
2402
a0881cab
DM
2403 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2404 type == FW_PORT_TYPE_BT_XAUI) {
b8ff05a9
DM
2405 v |= SUPPORTED_TP;
2406 if (caps & FW_PORT_CAP_SPEED_100M)
2407 v |= SUPPORTED_100baseT_Full;
2408 if (caps & FW_PORT_CAP_SPEED_1G)
2409 v |= SUPPORTED_1000baseT_Full;
2410 if (caps & FW_PORT_CAP_SPEED_10G)
2411 v |= SUPPORTED_10000baseT_Full;
2412 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2413 v |= SUPPORTED_Backplane;
2414 if (caps & FW_PORT_CAP_SPEED_1G)
2415 v |= SUPPORTED_1000baseKX_Full;
2416 if (caps & FW_PORT_CAP_SPEED_10G)
2417 v |= SUPPORTED_10000baseKX4_Full;
2418 } else if (type == FW_PORT_TYPE_KR)
2419 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
a0881cab 2420 else if (type == FW_PORT_TYPE_BP_AP)
7d5e77aa
DM
2421 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2422 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2423 else if (type == FW_PORT_TYPE_BP4_AP)
2424 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2425 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2426 SUPPORTED_10000baseKX4_Full;
a0881cab
DM
2427 else if (type == FW_PORT_TYPE_FIBER_XFI ||
2428 type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
b8ff05a9 2429 v |= SUPPORTED_FIBRE;
72aca4bf
KS
2430 else if (type == FW_PORT_TYPE_BP40_BA)
2431 v |= SUPPORTED_40000baseSR4_Full;
b8ff05a9
DM
2432
2433 if (caps & FW_PORT_CAP_ANEG)
2434 v |= SUPPORTED_Autoneg;
2435 return v;
2436}
2437
2438static unsigned int to_fw_linkcaps(unsigned int caps)
2439{
2440 unsigned int v = 0;
2441
2442 if (caps & ADVERTISED_100baseT_Full)
2443 v |= FW_PORT_CAP_SPEED_100M;
2444 if (caps & ADVERTISED_1000baseT_Full)
2445 v |= FW_PORT_CAP_SPEED_1G;
2446 if (caps & ADVERTISED_10000baseT_Full)
2447 v |= FW_PORT_CAP_SPEED_10G;
72aca4bf
KS
2448 if (caps & ADVERTISED_40000baseSR4_Full)
2449 v |= FW_PORT_CAP_SPEED_40G;
b8ff05a9
DM
2450 return v;
2451}
2452
2453static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2454{
2455 const struct port_info *p = netdev_priv(dev);
2456
2457 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
a0881cab 2458 p->port_type == FW_PORT_TYPE_BT_XFI ||
b8ff05a9
DM
2459 p->port_type == FW_PORT_TYPE_BT_XAUI)
2460 cmd->port = PORT_TP;
a0881cab
DM
2461 else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2462 p->port_type == FW_PORT_TYPE_FIBER_XAUI)
b8ff05a9 2463 cmd->port = PORT_FIBRE;
3e00a509
HS
2464 else if (p->port_type == FW_PORT_TYPE_SFP ||
2465 p->port_type == FW_PORT_TYPE_QSFP_10G ||
2466 p->port_type == FW_PORT_TYPE_QSFP) {
2467 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2468 p->mod_type == FW_PORT_MOD_TYPE_SR ||
2469 p->mod_type == FW_PORT_MOD_TYPE_ER ||
2470 p->mod_type == FW_PORT_MOD_TYPE_LRM)
2471 cmd->port = PORT_FIBRE;
2472 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2473 p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
a0881cab
DM
2474 cmd->port = PORT_DA;
2475 else
3e00a509 2476 cmd->port = PORT_OTHER;
a0881cab 2477 } else
b8ff05a9
DM
2478 cmd->port = PORT_OTHER;
2479
2480 if (p->mdio_addr >= 0) {
2481 cmd->phy_address = p->mdio_addr;
2482 cmd->transceiver = XCVR_EXTERNAL;
2483 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2484 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2485 } else {
2486 cmd->phy_address = 0; /* not really, but no better option */
2487 cmd->transceiver = XCVR_INTERNAL;
2488 cmd->mdio_support = 0;
2489 }
2490
2491 cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2492 cmd->advertising = from_fw_linkcaps(p->port_type,
2493 p->link_cfg.advertising);
70739497
DD
2494 ethtool_cmd_speed_set(cmd,
2495 netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
b8ff05a9
DM
2496 cmd->duplex = DUPLEX_FULL;
2497 cmd->autoneg = p->link_cfg.autoneg;
2498 cmd->maxtxpkt = 0;
2499 cmd->maxrxpkt = 0;
2500 return 0;
2501}
2502
2503static unsigned int speed_to_caps(int speed)
2504{
e8b39015 2505 if (speed == 100)
b8ff05a9 2506 return FW_PORT_CAP_SPEED_100M;
e8b39015 2507 if (speed == 1000)
b8ff05a9 2508 return FW_PORT_CAP_SPEED_1G;
e8b39015 2509 if (speed == 10000)
b8ff05a9 2510 return FW_PORT_CAP_SPEED_10G;
e8b39015 2511 if (speed == 40000)
72aca4bf 2512 return FW_PORT_CAP_SPEED_40G;
b8ff05a9
DM
2513 return 0;
2514}
2515
2516static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2517{
2518 unsigned int cap;
2519 struct port_info *p = netdev_priv(dev);
2520 struct link_config *lc = &p->link_cfg;
25db0338 2521 u32 speed = ethtool_cmd_speed(cmd);
b8ff05a9
DM
2522
2523 if (cmd->duplex != DUPLEX_FULL) /* only full-duplex supported */
2524 return -EINVAL;
2525
2526 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2527 /*
2528 * PHY offers a single speed. See if that's what's
2529 * being requested.
2530 */
2531 if (cmd->autoneg == AUTONEG_DISABLE &&
25db0338
DD
2532 (lc->supported & speed_to_caps(speed)))
2533 return 0;
b8ff05a9
DM
2534 return -EINVAL;
2535 }
2536
2537 if (cmd->autoneg == AUTONEG_DISABLE) {
25db0338 2538 cap = speed_to_caps(speed);
b8ff05a9 2539
72aca4bf 2540 if (!(lc->supported & cap) ||
e8b39015
BH
2541 (speed == 1000) ||
2542 (speed == 10000) ||
72aca4bf 2543 (speed == 40000))
b8ff05a9
DM
2544 return -EINVAL;
2545 lc->requested_speed = cap;
2546 lc->advertising = 0;
2547 } else {
2548 cap = to_fw_linkcaps(cmd->advertising);
2549 if (!(lc->supported & cap))
2550 return -EINVAL;
2551 lc->requested_speed = 0;
2552 lc->advertising = cap | FW_PORT_CAP_ANEG;
2553 }
2554 lc->autoneg = cmd->autoneg;
2555
2556 if (netif_running(dev))
060e0c75
DM
2557 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2558 lc);
b8ff05a9
DM
2559 return 0;
2560}
2561
2562static void get_pauseparam(struct net_device *dev,
2563 struct ethtool_pauseparam *epause)
2564{
2565 struct port_info *p = netdev_priv(dev);
2566
2567 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2568 epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2569 epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2570}
2571
2572static int set_pauseparam(struct net_device *dev,
2573 struct ethtool_pauseparam *epause)
2574{
2575 struct port_info *p = netdev_priv(dev);
2576 struct link_config *lc = &p->link_cfg;
2577
2578 if (epause->autoneg == AUTONEG_DISABLE)
2579 lc->requested_fc = 0;
2580 else if (lc->supported & FW_PORT_CAP_ANEG)
2581 lc->requested_fc = PAUSE_AUTONEG;
2582 else
2583 return -EINVAL;
2584
2585 if (epause->rx_pause)
2586 lc->requested_fc |= PAUSE_RX;
2587 if (epause->tx_pause)
2588 lc->requested_fc |= PAUSE_TX;
2589 if (netif_running(dev))
060e0c75
DM
2590 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2591 lc);
b8ff05a9
DM
2592 return 0;
2593}
2594
b8ff05a9
DM
2595static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2596{
2597 const struct port_info *pi = netdev_priv(dev);
2598 const struct sge *s = &pi->adapter->sge;
2599
2600 e->rx_max_pending = MAX_RX_BUFFERS;
2601 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2602 e->rx_jumbo_max_pending = 0;
2603 e->tx_max_pending = MAX_TXQ_ENTRIES;
2604
2605 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2606 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2607 e->rx_jumbo_pending = 0;
2608 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2609}
2610
2611static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2612{
2613 int i;
2614 const struct port_info *pi = netdev_priv(dev);
2615 struct adapter *adapter = pi->adapter;
2616 struct sge *s = &adapter->sge;
2617
2618 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2619 e->tx_pending > MAX_TXQ_ENTRIES ||
2620 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2621 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2622 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2623 return -EINVAL;
2624
2625 if (adapter->flags & FULL_INIT_DONE)
2626 return -EBUSY;
2627
2628 for (i = 0; i < pi->nqsets; ++i) {
2629 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2630 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2631 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2632 }
2633 return 0;
2634}
2635
2636static int closest_timer(const struct sge *s, int time)
2637{
2638 int i, delta, match = 0, min_delta = INT_MAX;
2639
2640 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2641 delta = time - s->timer_val[i];
2642 if (delta < 0)
2643 delta = -delta;
2644 if (delta < min_delta) {
2645 min_delta = delta;
2646 match = i;
2647 }
2648 }
2649 return match;
2650}
2651
2652static int closest_thres(const struct sge *s, int thres)
2653{
2654 int i, delta, match = 0, min_delta = INT_MAX;
2655
2656 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2657 delta = thres - s->counter_val[i];
2658 if (delta < 0)
2659 delta = -delta;
2660 if (delta < min_delta) {
2661 min_delta = delta;
2662 match = i;
2663 }
2664 }
2665 return match;
2666}
2667
2668/*
2669 * Return a queue's interrupt hold-off time in us. 0 means no timer.
2670 */
2671static unsigned int qtimer_val(const struct adapter *adap,
2672 const struct sge_rspq *q)
2673{
2674 unsigned int idx = q->intr_params >> 1;
2675
2676 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2677}
2678
2679/**
c887ad0e 2680 * set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM
2681 * @q: the Rx queue
2682 * @us: the hold-off time in us, or 0 to disable timer
2683 * @cnt: the hold-off packet count, or 0 to disable counter
2684 *
2685 * Sets an Rx queue's interrupt hold-off time and packet count. At least
2686 * one of the two needs to be enabled for the queue to generate interrupts.
2687 */
c887ad0e
HS
2688static int set_rspq_intr_params(struct sge_rspq *q,
2689 unsigned int us, unsigned int cnt)
b8ff05a9 2690{
c887ad0e
HS
2691 struct adapter *adap = q->adap;
2692
b8ff05a9
DM
2693 if ((us | cnt) == 0)
2694 cnt = 1;
2695
2696 if (cnt) {
2697 int err;
2698 u32 v, new_idx;
2699
2700 new_idx = closest_thres(&adap->sge, cnt);
2701 if (q->desc && q->pktcnt_idx != new_idx) {
2702 /* the queue has already been created, update it */
2703 v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2704 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2705 FW_PARAMS_PARAM_YZ(q->cntxt_id);
060e0c75
DM
2706 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2707 &new_idx);
b8ff05a9
DM
2708 if (err)
2709 return err;
2710 }
2711 q->pktcnt_idx = new_idx;
2712 }
2713
2714 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2715 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2716 return 0;
2717}
2718
c887ad0e
HS
2719/**
2720 * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2721 * @dev: the network device
2722 * @us: the hold-off time in us, or 0 to disable timer
2723 * @cnt: the hold-off packet count, or 0 to disable counter
2724 *
2725 * Set the RX interrupt hold-off parameters for a network device.
2726 */
2727static int set_rx_intr_params(struct net_device *dev,
2728 unsigned int us, unsigned int cnt)
b8ff05a9 2729{
c887ad0e
HS
2730 int i, err;
2731 struct port_info *pi = netdev_priv(dev);
b8ff05a9 2732 struct adapter *adap = pi->adapter;
c887ad0e
HS
2733 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2734
2735 for (i = 0; i < pi->nqsets; i++, q++) {
2736 err = set_rspq_intr_params(&q->rspq, us, cnt);
2737 if (err)
2738 return err;
d4fc9dc2 2739 }
c887ad0e
HS
2740 return 0;
2741}
2742
2743static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2744{
2745 return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2746 c->rx_max_coalesced_frames);
b8ff05a9
DM
2747}
2748
2749static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2750{
2751 const struct port_info *pi = netdev_priv(dev);
2752 const struct adapter *adap = pi->adapter;
2753 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2754
2755 c->rx_coalesce_usecs = qtimer_val(adap, rq);
2756 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2757 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2758 return 0;
2759}
2760
1478b3ee
DM
2761/**
2762 * eeprom_ptov - translate a physical EEPROM address to virtual
2763 * @phys_addr: the physical EEPROM address
2764 * @fn: the PCI function number
2765 * @sz: size of function-specific area
2766 *
2767 * Translate a physical EEPROM address to virtual. The first 1K is
2768 * accessed through virtual addresses starting at 31K, the rest is
2769 * accessed through virtual addresses starting at 0.
2770 *
2771 * The mapping is as follows:
2772 * [0..1K) -> [31K..32K)
2773 * [1K..1K+A) -> [31K-A..31K)
2774 * [1K+A..ES) -> [0..ES-A-1K)
2775 *
2776 * where A = @fn * @sz, and ES = EEPROM size.
b8ff05a9 2777 */
1478b3ee 2778static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
b8ff05a9 2779{
1478b3ee 2780 fn *= sz;
b8ff05a9
DM
2781 if (phys_addr < 1024)
2782 return phys_addr + (31 << 10);
1478b3ee
DM
2783 if (phys_addr < 1024 + fn)
2784 return 31744 - fn + phys_addr - 1024;
b8ff05a9 2785 if (phys_addr < EEPROMSIZE)
1478b3ee 2786 return phys_addr - 1024 - fn;
b8ff05a9
DM
2787 return -EINVAL;
2788}
2789
2790/*
2791 * The next two routines implement eeprom read/write from physical addresses.
b8ff05a9
DM
2792 */
2793static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2794{
1478b3ee 2795 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
b8ff05a9
DM
2796
2797 if (vaddr >= 0)
2798 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2799 return vaddr < 0 ? vaddr : 0;
2800}
2801
2802static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2803{
1478b3ee 2804 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
b8ff05a9
DM
2805
2806 if (vaddr >= 0)
2807 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2808 return vaddr < 0 ? vaddr : 0;
2809}
2810
2811#define EEPROM_MAGIC 0x38E2F10C
2812
2813static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2814 u8 *data)
2815{
2816 int i, err = 0;
2817 struct adapter *adapter = netdev2adap(dev);
2818
2819 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2820 if (!buf)
2821 return -ENOMEM;
2822
2823 e->magic = EEPROM_MAGIC;
2824 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2825 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2826
2827 if (!err)
2828 memcpy(data, buf + e->offset, e->len);
2829 kfree(buf);
2830 return err;
2831}
2832
2833static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2834 u8 *data)
2835{
2836 u8 *buf;
2837 int err = 0;
2838 u32 aligned_offset, aligned_len, *p;
2839 struct adapter *adapter = netdev2adap(dev);
2840
2841 if (eeprom->magic != EEPROM_MAGIC)
2842 return -EINVAL;
2843
2844 aligned_offset = eeprom->offset & ~3;
2845 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2846
1478b3ee
DM
2847 if (adapter->fn > 0) {
2848 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2849
2850 if (aligned_offset < start ||
2851 aligned_offset + aligned_len > start + EEPROMPFSIZE)
2852 return -EPERM;
2853 }
2854
b8ff05a9
DM
2855 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2856 /*
2857 * RMW possibly needed for first or last words.
2858 */
2859 buf = kmalloc(aligned_len, GFP_KERNEL);
2860 if (!buf)
2861 return -ENOMEM;
2862 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2863 if (!err && aligned_len > 4)
2864 err = eeprom_rd_phys(adapter,
2865 aligned_offset + aligned_len - 4,
2866 (u32 *)&buf[aligned_len - 4]);
2867 if (err)
2868 goto out;
2869 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2870 } else
2871 buf = data;
2872
2873 err = t4_seeprom_wp(adapter, false);
2874 if (err)
2875 goto out;
2876
2877 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2878 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2879 aligned_offset += 4;
2880 }
2881
2882 if (!err)
2883 err = t4_seeprom_wp(adapter, true);
2884out:
2885 if (buf != data)
2886 kfree(buf);
2887 return err;
2888}
2889
2890static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2891{
2892 int ret;
2893 const struct firmware *fw;
2894 struct adapter *adap = netdev2adap(netdev);
2895
2896 ef->data[sizeof(ef->data) - 1] = '\0';
2897 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2898 if (ret < 0)
2899 return ret;
2900
2901 ret = t4_load_fw(adap, fw->data, fw->size);
2902 release_firmware(fw);
2903 if (!ret)
2904 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
2905 return ret;
2906}
2907
2908#define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2909#define BCAST_CRC 0xa0ccc1a6
2910
2911static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2912{
2913 wol->supported = WAKE_BCAST | WAKE_MAGIC;
2914 wol->wolopts = netdev2adap(dev)->wol;
2915 memset(&wol->sopass, 0, sizeof(wol->sopass));
2916}
2917
2918static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2919{
2920 int err = 0;
2921 struct port_info *pi = netdev_priv(dev);
2922
2923 if (wol->wolopts & ~WOL_SUPPORTED)
2924 return -EINVAL;
2925 t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2926 (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2927 if (wol->wolopts & WAKE_BCAST) {
2928 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2929 ~0ULL, 0, false);
2930 if (!err)
2931 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2932 ~6ULL, ~0ULL, BCAST_CRC, true);
2933 } else
2934 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2935 return err;
2936}
2937
c8f44aff 2938static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 2939{
2ed28baa 2940 const struct port_info *pi = netdev_priv(dev);
c8f44aff 2941 netdev_features_t changed = dev->features ^ features;
19ecae2c 2942 int err;
19ecae2c 2943
f646968f 2944 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 2945 return 0;
19ecae2c 2946
2ed28baa
MM
2947 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2948 -1, -1, -1,
f646968f 2949 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 2950 if (unlikely(err))
f646968f 2951 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 2952 return err;
87b6cf51
DM
2953}
2954
7850f63f 2955static u32 get_rss_table_size(struct net_device *dev)
671b0060
DM
2956{
2957 const struct port_info *pi = netdev_priv(dev);
671b0060 2958
7850f63f
BH
2959 return pi->rss_size;
2960}
2961
fe62d001 2962static int get_rss_table(struct net_device *dev, u32 *p, u8 *key)
7850f63f
BH
2963{
2964 const struct port_info *pi = netdev_priv(dev);
2965 unsigned int n = pi->rss_size;
2966
671b0060 2967 while (n--)
7850f63f 2968 p[n] = pi->rss[n];
671b0060
DM
2969 return 0;
2970}
2971
fe62d001 2972static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key)
671b0060
DM
2973{
2974 unsigned int i;
2975 struct port_info *pi = netdev_priv(dev);
2976
7850f63f
BH
2977 for (i = 0; i < pi->rss_size; i++)
2978 pi->rss[i] = p[i];
671b0060
DM
2979 if (pi->adapter->flags & FULL_INIT_DONE)
2980 return write_rss(pi, pi->rss);
2981 return 0;
2982}
2983
2984static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2985 u32 *rules)
671b0060 2986{
f796564a
DM
2987 const struct port_info *pi = netdev_priv(dev);
2988
671b0060 2989 switch (info->cmd) {
f796564a
DM
2990 case ETHTOOL_GRXFH: {
2991 unsigned int v = pi->rss_mode;
2992
2993 info->data = 0;
2994 switch (info->flow_type) {
2995 case TCP_V4_FLOW:
2996 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2997 info->data = RXH_IP_SRC | RXH_IP_DST |
2998 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2999 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3000 info->data = RXH_IP_SRC | RXH_IP_DST;
3001 break;
3002 case UDP_V4_FLOW:
3003 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
3004 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3005 info->data = RXH_IP_SRC | RXH_IP_DST |
3006 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3007 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3008 info->data = RXH_IP_SRC | RXH_IP_DST;
3009 break;
3010 case SCTP_V4_FLOW:
3011 case AH_ESP_V4_FLOW:
3012 case IPV4_FLOW:
3013 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3014 info->data = RXH_IP_SRC | RXH_IP_DST;
3015 break;
3016 case TCP_V6_FLOW:
3017 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3018 info->data = RXH_IP_SRC | RXH_IP_DST |
3019 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3020 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3021 info->data = RXH_IP_SRC | RXH_IP_DST;
3022 break;
3023 case UDP_V6_FLOW:
3024 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
3025 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3026 info->data = RXH_IP_SRC | RXH_IP_DST |
3027 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3028 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3029 info->data = RXH_IP_SRC | RXH_IP_DST;
3030 break;
3031 case SCTP_V6_FLOW:
3032 case AH_ESP_V6_FLOW:
3033 case IPV6_FLOW:
3034 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3035 info->data = RXH_IP_SRC | RXH_IP_DST;
3036 break;
3037 }
3038 return 0;
3039 }
671b0060 3040 case ETHTOOL_GRXRINGS:
f796564a 3041 info->data = pi->nqsets;
671b0060
DM
3042 return 0;
3043 }
3044 return -EOPNOTSUPP;
3045}
3046
9b07be4b 3047static const struct ethtool_ops cxgb_ethtool_ops = {
b8ff05a9
DM
3048 .get_settings = get_settings,
3049 .set_settings = set_settings,
3050 .get_drvinfo = get_drvinfo,
3051 .get_msglevel = get_msglevel,
3052 .set_msglevel = set_msglevel,
3053 .get_ringparam = get_sge_param,
3054 .set_ringparam = set_sge_param,
3055 .get_coalesce = get_coalesce,
3056 .set_coalesce = set_coalesce,
3057 .get_eeprom_len = get_eeprom_len,
3058 .get_eeprom = get_eeprom,
3059 .set_eeprom = set_eeprom,
3060 .get_pauseparam = get_pauseparam,
3061 .set_pauseparam = set_pauseparam,
b8ff05a9
DM
3062 .get_link = ethtool_op_get_link,
3063 .get_strings = get_strings,
c5e06360 3064 .set_phys_id = identify_port,
b8ff05a9
DM
3065 .nway_reset = restart_autoneg,
3066 .get_sset_count = get_sset_count,
3067 .get_ethtool_stats = get_stats,
3068 .get_regs_len = get_regs_len,
3069 .get_regs = get_regs,
3070 .get_wol = get_wol,
3071 .set_wol = set_wol,
671b0060 3072 .get_rxnfc = get_rxnfc,
7850f63f 3073 .get_rxfh_indir_size = get_rss_table_size,
fe62d001
BH
3074 .get_rxfh = get_rss_table,
3075 .set_rxfh = set_rss_table,
b8ff05a9
DM
3076 .flash_device = set_flash,
3077};
3078
3079/*
3080 * debugfs support
3081 */
b8ff05a9
DM
3082static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
3083 loff_t *ppos)
3084{
3085 loff_t pos = *ppos;
496ad9aa 3086 loff_t avail = file_inode(file)->i_size;
b8ff05a9
DM
3087 unsigned int mem = (uintptr_t)file->private_data & 3;
3088 struct adapter *adap = file->private_data - mem;
fc5ab020
HS
3089 __be32 *data;
3090 int ret;
b8ff05a9
DM
3091
3092 if (pos < 0)
3093 return -EINVAL;
3094 if (pos >= avail)
3095 return 0;
3096 if (count > avail - pos)
3097 count = avail - pos;
3098
fc5ab020
HS
3099 data = t4_alloc_mem(count);
3100 if (!data)
3101 return -ENOMEM;
b8ff05a9 3102
fc5ab020
HS
3103 spin_lock(&adap->win0_lock);
3104 ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);
3105 spin_unlock(&adap->win0_lock);
3106 if (ret) {
3107 t4_free_mem(data);
3108 return ret;
3109 }
3110 ret = copy_to_user(buf, data, count);
b8ff05a9 3111
fc5ab020
HS
3112 t4_free_mem(data);
3113 if (ret)
3114 return -EFAULT;
b8ff05a9 3115
fc5ab020 3116 *ppos = pos + count;
b8ff05a9
DM
3117 return count;
3118}
3119
3120static const struct file_operations mem_debugfs_fops = {
3121 .owner = THIS_MODULE,
234e3405 3122 .open = simple_open,
b8ff05a9 3123 .read = mem_read,
6038f373 3124 .llseek = default_llseek,
b8ff05a9
DM
3125};
3126
91744948 3127static void add_debugfs_mem(struct adapter *adap, const char *name,
1dd06ae8 3128 unsigned int idx, unsigned int size_mb)
b8ff05a9
DM
3129{
3130 struct dentry *de;
3131
3132 de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
3133 (void *)adap + idx, &mem_debugfs_fops);
3134 if (de && de->d_inode)
3135 de->d_inode->i_size = size_mb << 20;
3136}
3137
91744948 3138static int setup_debugfs(struct adapter *adap)
b8ff05a9
DM
3139{
3140 int i;
19dd37ba 3141 u32 size;
b8ff05a9
DM
3142
3143 if (IS_ERR_OR_NULL(adap->debugfs_root))
3144 return -1;
3145
3146 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
19dd37ba
SR
3147 if (i & EDRAM0_ENABLE) {
3148 size = t4_read_reg(adap, MA_EDRAM0_BAR);
3149 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM_SIZE_GET(size));
3150 }
3151 if (i & EDRAM1_ENABLE) {
3152 size = t4_read_reg(adap, MA_EDRAM1_BAR);
3153 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM_SIZE_GET(size));
3154 }
d14807dd 3155 if (is_t4(adap->params.chip)) {
19dd37ba
SR
3156 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3157 if (i & EXT_MEM_ENABLE)
3158 add_debugfs_mem(adap, "mc", MEM_MC,
3159 EXT_MEM_SIZE_GET(size));
3160 } else {
3161 if (i & EXT_MEM_ENABLE) {
3162 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3163 add_debugfs_mem(adap, "mc0", MEM_MC0,
3164 EXT_MEM_SIZE_GET(size));
3165 }
3166 if (i & EXT_MEM1_ENABLE) {
3167 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR);
3168 add_debugfs_mem(adap, "mc1", MEM_MC1,
3169 EXT_MEM_SIZE_GET(size));
3170 }
3171 }
b8ff05a9
DM
3172 if (adap->l2t)
3173 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
3174 &t4_l2t_fops);
3175 return 0;
3176}
3177
3178/*
3179 * upper-layer driver support
3180 */
3181
3182/*
3183 * Allocate an active-open TID and set it to the supplied value.
3184 */
3185int cxgb4_alloc_atid(struct tid_info *t, void *data)
3186{
3187 int atid = -1;
3188
3189 spin_lock_bh(&t->atid_lock);
3190 if (t->afree) {
3191 union aopen_entry *p = t->afree;
3192
f2b7e78d 3193 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM
3194 t->afree = p->next;
3195 p->data = data;
3196 t->atids_in_use++;
3197 }
3198 spin_unlock_bh(&t->atid_lock);
3199 return atid;
3200}
3201EXPORT_SYMBOL(cxgb4_alloc_atid);
3202
3203/*
3204 * Release an active-open TID.
3205 */
3206void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3207{
f2b7e78d 3208 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM
3209
3210 spin_lock_bh(&t->atid_lock);
3211 p->next = t->afree;
3212 t->afree = p;
3213 t->atids_in_use--;
3214 spin_unlock_bh(&t->atid_lock);
3215}
3216EXPORT_SYMBOL(cxgb4_free_atid);
3217
3218/*
3219 * Allocate a server TID and set it to the supplied value.
3220 */
3221int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3222{
3223 int stid;
3224
3225 spin_lock_bh(&t->stid_lock);
3226 if (family == PF_INET) {
3227 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3228 if (stid < t->nstids)
3229 __set_bit(stid, t->stid_bmap);
3230 else
3231 stid = -1;
3232 } else {
3233 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3234 if (stid < 0)
3235 stid = -1;
3236 }
3237 if (stid >= 0) {
3238 t->stid_tab[stid].data = data;
3239 stid += t->stid_base;
15f63b74
KS
3240 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3241 * This is equivalent to 4 TIDs. With CLIP enabled it
3242 * needs 2 TIDs.
3243 */
3244 if (family == PF_INET)
3245 t->stids_in_use++;
3246 else
3247 t->stids_in_use += 4;
b8ff05a9
DM
3248 }
3249 spin_unlock_bh(&t->stid_lock);
3250 return stid;
3251}
3252EXPORT_SYMBOL(cxgb4_alloc_stid);
3253
dca4faeb
VP
3254/* Allocate a server filter TID and set it to the supplied value.
3255 */
3256int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3257{
3258 int stid;
3259
3260 spin_lock_bh(&t->stid_lock);
3261 if (family == PF_INET) {
3262 stid = find_next_zero_bit(t->stid_bmap,
3263 t->nstids + t->nsftids, t->nstids);
3264 if (stid < (t->nstids + t->nsftids))
3265 __set_bit(stid, t->stid_bmap);
3266 else
3267 stid = -1;
3268 } else {
3269 stid = -1;
3270 }
3271 if (stid >= 0) {
3272 t->stid_tab[stid].data = data;
470c60c4
KS
3273 stid -= t->nstids;
3274 stid += t->sftid_base;
dca4faeb
VP
3275 t->stids_in_use++;
3276 }
3277 spin_unlock_bh(&t->stid_lock);
3278 return stid;
3279}
3280EXPORT_SYMBOL(cxgb4_alloc_sftid);
3281
3282/* Release a server TID.
b8ff05a9
DM
3283 */
3284void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3285{
470c60c4
KS
3286 /* Is it a server filter TID? */
3287 if (t->nsftids && (stid >= t->sftid_base)) {
3288 stid -= t->sftid_base;
3289 stid += t->nstids;
3290 } else {
3291 stid -= t->stid_base;
3292 }
3293
b8ff05a9
DM
3294 spin_lock_bh(&t->stid_lock);
3295 if (family == PF_INET)
3296 __clear_bit(stid, t->stid_bmap);
3297 else
3298 bitmap_release_region(t->stid_bmap, stid, 2);
3299 t->stid_tab[stid].data = NULL;
15f63b74
KS
3300 if (family == PF_INET)
3301 t->stids_in_use--;
3302 else
3303 t->stids_in_use -= 4;
b8ff05a9
DM
3304 spin_unlock_bh(&t->stid_lock);
3305}
3306EXPORT_SYMBOL(cxgb4_free_stid);
3307
3308/*
3309 * Populate a TID_RELEASE WR. Caller must properly size the skb.
3310 */
3311static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3312 unsigned int tid)
3313{
3314 struct cpl_tid_release *req;
3315
3316 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3317 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3318 INIT_TP_WR(req, tid);
3319 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3320}
3321
3322/*
3323 * Queue a TID release request and if necessary schedule a work queue to
3324 * process it.
3325 */
31b9c19b 3326static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3327 unsigned int tid)
b8ff05a9
DM
3328{
3329 void **p = &t->tid_tab[tid];
3330 struct adapter *adap = container_of(t, struct adapter, tids);
3331
3332 spin_lock_bh(&adap->tid_release_lock);
3333 *p = adap->tid_release_head;
3334 /* Low 2 bits encode the Tx channel number */
3335 adap->tid_release_head = (void **)((uintptr_t)p | chan);
3336 if (!adap->tid_release_task_busy) {
3337 adap->tid_release_task_busy = true;
3069ee9b 3338 queue_work(workq, &adap->tid_release_task);
b8ff05a9
DM
3339 }
3340 spin_unlock_bh(&adap->tid_release_lock);
3341}
b8ff05a9
DM
3342
3343/*
3344 * Process the list of pending TID release requests.
3345 */
3346static void process_tid_release_list(struct work_struct *work)
3347{
3348 struct sk_buff *skb;
3349 struct adapter *adap;
3350
3351 adap = container_of(work, struct adapter, tid_release_task);
3352
3353 spin_lock_bh(&adap->tid_release_lock);
3354 while (adap->tid_release_head) {
3355 void **p = adap->tid_release_head;
3356 unsigned int chan = (uintptr_t)p & 3;
3357 p = (void *)p - chan;
3358
3359 adap->tid_release_head = *p;
3360 *p = NULL;
3361 spin_unlock_bh(&adap->tid_release_lock);
3362
3363 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3364 GFP_KERNEL)))
3365 schedule_timeout_uninterruptible(1);
3366
3367 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3368 t4_ofld_send(adap, skb);
3369 spin_lock_bh(&adap->tid_release_lock);
3370 }
3371 adap->tid_release_task_busy = false;
3372 spin_unlock_bh(&adap->tid_release_lock);
3373}
3374
3375/*
3376 * Release a TID and inform HW. If we are unable to allocate the release
3377 * message we defer to a work queue.
3378 */
3379void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3380{
3381 void *old;
3382 struct sk_buff *skb;
3383 struct adapter *adap = container_of(t, struct adapter, tids);
3384
3385 old = t->tid_tab[tid];
3386 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3387 if (likely(skb)) {
3388 t->tid_tab[tid] = NULL;
3389 mk_tid_release(skb, chan, tid);
3390 t4_ofld_send(adap, skb);
3391 } else
3392 cxgb4_queue_tid_release(t, chan, tid);
3393 if (old)
3394 atomic_dec(&t->tids_in_use);
3395}
3396EXPORT_SYMBOL(cxgb4_remove_tid);
3397
3398/*
3399 * Allocate and initialize the TID tables. Returns 0 on success.
3400 */
3401static int tid_init(struct tid_info *t)
3402{
3403 size_t size;
f2b7e78d 3404 unsigned int stid_bmap_size;
b8ff05a9 3405 unsigned int natids = t->natids;
b6f8eaec 3406 struct adapter *adap = container_of(t, struct adapter, tids);
b8ff05a9 3407
dca4faeb 3408 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
f2b7e78d
VP
3409 size = t->ntids * sizeof(*t->tid_tab) +
3410 natids * sizeof(*t->atid_tab) +
b8ff05a9 3411 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 3412 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 3413 stid_bmap_size * sizeof(long) +
dca4faeb
VP
3414 t->nftids * sizeof(*t->ftid_tab) +
3415 t->nsftids * sizeof(*t->ftid_tab);
f2b7e78d 3416
b8ff05a9
DM
3417 t->tid_tab = t4_alloc_mem(size);
3418 if (!t->tid_tab)
3419 return -ENOMEM;
3420
3421 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3422 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 3423 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 3424 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
b8ff05a9
DM
3425 spin_lock_init(&t->stid_lock);
3426 spin_lock_init(&t->atid_lock);
3427
3428 t->stids_in_use = 0;
3429 t->afree = NULL;
3430 t->atids_in_use = 0;
3431 atomic_set(&t->tids_in_use, 0);
3432
3433 /* Setup the free list for atid_tab and clear the stid bitmap. */
3434 if (natids) {
3435 while (--natids)
3436 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3437 t->afree = t->atid_tab;
3438 }
dca4faeb 3439 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
b6f8eaec
KS
3440 /* Reserve stid 0 for T4/T5 adapters */
3441 if (!t->stid_base &&
3442 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3443 __set_bit(0, t->stid_bmap);
3444
b8ff05a9
DM
3445 return 0;
3446}
3447
01bcca68
VP
3448static int cxgb4_clip_get(const struct net_device *dev,
3449 const struct in6_addr *lip)
3450{
3451 struct adapter *adap;
3452 struct fw_clip_cmd c;
3453
3454 adap = netdev2adap(dev);
3455 memset(&c, 0, sizeof(c));
3456 c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3457 FW_CMD_REQUEST | FW_CMD_WRITE);
3458 c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_ALLOC | FW_LEN16(c));
12f2a479
JP
3459 c.ip_hi = *(__be64 *)(lip->s6_addr);
3460 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
01bcca68
VP
3461 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3462}
3463
3464static int cxgb4_clip_release(const struct net_device *dev,
3465 const struct in6_addr *lip)
3466{
3467 struct adapter *adap;
3468 struct fw_clip_cmd c;
3469
3470 adap = netdev2adap(dev);
3471 memset(&c, 0, sizeof(c));
3472 c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3473 FW_CMD_REQUEST | FW_CMD_READ);
3474 c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_FREE | FW_LEN16(c));
12f2a479
JP
3475 c.ip_hi = *(__be64 *)(lip->s6_addr);
3476 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
01bcca68
VP
3477 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3478}
3479
b8ff05a9
DM
3480/**
3481 * cxgb4_create_server - create an IP server
3482 * @dev: the device
3483 * @stid: the server TID
3484 * @sip: local IP address to bind server to
3485 * @sport: the server's TCP port
3486 * @queue: queue to direct messages from this server to
3487 *
3488 * Create an IP server for the given port and address.
3489 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3490 */
3491int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP
3492 __be32 sip, __be16 sport, __be16 vlan,
3493 unsigned int queue)
b8ff05a9
DM
3494{
3495 unsigned int chan;
3496 struct sk_buff *skb;
3497 struct adapter *adap;
3498 struct cpl_pass_open_req *req;
80f40c1f 3499 int ret;
b8ff05a9
DM
3500
3501 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3502 if (!skb)
3503 return -ENOMEM;
3504
3505 adap = netdev2adap(dev);
3506 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3507 INIT_TP_WR(req, 0);
3508 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3509 req->local_port = sport;
3510 req->peer_port = htons(0);
3511 req->local_ip = sip;
3512 req->peer_ip = htonl(0);
e46dab4d 3513 chan = rxq_to_chan(&adap->sge, queue);
b8ff05a9
DM
3514 req->opt0 = cpu_to_be64(TX_CHAN(chan));
3515 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3516 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
80f40c1f
VP
3517 ret = t4_mgmt_tx(adap, skb);
3518 return net_xmit_eval(ret);
b8ff05a9
DM
3519}
3520EXPORT_SYMBOL(cxgb4_create_server);
3521
80f40c1f
VP
3522/* cxgb4_create_server6 - create an IPv6 server
3523 * @dev: the device
3524 * @stid: the server TID
3525 * @sip: local IPv6 address to bind server to
3526 * @sport: the server's TCP port
3527 * @queue: queue to direct messages from this server to
3528 *
3529 * Create an IPv6 server for the given port and address.
3530 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3531 */
3532int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3533 const struct in6_addr *sip, __be16 sport,
3534 unsigned int queue)
3535{
3536 unsigned int chan;
3537 struct sk_buff *skb;
3538 struct adapter *adap;
3539 struct cpl_pass_open_req6 *req;
3540 int ret;
3541
3542 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3543 if (!skb)
3544 return -ENOMEM;
3545
3546 adap = netdev2adap(dev);
3547 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3548 INIT_TP_WR(req, 0);
3549 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3550 req->local_port = sport;
3551 req->peer_port = htons(0);
3552 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3553 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3554 req->peer_ip_hi = cpu_to_be64(0);
3555 req->peer_ip_lo = cpu_to_be64(0);
3556 chan = rxq_to_chan(&adap->sge, queue);
3557 req->opt0 = cpu_to_be64(TX_CHAN(chan));
3558 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3559 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3560 ret = t4_mgmt_tx(adap, skb);
3561 return net_xmit_eval(ret);
3562}
3563EXPORT_SYMBOL(cxgb4_create_server6);
3564
3565int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3566 unsigned int queue, bool ipv6)
3567{
3568 struct sk_buff *skb;
3569 struct adapter *adap;
3570 struct cpl_close_listsvr_req *req;
3571 int ret;
3572
3573 adap = netdev2adap(dev);
3574
3575 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3576 if (!skb)
3577 return -ENOMEM;
3578
3579 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3580 INIT_TP_WR(req, 0);
3581 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3582 req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3583 LISTSVR_IPV6(0)) | QUEUENO(queue));
3584 ret = t4_mgmt_tx(adap, skb);
3585 return net_xmit_eval(ret);
3586}
3587EXPORT_SYMBOL(cxgb4_remove_server);
3588
b8ff05a9
DM
3589/**
3590 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3591 * @mtus: the HW MTU table
3592 * @mtu: the target MTU
3593 * @idx: index of selected entry in the MTU table
3594 *
3595 * Returns the index and the value in the HW MTU table that is closest to
3596 * but does not exceed @mtu, unless @mtu is smaller than any value in the
3597 * table, in which case that smallest available value is selected.
3598 */
3599unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3600 unsigned int *idx)
3601{
3602 unsigned int i = 0;
3603
3604 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3605 ++i;
3606 if (idx)
3607 *idx = i;
3608 return mtus[i];
3609}
3610EXPORT_SYMBOL(cxgb4_best_mtu);
3611
92e7ae71
HS
3612/**
3613 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3614 * @mtus: the HW MTU table
3615 * @header_size: Header Size
3616 * @data_size_max: maximum Data Segment Size
3617 * @data_size_align: desired Data Segment Size Alignment (2^N)
3618 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3619 *
3620 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
3621 * MTU Table based solely on a Maximum MTU parameter, we break that
3622 * parameter up into a Header Size and Maximum Data Segment Size, and
3623 * provide a desired Data Segment Size Alignment. If we find an MTU in
3624 * the Hardware MTU Table which will result in a Data Segment Size with
3625 * the requested alignment _and_ that MTU isn't "too far" from the
3626 * closest MTU, then we'll return that rather than the closest MTU.
3627 */
3628unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3629 unsigned short header_size,
3630 unsigned short data_size_max,
3631 unsigned short data_size_align,
3632 unsigned int *mtu_idxp)
3633{
3634 unsigned short max_mtu = header_size + data_size_max;
3635 unsigned short data_size_align_mask = data_size_align - 1;
3636 int mtu_idx, aligned_mtu_idx;
3637
3638 /* Scan the MTU Table till we find an MTU which is larger than our
3639 * Maximum MTU or we reach the end of the table. Along the way,
3640 * record the last MTU found, if any, which will result in a Data
3641 * Segment Length matching the requested alignment.
3642 */
3643 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3644 unsigned short data_size = mtus[mtu_idx] - header_size;
3645
3646 /* If this MTU minus the Header Size would result in a
3647 * Data Segment Size of the desired alignment, remember it.
3648 */
3649 if ((data_size & data_size_align_mask) == 0)
3650 aligned_mtu_idx = mtu_idx;
3651
3652 /* If we're not at the end of the Hardware MTU Table and the
3653 * next element is larger than our Maximum MTU, drop out of
3654 * the loop.
3655 */
3656 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3657 break;
3658 }
3659
3660 /* If we fell out of the loop because we ran to the end of the table,
3661 * then we just have to use the last [largest] entry.
3662 */
3663 if (mtu_idx == NMTUS)
3664 mtu_idx--;
3665
3666 /* If we found an MTU which resulted in the requested Data Segment
3667 * Length alignment and that's "not far" from the largest MTU which is
3668 * less than or equal to the maximum MTU, then use that.
3669 */
3670 if (aligned_mtu_idx >= 0 &&
3671 mtu_idx - aligned_mtu_idx <= 1)
3672 mtu_idx = aligned_mtu_idx;
3673
3674 /* If the caller has passed in an MTU Index pointer, pass the
3675 * MTU Index back. Return the MTU value.
3676 */
3677 if (mtu_idxp)
3678 *mtu_idxp = mtu_idx;
3679 return mtus[mtu_idx];
3680}
3681EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3682
b8ff05a9
DM
3683/**
3684 * cxgb4_port_chan - get the HW channel of a port
3685 * @dev: the net device for the port
3686 *
3687 * Return the HW Tx channel of the given port.
3688 */
3689unsigned int cxgb4_port_chan(const struct net_device *dev)
3690{
3691 return netdev2pinfo(dev)->tx_chan;
3692}
3693EXPORT_SYMBOL(cxgb4_port_chan);
3694
881806bc
VP
3695unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3696{
3697 struct adapter *adap = netdev2adap(dev);
2cc301d2 3698 u32 v1, v2, lp_count, hp_count;
881806bc 3699
2cc301d2
SR
3700 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3701 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
d14807dd 3702 if (is_t4(adap->params.chip)) {
2cc301d2
SR
3703 lp_count = G_LP_COUNT(v1);
3704 hp_count = G_HP_COUNT(v1);
3705 } else {
3706 lp_count = G_LP_COUNT_T5(v1);
3707 hp_count = G_HP_COUNT_T5(v2);
3708 }
3709 return lpfifo ? lp_count : hp_count;
881806bc
VP
3710}
3711EXPORT_SYMBOL(cxgb4_dbfifo_count);
3712
b8ff05a9
DM
3713/**
3714 * cxgb4_port_viid - get the VI id of a port
3715 * @dev: the net device for the port
3716 *
3717 * Return the VI id of the given port.
3718 */
3719unsigned int cxgb4_port_viid(const struct net_device *dev)
3720{
3721 return netdev2pinfo(dev)->viid;
3722}
3723EXPORT_SYMBOL(cxgb4_port_viid);
3724
3725/**
3726 * cxgb4_port_idx - get the index of a port
3727 * @dev: the net device for the port
3728 *
3729 * Return the index of the given port.
3730 */
3731unsigned int cxgb4_port_idx(const struct net_device *dev)
3732{
3733 return netdev2pinfo(dev)->port_id;
3734}
3735EXPORT_SYMBOL(cxgb4_port_idx);
3736
b8ff05a9
DM
3737void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3738 struct tp_tcp_stats *v6)
3739{
3740 struct adapter *adap = pci_get_drvdata(pdev);
3741
3742 spin_lock(&adap->stats_lock);
3743 t4_tp_get_tcp_stats(adap, v4, v6);
3744 spin_unlock(&adap->stats_lock);
3745}
3746EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3747
3748void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3749 const unsigned int *pgsz_order)
3750{
3751 struct adapter *adap = netdev2adap(dev);
3752
3753 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3754 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3755 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3756 HPZ3(pgsz_order[3]));
3757}
3758EXPORT_SYMBOL(cxgb4_iscsi_init);
3759
3069ee9b
VP
3760int cxgb4_flush_eq_cache(struct net_device *dev)
3761{
3762 struct adapter *adap = netdev2adap(dev);
3763 int ret;
3764
3765 ret = t4_fwaddrspace_write(adap, adap->mbox,
3766 0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3767 return ret;
3768}
3769EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3770
3771static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3772{
3773 u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3774 __be64 indices;
3775 int ret;
3776
fc5ab020
HS
3777 spin_lock(&adap->win0_lock);
3778 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3779 sizeof(indices), (__be32 *)&indices,
3780 T4_MEMORY_READ);
3781 spin_unlock(&adap->win0_lock);
3069ee9b 3782 if (!ret) {
404d9e3f
VP
3783 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3784 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP
3785 }
3786 return ret;
3787}
3788
3789int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3790 u16 size)
3791{
3792 struct adapter *adap = netdev2adap(dev);
3793 u16 hw_pidx, hw_cidx;
3794 int ret;
3795
3796 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3797 if (ret)
3798 goto out;
3799
3800 if (pidx != hw_pidx) {
3801 u16 delta;
3802
3803 if (pidx >= hw_pidx)
3804 delta = pidx - hw_pidx;
3805 else
3806 delta = size - hw_pidx + pidx;
3807 wmb();
840f3000
VP
3808 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3809 QID(qid) | PIDX(delta));
3069ee9b
VP
3810 }
3811out:
3812 return ret;
3813}
3814EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3815
3cbdb928
VP
3816void cxgb4_disable_db_coalescing(struct net_device *dev)
3817{
3818 struct adapter *adap;
3819
3820 adap = netdev2adap(dev);
3821 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3822 F_NOCOALESCE);
3823}
3824EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3825
3826void cxgb4_enable_db_coalescing(struct net_device *dev)
3827{
3828 struct adapter *adap;
3829
3830 adap = netdev2adap(dev);
3831 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3832}
3833EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3834
b8ff05a9
DM
3835static struct pci_driver cxgb4_driver;
3836
3837static void check_neigh_update(struct neighbour *neigh)
3838{
3839 const struct device *parent;
3840 const struct net_device *netdev = neigh->dev;
3841
3842 if (netdev->priv_flags & IFF_802_1Q_VLAN)
3843 netdev = vlan_dev_real_dev(netdev);
3844 parent = netdev->dev.parent;
3845 if (parent && parent->driver == &cxgb4_driver.driver)
3846 t4_l2t_update(dev_get_drvdata(parent), neigh);
3847}
3848
3849static int netevent_cb(struct notifier_block *nb, unsigned long event,
3850 void *data)
3851{
3852 switch (event) {
3853 case NETEVENT_NEIGH_UPDATE:
3854 check_neigh_update(data);
3855 break;
b8ff05a9
DM
3856 case NETEVENT_REDIRECT:
3857 default:
3858 break;
3859 }
3860 return 0;
3861}
3862
3863static bool netevent_registered;
3864static struct notifier_block cxgb4_netevent_nb = {
3865 .notifier_call = netevent_cb
3866};
3867
3069ee9b
VP
3868static void drain_db_fifo(struct adapter *adap, int usecs)
3869{
2cc301d2 3870 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP
3871
3872 do {
2cc301d2
SR
3873 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3874 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
d14807dd 3875 if (is_t4(adap->params.chip)) {
2cc301d2
SR
3876 lp_count = G_LP_COUNT(v1);
3877 hp_count = G_HP_COUNT(v1);
3878 } else {
3879 lp_count = G_LP_COUNT_T5(v1);
3880 hp_count = G_HP_COUNT_T5(v2);
3881 }
3882
3883 if (lp_count == 0 && hp_count == 0)
3884 break;
3069ee9b
VP
3885 set_current_state(TASK_UNINTERRUPTIBLE);
3886 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP
3887 } while (1);
3888}
3889
3890static void disable_txq_db(struct sge_txq *q)
3891{
05eb2389
SW
3892 unsigned long flags;
3893
3894 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 3895 q->db_disabled = 1;
05eb2389 3896 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP
3897}
3898
05eb2389 3899static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP
3900{
3901 spin_lock_irq(&q->db_lock);
05eb2389
SW
3902 if (q->db_pidx_inc) {
3903 /* Make sure that all writes to the TX descriptors
3904 * are committed before we tell HW about them.
3905 */
3906 wmb();
3907 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3908 QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3909 q->db_pidx_inc = 0;
3910 }
3069ee9b
VP
3911 q->db_disabled = 0;
3912 spin_unlock_irq(&q->db_lock);
3913}
3914
3915static void disable_dbs(struct adapter *adap)
3916{
3917 int i;
3918
3919 for_each_ethrxq(&adap->sge, i)
3920 disable_txq_db(&adap->sge.ethtxq[i].q);
3921 for_each_ofldrxq(&adap->sge, i)
3922 disable_txq_db(&adap->sge.ofldtxq[i].q);
3923 for_each_port(adap, i)
3924 disable_txq_db(&adap->sge.ctrlq[i].q);
3925}
3926
3927static void enable_dbs(struct adapter *adap)
3928{
3929 int i;
3930
3931 for_each_ethrxq(&adap->sge, i)
05eb2389 3932 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3069ee9b 3933 for_each_ofldrxq(&adap->sge, i)
05eb2389 3934 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3069ee9b 3935 for_each_port(adap, i)
05eb2389
SW
3936 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
3937}
3938
3939static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
3940{
3941 if (adap->uld_handle[CXGB4_ULD_RDMA])
3942 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
3943 cmd);
3944}
3945
3946static void process_db_full(struct work_struct *work)
3947{
3948 struct adapter *adap;
3949
3950 adap = container_of(work, struct adapter, db_full_task);
3951
3952 drain_db_fifo(adap, dbfifo_drain_delay);
3953 enable_dbs(adap);
3954 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3955 t4_set_reg_field(adap, SGE_INT_ENABLE3,
3956 DBFIFO_HP_INT | DBFIFO_LP_INT,
3957 DBFIFO_HP_INT | DBFIFO_LP_INT);
3069ee9b
VP
3958}
3959
3960static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
3961{
3962 u16 hw_pidx, hw_cidx;
3963 int ret;
3964
05eb2389 3965 spin_lock_irq(&q->db_lock);
3069ee9b
VP
3966 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
3967 if (ret)
3968 goto out;
3969 if (q->db_pidx != hw_pidx) {
3970 u16 delta;
3971
3972 if (q->db_pidx >= hw_pidx)
3973 delta = q->db_pidx - hw_pidx;
3974 else
3975 delta = q->size - hw_pidx + q->db_pidx;
3976 wmb();
840f3000
VP
3977 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3978 QID(q->cntxt_id) | PIDX(delta));
3069ee9b
VP
3979 }
3980out:
3981 q->db_disabled = 0;
05eb2389
SW
3982 q->db_pidx_inc = 0;
3983 spin_unlock_irq(&q->db_lock);
3069ee9b
VP
3984 if (ret)
3985 CH_WARN(adap, "DB drop recovery failed.\n");
3986}
3987static void recover_all_queues(struct adapter *adap)
3988{
3989 int i;
3990
3991 for_each_ethrxq(&adap->sge, i)
3992 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
3993 for_each_ofldrxq(&adap->sge, i)
3994 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
3995 for_each_port(adap, i)
3996 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
3997}
3998
881806bc
VP
3999static void process_db_drop(struct work_struct *work)
4000{
4001 struct adapter *adap;
881806bc 4002
3069ee9b 4003 adap = container_of(work, struct adapter, db_drop_task);
881806bc 4004
d14807dd 4005 if (is_t4(adap->params.chip)) {
05eb2389 4006 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4007 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 4008 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4009 recover_all_queues(adap);
05eb2389 4010 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 4011 enable_dbs(adap);
05eb2389 4012 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2cc301d2
SR
4013 } else {
4014 u32 dropped_db = t4_read_reg(adap, 0x010ac);
4015 u16 qid = (dropped_db >> 15) & 0x1ffff;
4016 u16 pidx_inc = dropped_db & 0x1fff;
4017 unsigned int s_qpp;
4018 unsigned short udb_density;
4019 unsigned long qpshift;
4020 int page;
4021 u32 udb;
4022
4023 dev_warn(adap->pdev_dev,
4024 "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4025 dropped_db, qid,
4026 (dropped_db >> 14) & 1,
4027 (dropped_db >> 13) & 1,
4028 pidx_inc);
4029
4030 drain_db_fifo(adap, 1);
4031
4032 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
4033 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
4034 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
4035 qpshift = PAGE_SHIFT - ilog2(udb_density);
4036 udb = qid << qpshift;
4037 udb &= PAGE_MASK;
4038 page = udb / PAGE_SIZE;
4039 udb += (qid - (page * udb_density)) * 128;
4040
4041 writel(PIDX(pidx_inc), adap->bar2 + udb + 8);
4042
4043 /* Re-enable BAR2 WC */
4044 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4045 }
4046
3069ee9b 4047 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
881806bc
VP
4048}
4049
4050void t4_db_full(struct adapter *adap)
4051{
d14807dd 4052 if (is_t4(adap->params.chip)) {
05eb2389
SW
4053 disable_dbs(adap);
4054 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2cc301d2
SR
4055 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4056 DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4057 queue_work(workq, &adap->db_full_task);
4058 }
881806bc
VP
4059}
4060
4061void t4_db_dropped(struct adapter *adap)
4062{
05eb2389
SW
4063 if (is_t4(adap->params.chip)) {
4064 disable_dbs(adap);
4065 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4066 }
4067 queue_work(workq, &adap->db_drop_task);
881806bc
VP
4068}
4069
b8ff05a9
DM
4070static void uld_attach(struct adapter *adap, unsigned int uld)
4071{
4072 void *handle;
4073 struct cxgb4_lld_info lli;
dca4faeb 4074 unsigned short i;
b8ff05a9
DM
4075
4076 lli.pdev = adap->pdev;
35b1de55 4077 lli.pf = adap->fn;
b8ff05a9
DM
4078 lli.l2t = adap->l2t;
4079 lli.tids = &adap->tids;
4080 lli.ports = adap->port;
4081 lli.vr = &adap->vres;
4082 lli.mtus = adap->params.mtus;
4083 if (uld == CXGB4_ULD_RDMA) {
4084 lli.rxq_ids = adap->sge.rdma_rxq;
cf38be6d 4085 lli.ciq_ids = adap->sge.rdma_ciq;
b8ff05a9 4086 lli.nrxq = adap->sge.rdmaqs;
cf38be6d 4087 lli.nciq = adap->sge.rdmaciqs;
b8ff05a9
DM
4088 } else if (uld == CXGB4_ULD_ISCSI) {
4089 lli.rxq_ids = adap->sge.ofld_rxq;
4090 lli.nrxq = adap->sge.ofldqsets;
4091 }
4092 lli.ntxq = adap->sge.ofldqsets;
4093 lli.nchan = adap->params.nports;
4094 lli.nports = adap->params.nports;
4095 lli.wr_cred = adap->params.ofldq_wr_cred;
d14807dd 4096 lli.adapter_type = adap->params.chip;
b8ff05a9
DM
4097 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
4098 lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
060e0c75
DM
4099 t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4100 (adap->fn * 4));
b8ff05a9 4101 lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
060e0c75
DM
4102 t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4103 (adap->fn * 4));
dcf7b6f5 4104 lli.filt_mode = adap->params.tp.vlan_pri_map;
dca4faeb
VP
4105 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4106 for (i = 0; i < NCHAN; i++)
4107 lli.tx_modq[i] = i;
b8ff05a9
DM
4108 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4109 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4110 lli.fw_vers = adap->params.fw_vers;
3069ee9b 4111 lli.dbfifo_int_thresh = dbfifo_int_thresh;
04e10e21
HS
4112 lli.sge_ingpadboundary = adap->sge.fl_align;
4113 lli.sge_egrstatuspagesize = adap->sge.stat_len;
dca4faeb
VP
4114 lli.sge_pktshift = adap->sge.pktshift;
4115 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4c2c5763
HS
4116 lli.max_ordird_qp = adap->params.max_ordird_qp;
4117 lli.max_ird_adapter = adap->params.max_ird_adapter;
1ac0f095 4118 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
b8ff05a9
DM
4119
4120 handle = ulds[uld].add(&lli);
4121 if (IS_ERR(handle)) {
4122 dev_warn(adap->pdev_dev,
4123 "could not attach to the %s driver, error %ld\n",
4124 uld_str[uld], PTR_ERR(handle));
4125 return;
4126 }
4127
4128 adap->uld_handle[uld] = handle;
4129
4130 if (!netevent_registered) {
4131 register_netevent_notifier(&cxgb4_netevent_nb);
4132 netevent_registered = true;
4133 }
e29f5dbc
DM
4134
4135 if (adap->flags & FULL_INIT_DONE)
4136 ulds[uld].state_change(handle, CXGB4_STATE_UP);
b8ff05a9
DM
4137}
4138
4139static void attach_ulds(struct adapter *adap)
4140{
4141 unsigned int i;
4142
01bcca68
VP
4143 spin_lock(&adap_rcu_lock);
4144 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4145 spin_unlock(&adap_rcu_lock);
4146
b8ff05a9
DM
4147 mutex_lock(&uld_mutex);
4148 list_add_tail(&adap->list_node, &adapter_list);
4149 for (i = 0; i < CXGB4_ULD_MAX; i++)
4150 if (ulds[i].add)
4151 uld_attach(adap, i);
4152 mutex_unlock(&uld_mutex);
4153}
4154
4155static void detach_ulds(struct adapter *adap)
4156{
4157 unsigned int i;
4158
4159 mutex_lock(&uld_mutex);
4160 list_del(&adap->list_node);
4161 for (i = 0; i < CXGB4_ULD_MAX; i++)
4162 if (adap->uld_handle[i]) {
4163 ulds[i].state_change(adap->uld_handle[i],
4164 CXGB4_STATE_DETACH);
4165 adap->uld_handle[i] = NULL;
4166 }
4167 if (netevent_registered && list_empty(&adapter_list)) {
4168 unregister_netevent_notifier(&cxgb4_netevent_nb);
4169 netevent_registered = false;
4170 }
4171 mutex_unlock(&uld_mutex);
01bcca68
VP
4172
4173 spin_lock(&adap_rcu_lock);
4174 list_del_rcu(&adap->rcu_node);
4175 spin_unlock(&adap_rcu_lock);
b8ff05a9
DM
4176}
4177
4178static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4179{
4180 unsigned int i;
4181
4182 mutex_lock(&uld_mutex);
4183 for (i = 0; i < CXGB4_ULD_MAX; i++)
4184 if (adap->uld_handle[i])
4185 ulds[i].state_change(adap->uld_handle[i], new_state);
4186 mutex_unlock(&uld_mutex);
4187}
4188
4189/**
4190 * cxgb4_register_uld - register an upper-layer driver
4191 * @type: the ULD type
4192 * @p: the ULD methods
4193 *
4194 * Registers an upper-layer driver with this driver and notifies the ULD
4195 * about any presently available devices that support its type. Returns
4196 * %-EBUSY if a ULD of the same type is already registered.
4197 */
4198int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4199{
4200 int ret = 0;
4201 struct adapter *adap;
4202
4203 if (type >= CXGB4_ULD_MAX)
4204 return -EINVAL;
4205 mutex_lock(&uld_mutex);
4206 if (ulds[type].add) {
4207 ret = -EBUSY;
4208 goto out;
4209 }
4210 ulds[type] = *p;
4211 list_for_each_entry(adap, &adapter_list, list_node)
4212 uld_attach(adap, type);
4213out: mutex_unlock(&uld_mutex);
4214 return ret;
4215}
4216EXPORT_SYMBOL(cxgb4_register_uld);
4217
4218/**
4219 * cxgb4_unregister_uld - unregister an upper-layer driver
4220 * @type: the ULD type
4221 *
4222 * Unregisters an existing upper-layer driver.
4223 */
4224int cxgb4_unregister_uld(enum cxgb4_uld type)
4225{
4226 struct adapter *adap;
4227
4228 if (type >= CXGB4_ULD_MAX)
4229 return -EINVAL;
4230 mutex_lock(&uld_mutex);
4231 list_for_each_entry(adap, &adapter_list, list_node)
4232 adap->uld_handle[type] = NULL;
4233 ulds[type].add = NULL;
4234 mutex_unlock(&uld_mutex);
4235 return 0;
4236}
4237EXPORT_SYMBOL(cxgb4_unregister_uld);
4238
01bcca68 4239/* Check if netdev on which event is occured belongs to us or not. Return
ee9a33b2
LR
4240 * success (true) if it belongs otherwise failure (false).
4241 * Called with rcu_read_lock() held.
01bcca68 4242 */
ee9a33b2 4243static bool cxgb4_netdev(const struct net_device *netdev)
01bcca68
VP
4244{
4245 struct adapter *adap;
4246 int i;
4247
01bcca68
VP
4248 list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4249 for (i = 0; i < MAX_NPORTS; i++)
ee9a33b2
LR
4250 if (adap->port[i] == netdev)
4251 return true;
4252 return false;
01bcca68
VP
4253}
4254
4255static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4256 unsigned long event)
4257{
4258 int ret = NOTIFY_DONE;
4259
4260 rcu_read_lock();
4261 if (cxgb4_netdev(event_dev)) {
4262 switch (event) {
4263 case NETDEV_UP:
4264 ret = cxgb4_clip_get(event_dev,
4265 (const struct in6_addr *)ifa->addr.s6_addr);
4266 if (ret < 0) {
4267 rcu_read_unlock();
4268 return ret;
4269 }
4270 ret = NOTIFY_OK;
4271 break;
4272 case NETDEV_DOWN:
4273 cxgb4_clip_release(event_dev,
4274 (const struct in6_addr *)ifa->addr.s6_addr);
4275 ret = NOTIFY_OK;
4276 break;
4277 default:
4278 break;
4279 }
4280 }
4281 rcu_read_unlock();
4282 return ret;
4283}
4284
4285static int cxgb4_inet6addr_handler(struct notifier_block *this,
4286 unsigned long event, void *data)
4287{
4288 struct inet6_ifaddr *ifa = data;
4289 struct net_device *event_dev;
4290 int ret = NOTIFY_DONE;
01bcca68 4291 struct bonding *bond = netdev_priv(ifa->idev->dev);
9caff1e7 4292 struct list_head *iter;
01bcca68
VP
4293 struct slave *slave;
4294 struct pci_dev *first_pdev = NULL;
4295
4296 if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4297 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4298 ret = clip_add(event_dev, ifa, event);
4299 } else if (ifa->idev->dev->flags & IFF_MASTER) {
4300 /* It is possible that two different adapters are bonded in one
4301 * bond. We need to find such different adapters and add clip
4302 * in all of them only once.
4303 */
4304 read_lock(&bond->lock);
9caff1e7 4305 bond_for_each_slave(bond, slave, iter) {
01bcca68
VP
4306 if (!first_pdev) {
4307 ret = clip_add(slave->dev, ifa, event);
4308 /* If clip_add is success then only initialize
4309 * first_pdev since it means it is our device
4310 */
4311 if (ret == NOTIFY_OK)
4312 first_pdev = to_pci_dev(
4313 slave->dev->dev.parent);
4314 } else if (first_pdev !=
4315 to_pci_dev(slave->dev->dev.parent))
4316 ret = clip_add(slave->dev, ifa, event);
4317 }
4318 read_unlock(&bond->lock);
4319 } else
4320 ret = clip_add(ifa->idev->dev, ifa, event);
4321
4322 return ret;
4323}
4324
4325static struct notifier_block cxgb4_inet6addr_notifier = {
4326 .notifier_call = cxgb4_inet6addr_handler
4327};
4328
4329/* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4330 * a physical device.
4331 * The physical device reference is needed to send the actul CLIP command.
4332 */
4333static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4334{
4335 struct inet6_dev *idev = NULL;
4336 struct inet6_ifaddr *ifa;
4337 int ret = 0;
4338
4339 idev = __in6_dev_get(root_dev);
4340 if (!idev)
4341 return ret;
4342
4343 read_lock_bh(&idev->lock);
4344 list_for_each_entry(ifa, &idev->addr_list, if_list) {
4345 ret = cxgb4_clip_get(dev,
4346 (const struct in6_addr *)ifa->addr.s6_addr);
4347 if (ret < 0)
4348 break;
4349 }
4350 read_unlock_bh(&idev->lock);
4351
4352 return ret;
4353}
4354
4355static int update_root_dev_clip(struct net_device *dev)
4356{
4357 struct net_device *root_dev = NULL;
4358 int i, ret = 0;
4359
4360 /* First populate the real net device's IPv6 addresses */
4361 ret = update_dev_clip(dev, dev);
4362 if (ret)
4363 return ret;
4364
4365 /* Parse all bond and vlan devices layered on top of the physical dev */
4366 for (i = 0; i < VLAN_N_VID; i++) {
f06c7f9f 4367 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
01bcca68
VP
4368 if (!root_dev)
4369 continue;
4370
4371 ret = update_dev_clip(root_dev, dev);
4372 if (ret)
4373 break;
4374 }
4375 return ret;
4376}
4377
4378static void update_clip(const struct adapter *adap)
4379{
4380 int i;
4381 struct net_device *dev;
4382 int ret;
4383
4384 rcu_read_lock();
4385
4386 for (i = 0; i < MAX_NPORTS; i++) {
4387 dev = adap->port[i];
4388 ret = 0;
4389
4390 if (dev)
4391 ret = update_root_dev_clip(dev);
4392
4393 if (ret < 0)
4394 break;
4395 }
4396 rcu_read_unlock();
4397}
4398
b8ff05a9
DM
4399/**
4400 * cxgb_up - enable the adapter
4401 * @adap: adapter being enabled
4402 *
4403 * Called when the first port is enabled, this function performs the
4404 * actions necessary to make an adapter operational, such as completing
4405 * the initialization of HW modules, and enabling interrupts.
4406 *
4407 * Must be called with the rtnl lock held.
4408 */
4409static int cxgb_up(struct adapter *adap)
4410{
aaefae9b 4411 int err;
b8ff05a9 4412
aaefae9b
DM
4413 err = setup_sge_queues(adap);
4414 if (err)
4415 goto out;
4416 err = setup_rss(adap);
4417 if (err)
4418 goto freeq;
b8ff05a9
DM
4419
4420 if (adap->flags & USING_MSIX) {
aaefae9b 4421 name_msix_vecs(adap);
b8ff05a9
DM
4422 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4423 adap->msix_info[0].desc, adap);
4424 if (err)
4425 goto irq_err;
4426
4427 err = request_msix_queue_irqs(adap);
4428 if (err) {
4429 free_irq(adap->msix_info[0].vec, adap);
4430 goto irq_err;
4431 }
4432 } else {
4433 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4434 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 4435 adap->port[0]->name, adap);
b8ff05a9
DM
4436 if (err)
4437 goto irq_err;
4438 }
4439 enable_rx(adap);
4440 t4_sge_start(adap);
4441 t4_intr_enable(adap);
aaefae9b 4442 adap->flags |= FULL_INIT_DONE;
b8ff05a9 4443 notify_ulds(adap, CXGB4_STATE_UP);
01bcca68 4444 update_clip(adap);
b8ff05a9
DM
4445 out:
4446 return err;
4447 irq_err:
4448 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM
4449 freeq:
4450 t4_free_sge_resources(adap);
b8ff05a9
DM
4451 goto out;
4452}
4453
4454static void cxgb_down(struct adapter *adapter)
4455{
4456 t4_intr_disable(adapter);
4457 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP
4458 cancel_work_sync(&adapter->db_full_task);
4459 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 4460 adapter->tid_release_task_busy = false;
204dc3c0 4461 adapter->tid_release_head = NULL;
b8ff05a9
DM
4462
4463 if (adapter->flags & USING_MSIX) {
4464 free_msix_queue_irqs(adapter);
4465 free_irq(adapter->msix_info[0].vec, adapter);
4466 } else
4467 free_irq(adapter->pdev->irq, adapter);
4468 quiesce_rx(adapter);
aaefae9b
DM
4469 t4_sge_stop(adapter);
4470 t4_free_sge_resources(adapter);
4471 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM
4472}
4473
4474/*
4475 * net_device operations
4476 */
4477static int cxgb_open(struct net_device *dev)
4478{
4479 int err;
4480 struct port_info *pi = netdev_priv(dev);
4481 struct adapter *adapter = pi->adapter;
4482
6a3c869a
DM
4483 netif_carrier_off(dev);
4484
aaefae9b
DM
4485 if (!(adapter->flags & FULL_INIT_DONE)) {
4486 err = cxgb_up(adapter);
4487 if (err < 0)
4488 return err;
4489 }
b8ff05a9 4490
f68707b8
DM
4491 err = link_start(dev);
4492 if (!err)
4493 netif_tx_start_all_queues(dev);
4494 return err;
b8ff05a9
DM
4495}
4496
4497static int cxgb_close(struct net_device *dev)
4498{
b8ff05a9
DM
4499 struct port_info *pi = netdev_priv(dev);
4500 struct adapter *adapter = pi->adapter;
4501
4502 netif_tx_stop_all_queues(dev);
4503 netif_carrier_off(dev);
060e0c75 4504 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
b8ff05a9
DM
4505}
4506
f2b7e78d
VP
4507/* Return an error number if the indicated filter isn't writable ...
4508 */
4509static int writable_filter(struct filter_entry *f)
4510{
4511 if (f->locked)
4512 return -EPERM;
4513 if (f->pending)
4514 return -EBUSY;
4515
4516 return 0;
4517}
4518
4519/* Delete the filter at the specified index (if valid). The checks for all
4520 * the common problems with doing this like the filter being locked, currently
4521 * pending in another operation, etc.
4522 */
4523static int delete_filter(struct adapter *adapter, unsigned int fidx)
4524{
4525 struct filter_entry *f;
4526 int ret;
4527
dca4faeb 4528 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
f2b7e78d
VP
4529 return -EINVAL;
4530
4531 f = &adapter->tids.ftid_tab[fidx];
4532 ret = writable_filter(f);
4533 if (ret)
4534 return ret;
4535 if (f->valid)
4536 return del_filter_wr(adapter, fidx);
4537
4538 return 0;
4539}
4540
dca4faeb 4541int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP
4542 __be32 sip, __be16 sport, __be16 vlan,
4543 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP
4544{
4545 int ret;
4546 struct filter_entry *f;
4547 struct adapter *adap;
4548 int i;
4549 u8 *val;
4550
4551 adap = netdev2adap(dev);
4552
1cab775c 4553 /* Adjust stid to correct filter index */
470c60c4 4554 stid -= adap->tids.sftid_base;
1cab775c
VP
4555 stid += adap->tids.nftids;
4556
dca4faeb
VP
4557 /* Check to make sure the filter requested is writable ...
4558 */
4559 f = &adap->tids.ftid_tab[stid];
4560 ret = writable_filter(f);
4561 if (ret)
4562 return ret;
4563
4564 /* Clear out any old resources being used by the filter before
4565 * we start constructing the new filter.
4566 */
4567 if (f->valid)
4568 clear_filter(adap, f);
4569
4570 /* Clear out filter specifications */
4571 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4572 f->fs.val.lport = cpu_to_be16(sport);
4573 f->fs.mask.lport = ~0;
4574 val = (u8 *)&sip;
793dad94 4575 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP
4576 for (i = 0; i < 4; i++) {
4577 f->fs.val.lip[i] = val[i];
4578 f->fs.mask.lip[i] = ~0;
4579 }
dcf7b6f5 4580 if (adap->params.tp.vlan_pri_map & F_PORT) {
793dad94
VP
4581 f->fs.val.iport = port;
4582 f->fs.mask.iport = mask;
4583 }
4584 }
dca4faeb 4585
dcf7b6f5 4586 if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
7c89e555
KS
4587 f->fs.val.proto = IPPROTO_TCP;
4588 f->fs.mask.proto = ~0;
4589 }
4590
dca4faeb
VP
4591 f->fs.dirsteer = 1;
4592 f->fs.iq = queue;
4593 /* Mark filter as locked */
4594 f->locked = 1;
4595 f->fs.rpttid = 1;
4596
4597 ret = set_filter_wr(adap, stid);
4598 if (ret) {
4599 clear_filter(adap, f);
4600 return ret;
4601 }
4602
4603 return 0;
4604}
4605EXPORT_SYMBOL(cxgb4_create_server_filter);
4606
4607int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4608 unsigned int queue, bool ipv6)
4609{
4610 int ret;
4611 struct filter_entry *f;
4612 struct adapter *adap;
4613
4614 adap = netdev2adap(dev);
1cab775c
VP
4615
4616 /* Adjust stid to correct filter index */
470c60c4 4617 stid -= adap->tids.sftid_base;
1cab775c
VP
4618 stid += adap->tids.nftids;
4619
dca4faeb
VP
4620 f = &adap->tids.ftid_tab[stid];
4621 /* Unlock the filter */
4622 f->locked = 0;
4623
4624 ret = delete_filter(adap, stid);
4625 if (ret)
4626 return ret;
4627
4628 return 0;
4629}
4630EXPORT_SYMBOL(cxgb4_remove_server_filter);
4631
f5152c90
DM
4632static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4633 struct rtnl_link_stats64 *ns)
b8ff05a9
DM
4634{
4635 struct port_stats stats;
4636 struct port_info *p = netdev_priv(dev);
4637 struct adapter *adapter = p->adapter;
b8ff05a9 4638
9fe6cb58
GS
4639 /* Block retrieving statistics during EEH error
4640 * recovery. Otherwise, the recovery might fail
4641 * and the PCI device will be removed permanently
4642 */
b8ff05a9 4643 spin_lock(&adapter->stats_lock);
9fe6cb58
GS
4644 if (!netif_device_present(dev)) {
4645 spin_unlock(&adapter->stats_lock);
4646 return ns;
4647 }
b8ff05a9
DM
4648 t4_get_port_stats(adapter, p->tx_chan, &stats);
4649 spin_unlock(&adapter->stats_lock);
4650
4651 ns->tx_bytes = stats.tx_octets;
4652 ns->tx_packets = stats.tx_frames;
4653 ns->rx_bytes = stats.rx_octets;
4654 ns->rx_packets = stats.rx_frames;
4655 ns->multicast = stats.rx_mcast_frames;
4656
4657 /* detailed rx_errors */
4658 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4659 stats.rx_runt;
4660 ns->rx_over_errors = 0;
4661 ns->rx_crc_errors = stats.rx_fcs_err;
4662 ns->rx_frame_errors = stats.rx_symbol_err;
4663 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
4664 stats.rx_ovflow2 + stats.rx_ovflow3 +
4665 stats.rx_trunc0 + stats.rx_trunc1 +
4666 stats.rx_trunc2 + stats.rx_trunc3;
4667 ns->rx_missed_errors = 0;
4668
4669 /* detailed tx_errors */
4670 ns->tx_aborted_errors = 0;
4671 ns->tx_carrier_errors = 0;
4672 ns->tx_fifo_errors = 0;
4673 ns->tx_heartbeat_errors = 0;
4674 ns->tx_window_errors = 0;
4675
4676 ns->tx_errors = stats.tx_error_frames;
4677 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4678 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4679 return ns;
4680}
4681
4682static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4683{
060e0c75 4684 unsigned int mbox;
b8ff05a9
DM
4685 int ret = 0, prtad, devad;
4686 struct port_info *pi = netdev_priv(dev);
4687 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4688
4689 switch (cmd) {
4690 case SIOCGMIIPHY:
4691 if (pi->mdio_addr < 0)
4692 return -EOPNOTSUPP;
4693 data->phy_id = pi->mdio_addr;
4694 break;
4695 case SIOCGMIIREG:
4696 case SIOCSMIIREG:
4697 if (mdio_phy_id_is_c45(data->phy_id)) {
4698 prtad = mdio_phy_id_prtad(data->phy_id);
4699 devad = mdio_phy_id_devad(data->phy_id);
4700 } else if (data->phy_id < 32) {
4701 prtad = data->phy_id;
4702 devad = 0;
4703 data->reg_num &= 0x1f;
4704 } else
4705 return -EINVAL;
4706
060e0c75 4707 mbox = pi->adapter->fn;
b8ff05a9 4708 if (cmd == SIOCGMIIREG)
060e0c75 4709 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM
4710 data->reg_num, &data->val_out);
4711 else
060e0c75 4712 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM
4713 data->reg_num, data->val_in);
4714 break;
4715 default:
4716 return -EOPNOTSUPP;
4717 }
4718 return ret;
4719}
4720
4721static void cxgb_set_rxmode(struct net_device *dev)
4722{
4723 /* unfortunately we can't return errors to the stack */
4724 set_rxmode(dev, -1, false);
4725}
4726
4727static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4728{
4729 int ret;
4730 struct port_info *pi = netdev_priv(dev);
4731
4732 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
4733 return -EINVAL;
060e0c75
DM
4734 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4735 -1, -1, -1, true);
b8ff05a9
DM
4736 if (!ret)
4737 dev->mtu = new_mtu;
4738 return ret;
4739}
4740
4741static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4742{
4743 int ret;
4744 struct sockaddr *addr = p;
4745 struct port_info *pi = netdev_priv(dev);
4746
4747 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 4748 return -EADDRNOTAVAIL;
b8ff05a9 4749
060e0c75
DM
4750 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4751 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM
4752 if (ret < 0)
4753 return ret;
4754
4755 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4756 pi->xact_addr_filt = ret;
4757 return 0;
4758}
4759
b8ff05a9
DM
4760#ifdef CONFIG_NET_POLL_CONTROLLER
4761static void cxgb_netpoll(struct net_device *dev)
4762{
4763 struct port_info *pi = netdev_priv(dev);
4764 struct adapter *adap = pi->adapter;
4765
4766 if (adap->flags & USING_MSIX) {
4767 int i;
4768 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4769
4770 for (i = pi->nqsets; i; i--, rx++)
4771 t4_sge_intr_msix(0, &rx->rspq);
4772 } else
4773 t4_intr_handler(adap)(0, adap);
4774}
4775#endif
4776
4777static const struct net_device_ops cxgb4_netdev_ops = {
4778 .ndo_open = cxgb_open,
4779 .ndo_stop = cxgb_close,
4780 .ndo_start_xmit = t4_eth_xmit,
688848b1 4781 .ndo_select_queue = cxgb_select_queue,
9be793bf 4782 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM
4783 .ndo_set_rx_mode = cxgb_set_rxmode,
4784 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 4785 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM
4786 .ndo_validate_addr = eth_validate_addr,
4787 .ndo_do_ioctl = cxgb_ioctl,
4788 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM
4789#ifdef CONFIG_NET_POLL_CONTROLLER
4790 .ndo_poll_controller = cxgb_netpoll,
4791#endif
4792};
4793
4794void t4_fatal_err(struct adapter *adap)
4795{
4796 t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4797 t4_intr_disable(adap);
4798 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4799}
4800
0abfd152
HS
4801/* Return the specified PCI-E Configuration Space register from our Physical
4802 * Function. We try first via a Firmware LDST Command since we prefer to let
4803 * the firmware own all of these registers, but if that fails we go for it
4804 * directly ourselves.
4805 */
4806static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4807{
4808 struct fw_ldst_cmd ldst_cmd;
4809 u32 val;
4810 int ret;
4811
4812 /* Construct and send the Firmware LDST Command to retrieve the
4813 * specified PCI-E Configuration Space register.
4814 */
4815 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4816 ldst_cmd.op_to_addrspace =
4817 htonl(FW_CMD_OP(FW_LDST_CMD) |
4818 FW_CMD_REQUEST |
4819 FW_CMD_READ |
4820 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
4821 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4822 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
4823 ldst_cmd.u.pcie.ctrl_to_fn =
4824 (FW_LDST_CMD_LC | FW_LDST_CMD_FN(adap->fn));
4825 ldst_cmd.u.pcie.r = reg;
4826 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4827 &ldst_cmd);
4828
4829 /* If the LDST Command suucceeded, exctract the returned register
4830 * value. Otherwise read it directly ourself.
4831 */
4832 if (ret == 0)
4833 val = ntohl(ldst_cmd.u.pcie.data[0]);
4834 else
4835 t4_hw_pci_read_cfg4(adap, reg, &val);
4836
4837 return val;
4838}
4839
b8ff05a9
DM
4840static void setup_memwin(struct adapter *adap)
4841{
0abfd152 4842 u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
b8ff05a9 4843
d14807dd 4844 if (is_t4(adap->params.chip)) {
0abfd152
HS
4845 u32 bar0;
4846
4847 /* Truncation intentional: we only read the bottom 32-bits of
4848 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
4849 * mechanism to read BAR0 instead of using
4850 * pci_resource_start() because we could be operating from
4851 * within a Virtual Machine which is trapping our accesses to
4852 * our Configuration Space and we need to set up the PCI-E
4853 * Memory Window decoders with the actual addresses which will
4854 * be coming across the PCI-E link.
4855 */
4856 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4857 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4858 adap->t4_bar0 = bar0;
4859
19dd37ba
SR
4860 mem_win0_base = bar0 + MEMWIN0_BASE;
4861 mem_win1_base = bar0 + MEMWIN1_BASE;
4862 mem_win2_base = bar0 + MEMWIN2_BASE;
0abfd152 4863 mem_win2_aperture = MEMWIN2_APERTURE;
19dd37ba
SR
4864 } else {
4865 /* For T5, only relative offset inside the PCIe BAR is passed */
4866 mem_win0_base = MEMWIN0_BASE;
0abfd152 4867 mem_win1_base = MEMWIN1_BASE;
19dd37ba 4868 mem_win2_base = MEMWIN2_BASE_T5;
0abfd152 4869 mem_win2_aperture = MEMWIN2_APERTURE_T5;
19dd37ba 4870 }
b8ff05a9 4871 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
19dd37ba 4872 mem_win0_base | BIR(0) |
b8ff05a9
DM
4873 WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4874 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
19dd37ba 4875 mem_win1_base | BIR(0) |
b8ff05a9
DM
4876 WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4877 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
19dd37ba 4878 mem_win2_base | BIR(0) |
0abfd152
HS
4879 WINDOW(ilog2(mem_win2_aperture) - 10));
4880 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
636f9d37
VP
4881}
4882
4883static void setup_memwin_rdma(struct adapter *adap)
4884{
1ae970e0 4885 if (adap->vres.ocq.size) {
0abfd152
HS
4886 u32 start;
4887 unsigned int sz_kb;
1ae970e0 4888
0abfd152
HS
4889 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4890 start &= PCI_BASE_ADDRESS_MEM_MASK;
4891 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM
4892 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4893 t4_write_reg(adap,
4894 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4895 start | BIR(1) | WINDOW(ilog2(sz_kb)));
4896 t4_write_reg(adap,
4897 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4898 adap->vres.ocq.start);
4899 t4_read_reg(adap,
4900 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4901 }
b8ff05a9
DM
4902}
4903
02b5fb8e
DM
4904static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4905{
4906 u32 v;
4907 int ret;
4908
4909 /* get device capabilities */
4910 memset(c, 0, sizeof(*c));
4911 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4912 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 4913 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
060e0c75 4914 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
02b5fb8e
DM
4915 if (ret < 0)
4916 return ret;
4917
4918 /* select capabilities we'll be using */
4919 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4920 if (!vf_acls)
4921 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4922 else
4923 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4924 } else if (vf_acls) {
4925 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
4926 return ret;
4927 }
4928 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4929 FW_CMD_REQUEST | FW_CMD_WRITE);
060e0c75 4930 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
02b5fb8e
DM
4931 if (ret < 0)
4932 return ret;
4933
060e0c75 4934 ret = t4_config_glbl_rss(adap, adap->fn,
02b5fb8e
DM
4935 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4936 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
4937 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
4938 if (ret < 0)
4939 return ret;
4940
060e0c75
DM
4941 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
4942 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
02b5fb8e
DM
4943 if (ret < 0)
4944 return ret;
4945
4946 t4_sge_init(adap);
4947
02b5fb8e
DM
4948 /* tweak some settings */
4949 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
4950 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
4951 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
4952 v = t4_read_reg(adap, TP_PIO_DATA);
4953 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
060e0c75 4954
dca4faeb
VP
4955 /* first 4 Tx modulation queues point to consecutive Tx channels */
4956 adap->params.tp.tx_modq_map = 0xE4;
4957 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
4958 V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
4959
4960 /* associate each Tx modulation queue with consecutive Tx channels */
4961 v = 0x84218421;
4962 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4963 &v, 1, A_TP_TX_SCHED_HDR);
4964 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4965 &v, 1, A_TP_TX_SCHED_FIFO);
4966 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4967 &v, 1, A_TP_TX_SCHED_PCMD);
4968
4969#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
4970 if (is_offload(adap)) {
4971 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
4972 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4973 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4974 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4975 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4976 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
4977 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4978 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4979 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4980 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4981 }
4982
060e0c75
DM
4983 /* get basic stuff going */
4984 return t4_early_init(adap, adap->fn);
02b5fb8e
DM
4985}
4986
b8ff05a9
DM
4987/*
4988 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
4989 */
4990#define MAX_ATIDS 8192U
4991
636f9d37
VP
4992/*
4993 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4994 *
4995 * If the firmware we're dealing with has Configuration File support, then
4996 * we use that to perform all configuration
4997 */
4998
4999/*
5000 * Tweak configuration based on module parameters, etc. Most of these have
5001 * defaults assigned to them by Firmware Configuration Files (if we're using
5002 * them) but need to be explicitly set if we're using hard-coded
5003 * initialization. But even in the case of using Firmware Configuration
5004 * Files, we'd like to expose the ability to change these via module
5005 * parameters so these are essentially common tweaks/settings for
5006 * Configuration Files and hard-coded initialization ...
5007 */
5008static int adap_init0_tweaks(struct adapter *adapter)
5009{
5010 /*
5011 * Fix up various Host-Dependent Parameters like Page Size, Cache
5012 * Line Size, etc. The firmware default is for a 4KB Page Size and
5013 * 64B Cache Line Size ...
5014 */
5015 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
5016
5017 /*
5018 * Process module parameters which affect early initialization.
5019 */
5020 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
5021 dev_err(&adapter->pdev->dev,
5022 "Ignoring illegal rx_dma_offset=%d, using 2\n",
5023 rx_dma_offset);
5024 rx_dma_offset = 2;
5025 }
5026 t4_set_reg_field(adapter, SGE_CONTROL,
5027 PKTSHIFT_MASK,
5028 PKTSHIFT(rx_dma_offset));
5029
5030 /*
5031 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5032 * adds the pseudo header itself.
5033 */
5034 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5035 CSUM_HAS_PSEUDO_HDR, 0);
5036
5037 return 0;
5038}
5039
5040/*
5041 * Attempt to initialize the adapter via a Firmware Configuration File.
5042 */
5043static int adap_init0_config(struct adapter *adapter, int reset)
5044{
5045 struct fw_caps_config_cmd caps_cmd;
5046 const struct firmware *cf;
5047 unsigned long mtype = 0, maddr = 0;
5048 u32 finiver, finicsum, cfcsum;
16e47624
HS
5049 int ret;
5050 int config_issued = 0;
0a57a536 5051 char *fw_config_file, fw_config_file_path[256];
16e47624 5052 char *config_name = NULL;
636f9d37
VP
5053
5054 /*
5055 * Reset device if necessary.
5056 */
5057 if (reset) {
5058 ret = t4_fw_reset(adapter, adapter->mbox,
5059 PIORSTMODE | PIORST);
5060 if (ret < 0)
5061 goto bye;
5062 }
5063
5064 /*
5065 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5066 * then use that. Otherwise, use the configuration file stored
5067 * in the adapter flash ...
5068 */
d14807dd 5069 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 5070 case CHELSIO_T4:
16e47624 5071 fw_config_file = FW4_CFNAME;
0a57a536
SR
5072 break;
5073 case CHELSIO_T5:
5074 fw_config_file = FW5_CFNAME;
5075 break;
5076 default:
5077 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5078 adapter->pdev->device);
5079 ret = -EINVAL;
5080 goto bye;
5081 }
5082
5083 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 5084 if (ret < 0) {
16e47624 5085 config_name = "On FLASH";
636f9d37
VP
5086 mtype = FW_MEMTYPE_CF_FLASH;
5087 maddr = t4_flash_cfg_addr(adapter);
5088 } else {
5089 u32 params[7], val[7];
5090
16e47624
HS
5091 sprintf(fw_config_file_path,
5092 "/lib/firmware/%s", fw_config_file);
5093 config_name = fw_config_file_path;
5094
636f9d37
VP
5095 if (cf->size >= FLASH_CFG_MAX_SIZE)
5096 ret = -ENOMEM;
5097 else {
5098 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5099 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5100 ret = t4_query_params(adapter, adapter->mbox,
5101 adapter->fn, 0, 1, params, val);
5102 if (ret == 0) {
5103 /*
fc5ab020 5104 * For t4_memory_rw() below addresses and
636f9d37
VP
5105 * sizes have to be in terms of multiples of 4
5106 * bytes. So, if the Configuration File isn't
5107 * a multiple of 4 bytes in length we'll have
5108 * to write that out separately since we can't
5109 * guarantee that the bytes following the
5110 * residual byte in the buffer returned by
5111 * request_firmware() are zeroed out ...
5112 */
5113 size_t resid = cf->size & 0x3;
5114 size_t size = cf->size & ~0x3;
5115 __be32 *data = (__be32 *)cf->data;
5116
5117 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
5118 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
5119
fc5ab020
HS
5120 spin_lock(&adapter->win0_lock);
5121 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5122 size, data, T4_MEMORY_WRITE);
636f9d37
VP
5123 if (ret == 0 && resid != 0) {
5124 union {
5125 __be32 word;
5126 char buf[4];
5127 } last;
5128 int i;
5129
5130 last.word = data[size >> 2];
5131 for (i = resid; i < 4; i++)
5132 last.buf[i] = 0;
fc5ab020
HS
5133 ret = t4_memory_rw(adapter, 0, mtype,
5134 maddr + size,
5135 4, &last.word,
5136 T4_MEMORY_WRITE);
636f9d37 5137 }
fc5ab020 5138 spin_unlock(&adapter->win0_lock);
636f9d37
VP
5139 }
5140 }
5141
5142 release_firmware(cf);
5143 if (ret)
5144 goto bye;
5145 }
5146
5147 /*
5148 * Issue a Capability Configuration command to the firmware to get it
5149 * to parse the Configuration File. We don't use t4_fw_config_file()
5150 * because we want the ability to modify various features after we've
5151 * processed the configuration file ...
5152 */
5153 memset(&caps_cmd, 0, sizeof(caps_cmd));
5154 caps_cmd.op_to_write =
5155 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5156 FW_CMD_REQUEST |
5157 FW_CMD_READ);
ce91a923 5158 caps_cmd.cfvalid_to_len16 =
636f9d37
VP
5159 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
5160 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5161 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
5162 FW_LEN16(caps_cmd));
5163 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5164 &caps_cmd);
16e47624
HS
5165
5166 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5167 * Configuration File in FLASH), our last gasp effort is to use the
5168 * Firmware Configuration File which is embedded in the firmware. A
5169 * very few early versions of the firmware didn't have one embedded
5170 * but we can ignore those.
5171 */
5172 if (ret == -ENOENT) {
5173 memset(&caps_cmd, 0, sizeof(caps_cmd));
5174 caps_cmd.op_to_write =
5175 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5176 FW_CMD_REQUEST |
5177 FW_CMD_READ);
5178 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5179 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5180 sizeof(caps_cmd), &caps_cmd);
5181 config_name = "Firmware Default";
5182 }
5183
5184 config_issued = 1;
636f9d37
VP
5185 if (ret < 0)
5186 goto bye;
5187
5188 finiver = ntohl(caps_cmd.finiver);
5189 finicsum = ntohl(caps_cmd.finicsum);
5190 cfcsum = ntohl(caps_cmd.cfcsum);
5191 if (finicsum != cfcsum)
5192 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5193 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5194 finicsum, cfcsum);
5195
636f9d37
VP
5196 /*
5197 * And now tell the firmware to use the configuration we just loaded.
5198 */
5199 caps_cmd.op_to_write =
5200 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5201 FW_CMD_REQUEST |
5202 FW_CMD_WRITE);
ce91a923 5203 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP
5204 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5205 NULL);
5206 if (ret < 0)
5207 goto bye;
5208
5209 /*
5210 * Tweak configuration based on system architecture, module
5211 * parameters, etc.
5212 */
5213 ret = adap_init0_tweaks(adapter);
5214 if (ret < 0)
5215 goto bye;
5216
5217 /*
5218 * And finally tell the firmware to initialize itself using the
5219 * parameters from the Configuration File.
5220 */
5221 ret = t4_fw_initialize(adapter, adapter->mbox);
5222 if (ret < 0)
5223 goto bye;
5224
5225 /*
5226 * Return successfully and note that we're operating with parameters
5227 * not supplied by the driver, rather than from hard-wired
5228 * initialization constants burried in the driver.
5229 */
5230 adapter->flags |= USING_SOFT_PARAMS;
5231 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS
5232 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5233 config_name, finiver, cfcsum);
636f9d37
VP
5234 return 0;
5235
5236 /*
5237 * Something bad happened. Return the error ... (If the "error"
5238 * is that there's no Configuration File on the adapter we don't
5239 * want to issue a warning since this is fairly common.)
5240 */
5241bye:
16e47624
HS
5242 if (config_issued && ret != -ENOENT)
5243 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5244 config_name, -ret);
636f9d37
VP
5245 return ret;
5246}
5247
13ee15d3
VP
5248/*
5249 * Attempt to initialize the adapter via hard-coded, driver supplied
5250 * parameters ...
5251 */
5252static int adap_init0_no_config(struct adapter *adapter, int reset)
5253{
5254 struct sge *s = &adapter->sge;
5255 struct fw_caps_config_cmd caps_cmd;
5256 u32 v;
5257 int i, ret;
5258
5259 /*
5260 * Reset device if necessary
5261 */
5262 if (reset) {
5263 ret = t4_fw_reset(adapter, adapter->mbox,
5264 PIORSTMODE | PIORST);
5265 if (ret < 0)
5266 goto bye;
5267 }
5268
5269 /*
5270 * Get device capabilities and select which we'll be using.
5271 */
5272 memset(&caps_cmd, 0, sizeof(caps_cmd));
5273 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5274 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5275 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
13ee15d3
VP
5276 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5277 &caps_cmd);
5278 if (ret < 0)
5279 goto bye;
5280
13ee15d3
VP
5281 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5282 if (!vf_acls)
5283 caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5284 else
5285 caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5286 } else if (vf_acls) {
5287 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5288 goto bye;
5289 }
5290 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5291 FW_CMD_REQUEST | FW_CMD_WRITE);
5292 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5293 NULL);
5294 if (ret < 0)
5295 goto bye;
5296
5297 /*
5298 * Tweak configuration based on system architecture, module
5299 * parameters, etc.
5300 */
5301 ret = adap_init0_tweaks(adapter);
5302 if (ret < 0)
5303 goto bye;
5304
5305 /*
5306 * Select RSS Global Mode we want to use. We use "Basic Virtual"
5307 * mode which maps each Virtual Interface to its own section of
5308 * the RSS Table and we turn on all map and hash enables ...
5309 */
5310 adapter->flags |= RSS_TNLALLLOOKUP;
5311 ret = t4_config_glbl_rss(adapter, adapter->mbox,
5312 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5313 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5314 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
5315 ((adapter->flags & RSS_TNLALLLOOKUP) ?
5316 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
5317 if (ret < 0)
5318 goto bye;
5319
5320 /*
5321 * Set up our own fundamental resource provisioning ...
5322 */
5323 ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5324 PFRES_NEQ, PFRES_NETHCTRL,
5325 PFRES_NIQFLINT, PFRES_NIQ,
5326 PFRES_TC, PFRES_NVI,
5327 FW_PFVF_CMD_CMASK_MASK,
5328 pfvfres_pmask(adapter, adapter->fn, 0),
5329 PFRES_NEXACTF,
5330 PFRES_R_CAPS, PFRES_WX_CAPS);
5331 if (ret < 0)
5332 goto bye;
5333
5334 /*
5335 * Perform low level SGE initialization. We need to do this before we
5336 * send the firmware the INITIALIZE command because that will cause
5337 * any other PF Drivers which are waiting for the Master
5338 * Initialization to proceed forward.
5339 */
5340 for (i = 0; i < SGE_NTIMERS - 1; i++)
5341 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5342 s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5343 s->counter_val[0] = 1;
5344 for (i = 1; i < SGE_NCOUNTERS; i++)
5345 s->counter_val[i] = min(intr_cnt[i - 1],
5346 THRESHOLD_0_GET(THRESHOLD_0_MASK));
5347 t4_sge_init(adapter);
5348
5349#ifdef CONFIG_PCI_IOV
5350 /*
5351 * Provision resource limits for Virtual Functions. We currently
5352 * grant them all the same static resource limits except for the Port
5353 * Access Rights Mask which we're assigning based on the PF. All of
5354 * the static provisioning stuff for both the PF and VF really needs
5355 * to be managed in a persistent manner for each device which the
5356 * firmware controls.
5357 */
5358 {
5359 int pf, vf;
5360
7d6727cf 5361 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
13ee15d3
VP
5362 if (num_vf[pf] <= 0)
5363 continue;
5364
5365 /* VF numbering starts at 1! */
5366 for (vf = 1; vf <= num_vf[pf]; vf++) {
5367 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5368 pf, vf,
5369 VFRES_NEQ, VFRES_NETHCTRL,
5370 VFRES_NIQFLINT, VFRES_NIQ,
5371 VFRES_TC, VFRES_NVI,
1f1e4958 5372 FW_PFVF_CMD_CMASK_MASK,
13ee15d3
VP
5373 pfvfres_pmask(
5374 adapter, pf, vf),
5375 VFRES_NEXACTF,
5376 VFRES_R_CAPS, VFRES_WX_CAPS);
5377 if (ret < 0)
5378 dev_warn(adapter->pdev_dev,
5379 "failed to "\
5380 "provision pf/vf=%d/%d; "
5381 "err=%d\n", pf, vf, ret);
5382 }
5383 }
5384 }
5385#endif
5386
5387 /*
5388 * Set up the default filter mode. Later we'll want to implement this
5389 * via a firmware command, etc. ... This needs to be done before the
5390 * firmare initialization command ... If the selected set of fields
5391 * isn't equal to the default value, we'll need to make sure that the
5392 * field selections will fit in the 36-bit budget.
5393 */
5394 if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
404d9e3f 5395 int j, bits = 0;
13ee15d3 5396
404d9e3f
VP
5397 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5398 switch (tp_vlan_pri_map & (1 << j)) {
13ee15d3
VP
5399 case 0:
5400 /* compressed filter field not enabled */
5401 break;
5402 case FCOE_MASK:
5403 bits += 1;
5404 break;
5405 case PORT_MASK:
5406 bits += 3;
5407 break;
5408 case VNIC_ID_MASK:
5409 bits += 17;
5410 break;
5411 case VLAN_MASK:
5412 bits += 17;
5413 break;
5414 case TOS_MASK:
5415 bits += 8;
5416 break;
5417 case PROTOCOL_MASK:
5418 bits += 8;
5419 break;
5420 case ETHERTYPE_MASK:
5421 bits += 16;
5422 break;
5423 case MACMATCH_MASK:
5424 bits += 9;
5425 break;
5426 case MPSHITTYPE_MASK:
5427 bits += 3;
5428 break;
5429 case FRAGMENTATION_MASK:
5430 bits += 1;
5431 break;
5432 }
5433
5434 if (bits > 36) {
5435 dev_err(adapter->pdev_dev,
5436 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5437 " using %#x\n", tp_vlan_pri_map, bits,
5438 TP_VLAN_PRI_MAP_DEFAULT);
5439 tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5440 }
5441 }
5442 v = tp_vlan_pri_map;
5443 t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5444 &v, 1, TP_VLAN_PRI_MAP);
5445
5446 /*
5447 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5448 * to support any of the compressed filter fields above. Newer
5449 * versions of the firmware do this automatically but it doesn't hurt
5450 * to set it here. Meanwhile, we do _not_ need to set Lookup Every
5451 * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5452 * since the firmware automatically turns this on and off when we have
5453 * a non-zero number of filters active (since it does have a
5454 * performance impact).
5455 */
5456 if (tp_vlan_pri_map)
5457 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5458 FIVETUPLELOOKUP_MASK,
5459 FIVETUPLELOOKUP_MASK);
5460
5461 /*
5462 * Tweak some settings.
5463 */
5464 t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5465 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5466 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5467 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5468
5469 /*
5470 * Get basic stuff going by issuing the Firmware Initialize command.
5471 * Note that this _must_ be after all PFVF commands ...
5472 */
5473 ret = t4_fw_initialize(adapter, adapter->mbox);
5474 if (ret < 0)
5475 goto bye;
5476
5477 /*
5478 * Return successfully!
5479 */
5480 dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5481 "driver parameters\n");
5482 return 0;
5483
5484 /*
5485 * Something bad happened. Return the error ...
5486 */
5487bye:
5488 return ret;
5489}
5490
16e47624
HS
5491static struct fw_info fw_info_array[] = {
5492 {
5493 .chip = CHELSIO_T4,
5494 .fs_name = FW4_CFNAME,
5495 .fw_mod_name = FW4_FNAME,
5496 .fw_hdr = {
5497 .chip = FW_HDR_CHIP_T4,
5498 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5499 .intfver_nic = FW_INTFVER(T4, NIC),
5500 .intfver_vnic = FW_INTFVER(T4, VNIC),
5501 .intfver_ri = FW_INTFVER(T4, RI),
5502 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5503 .intfver_fcoe = FW_INTFVER(T4, FCOE),
5504 },
5505 }, {
5506 .chip = CHELSIO_T5,
5507 .fs_name = FW5_CFNAME,
5508 .fw_mod_name = FW5_FNAME,
5509 .fw_hdr = {
5510 .chip = FW_HDR_CHIP_T5,
5511 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5512 .intfver_nic = FW_INTFVER(T5, NIC),
5513 .intfver_vnic = FW_INTFVER(T5, VNIC),
5514 .intfver_ri = FW_INTFVER(T5, RI),
5515 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5516 .intfver_fcoe = FW_INTFVER(T5, FCOE),
5517 },
5518 }
5519};
5520
5521static struct fw_info *find_fw_info(int chip)
5522{
5523 int i;
5524
5525 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5526 if (fw_info_array[i].chip == chip)
5527 return &fw_info_array[i];
5528 }
5529 return NULL;
5530}
5531
b8ff05a9
DM
5532/*
5533 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5534 */
5535static int adap_init0(struct adapter *adap)
5536{
5537 int ret;
5538 u32 v, port_vec;
5539 enum dev_state state;
5540 u32 params[7], val[7];
9a4da2cd 5541 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 5542 int reset = 1;
b8ff05a9 5543
636f9d37
VP
5544 /*
5545 * Contact FW, advertising Master capability (and potentially forcing
5546 * ourselves as the Master PF if our module parameter force_init is
5547 * set).
5548 */
5549 ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5550 force_init ? MASTER_MUST : MASTER_MAY,
5551 &state);
b8ff05a9
DM
5552 if (ret < 0) {
5553 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5554 ret);
5555 return ret;
5556 }
636f9d37
VP
5557 if (ret == adap->mbox)
5558 adap->flags |= MASTER_PF;
5559 if (force_init && state == DEV_STATE_INIT)
5560 state = DEV_STATE_UNINIT;
b8ff05a9 5561
636f9d37
VP
5562 /*
5563 * If we're the Master PF Driver and the device is uninitialized,
5564 * then let's consider upgrading the firmware ... (We always want
5565 * to check the firmware version number in order to A. get it for
5566 * later reporting and B. to warn if the currently loaded firmware
5567 * is excessively mismatched relative to the driver.)
5568 */
16e47624
HS
5569 t4_get_fw_version(adap, &adap->params.fw_vers);
5570 t4_get_tp_version(adap, &adap->params.tp_vers);
636f9d37 5571 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS
5572 struct fw_info *fw_info;
5573 struct fw_hdr *card_fw;
5574 const struct firmware *fw;
5575 const u8 *fw_data = NULL;
5576 unsigned int fw_size = 0;
5577
5578 /* This is the firmware whose headers the driver was compiled
5579 * against
5580 */
5581 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5582 if (fw_info == NULL) {
5583 dev_err(adap->pdev_dev,
5584 "unable to get firmware info for chip %d.\n",
5585 CHELSIO_CHIP_VERSION(adap->params.chip));
5586 return -EINVAL;
636f9d37 5587 }
16e47624
HS
5588
5589 /* allocate memory to read the header of the firmware on the
5590 * card
5591 */
5592 card_fw = t4_alloc_mem(sizeof(*card_fw));
5593
5594 /* Get FW from from /lib/firmware/ */
5595 ret = request_firmware(&fw, fw_info->fw_mod_name,
5596 adap->pdev_dev);
5597 if (ret < 0) {
5598 dev_err(adap->pdev_dev,
5599 "unable to load firmware image %s, error %d\n",
5600 fw_info->fw_mod_name, ret);
5601 } else {
5602 fw_data = fw->data;
5603 fw_size = fw->size;
5604 }
5605
5606 /* upgrade FW logic */
5607 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5608 state, &reset);
5609
5610 /* Cleaning up */
5611 if (fw != NULL)
5612 release_firmware(fw);
5613 t4_free_mem(card_fw);
5614
636f9d37 5615 if (ret < 0)
16e47624 5616 goto bye;
636f9d37 5617 }
b8ff05a9 5618
636f9d37
VP
5619 /*
5620 * Grab VPD parameters. This should be done after we establish a
5621 * connection to the firmware since some of the VPD parameters
5622 * (notably the Core Clock frequency) are retrieved via requests to
5623 * the firmware. On the other hand, we need these fairly early on
5624 * so we do this right after getting ahold of the firmware.
5625 */
5626 ret = get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM
5627 if (ret < 0)
5628 goto bye;
a0881cab 5629
636f9d37 5630 /*
13ee15d3
VP
5631 * Find out what ports are available to us. Note that we need to do
5632 * this before calling adap_init0_no_config() since it needs nports
5633 * and portvec ...
636f9d37
VP
5634 */
5635 v =
5636 FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5637 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
5638 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
a0881cab
DM
5639 if (ret < 0)
5640 goto bye;
5641
636f9d37
VP
5642 adap->params.nports = hweight32(port_vec);
5643 adap->params.portvec = port_vec;
5644
5645 /*
5646 * If the firmware is initialized already (and we're not forcing a
5647 * master initialization), note that we're living with existing
5648 * adapter parameters. Otherwise, it's time to try initializing the
5649 * adapter ...
5650 */
5651 if (state == DEV_STATE_INIT) {
5652 dev_info(adap->pdev_dev, "Coming up as %s: "\
5653 "Adapter already initialized\n",
5654 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5655 adap->flags |= USING_SOFT_PARAMS;
5656 } else {
5657 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5658 "Initializing adapter\n");
636f9d37
VP
5659
5660 /*
5661 * If the firmware doesn't support Configuration
5662 * Files warn user and exit,
5663 */
5664 if (ret < 0)
13ee15d3 5665 dev_warn(adap->pdev_dev, "Firmware doesn't support "
636f9d37 5666 "configuration file.\n");
13ee15d3
VP
5667 if (force_old_init)
5668 ret = adap_init0_no_config(adap, reset);
636f9d37
VP
5669 else {
5670 /*
13ee15d3
VP
5671 * Find out whether we're dealing with a version of
5672 * the firmware which has configuration file support.
636f9d37 5673 */
13ee15d3
VP
5674 params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5675 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5676 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5677 params, val);
636f9d37 5678
13ee15d3
VP
5679 /*
5680 * If the firmware doesn't support Configuration
5681 * Files, use the old Driver-based, hard-wired
5682 * initialization. Otherwise, try using the
5683 * Configuration File support and fall back to the
5684 * Driver-based initialization if there's no
5685 * Configuration File found.
5686 */
5687 if (ret < 0)
5688 ret = adap_init0_no_config(adap, reset);
5689 else {
5690 /*
5691 * The firmware provides us with a memory
5692 * buffer where we can load a Configuration
5693 * File from the host if we want to override
5694 * the Configuration File in flash.
5695 */
5696
5697 ret = adap_init0_config(adap, reset);
5698 if (ret == -ENOENT) {
5699 dev_info(adap->pdev_dev,
5700 "No Configuration File present "
16e47624 5701 "on adapter. Using hard-wired "
13ee15d3
VP
5702 "configuration parameters.\n");
5703 ret = adap_init0_no_config(adap, reset);
5704 }
636f9d37
VP
5705 }
5706 }
5707 if (ret < 0) {
5708 dev_err(adap->pdev_dev,
5709 "could not initialize adapter, error %d\n",
5710 -ret);
5711 goto bye;
5712 }
5713 }
5714
5715 /*
5716 * If we're living with non-hard-coded parameters (either from a
5717 * Firmware Configuration File or values programmed by a different PF
5718 * Driver), give the SGE code a chance to pull in anything that it
5719 * needs ... Note that this must be called after we retrieve our VPD
5720 * parameters in order to know how to convert core ticks to seconds.
5721 */
5722 if (adap->flags & USING_SOFT_PARAMS) {
5723 ret = t4_sge_init(adap);
5724 if (ret < 0)
5725 goto bye;
5726 }
5727
9a4da2cd
VP
5728 if (is_bypass_device(adap->pdev->device))
5729 adap->params.bypass = 1;
5730
636f9d37
VP
5731 /*
5732 * Grab some of our basic fundamental operating parameters.
5733 */
5734#define FW_PARAM_DEV(param) \
5735 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5736 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5737
b8ff05a9 5738#define FW_PARAM_PFVF(param) \
636f9d37
VP
5739 FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5740 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
5741 FW_PARAMS_PARAM_Y(0) | \
5742 FW_PARAMS_PARAM_Z(0)
b8ff05a9 5743
636f9d37 5744 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM
5745 params[1] = FW_PARAM_PFVF(L2T_START);
5746 params[2] = FW_PARAM_PFVF(L2T_END);
5747 params[3] = FW_PARAM_PFVF(FILTER_START);
5748 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 5749 params[5] = FW_PARAM_PFVF(IQFLINT_START);
636f9d37 5750 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
b8ff05a9
DM
5751 if (ret < 0)
5752 goto bye;
636f9d37
VP
5753 adap->sge.egr_start = val[0];
5754 adap->l2t_start = val[1];
5755 adap->l2t_end = val[2];
b8ff05a9
DM
5756 adap->tids.ftid_base = val[3];
5757 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 5758 adap->sge.ingr_start = val[5];
b8ff05a9 5759
636f9d37
VP
5760 /* query params related to active filter region */
5761 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5762 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5763 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5764 /* If Active filter size is set we enable establishing
5765 * offload connection through firmware work request
5766 */
5767 if ((val[0] != val[1]) && (ret >= 0)) {
5768 adap->flags |= FW_OFLD_CONN;
5769 adap->tids.aftid_base = val[0];
5770 adap->tids.aftid_end = val[1];
5771 }
5772
b407a4a9
VP
5773 /* If we're running on newer firmware, let it know that we're
5774 * prepared to deal with encapsulated CPL messages. Older
5775 * firmware won't understand this and we'll just get
5776 * unencapsulated messages ...
5777 */
5778 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5779 val[0] = 1;
5780 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5781
1ac0f095
KS
5782 /*
5783 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5784 * capability. Earlier versions of the firmware didn't have the
5785 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5786 * permission to use ULPTX MEMWRITE DSGL.
5787 */
5788 if (is_t4(adap->params.chip)) {
5789 adap->params.ulptx_memwrite_dsgl = false;
5790 } else {
5791 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5792 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5793 1, params, val);
5794 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5795 }
5796
636f9d37
VP
5797 /*
5798 * Get device capabilities so we can determine what resources we need
5799 * to manage.
5800 */
5801 memset(&caps_cmd, 0, sizeof(caps_cmd));
9a4da2cd 5802 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
13ee15d3 5803 FW_CMD_REQUEST | FW_CMD_READ);
ce91a923 5804 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP
5805 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5806 &caps_cmd);
5807 if (ret < 0)
5808 goto bye;
5809
13ee15d3 5810 if (caps_cmd.ofldcaps) {
b8ff05a9
DM
5811 /* query offload-related parameters */
5812 params[0] = FW_PARAM_DEV(NTID);
5813 params[1] = FW_PARAM_PFVF(SERVER_START);
5814 params[2] = FW_PARAM_PFVF(SERVER_END);
5815 params[3] = FW_PARAM_PFVF(TDDP_START);
5816 params[4] = FW_PARAM_PFVF(TDDP_END);
5817 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
636f9d37
VP
5818 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5819 params, val);
b8ff05a9
DM
5820 if (ret < 0)
5821 goto bye;
5822 adap->tids.ntids = val[0];
5823 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5824 adap->tids.stid_base = val[1];
5825 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37
VP
5826 /*
5827 * Setup server filter region. Divide the availble filter
5828 * region into two parts. Regular filters get 1/3rd and server
5829 * filters get 2/3rd part. This is only enabled if workarond
5830 * path is enabled.
5831 * 1. For regular filters.
5832 * 2. Server filter: This are special filters which are used
5833 * to redirect SYN packets to offload queue.
5834 */
5835 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5836 adap->tids.sftid_base = adap->tids.ftid_base +
5837 DIV_ROUND_UP(adap->tids.nftids, 3);
5838 adap->tids.nsftids = adap->tids.nftids -
5839 DIV_ROUND_UP(adap->tids.nftids, 3);
5840 adap->tids.nftids = adap->tids.sftid_base -
5841 adap->tids.ftid_base;
5842 }
b8ff05a9
DM
5843 adap->vres.ddp.start = val[3];
5844 adap->vres.ddp.size = val[4] - val[3] + 1;
5845 adap->params.ofldq_wr_cred = val[5];
636f9d37 5846
b8ff05a9
DM
5847 adap->params.offload = 1;
5848 }
636f9d37 5849 if (caps_cmd.rdmacaps) {
b8ff05a9
DM
5850 params[0] = FW_PARAM_PFVF(STAG_START);
5851 params[1] = FW_PARAM_PFVF(STAG_END);
5852 params[2] = FW_PARAM_PFVF(RQ_START);
5853 params[3] = FW_PARAM_PFVF(RQ_END);
5854 params[4] = FW_PARAM_PFVF(PBL_START);
5855 params[5] = FW_PARAM_PFVF(PBL_END);
636f9d37
VP
5856 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5857 params, val);
b8ff05a9
DM
5858 if (ret < 0)
5859 goto bye;
5860 adap->vres.stag.start = val[0];
5861 adap->vres.stag.size = val[1] - val[0] + 1;
5862 adap->vres.rq.start = val[2];
5863 adap->vres.rq.size = val[3] - val[2] + 1;
5864 adap->vres.pbl.start = val[4];
5865 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab
DM
5866
5867 params[0] = FW_PARAM_PFVF(SQRQ_START);
5868 params[1] = FW_PARAM_PFVF(SQRQ_END);
5869 params[2] = FW_PARAM_PFVF(CQ_START);
5870 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM
5871 params[4] = FW_PARAM_PFVF(OCQ_START);
5872 params[5] = FW_PARAM_PFVF(OCQ_END);
636f9d37 5873 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
a0881cab
DM
5874 if (ret < 0)
5875 goto bye;
5876 adap->vres.qp.start = val[0];
5877 adap->vres.qp.size = val[1] - val[0] + 1;
5878 adap->vres.cq.start = val[2];
5879 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM
5880 adap->vres.ocq.start = val[4];
5881 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS
5882
5883 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5884 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5885 ret = t4_query_params(adap, 0, 0, 0, 2, params, val);
5886 if (ret < 0) {
5887 adap->params.max_ordird_qp = 8;
5888 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5889 ret = 0;
5890 } else {
5891 adap->params.max_ordird_qp = val[0];
5892 adap->params.max_ird_adapter = val[1];
5893 }
5894 dev_info(adap->pdev_dev,
5895 "max_ordird_qp %d max_ird_adapter %d\n",
5896 adap->params.max_ordird_qp,
5897 adap->params.max_ird_adapter);
b8ff05a9 5898 }
636f9d37 5899 if (caps_cmd.iscsicaps) {
b8ff05a9
DM
5900 params[0] = FW_PARAM_PFVF(ISCSI_START);
5901 params[1] = FW_PARAM_PFVF(ISCSI_END);
636f9d37
VP
5902 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5903 params, val);
b8ff05a9
DM
5904 if (ret < 0)
5905 goto bye;
5906 adap->vres.iscsi.start = val[0];
5907 adap->vres.iscsi.size = val[1] - val[0] + 1;
5908 }
5909#undef FW_PARAM_PFVF
5910#undef FW_PARAM_DEV
5911
92e7ae71
HS
5912 /* The MTU/MSS Table is initialized by now, so load their values. If
5913 * we're initializing the adapter, then we'll make any modifications
5914 * we want to the MTU/MSS Table and also initialize the congestion
5915 * parameters.
636f9d37 5916 */
b8ff05a9 5917 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS
5918 if (state != DEV_STATE_INIT) {
5919 int i;
5920
5921 /* The default MTU Table contains values 1492 and 1500.
5922 * However, for TCP, it's better to have two values which are
5923 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5924 * This allows us to have a TCP Data Payload which is a
5925 * multiple of 8 regardless of what combination of TCP Options
5926 * are in use (always a multiple of 4 bytes) which is
5927 * important for performance reasons. For instance, if no
5928 * options are in use, then we have a 20-byte IP header and a
5929 * 20-byte TCP header. In this case, a 1500-byte MSS would
5930 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5931 * which is not a multiple of 8. So using an MSS of 1488 in
5932 * this case results in a TCP Data Payload of 1448 bytes which
5933 * is a multiple of 8. On the other hand, if 12-byte TCP Time
5934 * Stamps have been negotiated, then an MTU of 1500 bytes
5935 * results in a TCP Data Payload of 1448 bytes which, as
5936 * above, is a multiple of 8 bytes ...
5937 */
5938 for (i = 0; i < NMTUS; i++)
5939 if (adap->params.mtus[i] == 1492) {
5940 adap->params.mtus[i] = 1488;
5941 break;
5942 }
7ee9ff94 5943
92e7ae71
HS
5944 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5945 adap->params.b_wnd);
5946 }
dcf7b6f5 5947 t4_init_tp_params(adap);
636f9d37 5948 adap->flags |= FW_OK;
b8ff05a9
DM
5949 return 0;
5950
5951 /*
636f9d37
VP
5952 * Something bad happened. If a command timed out or failed with EIO
5953 * FW does not operate within its spec or something catastrophic
5954 * happened to HW/FW, stop issuing commands.
b8ff05a9 5955 */
636f9d37
VP
5956bye:
5957 if (ret != -ETIMEDOUT && ret != -EIO)
5958 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM
5959 return ret;
5960}
5961
204dc3c0
DM
5962/* EEH callbacks */
5963
5964static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5965 pci_channel_state_t state)
5966{
5967 int i;
5968 struct adapter *adap = pci_get_drvdata(pdev);
5969
5970 if (!adap)
5971 goto out;
5972
5973 rtnl_lock();
5974 adap->flags &= ~FW_OK;
5975 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 5976 spin_lock(&adap->stats_lock);
204dc3c0
DM
5977 for_each_port(adap, i) {
5978 struct net_device *dev = adap->port[i];
5979
5980 netif_device_detach(dev);
5981 netif_carrier_off(dev);
5982 }
9fe6cb58 5983 spin_unlock(&adap->stats_lock);
204dc3c0
DM
5984 if (adap->flags & FULL_INIT_DONE)
5985 cxgb_down(adap);
5986 rtnl_unlock();
144be3d9
GS
5987 if ((adap->flags & DEV_ENABLED)) {
5988 pci_disable_device(pdev);
5989 adap->flags &= ~DEV_ENABLED;
5990 }
204dc3c0
DM
5991out: return state == pci_channel_io_perm_failure ?
5992 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5993}
5994
5995static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5996{
5997 int i, ret;
5998 struct fw_caps_config_cmd c;
5999 struct adapter *adap = pci_get_drvdata(pdev);
6000
6001 if (!adap) {
6002 pci_restore_state(pdev);
6003 pci_save_state(pdev);
6004 return PCI_ERS_RESULT_RECOVERED;
6005 }
6006
144be3d9
GS
6007 if (!(adap->flags & DEV_ENABLED)) {
6008 if (pci_enable_device(pdev)) {
6009 dev_err(&pdev->dev, "Cannot reenable PCI "
6010 "device after reset\n");
6011 return PCI_ERS_RESULT_DISCONNECT;
6012 }
6013 adap->flags |= DEV_ENABLED;
204dc3c0
DM
6014 }
6015
6016 pci_set_master(pdev);
6017 pci_restore_state(pdev);
6018 pci_save_state(pdev);
6019 pci_cleanup_aer_uncorrect_error_status(pdev);
6020
6021 if (t4_wait_dev_ready(adap) < 0)
6022 return PCI_ERS_RESULT_DISCONNECT;
777c2300 6023 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
204dc3c0
DM
6024 return PCI_ERS_RESULT_DISCONNECT;
6025 adap->flags |= FW_OK;
6026 if (adap_init1(adap, &c))
6027 return PCI_ERS_RESULT_DISCONNECT;
6028
6029 for_each_port(adap, i) {
6030 struct port_info *p = adap2pinfo(adap, i);
6031
060e0c75
DM
6032 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
6033 NULL, NULL);
204dc3c0
DM
6034 if (ret < 0)
6035 return PCI_ERS_RESULT_DISCONNECT;
6036 p->viid = ret;
6037 p->xact_addr_filt = -1;
6038 }
6039
6040 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6041 adap->params.b_wnd);
1ae970e0 6042 setup_memwin(adap);
204dc3c0
DM
6043 if (cxgb_up(adap))
6044 return PCI_ERS_RESULT_DISCONNECT;
6045 return PCI_ERS_RESULT_RECOVERED;
6046}
6047
6048static void eeh_resume(struct pci_dev *pdev)
6049{
6050 int i;
6051 struct adapter *adap = pci_get_drvdata(pdev);
6052
6053 if (!adap)
6054 return;
6055
6056 rtnl_lock();
6057 for_each_port(adap, i) {
6058 struct net_device *dev = adap->port[i];
6059
6060 if (netif_running(dev)) {
6061 link_start(dev);
6062 cxgb_set_rxmode(dev);
6063 }
6064 netif_device_attach(dev);
6065 }
6066 rtnl_unlock();
6067}
6068
3646f0e5 6069static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM
6070 .error_detected = eeh_err_detected,
6071 .slot_reset = eeh_slot_reset,
6072 .resume = eeh_resume,
6073};
6074
57d8b764 6075static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 6076{
57d8b764
KS
6077 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6078 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
b8ff05a9
DM
6079}
6080
c887ad0e
HS
6081static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6082 unsigned int us, unsigned int cnt,
b8ff05a9
DM
6083 unsigned int size, unsigned int iqe_size)
6084{
c887ad0e
HS
6085 q->adap = adap;
6086 set_rspq_intr_params(q, us, cnt);
b8ff05a9
DM
6087 q->iqe_len = iqe_size;
6088 q->size = size;
6089}
6090
6091/*
6092 * Perform default configuration of DMA queues depending on the number and type
6093 * of ports we found and the number of available CPUs. Most settings can be
6094 * modified by the admin prior to actual use.
6095 */
91744948 6096static void cfg_queues(struct adapter *adap)
b8ff05a9
DM
6097{
6098 struct sge *s = &adap->sge;
688848b1
AB
6099 int i, n10g = 0, qidx = 0;
6100#ifndef CONFIG_CHELSIO_T4_DCB
6101 int q10g = 0;
6102#endif
cf38be6d 6103 int ciq_size;
b8ff05a9
DM
6104
6105 for_each_port(adap, i)
57d8b764 6106 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB
6107#ifdef CONFIG_CHELSIO_T4_DCB
6108 /* For Data Center Bridging support we need to be able to support up
6109 * to 8 Traffic Priorities; each of which will be assigned to its
6110 * own TX Queue in order to prevent Head-Of-Line Blocking.
6111 */
6112 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6113 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6114 MAX_ETH_QSETS, adap->params.nports * 8);
6115 BUG_ON(1);
6116 }
b8ff05a9 6117
688848b1
AB
6118 for_each_port(adap, i) {
6119 struct port_info *pi = adap2pinfo(adap, i);
6120
6121 pi->first_qset = qidx;
6122 pi->nqsets = 8;
6123 qidx += pi->nqsets;
6124 }
6125#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM
6126 /*
6127 * We default to 1 queue per non-10G port and up to # of cores queues
6128 * per 10G port.
6129 */
6130 if (n10g)
6131 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM
6132 if (q10g > netif_get_num_default_rss_queues())
6133 q10g = netif_get_num_default_rss_queues();
b8ff05a9
DM
6134
6135 for_each_port(adap, i) {
6136 struct port_info *pi = adap2pinfo(adap, i);
6137
6138 pi->first_qset = qidx;
57d8b764 6139 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM
6140 qidx += pi->nqsets;
6141 }
688848b1 6142#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM
6143
6144 s->ethqsets = qidx;
6145 s->max_ethqsets = qidx; /* MSI-X may lower it later */
6146
6147 if (is_offload(adap)) {
6148 /*
6149 * For offload we use 1 queue/channel if all ports are up to 1G,
6150 * otherwise we divide all available queues amongst the channels
6151 * capped by the number of available cores.
6152 */
6153 if (n10g) {
6154 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6155 num_online_cpus());
6156 s->ofldqsets = roundup(i, adap->params.nports);
6157 } else
6158 s->ofldqsets = adap->params.nports;
6159 /* For RDMA one Rx queue per channel suffices */
6160 s->rdmaqs = adap->params.nports;
cf38be6d 6161 s->rdmaciqs = adap->params.nports;
b8ff05a9
DM
6162 }
6163
6164 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6165 struct sge_eth_rxq *r = &s->ethrxq[i];
6166
c887ad0e 6167 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM
6168 r->fl.size = 72;
6169 }
6170
6171 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6172 s->ethtxq[i].q.size = 1024;
6173
6174 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6175 s->ctrlq[i].q.size = 512;
6176
6177 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6178 s->ofldtxq[i].q.size = 1024;
6179
6180 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6181 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6182
c887ad0e 6183 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
b8ff05a9
DM
6184 r->rspq.uld = CXGB4_ULD_ISCSI;
6185 r->fl.size = 72;
6186 }
6187
6188 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6189 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6190
c887ad0e 6191 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
b8ff05a9
DM
6192 r->rspq.uld = CXGB4_ULD_RDMA;
6193 r->fl.size = 72;
6194 }
6195
cf38be6d
HS
6196 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6197 if (ciq_size > SGE_MAX_IQ_SIZE) {
6198 CH_WARN(adap, "CIQ size too small for available IQs\n");
6199 ciq_size = SGE_MAX_IQ_SIZE;
6200 }
6201
6202 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6203 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6204
c887ad0e 6205 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
cf38be6d
HS
6206 r->rspq.uld = CXGB4_ULD_RDMA;
6207 }
6208
c887ad0e
HS
6209 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6210 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
b8ff05a9
DM
6211}
6212
6213/*
6214 * Reduce the number of Ethernet queues across all ports to at most n.
6215 * n provides at least one queue per port.
6216 */
91744948 6217static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM
6218{
6219 int i;
6220 struct port_info *pi;
6221
6222 while (n < adap->sge.ethqsets)
6223 for_each_port(adap, i) {
6224 pi = adap2pinfo(adap, i);
6225 if (pi->nqsets > 1) {
6226 pi->nqsets--;
6227 adap->sge.ethqsets--;
6228 if (adap->sge.ethqsets <= n)
6229 break;
6230 }
6231 }
6232
6233 n = 0;
6234 for_each_port(adap, i) {
6235 pi = adap2pinfo(adap, i);
6236 pi->first_qset = n;
6237 n += pi->nqsets;
6238 }
6239}
6240
6241/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6242#define EXTRA_VECS 2
6243
91744948 6244static int enable_msix(struct adapter *adap)
b8ff05a9
DM
6245{
6246 int ofld_need = 0;
c32ad224 6247 int i, want, need;
b8ff05a9
DM
6248 struct sge *s = &adap->sge;
6249 unsigned int nchan = adap->params.nports;
6250 struct msix_entry entries[MAX_INGQ + 1];
6251
6252 for (i = 0; i < ARRAY_SIZE(entries); ++i)
6253 entries[i].entry = i;
6254
6255 want = s->max_ethqsets + EXTRA_VECS;
6256 if (is_offload(adap)) {
cf38be6d 6257 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
b8ff05a9 6258 /* need nchan for each possible ULD */
cf38be6d 6259 ofld_need = 3 * nchan;
b8ff05a9 6260 }
688848b1
AB
6261#ifdef CONFIG_CHELSIO_T4_DCB
6262 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6263 * each port.
6264 */
6265 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6266#else
b8ff05a9 6267 need = adap->params.nports + EXTRA_VECS + ofld_need;
688848b1 6268#endif
c32ad224
AG
6269 want = pci_enable_msix_range(adap->pdev, entries, need, want);
6270 if (want < 0)
6271 return want;
b8ff05a9 6272
c32ad224
AG
6273 /*
6274 * Distribute available vectors to the various queue groups.
6275 * Every group gets its minimum requirement and NIC gets top
6276 * priority for leftovers.
6277 */
6278 i = want - EXTRA_VECS - ofld_need;
6279 if (i < s->max_ethqsets) {
6280 s->max_ethqsets = i;
6281 if (i < s->ethqsets)
6282 reduce_ethqs(adap, i);
6283 }
6284 if (is_offload(adap)) {
6285 i = want - EXTRA_VECS - s->max_ethqsets;
6286 i -= ofld_need - nchan;
6287 s->ofldqsets = (i / nchan) * nchan; /* round down */
6288 }
6289 for (i = 0; i < want; ++i)
6290 adap->msix_info[i].vec = entries[i].vector;
6291
6292 return 0;
b8ff05a9
DM
6293}
6294
6295#undef EXTRA_VECS
6296
91744948 6297static int init_rss(struct adapter *adap)
671b0060
DM
6298{
6299 unsigned int i, j;
6300
6301 for_each_port(adap, i) {
6302 struct port_info *pi = adap2pinfo(adap, i);
6303
6304 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6305 if (!pi->rss)
6306 return -ENOMEM;
6307 for (j = 0; j < pi->rss_size; j++)
278bc429 6308 pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
671b0060
DM
6309 }
6310 return 0;
6311}
6312
91744948 6313static void print_port_info(const struct net_device *dev)
b8ff05a9 6314{
b8ff05a9 6315 char buf[80];
118969ed 6316 char *bufp = buf;
f1a051b9 6317 const char *spd = "";
118969ed
DM
6318 const struct port_info *pi = netdev_priv(dev);
6319 const struct adapter *adap = pi->adapter;
f1a051b9
DM
6320
6321 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6322 spd = " 2.5 GT/s";
6323 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6324 spd = " 5 GT/s";
d2e752db
RD
6325 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6326 spd = " 8 GT/s";
b8ff05a9 6327
118969ed
DM
6328 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6329 bufp += sprintf(bufp, "100/");
6330 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6331 bufp += sprintf(bufp, "1000/");
6332 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6333 bufp += sprintf(bufp, "10G/");
72aca4bf
KS
6334 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6335 bufp += sprintf(bufp, "40G/");
118969ed
DM
6336 if (bufp != buf)
6337 --bufp;
72aca4bf 6338 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed
DM
6339
6340 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
0a57a536 6341 adap->params.vpd.id,
d14807dd 6342 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
118969ed
DM
6343 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6344 (adap->flags & USING_MSIX) ? " MSI-X" :
6345 (adap->flags & USING_MSI) ? " MSI" : "");
a94cd705
KS
6346 netdev_info(dev, "S/N: %s, P/N: %s\n",
6347 adap->params.vpd.sn, adap->params.vpd.pn);
b8ff05a9
DM
6348}
6349
91744948 6350static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
ef306b50 6351{
e5c8ae5f 6352 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
ef306b50
DM
6353}
6354
06546391
DM
6355/*
6356 * Free the following resources:
6357 * - memory used for tables
6358 * - MSI/MSI-X
6359 * - net devices
6360 * - resources FW is holding for us
6361 */
6362static void free_some_resources(struct adapter *adapter)
6363{
6364 unsigned int i;
6365
6366 t4_free_mem(adapter->l2t);
6367 t4_free_mem(adapter->tids.tid_tab);
6368 disable_msi(adapter);
6369
6370 for_each_port(adapter, i)
671b0060
DM
6371 if (adapter->port[i]) {
6372 kfree(adap2pinfo(adapter, i)->rss);
06546391 6373 free_netdev(adapter->port[i]);
671b0060 6374 }
06546391 6375 if (adapter->flags & FW_OK)
060e0c75 6376 t4_fw_bye(adapter, adapter->fn);
06546391
DM
6377}
6378
2ed28baa 6379#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 6380#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 6381 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 6382#define SEGMENT_SIZE 128
b8ff05a9 6383
1dd06ae8 6384static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 6385{
22adfe0a 6386 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 6387 struct port_info *pi;
c8f44aff 6388 bool highdma = false;
b8ff05a9
DM
6389 struct adapter *adapter = NULL;
6390
6391 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6392
6393 err = pci_request_regions(pdev, KBUILD_MODNAME);
6394 if (err) {
6395 /* Just info, some other driver may have claimed the device. */
6396 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6397 return err;
6398 }
6399
b8ff05a9
DM
6400 err = pci_enable_device(pdev);
6401 if (err) {
6402 dev_err(&pdev->dev, "cannot enable PCI device\n");
6403 goto out_release_regions;
6404 }
6405
6406 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 6407 highdma = true;
b8ff05a9
DM
6408 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6409 if (err) {
6410 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6411 "coherent allocations\n");
6412 goto out_disable_device;
6413 }
6414 } else {
6415 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6416 if (err) {
6417 dev_err(&pdev->dev, "no usable DMA configuration\n");
6418 goto out_disable_device;
6419 }
6420 }
6421
6422 pci_enable_pcie_error_reporting(pdev);
ef306b50 6423 enable_pcie_relaxed_ordering(pdev);
b8ff05a9
DM
6424 pci_set_master(pdev);
6425 pci_save_state(pdev);
6426
6427 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6428 if (!adapter) {
6429 err = -ENOMEM;
6430 goto out_disable_device;
6431 }
6432
144be3d9
GS
6433 /* PCI device has been enabled */
6434 adapter->flags |= DEV_ENABLED;
6435
b8ff05a9
DM
6436 adapter->regs = pci_ioremap_bar(pdev, 0);
6437 if (!adapter->regs) {
6438 dev_err(&pdev->dev, "cannot map device registers\n");
6439 err = -ENOMEM;
6440 goto out_free_adapter;
6441 }
6442
35b1de55
HS
6443 /* We control everything through one PF */
6444 func = SOURCEPF_GET(readl(adapter->regs + PL_WHOAMI));
6445 if ((pdev->device == 0xa000 && func != 0) ||
6446 func != ent->driver_data) {
6447 pci_save_state(pdev); /* to restore SR-IOV later */
6448 err = 0;
6449 goto out_unmap_bar0;
6450 }
6451
b8ff05a9
DM
6452 adapter->pdev = pdev;
6453 adapter->pdev_dev = &pdev->dev;
3069ee9b 6454 adapter->mbox = func;
060e0c75 6455 adapter->fn = func;
b8ff05a9
DM
6456 adapter->msg_enable = dflt_msg_enable;
6457 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6458
6459 spin_lock_init(&adapter->stats_lock);
6460 spin_lock_init(&adapter->tid_release_lock);
6461
6462 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP
6463 INIT_WORK(&adapter->db_full_task, process_db_full);
6464 INIT_WORK(&adapter->db_drop_task, process_db_drop);
b8ff05a9
DM
6465
6466 err = t4_prep_adapter(adapter);
6467 if (err)
22adfe0a
SR
6468 goto out_unmap_bar0;
6469
d14807dd 6470 if (!is_t4(adapter->params.chip)) {
22adfe0a
SR
6471 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6472 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6473 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6474 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6475
6476 /* Each segment size is 128B. Write coalescing is enabled only
6477 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6478 * queue is less no of segments that can be accommodated in
6479 * a page size.
6480 */
6481 if (qpp > num_seg) {
6482 dev_err(&pdev->dev,
6483 "Incorrect number of egress queues per page\n");
6484 err = -EINVAL;
6485 goto out_unmap_bar0;
6486 }
6487 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6488 pci_resource_len(pdev, 2));
6489 if (!adapter->bar2) {
6490 dev_err(&pdev->dev, "cannot map device bar2 region\n");
6491 err = -ENOMEM;
6492 goto out_unmap_bar0;
6493 }
6494 }
6495
636f9d37 6496 setup_memwin(adapter);
b8ff05a9 6497 err = adap_init0(adapter);
636f9d37 6498 setup_memwin_rdma(adapter);
b8ff05a9
DM
6499 if (err)
6500 goto out_unmap_bar;
6501
6502 for_each_port(adapter, i) {
6503 struct net_device *netdev;
6504
6505 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6506 MAX_ETH_QSETS);
6507 if (!netdev) {
6508 err = -ENOMEM;
6509 goto out_free_dev;
6510 }
6511
6512 SET_NETDEV_DEV(netdev, &pdev->dev);
6513
6514 adapter->port[i] = netdev;
6515 pi = netdev_priv(netdev);
6516 pi->adapter = adapter;
6517 pi->xact_addr_filt = -1;
b8ff05a9 6518 pi->port_id = i;
b8ff05a9
DM
6519 netdev->irq = pdev->irq;
6520
2ed28baa
MM
6521 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6522 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6523 NETIF_F_RXCSUM | NETIF_F_RXHASH |
f646968f 6524 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c8f44aff
MM
6525 if (highdma)
6526 netdev->hw_features |= NETIF_F_HIGHDMA;
6527 netdev->features |= netdev->hw_features;
b8ff05a9
DM
6528 netdev->vlan_features = netdev->features & VLAN_FEAT;
6529
01789349
JP
6530 netdev->priv_flags |= IFF_UNICAST_FLT;
6531
b8ff05a9 6532 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB
6533#ifdef CONFIG_CHELSIO_T4_DCB
6534 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6535 cxgb4_dcb_state_init(netdev);
6536#endif
7ad24ea4 6537 netdev->ethtool_ops = &cxgb_ethtool_ops;
b8ff05a9
DM
6538 }
6539
6540 pci_set_drvdata(pdev, adapter);
6541
6542 if (adapter->flags & FW_OK) {
060e0c75 6543 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM
6544 if (err)
6545 goto out_free_dev;
6546 }
6547
6548 /*
6549 * Configure queues and allocate tables now, they can be needed as
6550 * soon as the first register_netdev completes.
6551 */
6552 cfg_queues(adapter);
6553
6554 adapter->l2t = t4_init_l2t();
6555 if (!adapter->l2t) {
6556 /* We tolerate a lack of L2T, giving up some functionality */
6557 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6558 adapter->params.offload = 0;
6559 }
6560
6561 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6562 dev_warn(&pdev->dev, "could not allocate TID table, "
6563 "continuing\n");
6564 adapter->params.offload = 0;
6565 }
6566
f7cabcdd
DM
6567 /* See what interrupts we'll be using */
6568 if (msi > 1 && enable_msix(adapter) == 0)
6569 adapter->flags |= USING_MSIX;
6570 else if (msi > 0 && pci_enable_msi(pdev) == 0)
6571 adapter->flags |= USING_MSI;
6572
671b0060
DM
6573 err = init_rss(adapter);
6574 if (err)
6575 goto out_free_dev;
6576
b8ff05a9
DM
6577 /*
6578 * The card is now ready to go. If any errors occur during device
6579 * registration we do not fail the whole card but rather proceed only
6580 * with the ports we manage to register successfully. However we must
6581 * register at least one net device.
6582 */
6583 for_each_port(adapter, i) {
a57cabe0
DM
6584 pi = adap2pinfo(adapter, i);
6585 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6586 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6587
b8ff05a9
DM
6588 err = register_netdev(adapter->port[i]);
6589 if (err)
b1a3c2b6 6590 break;
b1a3c2b6
DM
6591 adapter->chan_map[pi->tx_chan] = i;
6592 print_port_info(adapter->port[i]);
b8ff05a9 6593 }
b1a3c2b6 6594 if (i == 0) {
b8ff05a9
DM
6595 dev_err(&pdev->dev, "could not register any net devices\n");
6596 goto out_free_dev;
6597 }
b1a3c2b6
DM
6598 if (err) {
6599 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6600 err = 0;
6403eab1 6601 }
b8ff05a9
DM
6602
6603 if (cxgb4_debugfs_root) {
6604 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6605 cxgb4_debugfs_root);
6606 setup_debugfs(adapter);
6607 }
6608
6482aa7c
DLR
6609 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6610 pdev->needs_freset = 1;
6611
b8ff05a9
DM
6612 if (is_offload(adapter))
6613 attach_ulds(adapter);
6614
b8ff05a9 6615#ifdef CONFIG_PCI_IOV
7d6727cf 6616 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
b8ff05a9
DM
6617 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6618 dev_info(&pdev->dev,
6619 "instantiated %u virtual functions\n",
6620 num_vf[func]);
6621#endif
6622 return 0;
6623
6624 out_free_dev:
06546391 6625 free_some_resources(adapter);
b8ff05a9 6626 out_unmap_bar:
d14807dd 6627 if (!is_t4(adapter->params.chip))
22adfe0a
SR
6628 iounmap(adapter->bar2);
6629 out_unmap_bar0:
b8ff05a9
DM
6630 iounmap(adapter->regs);
6631 out_free_adapter:
6632 kfree(adapter);
6633 out_disable_device:
6634 pci_disable_pcie_error_reporting(pdev);
6635 pci_disable_device(pdev);
6636 out_release_regions:
6637 pci_release_regions(pdev);
b8ff05a9
DM
6638 return err;
6639}
6640
91744948 6641static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM
6642{
6643 struct adapter *adapter = pci_get_drvdata(pdev);
6644
636f9d37 6645#ifdef CONFIG_PCI_IOV
b8ff05a9
DM
6646 pci_disable_sriov(pdev);
6647
636f9d37
VP
6648#endif
6649
b8ff05a9
DM
6650 if (adapter) {
6651 int i;
6652
6653 if (is_offload(adapter))
6654 detach_ulds(adapter);
6655
6656 for_each_port(adapter, i)
8f3a7676 6657 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM
6658 unregister_netdev(adapter->port[i]);
6659
9f16dc2e 6660 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 6661
f2b7e78d
VP
6662 /* If we allocated filters, free up state associated with any
6663 * valid filters ...
6664 */
6665 if (adapter->tids.ftid_tab) {
6666 struct filter_entry *f = &adapter->tids.ftid_tab[0];
dca4faeb
VP
6667 for (i = 0; i < (adapter->tids.nftids +
6668 adapter->tids.nsftids); i++, f++)
f2b7e78d
VP
6669 if (f->valid)
6670 clear_filter(adapter, f);
6671 }
6672
aaefae9b
DM
6673 if (adapter->flags & FULL_INIT_DONE)
6674 cxgb_down(adapter);
b8ff05a9 6675
06546391 6676 free_some_resources(adapter);
b8ff05a9 6677 iounmap(adapter->regs);
d14807dd 6678 if (!is_t4(adapter->params.chip))
22adfe0a 6679 iounmap(adapter->bar2);
b8ff05a9 6680 pci_disable_pcie_error_reporting(pdev);
144be3d9
GS
6681 if ((adapter->flags & DEV_ENABLED)) {
6682 pci_disable_device(pdev);
6683 adapter->flags &= ~DEV_ENABLED;
6684 }
b8ff05a9 6685 pci_release_regions(pdev);
ee9a33b2 6686 synchronize_rcu();
8b662fe7 6687 kfree(adapter);
a069ec91 6688 } else
b8ff05a9
DM
6689 pci_release_regions(pdev);
6690}
6691
6692static struct pci_driver cxgb4_driver = {
6693 .name = KBUILD_MODNAME,
6694 .id_table = cxgb4_pci_tbl,
6695 .probe = init_one,
91744948 6696 .remove = remove_one,
687d705c 6697 .shutdown = remove_one,
204dc3c0 6698 .err_handler = &cxgb4_eeh,
b8ff05a9
DM
6699};
6700
6701static int __init cxgb4_init_module(void)
6702{
6703 int ret;
6704
3069ee9b
VP
6705 workq = create_singlethread_workqueue("cxgb4");
6706 if (!workq)
6707 return -ENOMEM;
6708
b8ff05a9
DM
6709 /* Debugfs support is optional, just warn if this fails */
6710 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6711 if (!cxgb4_debugfs_root)
428ac43f 6712 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM
6713
6714 ret = pci_register_driver(&cxgb4_driver);
73a695f8 6715 if (ret < 0) {
b8ff05a9 6716 debugfs_remove(cxgb4_debugfs_root);
73a695f8
WY
6717 destroy_workqueue(workq);
6718 }
01bcca68
VP
6719
6720 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6721
b8ff05a9
DM
6722 return ret;
6723}
6724
6725static void __exit cxgb4_cleanup_module(void)
6726{
01bcca68 6727 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
b8ff05a9
DM
6728 pci_unregister_driver(&cxgb4_driver);
6729 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
3069ee9b
VP
6730 flush_workqueue(workq);
6731 destroy_workqueue(workq);
b8ff05a9
DM
6732}
6733
6734module_init(cxgb4_init_module);
6735module_exit(cxgb4_cleanup_module);