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b8ff05a9 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
b8ff05a9 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
36 | ||
37 | #include <linux/bitmap.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <linux/ctype.h> | |
40 | #include <linux/debugfs.h> | |
41 | #include <linux/err.h> | |
42 | #include <linux/etherdevice.h> | |
43 | #include <linux/firmware.h> | |
01789349 | 44 | #include <linux/if.h> |
b8ff05a9 DM |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/init.h> | |
47 | #include <linux/log2.h> | |
48 | #include <linux/mdio.h> | |
49 | #include <linux/module.h> | |
50 | #include <linux/moduleparam.h> | |
51 | #include <linux/mutex.h> | |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/aer.h> | |
55 | #include <linux/rtnetlink.h> | |
56 | #include <linux/sched.h> | |
57 | #include <linux/seq_file.h> | |
58 | #include <linux/sockios.h> | |
59 | #include <linux/vmalloc.h> | |
60 | #include <linux/workqueue.h> | |
61 | #include <net/neighbour.h> | |
62 | #include <net/netevent.h> | |
01bcca68 | 63 | #include <net/addrconf.h> |
1ef8019b | 64 | #include <net/bonding.h> |
b5a02f50 | 65 | #include <net/addrconf.h> |
b8ff05a9 DM |
66 | #include <asm/uaccess.h> |
67 | ||
68 | #include "cxgb4.h" | |
69 | #include "t4_regs.h" | |
f612b815 | 70 | #include "t4_values.h" |
b8ff05a9 DM |
71 | #include "t4_msg.h" |
72 | #include "t4fw_api.h" | |
cd6c2f12 | 73 | #include "t4fw_version.h" |
688848b1 | 74 | #include "cxgb4_dcb.h" |
fd88b31a | 75 | #include "cxgb4_debugfs.h" |
b5a02f50 | 76 | #include "clip_tbl.h" |
b8ff05a9 DM |
77 | #include "l2t.h" |
78 | ||
812034f1 HS |
79 | char cxgb4_driver_name[] = KBUILD_MODNAME; |
80 | ||
01bcca68 VP |
81 | #ifdef DRV_VERSION |
82 | #undef DRV_VERSION | |
83 | #endif | |
3a7f8554 | 84 | #define DRV_VERSION "2.0.0-ko" |
812034f1 | 85 | const char cxgb4_driver_version[] = DRV_VERSION; |
52a5f846 | 86 | #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" |
b8ff05a9 | 87 | |
f2b7e78d VP |
88 | /* Host shadow copy of ingress filter entry. This is in host native format |
89 | * and doesn't match the ordering or bit order, etc. of the hardware of the | |
90 | * firmware command. The use of bit-field structure elements is purely to | |
91 | * remind ourselves of the field size limitations and save memory in the case | |
92 | * where the filter table is large. | |
93 | */ | |
94 | struct filter_entry { | |
95 | /* Administrative fields for filter. | |
96 | */ | |
97 | u32 valid:1; /* filter allocated and valid */ | |
98 | u32 locked:1; /* filter is administratively locked */ | |
99 | ||
100 | u32 pending:1; /* filter action is pending firmware reply */ | |
101 | u32 smtidx:8; /* Source MAC Table index for smac */ | |
102 | struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ | |
103 | ||
104 | /* The filter itself. Most of this is a straight copy of information | |
105 | * provided by the extended ioctl(). Some fields are translated to | |
106 | * internal forms -- for instance the Ingress Queue ID passed in from | |
107 | * the ioctl() is translated into the Absolute Ingress Queue ID. | |
108 | */ | |
109 | struct ch_filter_specification fs; | |
110 | }; | |
111 | ||
b8ff05a9 DM |
112 | #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ |
113 | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ | |
114 | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) | |
115 | ||
3fedeab1 HS |
116 | /* Macros needed to support the PCI Device ID Table ... |
117 | */ | |
118 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ | |
768ffc66 | 119 | static const struct pci_device_id cxgb4_pci_tbl[] = { |
3fedeab1 | 120 | #define CH_PCI_DEVICE_ID_FUNCTION 0x4 |
b8ff05a9 | 121 | |
3fedeab1 HS |
122 | /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is |
123 | * called for both. | |
124 | */ | |
125 | #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 | |
126 | ||
127 | #define CH_PCI_ID_TABLE_ENTRY(devid) \ | |
128 | {PCI_VDEVICE(CHELSIO, (devid)), 4} | |
129 | ||
130 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ | |
131 | { 0, } \ | |
132 | } | |
133 | ||
134 | #include "t4_pci_id_tbl.h" | |
b8ff05a9 | 135 | |
16e47624 | 136 | #define FW4_FNAME "cxgb4/t4fw.bin" |
0a57a536 | 137 | #define FW5_FNAME "cxgb4/t5fw.bin" |
3ccc6cf7 | 138 | #define FW6_FNAME "cxgb4/t6fw.bin" |
16e47624 | 139 | #define FW4_CFNAME "cxgb4/t4-config.txt" |
0a57a536 | 140 | #define FW5_CFNAME "cxgb4/t5-config.txt" |
3ccc6cf7 | 141 | #define FW6_CFNAME "cxgb4/t6-config.txt" |
01b69614 HS |
142 | #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" |
143 | #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" | |
144 | #define PHY_AQ1202_DEVICEID 0x4409 | |
145 | #define PHY_BCM84834_DEVICEID 0x4486 | |
b8ff05a9 DM |
146 | |
147 | MODULE_DESCRIPTION(DRV_DESC); | |
148 | MODULE_AUTHOR("Chelsio Communications"); | |
149 | MODULE_LICENSE("Dual BSD/GPL"); | |
150 | MODULE_VERSION(DRV_VERSION); | |
151 | MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); | |
16e47624 | 152 | MODULE_FIRMWARE(FW4_FNAME); |
0a57a536 | 153 | MODULE_FIRMWARE(FW5_FNAME); |
52a5f846 | 154 | MODULE_FIRMWARE(FW6_FNAME); |
b8ff05a9 | 155 | |
636f9d37 VP |
156 | /* |
157 | * Normally we're willing to become the firmware's Master PF but will be happy | |
158 | * if another PF has already become the Master and initialized the adapter. | |
159 | * Setting "force_init" will cause this driver to forcibly establish itself as | |
160 | * the Master PF and initialize the adapter. | |
161 | */ | |
162 | static uint force_init; | |
163 | ||
164 | module_param(force_init, uint, 0644); | |
165 | MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter"); | |
166 | ||
13ee15d3 VP |
167 | /* |
168 | * Normally if the firmware we connect to has Configuration File support, we | |
169 | * use that and only fall back to the old Driver-based initialization if the | |
170 | * Configuration File fails for some reason. If force_old_init is set, then | |
171 | * we'll always use the old Driver-based initialization sequence. | |
172 | */ | |
173 | static uint force_old_init; | |
174 | ||
175 | module_param(force_old_init, uint, 0644); | |
06640310 HS |
176 | MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated" |
177 | " parameter"); | |
13ee15d3 | 178 | |
b8ff05a9 DM |
179 | static int dflt_msg_enable = DFLT_MSG_ENABLE; |
180 | ||
181 | module_param(dflt_msg_enable, int, 0644); | |
182 | MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap"); | |
183 | ||
184 | /* | |
185 | * The driver uses the best interrupt scheme available on a platform in the | |
186 | * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which | |
187 | * of these schemes the driver may consider as follows: | |
188 | * | |
189 | * msi = 2: choose from among all three options | |
190 | * msi = 1: only consider MSI and INTx interrupts | |
191 | * msi = 0: force INTx interrupts | |
192 | */ | |
193 | static int msi = 2; | |
194 | ||
195 | module_param(msi, int, 0644); | |
196 | MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); | |
197 | ||
198 | /* | |
199 | * Queue interrupt hold-off timer values. Queues default to the first of these | |
200 | * upon creation. | |
201 | */ | |
202 | static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 }; | |
203 | ||
204 | module_param_array(intr_holdoff, uint, NULL, 0644); | |
205 | MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers " | |
06640310 | 206 | "0..4 in microseconds, deprecated parameter"); |
b8ff05a9 DM |
207 | |
208 | static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 }; | |
209 | ||
210 | module_param_array(intr_cnt, uint, NULL, 0644); | |
211 | MODULE_PARM_DESC(intr_cnt, | |
06640310 HS |
212 | "thresholds 1..3 for queue interrupt packet counters, " |
213 | "deprecated parameter"); | |
b8ff05a9 | 214 | |
636f9d37 VP |
215 | /* |
216 | * Normally we tell the chip to deliver Ingress Packets into our DMA buffers | |
217 | * offset by 2 bytes in order to have the IP headers line up on 4-byte | |
218 | * boundaries. This is a requirement for many architectures which will throw | |
219 | * a machine check fault if an attempt is made to access one of the 4-byte IP | |
220 | * header fields on a non-4-byte boundary. And it's a major performance issue | |
221 | * even on some architectures which allow it like some implementations of the | |
222 | * x86 ISA. However, some architectures don't mind this and for some very | |
223 | * edge-case performance sensitive applications (like forwarding large volumes | |
224 | * of small packets), setting this DMA offset to 0 will decrease the number of | |
225 | * PCI-E Bus transfers enough to measurably affect performance. | |
226 | */ | |
227 | static int rx_dma_offset = 2; | |
228 | ||
eb939922 | 229 | static bool vf_acls; |
b8ff05a9 DM |
230 | |
231 | #ifdef CONFIG_PCI_IOV | |
232 | module_param(vf_acls, bool, 0644); | |
06640310 HS |
233 | MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, " |
234 | "deprecated parameter"); | |
b8ff05a9 | 235 | |
7d6727cf SR |
236 | /* Configure the number of PCI-E Virtual Function which are to be instantiated |
237 | * on SR-IOV Capable Physical Functions. | |
0a57a536 | 238 | */ |
7d6727cf | 239 | static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV]; |
b8ff05a9 DM |
240 | |
241 | module_param_array(num_vf, uint, NULL, 0644); | |
7d6727cf | 242 | MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3"); |
b8ff05a9 DM |
243 | #endif |
244 | ||
688848b1 AB |
245 | /* TX Queue select used to determine what algorithm to use for selecting TX |
246 | * queue. Select between the kernel provided function (select_queue=0) or user | |
247 | * cxgb_select_queue function (select_queue=1) | |
248 | * | |
249 | * Default: select_queue=0 | |
250 | */ | |
251 | static int select_queue; | |
252 | module_param(select_queue, int, 0644); | |
253 | MODULE_PARM_DESC(select_queue, | |
254 | "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); | |
255 | ||
06640310 | 256 | static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC; |
13ee15d3 | 257 | |
f2b7e78d | 258 | module_param(tp_vlan_pri_map, uint, 0644); |
06640310 HS |
259 | MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, " |
260 | "deprecated parameter"); | |
f2b7e78d | 261 | |
b8ff05a9 DM |
262 | static struct dentry *cxgb4_debugfs_root; |
263 | ||
264 | static LIST_HEAD(adapter_list); | |
265 | static DEFINE_MUTEX(uld_mutex); | |
01bcca68 VP |
266 | /* Adapter list to be accessed from atomic context */ |
267 | static LIST_HEAD(adap_rcu_list); | |
268 | static DEFINE_SPINLOCK(adap_rcu_lock); | |
b8ff05a9 DM |
269 | static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX]; |
270 | static const char *uld_str[] = { "RDMA", "iSCSI" }; | |
271 | ||
272 | static void link_report(struct net_device *dev) | |
273 | { | |
274 | if (!netif_carrier_ok(dev)) | |
275 | netdev_info(dev, "link down\n"); | |
276 | else { | |
277 | static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; | |
278 | ||
85412255 | 279 | const char *s; |
b8ff05a9 DM |
280 | const struct port_info *p = netdev_priv(dev); |
281 | ||
282 | switch (p->link_cfg.speed) { | |
e8b39015 | 283 | case 10000: |
b8ff05a9 DM |
284 | s = "10Gbps"; |
285 | break; | |
e8b39015 | 286 | case 1000: |
b8ff05a9 DM |
287 | s = "1000Mbps"; |
288 | break; | |
e8b39015 | 289 | case 100: |
b8ff05a9 DM |
290 | s = "100Mbps"; |
291 | break; | |
e8b39015 | 292 | case 40000: |
72aca4bf KS |
293 | s = "40Gbps"; |
294 | break; | |
85412255 HS |
295 | default: |
296 | pr_info("%s: unsupported speed: %d\n", | |
297 | dev->name, p->link_cfg.speed); | |
298 | return; | |
b8ff05a9 DM |
299 | } |
300 | ||
301 | netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, | |
302 | fc[p->link_cfg.fc]); | |
303 | } | |
304 | } | |
305 | ||
688848b1 AB |
306 | #ifdef CONFIG_CHELSIO_T4_DCB |
307 | /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ | |
308 | static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) | |
309 | { | |
310 | struct port_info *pi = netdev_priv(dev); | |
311 | struct adapter *adap = pi->adapter; | |
312 | struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; | |
313 | int i; | |
314 | ||
315 | /* We use a simple mapping of Port TX Queue Index to DCB | |
316 | * Priority when we're enabling DCB. | |
317 | */ | |
318 | for (i = 0; i < pi->nqsets; i++, txq++) { | |
319 | u32 name, value; | |
320 | int err; | |
321 | ||
5167865a HS |
322 | name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
323 | FW_PARAMS_PARAM_X_V( | |
324 | FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | | |
325 | FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); | |
688848b1 AB |
326 | value = enable ? i : 0xffffffff; |
327 | ||
328 | /* Since we can be called while atomic (from "interrupt | |
329 | * level") we need to issue the Set Parameters Commannd | |
330 | * without sleeping (timeout < 0). | |
331 | */ | |
b2612722 | 332 | err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, |
01b69614 HS |
333 | &name, &value, |
334 | -FW_CMD_MAX_TIMEOUT); | |
688848b1 AB |
335 | |
336 | if (err) | |
337 | dev_err(adap->pdev_dev, | |
338 | "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", | |
339 | enable ? "set" : "unset", pi->port_id, i, -err); | |
10b00466 AB |
340 | else |
341 | txq->dcb_prio = value; | |
688848b1 AB |
342 | } |
343 | } | |
344 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
345 | ||
b8ff05a9 DM |
346 | void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) |
347 | { | |
348 | struct net_device *dev = adapter->port[port_id]; | |
349 | ||
350 | /* Skip changes from disabled ports. */ | |
351 | if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { | |
352 | if (link_stat) | |
353 | netif_carrier_on(dev); | |
688848b1 AB |
354 | else { |
355 | #ifdef CONFIG_CHELSIO_T4_DCB | |
356 | cxgb4_dcb_state_init(dev); | |
357 | dcb_tx_queue_prio_enable(dev, false); | |
358 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
b8ff05a9 | 359 | netif_carrier_off(dev); |
688848b1 | 360 | } |
b8ff05a9 DM |
361 | |
362 | link_report(dev); | |
363 | } | |
364 | } | |
365 | ||
366 | void t4_os_portmod_changed(const struct adapter *adap, int port_id) | |
367 | { | |
368 | static const char *mod_str[] = { | |
a0881cab | 369 | NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" |
b8ff05a9 DM |
370 | }; |
371 | ||
372 | const struct net_device *dev = adap->port[port_id]; | |
373 | const struct port_info *pi = netdev_priv(dev); | |
374 | ||
375 | if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) | |
376 | netdev_info(dev, "port module unplugged\n"); | |
a0881cab | 377 | else if (pi->mod_type < ARRAY_SIZE(mod_str)) |
b8ff05a9 DM |
378 | netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); |
379 | } | |
380 | ||
381 | /* | |
382 | * Configure the exact and hash address filters to handle a port's multicast | |
383 | * and secondary unicast MAC addresses. | |
384 | */ | |
385 | static int set_addr_filters(const struct net_device *dev, bool sleep) | |
386 | { | |
387 | u64 mhash = 0; | |
388 | u64 uhash = 0; | |
389 | bool free = true; | |
390 | u16 filt_idx[7]; | |
391 | const u8 *addr[7]; | |
392 | int ret, naddr = 0; | |
b8ff05a9 DM |
393 | const struct netdev_hw_addr *ha; |
394 | int uc_cnt = netdev_uc_count(dev); | |
4a35ecf8 | 395 | int mc_cnt = netdev_mc_count(dev); |
b8ff05a9 | 396 | const struct port_info *pi = netdev_priv(dev); |
b2612722 | 397 | unsigned int mb = pi->adapter->pf; |
b8ff05a9 DM |
398 | |
399 | /* first do the secondary unicast addresses */ | |
400 | netdev_for_each_uc_addr(ha, dev) { | |
401 | addr[naddr++] = ha->addr; | |
402 | if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) { | |
060e0c75 | 403 | ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free, |
b8ff05a9 DM |
404 | naddr, addr, filt_idx, &uhash, sleep); |
405 | if (ret < 0) | |
406 | return ret; | |
407 | ||
408 | free = false; | |
409 | naddr = 0; | |
410 | } | |
411 | } | |
412 | ||
413 | /* next set up the multicast addresses */ | |
4a35ecf8 DM |
414 | netdev_for_each_mc_addr(ha, dev) { |
415 | addr[naddr++] = ha->addr; | |
416 | if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) { | |
060e0c75 | 417 | ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free, |
b8ff05a9 DM |
418 | naddr, addr, filt_idx, &mhash, sleep); |
419 | if (ret < 0) | |
420 | return ret; | |
421 | ||
422 | free = false; | |
423 | naddr = 0; | |
424 | } | |
425 | } | |
426 | ||
060e0c75 | 427 | return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0, |
b8ff05a9 DM |
428 | uhash | mhash, sleep); |
429 | } | |
430 | ||
3069ee9b VP |
431 | int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ |
432 | module_param(dbfifo_int_thresh, int, 0644); | |
433 | MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); | |
434 | ||
404d9e3f VP |
435 | /* |
436 | * usecs to sleep while draining the dbfifo | |
437 | */ | |
438 | static int dbfifo_drain_delay = 1000; | |
3069ee9b VP |
439 | module_param(dbfifo_drain_delay, int, 0644); |
440 | MODULE_PARM_DESC(dbfifo_drain_delay, | |
441 | "usecs to sleep while draining the dbfifo"); | |
442 | ||
b8ff05a9 DM |
443 | /* |
444 | * Set Rx properties of a port, such as promiscruity, address filters, and MTU. | |
445 | * If @mtu is -1 it is left unchanged. | |
446 | */ | |
447 | static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) | |
448 | { | |
449 | int ret; | |
450 | struct port_info *pi = netdev_priv(dev); | |
451 | ||
452 | ret = set_addr_filters(dev, sleep_ok); | |
453 | if (ret == 0) | |
b2612722 | 454 | ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu, |
b8ff05a9 | 455 | (dev->flags & IFF_PROMISC) ? 1 : 0, |
f8f5aafa | 456 | (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, |
b8ff05a9 DM |
457 | sleep_ok); |
458 | return ret; | |
459 | } | |
460 | ||
461 | /** | |
462 | * link_start - enable a port | |
463 | * @dev: the port to enable | |
464 | * | |
465 | * Performs the MAC and PHY actions needed to enable a port. | |
466 | */ | |
467 | static int link_start(struct net_device *dev) | |
468 | { | |
469 | int ret; | |
470 | struct port_info *pi = netdev_priv(dev); | |
b2612722 | 471 | unsigned int mb = pi->adapter->pf; |
b8ff05a9 DM |
472 | |
473 | /* | |
474 | * We do not set address filters and promiscuity here, the stack does | |
475 | * that step explicitly. | |
476 | */ | |
060e0c75 | 477 | ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, |
f646968f | 478 | !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); |
b8ff05a9 | 479 | if (ret == 0) { |
060e0c75 | 480 | ret = t4_change_mac(pi->adapter, mb, pi->viid, |
b8ff05a9 | 481 | pi->xact_addr_filt, dev->dev_addr, true, |
b6bd29e7 | 482 | true); |
b8ff05a9 DM |
483 | if (ret >= 0) { |
484 | pi->xact_addr_filt = ret; | |
485 | ret = 0; | |
486 | } | |
487 | } | |
488 | if (ret == 0) | |
4036da90 | 489 | ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, |
060e0c75 | 490 | &pi->link_cfg); |
30f00847 AB |
491 | if (ret == 0) { |
492 | local_bh_disable(); | |
688848b1 AB |
493 | ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true, |
494 | true, CXGB4_DCB_ENABLED); | |
30f00847 AB |
495 | local_bh_enable(); |
496 | } | |
688848b1 | 497 | |
b8ff05a9 DM |
498 | return ret; |
499 | } | |
500 | ||
688848b1 AB |
501 | int cxgb4_dcb_enabled(const struct net_device *dev) |
502 | { | |
503 | #ifdef CONFIG_CHELSIO_T4_DCB | |
504 | struct port_info *pi = netdev_priv(dev); | |
505 | ||
3bb06261 AB |
506 | if (!pi->dcb.enabled) |
507 | return 0; | |
508 | ||
509 | return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || | |
510 | (pi->dcb.state == CXGB4_DCB_STATE_HOST)); | |
688848b1 AB |
511 | #else |
512 | return 0; | |
513 | #endif | |
514 | } | |
515 | EXPORT_SYMBOL(cxgb4_dcb_enabled); | |
516 | ||
517 | #ifdef CONFIG_CHELSIO_T4_DCB | |
518 | /* Handle a Data Center Bridging update message from the firmware. */ | |
519 | static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) | |
520 | { | |
2b5fb1f2 | 521 | int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); |
688848b1 AB |
522 | struct net_device *dev = adap->port[port]; |
523 | int old_dcb_enabled = cxgb4_dcb_enabled(dev); | |
524 | int new_dcb_enabled; | |
525 | ||
526 | cxgb4_dcb_handle_fw_update(adap, pcmd); | |
527 | new_dcb_enabled = cxgb4_dcb_enabled(dev); | |
528 | ||
529 | /* If the DCB has become enabled or disabled on the port then we're | |
530 | * going to need to set up/tear down DCB Priority parameters for the | |
531 | * TX Queues associated with the port. | |
532 | */ | |
533 | if (new_dcb_enabled != old_dcb_enabled) | |
534 | dcb_tx_queue_prio_enable(dev, new_dcb_enabled); | |
535 | } | |
536 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
537 | ||
f2b7e78d VP |
538 | /* Clear a filter and release any of its resources that we own. This also |
539 | * clears the filter's "pending" status. | |
540 | */ | |
541 | static void clear_filter(struct adapter *adap, struct filter_entry *f) | |
542 | { | |
543 | /* If the new or old filter have loopback rewriteing rules then we'll | |
544 | * need to free any existing Layer Two Table (L2T) entries of the old | |
545 | * filter rule. The firmware will handle freeing up any Source MAC | |
546 | * Table (SMT) entries used for rewriting Source MAC Addresses in | |
547 | * loopback rules. | |
548 | */ | |
549 | if (f->l2t) | |
550 | cxgb4_l2t_release(f->l2t); | |
551 | ||
552 | /* The zeroing of the filter rule below clears the filter valid, | |
553 | * pending, locked flags, l2t pointer, etc. so it's all we need for | |
554 | * this operation. | |
555 | */ | |
556 | memset(f, 0, sizeof(*f)); | |
557 | } | |
558 | ||
559 | /* Handle a filter write/deletion reply. | |
560 | */ | |
561 | static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl) | |
562 | { | |
563 | unsigned int idx = GET_TID(rpl); | |
564 | unsigned int nidx = idx - adap->tids.ftid_base; | |
565 | unsigned int ret; | |
566 | struct filter_entry *f; | |
567 | ||
568 | if (idx >= adap->tids.ftid_base && nidx < | |
569 | (adap->tids.nftids + adap->tids.nsftids)) { | |
570 | idx = nidx; | |
bdc590b9 | 571 | ret = TCB_COOKIE_G(rpl->cookie); |
f2b7e78d VP |
572 | f = &adap->tids.ftid_tab[idx]; |
573 | ||
574 | if (ret == FW_FILTER_WR_FLT_DELETED) { | |
575 | /* Clear the filter when we get confirmation from the | |
576 | * hardware that the filter has been deleted. | |
577 | */ | |
578 | clear_filter(adap, f); | |
579 | } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) { | |
580 | dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n", | |
581 | idx); | |
582 | clear_filter(adap, f); | |
583 | } else if (ret == FW_FILTER_WR_FLT_ADDED) { | |
584 | f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff; | |
585 | f->pending = 0; /* asynchronous setup completed */ | |
586 | f->valid = 1; | |
587 | } else { | |
588 | /* Something went wrong. Issue a warning about the | |
589 | * problem and clear everything out. | |
590 | */ | |
591 | dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n", | |
592 | idx, ret); | |
593 | clear_filter(adap, f); | |
594 | } | |
595 | } | |
596 | } | |
597 | ||
598 | /* Response queue handler for the FW event queue. | |
b8ff05a9 DM |
599 | */ |
600 | static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, | |
601 | const struct pkt_gl *gl) | |
602 | { | |
603 | u8 opcode = ((const struct rss_header *)rsp)->opcode; | |
604 | ||
605 | rsp++; /* skip RSS header */ | |
b407a4a9 VP |
606 | |
607 | /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. | |
608 | */ | |
609 | if (unlikely(opcode == CPL_FW4_MSG && | |
610 | ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { | |
611 | rsp++; | |
612 | opcode = ((const struct rss_header *)rsp)->opcode; | |
613 | rsp++; | |
614 | if (opcode != CPL_SGE_EGR_UPDATE) { | |
615 | dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" | |
616 | , opcode); | |
617 | goto out; | |
618 | } | |
619 | } | |
620 | ||
b8ff05a9 DM |
621 | if (likely(opcode == CPL_SGE_EGR_UPDATE)) { |
622 | const struct cpl_sge_egr_update *p = (void *)rsp; | |
bdc590b9 | 623 | unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); |
e46dab4d | 624 | struct sge_txq *txq; |
b8ff05a9 | 625 | |
e46dab4d | 626 | txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; |
b8ff05a9 | 627 | txq->restarts++; |
e46dab4d | 628 | if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) { |
b8ff05a9 DM |
629 | struct sge_eth_txq *eq; |
630 | ||
631 | eq = container_of(txq, struct sge_eth_txq, q); | |
632 | netif_tx_wake_queue(eq->txq); | |
633 | } else { | |
634 | struct sge_ofld_txq *oq; | |
635 | ||
636 | oq = container_of(txq, struct sge_ofld_txq, q); | |
637 | tasklet_schedule(&oq->qresume_tsk); | |
638 | } | |
639 | } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { | |
640 | const struct cpl_fw6_msg *p = (void *)rsp; | |
641 | ||
688848b1 AB |
642 | #ifdef CONFIG_CHELSIO_T4_DCB |
643 | const struct fw_port_cmd *pcmd = (const void *)p->data; | |
e2ac9628 | 644 | unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); |
688848b1 | 645 | unsigned int action = |
2b5fb1f2 | 646 | FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); |
688848b1 AB |
647 | |
648 | if (cmd == FW_PORT_CMD && | |
649 | action == FW_PORT_ACTION_GET_PORT_INFO) { | |
2b5fb1f2 | 650 | int port = FW_PORT_CMD_PORTID_G( |
688848b1 AB |
651 | be32_to_cpu(pcmd->op_to_portid)); |
652 | struct net_device *dev = q->adap->port[port]; | |
653 | int state_input = ((pcmd->u.info.dcbxdis_pkd & | |
2b5fb1f2 | 654 | FW_PORT_CMD_DCBXDIS_F) |
688848b1 AB |
655 | ? CXGB4_DCB_INPUT_FW_DISABLED |
656 | : CXGB4_DCB_INPUT_FW_ENABLED); | |
657 | ||
658 | cxgb4_dcb_state_fsm(dev, state_input); | |
659 | } | |
660 | ||
661 | if (cmd == FW_PORT_CMD && | |
662 | action == FW_PORT_ACTION_L2_DCB_CFG) | |
663 | dcb_rpl(q->adap, pcmd); | |
664 | else | |
665 | #endif | |
666 | if (p->type == 0) | |
667 | t4_handle_fw_rpl(q->adap, p->data); | |
b8ff05a9 DM |
668 | } else if (opcode == CPL_L2T_WRITE_RPL) { |
669 | const struct cpl_l2t_write_rpl *p = (void *)rsp; | |
670 | ||
671 | do_l2t_write_rpl(q->adap, p); | |
f2b7e78d VP |
672 | } else if (opcode == CPL_SET_TCB_RPL) { |
673 | const struct cpl_set_tcb_rpl *p = (void *)rsp; | |
674 | ||
675 | filter_rpl(q->adap, p); | |
b8ff05a9 DM |
676 | } else |
677 | dev_err(q->adap->pdev_dev, | |
678 | "unexpected CPL %#x on FW event queue\n", opcode); | |
b407a4a9 | 679 | out: |
b8ff05a9 DM |
680 | return 0; |
681 | } | |
682 | ||
683 | /** | |
684 | * uldrx_handler - response queue handler for ULD queues | |
685 | * @q: the response queue that received the packet | |
686 | * @rsp: the response queue descriptor holding the offload message | |
687 | * @gl: the gather list of packet fragments | |
688 | * | |
689 | * Deliver an ingress offload packet to a ULD. All processing is done by | |
690 | * the ULD, we just maintain statistics. | |
691 | */ | |
692 | static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp, | |
693 | const struct pkt_gl *gl) | |
694 | { | |
695 | struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq); | |
696 | ||
b407a4a9 VP |
697 | /* FW can send CPLs encapsulated in a CPL_FW4_MSG. |
698 | */ | |
699 | if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG && | |
700 | ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL) | |
701 | rsp += 2; | |
702 | ||
b8ff05a9 DM |
703 | if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) { |
704 | rxq->stats.nomem++; | |
705 | return -1; | |
706 | } | |
707 | if (gl == NULL) | |
708 | rxq->stats.imm++; | |
709 | else if (gl == CXGB4_MSG_AN) | |
710 | rxq->stats.an++; | |
711 | else | |
712 | rxq->stats.pkts++; | |
713 | return 0; | |
714 | } | |
715 | ||
716 | static void disable_msi(struct adapter *adapter) | |
717 | { | |
718 | if (adapter->flags & USING_MSIX) { | |
719 | pci_disable_msix(adapter->pdev); | |
720 | adapter->flags &= ~USING_MSIX; | |
721 | } else if (adapter->flags & USING_MSI) { | |
722 | pci_disable_msi(adapter->pdev); | |
723 | adapter->flags &= ~USING_MSI; | |
724 | } | |
725 | } | |
726 | ||
727 | /* | |
728 | * Interrupt handler for non-data events used with MSI-X. | |
729 | */ | |
730 | static irqreturn_t t4_nondata_intr(int irq, void *cookie) | |
731 | { | |
732 | struct adapter *adap = cookie; | |
0d804338 | 733 | u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); |
b8ff05a9 | 734 | |
0d804338 | 735 | if (v & PFSW_F) { |
b8ff05a9 | 736 | adap->swintr = 1; |
0d804338 | 737 | t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); |
b8ff05a9 | 738 | } |
c3c7b121 HS |
739 | if (adap->flags & MASTER_PF) |
740 | t4_slow_intr_handler(adap); | |
b8ff05a9 DM |
741 | return IRQ_HANDLED; |
742 | } | |
743 | ||
744 | /* | |
745 | * Name the MSI-X interrupts. | |
746 | */ | |
747 | static void name_msix_vecs(struct adapter *adap) | |
748 | { | |
ba27816c | 749 | int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); |
b8ff05a9 DM |
750 | |
751 | /* non-data interrupts */ | |
b1a3c2b6 | 752 | snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); |
b8ff05a9 DM |
753 | |
754 | /* FW events */ | |
b1a3c2b6 DM |
755 | snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", |
756 | adap->port[0]->name); | |
b8ff05a9 DM |
757 | |
758 | /* Ethernet queues */ | |
759 | for_each_port(adap, j) { | |
760 | struct net_device *d = adap->port[j]; | |
761 | const struct port_info *pi = netdev_priv(d); | |
762 | ||
ba27816c | 763 | for (i = 0; i < pi->nqsets; i++, msi_idx++) |
b8ff05a9 DM |
764 | snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", |
765 | d->name, i); | |
b8ff05a9 DM |
766 | } |
767 | ||
768 | /* offload queues */ | |
ba27816c DM |
769 | for_each_ofldrxq(&adap->sge, i) |
770 | snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d", | |
b1a3c2b6 | 771 | adap->port[0]->name, i); |
ba27816c DM |
772 | |
773 | for_each_rdmarxq(&adap->sge, i) | |
774 | snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d", | |
b1a3c2b6 | 775 | adap->port[0]->name, i); |
cf38be6d HS |
776 | |
777 | for_each_rdmaciq(&adap->sge, i) | |
778 | snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d", | |
779 | adap->port[0]->name, i); | |
b8ff05a9 DM |
780 | } |
781 | ||
782 | static int request_msix_queue_irqs(struct adapter *adap) | |
783 | { | |
784 | struct sge *s = &adap->sge; | |
cf38be6d HS |
785 | int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0; |
786 | int msi_index = 2; | |
b8ff05a9 DM |
787 | |
788 | err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, | |
789 | adap->msix_info[1].desc, &s->fw_evtq); | |
790 | if (err) | |
791 | return err; | |
792 | ||
793 | for_each_ethrxq(s, ethqidx) { | |
404d9e3f VP |
794 | err = request_irq(adap->msix_info[msi_index].vec, |
795 | t4_sge_intr_msix, 0, | |
796 | adap->msix_info[msi_index].desc, | |
b8ff05a9 DM |
797 | &s->ethrxq[ethqidx].rspq); |
798 | if (err) | |
799 | goto unwind; | |
404d9e3f | 800 | msi_index++; |
b8ff05a9 DM |
801 | } |
802 | for_each_ofldrxq(s, ofldqidx) { | |
404d9e3f VP |
803 | err = request_irq(adap->msix_info[msi_index].vec, |
804 | t4_sge_intr_msix, 0, | |
805 | adap->msix_info[msi_index].desc, | |
b8ff05a9 DM |
806 | &s->ofldrxq[ofldqidx].rspq); |
807 | if (err) | |
808 | goto unwind; | |
404d9e3f | 809 | msi_index++; |
b8ff05a9 DM |
810 | } |
811 | for_each_rdmarxq(s, rdmaqidx) { | |
404d9e3f VP |
812 | err = request_irq(adap->msix_info[msi_index].vec, |
813 | t4_sge_intr_msix, 0, | |
814 | adap->msix_info[msi_index].desc, | |
b8ff05a9 DM |
815 | &s->rdmarxq[rdmaqidx].rspq); |
816 | if (err) | |
817 | goto unwind; | |
404d9e3f | 818 | msi_index++; |
b8ff05a9 | 819 | } |
cf38be6d HS |
820 | for_each_rdmaciq(s, rdmaciqqidx) { |
821 | err = request_irq(adap->msix_info[msi_index].vec, | |
822 | t4_sge_intr_msix, 0, | |
823 | adap->msix_info[msi_index].desc, | |
824 | &s->rdmaciq[rdmaciqqidx].rspq); | |
825 | if (err) | |
826 | goto unwind; | |
827 | msi_index++; | |
828 | } | |
b8ff05a9 DM |
829 | return 0; |
830 | ||
831 | unwind: | |
cf38be6d HS |
832 | while (--rdmaciqqidx >= 0) |
833 | free_irq(adap->msix_info[--msi_index].vec, | |
834 | &s->rdmaciq[rdmaciqqidx].rspq); | |
b8ff05a9 | 835 | while (--rdmaqidx >= 0) |
404d9e3f | 836 | free_irq(adap->msix_info[--msi_index].vec, |
b8ff05a9 DM |
837 | &s->rdmarxq[rdmaqidx].rspq); |
838 | while (--ofldqidx >= 0) | |
404d9e3f | 839 | free_irq(adap->msix_info[--msi_index].vec, |
b8ff05a9 DM |
840 | &s->ofldrxq[ofldqidx].rspq); |
841 | while (--ethqidx >= 0) | |
404d9e3f VP |
842 | free_irq(adap->msix_info[--msi_index].vec, |
843 | &s->ethrxq[ethqidx].rspq); | |
b8ff05a9 DM |
844 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); |
845 | return err; | |
846 | } | |
847 | ||
848 | static void free_msix_queue_irqs(struct adapter *adap) | |
849 | { | |
404d9e3f | 850 | int i, msi_index = 2; |
b8ff05a9 DM |
851 | struct sge *s = &adap->sge; |
852 | ||
853 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); | |
854 | for_each_ethrxq(s, i) | |
404d9e3f | 855 | free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); |
b8ff05a9 | 856 | for_each_ofldrxq(s, i) |
404d9e3f | 857 | free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq); |
b8ff05a9 | 858 | for_each_rdmarxq(s, i) |
404d9e3f | 859 | free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq); |
cf38be6d HS |
860 | for_each_rdmaciq(s, i) |
861 | free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq); | |
b8ff05a9 DM |
862 | } |
863 | ||
671b0060 | 864 | /** |
812034f1 | 865 | * cxgb4_write_rss - write the RSS table for a given port |
671b0060 DM |
866 | * @pi: the port |
867 | * @queues: array of queue indices for RSS | |
868 | * | |
869 | * Sets up the portion of the HW RSS table for the port's VI to distribute | |
870 | * packets to the Rx queues in @queues. | |
c035e183 | 871 | * Should never be called before setting up sge eth rx queues |
671b0060 | 872 | */ |
812034f1 | 873 | int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) |
671b0060 DM |
874 | { |
875 | u16 *rss; | |
876 | int i, err; | |
c035e183 HS |
877 | struct adapter *adapter = pi->adapter; |
878 | const struct sge_eth_rxq *rxq; | |
671b0060 | 879 | |
c035e183 | 880 | rxq = &adapter->sge.ethrxq[pi->first_qset]; |
671b0060 DM |
881 | rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL); |
882 | if (!rss) | |
883 | return -ENOMEM; | |
884 | ||
885 | /* map the queue indices to queue ids */ | |
886 | for (i = 0; i < pi->rss_size; i++, queues++) | |
c035e183 | 887 | rss[i] = rxq[*queues].rspq.abs_id; |
671b0060 | 888 | |
b2612722 | 889 | err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, |
060e0c75 | 890 | pi->rss_size, rss, pi->rss_size); |
c035e183 HS |
891 | /* If Tunnel All Lookup isn't specified in the global RSS |
892 | * Configuration, then we need to specify a default Ingress | |
893 | * Queue for any ingress packets which aren't hashed. We'll | |
894 | * use our first ingress queue ... | |
895 | */ | |
896 | if (!err) | |
897 | err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, | |
898 | FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | | |
899 | FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | | |
900 | FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | | |
901 | FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | | |
902 | FW_RSS_VI_CONFIG_CMD_UDPEN_F, | |
903 | rss[0]); | |
671b0060 DM |
904 | kfree(rss); |
905 | return err; | |
906 | } | |
907 | ||
b8ff05a9 DM |
908 | /** |
909 | * setup_rss - configure RSS | |
910 | * @adap: the adapter | |
911 | * | |
671b0060 | 912 | * Sets up RSS for each port. |
b8ff05a9 DM |
913 | */ |
914 | static int setup_rss(struct adapter *adap) | |
915 | { | |
c035e183 | 916 | int i, j, err; |
b8ff05a9 DM |
917 | |
918 | for_each_port(adap, i) { | |
919 | const struct port_info *pi = adap2pinfo(adap, i); | |
b8ff05a9 | 920 | |
c035e183 HS |
921 | /* Fill default values with equal distribution */ |
922 | for (j = 0; j < pi->rss_size; j++) | |
923 | pi->rss[j] = j % pi->nqsets; | |
924 | ||
812034f1 | 925 | err = cxgb4_write_rss(pi, pi->rss); |
b8ff05a9 DM |
926 | if (err) |
927 | return err; | |
928 | } | |
929 | return 0; | |
930 | } | |
931 | ||
e46dab4d DM |
932 | /* |
933 | * Return the channel of the ingress queue with the given qid. | |
934 | */ | |
935 | static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) | |
936 | { | |
937 | qid -= p->ingr_start; | |
938 | return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; | |
939 | } | |
940 | ||
b8ff05a9 DM |
941 | /* |
942 | * Wait until all NAPI handlers are descheduled. | |
943 | */ | |
944 | static void quiesce_rx(struct adapter *adap) | |
945 | { | |
946 | int i; | |
947 | ||
4b8e27a8 | 948 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
949 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
950 | ||
3a336cb1 | 951 | if (q && q->handler) { |
b8ff05a9 | 952 | napi_disable(&q->napi); |
3a336cb1 HS |
953 | local_bh_disable(); |
954 | while (!cxgb_poll_lock_napi(q)) | |
955 | mdelay(1); | |
956 | local_bh_enable(); | |
957 | } | |
958 | ||
b8ff05a9 DM |
959 | } |
960 | } | |
961 | ||
b37987e8 HS |
962 | /* Disable interrupt and napi handler */ |
963 | static void disable_interrupts(struct adapter *adap) | |
964 | { | |
965 | if (adap->flags & FULL_INIT_DONE) { | |
966 | t4_intr_disable(adap); | |
967 | if (adap->flags & USING_MSIX) { | |
968 | free_msix_queue_irqs(adap); | |
969 | free_irq(adap->msix_info[0].vec, adap); | |
970 | } else { | |
971 | free_irq(adap->pdev->irq, adap); | |
972 | } | |
973 | quiesce_rx(adap); | |
974 | } | |
975 | } | |
976 | ||
b8ff05a9 DM |
977 | /* |
978 | * Enable NAPI scheduling and interrupt generation for all Rx queues. | |
979 | */ | |
980 | static void enable_rx(struct adapter *adap) | |
981 | { | |
982 | int i; | |
983 | ||
4b8e27a8 | 984 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
985 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
986 | ||
987 | if (!q) | |
988 | continue; | |
3a336cb1 HS |
989 | if (q->handler) { |
990 | cxgb_busy_poll_init_lock(q); | |
b8ff05a9 | 991 | napi_enable(&q->napi); |
3a336cb1 | 992 | } |
b8ff05a9 | 993 | /* 0-increment GTS to start the timer and enable interrupts */ |
f612b815 HS |
994 | t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), |
995 | SEINTARM_V(q->intr_params) | | |
996 | INGRESSQID_V(q->cntxt_id)); | |
b8ff05a9 DM |
997 | } |
998 | } | |
999 | ||
1c6a5b0e HS |
1000 | static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q, |
1001 | unsigned int nq, unsigned int per_chan, int msi_idx, | |
1002 | u16 *ids) | |
1003 | { | |
1004 | int i, err; | |
1005 | ||
1006 | for (i = 0; i < nq; i++, q++) { | |
1007 | if (msi_idx > 0) | |
1008 | msi_idx++; | |
1009 | err = t4_sge_alloc_rxq(adap, &q->rspq, false, | |
1010 | adap->port[i / per_chan], | |
1011 | msi_idx, q->fl.size ? &q->fl : NULL, | |
145ef8a5 | 1012 | uldrx_handler, 0); |
1c6a5b0e HS |
1013 | if (err) |
1014 | return err; | |
1015 | memset(&q->stats, 0, sizeof(q->stats)); | |
1016 | if (ids) | |
1017 | ids[i] = q->rspq.abs_id; | |
1018 | } | |
1019 | return 0; | |
1020 | } | |
1021 | ||
b8ff05a9 DM |
1022 | /** |
1023 | * setup_sge_queues - configure SGE Tx/Rx/response queues | |
1024 | * @adap: the adapter | |
1025 | * | |
1026 | * Determines how many sets of SGE queues to use and initializes them. | |
1027 | * We support multiple queue sets per port if we have MSI-X, otherwise | |
1028 | * just one queue set per port. | |
1029 | */ | |
1030 | static int setup_sge_queues(struct adapter *adap) | |
1031 | { | |
1032 | int err, msi_idx, i, j; | |
1033 | struct sge *s = &adap->sge; | |
1034 | ||
4b8e27a8 HS |
1035 | bitmap_zero(s->starving_fl, s->egr_sz); |
1036 | bitmap_zero(s->txq_maperr, s->egr_sz); | |
b8ff05a9 DM |
1037 | |
1038 | if (adap->flags & USING_MSIX) | |
1039 | msi_idx = 1; /* vector 0 is for non-queue interrupts */ | |
1040 | else { | |
1041 | err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, | |
145ef8a5 | 1042 | NULL, NULL, -1); |
b8ff05a9 DM |
1043 | if (err) |
1044 | return err; | |
1045 | msi_idx = -((int)s->intrq.abs_id + 1); | |
1046 | } | |
1047 | ||
4b8e27a8 HS |
1048 | /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here, |
1049 | * don't forget to update the following which need to be | |
1050 | * synchronized to and changes here. | |
1051 | * | |
1052 | * 1. The calculations of MAX_INGQ in cxgb4.h. | |
1053 | * | |
1054 | * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs | |
1055 | * to accommodate any new/deleted Ingress Queues | |
1056 | * which need MSI-X Vectors. | |
1057 | * | |
1058 | * 3. Update sge_qinfo_show() to include information on the | |
1059 | * new/deleted queues. | |
1060 | */ | |
b8ff05a9 | 1061 | err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], |
145ef8a5 | 1062 | msi_idx, NULL, fwevtq_handler, -1); |
b8ff05a9 DM |
1063 | if (err) { |
1064 | freeout: t4_free_sge_resources(adap); | |
1065 | return err; | |
1066 | } | |
1067 | ||
1068 | for_each_port(adap, i) { | |
1069 | struct net_device *dev = adap->port[i]; | |
1070 | struct port_info *pi = netdev_priv(dev); | |
1071 | struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; | |
1072 | struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; | |
1073 | ||
1074 | for (j = 0; j < pi->nqsets; j++, q++) { | |
1075 | if (msi_idx > 0) | |
1076 | msi_idx++; | |
1077 | err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, | |
1078 | msi_idx, &q->fl, | |
145ef8a5 HS |
1079 | t4_ethrx_handler, |
1080 | t4_get_mps_bg_map(adap, | |
1081 | pi->tx_chan)); | |
b8ff05a9 DM |
1082 | if (err) |
1083 | goto freeout; | |
1084 | q->rspq.idx = j; | |
1085 | memset(&q->stats, 0, sizeof(q->stats)); | |
1086 | } | |
1087 | for (j = 0; j < pi->nqsets; j++, t++) { | |
1088 | err = t4_sge_alloc_eth_txq(adap, t, dev, | |
1089 | netdev_get_tx_queue(dev, j), | |
1090 | s->fw_evtq.cntxt_id); | |
1091 | if (err) | |
1092 | goto freeout; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */ | |
1097 | for_each_ofldrxq(s, i) { | |
1c6a5b0e HS |
1098 | err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], |
1099 | adap->port[i / j], | |
b8ff05a9 DM |
1100 | s->fw_evtq.cntxt_id); |
1101 | if (err) | |
1102 | goto freeout; | |
1103 | } | |
1104 | ||
1c6a5b0e HS |
1105 | #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \ |
1106 | err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \ | |
1107 | if (err) \ | |
1108 | goto freeout; \ | |
1109 | if (msi_idx > 0) \ | |
1110 | msi_idx += nq; \ | |
1111 | } while (0) | |
b8ff05a9 | 1112 | |
1c6a5b0e HS |
1113 | ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq); |
1114 | ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq); | |
f36e58e5 HS |
1115 | j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */ |
1116 | ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq); | |
b8ff05a9 | 1117 | |
1c6a5b0e | 1118 | #undef ALLOC_OFLD_RXQS |
cf38be6d | 1119 | |
b8ff05a9 DM |
1120 | for_each_port(adap, i) { |
1121 | /* | |
1122 | * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't | |
1123 | * have RDMA queues, and that's the right value. | |
1124 | */ | |
1125 | err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], | |
1126 | s->fw_evtq.cntxt_id, | |
1127 | s->rdmarxq[i].rspq.cntxt_id); | |
1128 | if (err) | |
1129 | goto freeout; | |
1130 | } | |
1131 | ||
9bb59b96 | 1132 | t4_write_reg(adap, is_t4(adap->params.chip) ? |
837e4a42 HS |
1133 | MPS_TRC_RSS_CONTROL_A : |
1134 | MPS_T5_TRC_RSS_CONTROL_A, | |
1135 | RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | | |
1136 | QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); | |
b8ff05a9 DM |
1137 | return 0; |
1138 | } | |
1139 | ||
b8ff05a9 DM |
1140 | /* |
1141 | * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc. | |
1142 | * The allocated memory is cleared. | |
1143 | */ | |
1144 | void *t4_alloc_mem(size_t size) | |
1145 | { | |
8be04b93 | 1146 | void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); |
b8ff05a9 DM |
1147 | |
1148 | if (!p) | |
89bf67f1 | 1149 | p = vzalloc(size); |
b8ff05a9 DM |
1150 | return p; |
1151 | } | |
1152 | ||
1153 | /* | |
1154 | * Free memory allocated through alloc_mem(). | |
1155 | */ | |
fd88b31a | 1156 | void t4_free_mem(void *addr) |
b8ff05a9 | 1157 | { |
d2fcb548 | 1158 | kvfree(addr); |
b8ff05a9 DM |
1159 | } |
1160 | ||
f2b7e78d VP |
1161 | /* Send a Work Request to write the filter at a specified index. We construct |
1162 | * a Firmware Filter Work Request to have the work done and put the indicated | |
1163 | * filter into "pending" mode which will prevent any further actions against | |
1164 | * it till we get a reply from the firmware on the completion status of the | |
1165 | * request. | |
1166 | */ | |
1167 | static int set_filter_wr(struct adapter *adapter, int fidx) | |
1168 | { | |
1169 | struct filter_entry *f = &adapter->tids.ftid_tab[fidx]; | |
1170 | struct sk_buff *skb; | |
1171 | struct fw_filter_wr *fwr; | |
1172 | unsigned int ftid; | |
1173 | ||
f72f116a MH |
1174 | skb = alloc_skb(sizeof(*fwr), GFP_KERNEL); |
1175 | if (!skb) | |
1176 | return -ENOMEM; | |
1177 | ||
f2b7e78d VP |
1178 | /* If the new filter requires loopback Destination MAC and/or VLAN |
1179 | * rewriting then we need to allocate a Layer 2 Table (L2T) entry for | |
1180 | * the filter. | |
1181 | */ | |
1182 | if (f->fs.newdmac || f->fs.newvlan) { | |
1183 | /* allocate L2T entry for new filter */ | |
f7502659 HS |
1184 | f->l2t = t4_l2t_alloc_switching(adapter, f->fs.vlan, |
1185 | f->fs.eport, f->fs.dmac); | |
f72f116a | 1186 | if (f->l2t == NULL) { |
f72f116a | 1187 | kfree_skb(skb); |
f2b7e78d VP |
1188 | return -ENOMEM; |
1189 | } | |
1190 | } | |
1191 | ||
1192 | ftid = adapter->tids.ftid_base + fidx; | |
1193 | ||
f2b7e78d VP |
1194 | fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr)); |
1195 | memset(fwr, 0, sizeof(*fwr)); | |
1196 | ||
1197 | /* It would be nice to put most of the following in t4_hw.c but most | |
1198 | * of the work is translating the cxgbtool ch_filter_specification | |
1199 | * into the Work Request and the definition of that structure is | |
1200 | * currently in cxgbtool.h which isn't appropriate to pull into the | |
1201 | * common code. We may eventually try to come up with a more neutral | |
1202 | * filter specification structure but for now it's easiest to simply | |
1203 | * put this fairly direct code in line ... | |
1204 | */ | |
e2ac9628 HS |
1205 | fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR)); |
1206 | fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16)); | |
f2b7e78d | 1207 | fwr->tid_to_iq = |
77a80e23 HS |
1208 | htonl(FW_FILTER_WR_TID_V(ftid) | |
1209 | FW_FILTER_WR_RQTYPE_V(f->fs.type) | | |
1210 | FW_FILTER_WR_NOREPLY_V(0) | | |
1211 | FW_FILTER_WR_IQ_V(f->fs.iq)); | |
f2b7e78d | 1212 | fwr->del_filter_to_l2tix = |
77a80e23 HS |
1213 | htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) | |
1214 | FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) | | |
1215 | FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) | | |
1216 | FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) | | |
1217 | FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) | | |
1218 | FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) | | |
1219 | FW_FILTER_WR_DMAC_V(f->fs.newdmac) | | |
1220 | FW_FILTER_WR_SMAC_V(f->fs.newsmac) | | |
1221 | FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT || | |
f2b7e78d | 1222 | f->fs.newvlan == VLAN_REWRITE) | |
77a80e23 | 1223 | FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE || |
f2b7e78d | 1224 | f->fs.newvlan == VLAN_REWRITE) | |
77a80e23 HS |
1225 | FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) | |
1226 | FW_FILTER_WR_TXCHAN_V(f->fs.eport) | | |
1227 | FW_FILTER_WR_PRIO_V(f->fs.prio) | | |
1228 | FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0)); | |
f2b7e78d VP |
1229 | fwr->ethtype = htons(f->fs.val.ethtype); |
1230 | fwr->ethtypem = htons(f->fs.mask.ethtype); | |
1231 | fwr->frag_to_ovlan_vldm = | |
77a80e23 HS |
1232 | (FW_FILTER_WR_FRAG_V(f->fs.val.frag) | |
1233 | FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) | | |
1234 | FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) | | |
1235 | FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) | | |
1236 | FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) | | |
1237 | FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld)); | |
f2b7e78d VP |
1238 | fwr->smac_sel = 0; |
1239 | fwr->rx_chan_rx_rpl_iq = | |
77a80e23 HS |
1240 | htons(FW_FILTER_WR_RX_CHAN_V(0) | |
1241 | FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id)); | |
f2b7e78d | 1242 | fwr->maci_to_matchtypem = |
77a80e23 HS |
1243 | htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) | |
1244 | FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) | | |
1245 | FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) | | |
1246 | FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) | | |
1247 | FW_FILTER_WR_PORT_V(f->fs.val.iport) | | |
1248 | FW_FILTER_WR_PORTM_V(f->fs.mask.iport) | | |
1249 | FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) | | |
1250 | FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype)); | |
f2b7e78d VP |
1251 | fwr->ptcl = f->fs.val.proto; |
1252 | fwr->ptclm = f->fs.mask.proto; | |
1253 | fwr->ttyp = f->fs.val.tos; | |
1254 | fwr->ttypm = f->fs.mask.tos; | |
1255 | fwr->ivlan = htons(f->fs.val.ivlan); | |
1256 | fwr->ivlanm = htons(f->fs.mask.ivlan); | |
1257 | fwr->ovlan = htons(f->fs.val.ovlan); | |
1258 | fwr->ovlanm = htons(f->fs.mask.ovlan); | |
1259 | memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip)); | |
1260 | memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm)); | |
1261 | memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip)); | |
1262 | memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm)); | |
1263 | fwr->lp = htons(f->fs.val.lport); | |
1264 | fwr->lpm = htons(f->fs.mask.lport); | |
1265 | fwr->fp = htons(f->fs.val.fport); | |
1266 | fwr->fpm = htons(f->fs.mask.fport); | |
1267 | if (f->fs.newsmac) | |
1268 | memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma)); | |
1269 | ||
1270 | /* Mark the filter as "pending" and ship off the Filter Work Request. | |
1271 | * When we get the Work Request Reply we'll clear the pending status. | |
1272 | */ | |
1273 | f->pending = 1; | |
1274 | set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); | |
1275 | t4_ofld_send(adapter, skb); | |
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | /* Delete the filter at a specified index. | |
1280 | */ | |
1281 | static int del_filter_wr(struct adapter *adapter, int fidx) | |
1282 | { | |
1283 | struct filter_entry *f = &adapter->tids.ftid_tab[fidx]; | |
1284 | struct sk_buff *skb; | |
1285 | struct fw_filter_wr *fwr; | |
1286 | unsigned int len, ftid; | |
1287 | ||
1288 | len = sizeof(*fwr); | |
1289 | ftid = adapter->tids.ftid_base + fidx; | |
1290 | ||
f72f116a MH |
1291 | skb = alloc_skb(len, GFP_KERNEL); |
1292 | if (!skb) | |
1293 | return -ENOMEM; | |
1294 | ||
f2b7e78d VP |
1295 | fwr = (struct fw_filter_wr *)__skb_put(skb, len); |
1296 | t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id); | |
1297 | ||
1298 | /* Mark the filter as "pending" and ship off the Filter Work Request. | |
1299 | * When we get the Work Request Reply we'll clear the pending status. | |
1300 | */ | |
1301 | f->pending = 1; | |
1302 | t4_mgmt_tx(adapter, skb); | |
1303 | return 0; | |
1304 | } | |
1305 | ||
688848b1 AB |
1306 | static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, |
1307 | void *accel_priv, select_queue_fallback_t fallback) | |
1308 | { | |
1309 | int txq; | |
1310 | ||
1311 | #ifdef CONFIG_CHELSIO_T4_DCB | |
1312 | /* If a Data Center Bridging has been successfully negotiated on this | |
1313 | * link then we'll use the skb's priority to map it to a TX Queue. | |
1314 | * The skb's priority is determined via the VLAN Tag Priority Code | |
1315 | * Point field. | |
1316 | */ | |
1317 | if (cxgb4_dcb_enabled(dev)) { | |
1318 | u16 vlan_tci; | |
1319 | int err; | |
1320 | ||
1321 | err = vlan_get_tag(skb, &vlan_tci); | |
1322 | if (unlikely(err)) { | |
1323 | if (net_ratelimit()) | |
1324 | netdev_warn(dev, | |
1325 | "TX Packet without VLAN Tag on DCB Link\n"); | |
1326 | txq = 0; | |
1327 | } else { | |
1328 | txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; | |
84a200b3 VP |
1329 | #ifdef CONFIG_CHELSIO_T4_FCOE |
1330 | if (skb->protocol == htons(ETH_P_FCOE)) | |
1331 | txq = skb->priority & 0x7; | |
1332 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
688848b1 AB |
1333 | } |
1334 | return txq; | |
1335 | } | |
1336 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
1337 | ||
1338 | if (select_queue) { | |
1339 | txq = (skb_rx_queue_recorded(skb) | |
1340 | ? skb_get_rx_queue(skb) | |
1341 | : smp_processor_id()); | |
1342 | ||
1343 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
1344 | txq -= dev->real_num_tx_queues; | |
1345 | ||
1346 | return txq; | |
1347 | } | |
1348 | ||
1349 | return fallback(dev, skb) % dev->real_num_tx_queues; | |
1350 | } | |
1351 | ||
b8ff05a9 DM |
1352 | static int closest_timer(const struct sge *s, int time) |
1353 | { | |
1354 | int i, delta, match = 0, min_delta = INT_MAX; | |
1355 | ||
1356 | for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { | |
1357 | delta = time - s->timer_val[i]; | |
1358 | if (delta < 0) | |
1359 | delta = -delta; | |
1360 | if (delta < min_delta) { | |
1361 | min_delta = delta; | |
1362 | match = i; | |
1363 | } | |
1364 | } | |
1365 | return match; | |
1366 | } | |
1367 | ||
1368 | static int closest_thres(const struct sge *s, int thres) | |
1369 | { | |
1370 | int i, delta, match = 0, min_delta = INT_MAX; | |
1371 | ||
1372 | for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { | |
1373 | delta = thres - s->counter_val[i]; | |
1374 | if (delta < 0) | |
1375 | delta = -delta; | |
1376 | if (delta < min_delta) { | |
1377 | min_delta = delta; | |
1378 | match = i; | |
1379 | } | |
1380 | } | |
1381 | return match; | |
1382 | } | |
1383 | ||
b8ff05a9 | 1384 | /** |
812034f1 | 1385 | * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters |
b8ff05a9 DM |
1386 | * @q: the Rx queue |
1387 | * @us: the hold-off time in us, or 0 to disable timer | |
1388 | * @cnt: the hold-off packet count, or 0 to disable counter | |
1389 | * | |
1390 | * Sets an Rx queue's interrupt hold-off time and packet count. At least | |
1391 | * one of the two needs to be enabled for the queue to generate interrupts. | |
1392 | */ | |
812034f1 HS |
1393 | int cxgb4_set_rspq_intr_params(struct sge_rspq *q, |
1394 | unsigned int us, unsigned int cnt) | |
b8ff05a9 | 1395 | { |
c887ad0e HS |
1396 | struct adapter *adap = q->adap; |
1397 | ||
b8ff05a9 DM |
1398 | if ((us | cnt) == 0) |
1399 | cnt = 1; | |
1400 | ||
1401 | if (cnt) { | |
1402 | int err; | |
1403 | u32 v, new_idx; | |
1404 | ||
1405 | new_idx = closest_thres(&adap->sge, cnt); | |
1406 | if (q->desc && q->pktcnt_idx != new_idx) { | |
1407 | /* the queue has already been created, update it */ | |
5167865a HS |
1408 | v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
1409 | FW_PARAMS_PARAM_X_V( | |
1410 | FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | | |
1411 | FW_PARAMS_PARAM_YZ_V(q->cntxt_id); | |
b2612722 HS |
1412 | err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, |
1413 | &v, &new_idx); | |
b8ff05a9 DM |
1414 | if (err) |
1415 | return err; | |
1416 | } | |
1417 | q->pktcnt_idx = new_idx; | |
1418 | } | |
1419 | ||
1420 | us = us == 0 ? 6 : closest_timer(&adap->sge, us); | |
1ecc7b7a | 1421 | q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); |
b8ff05a9 DM |
1422 | return 0; |
1423 | } | |
1424 | ||
c8f44aff | 1425 | static int cxgb_set_features(struct net_device *dev, netdev_features_t features) |
87b6cf51 | 1426 | { |
2ed28baa | 1427 | const struct port_info *pi = netdev_priv(dev); |
c8f44aff | 1428 | netdev_features_t changed = dev->features ^ features; |
19ecae2c | 1429 | int err; |
19ecae2c | 1430 | |
f646968f | 1431 | if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) |
2ed28baa | 1432 | return 0; |
19ecae2c | 1433 | |
b2612722 | 1434 | err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, |
2ed28baa | 1435 | -1, -1, -1, |
f646968f | 1436 | !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); |
2ed28baa | 1437 | if (unlikely(err)) |
f646968f | 1438 | dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; |
19ecae2c | 1439 | return err; |
87b6cf51 DM |
1440 | } |
1441 | ||
91744948 | 1442 | static int setup_debugfs(struct adapter *adap) |
b8ff05a9 | 1443 | { |
b8ff05a9 DM |
1444 | if (IS_ERR_OR_NULL(adap->debugfs_root)) |
1445 | return -1; | |
1446 | ||
fd88b31a HS |
1447 | #ifdef CONFIG_DEBUG_FS |
1448 | t4_setup_debugfs(adap); | |
1449 | #endif | |
b8ff05a9 DM |
1450 | return 0; |
1451 | } | |
1452 | ||
1453 | /* | |
1454 | * upper-layer driver support | |
1455 | */ | |
1456 | ||
1457 | /* | |
1458 | * Allocate an active-open TID and set it to the supplied value. | |
1459 | */ | |
1460 | int cxgb4_alloc_atid(struct tid_info *t, void *data) | |
1461 | { | |
1462 | int atid = -1; | |
1463 | ||
1464 | spin_lock_bh(&t->atid_lock); | |
1465 | if (t->afree) { | |
1466 | union aopen_entry *p = t->afree; | |
1467 | ||
f2b7e78d | 1468 | atid = (p - t->atid_tab) + t->atid_base; |
b8ff05a9 DM |
1469 | t->afree = p->next; |
1470 | p->data = data; | |
1471 | t->atids_in_use++; | |
1472 | } | |
1473 | spin_unlock_bh(&t->atid_lock); | |
1474 | return atid; | |
1475 | } | |
1476 | EXPORT_SYMBOL(cxgb4_alloc_atid); | |
1477 | ||
1478 | /* | |
1479 | * Release an active-open TID. | |
1480 | */ | |
1481 | void cxgb4_free_atid(struct tid_info *t, unsigned int atid) | |
1482 | { | |
f2b7e78d | 1483 | union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; |
b8ff05a9 DM |
1484 | |
1485 | spin_lock_bh(&t->atid_lock); | |
1486 | p->next = t->afree; | |
1487 | t->afree = p; | |
1488 | t->atids_in_use--; | |
1489 | spin_unlock_bh(&t->atid_lock); | |
1490 | } | |
1491 | EXPORT_SYMBOL(cxgb4_free_atid); | |
1492 | ||
1493 | /* | |
1494 | * Allocate a server TID and set it to the supplied value. | |
1495 | */ | |
1496 | int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) | |
1497 | { | |
1498 | int stid; | |
1499 | ||
1500 | spin_lock_bh(&t->stid_lock); | |
1501 | if (family == PF_INET) { | |
1502 | stid = find_first_zero_bit(t->stid_bmap, t->nstids); | |
1503 | if (stid < t->nstids) | |
1504 | __set_bit(stid, t->stid_bmap); | |
1505 | else | |
1506 | stid = -1; | |
1507 | } else { | |
1508 | stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2); | |
1509 | if (stid < 0) | |
1510 | stid = -1; | |
1511 | } | |
1512 | if (stid >= 0) { | |
1513 | t->stid_tab[stid].data = data; | |
1514 | stid += t->stid_base; | |
15f63b74 KS |
1515 | /* IPv6 requires max of 520 bits or 16 cells in TCAM |
1516 | * This is equivalent to 4 TIDs. With CLIP enabled it | |
1517 | * needs 2 TIDs. | |
1518 | */ | |
1519 | if (family == PF_INET) | |
1520 | t->stids_in_use++; | |
1521 | else | |
1522 | t->stids_in_use += 4; | |
b8ff05a9 DM |
1523 | } |
1524 | spin_unlock_bh(&t->stid_lock); | |
1525 | return stid; | |
1526 | } | |
1527 | EXPORT_SYMBOL(cxgb4_alloc_stid); | |
1528 | ||
dca4faeb VP |
1529 | /* Allocate a server filter TID and set it to the supplied value. |
1530 | */ | |
1531 | int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) | |
1532 | { | |
1533 | int stid; | |
1534 | ||
1535 | spin_lock_bh(&t->stid_lock); | |
1536 | if (family == PF_INET) { | |
1537 | stid = find_next_zero_bit(t->stid_bmap, | |
1538 | t->nstids + t->nsftids, t->nstids); | |
1539 | if (stid < (t->nstids + t->nsftids)) | |
1540 | __set_bit(stid, t->stid_bmap); | |
1541 | else | |
1542 | stid = -1; | |
1543 | } else { | |
1544 | stid = -1; | |
1545 | } | |
1546 | if (stid >= 0) { | |
1547 | t->stid_tab[stid].data = data; | |
470c60c4 KS |
1548 | stid -= t->nstids; |
1549 | stid += t->sftid_base; | |
2248b293 | 1550 | t->sftids_in_use++; |
dca4faeb VP |
1551 | } |
1552 | spin_unlock_bh(&t->stid_lock); | |
1553 | return stid; | |
1554 | } | |
1555 | EXPORT_SYMBOL(cxgb4_alloc_sftid); | |
1556 | ||
1557 | /* Release a server TID. | |
b8ff05a9 DM |
1558 | */ |
1559 | void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) | |
1560 | { | |
470c60c4 KS |
1561 | /* Is it a server filter TID? */ |
1562 | if (t->nsftids && (stid >= t->sftid_base)) { | |
1563 | stid -= t->sftid_base; | |
1564 | stid += t->nstids; | |
1565 | } else { | |
1566 | stid -= t->stid_base; | |
1567 | } | |
1568 | ||
b8ff05a9 DM |
1569 | spin_lock_bh(&t->stid_lock); |
1570 | if (family == PF_INET) | |
1571 | __clear_bit(stid, t->stid_bmap); | |
1572 | else | |
1573 | bitmap_release_region(t->stid_bmap, stid, 2); | |
1574 | t->stid_tab[stid].data = NULL; | |
2248b293 HS |
1575 | if (stid < t->nstids) { |
1576 | if (family == PF_INET) | |
1577 | t->stids_in_use--; | |
1578 | else | |
1579 | t->stids_in_use -= 4; | |
1580 | } else { | |
1581 | t->sftids_in_use--; | |
1582 | } | |
b8ff05a9 DM |
1583 | spin_unlock_bh(&t->stid_lock); |
1584 | } | |
1585 | EXPORT_SYMBOL(cxgb4_free_stid); | |
1586 | ||
1587 | /* | |
1588 | * Populate a TID_RELEASE WR. Caller must properly size the skb. | |
1589 | */ | |
1590 | static void mk_tid_release(struct sk_buff *skb, unsigned int chan, | |
1591 | unsigned int tid) | |
1592 | { | |
1593 | struct cpl_tid_release *req; | |
1594 | ||
1595 | set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); | |
1596 | req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req)); | |
1597 | INIT_TP_WR(req, tid); | |
1598 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); | |
1599 | } | |
1600 | ||
1601 | /* | |
1602 | * Queue a TID release request and if necessary schedule a work queue to | |
1603 | * process it. | |
1604 | */ | |
31b9c19b | 1605 | static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, |
1606 | unsigned int tid) | |
b8ff05a9 DM |
1607 | { |
1608 | void **p = &t->tid_tab[tid]; | |
1609 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1610 | ||
1611 | spin_lock_bh(&adap->tid_release_lock); | |
1612 | *p = adap->tid_release_head; | |
1613 | /* Low 2 bits encode the Tx channel number */ | |
1614 | adap->tid_release_head = (void **)((uintptr_t)p | chan); | |
1615 | if (!adap->tid_release_task_busy) { | |
1616 | adap->tid_release_task_busy = true; | |
29aaee65 | 1617 | queue_work(adap->workq, &adap->tid_release_task); |
b8ff05a9 DM |
1618 | } |
1619 | spin_unlock_bh(&adap->tid_release_lock); | |
1620 | } | |
b8ff05a9 DM |
1621 | |
1622 | /* | |
1623 | * Process the list of pending TID release requests. | |
1624 | */ | |
1625 | static void process_tid_release_list(struct work_struct *work) | |
1626 | { | |
1627 | struct sk_buff *skb; | |
1628 | struct adapter *adap; | |
1629 | ||
1630 | adap = container_of(work, struct adapter, tid_release_task); | |
1631 | ||
1632 | spin_lock_bh(&adap->tid_release_lock); | |
1633 | while (adap->tid_release_head) { | |
1634 | void **p = adap->tid_release_head; | |
1635 | unsigned int chan = (uintptr_t)p & 3; | |
1636 | p = (void *)p - chan; | |
1637 | ||
1638 | adap->tid_release_head = *p; | |
1639 | *p = NULL; | |
1640 | spin_unlock_bh(&adap->tid_release_lock); | |
1641 | ||
1642 | while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), | |
1643 | GFP_KERNEL))) | |
1644 | schedule_timeout_uninterruptible(1); | |
1645 | ||
1646 | mk_tid_release(skb, chan, p - adap->tids.tid_tab); | |
1647 | t4_ofld_send(adap, skb); | |
1648 | spin_lock_bh(&adap->tid_release_lock); | |
1649 | } | |
1650 | adap->tid_release_task_busy = false; | |
1651 | spin_unlock_bh(&adap->tid_release_lock); | |
1652 | } | |
1653 | ||
1654 | /* | |
1655 | * Release a TID and inform HW. If we are unable to allocate the release | |
1656 | * message we defer to a work queue. | |
1657 | */ | |
1658 | void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid) | |
1659 | { | |
b8ff05a9 DM |
1660 | struct sk_buff *skb; |
1661 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1662 | ||
9a1bb9f6 HS |
1663 | WARN_ON(tid >= t->ntids); |
1664 | ||
1665 | if (t->tid_tab[tid]) { | |
1666 | t->tid_tab[tid] = NULL; | |
1667 | if (t->hash_base && (tid >= t->hash_base)) | |
1668 | atomic_dec(&t->hash_tids_in_use); | |
1669 | else | |
1670 | atomic_dec(&t->tids_in_use); | |
1671 | } | |
1672 | ||
b8ff05a9 DM |
1673 | skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); |
1674 | if (likely(skb)) { | |
b8ff05a9 DM |
1675 | mk_tid_release(skb, chan, tid); |
1676 | t4_ofld_send(adap, skb); | |
1677 | } else | |
1678 | cxgb4_queue_tid_release(t, chan, tid); | |
b8ff05a9 DM |
1679 | } |
1680 | EXPORT_SYMBOL(cxgb4_remove_tid); | |
1681 | ||
1682 | /* | |
1683 | * Allocate and initialize the TID tables. Returns 0 on success. | |
1684 | */ | |
1685 | static int tid_init(struct tid_info *t) | |
1686 | { | |
1687 | size_t size; | |
f2b7e78d | 1688 | unsigned int stid_bmap_size; |
b8ff05a9 | 1689 | unsigned int natids = t->natids; |
b6f8eaec | 1690 | struct adapter *adap = container_of(t, struct adapter, tids); |
b8ff05a9 | 1691 | |
dca4faeb | 1692 | stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); |
f2b7e78d VP |
1693 | size = t->ntids * sizeof(*t->tid_tab) + |
1694 | natids * sizeof(*t->atid_tab) + | |
b8ff05a9 | 1695 | t->nstids * sizeof(*t->stid_tab) + |
dca4faeb | 1696 | t->nsftids * sizeof(*t->stid_tab) + |
f2b7e78d | 1697 | stid_bmap_size * sizeof(long) + |
dca4faeb VP |
1698 | t->nftids * sizeof(*t->ftid_tab) + |
1699 | t->nsftids * sizeof(*t->ftid_tab); | |
f2b7e78d | 1700 | |
b8ff05a9 DM |
1701 | t->tid_tab = t4_alloc_mem(size); |
1702 | if (!t->tid_tab) | |
1703 | return -ENOMEM; | |
1704 | ||
1705 | t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; | |
1706 | t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; | |
dca4faeb | 1707 | t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; |
f2b7e78d | 1708 | t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; |
b8ff05a9 DM |
1709 | spin_lock_init(&t->stid_lock); |
1710 | spin_lock_init(&t->atid_lock); | |
1711 | ||
1712 | t->stids_in_use = 0; | |
2248b293 | 1713 | t->sftids_in_use = 0; |
b8ff05a9 DM |
1714 | t->afree = NULL; |
1715 | t->atids_in_use = 0; | |
1716 | atomic_set(&t->tids_in_use, 0); | |
9a1bb9f6 | 1717 | atomic_set(&t->hash_tids_in_use, 0); |
b8ff05a9 DM |
1718 | |
1719 | /* Setup the free list for atid_tab and clear the stid bitmap. */ | |
1720 | if (natids) { | |
1721 | while (--natids) | |
1722 | t->atid_tab[natids - 1].next = &t->atid_tab[natids]; | |
1723 | t->afree = t->atid_tab; | |
1724 | } | |
dca4faeb | 1725 | bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); |
b6f8eaec KS |
1726 | /* Reserve stid 0 for T4/T5 adapters */ |
1727 | if (!t->stid_base && | |
3ccc6cf7 | 1728 | (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)) |
b6f8eaec KS |
1729 | __set_bit(0, t->stid_bmap); |
1730 | ||
b8ff05a9 DM |
1731 | return 0; |
1732 | } | |
1733 | ||
1734 | /** | |
1735 | * cxgb4_create_server - create an IP server | |
1736 | * @dev: the device | |
1737 | * @stid: the server TID | |
1738 | * @sip: local IP address to bind server to | |
1739 | * @sport: the server's TCP port | |
1740 | * @queue: queue to direct messages from this server to | |
1741 | * | |
1742 | * Create an IP server for the given port and address. | |
1743 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1744 | */ | |
1745 | int cxgb4_create_server(const struct net_device *dev, unsigned int stid, | |
793dad94 VP |
1746 | __be32 sip, __be16 sport, __be16 vlan, |
1747 | unsigned int queue) | |
b8ff05a9 DM |
1748 | { |
1749 | unsigned int chan; | |
1750 | struct sk_buff *skb; | |
1751 | struct adapter *adap; | |
1752 | struct cpl_pass_open_req *req; | |
80f40c1f | 1753 | int ret; |
b8ff05a9 DM |
1754 | |
1755 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1756 | if (!skb) | |
1757 | return -ENOMEM; | |
1758 | ||
1759 | adap = netdev2adap(dev); | |
1760 | req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req)); | |
1761 | INIT_TP_WR(req, 0); | |
1762 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); | |
1763 | req->local_port = sport; | |
1764 | req->peer_port = htons(0); | |
1765 | req->local_ip = sip; | |
1766 | req->peer_ip = htonl(0); | |
e46dab4d | 1767 | chan = rxq_to_chan(&adap->sge, queue); |
d7990b0c | 1768 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1769 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1770 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1771 | ret = t4_mgmt_tx(adap, skb); |
1772 | return net_xmit_eval(ret); | |
b8ff05a9 DM |
1773 | } |
1774 | EXPORT_SYMBOL(cxgb4_create_server); | |
1775 | ||
80f40c1f VP |
1776 | /* cxgb4_create_server6 - create an IPv6 server |
1777 | * @dev: the device | |
1778 | * @stid: the server TID | |
1779 | * @sip: local IPv6 address to bind server to | |
1780 | * @sport: the server's TCP port | |
1781 | * @queue: queue to direct messages from this server to | |
1782 | * | |
1783 | * Create an IPv6 server for the given port and address. | |
1784 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1785 | */ | |
1786 | int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, | |
1787 | const struct in6_addr *sip, __be16 sport, | |
1788 | unsigned int queue) | |
1789 | { | |
1790 | unsigned int chan; | |
1791 | struct sk_buff *skb; | |
1792 | struct adapter *adap; | |
1793 | struct cpl_pass_open_req6 *req; | |
1794 | int ret; | |
1795 | ||
1796 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1797 | if (!skb) | |
1798 | return -ENOMEM; | |
1799 | ||
1800 | adap = netdev2adap(dev); | |
1801 | req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req)); | |
1802 | INIT_TP_WR(req, 0); | |
1803 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); | |
1804 | req->local_port = sport; | |
1805 | req->peer_port = htons(0); | |
1806 | req->local_ip_hi = *(__be64 *)(sip->s6_addr); | |
1807 | req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); | |
1808 | req->peer_ip_hi = cpu_to_be64(0); | |
1809 | req->peer_ip_lo = cpu_to_be64(0); | |
1810 | chan = rxq_to_chan(&adap->sge, queue); | |
d7990b0c | 1811 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1812 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1813 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1814 | ret = t4_mgmt_tx(adap, skb); |
1815 | return net_xmit_eval(ret); | |
1816 | } | |
1817 | EXPORT_SYMBOL(cxgb4_create_server6); | |
1818 | ||
1819 | int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, | |
1820 | unsigned int queue, bool ipv6) | |
1821 | { | |
1822 | struct sk_buff *skb; | |
1823 | struct adapter *adap; | |
1824 | struct cpl_close_listsvr_req *req; | |
1825 | int ret; | |
1826 | ||
1827 | adap = netdev2adap(dev); | |
1828 | ||
1829 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1830 | if (!skb) | |
1831 | return -ENOMEM; | |
1832 | ||
1833 | req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req)); | |
1834 | INIT_TP_WR(req, 0); | |
1835 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); | |
bdc590b9 HS |
1836 | req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : |
1837 | LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); | |
80f40c1f VP |
1838 | ret = t4_mgmt_tx(adap, skb); |
1839 | return net_xmit_eval(ret); | |
1840 | } | |
1841 | EXPORT_SYMBOL(cxgb4_remove_server); | |
1842 | ||
b8ff05a9 DM |
1843 | /** |
1844 | * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU | |
1845 | * @mtus: the HW MTU table | |
1846 | * @mtu: the target MTU | |
1847 | * @idx: index of selected entry in the MTU table | |
1848 | * | |
1849 | * Returns the index and the value in the HW MTU table that is closest to | |
1850 | * but does not exceed @mtu, unless @mtu is smaller than any value in the | |
1851 | * table, in which case that smallest available value is selected. | |
1852 | */ | |
1853 | unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, | |
1854 | unsigned int *idx) | |
1855 | { | |
1856 | unsigned int i = 0; | |
1857 | ||
1858 | while (i < NMTUS - 1 && mtus[i + 1] <= mtu) | |
1859 | ++i; | |
1860 | if (idx) | |
1861 | *idx = i; | |
1862 | return mtus[i]; | |
1863 | } | |
1864 | EXPORT_SYMBOL(cxgb4_best_mtu); | |
1865 | ||
92e7ae71 HS |
1866 | /** |
1867 | * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned | |
1868 | * @mtus: the HW MTU table | |
1869 | * @header_size: Header Size | |
1870 | * @data_size_max: maximum Data Segment Size | |
1871 | * @data_size_align: desired Data Segment Size Alignment (2^N) | |
1872 | * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) | |
1873 | * | |
1874 | * Similar to cxgb4_best_mtu() but instead of searching the Hardware | |
1875 | * MTU Table based solely on a Maximum MTU parameter, we break that | |
1876 | * parameter up into a Header Size and Maximum Data Segment Size, and | |
1877 | * provide a desired Data Segment Size Alignment. If we find an MTU in | |
1878 | * the Hardware MTU Table which will result in a Data Segment Size with | |
1879 | * the requested alignment _and_ that MTU isn't "too far" from the | |
1880 | * closest MTU, then we'll return that rather than the closest MTU. | |
1881 | */ | |
1882 | unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, | |
1883 | unsigned short header_size, | |
1884 | unsigned short data_size_max, | |
1885 | unsigned short data_size_align, | |
1886 | unsigned int *mtu_idxp) | |
1887 | { | |
1888 | unsigned short max_mtu = header_size + data_size_max; | |
1889 | unsigned short data_size_align_mask = data_size_align - 1; | |
1890 | int mtu_idx, aligned_mtu_idx; | |
1891 | ||
1892 | /* Scan the MTU Table till we find an MTU which is larger than our | |
1893 | * Maximum MTU or we reach the end of the table. Along the way, | |
1894 | * record the last MTU found, if any, which will result in a Data | |
1895 | * Segment Length matching the requested alignment. | |
1896 | */ | |
1897 | for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { | |
1898 | unsigned short data_size = mtus[mtu_idx] - header_size; | |
1899 | ||
1900 | /* If this MTU minus the Header Size would result in a | |
1901 | * Data Segment Size of the desired alignment, remember it. | |
1902 | */ | |
1903 | if ((data_size & data_size_align_mask) == 0) | |
1904 | aligned_mtu_idx = mtu_idx; | |
1905 | ||
1906 | /* If we're not at the end of the Hardware MTU Table and the | |
1907 | * next element is larger than our Maximum MTU, drop out of | |
1908 | * the loop. | |
1909 | */ | |
1910 | if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) | |
1911 | break; | |
1912 | } | |
1913 | ||
1914 | /* If we fell out of the loop because we ran to the end of the table, | |
1915 | * then we just have to use the last [largest] entry. | |
1916 | */ | |
1917 | if (mtu_idx == NMTUS) | |
1918 | mtu_idx--; | |
1919 | ||
1920 | /* If we found an MTU which resulted in the requested Data Segment | |
1921 | * Length alignment and that's "not far" from the largest MTU which is | |
1922 | * less than or equal to the maximum MTU, then use that. | |
1923 | */ | |
1924 | if (aligned_mtu_idx >= 0 && | |
1925 | mtu_idx - aligned_mtu_idx <= 1) | |
1926 | mtu_idx = aligned_mtu_idx; | |
1927 | ||
1928 | /* If the caller has passed in an MTU Index pointer, pass the | |
1929 | * MTU Index back. Return the MTU value. | |
1930 | */ | |
1931 | if (mtu_idxp) | |
1932 | *mtu_idxp = mtu_idx; | |
1933 | return mtus[mtu_idx]; | |
1934 | } | |
1935 | EXPORT_SYMBOL(cxgb4_best_aligned_mtu); | |
1936 | ||
27999805 H |
1937 | /** |
1938 | * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI | |
1939 | * @chip: chip type | |
1940 | * @viid: VI id of the given port | |
1941 | * | |
1942 | * Return the SMT index for this VI. | |
1943 | */ | |
1944 | unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid) | |
1945 | { | |
1946 | /* In T4/T5, SMT contains 256 SMAC entries organized in | |
1947 | * 128 rows of 2 entries each. | |
1948 | * In T6, SMT contains 256 SMAC entries in 256 rows. | |
1949 | * TODO: The below code needs to be updated when we add support | |
1950 | * for 256 VFs. | |
1951 | */ | |
1952 | if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) | |
1953 | return ((viid & 0x7f) << 1); | |
1954 | else | |
1955 | return (viid & 0x7f); | |
1956 | } | |
1957 | EXPORT_SYMBOL(cxgb4_tp_smt_idx); | |
1958 | ||
b8ff05a9 DM |
1959 | /** |
1960 | * cxgb4_port_chan - get the HW channel of a port | |
1961 | * @dev: the net device for the port | |
1962 | * | |
1963 | * Return the HW Tx channel of the given port. | |
1964 | */ | |
1965 | unsigned int cxgb4_port_chan(const struct net_device *dev) | |
1966 | { | |
1967 | return netdev2pinfo(dev)->tx_chan; | |
1968 | } | |
1969 | EXPORT_SYMBOL(cxgb4_port_chan); | |
1970 | ||
881806bc VP |
1971 | unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) |
1972 | { | |
1973 | struct adapter *adap = netdev2adap(dev); | |
2cc301d2 | 1974 | u32 v1, v2, lp_count, hp_count; |
881806bc | 1975 | |
f061de42 HS |
1976 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
1977 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 1978 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
1979 | lp_count = LP_COUNT_G(v1); |
1980 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 1981 | } else { |
f061de42 HS |
1982 | lp_count = LP_COUNT_T5_G(v1); |
1983 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
1984 | } |
1985 | return lpfifo ? lp_count : hp_count; | |
881806bc VP |
1986 | } |
1987 | EXPORT_SYMBOL(cxgb4_dbfifo_count); | |
1988 | ||
b8ff05a9 DM |
1989 | /** |
1990 | * cxgb4_port_viid - get the VI id of a port | |
1991 | * @dev: the net device for the port | |
1992 | * | |
1993 | * Return the VI id of the given port. | |
1994 | */ | |
1995 | unsigned int cxgb4_port_viid(const struct net_device *dev) | |
1996 | { | |
1997 | return netdev2pinfo(dev)->viid; | |
1998 | } | |
1999 | EXPORT_SYMBOL(cxgb4_port_viid); | |
2000 | ||
2001 | /** | |
2002 | * cxgb4_port_idx - get the index of a port | |
2003 | * @dev: the net device for the port | |
2004 | * | |
2005 | * Return the index of the given port. | |
2006 | */ | |
2007 | unsigned int cxgb4_port_idx(const struct net_device *dev) | |
2008 | { | |
2009 | return netdev2pinfo(dev)->port_id; | |
2010 | } | |
2011 | EXPORT_SYMBOL(cxgb4_port_idx); | |
2012 | ||
b8ff05a9 DM |
2013 | void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, |
2014 | struct tp_tcp_stats *v6) | |
2015 | { | |
2016 | struct adapter *adap = pci_get_drvdata(pdev); | |
2017 | ||
2018 | spin_lock(&adap->stats_lock); | |
2019 | t4_tp_get_tcp_stats(adap, v4, v6); | |
2020 | spin_unlock(&adap->stats_lock); | |
2021 | } | |
2022 | EXPORT_SYMBOL(cxgb4_get_tcp_stats); | |
2023 | ||
2024 | void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, | |
2025 | const unsigned int *pgsz_order) | |
2026 | { | |
2027 | struct adapter *adap = netdev2adap(dev); | |
2028 | ||
0d804338 HS |
2029 | t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); |
2030 | t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | | |
2031 | HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | | |
2032 | HPZ3_V(pgsz_order[3])); | |
b8ff05a9 DM |
2033 | } |
2034 | EXPORT_SYMBOL(cxgb4_iscsi_init); | |
2035 | ||
3069ee9b VP |
2036 | int cxgb4_flush_eq_cache(struct net_device *dev) |
2037 | { | |
2038 | struct adapter *adap = netdev2adap(dev); | |
3069ee9b | 2039 | |
5d700ecb | 2040 | return t4_sge_ctxt_flush(adap, adap->mbox); |
3069ee9b VP |
2041 | } |
2042 | EXPORT_SYMBOL(cxgb4_flush_eq_cache); | |
2043 | ||
2044 | static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) | |
2045 | { | |
f061de42 | 2046 | u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; |
3069ee9b VP |
2047 | __be64 indices; |
2048 | int ret; | |
2049 | ||
fc5ab020 HS |
2050 | spin_lock(&adap->win0_lock); |
2051 | ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, | |
2052 | sizeof(indices), (__be32 *)&indices, | |
2053 | T4_MEMORY_READ); | |
2054 | spin_unlock(&adap->win0_lock); | |
3069ee9b | 2055 | if (!ret) { |
404d9e3f VP |
2056 | *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; |
2057 | *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; | |
3069ee9b VP |
2058 | } |
2059 | return ret; | |
2060 | } | |
2061 | ||
2062 | int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, | |
2063 | u16 size) | |
2064 | { | |
2065 | struct adapter *adap = netdev2adap(dev); | |
2066 | u16 hw_pidx, hw_cidx; | |
2067 | int ret; | |
2068 | ||
2069 | ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); | |
2070 | if (ret) | |
2071 | goto out; | |
2072 | ||
2073 | if (pidx != hw_pidx) { | |
2074 | u16 delta; | |
f612b815 | 2075 | u32 val; |
3069ee9b VP |
2076 | |
2077 | if (pidx >= hw_pidx) | |
2078 | delta = pidx - hw_pidx; | |
2079 | else | |
2080 | delta = size - hw_pidx + pidx; | |
f612b815 HS |
2081 | |
2082 | if (is_t4(adap->params.chip)) | |
2083 | val = PIDX_V(delta); | |
2084 | else | |
2085 | val = PIDX_T5_V(delta); | |
3069ee9b | 2086 | wmb(); |
f612b815 HS |
2087 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
2088 | QID_V(qid) | val); | |
3069ee9b VP |
2089 | } |
2090 | out: | |
2091 | return ret; | |
2092 | } | |
2093 | EXPORT_SYMBOL(cxgb4_sync_txq_pidx); | |
2094 | ||
031cf476 HS |
2095 | int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) |
2096 | { | |
2097 | struct adapter *adap; | |
2098 | u32 offset, memtype, memaddr; | |
6559a7e8 | 2099 | u32 edc0_size, edc1_size, mc0_size, mc1_size, size; |
031cf476 HS |
2100 | u32 edc0_end, edc1_end, mc0_end, mc1_end; |
2101 | int ret; | |
2102 | ||
2103 | adap = netdev2adap(dev); | |
2104 | ||
2105 | offset = ((stag >> 8) * 32) + adap->vres.stag.start; | |
2106 | ||
2107 | /* Figure out where the offset lands in the Memory Type/Address scheme. | |
2108 | * This code assumes that the memory is laid out starting at offset 0 | |
2109 | * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 | |
2110 | * and EDC1. Some cards will have neither MC0 nor MC1, most cards have | |
2111 | * MC0, and some have both MC0 and MC1. | |
2112 | */ | |
6559a7e8 HS |
2113 | size = t4_read_reg(adap, MA_EDRAM0_BAR_A); |
2114 | edc0_size = EDRAM0_SIZE_G(size) << 20; | |
2115 | size = t4_read_reg(adap, MA_EDRAM1_BAR_A); | |
2116 | edc1_size = EDRAM1_SIZE_G(size) << 20; | |
2117 | size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); | |
2118 | mc0_size = EXT_MEM0_SIZE_G(size) << 20; | |
031cf476 HS |
2119 | |
2120 | edc0_end = edc0_size; | |
2121 | edc1_end = edc0_end + edc1_size; | |
2122 | mc0_end = edc1_end + mc0_size; | |
2123 | ||
2124 | if (offset < edc0_end) { | |
2125 | memtype = MEM_EDC0; | |
2126 | memaddr = offset; | |
2127 | } else if (offset < edc1_end) { | |
2128 | memtype = MEM_EDC1; | |
2129 | memaddr = offset - edc0_end; | |
2130 | } else { | |
2131 | if (offset < mc0_end) { | |
2132 | memtype = MEM_MC0; | |
2133 | memaddr = offset - edc1_end; | |
3ccc6cf7 | 2134 | } else if (is_t5(adap->params.chip)) { |
6559a7e8 HS |
2135 | size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); |
2136 | mc1_size = EXT_MEM1_SIZE_G(size) << 20; | |
031cf476 HS |
2137 | mc1_end = mc0_end + mc1_size; |
2138 | if (offset < mc1_end) { | |
2139 | memtype = MEM_MC1; | |
2140 | memaddr = offset - mc0_end; | |
2141 | } else { | |
2142 | /* offset beyond the end of any memory */ | |
2143 | goto err; | |
2144 | } | |
3ccc6cf7 HS |
2145 | } else { |
2146 | /* T4/T6 only has a single memory channel */ | |
2147 | goto err; | |
031cf476 HS |
2148 | } |
2149 | } | |
2150 | ||
2151 | spin_lock(&adap->win0_lock); | |
2152 | ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); | |
2153 | spin_unlock(&adap->win0_lock); | |
2154 | return ret; | |
2155 | ||
2156 | err: | |
2157 | dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", | |
2158 | stag, offset); | |
2159 | return -EINVAL; | |
2160 | } | |
2161 | EXPORT_SYMBOL(cxgb4_read_tpte); | |
2162 | ||
7730b4c7 HS |
2163 | u64 cxgb4_read_sge_timestamp(struct net_device *dev) |
2164 | { | |
2165 | u32 hi, lo; | |
2166 | struct adapter *adap; | |
2167 | ||
2168 | adap = netdev2adap(dev); | |
f612b815 HS |
2169 | lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); |
2170 | hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); | |
7730b4c7 HS |
2171 | |
2172 | return ((u64)hi << 32) | (u64)lo; | |
2173 | } | |
2174 | EXPORT_SYMBOL(cxgb4_read_sge_timestamp); | |
2175 | ||
df64e4d3 HS |
2176 | int cxgb4_bar2_sge_qregs(struct net_device *dev, |
2177 | unsigned int qid, | |
2178 | enum cxgb4_bar2_qtype qtype, | |
66cf188e | 2179 | int user, |
df64e4d3 HS |
2180 | u64 *pbar2_qoffset, |
2181 | unsigned int *pbar2_qid) | |
2182 | { | |
b2612722 | 2183 | return t4_bar2_sge_qregs(netdev2adap(dev), |
df64e4d3 HS |
2184 | qid, |
2185 | (qtype == CXGB4_BAR2_QTYPE_EGRESS | |
2186 | ? T4_BAR2_QTYPE_EGRESS | |
2187 | : T4_BAR2_QTYPE_INGRESS), | |
66cf188e | 2188 | user, |
df64e4d3 HS |
2189 | pbar2_qoffset, |
2190 | pbar2_qid); | |
2191 | } | |
2192 | EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); | |
2193 | ||
b8ff05a9 DM |
2194 | static struct pci_driver cxgb4_driver; |
2195 | ||
2196 | static void check_neigh_update(struct neighbour *neigh) | |
2197 | { | |
2198 | const struct device *parent; | |
2199 | const struct net_device *netdev = neigh->dev; | |
2200 | ||
2201 | if (netdev->priv_flags & IFF_802_1Q_VLAN) | |
2202 | netdev = vlan_dev_real_dev(netdev); | |
2203 | parent = netdev->dev.parent; | |
2204 | if (parent && parent->driver == &cxgb4_driver.driver) | |
2205 | t4_l2t_update(dev_get_drvdata(parent), neigh); | |
2206 | } | |
2207 | ||
2208 | static int netevent_cb(struct notifier_block *nb, unsigned long event, | |
2209 | void *data) | |
2210 | { | |
2211 | switch (event) { | |
2212 | case NETEVENT_NEIGH_UPDATE: | |
2213 | check_neigh_update(data); | |
2214 | break; | |
b8ff05a9 DM |
2215 | case NETEVENT_REDIRECT: |
2216 | default: | |
2217 | break; | |
2218 | } | |
2219 | return 0; | |
2220 | } | |
2221 | ||
2222 | static bool netevent_registered; | |
2223 | static struct notifier_block cxgb4_netevent_nb = { | |
2224 | .notifier_call = netevent_cb | |
2225 | }; | |
2226 | ||
3069ee9b VP |
2227 | static void drain_db_fifo(struct adapter *adap, int usecs) |
2228 | { | |
2cc301d2 | 2229 | u32 v1, v2, lp_count, hp_count; |
3069ee9b VP |
2230 | |
2231 | do { | |
f061de42 HS |
2232 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
2233 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 2234 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
2235 | lp_count = LP_COUNT_G(v1); |
2236 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 2237 | } else { |
f061de42 HS |
2238 | lp_count = LP_COUNT_T5_G(v1); |
2239 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
2240 | } |
2241 | ||
2242 | if (lp_count == 0 && hp_count == 0) | |
2243 | break; | |
3069ee9b VP |
2244 | set_current_state(TASK_UNINTERRUPTIBLE); |
2245 | schedule_timeout(usecs_to_jiffies(usecs)); | |
3069ee9b VP |
2246 | } while (1); |
2247 | } | |
2248 | ||
2249 | static void disable_txq_db(struct sge_txq *q) | |
2250 | { | |
05eb2389 SW |
2251 | unsigned long flags; |
2252 | ||
2253 | spin_lock_irqsave(&q->db_lock, flags); | |
3069ee9b | 2254 | q->db_disabled = 1; |
05eb2389 | 2255 | spin_unlock_irqrestore(&q->db_lock, flags); |
3069ee9b VP |
2256 | } |
2257 | ||
05eb2389 | 2258 | static void enable_txq_db(struct adapter *adap, struct sge_txq *q) |
3069ee9b VP |
2259 | { |
2260 | spin_lock_irq(&q->db_lock); | |
05eb2389 SW |
2261 | if (q->db_pidx_inc) { |
2262 | /* Make sure that all writes to the TX descriptors | |
2263 | * are committed before we tell HW about them. | |
2264 | */ | |
2265 | wmb(); | |
f612b815 HS |
2266 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
2267 | QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); | |
05eb2389 SW |
2268 | q->db_pidx_inc = 0; |
2269 | } | |
3069ee9b VP |
2270 | q->db_disabled = 0; |
2271 | spin_unlock_irq(&q->db_lock); | |
2272 | } | |
2273 | ||
2274 | static void disable_dbs(struct adapter *adap) | |
2275 | { | |
2276 | int i; | |
2277 | ||
2278 | for_each_ethrxq(&adap->sge, i) | |
2279 | disable_txq_db(&adap->sge.ethtxq[i].q); | |
2280 | for_each_ofldrxq(&adap->sge, i) | |
2281 | disable_txq_db(&adap->sge.ofldtxq[i].q); | |
2282 | for_each_port(adap, i) | |
2283 | disable_txq_db(&adap->sge.ctrlq[i].q); | |
2284 | } | |
2285 | ||
2286 | static void enable_dbs(struct adapter *adap) | |
2287 | { | |
2288 | int i; | |
2289 | ||
2290 | for_each_ethrxq(&adap->sge, i) | |
05eb2389 | 2291 | enable_txq_db(adap, &adap->sge.ethtxq[i].q); |
3069ee9b | 2292 | for_each_ofldrxq(&adap->sge, i) |
05eb2389 | 2293 | enable_txq_db(adap, &adap->sge.ofldtxq[i].q); |
3069ee9b | 2294 | for_each_port(adap, i) |
05eb2389 SW |
2295 | enable_txq_db(adap, &adap->sge.ctrlq[i].q); |
2296 | } | |
2297 | ||
2298 | static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) | |
2299 | { | |
2300 | if (adap->uld_handle[CXGB4_ULD_RDMA]) | |
2301 | ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA], | |
2302 | cmd); | |
2303 | } | |
2304 | ||
2305 | static void process_db_full(struct work_struct *work) | |
2306 | { | |
2307 | struct adapter *adap; | |
2308 | ||
2309 | adap = container_of(work, struct adapter, db_full_task); | |
2310 | ||
2311 | drain_db_fifo(adap, dbfifo_drain_delay); | |
2312 | enable_dbs(adap); | |
2313 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); | |
3ccc6cf7 HS |
2314 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
2315 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
2316 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, | |
2317 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); | |
2318 | else | |
2319 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
2320 | DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); | |
3069ee9b VP |
2321 | } |
2322 | ||
2323 | static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) | |
2324 | { | |
2325 | u16 hw_pidx, hw_cidx; | |
2326 | int ret; | |
2327 | ||
05eb2389 | 2328 | spin_lock_irq(&q->db_lock); |
3069ee9b VP |
2329 | ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); |
2330 | if (ret) | |
2331 | goto out; | |
2332 | if (q->db_pidx != hw_pidx) { | |
2333 | u16 delta; | |
f612b815 | 2334 | u32 val; |
3069ee9b VP |
2335 | |
2336 | if (q->db_pidx >= hw_pidx) | |
2337 | delta = q->db_pidx - hw_pidx; | |
2338 | else | |
2339 | delta = q->size - hw_pidx + q->db_pidx; | |
f612b815 HS |
2340 | |
2341 | if (is_t4(adap->params.chip)) | |
2342 | val = PIDX_V(delta); | |
2343 | else | |
2344 | val = PIDX_T5_V(delta); | |
3069ee9b | 2345 | wmb(); |
f612b815 HS |
2346 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
2347 | QID_V(q->cntxt_id) | val); | |
3069ee9b VP |
2348 | } |
2349 | out: | |
2350 | q->db_disabled = 0; | |
05eb2389 SW |
2351 | q->db_pidx_inc = 0; |
2352 | spin_unlock_irq(&q->db_lock); | |
3069ee9b VP |
2353 | if (ret) |
2354 | CH_WARN(adap, "DB drop recovery failed.\n"); | |
2355 | } | |
2356 | static void recover_all_queues(struct adapter *adap) | |
2357 | { | |
2358 | int i; | |
2359 | ||
2360 | for_each_ethrxq(&adap->sge, i) | |
2361 | sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); | |
2362 | for_each_ofldrxq(&adap->sge, i) | |
2363 | sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q); | |
2364 | for_each_port(adap, i) | |
2365 | sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); | |
2366 | } | |
2367 | ||
881806bc VP |
2368 | static void process_db_drop(struct work_struct *work) |
2369 | { | |
2370 | struct adapter *adap; | |
881806bc | 2371 | |
3069ee9b | 2372 | adap = container_of(work, struct adapter, db_drop_task); |
881806bc | 2373 | |
d14807dd | 2374 | if (is_t4(adap->params.chip)) { |
05eb2389 | 2375 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2376 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); |
05eb2389 | 2377 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2378 | recover_all_queues(adap); |
05eb2389 | 2379 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2380 | enable_dbs(adap); |
05eb2389 | 2381 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); |
3ccc6cf7 | 2382 | } else if (is_t5(adap->params.chip)) { |
2cc301d2 SR |
2383 | u32 dropped_db = t4_read_reg(adap, 0x010ac); |
2384 | u16 qid = (dropped_db >> 15) & 0x1ffff; | |
2385 | u16 pidx_inc = dropped_db & 0x1fff; | |
df64e4d3 HS |
2386 | u64 bar2_qoffset; |
2387 | unsigned int bar2_qid; | |
2388 | int ret; | |
2cc301d2 | 2389 | |
b2612722 | 2390 | ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, |
e0456717 | 2391 | 0, &bar2_qoffset, &bar2_qid); |
df64e4d3 HS |
2392 | if (ret) |
2393 | dev_err(adap->pdev_dev, "doorbell drop recovery: " | |
2394 | "qid=%d, pidx_inc=%d\n", qid, pidx_inc); | |
2395 | else | |
f612b815 | 2396 | writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), |
df64e4d3 | 2397 | adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); |
2cc301d2 SR |
2398 | |
2399 | /* Re-enable BAR2 WC */ | |
2400 | t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); | |
2401 | } | |
2402 | ||
3ccc6cf7 HS |
2403 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
2404 | t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); | |
881806bc VP |
2405 | } |
2406 | ||
2407 | void t4_db_full(struct adapter *adap) | |
2408 | { | |
d14807dd | 2409 | if (is_t4(adap->params.chip)) { |
05eb2389 SW |
2410 | disable_dbs(adap); |
2411 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
f612b815 HS |
2412 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, |
2413 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); | |
29aaee65 | 2414 | queue_work(adap->workq, &adap->db_full_task); |
2cc301d2 | 2415 | } |
881806bc VP |
2416 | } |
2417 | ||
2418 | void t4_db_dropped(struct adapter *adap) | |
2419 | { | |
05eb2389 SW |
2420 | if (is_t4(adap->params.chip)) { |
2421 | disable_dbs(adap); | |
2422 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
2423 | } | |
29aaee65 | 2424 | queue_work(adap->workq, &adap->db_drop_task); |
881806bc VP |
2425 | } |
2426 | ||
b8ff05a9 DM |
2427 | static void uld_attach(struct adapter *adap, unsigned int uld) |
2428 | { | |
2429 | void *handle; | |
2430 | struct cxgb4_lld_info lli; | |
dca4faeb | 2431 | unsigned short i; |
b8ff05a9 DM |
2432 | |
2433 | lli.pdev = adap->pdev; | |
b2612722 | 2434 | lli.pf = adap->pf; |
b8ff05a9 DM |
2435 | lli.l2t = adap->l2t; |
2436 | lli.tids = &adap->tids; | |
2437 | lli.ports = adap->port; | |
2438 | lli.vr = &adap->vres; | |
2439 | lli.mtus = adap->params.mtus; | |
2440 | if (uld == CXGB4_ULD_RDMA) { | |
2441 | lli.rxq_ids = adap->sge.rdma_rxq; | |
cf38be6d | 2442 | lli.ciq_ids = adap->sge.rdma_ciq; |
b8ff05a9 | 2443 | lli.nrxq = adap->sge.rdmaqs; |
cf38be6d | 2444 | lli.nciq = adap->sge.rdmaciqs; |
b8ff05a9 DM |
2445 | } else if (uld == CXGB4_ULD_ISCSI) { |
2446 | lli.rxq_ids = adap->sge.ofld_rxq; | |
2447 | lli.nrxq = adap->sge.ofldqsets; | |
2448 | } | |
2449 | lli.ntxq = adap->sge.ofldqsets; | |
2450 | lli.nchan = adap->params.nports; | |
2451 | lli.nports = adap->params.nports; | |
2452 | lli.wr_cred = adap->params.ofldq_wr_cred; | |
d14807dd | 2453 | lli.adapter_type = adap->params.chip; |
837e4a42 | 2454 | lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A)); |
7730b4c7 | 2455 | lli.cclk_ps = 1000000000 / adap->params.vpd.cclk; |
df64e4d3 HS |
2456 | lli.udb_density = 1 << adap->params.sge.eq_qpp; |
2457 | lli.ucq_density = 1 << adap->params.sge.iq_qpp; | |
dcf7b6f5 | 2458 | lli.filt_mode = adap->params.tp.vlan_pri_map; |
dca4faeb VP |
2459 | /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */ |
2460 | for (i = 0; i < NCHAN; i++) | |
2461 | lli.tx_modq[i] = i; | |
f612b815 HS |
2462 | lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A); |
2463 | lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A); | |
b8ff05a9 | 2464 | lli.fw_vers = adap->params.fw_vers; |
3069ee9b | 2465 | lli.dbfifo_int_thresh = dbfifo_int_thresh; |
04e10e21 HS |
2466 | lli.sge_ingpadboundary = adap->sge.fl_align; |
2467 | lli.sge_egrstatuspagesize = adap->sge.stat_len; | |
dca4faeb VP |
2468 | lli.sge_pktshift = adap->sge.pktshift; |
2469 | lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN; | |
4c2c5763 HS |
2470 | lli.max_ordird_qp = adap->params.max_ordird_qp; |
2471 | lli.max_ird_adapter = adap->params.max_ird_adapter; | |
1ac0f095 | 2472 | lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl; |
982b81eb | 2473 | lli.nodeid = dev_to_node(adap->pdev_dev); |
b8ff05a9 DM |
2474 | |
2475 | handle = ulds[uld].add(&lli); | |
2476 | if (IS_ERR(handle)) { | |
2477 | dev_warn(adap->pdev_dev, | |
2478 | "could not attach to the %s driver, error %ld\n", | |
2479 | uld_str[uld], PTR_ERR(handle)); | |
2480 | return; | |
2481 | } | |
2482 | ||
2483 | adap->uld_handle[uld] = handle; | |
2484 | ||
2485 | if (!netevent_registered) { | |
2486 | register_netevent_notifier(&cxgb4_netevent_nb); | |
2487 | netevent_registered = true; | |
2488 | } | |
e29f5dbc DM |
2489 | |
2490 | if (adap->flags & FULL_INIT_DONE) | |
2491 | ulds[uld].state_change(handle, CXGB4_STATE_UP); | |
b8ff05a9 DM |
2492 | } |
2493 | ||
2494 | static void attach_ulds(struct adapter *adap) | |
2495 | { | |
2496 | unsigned int i; | |
2497 | ||
01bcca68 VP |
2498 | spin_lock(&adap_rcu_lock); |
2499 | list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list); | |
2500 | spin_unlock(&adap_rcu_lock); | |
2501 | ||
b8ff05a9 DM |
2502 | mutex_lock(&uld_mutex); |
2503 | list_add_tail(&adap->list_node, &adapter_list); | |
2504 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
2505 | if (ulds[i].add) | |
2506 | uld_attach(adap, i); | |
2507 | mutex_unlock(&uld_mutex); | |
2508 | } | |
2509 | ||
2510 | static void detach_ulds(struct adapter *adap) | |
2511 | { | |
2512 | unsigned int i; | |
2513 | ||
2514 | mutex_lock(&uld_mutex); | |
2515 | list_del(&adap->list_node); | |
2516 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
2517 | if (adap->uld_handle[i]) { | |
2518 | ulds[i].state_change(adap->uld_handle[i], | |
2519 | CXGB4_STATE_DETACH); | |
2520 | adap->uld_handle[i] = NULL; | |
2521 | } | |
2522 | if (netevent_registered && list_empty(&adapter_list)) { | |
2523 | unregister_netevent_notifier(&cxgb4_netevent_nb); | |
2524 | netevent_registered = false; | |
2525 | } | |
2526 | mutex_unlock(&uld_mutex); | |
01bcca68 VP |
2527 | |
2528 | spin_lock(&adap_rcu_lock); | |
2529 | list_del_rcu(&adap->rcu_node); | |
2530 | spin_unlock(&adap_rcu_lock); | |
b8ff05a9 DM |
2531 | } |
2532 | ||
2533 | static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) | |
2534 | { | |
2535 | unsigned int i; | |
2536 | ||
2537 | mutex_lock(&uld_mutex); | |
2538 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
2539 | if (adap->uld_handle[i]) | |
2540 | ulds[i].state_change(adap->uld_handle[i], new_state); | |
2541 | mutex_unlock(&uld_mutex); | |
2542 | } | |
2543 | ||
2544 | /** | |
2545 | * cxgb4_register_uld - register an upper-layer driver | |
2546 | * @type: the ULD type | |
2547 | * @p: the ULD methods | |
2548 | * | |
2549 | * Registers an upper-layer driver with this driver and notifies the ULD | |
2550 | * about any presently available devices that support its type. Returns | |
2551 | * %-EBUSY if a ULD of the same type is already registered. | |
2552 | */ | |
2553 | int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p) | |
2554 | { | |
2555 | int ret = 0; | |
2556 | struct adapter *adap; | |
2557 | ||
2558 | if (type >= CXGB4_ULD_MAX) | |
2559 | return -EINVAL; | |
2560 | mutex_lock(&uld_mutex); | |
2561 | if (ulds[type].add) { | |
2562 | ret = -EBUSY; | |
2563 | goto out; | |
2564 | } | |
2565 | ulds[type] = *p; | |
2566 | list_for_each_entry(adap, &adapter_list, list_node) | |
2567 | uld_attach(adap, type); | |
2568 | out: mutex_unlock(&uld_mutex); | |
2569 | return ret; | |
2570 | } | |
2571 | EXPORT_SYMBOL(cxgb4_register_uld); | |
2572 | ||
2573 | /** | |
2574 | * cxgb4_unregister_uld - unregister an upper-layer driver | |
2575 | * @type: the ULD type | |
2576 | * | |
2577 | * Unregisters an existing upper-layer driver. | |
2578 | */ | |
2579 | int cxgb4_unregister_uld(enum cxgb4_uld type) | |
2580 | { | |
2581 | struct adapter *adap; | |
2582 | ||
2583 | if (type >= CXGB4_ULD_MAX) | |
2584 | return -EINVAL; | |
2585 | mutex_lock(&uld_mutex); | |
2586 | list_for_each_entry(adap, &adapter_list, list_node) | |
2587 | adap->uld_handle[type] = NULL; | |
2588 | ulds[type].add = NULL; | |
2589 | mutex_unlock(&uld_mutex); | |
2590 | return 0; | |
2591 | } | |
2592 | EXPORT_SYMBOL(cxgb4_unregister_uld); | |
2593 | ||
1bb60376 | 2594 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
2595 | static int cxgb4_inet6addr_handler(struct notifier_block *this, |
2596 | unsigned long event, void *data) | |
01bcca68 | 2597 | { |
b5a02f50 AB |
2598 | struct inet6_ifaddr *ifa = data; |
2599 | struct net_device *event_dev = ifa->idev->dev; | |
2600 | const struct device *parent = NULL; | |
2601 | #if IS_ENABLED(CONFIG_BONDING) | |
01bcca68 | 2602 | struct adapter *adap; |
b5a02f50 AB |
2603 | #endif |
2604 | if (event_dev->priv_flags & IFF_802_1Q_VLAN) | |
2605 | event_dev = vlan_dev_real_dev(event_dev); | |
2606 | #if IS_ENABLED(CONFIG_BONDING) | |
2607 | if (event_dev->flags & IFF_MASTER) { | |
2608 | list_for_each_entry(adap, &adapter_list, list_node) { | |
2609 | switch (event) { | |
2610 | case NETDEV_UP: | |
2611 | cxgb4_clip_get(adap->port[0], | |
2612 | (const u32 *)ifa, 1); | |
2613 | break; | |
2614 | case NETDEV_DOWN: | |
2615 | cxgb4_clip_release(adap->port[0], | |
2616 | (const u32 *)ifa, 1); | |
2617 | break; | |
2618 | default: | |
2619 | break; | |
2620 | } | |
2621 | } | |
2622 | return NOTIFY_OK; | |
2623 | } | |
2624 | #endif | |
01bcca68 | 2625 | |
b5a02f50 AB |
2626 | if (event_dev) |
2627 | parent = event_dev->dev.parent; | |
01bcca68 | 2628 | |
b5a02f50 | 2629 | if (parent && parent->driver == &cxgb4_driver.driver) { |
01bcca68 VP |
2630 | switch (event) { |
2631 | case NETDEV_UP: | |
b5a02f50 | 2632 | cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2633 | break; |
2634 | case NETDEV_DOWN: | |
b5a02f50 | 2635 | cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2636 | break; |
2637 | default: | |
2638 | break; | |
2639 | } | |
2640 | } | |
b5a02f50 | 2641 | return NOTIFY_OK; |
01bcca68 VP |
2642 | } |
2643 | ||
b5a02f50 | 2644 | static bool inet6addr_registered; |
01bcca68 VP |
2645 | static struct notifier_block cxgb4_inet6addr_notifier = { |
2646 | .notifier_call = cxgb4_inet6addr_handler | |
2647 | }; | |
2648 | ||
01bcca68 VP |
2649 | static void update_clip(const struct adapter *adap) |
2650 | { | |
2651 | int i; | |
2652 | struct net_device *dev; | |
2653 | int ret; | |
2654 | ||
2655 | rcu_read_lock(); | |
2656 | ||
2657 | for (i = 0; i < MAX_NPORTS; i++) { | |
2658 | dev = adap->port[i]; | |
2659 | ret = 0; | |
2660 | ||
2661 | if (dev) | |
b5a02f50 | 2662 | ret = cxgb4_update_root_dev_clip(dev); |
01bcca68 VP |
2663 | |
2664 | if (ret < 0) | |
2665 | break; | |
2666 | } | |
2667 | rcu_read_unlock(); | |
2668 | } | |
1bb60376 | 2669 | #endif /* IS_ENABLED(CONFIG_IPV6) */ |
01bcca68 | 2670 | |
b8ff05a9 DM |
2671 | /** |
2672 | * cxgb_up - enable the adapter | |
2673 | * @adap: adapter being enabled | |
2674 | * | |
2675 | * Called when the first port is enabled, this function performs the | |
2676 | * actions necessary to make an adapter operational, such as completing | |
2677 | * the initialization of HW modules, and enabling interrupts. | |
2678 | * | |
2679 | * Must be called with the rtnl lock held. | |
2680 | */ | |
2681 | static int cxgb_up(struct adapter *adap) | |
2682 | { | |
aaefae9b | 2683 | int err; |
b8ff05a9 | 2684 | |
aaefae9b DM |
2685 | err = setup_sge_queues(adap); |
2686 | if (err) | |
2687 | goto out; | |
2688 | err = setup_rss(adap); | |
2689 | if (err) | |
2690 | goto freeq; | |
b8ff05a9 DM |
2691 | |
2692 | if (adap->flags & USING_MSIX) { | |
aaefae9b | 2693 | name_msix_vecs(adap); |
b8ff05a9 DM |
2694 | err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, |
2695 | adap->msix_info[0].desc, adap); | |
2696 | if (err) | |
2697 | goto irq_err; | |
2698 | ||
2699 | err = request_msix_queue_irqs(adap); | |
2700 | if (err) { | |
2701 | free_irq(adap->msix_info[0].vec, adap); | |
2702 | goto irq_err; | |
2703 | } | |
2704 | } else { | |
2705 | err = request_irq(adap->pdev->irq, t4_intr_handler(adap), | |
2706 | (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, | |
b1a3c2b6 | 2707 | adap->port[0]->name, adap); |
b8ff05a9 DM |
2708 | if (err) |
2709 | goto irq_err; | |
2710 | } | |
2711 | enable_rx(adap); | |
2712 | t4_sge_start(adap); | |
2713 | t4_intr_enable(adap); | |
aaefae9b | 2714 | adap->flags |= FULL_INIT_DONE; |
b8ff05a9 | 2715 | notify_ulds(adap, CXGB4_STATE_UP); |
1bb60376 | 2716 | #if IS_ENABLED(CONFIG_IPV6) |
01bcca68 | 2717 | update_clip(adap); |
1bb60376 | 2718 | #endif |
b8ff05a9 DM |
2719 | out: |
2720 | return err; | |
2721 | irq_err: | |
2722 | dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); | |
aaefae9b DM |
2723 | freeq: |
2724 | t4_free_sge_resources(adap); | |
b8ff05a9 DM |
2725 | goto out; |
2726 | } | |
2727 | ||
2728 | static void cxgb_down(struct adapter *adapter) | |
2729 | { | |
b8ff05a9 | 2730 | cancel_work_sync(&adapter->tid_release_task); |
881806bc VP |
2731 | cancel_work_sync(&adapter->db_full_task); |
2732 | cancel_work_sync(&adapter->db_drop_task); | |
b8ff05a9 | 2733 | adapter->tid_release_task_busy = false; |
204dc3c0 | 2734 | adapter->tid_release_head = NULL; |
b8ff05a9 | 2735 | |
aaefae9b DM |
2736 | t4_sge_stop(adapter); |
2737 | t4_free_sge_resources(adapter); | |
2738 | adapter->flags &= ~FULL_INIT_DONE; | |
b8ff05a9 DM |
2739 | } |
2740 | ||
2741 | /* | |
2742 | * net_device operations | |
2743 | */ | |
2744 | static int cxgb_open(struct net_device *dev) | |
2745 | { | |
2746 | int err; | |
2747 | struct port_info *pi = netdev_priv(dev); | |
2748 | struct adapter *adapter = pi->adapter; | |
2749 | ||
6a3c869a DM |
2750 | netif_carrier_off(dev); |
2751 | ||
aaefae9b DM |
2752 | if (!(adapter->flags & FULL_INIT_DONE)) { |
2753 | err = cxgb_up(adapter); | |
2754 | if (err < 0) | |
2755 | return err; | |
2756 | } | |
b8ff05a9 | 2757 | |
f68707b8 DM |
2758 | err = link_start(dev); |
2759 | if (!err) | |
2760 | netif_tx_start_all_queues(dev); | |
2761 | return err; | |
b8ff05a9 DM |
2762 | } |
2763 | ||
2764 | static int cxgb_close(struct net_device *dev) | |
2765 | { | |
b8ff05a9 DM |
2766 | struct port_info *pi = netdev_priv(dev); |
2767 | struct adapter *adapter = pi->adapter; | |
2768 | ||
2769 | netif_tx_stop_all_queues(dev); | |
2770 | netif_carrier_off(dev); | |
b2612722 | 2771 | return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false); |
b8ff05a9 DM |
2772 | } |
2773 | ||
f2b7e78d VP |
2774 | /* Return an error number if the indicated filter isn't writable ... |
2775 | */ | |
2776 | static int writable_filter(struct filter_entry *f) | |
2777 | { | |
2778 | if (f->locked) | |
2779 | return -EPERM; | |
2780 | if (f->pending) | |
2781 | return -EBUSY; | |
2782 | ||
2783 | return 0; | |
2784 | } | |
2785 | ||
2786 | /* Delete the filter at the specified index (if valid). The checks for all | |
2787 | * the common problems with doing this like the filter being locked, currently | |
2788 | * pending in another operation, etc. | |
2789 | */ | |
2790 | static int delete_filter(struct adapter *adapter, unsigned int fidx) | |
2791 | { | |
2792 | struct filter_entry *f; | |
2793 | int ret; | |
2794 | ||
dca4faeb | 2795 | if (fidx >= adapter->tids.nftids + adapter->tids.nsftids) |
f2b7e78d VP |
2796 | return -EINVAL; |
2797 | ||
2798 | f = &adapter->tids.ftid_tab[fidx]; | |
2799 | ret = writable_filter(f); | |
2800 | if (ret) | |
2801 | return ret; | |
2802 | if (f->valid) | |
2803 | return del_filter_wr(adapter, fidx); | |
2804 | ||
2805 | return 0; | |
2806 | } | |
2807 | ||
dca4faeb | 2808 | int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, |
793dad94 VP |
2809 | __be32 sip, __be16 sport, __be16 vlan, |
2810 | unsigned int queue, unsigned char port, unsigned char mask) | |
dca4faeb VP |
2811 | { |
2812 | int ret; | |
2813 | struct filter_entry *f; | |
2814 | struct adapter *adap; | |
2815 | int i; | |
2816 | u8 *val; | |
2817 | ||
2818 | adap = netdev2adap(dev); | |
2819 | ||
1cab775c | 2820 | /* Adjust stid to correct filter index */ |
470c60c4 | 2821 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2822 | stid += adap->tids.nftids; |
2823 | ||
dca4faeb VP |
2824 | /* Check to make sure the filter requested is writable ... |
2825 | */ | |
2826 | f = &adap->tids.ftid_tab[stid]; | |
2827 | ret = writable_filter(f); | |
2828 | if (ret) | |
2829 | return ret; | |
2830 | ||
2831 | /* Clear out any old resources being used by the filter before | |
2832 | * we start constructing the new filter. | |
2833 | */ | |
2834 | if (f->valid) | |
2835 | clear_filter(adap, f); | |
2836 | ||
2837 | /* Clear out filter specifications */ | |
2838 | memset(&f->fs, 0, sizeof(struct ch_filter_specification)); | |
2839 | f->fs.val.lport = cpu_to_be16(sport); | |
2840 | f->fs.mask.lport = ~0; | |
2841 | val = (u8 *)&sip; | |
793dad94 | 2842 | if ((val[0] | val[1] | val[2] | val[3]) != 0) { |
dca4faeb VP |
2843 | for (i = 0; i < 4; i++) { |
2844 | f->fs.val.lip[i] = val[i]; | |
2845 | f->fs.mask.lip[i] = ~0; | |
2846 | } | |
0d804338 | 2847 | if (adap->params.tp.vlan_pri_map & PORT_F) { |
793dad94 VP |
2848 | f->fs.val.iport = port; |
2849 | f->fs.mask.iport = mask; | |
2850 | } | |
2851 | } | |
dca4faeb | 2852 | |
0d804338 | 2853 | if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { |
7c89e555 KS |
2854 | f->fs.val.proto = IPPROTO_TCP; |
2855 | f->fs.mask.proto = ~0; | |
2856 | } | |
2857 | ||
dca4faeb VP |
2858 | f->fs.dirsteer = 1; |
2859 | f->fs.iq = queue; | |
2860 | /* Mark filter as locked */ | |
2861 | f->locked = 1; | |
2862 | f->fs.rpttid = 1; | |
2863 | ||
2864 | ret = set_filter_wr(adap, stid); | |
2865 | if (ret) { | |
2866 | clear_filter(adap, f); | |
2867 | return ret; | |
2868 | } | |
2869 | ||
2870 | return 0; | |
2871 | } | |
2872 | EXPORT_SYMBOL(cxgb4_create_server_filter); | |
2873 | ||
2874 | int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, | |
2875 | unsigned int queue, bool ipv6) | |
2876 | { | |
2877 | int ret; | |
2878 | struct filter_entry *f; | |
2879 | struct adapter *adap; | |
2880 | ||
2881 | adap = netdev2adap(dev); | |
1cab775c VP |
2882 | |
2883 | /* Adjust stid to correct filter index */ | |
470c60c4 | 2884 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2885 | stid += adap->tids.nftids; |
2886 | ||
dca4faeb VP |
2887 | f = &adap->tids.ftid_tab[stid]; |
2888 | /* Unlock the filter */ | |
2889 | f->locked = 0; | |
2890 | ||
2891 | ret = delete_filter(adap, stid); | |
2892 | if (ret) | |
2893 | return ret; | |
2894 | ||
2895 | return 0; | |
2896 | } | |
2897 | EXPORT_SYMBOL(cxgb4_remove_server_filter); | |
2898 | ||
f5152c90 DM |
2899 | static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev, |
2900 | struct rtnl_link_stats64 *ns) | |
b8ff05a9 DM |
2901 | { |
2902 | struct port_stats stats; | |
2903 | struct port_info *p = netdev_priv(dev); | |
2904 | struct adapter *adapter = p->adapter; | |
b8ff05a9 | 2905 | |
9fe6cb58 GS |
2906 | /* Block retrieving statistics during EEH error |
2907 | * recovery. Otherwise, the recovery might fail | |
2908 | * and the PCI device will be removed permanently | |
2909 | */ | |
b8ff05a9 | 2910 | spin_lock(&adapter->stats_lock); |
9fe6cb58 GS |
2911 | if (!netif_device_present(dev)) { |
2912 | spin_unlock(&adapter->stats_lock); | |
2913 | return ns; | |
2914 | } | |
a4cfd929 HS |
2915 | t4_get_port_stats_offset(adapter, p->tx_chan, &stats, |
2916 | &p->stats_base); | |
b8ff05a9 DM |
2917 | spin_unlock(&adapter->stats_lock); |
2918 | ||
2919 | ns->tx_bytes = stats.tx_octets; | |
2920 | ns->tx_packets = stats.tx_frames; | |
2921 | ns->rx_bytes = stats.rx_octets; | |
2922 | ns->rx_packets = stats.rx_frames; | |
2923 | ns->multicast = stats.rx_mcast_frames; | |
2924 | ||
2925 | /* detailed rx_errors */ | |
2926 | ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + | |
2927 | stats.rx_runt; | |
2928 | ns->rx_over_errors = 0; | |
2929 | ns->rx_crc_errors = stats.rx_fcs_err; | |
2930 | ns->rx_frame_errors = stats.rx_symbol_err; | |
2931 | ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 + | |
2932 | stats.rx_ovflow2 + stats.rx_ovflow3 + | |
2933 | stats.rx_trunc0 + stats.rx_trunc1 + | |
2934 | stats.rx_trunc2 + stats.rx_trunc3; | |
2935 | ns->rx_missed_errors = 0; | |
2936 | ||
2937 | /* detailed tx_errors */ | |
2938 | ns->tx_aborted_errors = 0; | |
2939 | ns->tx_carrier_errors = 0; | |
2940 | ns->tx_fifo_errors = 0; | |
2941 | ns->tx_heartbeat_errors = 0; | |
2942 | ns->tx_window_errors = 0; | |
2943 | ||
2944 | ns->tx_errors = stats.tx_error_frames; | |
2945 | ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + | |
2946 | ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; | |
2947 | return ns; | |
2948 | } | |
2949 | ||
2950 | static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
2951 | { | |
060e0c75 | 2952 | unsigned int mbox; |
b8ff05a9 DM |
2953 | int ret = 0, prtad, devad; |
2954 | struct port_info *pi = netdev_priv(dev); | |
2955 | struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; | |
2956 | ||
2957 | switch (cmd) { | |
2958 | case SIOCGMIIPHY: | |
2959 | if (pi->mdio_addr < 0) | |
2960 | return -EOPNOTSUPP; | |
2961 | data->phy_id = pi->mdio_addr; | |
2962 | break; | |
2963 | case SIOCGMIIREG: | |
2964 | case SIOCSMIIREG: | |
2965 | if (mdio_phy_id_is_c45(data->phy_id)) { | |
2966 | prtad = mdio_phy_id_prtad(data->phy_id); | |
2967 | devad = mdio_phy_id_devad(data->phy_id); | |
2968 | } else if (data->phy_id < 32) { | |
2969 | prtad = data->phy_id; | |
2970 | devad = 0; | |
2971 | data->reg_num &= 0x1f; | |
2972 | } else | |
2973 | return -EINVAL; | |
2974 | ||
b2612722 | 2975 | mbox = pi->adapter->pf; |
b8ff05a9 | 2976 | if (cmd == SIOCGMIIREG) |
060e0c75 | 2977 | ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
2978 | data->reg_num, &data->val_out); |
2979 | else | |
060e0c75 | 2980 | ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
2981 | data->reg_num, data->val_in); |
2982 | break; | |
5e2a5ebc HS |
2983 | case SIOCGHWTSTAMP: |
2984 | return copy_to_user(req->ifr_data, &pi->tstamp_config, | |
2985 | sizeof(pi->tstamp_config)) ? | |
2986 | -EFAULT : 0; | |
2987 | case SIOCSHWTSTAMP: | |
2988 | if (copy_from_user(&pi->tstamp_config, req->ifr_data, | |
2989 | sizeof(pi->tstamp_config))) | |
2990 | return -EFAULT; | |
2991 | ||
2992 | switch (pi->tstamp_config.rx_filter) { | |
2993 | case HWTSTAMP_FILTER_NONE: | |
2994 | pi->rxtstamp = false; | |
2995 | break; | |
2996 | case HWTSTAMP_FILTER_ALL: | |
2997 | pi->rxtstamp = true; | |
2998 | break; | |
2999 | default: | |
3000 | pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; | |
3001 | return -ERANGE; | |
3002 | } | |
3003 | ||
3004 | return copy_to_user(req->ifr_data, &pi->tstamp_config, | |
3005 | sizeof(pi->tstamp_config)) ? | |
3006 | -EFAULT : 0; | |
b8ff05a9 DM |
3007 | default: |
3008 | return -EOPNOTSUPP; | |
3009 | } | |
3010 | return ret; | |
3011 | } | |
3012 | ||
3013 | static void cxgb_set_rxmode(struct net_device *dev) | |
3014 | { | |
3015 | /* unfortunately we can't return errors to the stack */ | |
3016 | set_rxmode(dev, -1, false); | |
3017 | } | |
3018 | ||
3019 | static int cxgb_change_mtu(struct net_device *dev, int new_mtu) | |
3020 | { | |
3021 | int ret; | |
3022 | struct port_info *pi = netdev_priv(dev); | |
3023 | ||
3024 | if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */ | |
3025 | return -EINVAL; | |
b2612722 | 3026 | ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, |
060e0c75 | 3027 | -1, -1, -1, true); |
b8ff05a9 DM |
3028 | if (!ret) |
3029 | dev->mtu = new_mtu; | |
3030 | return ret; | |
3031 | } | |
3032 | ||
3033 | static int cxgb_set_mac_addr(struct net_device *dev, void *p) | |
3034 | { | |
3035 | int ret; | |
3036 | struct sockaddr *addr = p; | |
3037 | struct port_info *pi = netdev_priv(dev); | |
3038 | ||
3039 | if (!is_valid_ether_addr(addr->sa_data)) | |
504f9b5a | 3040 | return -EADDRNOTAVAIL; |
b8ff05a9 | 3041 | |
b2612722 | 3042 | ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, |
060e0c75 | 3043 | pi->xact_addr_filt, addr->sa_data, true, true); |
b8ff05a9 DM |
3044 | if (ret < 0) |
3045 | return ret; | |
3046 | ||
3047 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
3048 | pi->xact_addr_filt = ret; | |
3049 | return 0; | |
3050 | } | |
3051 | ||
b8ff05a9 DM |
3052 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3053 | static void cxgb_netpoll(struct net_device *dev) | |
3054 | { | |
3055 | struct port_info *pi = netdev_priv(dev); | |
3056 | struct adapter *adap = pi->adapter; | |
3057 | ||
3058 | if (adap->flags & USING_MSIX) { | |
3059 | int i; | |
3060 | struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; | |
3061 | ||
3062 | for (i = pi->nqsets; i; i--, rx++) | |
3063 | t4_sge_intr_msix(0, &rx->rspq); | |
3064 | } else | |
3065 | t4_intr_handler(adap)(0, adap); | |
3066 | } | |
3067 | #endif | |
3068 | ||
3069 | static const struct net_device_ops cxgb4_netdev_ops = { | |
3070 | .ndo_open = cxgb_open, | |
3071 | .ndo_stop = cxgb_close, | |
3072 | .ndo_start_xmit = t4_eth_xmit, | |
688848b1 | 3073 | .ndo_select_queue = cxgb_select_queue, |
9be793bf | 3074 | .ndo_get_stats64 = cxgb_get_stats, |
b8ff05a9 DM |
3075 | .ndo_set_rx_mode = cxgb_set_rxmode, |
3076 | .ndo_set_mac_address = cxgb_set_mac_addr, | |
2ed28baa | 3077 | .ndo_set_features = cxgb_set_features, |
b8ff05a9 DM |
3078 | .ndo_validate_addr = eth_validate_addr, |
3079 | .ndo_do_ioctl = cxgb_ioctl, | |
3080 | .ndo_change_mtu = cxgb_change_mtu, | |
b8ff05a9 DM |
3081 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3082 | .ndo_poll_controller = cxgb_netpoll, | |
3083 | #endif | |
84a200b3 VP |
3084 | #ifdef CONFIG_CHELSIO_T4_FCOE |
3085 | .ndo_fcoe_enable = cxgb_fcoe_enable, | |
3086 | .ndo_fcoe_disable = cxgb_fcoe_disable, | |
3087 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
3a336cb1 HS |
3088 | #ifdef CONFIG_NET_RX_BUSY_POLL |
3089 | .ndo_busy_poll = cxgb_busy_poll, | |
3090 | #endif | |
3091 | ||
b8ff05a9 DM |
3092 | }; |
3093 | ||
3094 | void t4_fatal_err(struct adapter *adap) | |
3095 | { | |
f612b815 | 3096 | t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0); |
b8ff05a9 DM |
3097 | t4_intr_disable(adap); |
3098 | dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); | |
3099 | } | |
3100 | ||
3101 | static void setup_memwin(struct adapter *adap) | |
3102 | { | |
b562fc37 | 3103 | u32 nic_win_base = t4_get_util_window(adap); |
b8ff05a9 | 3104 | |
b562fc37 | 3105 | t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); |
636f9d37 VP |
3106 | } |
3107 | ||
3108 | static void setup_memwin_rdma(struct adapter *adap) | |
3109 | { | |
1ae970e0 | 3110 | if (adap->vres.ocq.size) { |
0abfd152 HS |
3111 | u32 start; |
3112 | unsigned int sz_kb; | |
1ae970e0 | 3113 | |
0abfd152 HS |
3114 | start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); |
3115 | start &= PCI_BASE_ADDRESS_MEM_MASK; | |
3116 | start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); | |
1ae970e0 DM |
3117 | sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; |
3118 | t4_write_reg(adap, | |
f061de42 HS |
3119 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), |
3120 | start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); | |
1ae970e0 | 3121 | t4_write_reg(adap, |
f061de42 | 3122 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), |
1ae970e0 DM |
3123 | adap->vres.ocq.start); |
3124 | t4_read_reg(adap, | |
f061de42 | 3125 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); |
1ae970e0 | 3126 | } |
b8ff05a9 DM |
3127 | } |
3128 | ||
02b5fb8e DM |
3129 | static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) |
3130 | { | |
3131 | u32 v; | |
3132 | int ret; | |
3133 | ||
3134 | /* get device capabilities */ | |
3135 | memset(c, 0, sizeof(*c)); | |
e2ac9628 HS |
3136 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3137 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 3138 | c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); |
b2612722 | 3139 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); |
02b5fb8e DM |
3140 | if (ret < 0) |
3141 | return ret; | |
3142 | ||
3143 | /* select capabilities we'll be using */ | |
3144 | if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) { | |
3145 | if (!vf_acls) | |
3146 | c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM); | |
3147 | else | |
3148 | c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM); | |
3149 | } else if (vf_acls) { | |
3150 | dev_err(adap->pdev_dev, "virtualization ACLs not supported"); | |
3151 | return ret; | |
3152 | } | |
e2ac9628 HS |
3153 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3154 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
b2612722 | 3155 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); |
02b5fb8e DM |
3156 | if (ret < 0) |
3157 | return ret; | |
3158 | ||
b2612722 | 3159 | ret = t4_config_glbl_rss(adap, adap->pf, |
02b5fb8e | 3160 | FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, |
b2e1a3f0 HS |
3161 | FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | |
3162 | FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); | |
02b5fb8e DM |
3163 | if (ret < 0) |
3164 | return ret; | |
3165 | ||
b2612722 | 3166 | ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, |
4b8e27a8 HS |
3167 | MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, |
3168 | FW_CMD_CAP_PF); | |
02b5fb8e DM |
3169 | if (ret < 0) |
3170 | return ret; | |
3171 | ||
3172 | t4_sge_init(adap); | |
3173 | ||
02b5fb8e | 3174 | /* tweak some settings */ |
837e4a42 | 3175 | t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); |
0d804338 | 3176 | t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); |
837e4a42 HS |
3177 | t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); |
3178 | v = t4_read_reg(adap, TP_PIO_DATA_A); | |
3179 | t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); | |
060e0c75 | 3180 | |
dca4faeb VP |
3181 | /* first 4 Tx modulation queues point to consecutive Tx channels */ |
3182 | adap->params.tp.tx_modq_map = 0xE4; | |
0d804338 HS |
3183 | t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, |
3184 | TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); | |
dca4faeb VP |
3185 | |
3186 | /* associate each Tx modulation queue with consecutive Tx channels */ | |
3187 | v = 0x84218421; | |
837e4a42 | 3188 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3189 | &v, 1, TP_TX_SCHED_HDR_A); |
837e4a42 | 3190 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3191 | &v, 1, TP_TX_SCHED_FIFO_A); |
837e4a42 | 3192 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3193 | &v, 1, TP_TX_SCHED_PCMD_A); |
dca4faeb VP |
3194 | |
3195 | #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ | |
3196 | if (is_offload(adap)) { | |
0d804338 HS |
3197 | t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, |
3198 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3199 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3200 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3201 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
3202 | t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, | |
3203 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3204 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3205 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3206 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
dca4faeb VP |
3207 | } |
3208 | ||
060e0c75 | 3209 | /* get basic stuff going */ |
b2612722 | 3210 | return t4_early_init(adap, adap->pf); |
02b5fb8e DM |
3211 | } |
3212 | ||
b8ff05a9 DM |
3213 | /* |
3214 | * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. | |
3215 | */ | |
3216 | #define MAX_ATIDS 8192U | |
3217 | ||
636f9d37 VP |
3218 | /* |
3219 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
3220 | * | |
3221 | * If the firmware we're dealing with has Configuration File support, then | |
3222 | * we use that to perform all configuration | |
3223 | */ | |
3224 | ||
3225 | /* | |
3226 | * Tweak configuration based on module parameters, etc. Most of these have | |
3227 | * defaults assigned to them by Firmware Configuration Files (if we're using | |
3228 | * them) but need to be explicitly set if we're using hard-coded | |
3229 | * initialization. But even in the case of using Firmware Configuration | |
3230 | * Files, we'd like to expose the ability to change these via module | |
3231 | * parameters so these are essentially common tweaks/settings for | |
3232 | * Configuration Files and hard-coded initialization ... | |
3233 | */ | |
3234 | static int adap_init0_tweaks(struct adapter *adapter) | |
3235 | { | |
3236 | /* | |
3237 | * Fix up various Host-Dependent Parameters like Page Size, Cache | |
3238 | * Line Size, etc. The firmware default is for a 4KB Page Size and | |
3239 | * 64B Cache Line Size ... | |
3240 | */ | |
3241 | t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); | |
3242 | ||
3243 | /* | |
3244 | * Process module parameters which affect early initialization. | |
3245 | */ | |
3246 | if (rx_dma_offset != 2 && rx_dma_offset != 0) { | |
3247 | dev_err(&adapter->pdev->dev, | |
3248 | "Ignoring illegal rx_dma_offset=%d, using 2\n", | |
3249 | rx_dma_offset); | |
3250 | rx_dma_offset = 2; | |
3251 | } | |
f612b815 HS |
3252 | t4_set_reg_field(adapter, SGE_CONTROL_A, |
3253 | PKTSHIFT_V(PKTSHIFT_M), | |
3254 | PKTSHIFT_V(rx_dma_offset)); | |
636f9d37 VP |
3255 | |
3256 | /* | |
3257 | * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux | |
3258 | * adds the pseudo header itself. | |
3259 | */ | |
837e4a42 HS |
3260 | t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, |
3261 | CSUM_HAS_PSEUDO_HDR_F, 0); | |
636f9d37 VP |
3262 | |
3263 | return 0; | |
3264 | } | |
3265 | ||
01b69614 HS |
3266 | /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips |
3267 | * unto themselves and they contain their own firmware to perform their | |
3268 | * tasks ... | |
3269 | */ | |
3270 | static int phy_aq1202_version(const u8 *phy_fw_data, | |
3271 | size_t phy_fw_size) | |
3272 | { | |
3273 | int offset; | |
3274 | ||
3275 | /* At offset 0x8 you're looking for the primary image's | |
3276 | * starting offset which is 3 Bytes wide | |
3277 | * | |
3278 | * At offset 0xa of the primary image, you look for the offset | |
3279 | * of the DRAM segment which is 3 Bytes wide. | |
3280 | * | |
3281 | * The FW version is at offset 0x27e of the DRAM and is 2 Bytes | |
3282 | * wide | |
3283 | */ | |
3284 | #define be16(__p) (((__p)[0] << 8) | (__p)[1]) | |
3285 | #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) | |
3286 | #define le24(__p) (le16(__p) | ((__p)[2] << 16)) | |
3287 | ||
3288 | offset = le24(phy_fw_data + 0x8) << 12; | |
3289 | offset = le24(phy_fw_data + offset + 0xa); | |
3290 | return be16(phy_fw_data + offset + 0x27e); | |
3291 | ||
3292 | #undef be16 | |
3293 | #undef le16 | |
3294 | #undef le24 | |
3295 | } | |
3296 | ||
3297 | static struct info_10gbt_phy_fw { | |
3298 | unsigned int phy_fw_id; /* PCI Device ID */ | |
3299 | char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ | |
3300 | int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); | |
3301 | int phy_flash; /* Has FLASH for PHY Firmware */ | |
3302 | } phy_info_array[] = { | |
3303 | { | |
3304 | PHY_AQ1202_DEVICEID, | |
3305 | PHY_AQ1202_FIRMWARE, | |
3306 | phy_aq1202_version, | |
3307 | 1, | |
3308 | }, | |
3309 | { | |
3310 | PHY_BCM84834_DEVICEID, | |
3311 | PHY_BCM84834_FIRMWARE, | |
3312 | NULL, | |
3313 | 0, | |
3314 | }, | |
3315 | { 0, NULL, NULL }, | |
3316 | }; | |
3317 | ||
3318 | static struct info_10gbt_phy_fw *find_phy_info(int devid) | |
3319 | { | |
3320 | int i; | |
3321 | ||
3322 | for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { | |
3323 | if (phy_info_array[i].phy_fw_id == devid) | |
3324 | return &phy_info_array[i]; | |
3325 | } | |
3326 | return NULL; | |
3327 | } | |
3328 | ||
3329 | /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to | |
3330 | * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error | |
3331 | * we return a negative error number. If we transfer new firmware we return 1 | |
3332 | * (from t4_load_phy_fw()). If we don't do anything we return 0. | |
3333 | */ | |
3334 | static int adap_init0_phy(struct adapter *adap) | |
3335 | { | |
3336 | const struct firmware *phyf; | |
3337 | int ret; | |
3338 | struct info_10gbt_phy_fw *phy_info; | |
3339 | ||
3340 | /* Use the device ID to determine which PHY file to flash. | |
3341 | */ | |
3342 | phy_info = find_phy_info(adap->pdev->device); | |
3343 | if (!phy_info) { | |
3344 | dev_warn(adap->pdev_dev, | |
3345 | "No PHY Firmware file found for this PHY\n"); | |
3346 | return -EOPNOTSUPP; | |
3347 | } | |
3348 | ||
3349 | /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then | |
3350 | * use that. The adapter firmware provides us with a memory buffer | |
3351 | * where we can load a PHY firmware file from the host if we want to | |
3352 | * override the PHY firmware File in flash. | |
3353 | */ | |
3354 | ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, | |
3355 | adap->pdev_dev); | |
3356 | if (ret < 0) { | |
3357 | /* For adapters without FLASH attached to PHY for their | |
3358 | * firmware, it's obviously a fatal error if we can't get the | |
3359 | * firmware to the adapter. For adapters with PHY firmware | |
3360 | * FLASH storage, it's worth a warning if we can't find the | |
3361 | * PHY Firmware but we'll neuter the error ... | |
3362 | */ | |
3363 | dev_err(adap->pdev_dev, "unable to find PHY Firmware image " | |
3364 | "/lib/firmware/%s, error %d\n", | |
3365 | phy_info->phy_fw_file, -ret); | |
3366 | if (phy_info->phy_flash) { | |
3367 | int cur_phy_fw_ver = 0; | |
3368 | ||
3369 | t4_phy_fw_ver(adap, &cur_phy_fw_ver); | |
3370 | dev_warn(adap->pdev_dev, "continuing with, on-adapter " | |
3371 | "FLASH copy, version %#x\n", cur_phy_fw_ver); | |
3372 | ret = 0; | |
3373 | } | |
3374 | ||
3375 | return ret; | |
3376 | } | |
3377 | ||
3378 | /* Load PHY Firmware onto adapter. | |
3379 | */ | |
3380 | ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, | |
3381 | phy_info->phy_fw_version, | |
3382 | (u8 *)phyf->data, phyf->size); | |
3383 | if (ret < 0) | |
3384 | dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", | |
3385 | -ret); | |
3386 | else if (ret > 0) { | |
3387 | int new_phy_fw_ver = 0; | |
3388 | ||
3389 | if (phy_info->phy_fw_version) | |
3390 | new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, | |
3391 | phyf->size); | |
3392 | dev_info(adap->pdev_dev, "Successfully transferred PHY " | |
3393 | "Firmware /lib/firmware/%s, version %#x\n", | |
3394 | phy_info->phy_fw_file, new_phy_fw_ver); | |
3395 | } | |
3396 | ||
3397 | release_firmware(phyf); | |
3398 | ||
3399 | return ret; | |
3400 | } | |
3401 | ||
636f9d37 VP |
3402 | /* |
3403 | * Attempt to initialize the adapter via a Firmware Configuration File. | |
3404 | */ | |
3405 | static int adap_init0_config(struct adapter *adapter, int reset) | |
3406 | { | |
3407 | struct fw_caps_config_cmd caps_cmd; | |
3408 | const struct firmware *cf; | |
3409 | unsigned long mtype = 0, maddr = 0; | |
3410 | u32 finiver, finicsum, cfcsum; | |
16e47624 HS |
3411 | int ret; |
3412 | int config_issued = 0; | |
0a57a536 | 3413 | char *fw_config_file, fw_config_file_path[256]; |
16e47624 | 3414 | char *config_name = NULL; |
636f9d37 VP |
3415 | |
3416 | /* | |
3417 | * Reset device if necessary. | |
3418 | */ | |
3419 | if (reset) { | |
3420 | ret = t4_fw_reset(adapter, adapter->mbox, | |
0d804338 | 3421 | PIORSTMODE_F | PIORST_F); |
636f9d37 VP |
3422 | if (ret < 0) |
3423 | goto bye; | |
3424 | } | |
3425 | ||
01b69614 HS |
3426 | /* If this is a 10Gb/s-BT adapter make sure the chip-external |
3427 | * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs | |
3428 | * to be performed after any global adapter RESET above since some | |
3429 | * PHYs only have local RAM copies of the PHY firmware. | |
3430 | */ | |
3431 | if (is_10gbt_device(adapter->pdev->device)) { | |
3432 | ret = adap_init0_phy(adapter); | |
3433 | if (ret < 0) | |
3434 | goto bye; | |
3435 | } | |
636f9d37 VP |
3436 | /* |
3437 | * If we have a T4 configuration file under /lib/firmware/cxgb4/, | |
3438 | * then use that. Otherwise, use the configuration file stored | |
3439 | * in the adapter flash ... | |
3440 | */ | |
d14807dd | 3441 | switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { |
0a57a536 | 3442 | case CHELSIO_T4: |
16e47624 | 3443 | fw_config_file = FW4_CFNAME; |
0a57a536 SR |
3444 | break; |
3445 | case CHELSIO_T5: | |
3446 | fw_config_file = FW5_CFNAME; | |
3447 | break; | |
3ccc6cf7 HS |
3448 | case CHELSIO_T6: |
3449 | fw_config_file = FW6_CFNAME; | |
3450 | break; | |
0a57a536 SR |
3451 | default: |
3452 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | |
3453 | adapter->pdev->device); | |
3454 | ret = -EINVAL; | |
3455 | goto bye; | |
3456 | } | |
3457 | ||
3458 | ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); | |
636f9d37 | 3459 | if (ret < 0) { |
16e47624 | 3460 | config_name = "On FLASH"; |
636f9d37 VP |
3461 | mtype = FW_MEMTYPE_CF_FLASH; |
3462 | maddr = t4_flash_cfg_addr(adapter); | |
3463 | } else { | |
3464 | u32 params[7], val[7]; | |
3465 | ||
16e47624 HS |
3466 | sprintf(fw_config_file_path, |
3467 | "/lib/firmware/%s", fw_config_file); | |
3468 | config_name = fw_config_file_path; | |
3469 | ||
636f9d37 VP |
3470 | if (cf->size >= FLASH_CFG_MAX_SIZE) |
3471 | ret = -ENOMEM; | |
3472 | else { | |
5167865a HS |
3473 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3474 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
636f9d37 | 3475 | ret = t4_query_params(adapter, adapter->mbox, |
b2612722 | 3476 | adapter->pf, 0, 1, params, val); |
636f9d37 VP |
3477 | if (ret == 0) { |
3478 | /* | |
fc5ab020 | 3479 | * For t4_memory_rw() below addresses and |
636f9d37 VP |
3480 | * sizes have to be in terms of multiples of 4 |
3481 | * bytes. So, if the Configuration File isn't | |
3482 | * a multiple of 4 bytes in length we'll have | |
3483 | * to write that out separately since we can't | |
3484 | * guarantee that the bytes following the | |
3485 | * residual byte in the buffer returned by | |
3486 | * request_firmware() are zeroed out ... | |
3487 | */ | |
3488 | size_t resid = cf->size & 0x3; | |
3489 | size_t size = cf->size & ~0x3; | |
3490 | __be32 *data = (__be32 *)cf->data; | |
3491 | ||
5167865a HS |
3492 | mtype = FW_PARAMS_PARAM_Y_G(val[0]); |
3493 | maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; | |
636f9d37 | 3494 | |
fc5ab020 HS |
3495 | spin_lock(&adapter->win0_lock); |
3496 | ret = t4_memory_rw(adapter, 0, mtype, maddr, | |
3497 | size, data, T4_MEMORY_WRITE); | |
636f9d37 VP |
3498 | if (ret == 0 && resid != 0) { |
3499 | union { | |
3500 | __be32 word; | |
3501 | char buf[4]; | |
3502 | } last; | |
3503 | int i; | |
3504 | ||
3505 | last.word = data[size >> 2]; | |
3506 | for (i = resid; i < 4; i++) | |
3507 | last.buf[i] = 0; | |
fc5ab020 HS |
3508 | ret = t4_memory_rw(adapter, 0, mtype, |
3509 | maddr + size, | |
3510 | 4, &last.word, | |
3511 | T4_MEMORY_WRITE); | |
636f9d37 | 3512 | } |
fc5ab020 | 3513 | spin_unlock(&adapter->win0_lock); |
636f9d37 VP |
3514 | } |
3515 | } | |
3516 | ||
3517 | release_firmware(cf); | |
3518 | if (ret) | |
3519 | goto bye; | |
3520 | } | |
3521 | ||
3522 | /* | |
3523 | * Issue a Capability Configuration command to the firmware to get it | |
3524 | * to parse the Configuration File. We don't use t4_fw_config_file() | |
3525 | * because we want the ability to modify various features after we've | |
3526 | * processed the configuration file ... | |
3527 | */ | |
3528 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3529 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3530 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3531 | FW_CMD_REQUEST_F | | |
3532 | FW_CMD_READ_F); | |
ce91a923 | 3533 | caps_cmd.cfvalid_to_len16 = |
5167865a HS |
3534 | htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | |
3535 | FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | | |
3536 | FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | | |
636f9d37 VP |
3537 | FW_LEN16(caps_cmd)); |
3538 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), | |
3539 | &caps_cmd); | |
16e47624 HS |
3540 | |
3541 | /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware | |
3542 | * Configuration File in FLASH), our last gasp effort is to use the | |
3543 | * Firmware Configuration File which is embedded in the firmware. A | |
3544 | * very few early versions of the firmware didn't have one embedded | |
3545 | * but we can ignore those. | |
3546 | */ | |
3547 | if (ret == -ENOENT) { | |
3548 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3549 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3550 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3551 | FW_CMD_REQUEST_F | | |
3552 | FW_CMD_READ_F); | |
16e47624 HS |
3553 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
3554 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, | |
3555 | sizeof(caps_cmd), &caps_cmd); | |
3556 | config_name = "Firmware Default"; | |
3557 | } | |
3558 | ||
3559 | config_issued = 1; | |
636f9d37 VP |
3560 | if (ret < 0) |
3561 | goto bye; | |
3562 | ||
3563 | finiver = ntohl(caps_cmd.finiver); | |
3564 | finicsum = ntohl(caps_cmd.finicsum); | |
3565 | cfcsum = ntohl(caps_cmd.cfcsum); | |
3566 | if (finicsum != cfcsum) | |
3567 | dev_warn(adapter->pdev_dev, "Configuration File checksum "\ | |
3568 | "mismatch: [fini] csum=%#x, computed csum=%#x\n", | |
3569 | finicsum, cfcsum); | |
3570 | ||
636f9d37 VP |
3571 | /* |
3572 | * And now tell the firmware to use the configuration we just loaded. | |
3573 | */ | |
3574 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3575 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3576 | FW_CMD_REQUEST_F | | |
3577 | FW_CMD_WRITE_F); | |
ce91a923 | 3578 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
3579 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), |
3580 | NULL); | |
3581 | if (ret < 0) | |
3582 | goto bye; | |
3583 | ||
3584 | /* | |
3585 | * Tweak configuration based on system architecture, module | |
3586 | * parameters, etc. | |
3587 | */ | |
3588 | ret = adap_init0_tweaks(adapter); | |
3589 | if (ret < 0) | |
3590 | goto bye; | |
3591 | ||
3592 | /* | |
3593 | * And finally tell the firmware to initialize itself using the | |
3594 | * parameters from the Configuration File. | |
3595 | */ | |
3596 | ret = t4_fw_initialize(adapter, adapter->mbox); | |
3597 | if (ret < 0) | |
3598 | goto bye; | |
3599 | ||
06640310 HS |
3600 | /* Emit Firmware Configuration File information and return |
3601 | * successfully. | |
636f9d37 | 3602 | */ |
636f9d37 | 3603 | dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ |
16e47624 HS |
3604 | "Configuration File \"%s\", version %#x, computed checksum %#x\n", |
3605 | config_name, finiver, cfcsum); | |
636f9d37 VP |
3606 | return 0; |
3607 | ||
3608 | /* | |
3609 | * Something bad happened. Return the error ... (If the "error" | |
3610 | * is that there's no Configuration File on the adapter we don't | |
3611 | * want to issue a warning since this is fairly common.) | |
3612 | */ | |
3613 | bye: | |
16e47624 HS |
3614 | if (config_issued && ret != -ENOENT) |
3615 | dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", | |
3616 | config_name, -ret); | |
636f9d37 VP |
3617 | return ret; |
3618 | } | |
3619 | ||
16e47624 HS |
3620 | static struct fw_info fw_info_array[] = { |
3621 | { | |
3622 | .chip = CHELSIO_T4, | |
3623 | .fs_name = FW4_CFNAME, | |
3624 | .fw_mod_name = FW4_FNAME, | |
3625 | .fw_hdr = { | |
3626 | .chip = FW_HDR_CHIP_T4, | |
3627 | .fw_ver = __cpu_to_be32(FW_VERSION(T4)), | |
3628 | .intfver_nic = FW_INTFVER(T4, NIC), | |
3629 | .intfver_vnic = FW_INTFVER(T4, VNIC), | |
3630 | .intfver_ri = FW_INTFVER(T4, RI), | |
3631 | .intfver_iscsi = FW_INTFVER(T4, ISCSI), | |
3632 | .intfver_fcoe = FW_INTFVER(T4, FCOE), | |
3633 | }, | |
3634 | }, { | |
3635 | .chip = CHELSIO_T5, | |
3636 | .fs_name = FW5_CFNAME, | |
3637 | .fw_mod_name = FW5_FNAME, | |
3638 | .fw_hdr = { | |
3639 | .chip = FW_HDR_CHIP_T5, | |
3640 | .fw_ver = __cpu_to_be32(FW_VERSION(T5)), | |
3641 | .intfver_nic = FW_INTFVER(T5, NIC), | |
3642 | .intfver_vnic = FW_INTFVER(T5, VNIC), | |
3643 | .intfver_ri = FW_INTFVER(T5, RI), | |
3644 | .intfver_iscsi = FW_INTFVER(T5, ISCSI), | |
3645 | .intfver_fcoe = FW_INTFVER(T5, FCOE), | |
3646 | }, | |
3ccc6cf7 HS |
3647 | }, { |
3648 | .chip = CHELSIO_T6, | |
3649 | .fs_name = FW6_CFNAME, | |
3650 | .fw_mod_name = FW6_FNAME, | |
3651 | .fw_hdr = { | |
3652 | .chip = FW_HDR_CHIP_T6, | |
3653 | .fw_ver = __cpu_to_be32(FW_VERSION(T6)), | |
3654 | .intfver_nic = FW_INTFVER(T6, NIC), | |
3655 | .intfver_vnic = FW_INTFVER(T6, VNIC), | |
3656 | .intfver_ofld = FW_INTFVER(T6, OFLD), | |
3657 | .intfver_ri = FW_INTFVER(T6, RI), | |
3658 | .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), | |
3659 | .intfver_iscsi = FW_INTFVER(T6, ISCSI), | |
3660 | .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), | |
3661 | .intfver_fcoe = FW_INTFVER(T6, FCOE), | |
3662 | }, | |
16e47624 | 3663 | } |
3ccc6cf7 | 3664 | |
16e47624 HS |
3665 | }; |
3666 | ||
3667 | static struct fw_info *find_fw_info(int chip) | |
3668 | { | |
3669 | int i; | |
3670 | ||
3671 | for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { | |
3672 | if (fw_info_array[i].chip == chip) | |
3673 | return &fw_info_array[i]; | |
3674 | } | |
3675 | return NULL; | |
3676 | } | |
3677 | ||
b8ff05a9 DM |
3678 | /* |
3679 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
3680 | */ | |
3681 | static int adap_init0(struct adapter *adap) | |
3682 | { | |
3683 | int ret; | |
3684 | u32 v, port_vec; | |
3685 | enum dev_state state; | |
3686 | u32 params[7], val[7]; | |
9a4da2cd | 3687 | struct fw_caps_config_cmd caps_cmd; |
dcf7b6f5 | 3688 | int reset = 1; |
b8ff05a9 | 3689 | |
ae469b68 HS |
3690 | /* Grab Firmware Device Log parameters as early as possible so we have |
3691 | * access to it for debugging, etc. | |
3692 | */ | |
3693 | ret = t4_init_devlog_params(adap); | |
3694 | if (ret < 0) | |
3695 | return ret; | |
3696 | ||
666224d4 HS |
3697 | /* Contact FW, advertising Master capability */ |
3698 | ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); | |
b8ff05a9 DM |
3699 | if (ret < 0) { |
3700 | dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", | |
3701 | ret); | |
3702 | return ret; | |
3703 | } | |
636f9d37 VP |
3704 | if (ret == adap->mbox) |
3705 | adap->flags |= MASTER_PF; | |
b8ff05a9 | 3706 | |
636f9d37 VP |
3707 | /* |
3708 | * If we're the Master PF Driver and the device is uninitialized, | |
3709 | * then let's consider upgrading the firmware ... (We always want | |
3710 | * to check the firmware version number in order to A. get it for | |
3711 | * later reporting and B. to warn if the currently loaded firmware | |
3712 | * is excessively mismatched relative to the driver.) | |
3713 | */ | |
16e47624 HS |
3714 | t4_get_fw_version(adap, &adap->params.fw_vers); |
3715 | t4_get_tp_version(adap, &adap->params.tp_vers); | |
a69265e9 HS |
3716 | ret = t4_check_fw_version(adap); |
3717 | /* If firmware is too old (not supported by driver) force an update. */ | |
21d11bd6 | 3718 | if (ret) |
a69265e9 | 3719 | state = DEV_STATE_UNINIT; |
636f9d37 | 3720 | if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { |
16e47624 HS |
3721 | struct fw_info *fw_info; |
3722 | struct fw_hdr *card_fw; | |
3723 | const struct firmware *fw; | |
3724 | const u8 *fw_data = NULL; | |
3725 | unsigned int fw_size = 0; | |
3726 | ||
3727 | /* This is the firmware whose headers the driver was compiled | |
3728 | * against | |
3729 | */ | |
3730 | fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3731 | if (fw_info == NULL) { | |
3732 | dev_err(adap->pdev_dev, | |
3733 | "unable to get firmware info for chip %d.\n", | |
3734 | CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3735 | return -EINVAL; | |
636f9d37 | 3736 | } |
16e47624 HS |
3737 | |
3738 | /* allocate memory to read the header of the firmware on the | |
3739 | * card | |
3740 | */ | |
3741 | card_fw = t4_alloc_mem(sizeof(*card_fw)); | |
3742 | ||
3743 | /* Get FW from from /lib/firmware/ */ | |
3744 | ret = request_firmware(&fw, fw_info->fw_mod_name, | |
3745 | adap->pdev_dev); | |
3746 | if (ret < 0) { | |
3747 | dev_err(adap->pdev_dev, | |
3748 | "unable to load firmware image %s, error %d\n", | |
3749 | fw_info->fw_mod_name, ret); | |
3750 | } else { | |
3751 | fw_data = fw->data; | |
3752 | fw_size = fw->size; | |
3753 | } | |
3754 | ||
3755 | /* upgrade FW logic */ | |
3756 | ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, | |
3757 | state, &reset); | |
3758 | ||
3759 | /* Cleaning up */ | |
0b5b6bee | 3760 | release_firmware(fw); |
16e47624 HS |
3761 | t4_free_mem(card_fw); |
3762 | ||
636f9d37 | 3763 | if (ret < 0) |
16e47624 | 3764 | goto bye; |
636f9d37 | 3765 | } |
b8ff05a9 | 3766 | |
636f9d37 VP |
3767 | /* |
3768 | * Grab VPD parameters. This should be done after we establish a | |
3769 | * connection to the firmware since some of the VPD parameters | |
3770 | * (notably the Core Clock frequency) are retrieved via requests to | |
3771 | * the firmware. On the other hand, we need these fairly early on | |
3772 | * so we do this right after getting ahold of the firmware. | |
3773 | */ | |
098ef6c2 | 3774 | ret = t4_get_vpd_params(adap, &adap->params.vpd); |
a0881cab DM |
3775 | if (ret < 0) |
3776 | goto bye; | |
a0881cab | 3777 | |
636f9d37 | 3778 | /* |
13ee15d3 VP |
3779 | * Find out what ports are available to us. Note that we need to do |
3780 | * this before calling adap_init0_no_config() since it needs nports | |
3781 | * and portvec ... | |
636f9d37 VP |
3782 | */ |
3783 | v = | |
5167865a HS |
3784 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3785 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); | |
b2612722 | 3786 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); |
a0881cab DM |
3787 | if (ret < 0) |
3788 | goto bye; | |
3789 | ||
636f9d37 VP |
3790 | adap->params.nports = hweight32(port_vec); |
3791 | adap->params.portvec = port_vec; | |
3792 | ||
06640310 HS |
3793 | /* If the firmware is initialized already, emit a simply note to that |
3794 | * effect. Otherwise, it's time to try initializing the adapter. | |
636f9d37 VP |
3795 | */ |
3796 | if (state == DEV_STATE_INIT) { | |
3797 | dev_info(adap->pdev_dev, "Coming up as %s: "\ | |
3798 | "Adapter already initialized\n", | |
3799 | adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); | |
636f9d37 VP |
3800 | } else { |
3801 | dev_info(adap->pdev_dev, "Coming up as MASTER: "\ | |
3802 | "Initializing adapter\n"); | |
06640310 HS |
3803 | |
3804 | /* Find out whether we're dealing with a version of the | |
3805 | * firmware which has configuration file support. | |
636f9d37 | 3806 | */ |
06640310 HS |
3807 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3808 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
b2612722 | 3809 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, |
06640310 | 3810 | params, val); |
13ee15d3 | 3811 | |
06640310 HS |
3812 | /* If the firmware doesn't support Configuration Files, |
3813 | * return an error. | |
3814 | */ | |
3815 | if (ret < 0) { | |
3816 | dev_err(adap->pdev_dev, "firmware doesn't support " | |
3817 | "Firmware Configuration Files\n"); | |
3818 | goto bye; | |
3819 | } | |
3820 | ||
3821 | /* The firmware provides us with a memory buffer where we can | |
3822 | * load a Configuration File from the host if we want to | |
3823 | * override the Configuration File in flash. | |
3824 | */ | |
3825 | ret = adap_init0_config(adap, reset); | |
3826 | if (ret == -ENOENT) { | |
3827 | dev_err(adap->pdev_dev, "no Configuration File " | |
3828 | "present on adapter.\n"); | |
3829 | goto bye; | |
636f9d37 VP |
3830 | } |
3831 | if (ret < 0) { | |
06640310 HS |
3832 | dev_err(adap->pdev_dev, "could not initialize " |
3833 | "adapter, error %d\n", -ret); | |
636f9d37 VP |
3834 | goto bye; |
3835 | } | |
3836 | } | |
3837 | ||
06640310 HS |
3838 | /* Give the SGE code a chance to pull in anything that it needs ... |
3839 | * Note that this must be called after we retrieve our VPD parameters | |
3840 | * in order to know how to convert core ticks to seconds, etc. | |
636f9d37 | 3841 | */ |
06640310 HS |
3842 | ret = t4_sge_init(adap); |
3843 | if (ret < 0) | |
3844 | goto bye; | |
636f9d37 | 3845 | |
9a4da2cd VP |
3846 | if (is_bypass_device(adap->pdev->device)) |
3847 | adap->params.bypass = 1; | |
3848 | ||
636f9d37 VP |
3849 | /* |
3850 | * Grab some of our basic fundamental operating parameters. | |
3851 | */ | |
3852 | #define FW_PARAM_DEV(param) \ | |
5167865a HS |
3853 | (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ |
3854 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) | |
636f9d37 | 3855 | |
b8ff05a9 | 3856 | #define FW_PARAM_PFVF(param) \ |
5167865a HS |
3857 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ |
3858 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ | |
3859 | FW_PARAMS_PARAM_Y_V(0) | \ | |
3860 | FW_PARAMS_PARAM_Z_V(0) | |
b8ff05a9 | 3861 | |
636f9d37 | 3862 | params[0] = FW_PARAM_PFVF(EQ_START); |
b8ff05a9 DM |
3863 | params[1] = FW_PARAM_PFVF(L2T_START); |
3864 | params[2] = FW_PARAM_PFVF(L2T_END); | |
3865 | params[3] = FW_PARAM_PFVF(FILTER_START); | |
3866 | params[4] = FW_PARAM_PFVF(FILTER_END); | |
e46dab4d | 3867 | params[5] = FW_PARAM_PFVF(IQFLINT_START); |
b2612722 | 3868 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); |
b8ff05a9 DM |
3869 | if (ret < 0) |
3870 | goto bye; | |
636f9d37 VP |
3871 | adap->sge.egr_start = val[0]; |
3872 | adap->l2t_start = val[1]; | |
3873 | adap->l2t_end = val[2]; | |
b8ff05a9 DM |
3874 | adap->tids.ftid_base = val[3]; |
3875 | adap->tids.nftids = val[4] - val[3] + 1; | |
e46dab4d | 3876 | adap->sge.ingr_start = val[5]; |
b8ff05a9 | 3877 | |
4b8e27a8 HS |
3878 | /* qids (ingress/egress) returned from firmware can be anywhere |
3879 | * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. | |
3880 | * Hence driver needs to allocate memory for this range to | |
3881 | * store the queue info. Get the highest IQFLINT/EQ index returned | |
3882 | * in FW_EQ_*_CMD.alloc command. | |
3883 | */ | |
3884 | params[0] = FW_PARAM_PFVF(EQ_END); | |
3885 | params[1] = FW_PARAM_PFVF(IQFLINT_END); | |
b2612722 | 3886 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
4b8e27a8 HS |
3887 | if (ret < 0) |
3888 | goto bye; | |
3889 | adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; | |
3890 | adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; | |
3891 | ||
3892 | adap->sge.egr_map = kcalloc(adap->sge.egr_sz, | |
3893 | sizeof(*adap->sge.egr_map), GFP_KERNEL); | |
3894 | if (!adap->sge.egr_map) { | |
3895 | ret = -ENOMEM; | |
3896 | goto bye; | |
3897 | } | |
3898 | ||
3899 | adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, | |
3900 | sizeof(*adap->sge.ingr_map), GFP_KERNEL); | |
3901 | if (!adap->sge.ingr_map) { | |
3902 | ret = -ENOMEM; | |
3903 | goto bye; | |
3904 | } | |
3905 | ||
3906 | /* Allocate the memory for the vaious egress queue bitmaps | |
5b377d11 | 3907 | * ie starving_fl, txq_maperr and blocked_fl. |
4b8e27a8 HS |
3908 | */ |
3909 | adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3910 | sizeof(long), GFP_KERNEL); | |
3911 | if (!adap->sge.starving_fl) { | |
3912 | ret = -ENOMEM; | |
3913 | goto bye; | |
3914 | } | |
3915 | ||
3916 | adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3917 | sizeof(long), GFP_KERNEL); | |
3918 | if (!adap->sge.txq_maperr) { | |
3919 | ret = -ENOMEM; | |
3920 | goto bye; | |
3921 | } | |
3922 | ||
5b377d11 HS |
3923 | #ifdef CONFIG_DEBUG_FS |
3924 | adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3925 | sizeof(long), GFP_KERNEL); | |
3926 | if (!adap->sge.blocked_fl) { | |
3927 | ret = -ENOMEM; | |
3928 | goto bye; | |
3929 | } | |
3930 | #endif | |
3931 | ||
b5a02f50 AB |
3932 | params[0] = FW_PARAM_PFVF(CLIP_START); |
3933 | params[1] = FW_PARAM_PFVF(CLIP_END); | |
b2612722 | 3934 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
b5a02f50 AB |
3935 | if (ret < 0) |
3936 | goto bye; | |
3937 | adap->clipt_start = val[0]; | |
3938 | adap->clipt_end = val[1]; | |
3939 | ||
636f9d37 VP |
3940 | /* query params related to active filter region */ |
3941 | params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); | |
3942 | params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); | |
b2612722 | 3943 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
636f9d37 VP |
3944 | /* If Active filter size is set we enable establishing |
3945 | * offload connection through firmware work request | |
3946 | */ | |
3947 | if ((val[0] != val[1]) && (ret >= 0)) { | |
3948 | adap->flags |= FW_OFLD_CONN; | |
3949 | adap->tids.aftid_base = val[0]; | |
3950 | adap->tids.aftid_end = val[1]; | |
3951 | } | |
3952 | ||
b407a4a9 VP |
3953 | /* If we're running on newer firmware, let it know that we're |
3954 | * prepared to deal with encapsulated CPL messages. Older | |
3955 | * firmware won't understand this and we'll just get | |
3956 | * unencapsulated messages ... | |
3957 | */ | |
3958 | params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); | |
3959 | val[0] = 1; | |
b2612722 | 3960 | (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); |
b407a4a9 | 3961 | |
1ac0f095 KS |
3962 | /* |
3963 | * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL | |
3964 | * capability. Earlier versions of the firmware didn't have the | |
3965 | * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no | |
3966 | * permission to use ULPTX MEMWRITE DSGL. | |
3967 | */ | |
3968 | if (is_t4(adap->params.chip)) { | |
3969 | adap->params.ulptx_memwrite_dsgl = false; | |
3970 | } else { | |
3971 | params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); | |
b2612722 | 3972 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, |
1ac0f095 KS |
3973 | 1, params, val); |
3974 | adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); | |
3975 | } | |
3976 | ||
636f9d37 VP |
3977 | /* |
3978 | * Get device capabilities so we can determine what resources we need | |
3979 | * to manage. | |
3980 | */ | |
3981 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
e2ac9628 HS |
3982 | caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3983 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 3984 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
3985 | ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), |
3986 | &caps_cmd); | |
3987 | if (ret < 0) | |
3988 | goto bye; | |
3989 | ||
13ee15d3 | 3990 | if (caps_cmd.ofldcaps) { |
b8ff05a9 DM |
3991 | /* query offload-related parameters */ |
3992 | params[0] = FW_PARAM_DEV(NTID); | |
3993 | params[1] = FW_PARAM_PFVF(SERVER_START); | |
3994 | params[2] = FW_PARAM_PFVF(SERVER_END); | |
3995 | params[3] = FW_PARAM_PFVF(TDDP_START); | |
3996 | params[4] = FW_PARAM_PFVF(TDDP_END); | |
3997 | params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); | |
b2612722 | 3998 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 3999 | params, val); |
b8ff05a9 DM |
4000 | if (ret < 0) |
4001 | goto bye; | |
4002 | adap->tids.ntids = val[0]; | |
4003 | adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); | |
4004 | adap->tids.stid_base = val[1]; | |
4005 | adap->tids.nstids = val[2] - val[1] + 1; | |
636f9d37 | 4006 | /* |
dbedd44e | 4007 | * Setup server filter region. Divide the available filter |
636f9d37 VP |
4008 | * region into two parts. Regular filters get 1/3rd and server |
4009 | * filters get 2/3rd part. This is only enabled if workarond | |
4010 | * path is enabled. | |
4011 | * 1. For regular filters. | |
4012 | * 2. Server filter: This are special filters which are used | |
4013 | * to redirect SYN packets to offload queue. | |
4014 | */ | |
4015 | if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { | |
4016 | adap->tids.sftid_base = adap->tids.ftid_base + | |
4017 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
4018 | adap->tids.nsftids = adap->tids.nftids - | |
4019 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
4020 | adap->tids.nftids = adap->tids.sftid_base - | |
4021 | adap->tids.ftid_base; | |
4022 | } | |
b8ff05a9 DM |
4023 | adap->vres.ddp.start = val[3]; |
4024 | adap->vres.ddp.size = val[4] - val[3] + 1; | |
4025 | adap->params.ofldq_wr_cred = val[5]; | |
636f9d37 | 4026 | |
b8ff05a9 DM |
4027 | adap->params.offload = 1; |
4028 | } | |
636f9d37 | 4029 | if (caps_cmd.rdmacaps) { |
b8ff05a9 DM |
4030 | params[0] = FW_PARAM_PFVF(STAG_START); |
4031 | params[1] = FW_PARAM_PFVF(STAG_END); | |
4032 | params[2] = FW_PARAM_PFVF(RQ_START); | |
4033 | params[3] = FW_PARAM_PFVF(RQ_END); | |
4034 | params[4] = FW_PARAM_PFVF(PBL_START); | |
4035 | params[5] = FW_PARAM_PFVF(PBL_END); | |
b2612722 | 4036 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 4037 | params, val); |
b8ff05a9 DM |
4038 | if (ret < 0) |
4039 | goto bye; | |
4040 | adap->vres.stag.start = val[0]; | |
4041 | adap->vres.stag.size = val[1] - val[0] + 1; | |
4042 | adap->vres.rq.start = val[2]; | |
4043 | adap->vres.rq.size = val[3] - val[2] + 1; | |
4044 | adap->vres.pbl.start = val[4]; | |
4045 | adap->vres.pbl.size = val[5] - val[4] + 1; | |
a0881cab DM |
4046 | |
4047 | params[0] = FW_PARAM_PFVF(SQRQ_START); | |
4048 | params[1] = FW_PARAM_PFVF(SQRQ_END); | |
4049 | params[2] = FW_PARAM_PFVF(CQ_START); | |
4050 | params[3] = FW_PARAM_PFVF(CQ_END); | |
1ae970e0 DM |
4051 | params[4] = FW_PARAM_PFVF(OCQ_START); |
4052 | params[5] = FW_PARAM_PFVF(OCQ_END); | |
b2612722 | 4053 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, |
5c937dd3 | 4054 | val); |
a0881cab DM |
4055 | if (ret < 0) |
4056 | goto bye; | |
4057 | adap->vres.qp.start = val[0]; | |
4058 | adap->vres.qp.size = val[1] - val[0] + 1; | |
4059 | adap->vres.cq.start = val[2]; | |
4060 | adap->vres.cq.size = val[3] - val[2] + 1; | |
1ae970e0 DM |
4061 | adap->vres.ocq.start = val[4]; |
4062 | adap->vres.ocq.size = val[5] - val[4] + 1; | |
4c2c5763 HS |
4063 | |
4064 | params[0] = FW_PARAM_DEV(MAXORDIRD_QP); | |
4065 | params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); | |
b2612722 | 4066 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, |
5c937dd3 | 4067 | val); |
4c2c5763 HS |
4068 | if (ret < 0) { |
4069 | adap->params.max_ordird_qp = 8; | |
4070 | adap->params.max_ird_adapter = 32 * adap->tids.ntids; | |
4071 | ret = 0; | |
4072 | } else { | |
4073 | adap->params.max_ordird_qp = val[0]; | |
4074 | adap->params.max_ird_adapter = val[1]; | |
4075 | } | |
4076 | dev_info(adap->pdev_dev, | |
4077 | "max_ordird_qp %d max_ird_adapter %d\n", | |
4078 | adap->params.max_ordird_qp, | |
4079 | adap->params.max_ird_adapter); | |
b8ff05a9 | 4080 | } |
636f9d37 | 4081 | if (caps_cmd.iscsicaps) { |
b8ff05a9 DM |
4082 | params[0] = FW_PARAM_PFVF(ISCSI_START); |
4083 | params[1] = FW_PARAM_PFVF(ISCSI_END); | |
b2612722 | 4084 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, |
636f9d37 | 4085 | params, val); |
b8ff05a9 DM |
4086 | if (ret < 0) |
4087 | goto bye; | |
4088 | adap->vres.iscsi.start = val[0]; | |
4089 | adap->vres.iscsi.size = val[1] - val[0] + 1; | |
4090 | } | |
4091 | #undef FW_PARAM_PFVF | |
4092 | #undef FW_PARAM_DEV | |
4093 | ||
92e7ae71 HS |
4094 | /* The MTU/MSS Table is initialized by now, so load their values. If |
4095 | * we're initializing the adapter, then we'll make any modifications | |
4096 | * we want to the MTU/MSS Table and also initialize the congestion | |
4097 | * parameters. | |
636f9d37 | 4098 | */ |
b8ff05a9 | 4099 | t4_read_mtu_tbl(adap, adap->params.mtus, NULL); |
92e7ae71 HS |
4100 | if (state != DEV_STATE_INIT) { |
4101 | int i; | |
4102 | ||
4103 | /* The default MTU Table contains values 1492 and 1500. | |
4104 | * However, for TCP, it's better to have two values which are | |
4105 | * a multiple of 8 +/- 4 bytes apart near this popular MTU. | |
4106 | * This allows us to have a TCP Data Payload which is a | |
4107 | * multiple of 8 regardless of what combination of TCP Options | |
4108 | * are in use (always a multiple of 4 bytes) which is | |
4109 | * important for performance reasons. For instance, if no | |
4110 | * options are in use, then we have a 20-byte IP header and a | |
4111 | * 20-byte TCP header. In this case, a 1500-byte MSS would | |
4112 | * result in a TCP Data Payload of 1500 - 40 == 1460 bytes | |
4113 | * which is not a multiple of 8. So using an MSS of 1488 in | |
4114 | * this case results in a TCP Data Payload of 1448 bytes which | |
4115 | * is a multiple of 8. On the other hand, if 12-byte TCP Time | |
4116 | * Stamps have been negotiated, then an MTU of 1500 bytes | |
4117 | * results in a TCP Data Payload of 1448 bytes which, as | |
4118 | * above, is a multiple of 8 bytes ... | |
4119 | */ | |
4120 | for (i = 0; i < NMTUS; i++) | |
4121 | if (adap->params.mtus[i] == 1492) { | |
4122 | adap->params.mtus[i] = 1488; | |
4123 | break; | |
4124 | } | |
7ee9ff94 | 4125 | |
92e7ae71 HS |
4126 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, |
4127 | adap->params.b_wnd); | |
4128 | } | |
df64e4d3 | 4129 | t4_init_sge_params(adap); |
636f9d37 | 4130 | adap->flags |= FW_OK; |
c1e9af0c | 4131 | t4_init_tp_params(adap); |
b8ff05a9 DM |
4132 | return 0; |
4133 | ||
4134 | /* | |
636f9d37 VP |
4135 | * Something bad happened. If a command timed out or failed with EIO |
4136 | * FW does not operate within its spec or something catastrophic | |
4137 | * happened to HW/FW, stop issuing commands. | |
b8ff05a9 | 4138 | */ |
636f9d37 | 4139 | bye: |
4b8e27a8 HS |
4140 | kfree(adap->sge.egr_map); |
4141 | kfree(adap->sge.ingr_map); | |
4142 | kfree(adap->sge.starving_fl); | |
4143 | kfree(adap->sge.txq_maperr); | |
5b377d11 HS |
4144 | #ifdef CONFIG_DEBUG_FS |
4145 | kfree(adap->sge.blocked_fl); | |
4146 | #endif | |
636f9d37 VP |
4147 | if (ret != -ETIMEDOUT && ret != -EIO) |
4148 | t4_fw_bye(adap, adap->mbox); | |
b8ff05a9 DM |
4149 | return ret; |
4150 | } | |
4151 | ||
204dc3c0 DM |
4152 | /* EEH callbacks */ |
4153 | ||
4154 | static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, | |
4155 | pci_channel_state_t state) | |
4156 | { | |
4157 | int i; | |
4158 | struct adapter *adap = pci_get_drvdata(pdev); | |
4159 | ||
4160 | if (!adap) | |
4161 | goto out; | |
4162 | ||
4163 | rtnl_lock(); | |
4164 | adap->flags &= ~FW_OK; | |
4165 | notify_ulds(adap, CXGB4_STATE_START_RECOVERY); | |
9fe6cb58 | 4166 | spin_lock(&adap->stats_lock); |
204dc3c0 DM |
4167 | for_each_port(adap, i) { |
4168 | struct net_device *dev = adap->port[i]; | |
4169 | ||
4170 | netif_device_detach(dev); | |
4171 | netif_carrier_off(dev); | |
4172 | } | |
9fe6cb58 | 4173 | spin_unlock(&adap->stats_lock); |
b37987e8 | 4174 | disable_interrupts(adap); |
204dc3c0 DM |
4175 | if (adap->flags & FULL_INIT_DONE) |
4176 | cxgb_down(adap); | |
4177 | rtnl_unlock(); | |
144be3d9 GS |
4178 | if ((adap->flags & DEV_ENABLED)) { |
4179 | pci_disable_device(pdev); | |
4180 | adap->flags &= ~DEV_ENABLED; | |
4181 | } | |
204dc3c0 DM |
4182 | out: return state == pci_channel_io_perm_failure ? |
4183 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
4184 | } | |
4185 | ||
4186 | static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) | |
4187 | { | |
4188 | int i, ret; | |
4189 | struct fw_caps_config_cmd c; | |
4190 | struct adapter *adap = pci_get_drvdata(pdev); | |
4191 | ||
4192 | if (!adap) { | |
4193 | pci_restore_state(pdev); | |
4194 | pci_save_state(pdev); | |
4195 | return PCI_ERS_RESULT_RECOVERED; | |
4196 | } | |
4197 | ||
144be3d9 GS |
4198 | if (!(adap->flags & DEV_ENABLED)) { |
4199 | if (pci_enable_device(pdev)) { | |
4200 | dev_err(&pdev->dev, "Cannot reenable PCI " | |
4201 | "device after reset\n"); | |
4202 | return PCI_ERS_RESULT_DISCONNECT; | |
4203 | } | |
4204 | adap->flags |= DEV_ENABLED; | |
204dc3c0 DM |
4205 | } |
4206 | ||
4207 | pci_set_master(pdev); | |
4208 | pci_restore_state(pdev); | |
4209 | pci_save_state(pdev); | |
4210 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
4211 | ||
8203b509 | 4212 | if (t4_wait_dev_ready(adap->regs) < 0) |
204dc3c0 | 4213 | return PCI_ERS_RESULT_DISCONNECT; |
b2612722 | 4214 | if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) |
204dc3c0 DM |
4215 | return PCI_ERS_RESULT_DISCONNECT; |
4216 | adap->flags |= FW_OK; | |
4217 | if (adap_init1(adap, &c)) | |
4218 | return PCI_ERS_RESULT_DISCONNECT; | |
4219 | ||
4220 | for_each_port(adap, i) { | |
4221 | struct port_info *p = adap2pinfo(adap, i); | |
4222 | ||
b2612722 | 4223 | ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, |
060e0c75 | 4224 | NULL, NULL); |
204dc3c0 DM |
4225 | if (ret < 0) |
4226 | return PCI_ERS_RESULT_DISCONNECT; | |
4227 | p->viid = ret; | |
4228 | p->xact_addr_filt = -1; | |
4229 | } | |
4230 | ||
4231 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, | |
4232 | adap->params.b_wnd); | |
1ae970e0 | 4233 | setup_memwin(adap); |
204dc3c0 DM |
4234 | if (cxgb_up(adap)) |
4235 | return PCI_ERS_RESULT_DISCONNECT; | |
4236 | return PCI_ERS_RESULT_RECOVERED; | |
4237 | } | |
4238 | ||
4239 | static void eeh_resume(struct pci_dev *pdev) | |
4240 | { | |
4241 | int i; | |
4242 | struct adapter *adap = pci_get_drvdata(pdev); | |
4243 | ||
4244 | if (!adap) | |
4245 | return; | |
4246 | ||
4247 | rtnl_lock(); | |
4248 | for_each_port(adap, i) { | |
4249 | struct net_device *dev = adap->port[i]; | |
4250 | ||
4251 | if (netif_running(dev)) { | |
4252 | link_start(dev); | |
4253 | cxgb_set_rxmode(dev); | |
4254 | } | |
4255 | netif_device_attach(dev); | |
4256 | } | |
4257 | rtnl_unlock(); | |
4258 | } | |
4259 | ||
3646f0e5 | 4260 | static const struct pci_error_handlers cxgb4_eeh = { |
204dc3c0 DM |
4261 | .error_detected = eeh_err_detected, |
4262 | .slot_reset = eeh_slot_reset, | |
4263 | .resume = eeh_resume, | |
4264 | }; | |
4265 | ||
57d8b764 | 4266 | static inline bool is_x_10g_port(const struct link_config *lc) |
b8ff05a9 | 4267 | { |
57d8b764 KS |
4268 | return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 || |
4269 | (lc->supported & FW_PORT_CAP_SPEED_40G) != 0; | |
b8ff05a9 DM |
4270 | } |
4271 | ||
c887ad0e HS |
4272 | static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, |
4273 | unsigned int us, unsigned int cnt, | |
b8ff05a9 DM |
4274 | unsigned int size, unsigned int iqe_size) |
4275 | { | |
c887ad0e | 4276 | q->adap = adap; |
812034f1 | 4277 | cxgb4_set_rspq_intr_params(q, us, cnt); |
b8ff05a9 DM |
4278 | q->iqe_len = iqe_size; |
4279 | q->size = size; | |
4280 | } | |
4281 | ||
4282 | /* | |
4283 | * Perform default configuration of DMA queues depending on the number and type | |
4284 | * of ports we found and the number of available CPUs. Most settings can be | |
4285 | * modified by the admin prior to actual use. | |
4286 | */ | |
91744948 | 4287 | static void cfg_queues(struct adapter *adap) |
b8ff05a9 DM |
4288 | { |
4289 | struct sge *s = &adap->sge; | |
688848b1 AB |
4290 | int i, n10g = 0, qidx = 0; |
4291 | #ifndef CONFIG_CHELSIO_T4_DCB | |
4292 | int q10g = 0; | |
4293 | #endif | |
cf38be6d | 4294 | int ciq_size; |
b8ff05a9 DM |
4295 | |
4296 | for_each_port(adap, i) | |
57d8b764 | 4297 | n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); |
688848b1 AB |
4298 | #ifdef CONFIG_CHELSIO_T4_DCB |
4299 | /* For Data Center Bridging support we need to be able to support up | |
4300 | * to 8 Traffic Priorities; each of which will be assigned to its | |
4301 | * own TX Queue in order to prevent Head-Of-Line Blocking. | |
4302 | */ | |
4303 | if (adap->params.nports * 8 > MAX_ETH_QSETS) { | |
4304 | dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", | |
4305 | MAX_ETH_QSETS, adap->params.nports * 8); | |
4306 | BUG_ON(1); | |
4307 | } | |
b8ff05a9 | 4308 | |
688848b1 AB |
4309 | for_each_port(adap, i) { |
4310 | struct port_info *pi = adap2pinfo(adap, i); | |
4311 | ||
4312 | pi->first_qset = qidx; | |
4313 | pi->nqsets = 8; | |
4314 | qidx += pi->nqsets; | |
4315 | } | |
4316 | #else /* !CONFIG_CHELSIO_T4_DCB */ | |
b8ff05a9 DM |
4317 | /* |
4318 | * We default to 1 queue per non-10G port and up to # of cores queues | |
4319 | * per 10G port. | |
4320 | */ | |
4321 | if (n10g) | |
4322 | q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; | |
5952dde7 YM |
4323 | if (q10g > netif_get_num_default_rss_queues()) |
4324 | q10g = netif_get_num_default_rss_queues(); | |
b8ff05a9 DM |
4325 | |
4326 | for_each_port(adap, i) { | |
4327 | struct port_info *pi = adap2pinfo(adap, i); | |
4328 | ||
4329 | pi->first_qset = qidx; | |
57d8b764 | 4330 | pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; |
b8ff05a9 DM |
4331 | qidx += pi->nqsets; |
4332 | } | |
688848b1 | 4333 | #endif /* !CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 DM |
4334 | |
4335 | s->ethqsets = qidx; | |
4336 | s->max_ethqsets = qidx; /* MSI-X may lower it later */ | |
4337 | ||
4338 | if (is_offload(adap)) { | |
4339 | /* | |
4340 | * For offload we use 1 queue/channel if all ports are up to 1G, | |
4341 | * otherwise we divide all available queues amongst the channels | |
4342 | * capped by the number of available cores. | |
4343 | */ | |
4344 | if (n10g) { | |
4345 | i = min_t(int, ARRAY_SIZE(s->ofldrxq), | |
4346 | num_online_cpus()); | |
4347 | s->ofldqsets = roundup(i, adap->params.nports); | |
4348 | } else | |
4349 | s->ofldqsets = adap->params.nports; | |
4350 | /* For RDMA one Rx queue per channel suffices */ | |
4351 | s->rdmaqs = adap->params.nports; | |
f36e58e5 HS |
4352 | /* Try and allow at least 1 CIQ per cpu rounding down |
4353 | * to the number of ports, with a minimum of 1 per port. | |
4354 | * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port. | |
4355 | * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port. | |
4356 | * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port. | |
4357 | */ | |
4358 | s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus()); | |
4359 | s->rdmaciqs = (s->rdmaciqs / adap->params.nports) * | |
4360 | adap->params.nports; | |
4361 | s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports); | |
b8ff05a9 DM |
4362 | } |
4363 | ||
4364 | for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { | |
4365 | struct sge_eth_rxq *r = &s->ethrxq[i]; | |
4366 | ||
c887ad0e | 4367 | init_rspq(adap, &r->rspq, 5, 10, 1024, 64); |
b8ff05a9 DM |
4368 | r->fl.size = 72; |
4369 | } | |
4370 | ||
4371 | for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) | |
4372 | s->ethtxq[i].q.size = 1024; | |
4373 | ||
4374 | for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) | |
4375 | s->ctrlq[i].q.size = 512; | |
4376 | ||
4377 | for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) | |
4378 | s->ofldtxq[i].q.size = 1024; | |
4379 | ||
4380 | for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) { | |
4381 | struct sge_ofld_rxq *r = &s->ofldrxq[i]; | |
4382 | ||
c887ad0e | 4383 | init_rspq(adap, &r->rspq, 5, 1, 1024, 64); |
b8ff05a9 DM |
4384 | r->rspq.uld = CXGB4_ULD_ISCSI; |
4385 | r->fl.size = 72; | |
4386 | } | |
4387 | ||
4388 | for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) { | |
4389 | struct sge_ofld_rxq *r = &s->rdmarxq[i]; | |
4390 | ||
c887ad0e | 4391 | init_rspq(adap, &r->rspq, 5, 1, 511, 64); |
b8ff05a9 DM |
4392 | r->rspq.uld = CXGB4_ULD_RDMA; |
4393 | r->fl.size = 72; | |
4394 | } | |
4395 | ||
cf38be6d HS |
4396 | ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids; |
4397 | if (ciq_size > SGE_MAX_IQ_SIZE) { | |
4398 | CH_WARN(adap, "CIQ size too small for available IQs\n"); | |
4399 | ciq_size = SGE_MAX_IQ_SIZE; | |
4400 | } | |
4401 | ||
4402 | for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) { | |
4403 | struct sge_ofld_rxq *r = &s->rdmaciq[i]; | |
4404 | ||
c887ad0e | 4405 | init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64); |
cf38be6d HS |
4406 | r->rspq.uld = CXGB4_ULD_RDMA; |
4407 | } | |
4408 | ||
c887ad0e HS |
4409 | init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); |
4410 | init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64); | |
b8ff05a9 DM |
4411 | } |
4412 | ||
4413 | /* | |
4414 | * Reduce the number of Ethernet queues across all ports to at most n. | |
4415 | * n provides at least one queue per port. | |
4416 | */ | |
91744948 | 4417 | static void reduce_ethqs(struct adapter *adap, int n) |
b8ff05a9 DM |
4418 | { |
4419 | int i; | |
4420 | struct port_info *pi; | |
4421 | ||
4422 | while (n < adap->sge.ethqsets) | |
4423 | for_each_port(adap, i) { | |
4424 | pi = adap2pinfo(adap, i); | |
4425 | if (pi->nqsets > 1) { | |
4426 | pi->nqsets--; | |
4427 | adap->sge.ethqsets--; | |
4428 | if (adap->sge.ethqsets <= n) | |
4429 | break; | |
4430 | } | |
4431 | } | |
4432 | ||
4433 | n = 0; | |
4434 | for_each_port(adap, i) { | |
4435 | pi = adap2pinfo(adap, i); | |
4436 | pi->first_qset = n; | |
4437 | n += pi->nqsets; | |
4438 | } | |
4439 | } | |
4440 | ||
4441 | /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ | |
4442 | #define EXTRA_VECS 2 | |
4443 | ||
91744948 | 4444 | static int enable_msix(struct adapter *adap) |
b8ff05a9 DM |
4445 | { |
4446 | int ofld_need = 0; | |
f36e58e5 | 4447 | int i, want, need, allocated; |
b8ff05a9 DM |
4448 | struct sge *s = &adap->sge; |
4449 | unsigned int nchan = adap->params.nports; | |
f36e58e5 HS |
4450 | struct msix_entry *entries; |
4451 | ||
4452 | entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1), | |
4453 | GFP_KERNEL); | |
4454 | if (!entries) | |
4455 | return -ENOMEM; | |
b8ff05a9 | 4456 | |
f36e58e5 | 4457 | for (i = 0; i < MAX_INGQ + 1; ++i) |
b8ff05a9 DM |
4458 | entries[i].entry = i; |
4459 | ||
4460 | want = s->max_ethqsets + EXTRA_VECS; | |
4461 | if (is_offload(adap)) { | |
cf38be6d | 4462 | want += s->rdmaqs + s->rdmaciqs + s->ofldqsets; |
b8ff05a9 | 4463 | /* need nchan for each possible ULD */ |
cf38be6d | 4464 | ofld_need = 3 * nchan; |
b8ff05a9 | 4465 | } |
688848b1 AB |
4466 | #ifdef CONFIG_CHELSIO_T4_DCB |
4467 | /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for | |
4468 | * each port. | |
4469 | */ | |
4470 | need = 8 * adap->params.nports + EXTRA_VECS + ofld_need; | |
4471 | #else | |
b8ff05a9 | 4472 | need = adap->params.nports + EXTRA_VECS + ofld_need; |
688848b1 | 4473 | #endif |
f36e58e5 HS |
4474 | allocated = pci_enable_msix_range(adap->pdev, entries, need, want); |
4475 | if (allocated < 0) { | |
4476 | dev_info(adap->pdev_dev, "not enough MSI-X vectors left," | |
4477 | " not using MSI-X\n"); | |
4478 | kfree(entries); | |
4479 | return allocated; | |
4480 | } | |
b8ff05a9 | 4481 | |
f36e58e5 | 4482 | /* Distribute available vectors to the various queue groups. |
c32ad224 AG |
4483 | * Every group gets its minimum requirement and NIC gets top |
4484 | * priority for leftovers. | |
4485 | */ | |
f36e58e5 | 4486 | i = allocated - EXTRA_VECS - ofld_need; |
c32ad224 AG |
4487 | if (i < s->max_ethqsets) { |
4488 | s->max_ethqsets = i; | |
4489 | if (i < s->ethqsets) | |
4490 | reduce_ethqs(adap, i); | |
4491 | } | |
4492 | if (is_offload(adap)) { | |
f36e58e5 HS |
4493 | if (allocated < want) { |
4494 | s->rdmaqs = nchan; | |
4495 | s->rdmaciqs = nchan; | |
4496 | } | |
4497 | ||
4498 | /* leftovers go to OFLD */ | |
4499 | i = allocated - EXTRA_VECS - s->max_ethqsets - | |
4500 | s->rdmaqs - s->rdmaciqs; | |
c32ad224 AG |
4501 | s->ofldqsets = (i / nchan) * nchan; /* round down */ |
4502 | } | |
f36e58e5 | 4503 | for (i = 0; i < allocated; ++i) |
c32ad224 | 4504 | adap->msix_info[i].vec = entries[i].vector; |
43eb4e82 HS |
4505 | dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " |
4506 | "nic %d iscsi %d rdma cpl %d rdma ciq %d\n", | |
4507 | allocated, s->max_ethqsets, s->ofldqsets, s->rdmaqs, | |
4508 | s->rdmaciqs); | |
c32ad224 | 4509 | |
f36e58e5 | 4510 | kfree(entries); |
c32ad224 | 4511 | return 0; |
b8ff05a9 DM |
4512 | } |
4513 | ||
4514 | #undef EXTRA_VECS | |
4515 | ||
91744948 | 4516 | static int init_rss(struct adapter *adap) |
671b0060 | 4517 | { |
c035e183 HS |
4518 | unsigned int i; |
4519 | int err; | |
4520 | ||
4521 | err = t4_init_rss_mode(adap, adap->mbox); | |
4522 | if (err) | |
4523 | return err; | |
671b0060 DM |
4524 | |
4525 | for_each_port(adap, i) { | |
4526 | struct port_info *pi = adap2pinfo(adap, i); | |
4527 | ||
4528 | pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); | |
4529 | if (!pi->rss) | |
4530 | return -ENOMEM; | |
671b0060 DM |
4531 | } |
4532 | return 0; | |
4533 | } | |
4534 | ||
547fd272 HS |
4535 | static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap, |
4536 | enum pci_bus_speed *speed, | |
4537 | enum pcie_link_width *width) | |
4538 | { | |
4539 | u32 lnkcap1, lnkcap2; | |
4540 | int err1, err2; | |
4541 | ||
4542 | #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ | |
4543 | ||
4544 | *speed = PCI_SPEED_UNKNOWN; | |
4545 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4546 | ||
4547 | err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP, | |
4548 | &lnkcap1); | |
4549 | err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2, | |
4550 | &lnkcap2); | |
4551 | if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ | |
4552 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
4553 | *speed = PCIE_SPEED_8_0GT; | |
4554 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
4555 | *speed = PCIE_SPEED_5_0GT; | |
4556 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
4557 | *speed = PCIE_SPEED_2_5GT; | |
4558 | } | |
4559 | if (!err1) { | |
4560 | *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; | |
4561 | if (!lnkcap2) { /* pre-r3.0 */ | |
4562 | if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) | |
4563 | *speed = PCIE_SPEED_5_0GT; | |
4564 | else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) | |
4565 | *speed = PCIE_SPEED_2_5GT; | |
4566 | } | |
4567 | } | |
4568 | ||
4569 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
4570 | return err1 ? err1 : err2 ? err2 : -EINVAL; | |
4571 | return 0; | |
4572 | } | |
4573 | ||
4574 | static void cxgb4_check_pcie_caps(struct adapter *adap) | |
4575 | { | |
4576 | enum pcie_link_width width, width_cap; | |
4577 | enum pci_bus_speed speed, speed_cap; | |
4578 | ||
4579 | #define PCIE_SPEED_STR(speed) \ | |
4580 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ | |
4581 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ | |
4582 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ | |
4583 | "Unknown") | |
4584 | ||
4585 | if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) { | |
4586 | dev_warn(adap->pdev_dev, | |
4587 | "Unable to determine PCIe device BW capabilities\n"); | |
4588 | return; | |
4589 | } | |
4590 | ||
4591 | if (pcie_get_minimum_link(adap->pdev, &speed, &width) || | |
4592 | speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { | |
4593 | dev_warn(adap->pdev_dev, | |
4594 | "Unable to determine PCI Express bandwidth.\n"); | |
4595 | return; | |
4596 | } | |
4597 | ||
4598 | dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n", | |
4599 | PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); | |
4600 | dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n", | |
4601 | width, width_cap); | |
4602 | if (speed < speed_cap || width < width_cap) | |
4603 | dev_info(adap->pdev_dev, | |
4604 | "A slot with more lanes and/or higher speed is " | |
4605 | "suggested for optimal performance.\n"); | |
4606 | } | |
4607 | ||
91744948 | 4608 | static void print_port_info(const struct net_device *dev) |
b8ff05a9 | 4609 | { |
b8ff05a9 | 4610 | char buf[80]; |
118969ed | 4611 | char *bufp = buf; |
f1a051b9 | 4612 | const char *spd = ""; |
118969ed DM |
4613 | const struct port_info *pi = netdev_priv(dev); |
4614 | const struct adapter *adap = pi->adapter; | |
f1a051b9 DM |
4615 | |
4616 | if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) | |
4617 | spd = " 2.5 GT/s"; | |
4618 | else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) | |
4619 | spd = " 5 GT/s"; | |
d2e752db RD |
4620 | else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) |
4621 | spd = " 8 GT/s"; | |
b8ff05a9 | 4622 | |
118969ed DM |
4623 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) |
4624 | bufp += sprintf(bufp, "100/"); | |
4625 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) | |
4626 | bufp += sprintf(bufp, "1000/"); | |
4627 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) | |
4628 | bufp += sprintf(bufp, "10G/"); | |
72aca4bf KS |
4629 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) |
4630 | bufp += sprintf(bufp, "40G/"); | |
118969ed DM |
4631 | if (bufp != buf) |
4632 | --bufp; | |
72aca4bf | 4633 | sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); |
118969ed | 4634 | |
547fd272 | 4635 | netdev_info(dev, "Chelsio %s rev %d %s %sNIC %s\n", |
0a57a536 | 4636 | adap->params.vpd.id, |
d14807dd | 4637 | CHELSIO_CHIP_RELEASE(adap->params.chip), buf, |
547fd272 | 4638 | is_offload(adap) ? "R" : "", |
118969ed DM |
4639 | (adap->flags & USING_MSIX) ? " MSI-X" : |
4640 | (adap->flags & USING_MSI) ? " MSI" : ""); | |
a94cd705 KS |
4641 | netdev_info(dev, "S/N: %s, P/N: %s\n", |
4642 | adap->params.vpd.sn, adap->params.vpd.pn); | |
b8ff05a9 DM |
4643 | } |
4644 | ||
91744948 | 4645 | static void enable_pcie_relaxed_ordering(struct pci_dev *dev) |
ef306b50 | 4646 | { |
e5c8ae5f | 4647 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); |
ef306b50 DM |
4648 | } |
4649 | ||
06546391 DM |
4650 | /* |
4651 | * Free the following resources: | |
4652 | * - memory used for tables | |
4653 | * - MSI/MSI-X | |
4654 | * - net devices | |
4655 | * - resources FW is holding for us | |
4656 | */ | |
4657 | static void free_some_resources(struct adapter *adapter) | |
4658 | { | |
4659 | unsigned int i; | |
4660 | ||
4661 | t4_free_mem(adapter->l2t); | |
4662 | t4_free_mem(adapter->tids.tid_tab); | |
4b8e27a8 HS |
4663 | kfree(adapter->sge.egr_map); |
4664 | kfree(adapter->sge.ingr_map); | |
4665 | kfree(adapter->sge.starving_fl); | |
4666 | kfree(adapter->sge.txq_maperr); | |
5b377d11 HS |
4667 | #ifdef CONFIG_DEBUG_FS |
4668 | kfree(adapter->sge.blocked_fl); | |
4669 | #endif | |
06546391 DM |
4670 | disable_msi(adapter); |
4671 | ||
4672 | for_each_port(adapter, i) | |
671b0060 | 4673 | if (adapter->port[i]) { |
4f3a0fcf HS |
4674 | struct port_info *pi = adap2pinfo(adapter, i); |
4675 | ||
4676 | if (pi->viid != 0) | |
4677 | t4_free_vi(adapter, adapter->mbox, adapter->pf, | |
4678 | 0, pi->viid); | |
671b0060 | 4679 | kfree(adap2pinfo(adapter, i)->rss); |
06546391 | 4680 | free_netdev(adapter->port[i]); |
671b0060 | 4681 | } |
06546391 | 4682 | if (adapter->flags & FW_OK) |
b2612722 | 4683 | t4_fw_bye(adapter, adapter->pf); |
06546391 DM |
4684 | } |
4685 | ||
2ed28baa | 4686 | #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) |
35d35682 | 4687 | #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ |
b8ff05a9 | 4688 | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) |
22adfe0a | 4689 | #define SEGMENT_SIZE 128 |
b8ff05a9 | 4690 | |
d86bd29e HS |
4691 | static int get_chip_type(struct pci_dev *pdev, u32 pl_rev) |
4692 | { | |
d86bd29e HS |
4693 | u16 device_id; |
4694 | ||
4695 | /* Retrieve adapter's device ID */ | |
4696 | pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); | |
46cdc9be | 4697 | |
4698 | switch (device_id >> 12) { | |
d86bd29e | 4699 | case CHELSIO_T4: |
46cdc9be | 4700 | return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); |
d86bd29e | 4701 | case CHELSIO_T5: |
46cdc9be | 4702 | return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); |
d86bd29e | 4703 | case CHELSIO_T6: |
46cdc9be | 4704 | return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); |
d86bd29e HS |
4705 | default: |
4706 | dev_err(&pdev->dev, "Device %d is not supported\n", | |
4707 | device_id); | |
d86bd29e | 4708 | } |
46cdc9be | 4709 | return -EINVAL; |
d86bd29e HS |
4710 | } |
4711 | ||
1dd06ae8 | 4712 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
b8ff05a9 | 4713 | { |
22adfe0a | 4714 | int func, i, err, s_qpp, qpp, num_seg; |
b8ff05a9 | 4715 | struct port_info *pi; |
c8f44aff | 4716 | bool highdma = false; |
b8ff05a9 | 4717 | struct adapter *adapter = NULL; |
d6ce2628 | 4718 | void __iomem *regs; |
d86bd29e HS |
4719 | u32 whoami, pl_rev; |
4720 | enum chip_type chip; | |
b8ff05a9 DM |
4721 | |
4722 | printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); | |
4723 | ||
4724 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
4725 | if (err) { | |
4726 | /* Just info, some other driver may have claimed the device. */ | |
4727 | dev_info(&pdev->dev, "cannot obtain PCI resources\n"); | |
4728 | return err; | |
4729 | } | |
4730 | ||
b8ff05a9 DM |
4731 | err = pci_enable_device(pdev); |
4732 | if (err) { | |
4733 | dev_err(&pdev->dev, "cannot enable PCI device\n"); | |
4734 | goto out_release_regions; | |
4735 | } | |
4736 | ||
d6ce2628 HS |
4737 | regs = pci_ioremap_bar(pdev, 0); |
4738 | if (!regs) { | |
4739 | dev_err(&pdev->dev, "cannot map device registers\n"); | |
4740 | err = -ENOMEM; | |
4741 | goto out_disable_device; | |
4742 | } | |
4743 | ||
8203b509 HS |
4744 | err = t4_wait_dev_ready(regs); |
4745 | if (err < 0) | |
4746 | goto out_unmap_bar0; | |
4747 | ||
d6ce2628 | 4748 | /* We control everything through one PF */ |
d86bd29e HS |
4749 | whoami = readl(regs + PL_WHOAMI_A); |
4750 | pl_rev = REV_G(readl(regs + PL_REV_A)); | |
4751 | chip = get_chip_type(pdev, pl_rev); | |
4752 | func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? | |
4753 | SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); | |
d6ce2628 HS |
4754 | if (func != ent->driver_data) { |
4755 | iounmap(regs); | |
4756 | pci_disable_device(pdev); | |
4757 | pci_save_state(pdev); /* to restore SR-IOV later */ | |
4758 | goto sriov; | |
4759 | } | |
4760 | ||
b8ff05a9 | 4761 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
c8f44aff | 4762 | highdma = true; |
b8ff05a9 DM |
4763 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
4764 | if (err) { | |
4765 | dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " | |
4766 | "coherent allocations\n"); | |
d6ce2628 | 4767 | goto out_unmap_bar0; |
b8ff05a9 DM |
4768 | } |
4769 | } else { | |
4770 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
4771 | if (err) { | |
4772 | dev_err(&pdev->dev, "no usable DMA configuration\n"); | |
d6ce2628 | 4773 | goto out_unmap_bar0; |
b8ff05a9 DM |
4774 | } |
4775 | } | |
4776 | ||
4777 | pci_enable_pcie_error_reporting(pdev); | |
ef306b50 | 4778 | enable_pcie_relaxed_ordering(pdev); |
b8ff05a9 DM |
4779 | pci_set_master(pdev); |
4780 | pci_save_state(pdev); | |
4781 | ||
4782 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); | |
4783 | if (!adapter) { | |
4784 | err = -ENOMEM; | |
d6ce2628 | 4785 | goto out_unmap_bar0; |
b8ff05a9 DM |
4786 | } |
4787 | ||
29aaee65 AB |
4788 | adapter->workq = create_singlethread_workqueue("cxgb4"); |
4789 | if (!adapter->workq) { | |
4790 | err = -ENOMEM; | |
4791 | goto out_free_adapter; | |
4792 | } | |
4793 | ||
144be3d9 GS |
4794 | /* PCI device has been enabled */ |
4795 | adapter->flags |= DEV_ENABLED; | |
4796 | ||
d6ce2628 | 4797 | adapter->regs = regs; |
b8ff05a9 DM |
4798 | adapter->pdev = pdev; |
4799 | adapter->pdev_dev = &pdev->dev; | |
3069ee9b | 4800 | adapter->mbox = func; |
b2612722 | 4801 | adapter->pf = func; |
b8ff05a9 DM |
4802 | adapter->msg_enable = dflt_msg_enable; |
4803 | memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); | |
4804 | ||
4805 | spin_lock_init(&adapter->stats_lock); | |
4806 | spin_lock_init(&adapter->tid_release_lock); | |
e327c225 | 4807 | spin_lock_init(&adapter->win0_lock); |
b8ff05a9 DM |
4808 | |
4809 | INIT_WORK(&adapter->tid_release_task, process_tid_release_list); | |
881806bc VP |
4810 | INIT_WORK(&adapter->db_full_task, process_db_full); |
4811 | INIT_WORK(&adapter->db_drop_task, process_db_drop); | |
b8ff05a9 DM |
4812 | |
4813 | err = t4_prep_adapter(adapter); | |
4814 | if (err) | |
d6ce2628 HS |
4815 | goto out_free_adapter; |
4816 | ||
22adfe0a | 4817 | |
d14807dd | 4818 | if (!is_t4(adapter->params.chip)) { |
f612b815 HS |
4819 | s_qpp = (QUEUESPERPAGEPF0_S + |
4820 | (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * | |
b2612722 | 4821 | adapter->pf); |
f612b815 HS |
4822 | qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, |
4823 | SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); | |
22adfe0a SR |
4824 | num_seg = PAGE_SIZE / SEGMENT_SIZE; |
4825 | ||
4826 | /* Each segment size is 128B. Write coalescing is enabled only | |
4827 | * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the | |
4828 | * queue is less no of segments that can be accommodated in | |
4829 | * a page size. | |
4830 | */ | |
4831 | if (qpp > num_seg) { | |
4832 | dev_err(&pdev->dev, | |
4833 | "Incorrect number of egress queues per page\n"); | |
4834 | err = -EINVAL; | |
d6ce2628 | 4835 | goto out_free_adapter; |
22adfe0a SR |
4836 | } |
4837 | adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), | |
4838 | pci_resource_len(pdev, 2)); | |
4839 | if (!adapter->bar2) { | |
4840 | dev_err(&pdev->dev, "cannot map device bar2 region\n"); | |
4841 | err = -ENOMEM; | |
d6ce2628 | 4842 | goto out_free_adapter; |
22adfe0a SR |
4843 | } |
4844 | } | |
4845 | ||
636f9d37 | 4846 | setup_memwin(adapter); |
b8ff05a9 | 4847 | err = adap_init0(adapter); |
5b377d11 HS |
4848 | #ifdef CONFIG_DEBUG_FS |
4849 | bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); | |
4850 | #endif | |
636f9d37 | 4851 | setup_memwin_rdma(adapter); |
b8ff05a9 DM |
4852 | if (err) |
4853 | goto out_unmap_bar; | |
4854 | ||
2a485cf7 HS |
4855 | /* configure SGE_STAT_CFG_A to read WC stats */ |
4856 | if (!is_t4(adapter->params.chip)) | |
4857 | t4_write_reg(adapter, SGE_STAT_CFG_A, | |
4858 | STATSOURCE_T5_V(7) | STATMODE_V(0)); | |
4859 | ||
b8ff05a9 DM |
4860 | for_each_port(adapter, i) { |
4861 | struct net_device *netdev; | |
4862 | ||
4863 | netdev = alloc_etherdev_mq(sizeof(struct port_info), | |
4864 | MAX_ETH_QSETS); | |
4865 | if (!netdev) { | |
4866 | err = -ENOMEM; | |
4867 | goto out_free_dev; | |
4868 | } | |
4869 | ||
4870 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
4871 | ||
4872 | adapter->port[i] = netdev; | |
4873 | pi = netdev_priv(netdev); | |
4874 | pi->adapter = adapter; | |
4875 | pi->xact_addr_filt = -1; | |
b8ff05a9 | 4876 | pi->port_id = i; |
b8ff05a9 DM |
4877 | netdev->irq = pdev->irq; |
4878 | ||
2ed28baa MM |
4879 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | |
4880 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
4881 | NETIF_F_RXCSUM | NETIF_F_RXHASH | | |
f646968f | 4882 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
c8f44aff MM |
4883 | if (highdma) |
4884 | netdev->hw_features |= NETIF_F_HIGHDMA; | |
4885 | netdev->features |= netdev->hw_features; | |
b8ff05a9 DM |
4886 | netdev->vlan_features = netdev->features & VLAN_FEAT; |
4887 | ||
01789349 JP |
4888 | netdev->priv_flags |= IFF_UNICAST_FLT; |
4889 | ||
b8ff05a9 | 4890 | netdev->netdev_ops = &cxgb4_netdev_ops; |
688848b1 AB |
4891 | #ifdef CONFIG_CHELSIO_T4_DCB |
4892 | netdev->dcbnl_ops = &cxgb4_dcb_ops; | |
4893 | cxgb4_dcb_state_init(netdev); | |
4894 | #endif | |
812034f1 | 4895 | cxgb4_set_ethtool_ops(netdev); |
b8ff05a9 DM |
4896 | } |
4897 | ||
4898 | pci_set_drvdata(pdev, adapter); | |
4899 | ||
4900 | if (adapter->flags & FW_OK) { | |
060e0c75 | 4901 | err = t4_port_init(adapter, func, func, 0); |
b8ff05a9 DM |
4902 | if (err) |
4903 | goto out_free_dev; | |
098ef6c2 HS |
4904 | } else if (adapter->params.nports == 1) { |
4905 | /* If we don't have a connection to the firmware -- possibly | |
4906 | * because of an error -- grab the raw VPD parameters so we | |
4907 | * can set the proper MAC Address on the debug network | |
4908 | * interface that we've created. | |
4909 | */ | |
4910 | u8 hw_addr[ETH_ALEN]; | |
4911 | u8 *na = adapter->params.vpd.na; | |
4912 | ||
4913 | err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); | |
4914 | if (!err) { | |
4915 | for (i = 0; i < ETH_ALEN; i++) | |
4916 | hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + | |
4917 | hex2val(na[2 * i + 1])); | |
4918 | t4_set_hw_addr(adapter, 0, hw_addr); | |
4919 | } | |
b8ff05a9 DM |
4920 | } |
4921 | ||
098ef6c2 | 4922 | /* Configure queues and allocate tables now, they can be needed as |
b8ff05a9 DM |
4923 | * soon as the first register_netdev completes. |
4924 | */ | |
4925 | cfg_queues(adapter); | |
4926 | ||
5be9ed8d | 4927 | adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); |
b8ff05a9 DM |
4928 | if (!adapter->l2t) { |
4929 | /* We tolerate a lack of L2T, giving up some functionality */ | |
4930 | dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); | |
4931 | adapter->params.offload = 0; | |
4932 | } | |
4933 | ||
b5a02f50 | 4934 | #if IS_ENABLED(CONFIG_IPV6) |
eb72f74f HS |
4935 | if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) && |
4936 | (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { | |
4937 | /* CLIP functionality is not present in hardware, | |
4938 | * hence disable all offload features | |
b5a02f50 AB |
4939 | */ |
4940 | dev_warn(&pdev->dev, | |
eb72f74f | 4941 | "CLIP not enabled in hardware, continuing\n"); |
b5a02f50 | 4942 | adapter->params.offload = 0; |
eb72f74f HS |
4943 | } else { |
4944 | adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, | |
4945 | adapter->clipt_end); | |
4946 | if (!adapter->clipt) { | |
4947 | /* We tolerate a lack of clip_table, giving up | |
4948 | * some functionality | |
4949 | */ | |
4950 | dev_warn(&pdev->dev, | |
4951 | "could not allocate Clip table, continuing\n"); | |
4952 | adapter->params.offload = 0; | |
4953 | } | |
b5a02f50 AB |
4954 | } |
4955 | #endif | |
b8ff05a9 DM |
4956 | if (is_offload(adapter) && tid_init(&adapter->tids) < 0) { |
4957 | dev_warn(&pdev->dev, "could not allocate TID table, " | |
4958 | "continuing\n"); | |
4959 | adapter->params.offload = 0; | |
4960 | } | |
4961 | ||
9a1bb9f6 HS |
4962 | if (is_offload(adapter)) { |
4963 | if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { | |
4964 | u32 hash_base, hash_reg; | |
4965 | ||
4966 | if (chip <= CHELSIO_T5) { | |
4967 | hash_reg = LE_DB_TID_HASHBASE_A; | |
4968 | hash_base = t4_read_reg(adapter, hash_reg); | |
4969 | adapter->tids.hash_base = hash_base / 4; | |
4970 | } else { | |
4971 | hash_reg = T6_LE_DB_HASH_TID_BASE_A; | |
4972 | hash_base = t4_read_reg(adapter, hash_reg); | |
4973 | adapter->tids.hash_base = hash_base; | |
4974 | } | |
4975 | } | |
4976 | } | |
4977 | ||
f7cabcdd DM |
4978 | /* See what interrupts we'll be using */ |
4979 | if (msi > 1 && enable_msix(adapter) == 0) | |
4980 | adapter->flags |= USING_MSIX; | |
4981 | else if (msi > 0 && pci_enable_msi(pdev) == 0) | |
4982 | adapter->flags |= USING_MSI; | |
4983 | ||
547fd272 HS |
4984 | /* check for PCI Express bandwidth capabiltites */ |
4985 | cxgb4_check_pcie_caps(adapter); | |
4986 | ||
671b0060 DM |
4987 | err = init_rss(adapter); |
4988 | if (err) | |
4989 | goto out_free_dev; | |
4990 | ||
b8ff05a9 DM |
4991 | /* |
4992 | * The card is now ready to go. If any errors occur during device | |
4993 | * registration we do not fail the whole card but rather proceed only | |
4994 | * with the ports we manage to register successfully. However we must | |
4995 | * register at least one net device. | |
4996 | */ | |
4997 | for_each_port(adapter, i) { | |
a57cabe0 DM |
4998 | pi = adap2pinfo(adapter, i); |
4999 | netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); | |
5000 | netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); | |
5001 | ||
b8ff05a9 DM |
5002 | err = register_netdev(adapter->port[i]); |
5003 | if (err) | |
b1a3c2b6 | 5004 | break; |
b1a3c2b6 DM |
5005 | adapter->chan_map[pi->tx_chan] = i; |
5006 | print_port_info(adapter->port[i]); | |
b8ff05a9 | 5007 | } |
b1a3c2b6 | 5008 | if (i == 0) { |
b8ff05a9 DM |
5009 | dev_err(&pdev->dev, "could not register any net devices\n"); |
5010 | goto out_free_dev; | |
5011 | } | |
b1a3c2b6 DM |
5012 | if (err) { |
5013 | dev_warn(&pdev->dev, "only %d net devices registered\n", i); | |
5014 | err = 0; | |
6403eab1 | 5015 | } |
b8ff05a9 DM |
5016 | |
5017 | if (cxgb4_debugfs_root) { | |
5018 | adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), | |
5019 | cxgb4_debugfs_root); | |
5020 | setup_debugfs(adapter); | |
5021 | } | |
5022 | ||
6482aa7c DLR |
5023 | /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ |
5024 | pdev->needs_freset = 1; | |
5025 | ||
b8ff05a9 DM |
5026 | if (is_offload(adapter)) |
5027 | attach_ulds(adapter); | |
5028 | ||
8e1e6059 | 5029 | sriov: |
b8ff05a9 | 5030 | #ifdef CONFIG_PCI_IOV |
7d6727cf | 5031 | if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0) |
b8ff05a9 DM |
5032 | if (pci_enable_sriov(pdev, num_vf[func]) == 0) |
5033 | dev_info(&pdev->dev, | |
5034 | "instantiated %u virtual functions\n", | |
5035 | num_vf[func]); | |
5036 | #endif | |
5037 | return 0; | |
5038 | ||
5039 | out_free_dev: | |
06546391 | 5040 | free_some_resources(adapter); |
b8ff05a9 | 5041 | out_unmap_bar: |
d14807dd | 5042 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5043 | iounmap(adapter->bar2); |
b8ff05a9 | 5044 | out_free_adapter: |
29aaee65 AB |
5045 | if (adapter->workq) |
5046 | destroy_workqueue(adapter->workq); | |
5047 | ||
b8ff05a9 | 5048 | kfree(adapter); |
d6ce2628 HS |
5049 | out_unmap_bar0: |
5050 | iounmap(regs); | |
b8ff05a9 DM |
5051 | out_disable_device: |
5052 | pci_disable_pcie_error_reporting(pdev); | |
5053 | pci_disable_device(pdev); | |
5054 | out_release_regions: | |
5055 | pci_release_regions(pdev); | |
b8ff05a9 DM |
5056 | return err; |
5057 | } | |
5058 | ||
91744948 | 5059 | static void remove_one(struct pci_dev *pdev) |
b8ff05a9 DM |
5060 | { |
5061 | struct adapter *adapter = pci_get_drvdata(pdev); | |
5062 | ||
636f9d37 | 5063 | #ifdef CONFIG_PCI_IOV |
b8ff05a9 DM |
5064 | pci_disable_sriov(pdev); |
5065 | ||
636f9d37 VP |
5066 | #endif |
5067 | ||
b8ff05a9 DM |
5068 | if (adapter) { |
5069 | int i; | |
5070 | ||
29aaee65 AB |
5071 | /* Tear down per-adapter Work Queue first since it can contain |
5072 | * references to our adapter data structure. | |
5073 | */ | |
5074 | destroy_workqueue(adapter->workq); | |
5075 | ||
b8ff05a9 DM |
5076 | if (is_offload(adapter)) |
5077 | detach_ulds(adapter); | |
5078 | ||
b37987e8 HS |
5079 | disable_interrupts(adapter); |
5080 | ||
b8ff05a9 | 5081 | for_each_port(adapter, i) |
8f3a7676 | 5082 | if (adapter->port[i]->reg_state == NETREG_REGISTERED) |
b8ff05a9 DM |
5083 | unregister_netdev(adapter->port[i]); |
5084 | ||
9f16dc2e | 5085 | debugfs_remove_recursive(adapter->debugfs_root); |
b8ff05a9 | 5086 | |
f2b7e78d VP |
5087 | /* If we allocated filters, free up state associated with any |
5088 | * valid filters ... | |
5089 | */ | |
5090 | if (adapter->tids.ftid_tab) { | |
5091 | struct filter_entry *f = &adapter->tids.ftid_tab[0]; | |
dca4faeb VP |
5092 | for (i = 0; i < (adapter->tids.nftids + |
5093 | adapter->tids.nsftids); i++, f++) | |
f2b7e78d VP |
5094 | if (f->valid) |
5095 | clear_filter(adapter, f); | |
5096 | } | |
5097 | ||
aaefae9b DM |
5098 | if (adapter->flags & FULL_INIT_DONE) |
5099 | cxgb_down(adapter); | |
b8ff05a9 | 5100 | |
06546391 | 5101 | free_some_resources(adapter); |
b5a02f50 AB |
5102 | #if IS_ENABLED(CONFIG_IPV6) |
5103 | t4_cleanup_clip_tbl(adapter); | |
5104 | #endif | |
b8ff05a9 | 5105 | iounmap(adapter->regs); |
d14807dd | 5106 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5107 | iounmap(adapter->bar2); |
b8ff05a9 | 5108 | pci_disable_pcie_error_reporting(pdev); |
144be3d9 GS |
5109 | if ((adapter->flags & DEV_ENABLED)) { |
5110 | pci_disable_device(pdev); | |
5111 | adapter->flags &= ~DEV_ENABLED; | |
5112 | } | |
b8ff05a9 | 5113 | pci_release_regions(pdev); |
ee9a33b2 | 5114 | synchronize_rcu(); |
8b662fe7 | 5115 | kfree(adapter); |
a069ec91 | 5116 | } else |
b8ff05a9 DM |
5117 | pci_release_regions(pdev); |
5118 | } | |
5119 | ||
5120 | static struct pci_driver cxgb4_driver = { | |
5121 | .name = KBUILD_MODNAME, | |
5122 | .id_table = cxgb4_pci_tbl, | |
5123 | .probe = init_one, | |
91744948 | 5124 | .remove = remove_one, |
687d705c | 5125 | .shutdown = remove_one, |
204dc3c0 | 5126 | .err_handler = &cxgb4_eeh, |
b8ff05a9 DM |
5127 | }; |
5128 | ||
5129 | static int __init cxgb4_init_module(void) | |
5130 | { | |
5131 | int ret; | |
5132 | ||
5133 | /* Debugfs support is optional, just warn if this fails */ | |
5134 | cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); | |
5135 | if (!cxgb4_debugfs_root) | |
428ac43f | 5136 | pr_warn("could not create debugfs entry, continuing\n"); |
b8ff05a9 DM |
5137 | |
5138 | ret = pci_register_driver(&cxgb4_driver); | |
29aaee65 | 5139 | if (ret < 0) |
b8ff05a9 | 5140 | debugfs_remove(cxgb4_debugfs_root); |
01bcca68 | 5141 | |
1bb60376 | 5142 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
5143 | if (!inet6addr_registered) { |
5144 | register_inet6addr_notifier(&cxgb4_inet6addr_notifier); | |
5145 | inet6addr_registered = true; | |
5146 | } | |
1bb60376 | 5147 | #endif |
01bcca68 | 5148 | |
b8ff05a9 DM |
5149 | return ret; |
5150 | } | |
5151 | ||
5152 | static void __exit cxgb4_cleanup_module(void) | |
5153 | { | |
1bb60376 | 5154 | #if IS_ENABLED(CONFIG_IPV6) |
1793c798 | 5155 | if (inet6addr_registered) { |
b5a02f50 AB |
5156 | unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); |
5157 | inet6addr_registered = false; | |
5158 | } | |
1bb60376 | 5159 | #endif |
b8ff05a9 DM |
5160 | pci_unregister_driver(&cxgb4_driver); |
5161 | debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ | |
5162 | } | |
5163 | ||
5164 | module_init(cxgb4_init_module); | |
5165 | module_exit(cxgb4_cleanup_module); |