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56d36be4 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
56d36be4 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
56d36be4 DM |
35 | #include <linux/delay.h> |
36 | #include "cxgb4.h" | |
37 | #include "t4_regs.h" | |
f612b815 | 38 | #include "t4_values.h" |
56d36be4 DM |
39 | #include "t4fw_api.h" |
40 | ||
41 | /** | |
42 | * t4_wait_op_done_val - wait until an operation is completed | |
43 | * @adapter: the adapter performing the operation | |
44 | * @reg: the register to check for completion | |
45 | * @mask: a single-bit field within @reg that indicates completion | |
46 | * @polarity: the value of the field when the operation is completed | |
47 | * @attempts: number of check iterations | |
48 | * @delay: delay in usecs between iterations | |
49 | * @valp: where to store the value of the register at completion time | |
50 | * | |
51 | * Wait until an operation is completed by checking a bit in a register | |
52 | * up to @attempts times. If @valp is not NULL the value of the register | |
53 | * at the time it indicated completion is stored there. Returns 0 if the | |
54 | * operation completes and -EAGAIN otherwise. | |
55 | */ | |
de498c89 RD |
56 | static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, |
57 | int polarity, int attempts, int delay, u32 *valp) | |
56d36be4 DM |
58 | { |
59 | while (1) { | |
60 | u32 val = t4_read_reg(adapter, reg); | |
61 | ||
62 | if (!!(val & mask) == polarity) { | |
63 | if (valp) | |
64 | *valp = val; | |
65 | return 0; | |
66 | } | |
67 | if (--attempts == 0) | |
68 | return -EAGAIN; | |
69 | if (delay) | |
70 | udelay(delay); | |
71 | } | |
72 | } | |
73 | ||
74 | static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, | |
75 | int polarity, int attempts, int delay) | |
76 | { | |
77 | return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, | |
78 | delay, NULL); | |
79 | } | |
80 | ||
81 | /** | |
82 | * t4_set_reg_field - set a register field to a value | |
83 | * @adapter: the adapter to program | |
84 | * @addr: the register address | |
85 | * @mask: specifies the portion of the register to modify | |
86 | * @val: the new value for the register field | |
87 | * | |
88 | * Sets a register field specified by the supplied mask to the | |
89 | * given value. | |
90 | */ | |
91 | void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, | |
92 | u32 val) | |
93 | { | |
94 | u32 v = t4_read_reg(adapter, addr) & ~mask; | |
95 | ||
96 | t4_write_reg(adapter, addr, v | val); | |
97 | (void) t4_read_reg(adapter, addr); /* flush */ | |
98 | } | |
99 | ||
100 | /** | |
101 | * t4_read_indirect - read indirectly addressed registers | |
102 | * @adap: the adapter | |
103 | * @addr_reg: register holding the indirect address | |
104 | * @data_reg: register holding the value of the indirect register | |
105 | * @vals: where the read register values are stored | |
106 | * @nregs: how many indirect registers to read | |
107 | * @start_idx: index of first indirect register to read | |
108 | * | |
109 | * Reads registers that are accessed indirectly through an address/data | |
110 | * register pair. | |
111 | */ | |
f2b7e78d | 112 | void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, |
de498c89 RD |
113 | unsigned int data_reg, u32 *vals, |
114 | unsigned int nregs, unsigned int start_idx) | |
56d36be4 DM |
115 | { |
116 | while (nregs--) { | |
117 | t4_write_reg(adap, addr_reg, start_idx); | |
118 | *vals++ = t4_read_reg(adap, data_reg); | |
119 | start_idx++; | |
120 | } | |
121 | } | |
122 | ||
13ee15d3 VP |
123 | /** |
124 | * t4_write_indirect - write indirectly addressed registers | |
125 | * @adap: the adapter | |
126 | * @addr_reg: register holding the indirect addresses | |
127 | * @data_reg: register holding the value for the indirect registers | |
128 | * @vals: values to write | |
129 | * @nregs: how many indirect registers to write | |
130 | * @start_idx: address of first indirect register to write | |
131 | * | |
132 | * Writes a sequential block of registers that are accessed indirectly | |
133 | * through an address/data register pair. | |
134 | */ | |
135 | void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, | |
136 | unsigned int data_reg, const u32 *vals, | |
137 | unsigned int nregs, unsigned int start_idx) | |
138 | { | |
139 | while (nregs--) { | |
140 | t4_write_reg(adap, addr_reg, start_idx++); | |
141 | t4_write_reg(adap, data_reg, *vals++); | |
142 | } | |
143 | } | |
144 | ||
0abfd152 HS |
145 | /* |
146 | * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor | |
147 | * mechanism. This guarantees that we get the real value even if we're | |
148 | * operating within a Virtual Machine and the Hypervisor is trapping our | |
149 | * Configuration Space accesses. | |
150 | */ | |
151 | void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) | |
152 | { | |
f061de42 | 153 | u32 req = ENABLE_F | FUNCTION_V(adap->fn) | REGISTER_V(reg); |
0abfd152 HS |
154 | |
155 | if (is_t4(adap->params.chip)) | |
f061de42 | 156 | req |= LOCALCFG_F; |
0abfd152 | 157 | |
f061de42 HS |
158 | t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req); |
159 | *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); | |
0abfd152 HS |
160 | |
161 | /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a | |
162 | * Configuration Space read. (None of the other fields matter when | |
163 | * ENABLE is 0 so a simple register write is easier than a | |
164 | * read-modify-write via t4_set_reg_field().) | |
165 | */ | |
f061de42 | 166 | t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); |
0abfd152 HS |
167 | } |
168 | ||
31d55c2d HS |
169 | /* |
170 | * t4_report_fw_error - report firmware error | |
171 | * @adap: the adapter | |
172 | * | |
173 | * The adapter firmware can indicate error conditions to the host. | |
174 | * If the firmware has indicated an error, print out the reason for | |
175 | * the firmware error. | |
176 | */ | |
177 | static void t4_report_fw_error(struct adapter *adap) | |
178 | { | |
179 | static const char *const reason[] = { | |
180 | "Crash", /* PCIE_FW_EVAL_CRASH */ | |
181 | "During Device Preparation", /* PCIE_FW_EVAL_PREP */ | |
182 | "During Device Configuration", /* PCIE_FW_EVAL_CONF */ | |
183 | "During Device Initialization", /* PCIE_FW_EVAL_INIT */ | |
184 | "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ | |
185 | "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ | |
186 | "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ | |
187 | "Reserved", /* reserved */ | |
188 | }; | |
189 | u32 pcie_fw; | |
190 | ||
f061de42 HS |
191 | pcie_fw = t4_read_reg(adap, PCIE_FW_A); |
192 | if (pcie_fw & PCIE_FW_ERR_F) | |
31d55c2d | 193 | dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", |
b2e1a3f0 | 194 | reason[PCIE_FW_EVAL_G(pcie_fw)]); |
31d55c2d HS |
195 | } |
196 | ||
56d36be4 DM |
197 | /* |
198 | * Get the reply to a mailbox command and store it in @rpl in big-endian order. | |
199 | */ | |
200 | static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, | |
201 | u32 mbox_addr) | |
202 | { | |
203 | for ( ; nflit; nflit--, mbox_addr += 8) | |
204 | *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); | |
205 | } | |
206 | ||
207 | /* | |
208 | * Handle a FW assertion reported in a mailbox. | |
209 | */ | |
210 | static void fw_asrt(struct adapter *adap, u32 mbox_addr) | |
211 | { | |
212 | struct fw_debug_cmd asrt; | |
213 | ||
214 | get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); | |
215 | dev_alert(adap->pdev_dev, | |
216 | "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", | |
217 | asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line), | |
218 | ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y)); | |
219 | } | |
220 | ||
221 | static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg) | |
222 | { | |
223 | dev_err(adap->pdev_dev, | |
224 | "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, | |
225 | (unsigned long long)t4_read_reg64(adap, data_reg), | |
226 | (unsigned long long)t4_read_reg64(adap, data_reg + 8), | |
227 | (unsigned long long)t4_read_reg64(adap, data_reg + 16), | |
228 | (unsigned long long)t4_read_reg64(adap, data_reg + 24), | |
229 | (unsigned long long)t4_read_reg64(adap, data_reg + 32), | |
230 | (unsigned long long)t4_read_reg64(adap, data_reg + 40), | |
231 | (unsigned long long)t4_read_reg64(adap, data_reg + 48), | |
232 | (unsigned long long)t4_read_reg64(adap, data_reg + 56)); | |
233 | } | |
234 | ||
235 | /** | |
236 | * t4_wr_mbox_meat - send a command to FW through the given mailbox | |
237 | * @adap: the adapter | |
238 | * @mbox: index of the mailbox to use | |
239 | * @cmd: the command to write | |
240 | * @size: command length in bytes | |
241 | * @rpl: where to optionally store the reply | |
242 | * @sleep_ok: if true we may sleep while awaiting command completion | |
243 | * | |
244 | * Sends the given command to FW through the selected mailbox and waits | |
245 | * for the FW to execute the command. If @rpl is not %NULL it is used to | |
246 | * store the FW's reply to the command. The command and its optional | |
247 | * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms | |
248 | * to respond. @sleep_ok determines whether we may sleep while awaiting | |
249 | * the response. If sleeping is allowed we use progressive backoff | |
250 | * otherwise we spin. | |
251 | * | |
252 | * The return value is 0 on success or a negative errno on failure. A | |
253 | * failure can happen either because we are not able to execute the | |
254 | * command or FW executes it but signals an error. In the latter case | |
255 | * the return value is the error code indicated by FW (negated). | |
256 | */ | |
257 | int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, | |
258 | void *rpl, bool sleep_ok) | |
259 | { | |
005b5717 | 260 | static const int delay[] = { |
56d36be4 DM |
261 | 1, 1, 3, 5, 10, 10, 20, 50, 100, 200 |
262 | }; | |
263 | ||
264 | u32 v; | |
265 | u64 res; | |
266 | int i, ms, delay_idx; | |
267 | const __be64 *p = cmd; | |
89c3a86c HS |
268 | u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); |
269 | u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A); | |
56d36be4 DM |
270 | |
271 | if ((size & 15) || size > MBOX_LEN) | |
272 | return -EINVAL; | |
273 | ||
204dc3c0 DM |
274 | /* |
275 | * If the device is off-line, as in EEH, commands will time out. | |
276 | * Fail them early so we don't waste time waiting. | |
277 | */ | |
278 | if (adap->pdev->error_state != pci_channel_io_normal) | |
279 | return -EIO; | |
280 | ||
89c3a86c | 281 | v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); |
56d36be4 | 282 | for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++) |
89c3a86c | 283 | v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); |
56d36be4 DM |
284 | |
285 | if (v != MBOX_OWNER_DRV) | |
286 | return v ? -EBUSY : -ETIMEDOUT; | |
287 | ||
288 | for (i = 0; i < size; i += 8) | |
289 | t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); | |
290 | ||
89c3a86c | 291 | t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); |
56d36be4 DM |
292 | t4_read_reg(adap, ctl_reg); /* flush write */ |
293 | ||
294 | delay_idx = 0; | |
295 | ms = delay[0]; | |
296 | ||
297 | for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) { | |
298 | if (sleep_ok) { | |
299 | ms = delay[delay_idx]; /* last element may repeat */ | |
300 | if (delay_idx < ARRAY_SIZE(delay) - 1) | |
301 | delay_idx++; | |
302 | msleep(ms); | |
303 | } else | |
304 | mdelay(ms); | |
305 | ||
306 | v = t4_read_reg(adap, ctl_reg); | |
89c3a86c HS |
307 | if (MBOWNER_G(v) == MBOX_OWNER_DRV) { |
308 | if (!(v & MBMSGVALID_F)) { | |
56d36be4 DM |
309 | t4_write_reg(adap, ctl_reg, 0); |
310 | continue; | |
311 | } | |
312 | ||
313 | res = t4_read_reg64(adap, data_reg); | |
e2ac9628 | 314 | if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) { |
56d36be4 | 315 | fw_asrt(adap, data_reg); |
e2ac9628 HS |
316 | res = FW_CMD_RETVAL_V(EIO); |
317 | } else if (rpl) { | |
56d36be4 | 318 | get_mbox_rpl(adap, rpl, size / 8, data_reg); |
e2ac9628 | 319 | } |
56d36be4 | 320 | |
e2ac9628 | 321 | if (FW_CMD_RETVAL_G((int)res)) |
56d36be4 DM |
322 | dump_mbox(adap, mbox, data_reg); |
323 | t4_write_reg(adap, ctl_reg, 0); | |
e2ac9628 | 324 | return -FW_CMD_RETVAL_G((int)res); |
56d36be4 DM |
325 | } |
326 | } | |
327 | ||
328 | dump_mbox(adap, mbox, data_reg); | |
329 | dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", | |
330 | *(const u8 *)cmd, mbox); | |
31d55c2d | 331 | t4_report_fw_error(adap); |
56d36be4 DM |
332 | return -ETIMEDOUT; |
333 | } | |
334 | ||
335 | /** | |
336 | * t4_mc_read - read from MC through backdoor accesses | |
337 | * @adap: the adapter | |
338 | * @addr: address of first byte requested | |
19dd37ba | 339 | * @idx: which MC to access |
56d36be4 DM |
340 | * @data: 64 bytes of data containing the requested address |
341 | * @ecc: where to store the corresponding 64-bit ECC word | |
342 | * | |
343 | * Read 64 bytes of data from MC starting at a 64-byte-aligned address | |
344 | * that covers the requested address @addr. If @parity is not %NULL it | |
345 | * is assigned the 64-bit ECC word for the read data. | |
346 | */ | |
19dd37ba | 347 | int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) |
56d36be4 DM |
348 | { |
349 | int i; | |
19dd37ba SR |
350 | u32 mc_bist_cmd, mc_bist_cmd_addr, mc_bist_cmd_len; |
351 | u32 mc_bist_status_rdata, mc_bist_data_pattern; | |
56d36be4 | 352 | |
d14807dd | 353 | if (is_t4(adap->params.chip)) { |
89c3a86c HS |
354 | mc_bist_cmd = MC_BIST_CMD_A; |
355 | mc_bist_cmd_addr = MC_BIST_CMD_ADDR_A; | |
356 | mc_bist_cmd_len = MC_BIST_CMD_LEN_A; | |
357 | mc_bist_status_rdata = MC_BIST_STATUS_RDATA_A; | |
358 | mc_bist_data_pattern = MC_BIST_DATA_PATTERN_A; | |
19dd37ba | 359 | } else { |
89c3a86c HS |
360 | mc_bist_cmd = MC_REG(MC_P_BIST_CMD_A, idx); |
361 | mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR_A, idx); | |
362 | mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN_A, idx); | |
363 | mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA_A, idx); | |
364 | mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx); | |
19dd37ba SR |
365 | } |
366 | ||
89c3a86c | 367 | if (t4_read_reg(adap, mc_bist_cmd) & START_BIST_F) |
56d36be4 | 368 | return -EBUSY; |
19dd37ba SR |
369 | t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU); |
370 | t4_write_reg(adap, mc_bist_cmd_len, 64); | |
371 | t4_write_reg(adap, mc_bist_data_pattern, 0xc); | |
89c3a86c HS |
372 | t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE_V(1) | START_BIST_F | |
373 | BIST_CMD_GAP_V(1)); | |
374 | i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST_F, 0, 10, 1); | |
56d36be4 DM |
375 | if (i) |
376 | return i; | |
377 | ||
19dd37ba | 378 | #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i) |
56d36be4 DM |
379 | |
380 | for (i = 15; i >= 0; i--) | |
381 | *data++ = htonl(t4_read_reg(adap, MC_DATA(i))); | |
382 | if (ecc) | |
383 | *ecc = t4_read_reg64(adap, MC_DATA(16)); | |
384 | #undef MC_DATA | |
385 | return 0; | |
386 | } | |
387 | ||
388 | /** | |
389 | * t4_edc_read - read from EDC through backdoor accesses | |
390 | * @adap: the adapter | |
391 | * @idx: which EDC to access | |
392 | * @addr: address of first byte requested | |
393 | * @data: 64 bytes of data containing the requested address | |
394 | * @ecc: where to store the corresponding 64-bit ECC word | |
395 | * | |
396 | * Read 64 bytes of data from EDC starting at a 64-byte-aligned address | |
397 | * that covers the requested address @addr. If @parity is not %NULL it | |
398 | * is assigned the 64-bit ECC word for the read data. | |
399 | */ | |
400 | int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) | |
401 | { | |
402 | int i; | |
19dd37ba SR |
403 | u32 edc_bist_cmd, edc_bist_cmd_addr, edc_bist_cmd_len; |
404 | u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata; | |
56d36be4 | 405 | |
d14807dd | 406 | if (is_t4(adap->params.chip)) { |
89c3a86c HS |
407 | edc_bist_cmd = EDC_REG(EDC_BIST_CMD_A, idx); |
408 | edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR_A, idx); | |
409 | edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN_A, idx); | |
410 | edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN_A, | |
19dd37ba | 411 | idx); |
89c3a86c HS |
412 | edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA_A, |
413 | idx); | |
19dd37ba | 414 | } else { |
89c3a86c HS |
415 | edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD_A, idx); |
416 | edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx); | |
417 | edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx); | |
19dd37ba | 418 | edc_bist_cmd_data_pattern = |
89c3a86c | 419 | EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx); |
19dd37ba | 420 | edc_bist_status_rdata = |
89c3a86c | 421 | EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A, idx); |
19dd37ba SR |
422 | } |
423 | ||
89c3a86c | 424 | if (t4_read_reg(adap, edc_bist_cmd) & START_BIST_F) |
56d36be4 | 425 | return -EBUSY; |
19dd37ba SR |
426 | t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU); |
427 | t4_write_reg(adap, edc_bist_cmd_len, 64); | |
428 | t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); | |
429 | t4_write_reg(adap, edc_bist_cmd, | |
89c3a86c HS |
430 | BIST_OPCODE_V(1) | BIST_CMD_GAP_V(1) | START_BIST_F); |
431 | i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST_F, 0, 10, 1); | |
56d36be4 DM |
432 | if (i) |
433 | return i; | |
434 | ||
19dd37ba | 435 | #define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i)) |
56d36be4 DM |
436 | |
437 | for (i = 15; i >= 0; i--) | |
438 | *data++ = htonl(t4_read_reg(adap, EDC_DATA(i))); | |
439 | if (ecc) | |
440 | *ecc = t4_read_reg64(adap, EDC_DATA(16)); | |
441 | #undef EDC_DATA | |
442 | return 0; | |
443 | } | |
444 | ||
5afc8b84 VP |
445 | /** |
446 | * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window | |
447 | * @adap: the adapter | |
fc5ab020 | 448 | * @win: PCI-E Memory Window to use |
5afc8b84 VP |
449 | * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC |
450 | * @addr: address within indicated memory type | |
451 | * @len: amount of memory to transfer | |
452 | * @buf: host memory buffer | |
fc5ab020 | 453 | * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0) |
5afc8b84 VP |
454 | * |
455 | * Reads/writes an [almost] arbitrary memory region in the firmware: the | |
fc5ab020 HS |
456 | * firmware memory address and host buffer must be aligned on 32-bit |
457 | * boudaries; the length may be arbitrary. The memory is transferred as | |
458 | * a raw byte sequence from/to the firmware's memory. If this memory | |
459 | * contains data structures which contain multi-byte integers, it's the | |
460 | * caller's responsibility to perform appropriate byte order conversions. | |
5afc8b84 | 461 | */ |
fc5ab020 HS |
462 | int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, |
463 | u32 len, __be32 *buf, int dir) | |
5afc8b84 | 464 | { |
fc5ab020 HS |
465 | u32 pos, offset, resid, memoffset; |
466 | u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base; | |
5afc8b84 | 467 | |
fc5ab020 | 468 | /* Argument sanity checks ... |
5afc8b84 | 469 | */ |
fc5ab020 | 470 | if (addr & 0x3) |
5afc8b84 VP |
471 | return -EINVAL; |
472 | ||
fc5ab020 HS |
473 | /* It's convenient to be able to handle lengths which aren't a |
474 | * multiple of 32-bits because we often end up transferring files to | |
475 | * the firmware. So we'll handle that by normalizing the length here | |
476 | * and then handling any residual transfer at the end. | |
477 | */ | |
478 | resid = len & 0x3; | |
479 | len -= resid; | |
8c357ebd | 480 | |
19dd37ba | 481 | /* Offset into the region of memory which is being accessed |
5afc8b84 VP |
482 | * MEM_EDC0 = 0 |
483 | * MEM_EDC1 = 1 | |
19dd37ba SR |
484 | * MEM_MC = 2 -- T4 |
485 | * MEM_MC0 = 2 -- For T5 | |
486 | * MEM_MC1 = 3 -- For T5 | |
5afc8b84 | 487 | */ |
6559a7e8 | 488 | edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); |
19dd37ba SR |
489 | if (mtype != MEM_MC1) |
490 | memoffset = (mtype * (edc_size * 1024 * 1024)); | |
491 | else { | |
6559a7e8 HS |
492 | mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, |
493 | MA_EXT_MEMORY1_BAR_A)); | |
19dd37ba SR |
494 | memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; |
495 | } | |
5afc8b84 VP |
496 | |
497 | /* Determine the PCIE_MEM_ACCESS_OFFSET */ | |
498 | addr = addr + memoffset; | |
499 | ||
fc5ab020 HS |
500 | /* Each PCI-E Memory Window is programmed with a window size -- or |
501 | * "aperture" -- which controls the granularity of its mapping onto | |
502 | * adapter memory. We need to grab that aperture in order to know | |
503 | * how to use the specified window. The window is also programmed | |
504 | * with the base address of the Memory Window in BAR0's address | |
505 | * space. For T4 this is an absolute PCI-E Bus Address. For T5 | |
506 | * the address is relative to BAR0. | |
5afc8b84 | 507 | */ |
fc5ab020 | 508 | mem_reg = t4_read_reg(adap, |
f061de42 | 509 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, |
fc5ab020 | 510 | win)); |
f061de42 HS |
511 | mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X); |
512 | mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X; | |
fc5ab020 HS |
513 | if (is_t4(adap->params.chip)) |
514 | mem_base -= adap->t4_bar0; | |
f061de42 | 515 | win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn); |
5afc8b84 | 516 | |
fc5ab020 HS |
517 | /* Calculate our initial PCI-E Memory Window Position and Offset into |
518 | * that Window. | |
519 | */ | |
520 | pos = addr & ~(mem_aperture-1); | |
521 | offset = addr - pos; | |
5afc8b84 | 522 | |
fc5ab020 HS |
523 | /* Set up initial PCI-E Memory Window to cover the start of our |
524 | * transfer. (Read it back to ensure that changes propagate before we | |
525 | * attempt to use the new value.) | |
526 | */ | |
527 | t4_write_reg(adap, | |
f061de42 | 528 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win), |
fc5ab020 HS |
529 | pos | win_pf); |
530 | t4_read_reg(adap, | |
f061de42 | 531 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win)); |
fc5ab020 HS |
532 | |
533 | /* Transfer data to/from the adapter as long as there's an integral | |
534 | * number of 32-bit transfers to complete. | |
535 | */ | |
536 | while (len > 0) { | |
537 | if (dir == T4_MEMORY_READ) | |
538 | *buf++ = (__force __be32) t4_read_reg(adap, | |
539 | mem_base + offset); | |
540 | else | |
541 | t4_write_reg(adap, mem_base + offset, | |
542 | (__force u32) *buf++); | |
543 | offset += sizeof(__be32); | |
544 | len -= sizeof(__be32); | |
545 | ||
546 | /* If we've reached the end of our current window aperture, | |
547 | * move the PCI-E Memory Window on to the next. Note that | |
548 | * doing this here after "len" may be 0 allows us to set up | |
549 | * the PCI-E Memory Window for a possible final residual | |
550 | * transfer below ... | |
5afc8b84 | 551 | */ |
fc5ab020 HS |
552 | if (offset == mem_aperture) { |
553 | pos += mem_aperture; | |
554 | offset = 0; | |
555 | t4_write_reg(adap, | |
f061de42 HS |
556 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, |
557 | win), pos | win_pf); | |
fc5ab020 | 558 | t4_read_reg(adap, |
f061de42 HS |
559 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, |
560 | win)); | |
5afc8b84 | 561 | } |
5afc8b84 VP |
562 | } |
563 | ||
fc5ab020 HS |
564 | /* If the original transfer had a length which wasn't a multiple of |
565 | * 32-bits, now's where we need to finish off the transfer of the | |
566 | * residual amount. The PCI-E Memory Window has already been moved | |
567 | * above (if necessary) to cover this final transfer. | |
568 | */ | |
569 | if (resid) { | |
570 | union { | |
571 | __be32 word; | |
572 | char byte[4]; | |
573 | } last; | |
574 | unsigned char *bp; | |
575 | int i; | |
576 | ||
c81576c2 | 577 | if (dir == T4_MEMORY_READ) { |
fc5ab020 HS |
578 | last.word = (__force __be32) t4_read_reg(adap, |
579 | mem_base + offset); | |
580 | for (bp = (unsigned char *)buf, i = resid; i < 4; i++) | |
581 | bp[i] = last.byte[i]; | |
582 | } else { | |
583 | last.word = *buf; | |
584 | for (i = resid; i < 4; i++) | |
585 | last.byte[i] = 0; | |
586 | t4_write_reg(adap, mem_base + offset, | |
587 | (__force u32) last.word); | |
588 | } | |
589 | } | |
5afc8b84 | 590 | |
fc5ab020 | 591 | return 0; |
5afc8b84 VP |
592 | } |
593 | ||
56d36be4 | 594 | #define EEPROM_STAT_ADDR 0x7bfc |
47ce9c48 SR |
595 | #define VPD_BASE 0x400 |
596 | #define VPD_BASE_OLD 0 | |
0a57a536 | 597 | #define VPD_LEN 1024 |
63a92fe6 | 598 | #define CHELSIO_VPD_UNIQUE_ID 0x82 |
56d36be4 DM |
599 | |
600 | /** | |
601 | * t4_seeprom_wp - enable/disable EEPROM write protection | |
602 | * @adapter: the adapter | |
603 | * @enable: whether to enable or disable write protection | |
604 | * | |
605 | * Enables or disables write protection on the serial EEPROM. | |
606 | */ | |
607 | int t4_seeprom_wp(struct adapter *adapter, bool enable) | |
608 | { | |
609 | unsigned int v = enable ? 0xc : 0; | |
610 | int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v); | |
611 | return ret < 0 ? ret : 0; | |
612 | } | |
613 | ||
614 | /** | |
615 | * get_vpd_params - read VPD parameters from VPD EEPROM | |
616 | * @adapter: adapter to read | |
617 | * @p: where to store the parameters | |
618 | * | |
619 | * Reads card parameters stored in VPD EEPROM. | |
620 | */ | |
636f9d37 | 621 | int get_vpd_params(struct adapter *adapter, struct vpd_params *p) |
56d36be4 | 622 | { |
636f9d37 | 623 | u32 cclk_param, cclk_val; |
47ce9c48 | 624 | int i, ret, addr; |
a94cd705 | 625 | int ec, sn, pn; |
8c357ebd | 626 | u8 *vpd, csum; |
23d88e1d | 627 | unsigned int vpdr_len, kw_offset, id_len; |
56d36be4 | 628 | |
8c357ebd VP |
629 | vpd = vmalloc(VPD_LEN); |
630 | if (!vpd) | |
631 | return -ENOMEM; | |
632 | ||
47ce9c48 SR |
633 | ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd); |
634 | if (ret < 0) | |
635 | goto out; | |
63a92fe6 HS |
636 | |
637 | /* The VPD shall have a unique identifier specified by the PCI SIG. | |
638 | * For chelsio adapters, the identifier is 0x82. The first byte of a VPD | |
639 | * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software | |
640 | * is expected to automatically put this entry at the | |
641 | * beginning of the VPD. | |
642 | */ | |
643 | addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; | |
47ce9c48 SR |
644 | |
645 | ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd); | |
56d36be4 | 646 | if (ret < 0) |
8c357ebd | 647 | goto out; |
56d36be4 | 648 | |
23d88e1d DM |
649 | if (vpd[0] != PCI_VPD_LRDT_ID_STRING) { |
650 | dev_err(adapter->pdev_dev, "missing VPD ID string\n"); | |
8c357ebd VP |
651 | ret = -EINVAL; |
652 | goto out; | |
23d88e1d DM |
653 | } |
654 | ||
655 | id_len = pci_vpd_lrdt_size(vpd); | |
656 | if (id_len > ID_LEN) | |
657 | id_len = ID_LEN; | |
658 | ||
659 | i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA); | |
660 | if (i < 0) { | |
661 | dev_err(adapter->pdev_dev, "missing VPD-R section\n"); | |
8c357ebd VP |
662 | ret = -EINVAL; |
663 | goto out; | |
23d88e1d DM |
664 | } |
665 | ||
666 | vpdr_len = pci_vpd_lrdt_size(&vpd[i]); | |
667 | kw_offset = i + PCI_VPD_LRDT_TAG_SIZE; | |
668 | if (vpdr_len + kw_offset > VPD_LEN) { | |
226ec5fd | 669 | dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len); |
8c357ebd VP |
670 | ret = -EINVAL; |
671 | goto out; | |
226ec5fd DM |
672 | } |
673 | ||
674 | #define FIND_VPD_KW(var, name) do { \ | |
23d88e1d | 675 | var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \ |
226ec5fd DM |
676 | if (var < 0) { \ |
677 | dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \ | |
8c357ebd VP |
678 | ret = -EINVAL; \ |
679 | goto out; \ | |
226ec5fd DM |
680 | } \ |
681 | var += PCI_VPD_INFO_FLD_HDR_SIZE; \ | |
682 | } while (0) | |
683 | ||
684 | FIND_VPD_KW(i, "RV"); | |
685 | for (csum = 0; i >= 0; i--) | |
686 | csum += vpd[i]; | |
56d36be4 DM |
687 | |
688 | if (csum) { | |
689 | dev_err(adapter->pdev_dev, | |
690 | "corrupted VPD EEPROM, actual csum %u\n", csum); | |
8c357ebd VP |
691 | ret = -EINVAL; |
692 | goto out; | |
56d36be4 DM |
693 | } |
694 | ||
226ec5fd DM |
695 | FIND_VPD_KW(ec, "EC"); |
696 | FIND_VPD_KW(sn, "SN"); | |
a94cd705 | 697 | FIND_VPD_KW(pn, "PN"); |
226ec5fd DM |
698 | #undef FIND_VPD_KW |
699 | ||
23d88e1d | 700 | memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len); |
56d36be4 | 701 | strim(p->id); |
226ec5fd | 702 | memcpy(p->ec, vpd + ec, EC_LEN); |
56d36be4 | 703 | strim(p->ec); |
226ec5fd DM |
704 | i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE); |
705 | memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); | |
56d36be4 | 706 | strim(p->sn); |
63a92fe6 | 707 | i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE); |
a94cd705 KS |
708 | memcpy(p->pn, vpd + pn, min(i, PN_LEN)); |
709 | strim(p->pn); | |
636f9d37 VP |
710 | |
711 | /* | |
712 | * Ask firmware for the Core Clock since it knows how to translate the | |
713 | * Reference Clock ('V2') VPD field into a Core Clock value ... | |
714 | */ | |
5167865a HS |
715 | cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
716 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK)); | |
636f9d37 VP |
717 | ret = t4_query_params(adapter, adapter->mbox, 0, 0, |
718 | 1, &cclk_param, &cclk_val); | |
8c357ebd VP |
719 | |
720 | out: | |
721 | vfree(vpd); | |
636f9d37 VP |
722 | if (ret) |
723 | return ret; | |
724 | p->cclk = cclk_val; | |
725 | ||
56d36be4 DM |
726 | return 0; |
727 | } | |
728 | ||
729 | /* serial flash and firmware constants */ | |
730 | enum { | |
731 | SF_ATTEMPTS = 10, /* max retries for SF operations */ | |
732 | ||
733 | /* flash command opcodes */ | |
734 | SF_PROG_PAGE = 2, /* program page */ | |
735 | SF_WR_DISABLE = 4, /* disable writes */ | |
736 | SF_RD_STATUS = 5, /* read status register */ | |
737 | SF_WR_ENABLE = 6, /* enable writes */ | |
738 | SF_RD_DATA_FAST = 0xb, /* read flash */ | |
900a6596 | 739 | SF_RD_ID = 0x9f, /* read ID */ |
56d36be4 DM |
740 | SF_ERASE_SECTOR = 0xd8, /* erase sector */ |
741 | ||
6f1d7210 | 742 | FW_MAX_SIZE = 16 * SF_SEC_SIZE, |
56d36be4 DM |
743 | }; |
744 | ||
745 | /** | |
746 | * sf1_read - read data from the serial flash | |
747 | * @adapter: the adapter | |
748 | * @byte_cnt: number of bytes to read | |
749 | * @cont: whether another operation will be chained | |
750 | * @lock: whether to lock SF for PL access only | |
751 | * @valp: where to store the read data | |
752 | * | |
753 | * Reads up to 4 bytes of data from the serial flash. The location of | |
754 | * the read needs to be specified prior to calling this by issuing the | |
755 | * appropriate commands to the serial flash. | |
756 | */ | |
757 | static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, | |
758 | int lock, u32 *valp) | |
759 | { | |
760 | int ret; | |
761 | ||
762 | if (!byte_cnt || byte_cnt > 4) | |
763 | return -EINVAL; | |
0d804338 | 764 | if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) |
56d36be4 | 765 | return -EBUSY; |
0d804338 HS |
766 | t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | |
767 | SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1)); | |
768 | ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5); | |
56d36be4 | 769 | if (!ret) |
0d804338 | 770 | *valp = t4_read_reg(adapter, SF_DATA_A); |
56d36be4 DM |
771 | return ret; |
772 | } | |
773 | ||
774 | /** | |
775 | * sf1_write - write data to the serial flash | |
776 | * @adapter: the adapter | |
777 | * @byte_cnt: number of bytes to write | |
778 | * @cont: whether another operation will be chained | |
779 | * @lock: whether to lock SF for PL access only | |
780 | * @val: value to write | |
781 | * | |
782 | * Writes up to 4 bytes of data to the serial flash. The location of | |
783 | * the write needs to be specified prior to calling this by issuing the | |
784 | * appropriate commands to the serial flash. | |
785 | */ | |
786 | static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, | |
787 | int lock, u32 val) | |
788 | { | |
789 | if (!byte_cnt || byte_cnt > 4) | |
790 | return -EINVAL; | |
0d804338 | 791 | if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) |
56d36be4 | 792 | return -EBUSY; |
0d804338 HS |
793 | t4_write_reg(adapter, SF_DATA_A, val); |
794 | t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | | |
795 | SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1)); | |
796 | return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5); | |
56d36be4 DM |
797 | } |
798 | ||
799 | /** | |
800 | * flash_wait_op - wait for a flash operation to complete | |
801 | * @adapter: the adapter | |
802 | * @attempts: max number of polls of the status register | |
803 | * @delay: delay between polls in ms | |
804 | * | |
805 | * Wait for a flash operation to complete by polling the status register. | |
806 | */ | |
807 | static int flash_wait_op(struct adapter *adapter, int attempts, int delay) | |
808 | { | |
809 | int ret; | |
810 | u32 status; | |
811 | ||
812 | while (1) { | |
813 | if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || | |
814 | (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) | |
815 | return ret; | |
816 | if (!(status & 1)) | |
817 | return 0; | |
818 | if (--attempts == 0) | |
819 | return -EAGAIN; | |
820 | if (delay) | |
821 | msleep(delay); | |
822 | } | |
823 | } | |
824 | ||
825 | /** | |
826 | * t4_read_flash - read words from serial flash | |
827 | * @adapter: the adapter | |
828 | * @addr: the start address for the read | |
829 | * @nwords: how many 32-bit words to read | |
830 | * @data: where to store the read data | |
831 | * @byte_oriented: whether to store data as bytes or as words | |
832 | * | |
833 | * Read the specified number of 32-bit words from the serial flash. | |
834 | * If @byte_oriented is set the read data is stored as a byte array | |
835 | * (i.e., big-endian), otherwise as 32-bit words in the platform's | |
836 | * natural endianess. | |
837 | */ | |
49216c1c HS |
838 | int t4_read_flash(struct adapter *adapter, unsigned int addr, |
839 | unsigned int nwords, u32 *data, int byte_oriented) | |
56d36be4 DM |
840 | { |
841 | int ret; | |
842 | ||
900a6596 | 843 | if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) |
56d36be4 DM |
844 | return -EINVAL; |
845 | ||
846 | addr = swab32(addr) | SF_RD_DATA_FAST; | |
847 | ||
848 | if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || | |
849 | (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) | |
850 | return ret; | |
851 | ||
852 | for ( ; nwords; nwords--, data++) { | |
853 | ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); | |
854 | if (nwords == 1) | |
0d804338 | 855 | t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ |
56d36be4 DM |
856 | if (ret) |
857 | return ret; | |
858 | if (byte_oriented) | |
404d9e3f | 859 | *data = (__force __u32) (htonl(*data)); |
56d36be4 DM |
860 | } |
861 | return 0; | |
862 | } | |
863 | ||
864 | /** | |
865 | * t4_write_flash - write up to a page of data to the serial flash | |
866 | * @adapter: the adapter | |
867 | * @addr: the start address to write | |
868 | * @n: length of data to write in bytes | |
869 | * @data: the data to write | |
870 | * | |
871 | * Writes up to a page of data (256 bytes) to the serial flash starting | |
872 | * at the given address. All the data must be written to the same page. | |
873 | */ | |
874 | static int t4_write_flash(struct adapter *adapter, unsigned int addr, | |
875 | unsigned int n, const u8 *data) | |
876 | { | |
877 | int ret; | |
878 | u32 buf[64]; | |
879 | unsigned int i, c, left, val, offset = addr & 0xff; | |
880 | ||
900a6596 | 881 | if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) |
56d36be4 DM |
882 | return -EINVAL; |
883 | ||
884 | val = swab32(addr) | SF_PROG_PAGE; | |
885 | ||
886 | if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || | |
887 | (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) | |
888 | goto unlock; | |
889 | ||
890 | for (left = n; left; left -= c) { | |
891 | c = min(left, 4U); | |
892 | for (val = 0, i = 0; i < c; ++i) | |
893 | val = (val << 8) + *data++; | |
894 | ||
895 | ret = sf1_write(adapter, c, c != left, 1, val); | |
896 | if (ret) | |
897 | goto unlock; | |
898 | } | |
900a6596 | 899 | ret = flash_wait_op(adapter, 8, 1); |
56d36be4 DM |
900 | if (ret) |
901 | goto unlock; | |
902 | ||
0d804338 | 903 | t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ |
56d36be4 DM |
904 | |
905 | /* Read the page to verify the write succeeded */ | |
906 | ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); | |
907 | if (ret) | |
908 | return ret; | |
909 | ||
910 | if (memcmp(data - n, (u8 *)buf + offset, n)) { | |
911 | dev_err(adapter->pdev_dev, | |
912 | "failed to correctly write the flash page at %#x\n", | |
913 | addr); | |
914 | return -EIO; | |
915 | } | |
916 | return 0; | |
917 | ||
918 | unlock: | |
0d804338 | 919 | t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ |
56d36be4 DM |
920 | return ret; |
921 | } | |
922 | ||
923 | /** | |
16e47624 | 924 | * t4_get_fw_version - read the firmware version |
56d36be4 DM |
925 | * @adapter: the adapter |
926 | * @vers: where to place the version | |
927 | * | |
928 | * Reads the FW version from flash. | |
929 | */ | |
16e47624 | 930 | int t4_get_fw_version(struct adapter *adapter, u32 *vers) |
56d36be4 | 931 | { |
16e47624 HS |
932 | return t4_read_flash(adapter, FLASH_FW_START + |
933 | offsetof(struct fw_hdr, fw_ver), 1, | |
934 | vers, 0); | |
56d36be4 DM |
935 | } |
936 | ||
937 | /** | |
16e47624 | 938 | * t4_get_tp_version - read the TP microcode version |
56d36be4 DM |
939 | * @adapter: the adapter |
940 | * @vers: where to place the version | |
941 | * | |
942 | * Reads the TP microcode version from flash. | |
943 | */ | |
16e47624 | 944 | int t4_get_tp_version(struct adapter *adapter, u32 *vers) |
56d36be4 | 945 | { |
16e47624 | 946 | return t4_read_flash(adapter, FLASH_FW_START + |
900a6596 | 947 | offsetof(struct fw_hdr, tp_microcode_ver), |
56d36be4 DM |
948 | 1, vers, 0); |
949 | } | |
950 | ||
16e47624 HS |
951 | /* Is the given firmware API compatible with the one the driver was compiled |
952 | * with? | |
56d36be4 | 953 | */ |
16e47624 | 954 | static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) |
56d36be4 | 955 | { |
56d36be4 | 956 | |
16e47624 HS |
957 | /* short circuit if it's the exact same firmware version */ |
958 | if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) | |
959 | return 1; | |
56d36be4 | 960 | |
16e47624 HS |
961 | #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) |
962 | if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && | |
963 | SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe)) | |
964 | return 1; | |
965 | #undef SAME_INTF | |
0a57a536 | 966 | |
16e47624 HS |
967 | return 0; |
968 | } | |
56d36be4 | 969 | |
16e47624 HS |
970 | /* The firmware in the filesystem is usable, but should it be installed? |
971 | * This routine explains itself in detail if it indicates the filesystem | |
972 | * firmware should be installed. | |
973 | */ | |
974 | static int should_install_fs_fw(struct adapter *adap, int card_fw_usable, | |
975 | int k, int c) | |
976 | { | |
977 | const char *reason; | |
978 | ||
979 | if (!card_fw_usable) { | |
980 | reason = "incompatible or unusable"; | |
981 | goto install; | |
e69972f5 JH |
982 | } |
983 | ||
16e47624 HS |
984 | if (k > c) { |
985 | reason = "older than the version supported with this driver"; | |
986 | goto install; | |
56d36be4 DM |
987 | } |
988 | ||
16e47624 HS |
989 | return 0; |
990 | ||
991 | install: | |
992 | dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " | |
993 | "installing firmware %u.%u.%u.%u on card.\n", | |
b2e1a3f0 HS |
994 | FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), |
995 | FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason, | |
996 | FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), | |
997 | FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); | |
56d36be4 | 998 | |
56d36be4 DM |
999 | return 1; |
1000 | } | |
1001 | ||
16e47624 HS |
1002 | int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, |
1003 | const u8 *fw_data, unsigned int fw_size, | |
1004 | struct fw_hdr *card_fw, enum dev_state state, | |
1005 | int *reset) | |
1006 | { | |
1007 | int ret, card_fw_usable, fs_fw_usable; | |
1008 | const struct fw_hdr *fs_fw; | |
1009 | const struct fw_hdr *drv_fw; | |
1010 | ||
1011 | drv_fw = &fw_info->fw_hdr; | |
1012 | ||
1013 | /* Read the header of the firmware on the card */ | |
1014 | ret = -t4_read_flash(adap, FLASH_FW_START, | |
1015 | sizeof(*card_fw) / sizeof(uint32_t), | |
1016 | (uint32_t *)card_fw, 1); | |
1017 | if (ret == 0) { | |
1018 | card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw); | |
1019 | } else { | |
1020 | dev_err(adap->pdev_dev, | |
1021 | "Unable to read card's firmware header: %d\n", ret); | |
1022 | card_fw_usable = 0; | |
1023 | } | |
1024 | ||
1025 | if (fw_data != NULL) { | |
1026 | fs_fw = (const void *)fw_data; | |
1027 | fs_fw_usable = fw_compatible(drv_fw, fs_fw); | |
1028 | } else { | |
1029 | fs_fw = NULL; | |
1030 | fs_fw_usable = 0; | |
1031 | } | |
1032 | ||
1033 | if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && | |
1034 | (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { | |
1035 | /* Common case: the firmware on the card is an exact match and | |
1036 | * the filesystem one is an exact match too, or the filesystem | |
1037 | * one is absent/incompatible. | |
1038 | */ | |
1039 | } else if (fs_fw_usable && state == DEV_STATE_UNINIT && | |
1040 | should_install_fs_fw(adap, card_fw_usable, | |
1041 | be32_to_cpu(fs_fw->fw_ver), | |
1042 | be32_to_cpu(card_fw->fw_ver))) { | |
1043 | ret = -t4_fw_upgrade(adap, adap->mbox, fw_data, | |
1044 | fw_size, 0); | |
1045 | if (ret != 0) { | |
1046 | dev_err(adap->pdev_dev, | |
1047 | "failed to install firmware: %d\n", ret); | |
1048 | goto bye; | |
1049 | } | |
1050 | ||
1051 | /* Installed successfully, update the cached header too. */ | |
1052 | memcpy(card_fw, fs_fw, sizeof(*card_fw)); | |
1053 | card_fw_usable = 1; | |
1054 | *reset = 0; /* already reset as part of load_fw */ | |
1055 | } | |
1056 | ||
1057 | if (!card_fw_usable) { | |
1058 | uint32_t d, c, k; | |
1059 | ||
1060 | d = be32_to_cpu(drv_fw->fw_ver); | |
1061 | c = be32_to_cpu(card_fw->fw_ver); | |
1062 | k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; | |
1063 | ||
1064 | dev_err(adap->pdev_dev, "Cannot find a usable firmware: " | |
1065 | "chip state %d, " | |
1066 | "driver compiled with %d.%d.%d.%d, " | |
1067 | "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n", | |
1068 | state, | |
b2e1a3f0 HS |
1069 | FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d), |
1070 | FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d), | |
1071 | FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), | |
1072 | FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), | |
1073 | FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), | |
1074 | FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); | |
16e47624 HS |
1075 | ret = EINVAL; |
1076 | goto bye; | |
1077 | } | |
1078 | ||
1079 | /* We're using whatever's on the card and it's known to be good. */ | |
1080 | adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); | |
1081 | adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); | |
1082 | ||
1083 | bye: | |
1084 | return ret; | |
1085 | } | |
1086 | ||
56d36be4 DM |
1087 | /** |
1088 | * t4_flash_erase_sectors - erase a range of flash sectors | |
1089 | * @adapter: the adapter | |
1090 | * @start: the first sector to erase | |
1091 | * @end: the last sector to erase | |
1092 | * | |
1093 | * Erases the sectors in the given inclusive range. | |
1094 | */ | |
1095 | static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) | |
1096 | { | |
1097 | int ret = 0; | |
1098 | ||
c0d5b8cf HS |
1099 | if (end >= adapter->params.sf_nsec) |
1100 | return -EINVAL; | |
1101 | ||
56d36be4 DM |
1102 | while (start <= end) { |
1103 | if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || | |
1104 | (ret = sf1_write(adapter, 4, 0, 1, | |
1105 | SF_ERASE_SECTOR | (start << 8))) != 0 || | |
900a6596 | 1106 | (ret = flash_wait_op(adapter, 14, 500)) != 0) { |
56d36be4 DM |
1107 | dev_err(adapter->pdev_dev, |
1108 | "erase of flash sector %d failed, error %d\n", | |
1109 | start, ret); | |
1110 | break; | |
1111 | } | |
1112 | start++; | |
1113 | } | |
0d804338 | 1114 | t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ |
56d36be4 DM |
1115 | return ret; |
1116 | } | |
1117 | ||
636f9d37 VP |
1118 | /** |
1119 | * t4_flash_cfg_addr - return the address of the flash configuration file | |
1120 | * @adapter: the adapter | |
1121 | * | |
1122 | * Return the address within the flash where the Firmware Configuration | |
1123 | * File is stored. | |
1124 | */ | |
1125 | unsigned int t4_flash_cfg_addr(struct adapter *adapter) | |
1126 | { | |
1127 | if (adapter->params.sf_size == 0x100000) | |
1128 | return FLASH_FPGA_CFG_START; | |
1129 | else | |
1130 | return FLASH_CFG_START; | |
1131 | } | |
1132 | ||
79af221d HS |
1133 | /* Return TRUE if the specified firmware matches the adapter. I.e. T4 |
1134 | * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead | |
1135 | * and emit an error message for mismatched firmware to save our caller the | |
1136 | * effort ... | |
1137 | */ | |
1138 | static bool t4_fw_matches_chip(const struct adapter *adap, | |
1139 | const struct fw_hdr *hdr) | |
1140 | { | |
1141 | /* The expression below will return FALSE for any unsupported adapter | |
1142 | * which will keep us "honest" in the future ... | |
1143 | */ | |
1144 | if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || | |
1145 | (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5)) | |
1146 | return true; | |
1147 | ||
1148 | dev_err(adap->pdev_dev, | |
1149 | "FW image (%d) is not suitable for this adapter (%d)\n", | |
1150 | hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); | |
1151 | return false; | |
1152 | } | |
1153 | ||
56d36be4 DM |
1154 | /** |
1155 | * t4_load_fw - download firmware | |
1156 | * @adap: the adapter | |
1157 | * @fw_data: the firmware image to write | |
1158 | * @size: image size | |
1159 | * | |
1160 | * Write the supplied firmware image to the card's serial flash. | |
1161 | */ | |
1162 | int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) | |
1163 | { | |
1164 | u32 csum; | |
1165 | int ret, addr; | |
1166 | unsigned int i; | |
1167 | u8 first_page[SF_PAGE_SIZE]; | |
404d9e3f | 1168 | const __be32 *p = (const __be32 *)fw_data; |
56d36be4 | 1169 | const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; |
900a6596 DM |
1170 | unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; |
1171 | unsigned int fw_img_start = adap->params.sf_fw_start; | |
1172 | unsigned int fw_start_sec = fw_img_start / sf_sec_size; | |
56d36be4 DM |
1173 | |
1174 | if (!size) { | |
1175 | dev_err(adap->pdev_dev, "FW image has no data\n"); | |
1176 | return -EINVAL; | |
1177 | } | |
1178 | if (size & 511) { | |
1179 | dev_err(adap->pdev_dev, | |
1180 | "FW image size not multiple of 512 bytes\n"); | |
1181 | return -EINVAL; | |
1182 | } | |
1183 | if (ntohs(hdr->len512) * 512 != size) { | |
1184 | dev_err(adap->pdev_dev, | |
1185 | "FW image size differs from size in FW header\n"); | |
1186 | return -EINVAL; | |
1187 | } | |
1188 | if (size > FW_MAX_SIZE) { | |
1189 | dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", | |
1190 | FW_MAX_SIZE); | |
1191 | return -EFBIG; | |
1192 | } | |
79af221d HS |
1193 | if (!t4_fw_matches_chip(adap, hdr)) |
1194 | return -EINVAL; | |
56d36be4 DM |
1195 | |
1196 | for (csum = 0, i = 0; i < size / sizeof(csum); i++) | |
1197 | csum += ntohl(p[i]); | |
1198 | ||
1199 | if (csum != 0xffffffff) { | |
1200 | dev_err(adap->pdev_dev, | |
1201 | "corrupted firmware image, checksum %#x\n", csum); | |
1202 | return -EINVAL; | |
1203 | } | |
1204 | ||
900a6596 DM |
1205 | i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ |
1206 | ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); | |
56d36be4 DM |
1207 | if (ret) |
1208 | goto out; | |
1209 | ||
1210 | /* | |
1211 | * We write the correct version at the end so the driver can see a bad | |
1212 | * version if the FW write fails. Start by writing a copy of the | |
1213 | * first page with a bad version. | |
1214 | */ | |
1215 | memcpy(first_page, fw_data, SF_PAGE_SIZE); | |
1216 | ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); | |
900a6596 | 1217 | ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page); |
56d36be4 DM |
1218 | if (ret) |
1219 | goto out; | |
1220 | ||
900a6596 | 1221 | addr = fw_img_start; |
56d36be4 DM |
1222 | for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { |
1223 | addr += SF_PAGE_SIZE; | |
1224 | fw_data += SF_PAGE_SIZE; | |
1225 | ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); | |
1226 | if (ret) | |
1227 | goto out; | |
1228 | } | |
1229 | ||
1230 | ret = t4_write_flash(adap, | |
900a6596 | 1231 | fw_img_start + offsetof(struct fw_hdr, fw_ver), |
56d36be4 DM |
1232 | sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver); |
1233 | out: | |
1234 | if (ret) | |
1235 | dev_err(adap->pdev_dev, "firmware download failed, error %d\n", | |
1236 | ret); | |
dff04bce HS |
1237 | else |
1238 | ret = t4_get_fw_version(adap, &adap->params.fw_vers); | |
56d36be4 DM |
1239 | return ret; |
1240 | } | |
1241 | ||
49216c1c HS |
1242 | /** |
1243 | * t4_fwcache - firmware cache operation | |
1244 | * @adap: the adapter | |
1245 | * @op : the operation (flush or flush and invalidate) | |
1246 | */ | |
1247 | int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) | |
1248 | { | |
1249 | struct fw_params_cmd c; | |
1250 | ||
1251 | memset(&c, 0, sizeof(c)); | |
1252 | c.op_to_vfn = | |
1253 | cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | | |
1254 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
1255 | FW_PARAMS_CMD_PFN_V(adap->fn) | | |
1256 | FW_PARAMS_CMD_VFN_V(0)); | |
1257 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); | |
1258 | c.param[0].mnem = | |
1259 | cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
1260 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE)); | |
1261 | c.param[0].val = (__force __be32)op; | |
1262 | ||
1263 | return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); | |
1264 | } | |
1265 | ||
797ff0f5 HS |
1266 | void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) |
1267 | { | |
1268 | unsigned int i, j; | |
1269 | ||
1270 | for (i = 0; i < 8; i++) { | |
1271 | u32 *p = la_buf + i; | |
1272 | ||
1273 | t4_write_reg(adap, ULP_RX_LA_CTL_A, i); | |
1274 | j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A); | |
1275 | t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j); | |
1276 | for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) | |
1277 | *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A); | |
1278 | } | |
1279 | } | |
1280 | ||
56d36be4 | 1281 | #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ |
72aca4bf KS |
1282 | FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \ |
1283 | FW_PORT_CAP_ANEG) | |
56d36be4 DM |
1284 | |
1285 | /** | |
1286 | * t4_link_start - apply link configuration to MAC/PHY | |
1287 | * @phy: the PHY to setup | |
1288 | * @mac: the MAC to setup | |
1289 | * @lc: the requested link configuration | |
1290 | * | |
1291 | * Set up a port's MAC and PHY according to a desired link configuration. | |
1292 | * - If the PHY can auto-negotiate first decide what to advertise, then | |
1293 | * enable/disable auto-negotiation as desired, and reset. | |
1294 | * - If the PHY does not auto-negotiate just reset it. | |
1295 | * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, | |
1296 | * otherwise do it later based on the outcome of auto-negotiation. | |
1297 | */ | |
1298 | int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, | |
1299 | struct link_config *lc) | |
1300 | { | |
1301 | struct fw_port_cmd c; | |
2b5fb1f2 | 1302 | unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO); |
56d36be4 DM |
1303 | |
1304 | lc->link_ok = 0; | |
1305 | if (lc->requested_fc & PAUSE_RX) | |
1306 | fc |= FW_PORT_CAP_FC_RX; | |
1307 | if (lc->requested_fc & PAUSE_TX) | |
1308 | fc |= FW_PORT_CAP_FC_TX; | |
1309 | ||
1310 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 1311 | c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) | FW_CMD_REQUEST_F | |
2b5fb1f2 HS |
1312 | FW_CMD_EXEC_F | FW_PORT_CMD_PORTID_V(port)); |
1313 | c.action_to_len16 = htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | | |
56d36be4 DM |
1314 | FW_LEN16(c)); |
1315 | ||
1316 | if (!(lc->supported & FW_PORT_CAP_ANEG)) { | |
1317 | c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc); | |
1318 | lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); | |
1319 | } else if (lc->autoneg == AUTONEG_DISABLE) { | |
1320 | c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi); | |
1321 | lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); | |
1322 | } else | |
1323 | c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi); | |
1324 | ||
1325 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
1326 | } | |
1327 | ||
1328 | /** | |
1329 | * t4_restart_aneg - restart autonegotiation | |
1330 | * @adap: the adapter | |
1331 | * @mbox: mbox to use for the FW command | |
1332 | * @port: the port id | |
1333 | * | |
1334 | * Restarts autonegotiation for the selected port. | |
1335 | */ | |
1336 | int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) | |
1337 | { | |
1338 | struct fw_port_cmd c; | |
1339 | ||
1340 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 1341 | c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) | FW_CMD_REQUEST_F | |
2b5fb1f2 HS |
1342 | FW_CMD_EXEC_F | FW_PORT_CMD_PORTID_V(port)); |
1343 | c.action_to_len16 = htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | | |
56d36be4 DM |
1344 | FW_LEN16(c)); |
1345 | c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG); | |
1346 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
1347 | } | |
1348 | ||
8caa1e84 VP |
1349 | typedef void (*int_handler_t)(struct adapter *adap); |
1350 | ||
56d36be4 DM |
1351 | struct intr_info { |
1352 | unsigned int mask; /* bits to check in interrupt status */ | |
1353 | const char *msg; /* message to print or NULL */ | |
1354 | short stat_idx; /* stat counter to increment or -1 */ | |
1355 | unsigned short fatal; /* whether the condition reported is fatal */ | |
8caa1e84 | 1356 | int_handler_t int_handler; /* platform-specific int handler */ |
56d36be4 DM |
1357 | }; |
1358 | ||
1359 | /** | |
1360 | * t4_handle_intr_status - table driven interrupt handler | |
1361 | * @adapter: the adapter that generated the interrupt | |
1362 | * @reg: the interrupt status register to process | |
1363 | * @acts: table of interrupt actions | |
1364 | * | |
1365 | * A table driven interrupt handler that applies a set of masks to an | |
1366 | * interrupt status word and performs the corresponding actions if the | |
25985edc | 1367 | * interrupts described by the mask have occurred. The actions include |
56d36be4 DM |
1368 | * optionally emitting a warning or alert message. The table is terminated |
1369 | * by an entry specifying mask 0. Returns the number of fatal interrupt | |
1370 | * conditions. | |
1371 | */ | |
1372 | static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, | |
1373 | const struct intr_info *acts) | |
1374 | { | |
1375 | int fatal = 0; | |
1376 | unsigned int mask = 0; | |
1377 | unsigned int status = t4_read_reg(adapter, reg); | |
1378 | ||
1379 | for ( ; acts->mask; ++acts) { | |
1380 | if (!(status & acts->mask)) | |
1381 | continue; | |
1382 | if (acts->fatal) { | |
1383 | fatal++; | |
1384 | dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, | |
1385 | status & acts->mask); | |
1386 | } else if (acts->msg && printk_ratelimit()) | |
1387 | dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, | |
1388 | status & acts->mask); | |
8caa1e84 VP |
1389 | if (acts->int_handler) |
1390 | acts->int_handler(adapter); | |
56d36be4 DM |
1391 | mask |= acts->mask; |
1392 | } | |
1393 | status &= mask; | |
1394 | if (status) /* clear processed interrupts */ | |
1395 | t4_write_reg(adapter, reg, status); | |
1396 | return fatal; | |
1397 | } | |
1398 | ||
1399 | /* | |
1400 | * Interrupt handler for the PCIE module. | |
1401 | */ | |
1402 | static void pcie_intr_handler(struct adapter *adapter) | |
1403 | { | |
005b5717 | 1404 | static const struct intr_info sysbus_intr_info[] = { |
f061de42 HS |
1405 | { RNPP_F, "RXNP array parity error", -1, 1 }, |
1406 | { RPCP_F, "RXPC array parity error", -1, 1 }, | |
1407 | { RCIP_F, "RXCIF array parity error", -1, 1 }, | |
1408 | { RCCP_F, "Rx completions control array parity error", -1, 1 }, | |
1409 | { RFTP_F, "RXFT array parity error", -1, 1 }, | |
56d36be4 DM |
1410 | { 0 } |
1411 | }; | |
005b5717 | 1412 | static const struct intr_info pcie_port_intr_info[] = { |
f061de42 HS |
1413 | { TPCP_F, "TXPC array parity error", -1, 1 }, |
1414 | { TNPP_F, "TXNP array parity error", -1, 1 }, | |
1415 | { TFTP_F, "TXFT array parity error", -1, 1 }, | |
1416 | { TCAP_F, "TXCA array parity error", -1, 1 }, | |
1417 | { TCIP_F, "TXCIF array parity error", -1, 1 }, | |
1418 | { RCAP_F, "RXCA array parity error", -1, 1 }, | |
1419 | { OTDD_F, "outbound request TLP discarded", -1, 1 }, | |
1420 | { RDPE_F, "Rx data parity error", -1, 1 }, | |
1421 | { TDUE_F, "Tx uncorrectable data error", -1, 1 }, | |
56d36be4 DM |
1422 | { 0 } |
1423 | }; | |
005b5717 | 1424 | static const struct intr_info pcie_intr_info[] = { |
f061de42 HS |
1425 | { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 }, |
1426 | { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 }, | |
1427 | { MSIDATAPERR_F, "MSI data parity error", -1, 1 }, | |
1428 | { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, | |
1429 | { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, | |
1430 | { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, | |
1431 | { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, | |
1432 | { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 }, | |
1433 | { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 }, | |
1434 | { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, | |
1435 | { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 }, | |
1436 | { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, | |
1437 | { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, | |
1438 | { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 }, | |
1439 | { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, | |
1440 | { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, | |
1441 | { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 }, | |
1442 | { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, | |
1443 | { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, | |
1444 | { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, | |
1445 | { FIDPERR_F, "PCI FID parity error", -1, 1 }, | |
1446 | { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 }, | |
1447 | { MATAGPERR_F, "PCI MA tag parity error", -1, 1 }, | |
1448 | { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, | |
1449 | { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 }, | |
1450 | { RXWRPERR_F, "PCI Rx write parity error", -1, 1 }, | |
1451 | { RPLPERR_F, "PCI replay buffer parity error", -1, 1 }, | |
1452 | { PCIESINT_F, "PCI core secondary fault", -1, 1 }, | |
1453 | { PCIEPINT_F, "PCI core primary fault", -1, 1 }, | |
1454 | { UNXSPLCPLERR_F, "PCI unexpected split completion error", | |
1455 | -1, 0 }, | |
56d36be4 DM |
1456 | { 0 } |
1457 | }; | |
1458 | ||
0a57a536 | 1459 | static struct intr_info t5_pcie_intr_info[] = { |
f061de42 | 1460 | { MSTGRPPERR_F, "Master Response Read Queue parity error", |
0a57a536 | 1461 | -1, 1 }, |
f061de42 HS |
1462 | { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, |
1463 | { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 }, | |
1464 | { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, | |
1465 | { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, | |
1466 | { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, | |
1467 | { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, | |
1468 | { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error", | |
0a57a536 | 1469 | -1, 1 }, |
f061de42 | 1470 | { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error", |
0a57a536 | 1471 | -1, 1 }, |
f061de42 HS |
1472 | { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, |
1473 | { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, | |
1474 | { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, | |
1475 | { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, | |
1476 | { DREQWRPERR_F, "PCI DMA channel write request parity error", | |
0a57a536 | 1477 | -1, 1 }, |
f061de42 HS |
1478 | { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, |
1479 | { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, | |
1480 | { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, | |
1481 | { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, | |
1482 | { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, | |
1483 | { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, | |
1484 | { FIDPERR_F, "PCI FID parity error", -1, 1 }, | |
1485 | { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, | |
1486 | { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, | |
1487 | { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, | |
1488 | { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error", | |
0a57a536 | 1489 | -1, 1 }, |
f061de42 HS |
1490 | { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error", |
1491 | -1, 1 }, | |
1492 | { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, | |
1493 | { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, | |
1494 | { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, | |
1495 | { READRSPERR_F, "Outbound read error", -1, 0 }, | |
0a57a536 SR |
1496 | { 0 } |
1497 | }; | |
1498 | ||
56d36be4 DM |
1499 | int fat; |
1500 | ||
9bb59b96 HS |
1501 | if (is_t4(adapter->params.chip)) |
1502 | fat = t4_handle_intr_status(adapter, | |
f061de42 HS |
1503 | PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A, |
1504 | sysbus_intr_info) + | |
9bb59b96 | 1505 | t4_handle_intr_status(adapter, |
f061de42 HS |
1506 | PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A, |
1507 | pcie_port_intr_info) + | |
1508 | t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A, | |
9bb59b96 HS |
1509 | pcie_intr_info); |
1510 | else | |
f061de42 | 1511 | fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A, |
9bb59b96 | 1512 | t5_pcie_intr_info); |
0a57a536 | 1513 | |
56d36be4 DM |
1514 | if (fat) |
1515 | t4_fatal_err(adapter); | |
1516 | } | |
1517 | ||
1518 | /* | |
1519 | * TP interrupt handler. | |
1520 | */ | |
1521 | static void tp_intr_handler(struct adapter *adapter) | |
1522 | { | |
005b5717 | 1523 | static const struct intr_info tp_intr_info[] = { |
56d36be4 | 1524 | { 0x3fffffff, "TP parity error", -1, 1 }, |
837e4a42 | 1525 | { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 }, |
56d36be4 DM |
1526 | { 0 } |
1527 | }; | |
1528 | ||
837e4a42 | 1529 | if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info)) |
56d36be4 DM |
1530 | t4_fatal_err(adapter); |
1531 | } | |
1532 | ||
1533 | /* | |
1534 | * SGE interrupt handler. | |
1535 | */ | |
1536 | static void sge_intr_handler(struct adapter *adapter) | |
1537 | { | |
1538 | u64 v; | |
1539 | ||
005b5717 | 1540 | static const struct intr_info sge_intr_info[] = { |
f612b815 | 1541 | { ERR_CPL_EXCEED_IQE_SIZE_F, |
56d36be4 | 1542 | "SGE received CPL exceeding IQE size", -1, 1 }, |
f612b815 | 1543 | { ERR_INVALID_CIDX_INC_F, |
56d36be4 | 1544 | "SGE GTS CIDX increment too large", -1, 0 }, |
f612b815 HS |
1545 | { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, |
1546 | { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full }, | |
1547 | { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full }, | |
1548 | { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped }, | |
1549 | { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F, | |
56d36be4 | 1550 | "SGE IQID > 1023 received CPL for FL", -1, 0 }, |
f612b815 | 1551 | { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, |
56d36be4 | 1552 | 0 }, |
f612b815 | 1553 | { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1, |
56d36be4 | 1554 | 0 }, |
f612b815 | 1555 | { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1, |
56d36be4 | 1556 | 0 }, |
f612b815 | 1557 | { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1, |
56d36be4 | 1558 | 0 }, |
f612b815 | 1559 | { ERR_ING_CTXT_PRIO_F, |
56d36be4 | 1560 | "SGE too many priority ingress contexts", -1, 0 }, |
f612b815 | 1561 | { ERR_EGR_CTXT_PRIO_F, |
56d36be4 | 1562 | "SGE too many priority egress contexts", -1, 0 }, |
f612b815 HS |
1563 | { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, |
1564 | { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, | |
56d36be4 DM |
1565 | { 0 } |
1566 | }; | |
1567 | ||
f612b815 HS |
1568 | v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) | |
1569 | ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32); | |
56d36be4 DM |
1570 | if (v) { |
1571 | dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n", | |
8caa1e84 | 1572 | (unsigned long long)v); |
f612b815 HS |
1573 | t4_write_reg(adapter, SGE_INT_CAUSE1_A, v); |
1574 | t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32); | |
56d36be4 DM |
1575 | } |
1576 | ||
f612b815 | 1577 | if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info) || |
56d36be4 DM |
1578 | v != 0) |
1579 | t4_fatal_err(adapter); | |
1580 | } | |
1581 | ||
89c3a86c HS |
1582 | #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\ |
1583 | OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F) | |
1584 | #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\ | |
1585 | IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F) | |
1586 | ||
56d36be4 DM |
1587 | /* |
1588 | * CIM interrupt handler. | |
1589 | */ | |
1590 | static void cim_intr_handler(struct adapter *adapter) | |
1591 | { | |
005b5717 | 1592 | static const struct intr_info cim_intr_info[] = { |
89c3a86c HS |
1593 | { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 }, |
1594 | { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, | |
1595 | { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, | |
1596 | { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 }, | |
1597 | { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 }, | |
1598 | { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 }, | |
1599 | { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 }, | |
56d36be4 DM |
1600 | { 0 } |
1601 | }; | |
005b5717 | 1602 | static const struct intr_info cim_upintr_info[] = { |
89c3a86c HS |
1603 | { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 }, |
1604 | { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 }, | |
1605 | { ILLWRINT_F, "CIM illegal write", -1, 1 }, | |
1606 | { ILLRDINT_F, "CIM illegal read", -1, 1 }, | |
1607 | { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 }, | |
1608 | { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 }, | |
1609 | { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 }, | |
1610 | { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 }, | |
1611 | { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 }, | |
1612 | { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 }, | |
1613 | { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 }, | |
1614 | { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 }, | |
1615 | { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 }, | |
1616 | { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 }, | |
1617 | { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 }, | |
1618 | { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 }, | |
1619 | { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 }, | |
1620 | { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 }, | |
1621 | { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 }, | |
1622 | { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 }, | |
1623 | { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 }, | |
1624 | { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 }, | |
1625 | { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 }, | |
1626 | { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 }, | |
1627 | { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 }, | |
1628 | { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 }, | |
1629 | { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 }, | |
1630 | { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 }, | |
56d36be4 DM |
1631 | { 0 } |
1632 | }; | |
1633 | ||
1634 | int fat; | |
1635 | ||
f061de42 | 1636 | if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F) |
31d55c2d HS |
1637 | t4_report_fw_error(adapter); |
1638 | ||
89c3a86c | 1639 | fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A, |
56d36be4 | 1640 | cim_intr_info) + |
89c3a86c | 1641 | t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A, |
56d36be4 DM |
1642 | cim_upintr_info); |
1643 | if (fat) | |
1644 | t4_fatal_err(adapter); | |
1645 | } | |
1646 | ||
1647 | /* | |
1648 | * ULP RX interrupt handler. | |
1649 | */ | |
1650 | static void ulprx_intr_handler(struct adapter *adapter) | |
1651 | { | |
005b5717 | 1652 | static const struct intr_info ulprx_intr_info[] = { |
91e9a1ec | 1653 | { 0x1800000, "ULPRX context error", -1, 1 }, |
56d36be4 DM |
1654 | { 0x7fffff, "ULPRX parity error", -1, 1 }, |
1655 | { 0 } | |
1656 | }; | |
1657 | ||
0d804338 | 1658 | if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info)) |
56d36be4 DM |
1659 | t4_fatal_err(adapter); |
1660 | } | |
1661 | ||
1662 | /* | |
1663 | * ULP TX interrupt handler. | |
1664 | */ | |
1665 | static void ulptx_intr_handler(struct adapter *adapter) | |
1666 | { | |
005b5717 | 1667 | static const struct intr_info ulptx_intr_info[] = { |
837e4a42 | 1668 | { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1, |
56d36be4 | 1669 | 0 }, |
837e4a42 | 1670 | { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1, |
56d36be4 | 1671 | 0 }, |
837e4a42 | 1672 | { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1, |
56d36be4 | 1673 | 0 }, |
837e4a42 | 1674 | { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1, |
56d36be4 DM |
1675 | 0 }, |
1676 | { 0xfffffff, "ULPTX parity error", -1, 1 }, | |
1677 | { 0 } | |
1678 | }; | |
1679 | ||
837e4a42 | 1680 | if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info)) |
56d36be4 DM |
1681 | t4_fatal_err(adapter); |
1682 | } | |
1683 | ||
1684 | /* | |
1685 | * PM TX interrupt handler. | |
1686 | */ | |
1687 | static void pmtx_intr_handler(struct adapter *adapter) | |
1688 | { | |
005b5717 | 1689 | static const struct intr_info pmtx_intr_info[] = { |
837e4a42 HS |
1690 | { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 }, |
1691 | { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 }, | |
1692 | { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 }, | |
1693 | { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 }, | |
1694 | { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 }, | |
1695 | { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 }, | |
1696 | { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", | |
1697 | -1, 1 }, | |
1698 | { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 }, | |
1699 | { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1}, | |
56d36be4 DM |
1700 | { 0 } |
1701 | }; | |
1702 | ||
837e4a42 | 1703 | if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info)) |
56d36be4 DM |
1704 | t4_fatal_err(adapter); |
1705 | } | |
1706 | ||
1707 | /* | |
1708 | * PM RX interrupt handler. | |
1709 | */ | |
1710 | static void pmrx_intr_handler(struct adapter *adapter) | |
1711 | { | |
005b5717 | 1712 | static const struct intr_info pmrx_intr_info[] = { |
837e4a42 HS |
1713 | { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 }, |
1714 | { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 }, | |
1715 | { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 }, | |
1716 | { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", | |
1717 | -1, 1 }, | |
1718 | { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 }, | |
1719 | { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1}, | |
56d36be4 DM |
1720 | { 0 } |
1721 | }; | |
1722 | ||
837e4a42 | 1723 | if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info)) |
56d36be4 DM |
1724 | t4_fatal_err(adapter); |
1725 | } | |
1726 | ||
1727 | /* | |
1728 | * CPL switch interrupt handler. | |
1729 | */ | |
1730 | static void cplsw_intr_handler(struct adapter *adapter) | |
1731 | { | |
005b5717 | 1732 | static const struct intr_info cplsw_intr_info[] = { |
0d804338 HS |
1733 | { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 }, |
1734 | { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 }, | |
1735 | { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 }, | |
1736 | { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 }, | |
1737 | { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 }, | |
1738 | { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 }, | |
56d36be4 DM |
1739 | { 0 } |
1740 | }; | |
1741 | ||
0d804338 | 1742 | if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info)) |
56d36be4 DM |
1743 | t4_fatal_err(adapter); |
1744 | } | |
1745 | ||
1746 | /* | |
1747 | * LE interrupt handler. | |
1748 | */ | |
1749 | static void le_intr_handler(struct adapter *adap) | |
1750 | { | |
005b5717 | 1751 | static const struct intr_info le_intr_info[] = { |
0d804338 HS |
1752 | { LIPMISS_F, "LE LIP miss", -1, 0 }, |
1753 | { LIP0_F, "LE 0 LIP error", -1, 0 }, | |
1754 | { PARITYERR_F, "LE parity error", -1, 1 }, | |
1755 | { UNKNOWNCMD_F, "LE unknown command", -1, 1 }, | |
1756 | { REQQPARERR_F, "LE request queue parity error", -1, 1 }, | |
56d36be4 DM |
1757 | { 0 } |
1758 | }; | |
1759 | ||
0d804338 | 1760 | if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, le_intr_info)) |
56d36be4 DM |
1761 | t4_fatal_err(adap); |
1762 | } | |
1763 | ||
1764 | /* | |
1765 | * MPS interrupt handler. | |
1766 | */ | |
1767 | static void mps_intr_handler(struct adapter *adapter) | |
1768 | { | |
005b5717 | 1769 | static const struct intr_info mps_rx_intr_info[] = { |
56d36be4 DM |
1770 | { 0xffffff, "MPS Rx parity error", -1, 1 }, |
1771 | { 0 } | |
1772 | }; | |
005b5717 | 1773 | static const struct intr_info mps_tx_intr_info[] = { |
837e4a42 HS |
1774 | { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, |
1775 | { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, | |
1776 | { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error", | |
1777 | -1, 1 }, | |
1778 | { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error", | |
1779 | -1, 1 }, | |
1780 | { BUBBLE_F, "MPS Tx underflow", -1, 1 }, | |
1781 | { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, | |
1782 | { FRMERR_F, "MPS Tx framing error", -1, 1 }, | |
56d36be4 DM |
1783 | { 0 } |
1784 | }; | |
005b5717 | 1785 | static const struct intr_info mps_trc_intr_info[] = { |
837e4a42 HS |
1786 | { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 }, |
1787 | { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error", | |
1788 | -1, 1 }, | |
1789 | { MISCPERR_F, "MPS TRC misc parity error", -1, 1 }, | |
56d36be4 DM |
1790 | { 0 } |
1791 | }; | |
005b5717 | 1792 | static const struct intr_info mps_stat_sram_intr_info[] = { |
56d36be4 DM |
1793 | { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, |
1794 | { 0 } | |
1795 | }; | |
005b5717 | 1796 | static const struct intr_info mps_stat_tx_intr_info[] = { |
56d36be4 DM |
1797 | { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, |
1798 | { 0 } | |
1799 | }; | |
005b5717 | 1800 | static const struct intr_info mps_stat_rx_intr_info[] = { |
56d36be4 DM |
1801 | { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, |
1802 | { 0 } | |
1803 | }; | |
005b5717 | 1804 | static const struct intr_info mps_cls_intr_info[] = { |
837e4a42 HS |
1805 | { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 }, |
1806 | { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 }, | |
1807 | { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 }, | |
56d36be4 DM |
1808 | { 0 } |
1809 | }; | |
1810 | ||
1811 | int fat; | |
1812 | ||
837e4a42 | 1813 | fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A, |
56d36be4 | 1814 | mps_rx_intr_info) + |
837e4a42 | 1815 | t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A, |
56d36be4 | 1816 | mps_tx_intr_info) + |
837e4a42 | 1817 | t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A, |
56d36be4 | 1818 | mps_trc_intr_info) + |
837e4a42 | 1819 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A, |
56d36be4 | 1820 | mps_stat_sram_intr_info) + |
837e4a42 | 1821 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A, |
56d36be4 | 1822 | mps_stat_tx_intr_info) + |
837e4a42 | 1823 | t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A, |
56d36be4 | 1824 | mps_stat_rx_intr_info) + |
837e4a42 | 1825 | t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A, |
56d36be4 DM |
1826 | mps_cls_intr_info); |
1827 | ||
837e4a42 HS |
1828 | t4_write_reg(adapter, MPS_INT_CAUSE_A, 0); |
1829 | t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */ | |
56d36be4 DM |
1830 | if (fat) |
1831 | t4_fatal_err(adapter); | |
1832 | } | |
1833 | ||
89c3a86c HS |
1834 | #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \ |
1835 | ECC_UE_INT_CAUSE_F) | |
56d36be4 DM |
1836 | |
1837 | /* | |
1838 | * EDC/MC interrupt handler. | |
1839 | */ | |
1840 | static void mem_intr_handler(struct adapter *adapter, int idx) | |
1841 | { | |
822dd8a8 | 1842 | static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; |
56d36be4 DM |
1843 | |
1844 | unsigned int addr, cnt_addr, v; | |
1845 | ||
1846 | if (idx <= MEM_EDC1) { | |
89c3a86c HS |
1847 | addr = EDC_REG(EDC_INT_CAUSE_A, idx); |
1848 | cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx); | |
822dd8a8 HS |
1849 | } else if (idx == MEM_MC) { |
1850 | if (is_t4(adapter->params.chip)) { | |
89c3a86c HS |
1851 | addr = MC_INT_CAUSE_A; |
1852 | cnt_addr = MC_ECC_STATUS_A; | |
822dd8a8 | 1853 | } else { |
89c3a86c HS |
1854 | addr = MC_P_INT_CAUSE_A; |
1855 | cnt_addr = MC_P_ECC_STATUS_A; | |
822dd8a8 | 1856 | } |
56d36be4 | 1857 | } else { |
89c3a86c HS |
1858 | addr = MC_REG(MC_P_INT_CAUSE_A, 1); |
1859 | cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1); | |
56d36be4 DM |
1860 | } |
1861 | ||
1862 | v = t4_read_reg(adapter, addr) & MEM_INT_MASK; | |
89c3a86c | 1863 | if (v & PERR_INT_CAUSE_F) |
56d36be4 DM |
1864 | dev_alert(adapter->pdev_dev, "%s FIFO parity error\n", |
1865 | name[idx]); | |
89c3a86c HS |
1866 | if (v & ECC_CE_INT_CAUSE_F) { |
1867 | u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr)); | |
56d36be4 | 1868 | |
89c3a86c | 1869 | t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M)); |
56d36be4 DM |
1870 | if (printk_ratelimit()) |
1871 | dev_warn(adapter->pdev_dev, | |
1872 | "%u %s correctable ECC data error%s\n", | |
1873 | cnt, name[idx], cnt > 1 ? "s" : ""); | |
1874 | } | |
89c3a86c | 1875 | if (v & ECC_UE_INT_CAUSE_F) |
56d36be4 DM |
1876 | dev_alert(adapter->pdev_dev, |
1877 | "%s uncorrectable ECC data error\n", name[idx]); | |
1878 | ||
1879 | t4_write_reg(adapter, addr, v); | |
89c3a86c | 1880 | if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F)) |
56d36be4 DM |
1881 | t4_fatal_err(adapter); |
1882 | } | |
1883 | ||
1884 | /* | |
1885 | * MA interrupt handler. | |
1886 | */ | |
1887 | static void ma_intr_handler(struct adapter *adap) | |
1888 | { | |
89c3a86c | 1889 | u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A); |
56d36be4 | 1890 | |
89c3a86c | 1891 | if (status & MEM_PERR_INT_CAUSE_F) { |
56d36be4 DM |
1892 | dev_alert(adap->pdev_dev, |
1893 | "MA parity error, parity status %#x\n", | |
89c3a86c | 1894 | t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A)); |
9bb59b96 HS |
1895 | if (is_t5(adap->params.chip)) |
1896 | dev_alert(adap->pdev_dev, | |
1897 | "MA parity error, parity status %#x\n", | |
1898 | t4_read_reg(adap, | |
89c3a86c | 1899 | MA_PARITY_ERROR_STATUS2_A)); |
9bb59b96 | 1900 | } |
89c3a86c HS |
1901 | if (status & MEM_WRAP_INT_CAUSE_F) { |
1902 | v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A); | |
56d36be4 DM |
1903 | dev_alert(adap->pdev_dev, "MA address wrap-around error by " |
1904 | "client %u to address %#x\n", | |
89c3a86c HS |
1905 | MEM_WRAP_CLIENT_NUM_G(v), |
1906 | MEM_WRAP_ADDRESS_G(v) << 4); | |
56d36be4 | 1907 | } |
89c3a86c | 1908 | t4_write_reg(adap, MA_INT_CAUSE_A, status); |
56d36be4 DM |
1909 | t4_fatal_err(adap); |
1910 | } | |
1911 | ||
1912 | /* | |
1913 | * SMB interrupt handler. | |
1914 | */ | |
1915 | static void smb_intr_handler(struct adapter *adap) | |
1916 | { | |
005b5717 | 1917 | static const struct intr_info smb_intr_info[] = { |
0d804338 HS |
1918 | { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 }, |
1919 | { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 }, | |
1920 | { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 }, | |
56d36be4 DM |
1921 | { 0 } |
1922 | }; | |
1923 | ||
0d804338 | 1924 | if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info)) |
56d36be4 DM |
1925 | t4_fatal_err(adap); |
1926 | } | |
1927 | ||
1928 | /* | |
1929 | * NC-SI interrupt handler. | |
1930 | */ | |
1931 | static void ncsi_intr_handler(struct adapter *adap) | |
1932 | { | |
005b5717 | 1933 | static const struct intr_info ncsi_intr_info[] = { |
0d804338 HS |
1934 | { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 }, |
1935 | { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 }, | |
1936 | { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 }, | |
1937 | { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 }, | |
56d36be4 DM |
1938 | { 0 } |
1939 | }; | |
1940 | ||
0d804338 | 1941 | if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info)) |
56d36be4 DM |
1942 | t4_fatal_err(adap); |
1943 | } | |
1944 | ||
1945 | /* | |
1946 | * XGMAC interrupt handler. | |
1947 | */ | |
1948 | static void xgmac_intr_handler(struct adapter *adap, int port) | |
1949 | { | |
0a57a536 SR |
1950 | u32 v, int_cause_reg; |
1951 | ||
d14807dd | 1952 | if (is_t4(adap->params.chip)) |
0d804338 | 1953 | int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A); |
0a57a536 | 1954 | else |
0d804338 | 1955 | int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A); |
0a57a536 SR |
1956 | |
1957 | v = t4_read_reg(adap, int_cause_reg); | |
56d36be4 | 1958 | |
0d804338 | 1959 | v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F; |
56d36be4 DM |
1960 | if (!v) |
1961 | return; | |
1962 | ||
0d804338 | 1963 | if (v & TXFIFO_PRTY_ERR_F) |
56d36be4 DM |
1964 | dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", |
1965 | port); | |
0d804338 | 1966 | if (v & RXFIFO_PRTY_ERR_F) |
56d36be4 DM |
1967 | dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", |
1968 | port); | |
0d804338 | 1969 | t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v); |
56d36be4 DM |
1970 | t4_fatal_err(adap); |
1971 | } | |
1972 | ||
1973 | /* | |
1974 | * PL interrupt handler. | |
1975 | */ | |
1976 | static void pl_intr_handler(struct adapter *adap) | |
1977 | { | |
005b5717 | 1978 | static const struct intr_info pl_intr_info[] = { |
0d804338 HS |
1979 | { FATALPERR_F, "T4 fatal parity error", -1, 1 }, |
1980 | { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 }, | |
56d36be4 DM |
1981 | { 0 } |
1982 | }; | |
1983 | ||
0d804338 | 1984 | if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info)) |
56d36be4 DM |
1985 | t4_fatal_err(adap); |
1986 | } | |
1987 | ||
0d804338 HS |
1988 | #define PF_INTR_MASK (PFSW_F) |
1989 | #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \ | |
1990 | EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \ | |
1991 | CPL_SWITCH_F | SGE_F | ULP_TX_F) | |
56d36be4 DM |
1992 | |
1993 | /** | |
1994 | * t4_slow_intr_handler - control path interrupt handler | |
1995 | * @adapter: the adapter | |
1996 | * | |
1997 | * T4 interrupt handler for non-data global interrupt events, e.g., errors. | |
1998 | * The designation 'slow' is because it involves register reads, while | |
1999 | * data interrupts typically don't involve any MMIOs. | |
2000 | */ | |
2001 | int t4_slow_intr_handler(struct adapter *adapter) | |
2002 | { | |
0d804338 | 2003 | u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A); |
56d36be4 DM |
2004 | |
2005 | if (!(cause & GLBL_INTR_MASK)) | |
2006 | return 0; | |
0d804338 | 2007 | if (cause & CIM_F) |
56d36be4 | 2008 | cim_intr_handler(adapter); |
0d804338 | 2009 | if (cause & MPS_F) |
56d36be4 | 2010 | mps_intr_handler(adapter); |
0d804338 | 2011 | if (cause & NCSI_F) |
56d36be4 | 2012 | ncsi_intr_handler(adapter); |
0d804338 | 2013 | if (cause & PL_F) |
56d36be4 | 2014 | pl_intr_handler(adapter); |
0d804338 | 2015 | if (cause & SMB_F) |
56d36be4 | 2016 | smb_intr_handler(adapter); |
0d804338 | 2017 | if (cause & XGMAC0_F) |
56d36be4 | 2018 | xgmac_intr_handler(adapter, 0); |
0d804338 | 2019 | if (cause & XGMAC1_F) |
56d36be4 | 2020 | xgmac_intr_handler(adapter, 1); |
0d804338 | 2021 | if (cause & XGMAC_KR0_F) |
56d36be4 | 2022 | xgmac_intr_handler(adapter, 2); |
0d804338 | 2023 | if (cause & XGMAC_KR1_F) |
56d36be4 | 2024 | xgmac_intr_handler(adapter, 3); |
0d804338 | 2025 | if (cause & PCIE_F) |
56d36be4 | 2026 | pcie_intr_handler(adapter); |
0d804338 | 2027 | if (cause & MC_F) |
56d36be4 | 2028 | mem_intr_handler(adapter, MEM_MC); |
0d804338 | 2029 | if (!is_t4(adapter->params.chip) && (cause & MC1_S)) |
822dd8a8 | 2030 | mem_intr_handler(adapter, MEM_MC1); |
0d804338 | 2031 | if (cause & EDC0_F) |
56d36be4 | 2032 | mem_intr_handler(adapter, MEM_EDC0); |
0d804338 | 2033 | if (cause & EDC1_F) |
56d36be4 | 2034 | mem_intr_handler(adapter, MEM_EDC1); |
0d804338 | 2035 | if (cause & LE_F) |
56d36be4 | 2036 | le_intr_handler(adapter); |
0d804338 | 2037 | if (cause & TP_F) |
56d36be4 | 2038 | tp_intr_handler(adapter); |
0d804338 | 2039 | if (cause & MA_F) |
56d36be4 | 2040 | ma_intr_handler(adapter); |
0d804338 | 2041 | if (cause & PM_TX_F) |
56d36be4 | 2042 | pmtx_intr_handler(adapter); |
0d804338 | 2043 | if (cause & PM_RX_F) |
56d36be4 | 2044 | pmrx_intr_handler(adapter); |
0d804338 | 2045 | if (cause & ULP_RX_F) |
56d36be4 | 2046 | ulprx_intr_handler(adapter); |
0d804338 | 2047 | if (cause & CPL_SWITCH_F) |
56d36be4 | 2048 | cplsw_intr_handler(adapter); |
0d804338 | 2049 | if (cause & SGE_F) |
56d36be4 | 2050 | sge_intr_handler(adapter); |
0d804338 | 2051 | if (cause & ULP_TX_F) |
56d36be4 DM |
2052 | ulptx_intr_handler(adapter); |
2053 | ||
2054 | /* Clear the interrupts just processed for which we are the master. */ | |
0d804338 HS |
2055 | t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK); |
2056 | (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */ | |
56d36be4 DM |
2057 | return 1; |
2058 | } | |
2059 | ||
2060 | /** | |
2061 | * t4_intr_enable - enable interrupts | |
2062 | * @adapter: the adapter whose interrupts should be enabled | |
2063 | * | |
2064 | * Enable PF-specific interrupts for the calling function and the top-level | |
2065 | * interrupt concentrator for global interrupts. Interrupts are already | |
2066 | * enabled at each module, here we just enable the roots of the interrupt | |
2067 | * hierarchies. | |
2068 | * | |
2069 | * Note: this function should be called only when the driver manages | |
2070 | * non PF-specific interrupts from the various HW modules. Only one PCI | |
2071 | * function at a time should be doing this. | |
2072 | */ | |
2073 | void t4_intr_enable(struct adapter *adapter) | |
2074 | { | |
0d804338 | 2075 | u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A)); |
56d36be4 | 2076 | |
f612b815 HS |
2077 | t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F | |
2078 | ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F | | |
2079 | ERR_DROPPED_DB_F | ERR_DATA_CPL_ON_HIGH_QID1_F | | |
2080 | ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F | | |
2081 | ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F | | |
2082 | ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F | | |
2083 | ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F | | |
2084 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F | | |
2085 | EGRESS_SIZE_ERR_F); | |
0d804338 HS |
2086 | t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK); |
2087 | t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf); | |
56d36be4 DM |
2088 | } |
2089 | ||
2090 | /** | |
2091 | * t4_intr_disable - disable interrupts | |
2092 | * @adapter: the adapter whose interrupts should be disabled | |
2093 | * | |
2094 | * Disable interrupts. We only disable the top-level interrupt | |
2095 | * concentrators. The caller must be a PCI function managing global | |
2096 | * interrupts. | |
2097 | */ | |
2098 | void t4_intr_disable(struct adapter *adapter) | |
2099 | { | |
0d804338 | 2100 | u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A)); |
56d36be4 | 2101 | |
0d804338 HS |
2102 | t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0); |
2103 | t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0); | |
56d36be4 DM |
2104 | } |
2105 | ||
56d36be4 DM |
2106 | /** |
2107 | * hash_mac_addr - return the hash value of a MAC address | |
2108 | * @addr: the 48-bit Ethernet MAC address | |
2109 | * | |
2110 | * Hashes a MAC address according to the hash function used by HW inexact | |
2111 | * (hash) address matching. | |
2112 | */ | |
2113 | static int hash_mac_addr(const u8 *addr) | |
2114 | { | |
2115 | u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; | |
2116 | u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; | |
2117 | a ^= b; | |
2118 | a ^= (a >> 12); | |
2119 | a ^= (a >> 6); | |
2120 | return a & 0x3f; | |
2121 | } | |
2122 | ||
2123 | /** | |
2124 | * t4_config_rss_range - configure a portion of the RSS mapping table | |
2125 | * @adapter: the adapter | |
2126 | * @mbox: mbox to use for the FW command | |
2127 | * @viid: virtual interface whose RSS subtable is to be written | |
2128 | * @start: start entry in the table to write | |
2129 | * @n: how many table entries to write | |
2130 | * @rspq: values for the response queue lookup table | |
2131 | * @nrspq: number of values in @rspq | |
2132 | * | |
2133 | * Programs the selected part of the VI's RSS mapping table with the | |
2134 | * provided values. If @nrspq < @n the supplied values are used repeatedly | |
2135 | * until the full table range is populated. | |
2136 | * | |
2137 | * The caller must ensure the values in @rspq are in the range allowed for | |
2138 | * @viid. | |
2139 | */ | |
2140 | int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, | |
2141 | int start, int n, const u16 *rspq, unsigned int nrspq) | |
2142 | { | |
2143 | int ret; | |
2144 | const u16 *rsp = rspq; | |
2145 | const u16 *rsp_end = rspq + nrspq; | |
2146 | struct fw_rss_ind_tbl_cmd cmd; | |
2147 | ||
2148 | memset(&cmd, 0, sizeof(cmd)); | |
e2ac9628 HS |
2149 | cmd.op_to_viid = htonl(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) | |
2150 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
b2e1a3f0 | 2151 | FW_RSS_IND_TBL_CMD_VIID_V(viid)); |
56d36be4 DM |
2152 | cmd.retval_len16 = htonl(FW_LEN16(cmd)); |
2153 | ||
2154 | /* each fw_rss_ind_tbl_cmd takes up to 32 entries */ | |
2155 | while (n > 0) { | |
2156 | int nq = min(n, 32); | |
2157 | __be32 *qp = &cmd.iq0_to_iq2; | |
2158 | ||
2159 | cmd.niqid = htons(nq); | |
2160 | cmd.startidx = htons(start); | |
2161 | ||
2162 | start += nq; | |
2163 | n -= nq; | |
2164 | ||
2165 | while (nq > 0) { | |
2166 | unsigned int v; | |
2167 | ||
b2e1a3f0 | 2168 | v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp); |
56d36be4 DM |
2169 | if (++rsp >= rsp_end) |
2170 | rsp = rspq; | |
b2e1a3f0 | 2171 | v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp); |
56d36be4 DM |
2172 | if (++rsp >= rsp_end) |
2173 | rsp = rspq; | |
b2e1a3f0 | 2174 | v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp); |
56d36be4 DM |
2175 | if (++rsp >= rsp_end) |
2176 | rsp = rspq; | |
2177 | ||
2178 | *qp++ = htonl(v); | |
2179 | nq -= 3; | |
2180 | } | |
2181 | ||
2182 | ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); | |
2183 | if (ret) | |
2184 | return ret; | |
2185 | } | |
2186 | return 0; | |
2187 | } | |
2188 | ||
2189 | /** | |
2190 | * t4_config_glbl_rss - configure the global RSS mode | |
2191 | * @adapter: the adapter | |
2192 | * @mbox: mbox to use for the FW command | |
2193 | * @mode: global RSS mode | |
2194 | * @flags: mode-specific flags | |
2195 | * | |
2196 | * Sets the global RSS mode. | |
2197 | */ | |
2198 | int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, | |
2199 | unsigned int flags) | |
2200 | { | |
2201 | struct fw_rss_glb_config_cmd c; | |
2202 | ||
2203 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
2204 | c.op_to_write = htonl(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) | |
2205 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
56d36be4 DM |
2206 | c.retval_len16 = htonl(FW_LEN16(c)); |
2207 | if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { | |
b2e1a3f0 | 2208 | c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode)); |
56d36be4 DM |
2209 | } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { |
2210 | c.u.basicvirtual.mode_pkd = | |
b2e1a3f0 | 2211 | htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode)); |
56d36be4 DM |
2212 | c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags); |
2213 | } else | |
2214 | return -EINVAL; | |
2215 | return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); | |
2216 | } | |
2217 | ||
688ea5fe HS |
2218 | /* Read an RSS table row */ |
2219 | static int rd_rss_row(struct adapter *adap, int row, u32 *val) | |
2220 | { | |
2221 | t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row); | |
2222 | return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1, | |
2223 | 5, 0, val); | |
2224 | } | |
2225 | ||
2226 | /** | |
2227 | * t4_read_rss - read the contents of the RSS mapping table | |
2228 | * @adapter: the adapter | |
2229 | * @map: holds the contents of the RSS mapping table | |
2230 | * | |
2231 | * Reads the contents of the RSS hash->queue mapping table. | |
2232 | */ | |
2233 | int t4_read_rss(struct adapter *adapter, u16 *map) | |
2234 | { | |
2235 | u32 val; | |
2236 | int i, ret; | |
2237 | ||
2238 | for (i = 0; i < RSS_NENTRIES / 2; ++i) { | |
2239 | ret = rd_rss_row(adapter, i, &val); | |
2240 | if (ret) | |
2241 | return ret; | |
2242 | *map++ = LKPTBLQUEUE0_G(val); | |
2243 | *map++ = LKPTBLQUEUE1_G(val); | |
2244 | } | |
2245 | return 0; | |
2246 | } | |
2247 | ||
2248 | /** | |
2249 | * t4_read_rss_key - read the global RSS key | |
2250 | * @adap: the adapter | |
2251 | * @key: 10-entry array holding the 320-bit RSS key | |
2252 | * | |
2253 | * Reads the global 320-bit RSS key. | |
2254 | */ | |
2255 | void t4_read_rss_key(struct adapter *adap, u32 *key) | |
2256 | { | |
2257 | t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, | |
2258 | TP_RSS_SECRET_KEY0_A); | |
2259 | } | |
2260 | ||
2261 | /** | |
2262 | * t4_write_rss_key - program one of the RSS keys | |
2263 | * @adap: the adapter | |
2264 | * @key: 10-entry array holding the 320-bit RSS key | |
2265 | * @idx: which RSS key to write | |
2266 | * | |
2267 | * Writes one of the RSS keys with the given 320-bit value. If @idx is | |
2268 | * 0..15 the corresponding entry in the RSS key table is written, | |
2269 | * otherwise the global RSS key is written. | |
2270 | */ | |
2271 | void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) | |
2272 | { | |
2273 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, | |
2274 | TP_RSS_SECRET_KEY0_A); | |
2275 | if (idx >= 0 && idx < 16) | |
2276 | t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, | |
2277 | KEYWRADDR_V(idx) | KEYWREN_F); | |
2278 | } | |
2279 | ||
2280 | /** | |
2281 | * t4_read_rss_pf_config - read PF RSS Configuration Table | |
2282 | * @adapter: the adapter | |
2283 | * @index: the entry in the PF RSS table to read | |
2284 | * @valp: where to store the returned value | |
2285 | * | |
2286 | * Reads the PF RSS Configuration Table at the specified index and returns | |
2287 | * the value found there. | |
2288 | */ | |
2289 | void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, | |
2290 | u32 *valp) | |
2291 | { | |
2292 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
2293 | valp, 1, TP_RSS_PF0_CONFIG_A + index); | |
2294 | } | |
2295 | ||
2296 | /** | |
2297 | * t4_read_rss_vf_config - read VF RSS Configuration Table | |
2298 | * @adapter: the adapter | |
2299 | * @index: the entry in the VF RSS table to read | |
2300 | * @vfl: where to store the returned VFL | |
2301 | * @vfh: where to store the returned VFH | |
2302 | * | |
2303 | * Reads the VF RSS Configuration Table at the specified index and returns | |
2304 | * the (VFL, VFH) values found there. | |
2305 | */ | |
2306 | void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, | |
2307 | u32 *vfl, u32 *vfh) | |
2308 | { | |
2309 | u32 vrt, mask, data; | |
2310 | ||
2311 | mask = VFWRADDR_V(VFWRADDR_M); | |
2312 | data = VFWRADDR_V(index); | |
2313 | ||
2314 | /* Request that the index'th VF Table values be read into VFL/VFH. | |
2315 | */ | |
2316 | vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A); | |
2317 | vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask); | |
2318 | vrt |= data | VFRDEN_F; | |
2319 | t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt); | |
2320 | ||
2321 | /* Grab the VFL/VFH values ... | |
2322 | */ | |
2323 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
2324 | vfl, 1, TP_RSS_VFL_CONFIG_A); | |
2325 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
2326 | vfh, 1, TP_RSS_VFH_CONFIG_A); | |
2327 | } | |
2328 | ||
2329 | /** | |
2330 | * t4_read_rss_pf_map - read PF RSS Map | |
2331 | * @adapter: the adapter | |
2332 | * | |
2333 | * Reads the PF RSS Map register and returns its value. | |
2334 | */ | |
2335 | u32 t4_read_rss_pf_map(struct adapter *adapter) | |
2336 | { | |
2337 | u32 pfmap; | |
2338 | ||
2339 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
2340 | &pfmap, 1, TP_RSS_PF_MAP_A); | |
2341 | return pfmap; | |
2342 | } | |
2343 | ||
2344 | /** | |
2345 | * t4_read_rss_pf_mask - read PF RSS Mask | |
2346 | * @adapter: the adapter | |
2347 | * | |
2348 | * Reads the PF RSS Mask register and returns its value. | |
2349 | */ | |
2350 | u32 t4_read_rss_pf_mask(struct adapter *adapter) | |
2351 | { | |
2352 | u32 pfmask; | |
2353 | ||
2354 | t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
2355 | &pfmask, 1, TP_RSS_PF_MSK_A); | |
2356 | return pfmask; | |
2357 | } | |
2358 | ||
56d36be4 DM |
2359 | /** |
2360 | * t4_tp_get_tcp_stats - read TP's TCP MIB counters | |
2361 | * @adap: the adapter | |
2362 | * @v4: holds the TCP/IP counter values | |
2363 | * @v6: holds the TCP/IPv6 counter values | |
2364 | * | |
2365 | * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. | |
2366 | * Either @v4 or @v6 may be %NULL to skip the corresponding stats. | |
2367 | */ | |
2368 | void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, | |
2369 | struct tp_tcp_stats *v6) | |
2370 | { | |
837e4a42 | 2371 | u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1]; |
56d36be4 | 2372 | |
837e4a42 | 2373 | #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A) |
56d36be4 DM |
2374 | #define STAT(x) val[STAT_IDX(x)] |
2375 | #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) | |
2376 | ||
2377 | if (v4) { | |
837e4a42 HS |
2378 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, |
2379 | ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A); | |
56d36be4 DM |
2380 | v4->tcpOutRsts = STAT(OUT_RST); |
2381 | v4->tcpInSegs = STAT64(IN_SEG); | |
2382 | v4->tcpOutSegs = STAT64(OUT_SEG); | |
2383 | v4->tcpRetransSegs = STAT64(RXT_SEG); | |
2384 | } | |
2385 | if (v6) { | |
837e4a42 HS |
2386 | t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, |
2387 | ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A); | |
56d36be4 DM |
2388 | v6->tcpOutRsts = STAT(OUT_RST); |
2389 | v6->tcpInSegs = STAT64(IN_SEG); | |
2390 | v6->tcpOutSegs = STAT64(OUT_SEG); | |
2391 | v6->tcpRetransSegs = STAT64(RXT_SEG); | |
2392 | } | |
2393 | #undef STAT64 | |
2394 | #undef STAT | |
2395 | #undef STAT_IDX | |
2396 | } | |
2397 | ||
56d36be4 DM |
2398 | /** |
2399 | * t4_read_mtu_tbl - returns the values in the HW path MTU table | |
2400 | * @adap: the adapter | |
2401 | * @mtus: where to store the MTU values | |
2402 | * @mtu_log: where to store the MTU base-2 log (may be %NULL) | |
2403 | * | |
2404 | * Reads the HW path MTU table. | |
2405 | */ | |
2406 | void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) | |
2407 | { | |
2408 | u32 v; | |
2409 | int i; | |
2410 | ||
2411 | for (i = 0; i < NMTUS; ++i) { | |
837e4a42 HS |
2412 | t4_write_reg(adap, TP_MTU_TABLE_A, |
2413 | MTUINDEX_V(0xff) | MTUVALUE_V(i)); | |
2414 | v = t4_read_reg(adap, TP_MTU_TABLE_A); | |
2415 | mtus[i] = MTUVALUE_G(v); | |
56d36be4 | 2416 | if (mtu_log) |
837e4a42 | 2417 | mtu_log[i] = MTUWIDTH_G(v); |
56d36be4 DM |
2418 | } |
2419 | } | |
2420 | ||
bad43792 HS |
2421 | /** |
2422 | * t4_read_cong_tbl - reads the congestion control table | |
2423 | * @adap: the adapter | |
2424 | * @incr: where to store the alpha values | |
2425 | * | |
2426 | * Reads the additive increments programmed into the HW congestion | |
2427 | * control table. | |
2428 | */ | |
2429 | void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) | |
2430 | { | |
2431 | unsigned int mtu, w; | |
2432 | ||
2433 | for (mtu = 0; mtu < NMTUS; ++mtu) | |
2434 | for (w = 0; w < NCCTRL_WIN; ++w) { | |
2435 | t4_write_reg(adap, TP_CCTRL_TABLE_A, | |
2436 | ROWINDEX_V(0xffff) | (mtu << 5) | w); | |
2437 | incr[mtu][w] = (u16)t4_read_reg(adap, | |
2438 | TP_CCTRL_TABLE_A) & 0x1fff; | |
2439 | } | |
2440 | } | |
2441 | ||
636f9d37 VP |
2442 | /** |
2443 | * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register | |
2444 | * @adap: the adapter | |
2445 | * @addr: the indirect TP register address | |
2446 | * @mask: specifies the field within the register to modify | |
2447 | * @val: new value for the field | |
2448 | * | |
2449 | * Sets a field of an indirect TP register to the given value. | |
2450 | */ | |
2451 | void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, | |
2452 | unsigned int mask, unsigned int val) | |
2453 | { | |
837e4a42 HS |
2454 | t4_write_reg(adap, TP_PIO_ADDR_A, addr); |
2455 | val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; | |
2456 | t4_write_reg(adap, TP_PIO_DATA_A, val); | |
636f9d37 VP |
2457 | } |
2458 | ||
56d36be4 DM |
2459 | /** |
2460 | * init_cong_ctrl - initialize congestion control parameters | |
2461 | * @a: the alpha values for congestion control | |
2462 | * @b: the beta values for congestion control | |
2463 | * | |
2464 | * Initialize the congestion control parameters. | |
2465 | */ | |
91744948 | 2466 | static void init_cong_ctrl(unsigned short *a, unsigned short *b) |
56d36be4 DM |
2467 | { |
2468 | a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; | |
2469 | a[9] = 2; | |
2470 | a[10] = 3; | |
2471 | a[11] = 4; | |
2472 | a[12] = 5; | |
2473 | a[13] = 6; | |
2474 | a[14] = 7; | |
2475 | a[15] = 8; | |
2476 | a[16] = 9; | |
2477 | a[17] = 10; | |
2478 | a[18] = 14; | |
2479 | a[19] = 17; | |
2480 | a[20] = 21; | |
2481 | a[21] = 25; | |
2482 | a[22] = 30; | |
2483 | a[23] = 35; | |
2484 | a[24] = 45; | |
2485 | a[25] = 60; | |
2486 | a[26] = 80; | |
2487 | a[27] = 100; | |
2488 | a[28] = 200; | |
2489 | a[29] = 300; | |
2490 | a[30] = 400; | |
2491 | a[31] = 500; | |
2492 | ||
2493 | b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; | |
2494 | b[9] = b[10] = 1; | |
2495 | b[11] = b[12] = 2; | |
2496 | b[13] = b[14] = b[15] = b[16] = 3; | |
2497 | b[17] = b[18] = b[19] = b[20] = b[21] = 4; | |
2498 | b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; | |
2499 | b[28] = b[29] = 6; | |
2500 | b[30] = b[31] = 7; | |
2501 | } | |
2502 | ||
2503 | /* The minimum additive increment value for the congestion control table */ | |
2504 | #define CC_MIN_INCR 2U | |
2505 | ||
2506 | /** | |
2507 | * t4_load_mtus - write the MTU and congestion control HW tables | |
2508 | * @adap: the adapter | |
2509 | * @mtus: the values for the MTU table | |
2510 | * @alpha: the values for the congestion control alpha parameter | |
2511 | * @beta: the values for the congestion control beta parameter | |
2512 | * | |
2513 | * Write the HW MTU table with the supplied MTUs and the high-speed | |
2514 | * congestion control table with the supplied alpha, beta, and MTUs. | |
2515 | * We write the two tables together because the additive increments | |
2516 | * depend on the MTUs. | |
2517 | */ | |
2518 | void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, | |
2519 | const unsigned short *alpha, const unsigned short *beta) | |
2520 | { | |
2521 | static const unsigned int avg_pkts[NCCTRL_WIN] = { | |
2522 | 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, | |
2523 | 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, | |
2524 | 28672, 40960, 57344, 81920, 114688, 163840, 229376 | |
2525 | }; | |
2526 | ||
2527 | unsigned int i, w; | |
2528 | ||
2529 | for (i = 0; i < NMTUS; ++i) { | |
2530 | unsigned int mtu = mtus[i]; | |
2531 | unsigned int log2 = fls(mtu); | |
2532 | ||
2533 | if (!(mtu & ((1 << log2) >> 2))) /* round */ | |
2534 | log2--; | |
837e4a42 HS |
2535 | t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) | |
2536 | MTUWIDTH_V(log2) | MTUVALUE_V(mtu)); | |
56d36be4 DM |
2537 | |
2538 | for (w = 0; w < NCCTRL_WIN; ++w) { | |
2539 | unsigned int inc; | |
2540 | ||
2541 | inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], | |
2542 | CC_MIN_INCR); | |
2543 | ||
837e4a42 | 2544 | t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) | |
56d36be4 DM |
2545 | (w << 16) | (beta[w] << 13) | inc); |
2546 | } | |
2547 | } | |
2548 | } | |
2549 | ||
b3bbe36a HS |
2550 | /** |
2551 | * t4_pmtx_get_stats - returns the HW stats from PMTX | |
2552 | * @adap: the adapter | |
2553 | * @cnt: where to store the count statistics | |
2554 | * @cycles: where to store the cycle statistics | |
2555 | * | |
2556 | * Returns performance statistics from PMTX. | |
2557 | */ | |
2558 | void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) | |
2559 | { | |
2560 | int i; | |
2561 | u32 data[2]; | |
2562 | ||
2563 | for (i = 0; i < PM_NSTATS; i++) { | |
2564 | t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); | |
2565 | cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); | |
2566 | if (is_t4(adap->params.chip)) { | |
2567 | cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A); | |
2568 | } else { | |
2569 | t4_read_indirect(adap, PM_TX_DBG_CTRL_A, | |
2570 | PM_TX_DBG_DATA_A, data, 2, | |
2571 | PM_TX_DBG_STAT_MSB_A); | |
2572 | cycles[i] = (((u64)data[0] << 32) | data[1]); | |
2573 | } | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | /** | |
2578 | * t4_pmrx_get_stats - returns the HW stats from PMRX | |
2579 | * @adap: the adapter | |
2580 | * @cnt: where to store the count statistics | |
2581 | * @cycles: where to store the cycle statistics | |
2582 | * | |
2583 | * Returns performance statistics from PMRX. | |
2584 | */ | |
2585 | void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) | |
2586 | { | |
2587 | int i; | |
2588 | u32 data[2]; | |
2589 | ||
2590 | for (i = 0; i < PM_NSTATS; i++) { | |
2591 | t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); | |
2592 | cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); | |
2593 | if (is_t4(adap->params.chip)) { | |
2594 | cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A); | |
2595 | } else { | |
2596 | t4_read_indirect(adap, PM_RX_DBG_CTRL_A, | |
2597 | PM_RX_DBG_DATA_A, data, 2, | |
2598 | PM_RX_DBG_STAT_MSB_A); | |
2599 | cycles[i] = (((u64)data[0] << 32) | data[1]); | |
2600 | } | |
2601 | } | |
2602 | } | |
2603 | ||
56d36be4 DM |
2604 | /** |
2605 | * get_mps_bg_map - return the buffer groups associated with a port | |
2606 | * @adap: the adapter | |
2607 | * @idx: the port index | |
2608 | * | |
2609 | * Returns a bitmap indicating which MPS buffer groups are associated | |
2610 | * with the given port. Bit i is set if buffer group i is used by the | |
2611 | * port. | |
2612 | */ | |
2613 | static unsigned int get_mps_bg_map(struct adapter *adap, int idx) | |
2614 | { | |
837e4a42 | 2615 | u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A)); |
56d36be4 DM |
2616 | |
2617 | if (n == 0) | |
2618 | return idx == 0 ? 0xf : 0; | |
2619 | if (n == 1) | |
2620 | return idx < 2 ? (3 << (2 * idx)) : 0; | |
2621 | return 1 << idx; | |
2622 | } | |
2623 | ||
72aca4bf KS |
2624 | /** |
2625 | * t4_get_port_type_description - return Port Type string description | |
2626 | * @port_type: firmware Port Type enumeration | |
2627 | */ | |
2628 | const char *t4_get_port_type_description(enum fw_port_type port_type) | |
2629 | { | |
2630 | static const char *const port_type_description[] = { | |
2631 | "R XFI", | |
2632 | "R XAUI", | |
2633 | "T SGMII", | |
2634 | "T XFI", | |
2635 | "T XAUI", | |
2636 | "KX4", | |
2637 | "CX4", | |
2638 | "KX", | |
2639 | "KR", | |
2640 | "R SFP+", | |
2641 | "KR/KX", | |
2642 | "KR/KX/KX4", | |
2643 | "R QSFP_10G", | |
5aa80e51 | 2644 | "R QSA", |
72aca4bf KS |
2645 | "R QSFP", |
2646 | "R BP40_BA", | |
2647 | }; | |
2648 | ||
2649 | if (port_type < ARRAY_SIZE(port_type_description)) | |
2650 | return port_type_description[port_type]; | |
2651 | return "UNKNOWN"; | |
2652 | } | |
2653 | ||
56d36be4 DM |
2654 | /** |
2655 | * t4_get_port_stats - collect port statistics | |
2656 | * @adap: the adapter | |
2657 | * @idx: the port index | |
2658 | * @p: the stats structure to fill | |
2659 | * | |
2660 | * Collect statistics related to the given port from HW. | |
2661 | */ | |
2662 | void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) | |
2663 | { | |
2664 | u32 bgmap = get_mps_bg_map(adap, idx); | |
2665 | ||
2666 | #define GET_STAT(name) \ | |
0a57a536 | 2667 | t4_read_reg64(adap, \ |
d14807dd | 2668 | (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ |
0a57a536 | 2669 | T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L))) |
56d36be4 DM |
2670 | #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) |
2671 | ||
2672 | p->tx_octets = GET_STAT(TX_PORT_BYTES); | |
2673 | p->tx_frames = GET_STAT(TX_PORT_FRAMES); | |
2674 | p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); | |
2675 | p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); | |
2676 | p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); | |
2677 | p->tx_error_frames = GET_STAT(TX_PORT_ERROR); | |
2678 | p->tx_frames_64 = GET_STAT(TX_PORT_64B); | |
2679 | p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); | |
2680 | p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); | |
2681 | p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); | |
2682 | p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); | |
2683 | p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); | |
2684 | p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); | |
2685 | p->tx_drop = GET_STAT(TX_PORT_DROP); | |
2686 | p->tx_pause = GET_STAT(TX_PORT_PAUSE); | |
2687 | p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); | |
2688 | p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); | |
2689 | p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); | |
2690 | p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); | |
2691 | p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); | |
2692 | p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); | |
2693 | p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); | |
2694 | p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); | |
2695 | ||
2696 | p->rx_octets = GET_STAT(RX_PORT_BYTES); | |
2697 | p->rx_frames = GET_STAT(RX_PORT_FRAMES); | |
2698 | p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); | |
2699 | p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); | |
2700 | p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); | |
2701 | p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); | |
2702 | p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); | |
2703 | p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); | |
2704 | p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); | |
2705 | p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); | |
2706 | p->rx_runt = GET_STAT(RX_PORT_LESS_64B); | |
2707 | p->rx_frames_64 = GET_STAT(RX_PORT_64B); | |
2708 | p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); | |
2709 | p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); | |
2710 | p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); | |
2711 | p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); | |
2712 | p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); | |
2713 | p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); | |
2714 | p->rx_pause = GET_STAT(RX_PORT_PAUSE); | |
2715 | p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); | |
2716 | p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); | |
2717 | p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); | |
2718 | p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); | |
2719 | p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); | |
2720 | p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); | |
2721 | p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); | |
2722 | p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); | |
2723 | ||
2724 | p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; | |
2725 | p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; | |
2726 | p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; | |
2727 | p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; | |
2728 | p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; | |
2729 | p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; | |
2730 | p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; | |
2731 | p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; | |
2732 | ||
2733 | #undef GET_STAT | |
2734 | #undef GET_STAT_COM | |
2735 | } | |
2736 | ||
56d36be4 DM |
2737 | /** |
2738 | * t4_wol_magic_enable - enable/disable magic packet WoL | |
2739 | * @adap: the adapter | |
2740 | * @port: the physical port index | |
2741 | * @addr: MAC address expected in magic packets, %NULL to disable | |
2742 | * | |
2743 | * Enables/disables magic packet wake-on-LAN for the selected port. | |
2744 | */ | |
2745 | void t4_wol_magic_enable(struct adapter *adap, unsigned int port, | |
2746 | const u8 *addr) | |
2747 | { | |
0a57a536 SR |
2748 | u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; |
2749 | ||
d14807dd | 2750 | if (is_t4(adap->params.chip)) { |
0a57a536 SR |
2751 | mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO); |
2752 | mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI); | |
0d804338 | 2753 | port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2_A); |
0a57a536 SR |
2754 | } else { |
2755 | mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO); | |
2756 | mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI); | |
837e4a42 | 2757 | port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A); |
0a57a536 SR |
2758 | } |
2759 | ||
56d36be4 | 2760 | if (addr) { |
0a57a536 | 2761 | t4_write_reg(adap, mag_id_reg_l, |
56d36be4 DM |
2762 | (addr[2] << 24) | (addr[3] << 16) | |
2763 | (addr[4] << 8) | addr[5]); | |
0a57a536 | 2764 | t4_write_reg(adap, mag_id_reg_h, |
56d36be4 DM |
2765 | (addr[0] << 8) | addr[1]); |
2766 | } | |
0d804338 HS |
2767 | t4_set_reg_field(adap, port_cfg_reg, MAGICEN_F, |
2768 | addr ? MAGICEN_F : 0); | |
56d36be4 DM |
2769 | } |
2770 | ||
2771 | /** | |
2772 | * t4_wol_pat_enable - enable/disable pattern-based WoL | |
2773 | * @adap: the adapter | |
2774 | * @port: the physical port index | |
2775 | * @map: bitmap of which HW pattern filters to set | |
2776 | * @mask0: byte mask for bytes 0-63 of a packet | |
2777 | * @mask1: byte mask for bytes 64-127 of a packet | |
2778 | * @crc: Ethernet CRC for selected bytes | |
2779 | * @enable: enable/disable switch | |
2780 | * | |
2781 | * Sets the pattern filters indicated in @map to mask out the bytes | |
2782 | * specified in @mask0/@mask1 in received packets and compare the CRC of | |
2783 | * the resulting packet against @crc. If @enable is %true pattern-based | |
2784 | * WoL is enabled, otherwise disabled. | |
2785 | */ | |
2786 | int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, | |
2787 | u64 mask0, u64 mask1, unsigned int crc, bool enable) | |
2788 | { | |
2789 | int i; | |
0a57a536 SR |
2790 | u32 port_cfg_reg; |
2791 | ||
d14807dd | 2792 | if (is_t4(adap->params.chip)) |
0d804338 | 2793 | port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2_A); |
0a57a536 | 2794 | else |
837e4a42 | 2795 | port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A); |
56d36be4 DM |
2796 | |
2797 | if (!enable) { | |
0d804338 | 2798 | t4_set_reg_field(adap, port_cfg_reg, PATEN_F, 0); |
56d36be4 DM |
2799 | return 0; |
2800 | } | |
2801 | if (map > 0xff) | |
2802 | return -EINVAL; | |
2803 | ||
0a57a536 | 2804 | #define EPIO_REG(name) \ |
0d804338 HS |
2805 | (is_t4(adap->params.chip) ? \ |
2806 | PORT_REG(port, XGMAC_PORT_EPIO_##name##_A) : \ | |
2807 | T5_PORT_REG(port, MAC_PORT_EPIO_##name##_A)) | |
56d36be4 DM |
2808 | |
2809 | t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); | |
2810 | t4_write_reg(adap, EPIO_REG(DATA2), mask1); | |
2811 | t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); | |
2812 | ||
2813 | for (i = 0; i < NWOL_PAT; i++, map >>= 1) { | |
2814 | if (!(map & 1)) | |
2815 | continue; | |
2816 | ||
2817 | /* write byte masks */ | |
2818 | t4_write_reg(adap, EPIO_REG(DATA0), mask0); | |
0d804338 | 2819 | t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i) | EPIOWR_F); |
56d36be4 | 2820 | t4_read_reg(adap, EPIO_REG(OP)); /* flush */ |
0d804338 | 2821 | if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F) |
56d36be4 DM |
2822 | return -ETIMEDOUT; |
2823 | ||
2824 | /* write CRC */ | |
2825 | t4_write_reg(adap, EPIO_REG(DATA0), crc); | |
0d804338 | 2826 | t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i + 32) | EPIOWR_F); |
56d36be4 | 2827 | t4_read_reg(adap, EPIO_REG(OP)); /* flush */ |
0d804338 | 2828 | if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F) |
56d36be4 DM |
2829 | return -ETIMEDOUT; |
2830 | } | |
2831 | #undef EPIO_REG | |
2832 | ||
0d804338 | 2833 | t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2_A), 0, PATEN_F); |
56d36be4 DM |
2834 | return 0; |
2835 | } | |
2836 | ||
f2b7e78d VP |
2837 | /* t4_mk_filtdelwr - create a delete filter WR |
2838 | * @ftid: the filter ID | |
2839 | * @wr: the filter work request to populate | |
2840 | * @qid: ingress queue to receive the delete notification | |
2841 | * | |
2842 | * Creates a filter work request to delete the supplied filter. If @qid is | |
2843 | * negative the delete notification is suppressed. | |
2844 | */ | |
2845 | void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) | |
2846 | { | |
2847 | memset(wr, 0, sizeof(*wr)); | |
e2ac9628 HS |
2848 | wr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR)); |
2849 | wr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*wr) / 16)); | |
77a80e23 HS |
2850 | wr->tid_to_iq = htonl(FW_FILTER_WR_TID_V(ftid) | |
2851 | FW_FILTER_WR_NOREPLY_V(qid < 0)); | |
2852 | wr->del_filter_to_l2tix = htonl(FW_FILTER_WR_DEL_FILTER_F); | |
f2b7e78d | 2853 | if (qid >= 0) |
77a80e23 | 2854 | wr->rx_chan_rx_rpl_iq = htons(FW_FILTER_WR_RX_RPL_IQ_V(qid)); |
f2b7e78d VP |
2855 | } |
2856 | ||
56d36be4 | 2857 | #define INIT_CMD(var, cmd, rd_wr) do { \ |
e2ac9628 HS |
2858 | (var).op_to_write = htonl(FW_CMD_OP_V(FW_##cmd##_CMD) | \ |
2859 | FW_CMD_REQUEST_F | FW_CMD_##rd_wr##_F); \ | |
56d36be4 DM |
2860 | (var).retval_len16 = htonl(FW_LEN16(var)); \ |
2861 | } while (0) | |
2862 | ||
8caa1e84 VP |
2863 | int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, |
2864 | u32 addr, u32 val) | |
2865 | { | |
2866 | struct fw_ldst_cmd c; | |
2867 | ||
2868 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
2869 | c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F | |
2870 | FW_CMD_WRITE_F | | |
5167865a | 2871 | FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE)); |
8caa1e84 VP |
2872 | c.cycles_to_len16 = htonl(FW_LEN16(c)); |
2873 | c.u.addrval.addr = htonl(addr); | |
2874 | c.u.addrval.val = htonl(val); | |
2875 | ||
2876 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2877 | } | |
2878 | ||
56d36be4 DM |
2879 | /** |
2880 | * t4_mdio_rd - read a PHY register through MDIO | |
2881 | * @adap: the adapter | |
2882 | * @mbox: mailbox to use for the FW command | |
2883 | * @phy_addr: the PHY address | |
2884 | * @mmd: the PHY MMD to access (0 for clause 22 PHYs) | |
2885 | * @reg: the register to read | |
2886 | * @valp: where to store the value | |
2887 | * | |
2888 | * Issues a FW command through the given mailbox to read a PHY register. | |
2889 | */ | |
2890 | int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
2891 | unsigned int mmd, unsigned int reg, u16 *valp) | |
2892 | { | |
2893 | int ret; | |
2894 | struct fw_ldst_cmd c; | |
2895 | ||
2896 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 2897 | c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F | |
5167865a | 2898 | FW_CMD_READ_F | FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO)); |
56d36be4 | 2899 | c.cycles_to_len16 = htonl(FW_LEN16(c)); |
5167865a HS |
2900 | c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR_V(phy_addr) | |
2901 | FW_LDST_CMD_MMD_V(mmd)); | |
56d36be4 DM |
2902 | c.u.mdio.raddr = htons(reg); |
2903 | ||
2904 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
2905 | if (ret == 0) | |
2906 | *valp = ntohs(c.u.mdio.rval); | |
2907 | return ret; | |
2908 | } | |
2909 | ||
2910 | /** | |
2911 | * t4_mdio_wr - write a PHY register through MDIO | |
2912 | * @adap: the adapter | |
2913 | * @mbox: mailbox to use for the FW command | |
2914 | * @phy_addr: the PHY address | |
2915 | * @mmd: the PHY MMD to access (0 for clause 22 PHYs) | |
2916 | * @reg: the register to write | |
2917 | * @valp: value to write | |
2918 | * | |
2919 | * Issues a FW command through the given mailbox to write a PHY register. | |
2920 | */ | |
2921 | int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |
2922 | unsigned int mmd, unsigned int reg, u16 val) | |
2923 | { | |
2924 | struct fw_ldst_cmd c; | |
2925 | ||
2926 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 2927 | c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F | |
5167865a | 2928 | FW_CMD_WRITE_F | FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO)); |
56d36be4 | 2929 | c.cycles_to_len16 = htonl(FW_LEN16(c)); |
5167865a HS |
2930 | c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR_V(phy_addr) | |
2931 | FW_LDST_CMD_MMD_V(mmd)); | |
56d36be4 DM |
2932 | c.u.mdio.raddr = htons(reg); |
2933 | c.u.mdio.rval = htons(val); | |
2934 | ||
2935 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
2936 | } | |
2937 | ||
68bce192 KS |
2938 | /** |
2939 | * t4_sge_decode_idma_state - decode the idma state | |
2940 | * @adap: the adapter | |
2941 | * @state: the state idma is stuck in | |
2942 | */ | |
2943 | void t4_sge_decode_idma_state(struct adapter *adapter, int state) | |
2944 | { | |
2945 | static const char * const t4_decode[] = { | |
2946 | "IDMA_IDLE", | |
2947 | "IDMA_PUSH_MORE_CPL_FIFO", | |
2948 | "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", | |
2949 | "Not used", | |
2950 | "IDMA_PHYSADDR_SEND_PCIEHDR", | |
2951 | "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", | |
2952 | "IDMA_PHYSADDR_SEND_PAYLOAD", | |
2953 | "IDMA_SEND_FIFO_TO_IMSG", | |
2954 | "IDMA_FL_REQ_DATA_FL_PREP", | |
2955 | "IDMA_FL_REQ_DATA_FL", | |
2956 | "IDMA_FL_DROP", | |
2957 | "IDMA_FL_H_REQ_HEADER_FL", | |
2958 | "IDMA_FL_H_SEND_PCIEHDR", | |
2959 | "IDMA_FL_H_PUSH_CPL_FIFO", | |
2960 | "IDMA_FL_H_SEND_CPL", | |
2961 | "IDMA_FL_H_SEND_IP_HDR_FIRST", | |
2962 | "IDMA_FL_H_SEND_IP_HDR", | |
2963 | "IDMA_FL_H_REQ_NEXT_HEADER_FL", | |
2964 | "IDMA_FL_H_SEND_NEXT_PCIEHDR", | |
2965 | "IDMA_FL_H_SEND_IP_HDR_PADDING", | |
2966 | "IDMA_FL_D_SEND_PCIEHDR", | |
2967 | "IDMA_FL_D_SEND_CPL_AND_IP_HDR", | |
2968 | "IDMA_FL_D_REQ_NEXT_DATA_FL", | |
2969 | "IDMA_FL_SEND_PCIEHDR", | |
2970 | "IDMA_FL_PUSH_CPL_FIFO", | |
2971 | "IDMA_FL_SEND_CPL", | |
2972 | "IDMA_FL_SEND_PAYLOAD_FIRST", | |
2973 | "IDMA_FL_SEND_PAYLOAD", | |
2974 | "IDMA_FL_REQ_NEXT_DATA_FL", | |
2975 | "IDMA_FL_SEND_NEXT_PCIEHDR", | |
2976 | "IDMA_FL_SEND_PADDING", | |
2977 | "IDMA_FL_SEND_COMPLETION_TO_IMSG", | |
2978 | "IDMA_FL_SEND_FIFO_TO_IMSG", | |
2979 | "IDMA_FL_REQ_DATAFL_DONE", | |
2980 | "IDMA_FL_REQ_HEADERFL_DONE", | |
2981 | }; | |
2982 | static const char * const t5_decode[] = { | |
2983 | "IDMA_IDLE", | |
2984 | "IDMA_ALMOST_IDLE", | |
2985 | "IDMA_PUSH_MORE_CPL_FIFO", | |
2986 | "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", | |
2987 | "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", | |
2988 | "IDMA_PHYSADDR_SEND_PCIEHDR", | |
2989 | "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", | |
2990 | "IDMA_PHYSADDR_SEND_PAYLOAD", | |
2991 | "IDMA_SEND_FIFO_TO_IMSG", | |
2992 | "IDMA_FL_REQ_DATA_FL", | |
2993 | "IDMA_FL_DROP", | |
2994 | "IDMA_FL_DROP_SEND_INC", | |
2995 | "IDMA_FL_H_REQ_HEADER_FL", | |
2996 | "IDMA_FL_H_SEND_PCIEHDR", | |
2997 | "IDMA_FL_H_PUSH_CPL_FIFO", | |
2998 | "IDMA_FL_H_SEND_CPL", | |
2999 | "IDMA_FL_H_SEND_IP_HDR_FIRST", | |
3000 | "IDMA_FL_H_SEND_IP_HDR", | |
3001 | "IDMA_FL_H_REQ_NEXT_HEADER_FL", | |
3002 | "IDMA_FL_H_SEND_NEXT_PCIEHDR", | |
3003 | "IDMA_FL_H_SEND_IP_HDR_PADDING", | |
3004 | "IDMA_FL_D_SEND_PCIEHDR", | |
3005 | "IDMA_FL_D_SEND_CPL_AND_IP_HDR", | |
3006 | "IDMA_FL_D_REQ_NEXT_DATA_FL", | |
3007 | "IDMA_FL_SEND_PCIEHDR", | |
3008 | "IDMA_FL_PUSH_CPL_FIFO", | |
3009 | "IDMA_FL_SEND_CPL", | |
3010 | "IDMA_FL_SEND_PAYLOAD_FIRST", | |
3011 | "IDMA_FL_SEND_PAYLOAD", | |
3012 | "IDMA_FL_REQ_NEXT_DATA_FL", | |
3013 | "IDMA_FL_SEND_NEXT_PCIEHDR", | |
3014 | "IDMA_FL_SEND_PADDING", | |
3015 | "IDMA_FL_SEND_COMPLETION_TO_IMSG", | |
3016 | }; | |
3017 | static const u32 sge_regs[] = { | |
f061de42 HS |
3018 | SGE_DEBUG_DATA_LOW_INDEX_2_A, |
3019 | SGE_DEBUG_DATA_LOW_INDEX_3_A, | |
3020 | SGE_DEBUG_DATA_HIGH_INDEX_10_A, | |
68bce192 KS |
3021 | }; |
3022 | const char **sge_idma_decode; | |
3023 | int sge_idma_decode_nstates; | |
3024 | int i; | |
3025 | ||
3026 | if (is_t4(adapter->params.chip)) { | |
3027 | sge_idma_decode = (const char **)t4_decode; | |
3028 | sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); | |
3029 | } else { | |
3030 | sge_idma_decode = (const char **)t5_decode; | |
3031 | sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); | |
3032 | } | |
3033 | ||
3034 | if (state < sge_idma_decode_nstates) | |
3035 | CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); | |
3036 | else | |
3037 | CH_WARN(adapter, "idma state %d unknown\n", state); | |
3038 | ||
3039 | for (i = 0; i < ARRAY_SIZE(sge_regs); i++) | |
3040 | CH_WARN(adapter, "SGE register %#x value %#x\n", | |
3041 | sge_regs[i], t4_read_reg(adapter, sge_regs[i])); | |
3042 | } | |
3043 | ||
56d36be4 | 3044 | /** |
636f9d37 VP |
3045 | * t4_fw_hello - establish communication with FW |
3046 | * @adap: the adapter | |
3047 | * @mbox: mailbox to use for the FW command | |
3048 | * @evt_mbox: mailbox to receive async FW events | |
3049 | * @master: specifies the caller's willingness to be the device master | |
3050 | * @state: returns the current device state (if non-NULL) | |
56d36be4 | 3051 | * |
636f9d37 VP |
3052 | * Issues a command to establish communication with FW. Returns either |
3053 | * an error (negative integer) or the mailbox of the Master PF. | |
56d36be4 DM |
3054 | */ |
3055 | int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, | |
3056 | enum dev_master master, enum dev_state *state) | |
3057 | { | |
3058 | int ret; | |
3059 | struct fw_hello_cmd c; | |
636f9d37 VP |
3060 | u32 v; |
3061 | unsigned int master_mbox; | |
3062 | int retries = FW_CMD_HELLO_RETRIES; | |
56d36be4 | 3063 | |
636f9d37 VP |
3064 | retry: |
3065 | memset(&c, 0, sizeof(c)); | |
56d36be4 | 3066 | INIT_CMD(c, HELLO, WRITE); |
ce91a923 | 3067 | c.err_to_clearinit = htonl( |
5167865a HS |
3068 | FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) | |
3069 | FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) | | |
3070 | FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ? mbox : | |
3071 | FW_HELLO_CMD_MBMASTER_M) | | |
3072 | FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) | | |
3073 | FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) | | |
3074 | FW_HELLO_CMD_CLEARINIT_F); | |
56d36be4 | 3075 | |
636f9d37 VP |
3076 | /* |
3077 | * Issue the HELLO command to the firmware. If it's not successful | |
3078 | * but indicates that we got a "busy" or "timeout" condition, retry | |
31d55c2d HS |
3079 | * the HELLO until we exhaust our retry limit. If we do exceed our |
3080 | * retry limit, check to see if the firmware left us any error | |
3081 | * information and report that if so. | |
636f9d37 | 3082 | */ |
56d36be4 | 3083 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); |
636f9d37 VP |
3084 | if (ret < 0) { |
3085 | if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) | |
3086 | goto retry; | |
f061de42 | 3087 | if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F) |
31d55c2d | 3088 | t4_report_fw_error(adap); |
636f9d37 VP |
3089 | return ret; |
3090 | } | |
3091 | ||
ce91a923 | 3092 | v = ntohl(c.err_to_clearinit); |
5167865a | 3093 | master_mbox = FW_HELLO_CMD_MBMASTER_G(v); |
636f9d37 | 3094 | if (state) { |
5167865a | 3095 | if (v & FW_HELLO_CMD_ERR_F) |
56d36be4 | 3096 | *state = DEV_STATE_ERR; |
5167865a | 3097 | else if (v & FW_HELLO_CMD_INIT_F) |
636f9d37 | 3098 | *state = DEV_STATE_INIT; |
56d36be4 DM |
3099 | else |
3100 | *state = DEV_STATE_UNINIT; | |
3101 | } | |
636f9d37 VP |
3102 | |
3103 | /* | |
3104 | * If we're not the Master PF then we need to wait around for the | |
3105 | * Master PF Driver to finish setting up the adapter. | |
3106 | * | |
3107 | * Note that we also do this wait if we're a non-Master-capable PF and | |
3108 | * there is no current Master PF; a Master PF may show up momentarily | |
3109 | * and we wouldn't want to fail pointlessly. (This can happen when an | |
3110 | * OS loads lots of different drivers rapidly at the same time). In | |
3111 | * this case, the Master PF returned by the firmware will be | |
b2e1a3f0 | 3112 | * PCIE_FW_MASTER_M so the test below will work ... |
636f9d37 | 3113 | */ |
5167865a | 3114 | if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 && |
636f9d37 VP |
3115 | master_mbox != mbox) { |
3116 | int waiting = FW_CMD_HELLO_TIMEOUT; | |
3117 | ||
3118 | /* | |
3119 | * Wait for the firmware to either indicate an error or | |
3120 | * initialized state. If we see either of these we bail out | |
3121 | * and report the issue to the caller. If we exhaust the | |
3122 | * "hello timeout" and we haven't exhausted our retries, try | |
3123 | * again. Otherwise bail with a timeout error. | |
3124 | */ | |
3125 | for (;;) { | |
3126 | u32 pcie_fw; | |
3127 | ||
3128 | msleep(50); | |
3129 | waiting -= 50; | |
3130 | ||
3131 | /* | |
3132 | * If neither Error nor Initialialized are indicated | |
3133 | * by the firmware keep waiting till we exaust our | |
3134 | * timeout ... and then retry if we haven't exhausted | |
3135 | * our retries ... | |
3136 | */ | |
f061de42 HS |
3137 | pcie_fw = t4_read_reg(adap, PCIE_FW_A); |
3138 | if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) { | |
636f9d37 VP |
3139 | if (waiting <= 0) { |
3140 | if (retries-- > 0) | |
3141 | goto retry; | |
3142 | ||
3143 | return -ETIMEDOUT; | |
3144 | } | |
3145 | continue; | |
3146 | } | |
3147 | ||
3148 | /* | |
3149 | * We either have an Error or Initialized condition | |
3150 | * report errors preferentially. | |
3151 | */ | |
3152 | if (state) { | |
f061de42 | 3153 | if (pcie_fw & PCIE_FW_ERR_F) |
636f9d37 | 3154 | *state = DEV_STATE_ERR; |
f061de42 | 3155 | else if (pcie_fw & PCIE_FW_INIT_F) |
636f9d37 VP |
3156 | *state = DEV_STATE_INIT; |
3157 | } | |
3158 | ||
3159 | /* | |
3160 | * If we arrived before a Master PF was selected and | |
3161 | * there's not a valid Master PF, grab its identity | |
3162 | * for our caller. | |
3163 | */ | |
b2e1a3f0 | 3164 | if (master_mbox == PCIE_FW_MASTER_M && |
f061de42 | 3165 | (pcie_fw & PCIE_FW_MASTER_VLD_F)) |
b2e1a3f0 | 3166 | master_mbox = PCIE_FW_MASTER_G(pcie_fw); |
636f9d37 VP |
3167 | break; |
3168 | } | |
3169 | } | |
3170 | ||
3171 | return master_mbox; | |
56d36be4 DM |
3172 | } |
3173 | ||
3174 | /** | |
3175 | * t4_fw_bye - end communication with FW | |
3176 | * @adap: the adapter | |
3177 | * @mbox: mailbox to use for the FW command | |
3178 | * | |
3179 | * Issues a command to terminate communication with FW. | |
3180 | */ | |
3181 | int t4_fw_bye(struct adapter *adap, unsigned int mbox) | |
3182 | { | |
3183 | struct fw_bye_cmd c; | |
3184 | ||
0062b15c | 3185 | memset(&c, 0, sizeof(c)); |
56d36be4 DM |
3186 | INIT_CMD(c, BYE, WRITE); |
3187 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
3188 | } | |
3189 | ||
3190 | /** | |
3191 | * t4_init_cmd - ask FW to initialize the device | |
3192 | * @adap: the adapter | |
3193 | * @mbox: mailbox to use for the FW command | |
3194 | * | |
3195 | * Issues a command to FW to partially initialize the device. This | |
3196 | * performs initialization that generally doesn't depend on user input. | |
3197 | */ | |
3198 | int t4_early_init(struct adapter *adap, unsigned int mbox) | |
3199 | { | |
3200 | struct fw_initialize_cmd c; | |
3201 | ||
0062b15c | 3202 | memset(&c, 0, sizeof(c)); |
56d36be4 DM |
3203 | INIT_CMD(c, INITIALIZE, WRITE); |
3204 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
3205 | } | |
3206 | ||
3207 | /** | |
3208 | * t4_fw_reset - issue a reset to FW | |
3209 | * @adap: the adapter | |
3210 | * @mbox: mailbox to use for the FW command | |
3211 | * @reset: specifies the type of reset to perform | |
3212 | * | |
3213 | * Issues a reset command of the specified type to FW. | |
3214 | */ | |
3215 | int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) | |
3216 | { | |
3217 | struct fw_reset_cmd c; | |
3218 | ||
0062b15c | 3219 | memset(&c, 0, sizeof(c)); |
56d36be4 DM |
3220 | INIT_CMD(c, RESET, WRITE); |
3221 | c.val = htonl(reset); | |
3222 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
3223 | } | |
3224 | ||
26f7cbc0 VP |
3225 | /** |
3226 | * t4_fw_halt - issue a reset/halt to FW and put uP into RESET | |
3227 | * @adap: the adapter | |
3228 | * @mbox: mailbox to use for the FW RESET command (if desired) | |
3229 | * @force: force uP into RESET even if FW RESET command fails | |
3230 | * | |
3231 | * Issues a RESET command to firmware (if desired) with a HALT indication | |
3232 | * and then puts the microprocessor into RESET state. The RESET command | |
3233 | * will only be issued if a legitimate mailbox is provided (mbox <= | |
b2e1a3f0 | 3234 | * PCIE_FW_MASTER_M). |
26f7cbc0 VP |
3235 | * |
3236 | * This is generally used in order for the host to safely manipulate the | |
3237 | * adapter without fear of conflicting with whatever the firmware might | |
3238 | * be doing. The only way out of this state is to RESTART the firmware | |
3239 | * ... | |
3240 | */ | |
de5b8677 | 3241 | static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) |
26f7cbc0 VP |
3242 | { |
3243 | int ret = 0; | |
3244 | ||
3245 | /* | |
3246 | * If a legitimate mailbox is provided, issue a RESET command | |
3247 | * with a HALT indication. | |
3248 | */ | |
b2e1a3f0 | 3249 | if (mbox <= PCIE_FW_MASTER_M) { |
26f7cbc0 VP |
3250 | struct fw_reset_cmd c; |
3251 | ||
3252 | memset(&c, 0, sizeof(c)); | |
3253 | INIT_CMD(c, RESET, WRITE); | |
0d804338 | 3254 | c.val = htonl(PIORST_F | PIORSTMODE_F); |
5167865a | 3255 | c.halt_pkd = htonl(FW_RESET_CMD_HALT_F); |
26f7cbc0 VP |
3256 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
3257 | } | |
3258 | ||
3259 | /* | |
3260 | * Normally we won't complete the operation if the firmware RESET | |
3261 | * command fails but if our caller insists we'll go ahead and put the | |
3262 | * uP into RESET. This can be useful if the firmware is hung or even | |
3263 | * missing ... We'll have to take the risk of putting the uP into | |
3264 | * RESET without the cooperation of firmware in that case. | |
3265 | * | |
3266 | * We also force the firmware's HALT flag to be on in case we bypassed | |
3267 | * the firmware RESET command above or we're dealing with old firmware | |
3268 | * which doesn't have the HALT capability. This will serve as a flag | |
3269 | * for the incoming firmware to know that it's coming out of a HALT | |
3270 | * rather than a RESET ... if it's new enough to understand that ... | |
3271 | */ | |
3272 | if (ret == 0 || force) { | |
89c3a86c | 3273 | t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); |
f061de42 | 3274 | t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, |
b2e1a3f0 | 3275 | PCIE_FW_HALT_F); |
26f7cbc0 VP |
3276 | } |
3277 | ||
3278 | /* | |
3279 | * And we always return the result of the firmware RESET command | |
3280 | * even when we force the uP into RESET ... | |
3281 | */ | |
3282 | return ret; | |
3283 | } | |
3284 | ||
3285 | /** | |
3286 | * t4_fw_restart - restart the firmware by taking the uP out of RESET | |
3287 | * @adap: the adapter | |
3288 | * @reset: if we want to do a RESET to restart things | |
3289 | * | |
3290 | * Restart firmware previously halted by t4_fw_halt(). On successful | |
3291 | * return the previous PF Master remains as the new PF Master and there | |
3292 | * is no need to issue a new HELLO command, etc. | |
3293 | * | |
3294 | * We do this in two ways: | |
3295 | * | |
3296 | * 1. If we're dealing with newer firmware we'll simply want to take | |
3297 | * the chip's microprocessor out of RESET. This will cause the | |
3298 | * firmware to start up from its start vector. And then we'll loop | |
3299 | * until the firmware indicates it's started again (PCIE_FW.HALT | |
3300 | * reset to 0) or we timeout. | |
3301 | * | |
3302 | * 2. If we're dealing with older firmware then we'll need to RESET | |
3303 | * the chip since older firmware won't recognize the PCIE_FW.HALT | |
3304 | * flag and automatically RESET itself on startup. | |
3305 | */ | |
de5b8677 | 3306 | static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) |
26f7cbc0 VP |
3307 | { |
3308 | if (reset) { | |
3309 | /* | |
3310 | * Since we're directing the RESET instead of the firmware | |
3311 | * doing it automatically, we need to clear the PCIE_FW.HALT | |
3312 | * bit. | |
3313 | */ | |
f061de42 | 3314 | t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0); |
26f7cbc0 VP |
3315 | |
3316 | /* | |
3317 | * If we've been given a valid mailbox, first try to get the | |
3318 | * firmware to do the RESET. If that works, great and we can | |
3319 | * return success. Otherwise, if we haven't been given a | |
3320 | * valid mailbox or the RESET command failed, fall back to | |
3321 | * hitting the chip with a hammer. | |
3322 | */ | |
b2e1a3f0 | 3323 | if (mbox <= PCIE_FW_MASTER_M) { |
89c3a86c | 3324 | t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); |
26f7cbc0 VP |
3325 | msleep(100); |
3326 | if (t4_fw_reset(adap, mbox, | |
0d804338 | 3327 | PIORST_F | PIORSTMODE_F) == 0) |
26f7cbc0 VP |
3328 | return 0; |
3329 | } | |
3330 | ||
0d804338 | 3331 | t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F); |
26f7cbc0 VP |
3332 | msleep(2000); |
3333 | } else { | |
3334 | int ms; | |
3335 | ||
89c3a86c | 3336 | t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); |
26f7cbc0 | 3337 | for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { |
f061de42 | 3338 | if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F)) |
26f7cbc0 VP |
3339 | return 0; |
3340 | msleep(100); | |
3341 | ms += 100; | |
3342 | } | |
3343 | return -ETIMEDOUT; | |
3344 | } | |
3345 | return 0; | |
3346 | } | |
3347 | ||
3348 | /** | |
3349 | * t4_fw_upgrade - perform all of the steps necessary to upgrade FW | |
3350 | * @adap: the adapter | |
3351 | * @mbox: mailbox to use for the FW RESET command (if desired) | |
3352 | * @fw_data: the firmware image to write | |
3353 | * @size: image size | |
3354 | * @force: force upgrade even if firmware doesn't cooperate | |
3355 | * | |
3356 | * Perform all of the steps necessary for upgrading an adapter's | |
3357 | * firmware image. Normally this requires the cooperation of the | |
3358 | * existing firmware in order to halt all existing activities | |
3359 | * but if an invalid mailbox token is passed in we skip that step | |
3360 | * (though we'll still put the adapter microprocessor into RESET in | |
3361 | * that case). | |
3362 | * | |
3363 | * On successful return the new firmware will have been loaded and | |
3364 | * the adapter will have been fully RESET losing all previous setup | |
3365 | * state. On unsuccessful return the adapter may be completely hosed ... | |
3366 | * positive errno indicates that the adapter is ~probably~ intact, a | |
3367 | * negative errno indicates that things are looking bad ... | |
3368 | */ | |
22c0b963 HS |
3369 | int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, |
3370 | const u8 *fw_data, unsigned int size, int force) | |
26f7cbc0 VP |
3371 | { |
3372 | const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; | |
3373 | int reset, ret; | |
3374 | ||
79af221d HS |
3375 | if (!t4_fw_matches_chip(adap, fw_hdr)) |
3376 | return -EINVAL; | |
3377 | ||
26f7cbc0 VP |
3378 | ret = t4_fw_halt(adap, mbox, force); |
3379 | if (ret < 0 && !force) | |
3380 | return ret; | |
3381 | ||
3382 | ret = t4_load_fw(adap, fw_data, size); | |
3383 | if (ret < 0) | |
3384 | return ret; | |
3385 | ||
3386 | /* | |
3387 | * Older versions of the firmware don't understand the new | |
3388 | * PCIE_FW.HALT flag and so won't know to perform a RESET when they | |
3389 | * restart. So for newly loaded older firmware we'll have to do the | |
3390 | * RESET for it so it starts up on a clean slate. We can tell if | |
3391 | * the newly loaded firmware will handle this right by checking | |
3392 | * its header flags to see if it advertises the capability. | |
3393 | */ | |
3394 | reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); | |
3395 | return t4_fw_restart(adap, mbox, reset); | |
3396 | } | |
3397 | ||
636f9d37 VP |
3398 | /** |
3399 | * t4_fixup_host_params - fix up host-dependent parameters | |
3400 | * @adap: the adapter | |
3401 | * @page_size: the host's Base Page Size | |
3402 | * @cache_line_size: the host's Cache Line Size | |
3403 | * | |
3404 | * Various registers in T4 contain values which are dependent on the | |
3405 | * host's Base Page and Cache Line Sizes. This function will fix all of | |
3406 | * those registers with the appropriate values as passed in ... | |
3407 | */ | |
3408 | int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, | |
3409 | unsigned int cache_line_size) | |
3410 | { | |
3411 | unsigned int page_shift = fls(page_size) - 1; | |
3412 | unsigned int sge_hps = page_shift - 10; | |
3413 | unsigned int stat_len = cache_line_size > 64 ? 128 : 64; | |
3414 | unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; | |
3415 | unsigned int fl_align_log = fls(fl_align) - 1; | |
3416 | ||
f612b815 HS |
3417 | t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, |
3418 | HOSTPAGESIZEPF0_V(sge_hps) | | |
3419 | HOSTPAGESIZEPF1_V(sge_hps) | | |
3420 | HOSTPAGESIZEPF2_V(sge_hps) | | |
3421 | HOSTPAGESIZEPF3_V(sge_hps) | | |
3422 | HOSTPAGESIZEPF4_V(sge_hps) | | |
3423 | HOSTPAGESIZEPF5_V(sge_hps) | | |
3424 | HOSTPAGESIZEPF6_V(sge_hps) | | |
3425 | HOSTPAGESIZEPF7_V(sge_hps)); | |
636f9d37 | 3426 | |
ce8f407a | 3427 | if (is_t4(adap->params.chip)) { |
f612b815 HS |
3428 | t4_set_reg_field(adap, SGE_CONTROL_A, |
3429 | INGPADBOUNDARY_V(INGPADBOUNDARY_M) | | |
3430 | EGRSTATUSPAGESIZE_F, | |
3431 | INGPADBOUNDARY_V(fl_align_log - | |
3432 | INGPADBOUNDARY_SHIFT_X) | | |
3433 | EGRSTATUSPAGESIZE_V(stat_len != 64)); | |
ce8f407a HS |
3434 | } else { |
3435 | /* T5 introduced the separation of the Free List Padding and | |
3436 | * Packing Boundaries. Thus, we can select a smaller Padding | |
3437 | * Boundary to avoid uselessly chewing up PCIe Link and Memory | |
3438 | * Bandwidth, and use a Packing Boundary which is large enough | |
3439 | * to avoid false sharing between CPUs, etc. | |
3440 | * | |
3441 | * For the PCI Link, the smaller the Padding Boundary the | |
3442 | * better. For the Memory Controller, a smaller Padding | |
3443 | * Boundary is better until we cross under the Memory Line | |
3444 | * Size (the minimum unit of transfer to/from Memory). If we | |
3445 | * have a Padding Boundary which is smaller than the Memory | |
3446 | * Line Size, that'll involve a Read-Modify-Write cycle on the | |
3447 | * Memory Controller which is never good. For T5 the smallest | |
3448 | * Padding Boundary which we can select is 32 bytes which is | |
3449 | * larger than any known Memory Controller Line Size so we'll | |
3450 | * use that. | |
3451 | * | |
3452 | * T5 has a different interpretation of the "0" value for the | |
3453 | * Packing Boundary. This corresponds to 16 bytes instead of | |
3454 | * the expected 32 bytes. We never have a Packing Boundary | |
3455 | * less than 32 bytes so we can't use that special value but | |
3456 | * on the other hand, if we wanted 32 bytes, the best we can | |
3457 | * really do is 64 bytes. | |
3458 | */ | |
3459 | if (fl_align <= 32) { | |
3460 | fl_align = 64; | |
3461 | fl_align_log = 6; | |
3462 | } | |
f612b815 HS |
3463 | t4_set_reg_field(adap, SGE_CONTROL_A, |
3464 | INGPADBOUNDARY_V(INGPADBOUNDARY_M) | | |
3465 | EGRSTATUSPAGESIZE_F, | |
3466 | INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) | | |
3467 | EGRSTATUSPAGESIZE_V(stat_len != 64)); | |
ce8f407a HS |
3468 | t4_set_reg_field(adap, SGE_CONTROL2_A, |
3469 | INGPACKBOUNDARY_V(INGPACKBOUNDARY_M), | |
3470 | INGPACKBOUNDARY_V(fl_align_log - | |
f612b815 | 3471 | INGPACKBOUNDARY_SHIFT_X)); |
ce8f407a | 3472 | } |
636f9d37 VP |
3473 | /* |
3474 | * Adjust various SGE Free List Host Buffer Sizes. | |
3475 | * | |
3476 | * This is something of a crock since we're using fixed indices into | |
3477 | * the array which are also known by the sge.c code and the T4 | |
3478 | * Firmware Configuration File. We need to come up with a much better | |
3479 | * approach to managing this array. For now, the first four entries | |
3480 | * are: | |
3481 | * | |
3482 | * 0: Host Page Size | |
3483 | * 1: 64KB | |
3484 | * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode) | |
3485 | * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode) | |
3486 | * | |
3487 | * For the single-MTU buffers in unpacked mode we need to include | |
3488 | * space for the SGE Control Packet Shift, 14 byte Ethernet header, | |
3489 | * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet | |
3490 | * Padding boundry. All of these are accommodated in the Factory | |
3491 | * Default Firmware Configuration File but we need to adjust it for | |
3492 | * this host's cache line size. | |
3493 | */ | |
f612b815 HS |
3494 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size); |
3495 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A, | |
3496 | (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) | |
636f9d37 | 3497 | & ~(fl_align-1)); |
f612b815 HS |
3498 | t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A, |
3499 | (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) | |
636f9d37 VP |
3500 | & ~(fl_align-1)); |
3501 | ||
0d804338 | 3502 | t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); |
636f9d37 VP |
3503 | |
3504 | return 0; | |
3505 | } | |
3506 | ||
3507 | /** | |
3508 | * t4_fw_initialize - ask FW to initialize the device | |
3509 | * @adap: the adapter | |
3510 | * @mbox: mailbox to use for the FW command | |
3511 | * | |
3512 | * Issues a command to FW to partially initialize the device. This | |
3513 | * performs initialization that generally doesn't depend on user input. | |
3514 | */ | |
3515 | int t4_fw_initialize(struct adapter *adap, unsigned int mbox) | |
3516 | { | |
3517 | struct fw_initialize_cmd c; | |
3518 | ||
3519 | memset(&c, 0, sizeof(c)); | |
3520 | INIT_CMD(c, INITIALIZE, WRITE); | |
3521 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
3522 | } | |
3523 | ||
56d36be4 DM |
3524 | /** |
3525 | * t4_query_params - query FW or device parameters | |
3526 | * @adap: the adapter | |
3527 | * @mbox: mailbox to use for the FW command | |
3528 | * @pf: the PF | |
3529 | * @vf: the VF | |
3530 | * @nparams: the number of parameters | |
3531 | * @params: the parameter names | |
3532 | * @val: the parameter values | |
3533 | * | |
3534 | * Reads the value of FW or device parameters. Up to 7 parameters can be | |
3535 | * queried at once. | |
3536 | */ | |
3537 | int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
3538 | unsigned int vf, unsigned int nparams, const u32 *params, | |
3539 | u32 *val) | |
3540 | { | |
3541 | int i, ret; | |
3542 | struct fw_params_cmd c; | |
3543 | __be32 *p = &c.param[0].mnem; | |
3544 | ||
3545 | if (nparams > 7) | |
3546 | return -EINVAL; | |
3547 | ||
3548 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 3549 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PARAMS_CMD) | FW_CMD_REQUEST_F | |
5167865a HS |
3550 | FW_CMD_READ_F | FW_PARAMS_CMD_PFN_V(pf) | |
3551 | FW_PARAMS_CMD_VFN_V(vf)); | |
56d36be4 DM |
3552 | c.retval_len16 = htonl(FW_LEN16(c)); |
3553 | for (i = 0; i < nparams; i++, p += 2) | |
3554 | *p = htonl(*params++); | |
3555 | ||
3556 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
3557 | if (ret == 0) | |
3558 | for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) | |
3559 | *val++ = ntohl(*p); | |
3560 | return ret; | |
3561 | } | |
3562 | ||
688848b1 AB |
3563 | /** |
3564 | * t4_set_params_nosleep - sets FW or device parameters | |
3565 | * @adap: the adapter | |
3566 | * @mbox: mailbox to use for the FW command | |
3567 | * @pf: the PF | |
3568 | * @vf: the VF | |
3569 | * @nparams: the number of parameters | |
3570 | * @params: the parameter names | |
3571 | * @val: the parameter values | |
3572 | * | |
3573 | * Does not ever sleep | |
3574 | * Sets the value of FW or device parameters. Up to 7 parameters can be | |
3575 | * specified at once. | |
3576 | */ | |
3577 | int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox, | |
3578 | unsigned int pf, unsigned int vf, | |
3579 | unsigned int nparams, const u32 *params, | |
3580 | const u32 *val) | |
3581 | { | |
3582 | struct fw_params_cmd c; | |
3583 | __be32 *p = &c.param[0].mnem; | |
3584 | ||
3585 | if (nparams > 7) | |
3586 | return -EINVAL; | |
3587 | ||
3588 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
3589 | c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | |
3590 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F | | |
5167865a HS |
3591 | FW_PARAMS_CMD_PFN_V(pf) | |
3592 | FW_PARAMS_CMD_VFN_V(vf)); | |
688848b1 AB |
3593 | c.retval_len16 = cpu_to_be32(FW_LEN16(c)); |
3594 | ||
3595 | while (nparams--) { | |
3596 | *p++ = cpu_to_be32(*params++); | |
3597 | *p++ = cpu_to_be32(*val++); | |
3598 | } | |
3599 | ||
3600 | return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); | |
3601 | } | |
3602 | ||
56d36be4 DM |
3603 | /** |
3604 | * t4_set_params - sets FW or device parameters | |
3605 | * @adap: the adapter | |
3606 | * @mbox: mailbox to use for the FW command | |
3607 | * @pf: the PF | |
3608 | * @vf: the VF | |
3609 | * @nparams: the number of parameters | |
3610 | * @params: the parameter names | |
3611 | * @val: the parameter values | |
3612 | * | |
3613 | * Sets the value of FW or device parameters. Up to 7 parameters can be | |
3614 | * specified at once. | |
3615 | */ | |
3616 | int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
3617 | unsigned int vf, unsigned int nparams, const u32 *params, | |
3618 | const u32 *val) | |
3619 | { | |
3620 | struct fw_params_cmd c; | |
3621 | __be32 *p = &c.param[0].mnem; | |
3622 | ||
3623 | if (nparams > 7) | |
3624 | return -EINVAL; | |
3625 | ||
3626 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 3627 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PARAMS_CMD) | FW_CMD_REQUEST_F | |
5167865a HS |
3628 | FW_CMD_WRITE_F | FW_PARAMS_CMD_PFN_V(pf) | |
3629 | FW_PARAMS_CMD_VFN_V(vf)); | |
56d36be4 DM |
3630 | c.retval_len16 = htonl(FW_LEN16(c)); |
3631 | while (nparams--) { | |
3632 | *p++ = htonl(*params++); | |
3633 | *p++ = htonl(*val++); | |
3634 | } | |
3635 | ||
3636 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
3637 | } | |
3638 | ||
3639 | /** | |
3640 | * t4_cfg_pfvf - configure PF/VF resource limits | |
3641 | * @adap: the adapter | |
3642 | * @mbox: mailbox to use for the FW command | |
3643 | * @pf: the PF being configured | |
3644 | * @vf: the VF being configured | |
3645 | * @txq: the max number of egress queues | |
3646 | * @txq_eth_ctrl: the max number of egress Ethernet or control queues | |
3647 | * @rxqi: the max number of interrupt-capable ingress queues | |
3648 | * @rxq: the max number of interruptless ingress queues | |
3649 | * @tc: the PCI traffic class | |
3650 | * @vi: the max number of virtual interfaces | |
3651 | * @cmask: the channel access rights mask for the PF/VF | |
3652 | * @pmask: the port access rights mask for the PF/VF | |
3653 | * @nexact: the maximum number of exact MPS filters | |
3654 | * @rcaps: read capabilities | |
3655 | * @wxcaps: write/execute capabilities | |
3656 | * | |
3657 | * Configures resource limits and capabilities for a physical or virtual | |
3658 | * function. | |
3659 | */ | |
3660 | int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
3661 | unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, | |
3662 | unsigned int rxqi, unsigned int rxq, unsigned int tc, | |
3663 | unsigned int vi, unsigned int cmask, unsigned int pmask, | |
3664 | unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) | |
3665 | { | |
3666 | struct fw_pfvf_cmd c; | |
3667 | ||
3668 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 3669 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F | |
5167865a HS |
3670 | FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) | |
3671 | FW_PFVF_CMD_VFN_V(vf)); | |
56d36be4 | 3672 | c.retval_len16 = htonl(FW_LEN16(c)); |
5167865a HS |
3673 | c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT_V(rxqi) | |
3674 | FW_PFVF_CMD_NIQ_V(rxq)); | |
3675 | c.type_to_neq = htonl(FW_PFVF_CMD_CMASK_V(cmask) | | |
3676 | FW_PFVF_CMD_PMASK_V(pmask) | | |
3677 | FW_PFVF_CMD_NEQ_V(txq)); | |
3678 | c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC_V(tc) | FW_PFVF_CMD_NVI_V(vi) | | |
3679 | FW_PFVF_CMD_NEXACTF_V(nexact)); | |
3680 | c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS_V(rcaps) | | |
3681 | FW_PFVF_CMD_WX_CAPS_V(wxcaps) | | |
3682 | FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl)); | |
56d36be4 DM |
3683 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
3684 | } | |
3685 | ||
3686 | /** | |
3687 | * t4_alloc_vi - allocate a virtual interface | |
3688 | * @adap: the adapter | |
3689 | * @mbox: mailbox to use for the FW command | |
3690 | * @port: physical port associated with the VI | |
3691 | * @pf: the PF owning the VI | |
3692 | * @vf: the VF owning the VI | |
3693 | * @nmac: number of MAC addresses needed (1 to 5) | |
3694 | * @mac: the MAC addresses of the VI | |
3695 | * @rss_size: size of RSS table slice associated with this VI | |
3696 | * | |
3697 | * Allocates a virtual interface for the given physical port. If @mac is | |
3698 | * not %NULL it contains the MAC addresses of the VI as assigned by FW. | |
3699 | * @mac should be large enough to hold @nmac Ethernet addresses, they are | |
3700 | * stored consecutively so the space needed is @nmac * 6 bytes. | |
3701 | * Returns a negative error number or the non-negative VI id. | |
3702 | */ | |
3703 | int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, | |
3704 | unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, | |
3705 | unsigned int *rss_size) | |
3706 | { | |
3707 | int ret; | |
3708 | struct fw_vi_cmd c; | |
3709 | ||
3710 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
3711 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F | |
3712 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
2b5fb1f2 HS |
3713 | FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf)); |
3714 | c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC_F | FW_LEN16(c)); | |
3715 | c.portid_pkd = FW_VI_CMD_PORTID_V(port); | |
56d36be4 DM |
3716 | c.nmac = nmac - 1; |
3717 | ||
3718 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
3719 | if (ret) | |
3720 | return ret; | |
3721 | ||
3722 | if (mac) { | |
3723 | memcpy(mac, c.mac, sizeof(c.mac)); | |
3724 | switch (nmac) { | |
3725 | case 5: | |
3726 | memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); | |
3727 | case 4: | |
3728 | memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); | |
3729 | case 3: | |
3730 | memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); | |
3731 | case 2: | |
3732 | memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); | |
3733 | } | |
3734 | } | |
3735 | if (rss_size) | |
2b5fb1f2 HS |
3736 | *rss_size = FW_VI_CMD_RSSSIZE_G(ntohs(c.rsssize_pkd)); |
3737 | return FW_VI_CMD_VIID_G(ntohs(c.type_viid)); | |
56d36be4 DM |
3738 | } |
3739 | ||
56d36be4 DM |
3740 | /** |
3741 | * t4_set_rxmode - set Rx properties of a virtual interface | |
3742 | * @adap: the adapter | |
3743 | * @mbox: mailbox to use for the FW command | |
3744 | * @viid: the VI id | |
3745 | * @mtu: the new MTU or -1 | |
3746 | * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change | |
3747 | * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change | |
3748 | * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change | |
f8f5aafa | 3749 | * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change |
56d36be4 DM |
3750 | * @sleep_ok: if true we may sleep while awaiting command completion |
3751 | * | |
3752 | * Sets Rx properties of a virtual interface. | |
3753 | */ | |
3754 | int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
f8f5aafa DM |
3755 | int mtu, int promisc, int all_multi, int bcast, int vlanex, |
3756 | bool sleep_ok) | |
56d36be4 DM |
3757 | { |
3758 | struct fw_vi_rxmode_cmd c; | |
3759 | ||
3760 | /* convert to FW values */ | |
3761 | if (mtu < 0) | |
3762 | mtu = FW_RXMODE_MTU_NO_CHG; | |
3763 | if (promisc < 0) | |
2b5fb1f2 | 3764 | promisc = FW_VI_RXMODE_CMD_PROMISCEN_M; |
56d36be4 | 3765 | if (all_multi < 0) |
2b5fb1f2 | 3766 | all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M; |
56d36be4 | 3767 | if (bcast < 0) |
2b5fb1f2 | 3768 | bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M; |
f8f5aafa | 3769 | if (vlanex < 0) |
2b5fb1f2 | 3770 | vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M; |
56d36be4 DM |
3771 | |
3772 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 3773 | c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST_F | |
2b5fb1f2 | 3774 | FW_CMD_WRITE_F | FW_VI_RXMODE_CMD_VIID_V(viid)); |
56d36be4 | 3775 | c.retval_len16 = htonl(FW_LEN16(c)); |
2b5fb1f2 HS |
3776 | c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU_V(mtu) | |
3777 | FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) | | |
3778 | FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) | | |
3779 | FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) | | |
3780 | FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex)); | |
56d36be4 DM |
3781 | return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); |
3782 | } | |
3783 | ||
3784 | /** | |
3785 | * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses | |
3786 | * @adap: the adapter | |
3787 | * @mbox: mailbox to use for the FW command | |
3788 | * @viid: the VI id | |
3789 | * @free: if true any existing filters for this VI id are first removed | |
3790 | * @naddr: the number of MAC addresses to allocate filters for (up to 7) | |
3791 | * @addr: the MAC address(es) | |
3792 | * @idx: where to store the index of each allocated filter | |
3793 | * @hash: pointer to hash address filter bitmap | |
3794 | * @sleep_ok: call is allowed to sleep | |
3795 | * | |
3796 | * Allocates an exact-match filter for each of the supplied addresses and | |
3797 | * sets it to the corresponding address. If @idx is not %NULL it should | |
3798 | * have at least @naddr entries, each of which will be set to the index of | |
3799 | * the filter allocated for the corresponding MAC address. If a filter | |
3800 | * could not be allocated for an address its index is set to 0xffff. | |
3801 | * If @hash is not %NULL addresses that fail to allocate an exact filter | |
3802 | * are hashed and update the hash filter bitmap pointed at by @hash. | |
3803 | * | |
3804 | * Returns a negative error number or the number of filters allocated. | |
3805 | */ | |
3806 | int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, | |
3807 | unsigned int viid, bool free, unsigned int naddr, | |
3808 | const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) | |
3809 | { | |
3810 | int i, ret; | |
3811 | struct fw_vi_mac_cmd c; | |
3812 | struct fw_vi_mac_exact *p; | |
d14807dd | 3813 | unsigned int max_naddr = is_t4(adap->params.chip) ? |
0a57a536 SR |
3814 | NUM_MPS_CLS_SRAM_L_INSTANCES : |
3815 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; | |
56d36be4 DM |
3816 | |
3817 | if (naddr > 7) | |
3818 | return -EINVAL; | |
3819 | ||
3820 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
3821 | c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F | |
3822 | FW_CMD_WRITE_F | (free ? FW_CMD_EXEC_F : 0) | | |
2b5fb1f2 HS |
3823 | FW_VI_MAC_CMD_VIID_V(viid)); |
3824 | c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS_V(free) | | |
e2ac9628 | 3825 | FW_CMD_LEN16_V((naddr + 2) / 2)); |
56d36be4 DM |
3826 | |
3827 | for (i = 0, p = c.u.exact; i < naddr; i++, p++) { | |
2b5fb1f2 HS |
3828 | p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID_F | |
3829 | FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC)); | |
56d36be4 DM |
3830 | memcpy(p->macaddr, addr[i], sizeof(p->macaddr)); |
3831 | } | |
3832 | ||
3833 | ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); | |
3834 | if (ret) | |
3835 | return ret; | |
3836 | ||
3837 | for (i = 0, p = c.u.exact; i < naddr; i++, p++) { | |
2b5fb1f2 | 3838 | u16 index = FW_VI_MAC_CMD_IDX_G(ntohs(p->valid_to_idx)); |
56d36be4 DM |
3839 | |
3840 | if (idx) | |
0a57a536 SR |
3841 | idx[i] = index >= max_naddr ? 0xffff : index; |
3842 | if (index < max_naddr) | |
56d36be4 DM |
3843 | ret++; |
3844 | else if (hash) | |
ce9aeb58 | 3845 | *hash |= (1ULL << hash_mac_addr(addr[i])); |
56d36be4 DM |
3846 | } |
3847 | return ret; | |
3848 | } | |
3849 | ||
3850 | /** | |
3851 | * t4_change_mac - modifies the exact-match filter for a MAC address | |
3852 | * @adap: the adapter | |
3853 | * @mbox: mailbox to use for the FW command | |
3854 | * @viid: the VI id | |
3855 | * @idx: index of existing filter for old value of MAC address, or -1 | |
3856 | * @addr: the new MAC address value | |
3857 | * @persist: whether a new MAC allocation should be persistent | |
3858 | * @add_smt: if true also add the address to the HW SMT | |
3859 | * | |
3860 | * Modifies an exact-match filter and sets it to the new MAC address. | |
3861 | * Note that in general it is not possible to modify the value of a given | |
3862 | * filter so the generic way to modify an address filter is to free the one | |
3863 | * being used by the old address value and allocate a new filter for the | |
3864 | * new address value. @idx can be -1 if the address is a new addition. | |
3865 | * | |
3866 | * Returns a negative error number or the index of the filter with the new | |
3867 | * MAC value. | |
3868 | */ | |
3869 | int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
3870 | int idx, const u8 *addr, bool persist, bool add_smt) | |
3871 | { | |
3872 | int ret, mode; | |
3873 | struct fw_vi_mac_cmd c; | |
3874 | struct fw_vi_mac_exact *p = c.u.exact; | |
d14807dd | 3875 | unsigned int max_mac_addr = is_t4(adap->params.chip) ? |
0a57a536 SR |
3876 | NUM_MPS_CLS_SRAM_L_INSTANCES : |
3877 | NUM_MPS_T5_CLS_SRAM_L_INSTANCES; | |
56d36be4 DM |
3878 | |
3879 | if (idx < 0) /* new allocation */ | |
3880 | idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; | |
3881 | mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; | |
3882 | ||
3883 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 3884 | c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F | |
2b5fb1f2 | 3885 | FW_CMD_WRITE_F | FW_VI_MAC_CMD_VIID_V(viid)); |
e2ac9628 | 3886 | c.freemacs_to_len16 = htonl(FW_CMD_LEN16_V(1)); |
2b5fb1f2 HS |
3887 | p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID_F | |
3888 | FW_VI_MAC_CMD_SMAC_RESULT_V(mode) | | |
3889 | FW_VI_MAC_CMD_IDX_V(idx)); | |
56d36be4 DM |
3890 | memcpy(p->macaddr, addr, sizeof(p->macaddr)); |
3891 | ||
3892 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
3893 | if (ret == 0) { | |
2b5fb1f2 | 3894 | ret = FW_VI_MAC_CMD_IDX_G(ntohs(p->valid_to_idx)); |
0a57a536 | 3895 | if (ret >= max_mac_addr) |
56d36be4 DM |
3896 | ret = -ENOMEM; |
3897 | } | |
3898 | return ret; | |
3899 | } | |
3900 | ||
3901 | /** | |
3902 | * t4_set_addr_hash - program the MAC inexact-match hash filter | |
3903 | * @adap: the adapter | |
3904 | * @mbox: mailbox to use for the FW command | |
3905 | * @viid: the VI id | |
3906 | * @ucast: whether the hash filter should also match unicast addresses | |
3907 | * @vec: the value to be written to the hash filter | |
3908 | * @sleep_ok: call is allowed to sleep | |
3909 | * | |
3910 | * Sets the 64-bit inexact-match hash filter for a virtual interface. | |
3911 | */ | |
3912 | int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
3913 | bool ucast, u64 vec, bool sleep_ok) | |
3914 | { | |
3915 | struct fw_vi_mac_cmd c; | |
3916 | ||
3917 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 3918 | c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F | |
2b5fb1f2 HS |
3919 | FW_CMD_WRITE_F | FW_VI_ENABLE_CMD_VIID_V(viid)); |
3920 | c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN_F | | |
3921 | FW_VI_MAC_CMD_HASHUNIEN_V(ucast) | | |
e2ac9628 | 3922 | FW_CMD_LEN16_V(1)); |
56d36be4 DM |
3923 | c.u.hash.hashvec = cpu_to_be64(vec); |
3924 | return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); | |
3925 | } | |
3926 | ||
688848b1 AB |
3927 | /** |
3928 | * t4_enable_vi_params - enable/disable a virtual interface | |
3929 | * @adap: the adapter | |
3930 | * @mbox: mailbox to use for the FW command | |
3931 | * @viid: the VI id | |
3932 | * @rx_en: 1=enable Rx, 0=disable Rx | |
3933 | * @tx_en: 1=enable Tx, 0=disable Tx | |
3934 | * @dcb_en: 1=enable delivery of Data Center Bridging messages. | |
3935 | * | |
3936 | * Enables/disables a virtual interface. Note that setting DCB Enable | |
3937 | * only makes sense when enabling a Virtual Interface ... | |
3938 | */ | |
3939 | int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, | |
3940 | unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) | |
3941 | { | |
3942 | struct fw_vi_enable_cmd c; | |
3943 | ||
3944 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 3945 | c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST_F | |
2b5fb1f2 | 3946 | FW_CMD_EXEC_F | FW_VI_ENABLE_CMD_VIID_V(viid)); |
688848b1 | 3947 | |
2b5fb1f2 HS |
3948 | c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN_V(rx_en) | |
3949 | FW_VI_ENABLE_CMD_EEN_V(tx_en) | FW_LEN16(c) | | |
3950 | FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en)); | |
30f00847 | 3951 | return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); |
688848b1 AB |
3952 | } |
3953 | ||
56d36be4 DM |
3954 | /** |
3955 | * t4_enable_vi - enable/disable a virtual interface | |
3956 | * @adap: the adapter | |
3957 | * @mbox: mailbox to use for the FW command | |
3958 | * @viid: the VI id | |
3959 | * @rx_en: 1=enable Rx, 0=disable Rx | |
3960 | * @tx_en: 1=enable Tx, 0=disable Tx | |
3961 | * | |
3962 | * Enables/disables a virtual interface. | |
3963 | */ | |
3964 | int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
3965 | bool rx_en, bool tx_en) | |
3966 | { | |
688848b1 | 3967 | return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); |
56d36be4 DM |
3968 | } |
3969 | ||
3970 | /** | |
3971 | * t4_identify_port - identify a VI's port by blinking its LED | |
3972 | * @adap: the adapter | |
3973 | * @mbox: mailbox to use for the FW command | |
3974 | * @viid: the VI id | |
3975 | * @nblinks: how many times to blink LED at 2.5 Hz | |
3976 | * | |
3977 | * Identifies a VI's port by blinking its LED. | |
3978 | */ | |
3979 | int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, | |
3980 | unsigned int nblinks) | |
3981 | { | |
3982 | struct fw_vi_enable_cmd c; | |
3983 | ||
0062b15c | 3984 | memset(&c, 0, sizeof(c)); |
e2ac9628 | 3985 | c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST_F | |
2b5fb1f2 HS |
3986 | FW_CMD_EXEC_F | FW_VI_ENABLE_CMD_VIID_V(viid)); |
3987 | c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c)); | |
56d36be4 DM |
3988 | c.blinkdur = htons(nblinks); |
3989 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
56d36be4 DM |
3990 | } |
3991 | ||
3992 | /** | |
3993 | * t4_iq_free - free an ingress queue and its FLs | |
3994 | * @adap: the adapter | |
3995 | * @mbox: mailbox to use for the FW command | |
3996 | * @pf: the PF owning the queues | |
3997 | * @vf: the VF owning the queues | |
3998 | * @iqtype: the ingress queue type | |
3999 | * @iqid: ingress queue id | |
4000 | * @fl0id: FL0 queue id or 0xffff if no attached FL0 | |
4001 | * @fl1id: FL1 queue id or 0xffff if no attached FL1 | |
4002 | * | |
4003 | * Frees an ingress queue and its associated FLs, if any. | |
4004 | */ | |
4005 | int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
4006 | unsigned int vf, unsigned int iqtype, unsigned int iqid, | |
4007 | unsigned int fl0id, unsigned int fl1id) | |
4008 | { | |
4009 | struct fw_iq_cmd c; | |
4010 | ||
4011 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 4012 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F | |
6e4b51a6 HS |
4013 | FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) | |
4014 | FW_IQ_CMD_VFN_V(vf)); | |
4015 | c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE_F | FW_LEN16(c)); | |
4016 | c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(iqtype)); | |
56d36be4 DM |
4017 | c.iqid = htons(iqid); |
4018 | c.fl0id = htons(fl0id); | |
4019 | c.fl1id = htons(fl1id); | |
4020 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); | |
4021 | } | |
4022 | ||
4023 | /** | |
4024 | * t4_eth_eq_free - free an Ethernet egress queue | |
4025 | * @adap: the adapter | |
4026 | * @mbox: mailbox to use for the FW command | |
4027 | * @pf: the PF owning the queue | |
4028 | * @vf: the VF owning the queue | |
4029 | * @eqid: egress queue id | |
4030 | * | |
4031 | * Frees an Ethernet egress queue. | |
4032 | */ | |
4033 | int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
4034 | unsigned int vf, unsigned int eqid) | |
4035 | { | |
4036 | struct fw_eq_eth_cmd c; | |
4037 | ||
4038 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 4039 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F | |
6e4b51a6 HS |
4040 | FW_CMD_EXEC_F | FW_EQ_ETH_CMD_PFN_V(pf) | |
4041 | FW_EQ_ETH_CMD_VFN_V(vf)); | |
4042 | c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c)); | |
4043 | c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID_V(eqid)); | |
56d36be4 DM |
4044 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
4045 | } | |
4046 | ||
4047 | /** | |
4048 | * t4_ctrl_eq_free - free a control egress queue | |
4049 | * @adap: the adapter | |
4050 | * @mbox: mailbox to use for the FW command | |
4051 | * @pf: the PF owning the queue | |
4052 | * @vf: the VF owning the queue | |
4053 | * @eqid: egress queue id | |
4054 | * | |
4055 | * Frees a control egress queue. | |
4056 | */ | |
4057 | int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
4058 | unsigned int vf, unsigned int eqid) | |
4059 | { | |
4060 | struct fw_eq_ctrl_cmd c; | |
4061 | ||
4062 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 4063 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F | |
6e4b51a6 HS |
4064 | FW_CMD_EXEC_F | FW_EQ_CTRL_CMD_PFN_V(pf) | |
4065 | FW_EQ_CTRL_CMD_VFN_V(vf)); | |
4066 | c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c)); | |
4067 | c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID_V(eqid)); | |
56d36be4 DM |
4068 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
4069 | } | |
4070 | ||
4071 | /** | |
4072 | * t4_ofld_eq_free - free an offload egress queue | |
4073 | * @adap: the adapter | |
4074 | * @mbox: mailbox to use for the FW command | |
4075 | * @pf: the PF owning the queue | |
4076 | * @vf: the VF owning the queue | |
4077 | * @eqid: egress queue id | |
4078 | * | |
4079 | * Frees a control egress queue. | |
4080 | */ | |
4081 | int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, | |
4082 | unsigned int vf, unsigned int eqid) | |
4083 | { | |
4084 | struct fw_eq_ofld_cmd c; | |
4085 | ||
4086 | memset(&c, 0, sizeof(c)); | |
e2ac9628 | 4087 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F | |
6e4b51a6 HS |
4088 | FW_CMD_EXEC_F | FW_EQ_OFLD_CMD_PFN_V(pf) | |
4089 | FW_EQ_OFLD_CMD_VFN_V(vf)); | |
4090 | c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c)); | |
4091 | c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID_V(eqid)); | |
56d36be4 DM |
4092 | return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); |
4093 | } | |
4094 | ||
4095 | /** | |
4096 | * t4_handle_fw_rpl - process a FW reply message | |
4097 | * @adap: the adapter | |
4098 | * @rpl: start of the FW message | |
4099 | * | |
4100 | * Processes a FW message, such as link state change messages. | |
4101 | */ | |
4102 | int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) | |
4103 | { | |
4104 | u8 opcode = *(const u8 *)rpl; | |
4105 | ||
4106 | if (opcode == FW_PORT_CMD) { /* link/module state change message */ | |
4107 | int speed = 0, fc = 0; | |
4108 | const struct fw_port_cmd *p = (void *)rpl; | |
2b5fb1f2 | 4109 | int chan = FW_PORT_CMD_PORTID_G(ntohl(p->op_to_portid)); |
56d36be4 DM |
4110 | int port = adap->chan_map[chan]; |
4111 | struct port_info *pi = adap2pinfo(adap, port); | |
4112 | struct link_config *lc = &pi->link_cfg; | |
4113 | u32 stat = ntohl(p->u.info.lstatus_to_modtype); | |
2b5fb1f2 HS |
4114 | int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0; |
4115 | u32 mod = FW_PORT_CMD_MODTYPE_G(stat); | |
56d36be4 | 4116 | |
2b5fb1f2 | 4117 | if (stat & FW_PORT_CMD_RXPAUSE_F) |
56d36be4 | 4118 | fc |= PAUSE_RX; |
2b5fb1f2 | 4119 | if (stat & FW_PORT_CMD_TXPAUSE_F) |
56d36be4 | 4120 | fc |= PAUSE_TX; |
2b5fb1f2 | 4121 | if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M)) |
e8b39015 | 4122 | speed = 100; |
2b5fb1f2 | 4123 | else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G)) |
e8b39015 | 4124 | speed = 1000; |
2b5fb1f2 | 4125 | else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G)) |
e8b39015 | 4126 | speed = 10000; |
2b5fb1f2 | 4127 | else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G)) |
e8b39015 | 4128 | speed = 40000; |
56d36be4 DM |
4129 | |
4130 | if (link_ok != lc->link_ok || speed != lc->speed || | |
4131 | fc != lc->fc) { /* something changed */ | |
4132 | lc->link_ok = link_ok; | |
4133 | lc->speed = speed; | |
4134 | lc->fc = fc; | |
444018a7 | 4135 | lc->supported = be16_to_cpu(p->u.info.pcap); |
56d36be4 DM |
4136 | t4_os_link_changed(adap, port, link_ok); |
4137 | } | |
4138 | if (mod != pi->mod_type) { | |
4139 | pi->mod_type = mod; | |
4140 | t4_os_portmod_changed(adap, port); | |
4141 | } | |
4142 | } | |
4143 | return 0; | |
4144 | } | |
4145 | ||
1dd06ae8 | 4146 | static void get_pci_mode(struct adapter *adapter, struct pci_params *p) |
56d36be4 DM |
4147 | { |
4148 | u16 val; | |
56d36be4 | 4149 | |
e5c8ae5f JL |
4150 | if (pci_is_pcie(adapter->pdev)) { |
4151 | pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); | |
56d36be4 DM |
4152 | p->speed = val & PCI_EXP_LNKSTA_CLS; |
4153 | p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; | |
4154 | } | |
4155 | } | |
4156 | ||
4157 | /** | |
4158 | * init_link_config - initialize a link's SW state | |
4159 | * @lc: structure holding the link state | |
4160 | * @caps: link capabilities | |
4161 | * | |
4162 | * Initializes the SW state maintained for each link, including the link's | |
4163 | * capabilities and default speed/flow-control/autonegotiation settings. | |
4164 | */ | |
1dd06ae8 | 4165 | static void init_link_config(struct link_config *lc, unsigned int caps) |
56d36be4 DM |
4166 | { |
4167 | lc->supported = caps; | |
4168 | lc->requested_speed = 0; | |
4169 | lc->speed = 0; | |
4170 | lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; | |
4171 | if (lc->supported & FW_PORT_CAP_ANEG) { | |
4172 | lc->advertising = lc->supported & ADVERT_MASK; | |
4173 | lc->autoneg = AUTONEG_ENABLE; | |
4174 | lc->requested_fc |= PAUSE_AUTONEG; | |
4175 | } else { | |
4176 | lc->advertising = 0; | |
4177 | lc->autoneg = AUTONEG_DISABLE; | |
4178 | } | |
4179 | } | |
4180 | ||
8203b509 HS |
4181 | #define CIM_PF_NOACCESS 0xeeeeeeee |
4182 | ||
4183 | int t4_wait_dev_ready(void __iomem *regs) | |
56d36be4 | 4184 | { |
8203b509 HS |
4185 | u32 whoami; |
4186 | ||
0d804338 | 4187 | whoami = readl(regs + PL_WHOAMI_A); |
8203b509 | 4188 | if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS) |
56d36be4 | 4189 | return 0; |
8203b509 | 4190 | |
56d36be4 | 4191 | msleep(500); |
0d804338 | 4192 | whoami = readl(regs + PL_WHOAMI_A); |
8203b509 | 4193 | return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO); |
56d36be4 DM |
4194 | } |
4195 | ||
fe2ee139 HS |
4196 | struct flash_desc { |
4197 | u32 vendor_and_model_id; | |
4198 | u32 size_mb; | |
4199 | }; | |
4200 | ||
91744948 | 4201 | static int get_flash_params(struct adapter *adap) |
900a6596 | 4202 | { |
fe2ee139 HS |
4203 | /* Table for non-Numonix supported flash parts. Numonix parts are left |
4204 | * to the preexisting code. All flash parts have 64KB sectors. | |
4205 | */ | |
4206 | static struct flash_desc supported_flash[] = { | |
4207 | { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ | |
4208 | }; | |
4209 | ||
900a6596 DM |
4210 | int ret; |
4211 | u32 info; | |
4212 | ||
4213 | ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); | |
4214 | if (!ret) | |
4215 | ret = sf1_read(adap, 3, 0, 1, &info); | |
0d804338 | 4216 | t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */ |
900a6596 DM |
4217 | if (ret) |
4218 | return ret; | |
4219 | ||
fe2ee139 HS |
4220 | for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret) |
4221 | if (supported_flash[ret].vendor_and_model_id == info) { | |
4222 | adap->params.sf_size = supported_flash[ret].size_mb; | |
4223 | adap->params.sf_nsec = | |
4224 | adap->params.sf_size / SF_SEC_SIZE; | |
4225 | return 0; | |
4226 | } | |
4227 | ||
900a6596 DM |
4228 | if ((info & 0xff) != 0x20) /* not a Numonix flash */ |
4229 | return -EINVAL; | |
4230 | info >>= 16; /* log2 of size */ | |
4231 | if (info >= 0x14 && info < 0x18) | |
4232 | adap->params.sf_nsec = 1 << (info - 16); | |
4233 | else if (info == 0x18) | |
4234 | adap->params.sf_nsec = 64; | |
4235 | else | |
4236 | return -EINVAL; | |
4237 | adap->params.sf_size = 1 << info; | |
4238 | adap->params.sf_fw_start = | |
89c3a86c | 4239 | t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M; |
c290607e HS |
4240 | |
4241 | if (adap->params.sf_size < FLASH_MIN_SIZE) | |
4242 | dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n", | |
4243 | adap->params.sf_size, FLASH_MIN_SIZE); | |
900a6596 DM |
4244 | return 0; |
4245 | } | |
4246 | ||
56d36be4 DM |
4247 | /** |
4248 | * t4_prep_adapter - prepare SW and HW for operation | |
4249 | * @adapter: the adapter | |
4250 | * @reset: if true perform a HW reset | |
4251 | * | |
4252 | * Initialize adapter SW state for the various HW modules, set initial | |
4253 | * values for some adapter tunables, take PHYs out of reset, and | |
4254 | * initialize the MDIO interface. | |
4255 | */ | |
91744948 | 4256 | int t4_prep_adapter(struct adapter *adapter) |
56d36be4 | 4257 | { |
0a57a536 SR |
4258 | int ret, ver; |
4259 | uint16_t device_id; | |
d14807dd | 4260 | u32 pl_rev; |
56d36be4 | 4261 | |
56d36be4 | 4262 | get_pci_mode(adapter, &adapter->params.pci); |
0d804338 | 4263 | pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A)); |
56d36be4 | 4264 | |
900a6596 DM |
4265 | ret = get_flash_params(adapter); |
4266 | if (ret < 0) { | |
4267 | dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret); | |
4268 | return ret; | |
4269 | } | |
4270 | ||
0a57a536 SR |
4271 | /* Retrieve adapter's device ID |
4272 | */ | |
4273 | pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id); | |
4274 | ver = device_id >> 12; | |
d14807dd | 4275 | adapter->params.chip = 0; |
0a57a536 SR |
4276 | switch (ver) { |
4277 | case CHELSIO_T4: | |
d14807dd | 4278 | adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); |
0a57a536 SR |
4279 | break; |
4280 | case CHELSIO_T5: | |
d14807dd | 4281 | adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); |
0a57a536 SR |
4282 | break; |
4283 | default: | |
4284 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | |
4285 | device_id); | |
4286 | return -EINVAL; | |
4287 | } | |
4288 | ||
f1ff24aa | 4289 | adapter->params.cim_la_size = CIMLA_SIZE; |
56d36be4 DM |
4290 | init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); |
4291 | ||
4292 | /* | |
4293 | * Default port for debugging in case we can't reach FW. | |
4294 | */ | |
4295 | adapter->params.nports = 1; | |
4296 | adapter->params.portvec = 1; | |
636f9d37 | 4297 | adapter->params.vpd.cclk = 50000; |
56d36be4 DM |
4298 | return 0; |
4299 | } | |
4300 | ||
e85c9a7a | 4301 | /** |
dd0bcc0b | 4302 | * cxgb4_t4_bar2_sge_qregs - return BAR2 SGE Queue register information |
e85c9a7a HS |
4303 | * @adapter: the adapter |
4304 | * @qid: the Queue ID | |
4305 | * @qtype: the Ingress or Egress type for @qid | |
4306 | * @pbar2_qoffset: BAR2 Queue Offset | |
4307 | * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues | |
4308 | * | |
4309 | * Returns the BAR2 SGE Queue Registers information associated with the | |
4310 | * indicated Absolute Queue ID. These are passed back in return value | |
4311 | * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue | |
4312 | * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. | |
4313 | * | |
4314 | * This may return an error which indicates that BAR2 SGE Queue | |
4315 | * registers aren't available. If an error is not returned, then the | |
4316 | * following values are returned: | |
4317 | * | |
4318 | * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers | |
4319 | * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid | |
4320 | * | |
4321 | * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which | |
4322 | * require the "Inferred Queue ID" ability may be used. E.g. the | |
4323 | * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, | |
4324 | * then these "Inferred Queue ID" register may not be used. | |
4325 | */ | |
dd0bcc0b | 4326 | int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter, |
e85c9a7a HS |
4327 | unsigned int qid, |
4328 | enum t4_bar2_qtype qtype, | |
4329 | u64 *pbar2_qoffset, | |
4330 | unsigned int *pbar2_qid) | |
4331 | { | |
4332 | unsigned int page_shift, page_size, qpp_shift, qpp_mask; | |
4333 | u64 bar2_page_offset, bar2_qoffset; | |
4334 | unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; | |
4335 | ||
4336 | /* T4 doesn't support BAR2 SGE Queue registers. | |
4337 | */ | |
4338 | if (is_t4(adapter->params.chip)) | |
4339 | return -EINVAL; | |
4340 | ||
4341 | /* Get our SGE Page Size parameters. | |
4342 | */ | |
4343 | page_shift = adapter->params.sge.hps + 10; | |
4344 | page_size = 1 << page_shift; | |
4345 | ||
4346 | /* Get the right Queues per Page parameters for our Queue. | |
4347 | */ | |
4348 | qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS | |
4349 | ? adapter->params.sge.eq_qpp | |
4350 | : adapter->params.sge.iq_qpp); | |
4351 | qpp_mask = (1 << qpp_shift) - 1; | |
4352 | ||
4353 | /* Calculate the basics of the BAR2 SGE Queue register area: | |
4354 | * o The BAR2 page the Queue registers will be in. | |
4355 | * o The BAR2 Queue ID. | |
4356 | * o The BAR2 Queue ID Offset into the BAR2 page. | |
4357 | */ | |
4358 | bar2_page_offset = ((qid >> qpp_shift) << page_shift); | |
4359 | bar2_qid = qid & qpp_mask; | |
4360 | bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; | |
4361 | ||
4362 | /* If the BAR2 Queue ID Offset is less than the Page Size, then the | |
4363 | * hardware will infer the Absolute Queue ID simply from the writes to | |
4364 | * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a | |
4365 | * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply | |
4366 | * write to the first BAR2 SGE Queue Area within the BAR2 Page with | |
4367 | * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID | |
4368 | * from the BAR2 Page and BAR2 Queue ID. | |
4369 | * | |
4370 | * One important censequence of this is that some BAR2 SGE registers | |
4371 | * have a "Queue ID" field and we can write the BAR2 SGE Queue ID | |
4372 | * there. But other registers synthesize the SGE Queue ID purely | |
4373 | * from the writes to the registers -- the Write Combined Doorbell | |
4374 | * Buffer is a good example. These BAR2 SGE Registers are only | |
4375 | * available for those BAR2 SGE Register areas where the SGE Absolute | |
4376 | * Queue ID can be inferred from simple writes. | |
4377 | */ | |
4378 | bar2_qoffset = bar2_page_offset; | |
4379 | bar2_qinferred = (bar2_qid_offset < page_size); | |
4380 | if (bar2_qinferred) { | |
4381 | bar2_qoffset += bar2_qid_offset; | |
4382 | bar2_qid = 0; | |
4383 | } | |
4384 | ||
4385 | *pbar2_qoffset = bar2_qoffset; | |
4386 | *pbar2_qid = bar2_qid; | |
4387 | return 0; | |
4388 | } | |
4389 | ||
4390 | /** | |
4391 | * t4_init_sge_params - initialize adap->params.sge | |
4392 | * @adapter: the adapter | |
4393 | * | |
4394 | * Initialize various fields of the adapter's SGE Parameters structure. | |
4395 | */ | |
4396 | int t4_init_sge_params(struct adapter *adapter) | |
4397 | { | |
4398 | struct sge_params *sge_params = &adapter->params.sge; | |
4399 | u32 hps, qpp; | |
4400 | unsigned int s_hps, s_qpp; | |
4401 | ||
4402 | /* Extract the SGE Page Size for our PF. | |
4403 | */ | |
f612b815 | 4404 | hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A); |
e85c9a7a HS |
4405 | s_hps = (HOSTPAGESIZEPF0_S + |
4406 | (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->fn); | |
4407 | sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M); | |
4408 | ||
4409 | /* Extract the SGE Egress and Ingess Queues Per Page for our PF. | |
4410 | */ | |
4411 | s_qpp = (QUEUESPERPAGEPF0_S + | |
4412 | (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn); | |
f612b815 HS |
4413 | qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A); |
4414 | sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); | |
f061de42 | 4415 | qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A); |
f612b815 | 4416 | sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); |
e85c9a7a HS |
4417 | |
4418 | return 0; | |
4419 | } | |
4420 | ||
dcf7b6f5 KS |
4421 | /** |
4422 | * t4_init_tp_params - initialize adap->params.tp | |
4423 | * @adap: the adapter | |
4424 | * | |
4425 | * Initialize various fields of the adapter's TP Parameters structure. | |
4426 | */ | |
4427 | int t4_init_tp_params(struct adapter *adap) | |
4428 | { | |
4429 | int chan; | |
4430 | u32 v; | |
4431 | ||
837e4a42 HS |
4432 | v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); |
4433 | adap->params.tp.tre = TIMERRESOLUTION_G(v); | |
4434 | adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); | |
dcf7b6f5 KS |
4435 | |
4436 | /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ | |
4437 | for (chan = 0; chan < NCHAN; chan++) | |
4438 | adap->params.tp.tx_modq[chan] = chan; | |
4439 | ||
4440 | /* Cache the adapter's Compressed Filter Mode and global Incress | |
4441 | * Configuration. | |
4442 | */ | |
837e4a42 | 4443 | t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
dcf7b6f5 | 4444 | &adap->params.tp.vlan_pri_map, 1, |
837e4a42 HS |
4445 | TP_VLAN_PRI_MAP_A); |
4446 | t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, | |
dcf7b6f5 | 4447 | &adap->params.tp.ingress_config, 1, |
837e4a42 | 4448 | TP_INGRESS_CONFIG_A); |
dcf7b6f5 KS |
4449 | |
4450 | /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field | |
4451 | * shift positions of several elements of the Compressed Filter Tuple | |
4452 | * for this adapter which we need frequently ... | |
4453 | */ | |
0d804338 HS |
4454 | adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); |
4455 | adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); | |
4456 | adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); | |
dcf7b6f5 | 4457 | adap->params.tp.protocol_shift = t4_filter_field_shift(adap, |
0d804338 | 4458 | PROTOCOL_F); |
dcf7b6f5 KS |
4459 | |
4460 | /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID | |
4461 | * represents the presense of an Outer VLAN instead of a VNIC ID. | |
4462 | */ | |
0d804338 | 4463 | if ((adap->params.tp.ingress_config & VNIC_F) == 0) |
dcf7b6f5 KS |
4464 | adap->params.tp.vnic_shift = -1; |
4465 | ||
4466 | return 0; | |
4467 | } | |
4468 | ||
4469 | /** | |
4470 | * t4_filter_field_shift - calculate filter field shift | |
4471 | * @adap: the adapter | |
4472 | * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) | |
4473 | * | |
4474 | * Return the shift position of a filter field within the Compressed | |
4475 | * Filter Tuple. The filter field is specified via its selection bit | |
4476 | * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. | |
4477 | */ | |
4478 | int t4_filter_field_shift(const struct adapter *adap, int filter_sel) | |
4479 | { | |
4480 | unsigned int filter_mode = adap->params.tp.vlan_pri_map; | |
4481 | unsigned int sel; | |
4482 | int field_shift; | |
4483 | ||
4484 | if ((filter_mode & filter_sel) == 0) | |
4485 | return -1; | |
4486 | ||
4487 | for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { | |
4488 | switch (filter_mode & sel) { | |
0d804338 HS |
4489 | case FCOE_F: |
4490 | field_shift += FT_FCOE_W; | |
dcf7b6f5 | 4491 | break; |
0d804338 HS |
4492 | case PORT_F: |
4493 | field_shift += FT_PORT_W; | |
dcf7b6f5 | 4494 | break; |
0d804338 HS |
4495 | case VNIC_ID_F: |
4496 | field_shift += FT_VNIC_ID_W; | |
dcf7b6f5 | 4497 | break; |
0d804338 HS |
4498 | case VLAN_F: |
4499 | field_shift += FT_VLAN_W; | |
dcf7b6f5 | 4500 | break; |
0d804338 HS |
4501 | case TOS_F: |
4502 | field_shift += FT_TOS_W; | |
dcf7b6f5 | 4503 | break; |
0d804338 HS |
4504 | case PROTOCOL_F: |
4505 | field_shift += FT_PROTOCOL_W; | |
dcf7b6f5 | 4506 | break; |
0d804338 HS |
4507 | case ETHERTYPE_F: |
4508 | field_shift += FT_ETHERTYPE_W; | |
dcf7b6f5 | 4509 | break; |
0d804338 HS |
4510 | case MACMATCH_F: |
4511 | field_shift += FT_MACMATCH_W; | |
dcf7b6f5 | 4512 | break; |
0d804338 HS |
4513 | case MPSHITTYPE_F: |
4514 | field_shift += FT_MPSHITTYPE_W; | |
dcf7b6f5 | 4515 | break; |
0d804338 HS |
4516 | case FRAGMENTATION_F: |
4517 | field_shift += FT_FRAGMENTATION_W; | |
dcf7b6f5 KS |
4518 | break; |
4519 | } | |
4520 | } | |
4521 | return field_shift; | |
4522 | } | |
4523 | ||
91744948 | 4524 | int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) |
56d36be4 DM |
4525 | { |
4526 | u8 addr[6]; | |
4527 | int ret, i, j = 0; | |
4528 | struct fw_port_cmd c; | |
f796564a | 4529 | struct fw_rss_vi_config_cmd rvc; |
56d36be4 DM |
4530 | |
4531 | memset(&c, 0, sizeof(c)); | |
f796564a | 4532 | memset(&rvc, 0, sizeof(rvc)); |
56d36be4 DM |
4533 | |
4534 | for_each_port(adap, i) { | |
4535 | unsigned int rss_size; | |
4536 | struct port_info *p = adap2pinfo(adap, i); | |
4537 | ||
4538 | while ((adap->params.portvec & (1 << j)) == 0) | |
4539 | j++; | |
4540 | ||
e2ac9628 HS |
4541 | c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) | |
4542 | FW_CMD_REQUEST_F | FW_CMD_READ_F | | |
2b5fb1f2 | 4543 | FW_PORT_CMD_PORTID_V(j)); |
56d36be4 | 4544 | c.action_to_len16 = htonl( |
2b5fb1f2 | 4545 | FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) | |
56d36be4 DM |
4546 | FW_LEN16(c)); |
4547 | ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); | |
4548 | if (ret) | |
4549 | return ret; | |
4550 | ||
4551 | ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); | |
4552 | if (ret < 0) | |
4553 | return ret; | |
4554 | ||
4555 | p->viid = ret; | |
4556 | p->tx_chan = j; | |
4557 | p->lport = j; | |
4558 | p->rss_size = rss_size; | |
4559 | memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); | |
40c9f8ab | 4560 | adap->port[i]->dev_port = j; |
56d36be4 DM |
4561 | |
4562 | ret = ntohl(c.u.info.lstatus_to_modtype); | |
2b5fb1f2 HS |
4563 | p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ? |
4564 | FW_PORT_CMD_MDIOADDR_G(ret) : -1; | |
4565 | p->port_type = FW_PORT_CMD_PTYPE_G(ret); | |
a0881cab | 4566 | p->mod_type = FW_PORT_MOD_TYPE_NA; |
56d36be4 | 4567 | |
e2ac9628 HS |
4568 | rvc.op_to_viid = htonl(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | |
4569 | FW_CMD_REQUEST_F | FW_CMD_READ_F | | |
f796564a DM |
4570 | FW_RSS_VI_CONFIG_CMD_VIID(p->viid)); |
4571 | rvc.retval_len16 = htonl(FW_LEN16(rvc)); | |
4572 | ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); | |
4573 | if (ret) | |
4574 | return ret; | |
4575 | p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen); | |
4576 | ||
56d36be4 DM |
4577 | init_link_config(&p->link_cfg, ntohs(c.u.info.pcap)); |
4578 | j++; | |
4579 | } | |
4580 | return 0; | |
4581 | } | |
f1ff24aa | 4582 | |
74b3092c HS |
4583 | /** |
4584 | * t4_read_cimq_cfg - read CIM queue configuration | |
4585 | * @adap: the adapter | |
4586 | * @base: holds the queue base addresses in bytes | |
4587 | * @size: holds the queue sizes in bytes | |
4588 | * @thres: holds the queue full thresholds in bytes | |
4589 | * | |
4590 | * Returns the current configuration of the CIM queues, starting with | |
4591 | * the IBQs, then the OBQs. | |
4592 | */ | |
4593 | void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) | |
4594 | { | |
4595 | unsigned int i, v; | |
4596 | int cim_num_obq = is_t4(adap->params.chip) ? | |
4597 | CIM_NUM_OBQ : CIM_NUM_OBQ_T5; | |
4598 | ||
4599 | for (i = 0; i < CIM_NUM_IBQ; i++) { | |
4600 | t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F | | |
4601 | QUENUMSELECT_V(i)); | |
4602 | v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); | |
4603 | /* value is in 256-byte units */ | |
4604 | *base++ = CIMQBASE_G(v) * 256; | |
4605 | *size++ = CIMQSIZE_G(v) * 256; | |
4606 | *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */ | |
4607 | } | |
4608 | for (i = 0; i < cim_num_obq; i++) { | |
4609 | t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | | |
4610 | QUENUMSELECT_V(i)); | |
4611 | v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); | |
4612 | /* value is in 256-byte units */ | |
4613 | *base++ = CIMQBASE_G(v) * 256; | |
4614 | *size++ = CIMQSIZE_G(v) * 256; | |
4615 | } | |
4616 | } | |
4617 | ||
e5f0e43b HS |
4618 | /** |
4619 | * t4_read_cim_ibq - read the contents of a CIM inbound queue | |
4620 | * @adap: the adapter | |
4621 | * @qid: the queue index | |
4622 | * @data: where to store the queue contents | |
4623 | * @n: capacity of @data in 32-bit words | |
4624 | * | |
4625 | * Reads the contents of the selected CIM queue starting at address 0 up | |
4626 | * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on | |
4627 | * error and the number of 32-bit words actually read on success. | |
4628 | */ | |
4629 | int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) | |
4630 | { | |
4631 | int i, err, attempts; | |
4632 | unsigned int addr; | |
4633 | const unsigned int nwords = CIM_IBQ_SIZE * 4; | |
4634 | ||
4635 | if (qid > 5 || (n & 3)) | |
4636 | return -EINVAL; | |
4637 | ||
4638 | addr = qid * nwords; | |
4639 | if (n > nwords) | |
4640 | n = nwords; | |
4641 | ||
4642 | /* It might take 3-10ms before the IBQ debug read access is allowed. | |
4643 | * Wait for 1 Sec with a delay of 1 usec. | |
4644 | */ | |
4645 | attempts = 1000000; | |
4646 | ||
4647 | for (i = 0; i < n; i++, addr++) { | |
4648 | t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | | |
4649 | IBQDBGEN_F); | |
4650 | err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0, | |
4651 | attempts, 1); | |
4652 | if (err) | |
4653 | return err; | |
4654 | *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A); | |
4655 | } | |
4656 | t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0); | |
c778af7d HS |
4657 | return i; |
4658 | } | |
4659 | ||
4660 | /** | |
4661 | * t4_read_cim_obq - read the contents of a CIM outbound queue | |
4662 | * @adap: the adapter | |
4663 | * @qid: the queue index | |
4664 | * @data: where to store the queue contents | |
4665 | * @n: capacity of @data in 32-bit words | |
4666 | * | |
4667 | * Reads the contents of the selected CIM queue starting at address 0 up | |
4668 | * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on | |
4669 | * error and the number of 32-bit words actually read on success. | |
4670 | */ | |
4671 | int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) | |
4672 | { | |
4673 | int i, err; | |
4674 | unsigned int addr, v, nwords; | |
4675 | int cim_num_obq = is_t4(adap->params.chip) ? | |
4676 | CIM_NUM_OBQ : CIM_NUM_OBQ_T5; | |
4677 | ||
4678 | if ((qid > (cim_num_obq - 1)) || (n & 3)) | |
4679 | return -EINVAL; | |
4680 | ||
4681 | t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | | |
4682 | QUENUMSELECT_V(qid)); | |
4683 | v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); | |
4684 | ||
4685 | addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */ | |
4686 | nwords = CIMQSIZE_G(v) * 64; /* same */ | |
4687 | if (n > nwords) | |
4688 | n = nwords; | |
4689 | ||
4690 | for (i = 0; i < n; i++, addr++) { | |
4691 | t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | | |
4692 | OBQDBGEN_F); | |
4693 | err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, | |
4694 | 2, 1); | |
4695 | if (err) | |
4696 | return err; | |
4697 | *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A); | |
4698 | } | |
4699 | t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0); | |
e5f0e43b HS |
4700 | return i; |
4701 | } | |
4702 | ||
f1ff24aa HS |
4703 | /** |
4704 | * t4_cim_read - read a block from CIM internal address space | |
4705 | * @adap: the adapter | |
4706 | * @addr: the start address within the CIM address space | |
4707 | * @n: number of words to read | |
4708 | * @valp: where to store the result | |
4709 | * | |
4710 | * Reads a block of 4-byte words from the CIM intenal address space. | |
4711 | */ | |
4712 | int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, | |
4713 | unsigned int *valp) | |
4714 | { | |
4715 | int ret = 0; | |
4716 | ||
4717 | if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) | |
4718 | return -EBUSY; | |
4719 | ||
4720 | for ( ; !ret && n--; addr += 4) { | |
4721 | t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); | |
4722 | ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, | |
4723 | 0, 5, 2); | |
4724 | if (!ret) | |
4725 | *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A); | |
4726 | } | |
4727 | return ret; | |
4728 | } | |
4729 | ||
4730 | /** | |
4731 | * t4_cim_write - write a block into CIM internal address space | |
4732 | * @adap: the adapter | |
4733 | * @addr: the start address within the CIM address space | |
4734 | * @n: number of words to write | |
4735 | * @valp: set of values to write | |
4736 | * | |
4737 | * Writes a block of 4-byte words into the CIM intenal address space. | |
4738 | */ | |
4739 | int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, | |
4740 | const unsigned int *valp) | |
4741 | { | |
4742 | int ret = 0; | |
4743 | ||
4744 | if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) | |
4745 | return -EBUSY; | |
4746 | ||
4747 | for ( ; !ret && n--; addr += 4) { | |
4748 | t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++); | |
4749 | t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); | |
4750 | ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, | |
4751 | 0, 5, 2); | |
4752 | } | |
4753 | return ret; | |
4754 | } | |
4755 | ||
4756 | static int t4_cim_write1(struct adapter *adap, unsigned int addr, | |
4757 | unsigned int val) | |
4758 | { | |
4759 | return t4_cim_write(adap, addr, 1, &val); | |
4760 | } | |
4761 | ||
4762 | /** | |
4763 | * t4_cim_read_la - read CIM LA capture buffer | |
4764 | * @adap: the adapter | |
4765 | * @la_buf: where to store the LA data | |
4766 | * @wrptr: the HW write pointer within the capture buffer | |
4767 | * | |
4768 | * Reads the contents of the CIM LA buffer with the most recent entry at | |
4769 | * the end of the returned data and with the entry at @wrptr first. | |
4770 | * We try to leave the LA in the running state we find it in. | |
4771 | */ | |
4772 | int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) | |
4773 | { | |
4774 | int i, ret; | |
4775 | unsigned int cfg, val, idx; | |
4776 | ||
4777 | ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); | |
4778 | if (ret) | |
4779 | return ret; | |
4780 | ||
4781 | if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */ | |
4782 | ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0); | |
4783 | if (ret) | |
4784 | return ret; | |
4785 | } | |
4786 | ||
4787 | ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); | |
4788 | if (ret) | |
4789 | goto restart; | |
4790 | ||
4791 | idx = UPDBGLAWRPTR_G(val); | |
4792 | if (wrptr) | |
4793 | *wrptr = idx; | |
4794 | ||
4795 | for (i = 0; i < adap->params.cim_la_size; i++) { | |
4796 | ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, | |
4797 | UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F); | |
4798 | if (ret) | |
4799 | break; | |
4800 | ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); | |
4801 | if (ret) | |
4802 | break; | |
4803 | if (val & UPDBGLARDEN_F) { | |
4804 | ret = -ETIMEDOUT; | |
4805 | break; | |
4806 | } | |
4807 | ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]); | |
4808 | if (ret) | |
4809 | break; | |
4810 | idx = (idx + 1) & UPDBGLARDPTR_M; | |
4811 | } | |
4812 | restart: | |
4813 | if (cfg & UPDBGLAEN_F) { | |
4814 | int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, | |
4815 | cfg & ~UPDBGLARDEN_F); | |
4816 | if (!ret) | |
4817 | ret = r; | |
4818 | } | |
4819 | return ret; | |
4820 | } | |
2d277b3b HS |
4821 | |
4822 | /** | |
4823 | * t4_tp_read_la - read TP LA capture buffer | |
4824 | * @adap: the adapter | |
4825 | * @la_buf: where to store the LA data | |
4826 | * @wrptr: the HW write pointer within the capture buffer | |
4827 | * | |
4828 | * Reads the contents of the TP LA buffer with the most recent entry at | |
4829 | * the end of the returned data and with the entry at @wrptr first. | |
4830 | * We leave the LA in the running state we find it in. | |
4831 | */ | |
4832 | void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) | |
4833 | { | |
4834 | bool last_incomplete; | |
4835 | unsigned int i, cfg, val, idx; | |
4836 | ||
4837 | cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff; | |
4838 | if (cfg & DBGLAENABLE_F) /* freeze LA */ | |
4839 | t4_write_reg(adap, TP_DBG_LA_CONFIG_A, | |
4840 | adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); | |
4841 | ||
4842 | val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); | |
4843 | idx = DBGLAWPTR_G(val); | |
4844 | last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0; | |
4845 | if (last_incomplete) | |
4846 | idx = (idx + 1) & DBGLARPTR_M; | |
4847 | if (wrptr) | |
4848 | *wrptr = idx; | |
4849 | ||
4850 | val &= 0xffff; | |
4851 | val &= ~DBGLARPTR_V(DBGLARPTR_M); | |
4852 | val |= adap->params.tp.la_mask; | |
4853 | ||
4854 | for (i = 0; i < TPLA_SIZE; i++) { | |
4855 | t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); | |
4856 | la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A); | |
4857 | idx = (idx + 1) & DBGLARPTR_M; | |
4858 | } | |
4859 | ||
4860 | /* Wipe out last entry if it isn't valid */ | |
4861 | if (last_incomplete) | |
4862 | la_buf[TPLA_SIZE - 1] = ~0ULL; | |
4863 | ||
4864 | if (cfg & DBGLAENABLE_F) /* restore running state */ | |
4865 | t4_write_reg(adap, TP_DBG_LA_CONFIG_A, | |
4866 | cfg | adap->params.tp.la_mask); | |
4867 | } |