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56d36be4 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
56d36be4 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #ifndef __T4_HW_H | |
36 | #define __T4_HW_H | |
37 | ||
38 | #include <linux/types.h> | |
39 | ||
40 | enum { | |
41 | NCHAN = 4, /* # of HW channels */ | |
42 | MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ | |
43 | EEPROMSIZE = 17408, /* Serial EEPROM physical size */ | |
44 | EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ | |
1478b3ee | 45 | EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ |
56d36be4 DM |
46 | RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ |
47 | TCB_SIZE = 128, /* TCB size */ | |
48 | NMTUS = 16, /* size of MTU table */ | |
49 | NCCTRL_WIN = 32, /* # of congestion control windows */ | |
56d36be4 | 50 | L2T_SIZE = 4096, /* # of L2T entries */ |
b3bbe36a | 51 | PM_NSTATS = 5, /* # of PM stats */ |
56d36be4 DM |
52 | MBOX_LEN = 64, /* mailbox size in bytes */ |
53 | TRACE_LEN = 112, /* length of trace data and mask */ | |
54 | FILTER_OPT_LEN = 36, /* filter tuple width for optional components */ | |
56d36be4 DM |
55 | }; |
56 | ||
f1ff24aa | 57 | enum { |
74b3092c HS |
58 | CIM_NUM_IBQ = 6, /* # of CIM IBQs */ |
59 | CIM_NUM_OBQ = 6, /* # of CIM OBQs */ | |
60 | CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ | |
f1ff24aa | 61 | CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ |
26fae93f | 62 | CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ |
e5f0e43b | 63 | CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ |
c778af7d | 64 | CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ |
2d277b3b | 65 | TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ |
797ff0f5 | 66 | ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ |
f1ff24aa HS |
67 | }; |
68 | ||
56d36be4 DM |
69 | enum { |
70 | SF_PAGE_SIZE = 256, /* serial flash page size */ | |
5afc8b84 | 71 | SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ |
56d36be4 DM |
72 | }; |
73 | ||
74 | enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ | |
75 | ||
76 | enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ | |
77 | ||
78 | enum { | |
79 | SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ | |
80 | SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ | |
81 | SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ | |
cf38be6d | 82 | SGE_MAX_IQ_SIZE = 65520, |
17edf259 CL |
83 | |
84 | SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */ | |
85 | SGE_TIMER_UPD_CIDX = 7, /* update cidx only */ | |
86 | ||
87 | SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */ | |
88 | ||
89 | SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */ | |
90 | SGE_INTRDST_IQ = 1, /* destination is an ingress queue */ | |
91 | ||
92 | SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */ | |
93 | SGE_UPDATEDEL_INTR = 1, /* interrupt */ | |
94 | SGE_UPDATEDEL_STPG = 2, /* status page */ | |
95 | SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */ | |
96 | ||
97 | SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */ | |
98 | SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */ | |
99 | SGE_HOSTFCMODE_STPG = 2, /* sent to status page */ | |
100 | SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */ | |
101 | ||
102 | SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */ | |
103 | SGE_FETCHBURSTMIN_32B = 1, | |
104 | SGE_FETCHBURSTMIN_64B = 2, | |
105 | SGE_FETCHBURSTMIN_128B = 3, | |
106 | ||
107 | SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */ | |
108 | SGE_FETCHBURSTMAX_128B = 1, | |
109 | SGE_FETCHBURSTMAX_256B = 2, | |
110 | SGE_FETCHBURSTMAX_512B = 3, | |
111 | ||
112 | SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */ | |
113 | SGE_CIDXFLUSHTHRESH_2 = 1, | |
114 | SGE_CIDXFLUSHTHRESH_4 = 2, | |
115 | SGE_CIDXFLUSHTHRESH_8 = 3, | |
116 | SGE_CIDXFLUSHTHRESH_16 = 4, | |
117 | SGE_CIDXFLUSHTHRESH_32 = 5, | |
118 | SGE_CIDXFLUSHTHRESH_64 = 6, | |
119 | SGE_CIDXFLUSHTHRESH_128 = 7, | |
120 | ||
121 | SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */ | |
56d36be4 DM |
122 | }; |
123 | ||
49aa284f HS |
124 | /* PCI-e memory window access */ |
125 | enum pcie_memwin { | |
126 | MEMWIN_NIC = 0, | |
127 | MEMWIN_RSVD1 = 1, | |
128 | MEMWIN_RSVD2 = 2, | |
129 | MEMWIN_RDMA = 3, | |
130 | MEMWIN_RSVD4 = 4, | |
131 | MEMWIN_FOISCSI = 5, | |
132 | MEMWIN_CSIOSTOR = 6, | |
133 | MEMWIN_RSVD7 = 7, | |
134 | }; | |
135 | ||
56d36be4 DM |
136 | struct sge_qstat { /* data written to SGE queue status entries */ |
137 | __be32 qid; | |
138 | __be16 cidx; | |
139 | __be16 pidx; | |
140 | }; | |
141 | ||
142 | /* | |
143 | * Structure for last 128 bits of response descriptors | |
144 | */ | |
145 | struct rsp_ctrl { | |
146 | __be32 hdrbuflen_pidx; | |
147 | __be32 pldbuflen_qid; | |
148 | union { | |
149 | u8 type_gen; | |
150 | __be64 last_flit; | |
151 | }; | |
152 | }; | |
153 | ||
1ecc7b7a HS |
154 | #define RSPD_NEWBUF_S 31 |
155 | #define RSPD_NEWBUF_V(x) ((x) << RSPD_NEWBUF_S) | |
156 | #define RSPD_NEWBUF_F RSPD_NEWBUF_V(1U) | |
56d36be4 | 157 | |
1ecc7b7a HS |
158 | #define RSPD_LEN_S 0 |
159 | #define RSPD_LEN_M 0x7fffffff | |
160 | #define RSPD_LEN_G(x) (((x) >> RSPD_LEN_S) & RSPD_LEN_M) | |
56d36be4 | 161 | |
1ecc7b7a HS |
162 | #define RSPD_QID_S RSPD_LEN_S |
163 | #define RSPD_QID_M RSPD_LEN_M | |
164 | #define RSPD_QID_G(x) RSPD_LEN_G(x) | |
165 | ||
166 | #define RSPD_GEN_S 7 | |
167 | ||
168 | #define RSPD_TYPE_S 4 | |
169 | #define RSPD_TYPE_M 0x3 | |
170 | #define RSPD_TYPE_G(x) (((x) >> RSPD_TYPE_S) & RSPD_TYPE_M) | |
171 | ||
172 | /* Rx queue interrupt deferral fields: counter enable and timer index */ | |
173 | #define QINTR_CNT_EN_S 0 | |
174 | #define QINTR_CNT_EN_V(x) ((x) << QINTR_CNT_EN_S) | |
175 | #define QINTR_CNT_EN_F QINTR_CNT_EN_V(1U) | |
176 | ||
177 | #define QINTR_TIMER_IDX_S 1 | |
178 | #define QINTR_TIMER_IDX_M 0x7 | |
179 | #define QINTR_TIMER_IDX_V(x) ((x) << QINTR_TIMER_IDX_S) | |
180 | #define QINTR_TIMER_IDX_G(x) (((x) >> QINTR_TIMER_IDX_S) & QINTR_TIMER_IDX_M) | |
5afc8b84 VP |
181 | |
182 | /* | |
183 | * Flash layout. | |
184 | */ | |
185 | #define FLASH_START(start) ((start) * SF_SEC_SIZE) | |
186 | #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) | |
187 | ||
188 | enum { | |
189 | /* | |
190 | * Various Expansion-ROM boot images, etc. | |
191 | */ | |
192 | FLASH_EXP_ROM_START_SEC = 0, | |
193 | FLASH_EXP_ROM_NSECS = 6, | |
194 | FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), | |
195 | FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), | |
196 | ||
197 | /* | |
198 | * iSCSI Boot Firmware Table (iBFT) and other driver-related | |
199 | * parameters ... | |
200 | */ | |
201 | FLASH_IBFT_START_SEC = 6, | |
202 | FLASH_IBFT_NSECS = 1, | |
203 | FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), | |
204 | FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), | |
205 | ||
206 | /* | |
207 | * Boot configuration data. | |
208 | */ | |
209 | FLASH_BOOTCFG_START_SEC = 7, | |
210 | FLASH_BOOTCFG_NSECS = 1, | |
211 | FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), | |
212 | FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), | |
213 | ||
214 | /* | |
215 | * Location of firmware image in FLASH. | |
216 | */ | |
217 | FLASH_FW_START_SEC = 8, | |
60d42bf6 | 218 | FLASH_FW_NSECS = 16, |
5afc8b84 VP |
219 | FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), |
220 | FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), | |
221 | ||
222 | /* | |
223 | * iSCSI persistent/crash information. | |
224 | */ | |
225 | FLASH_ISCSI_CRASH_START_SEC = 29, | |
226 | FLASH_ISCSI_CRASH_NSECS = 1, | |
227 | FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), | |
228 | FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), | |
229 | ||
230 | /* | |
231 | * FCoE persistent/crash information. | |
232 | */ | |
233 | FLASH_FCOE_CRASH_START_SEC = 30, | |
234 | FLASH_FCOE_CRASH_NSECS = 1, | |
235 | FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), | |
236 | FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), | |
237 | ||
238 | /* | |
239 | * Location of Firmware Configuration File in FLASH. Since the FPGA | |
240 | * "FLASH" is smaller we need to store the Configuration File in a | |
241 | * different location -- which will overlap the end of the firmware | |
242 | * image if firmware ever gets that large ... | |
243 | */ | |
244 | FLASH_CFG_START_SEC = 31, | |
245 | FLASH_CFG_NSECS = 1, | |
246 | FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), | |
247 | FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), | |
248 | ||
c290607e HS |
249 | /* We don't support FLASH devices which can't support the full |
250 | * standard set of sections which we need for normal | |
251 | * operations. | |
252 | */ | |
253 | FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE, | |
254 | ||
5afc8b84 VP |
255 | FLASH_FPGA_CFG_START_SEC = 15, |
256 | FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC), | |
257 | ||
258 | /* | |
259 | * Sectors 32-63 are reserved for FLASH failover. | |
260 | */ | |
261 | }; | |
262 | ||
263 | #undef FLASH_START | |
264 | #undef FLASH_MAX_SIZE | |
265 | ||
56d36be4 | 266 | #endif /* __T4_HW_H */ |