]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'mac80211-next-for-davem-2018-03-29' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_msg.h
CommitLineData
bbc02c7e
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
bbc02c7e
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __T4_MSG_H
36#define __T4_MSG_H
37
38#include <linux/types.h>
39
40enum {
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
45 CPL_GET_TCB = 0x6,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_ABORT_REQ = 0xA,
49 CPL_ABORT_RPL = 0xB,
50 CPL_RX_DATA_ACK = 0xD,
51 CPL_TX_PKT = 0xE,
52 CPL_L2T_WRITE_REQ = 0x12,
3bdb376e 53 CPL_SMT_WRITE_REQ = 0x14,
bbc02c7e 54 CPL_TID_RELEASE = 0x1A,
a3cdaa69 55 CPL_SRQ_TABLE_REQ = 0x1C,
b96c5cbb 56 CPL_TX_DATA_ISO = 0x1F,
bbc02c7e
DM		 57
58 CPL_CLOSE_LISTSRV_RPL = 0x20,
59 CPL_L2T_WRITE_RPL = 0x23,
60 CPL_PASS_OPEN_RPL = 0x24,
61 CPL_ACT_OPEN_RPL = 0x25,
62 CPL_PEER_CLOSE = 0x26,
63 CPL_ABORT_REQ_RSS = 0x2B,
64 CPL_ABORT_RPL_RSS = 0x2D,
3bdb376e 65 CPL_SMT_WRITE_RPL = 0x2E,
bbc02c7e 66
d6657781 67 CPL_RX_PHYS_ADDR = 0x30,
bbc02c7e
DM		 68 CPL_CLOSE_CON_RPL = 0x32,
69 CPL_ISCSI_HDR = 0x33,
70 CPL_RDMA_CQE = 0x35,
71 CPL_RDMA_CQE_READ_RSP = 0x36,
72 CPL_RDMA_CQE_ERR = 0x37,
73 CPL_RX_DATA = 0x39,
74 CPL_SET_TCB_RPL = 0x3A,
75 CPL_RX_PKT = 0x3B,
76 CPL_RX_DDP_COMPLETE = 0x3F,
77
78 CPL_ACT_ESTABLISH = 0x40,
79 CPL_PASS_ESTABLISH = 0x41,
80 CPL_RX_DATA_DDP = 0x42,
81 CPL_PASS_ACCEPT_REQ = 0x44,
44830d8f 82 CPL_RX_ISCSI_CMP = 0x45,
2422d9a3 83 CPL_TRACE_PKT_T5 = 0x48,
a2b81b35 84 CPL_RX_ISCSI_DDP = 0x49,
bbc02c7e
DM		 85
86 CPL_RDMA_READ_REQ = 0x60,
87
88 CPL_PASS_OPEN_REQ6 = 0x81,
89 CPL_ACT_OPEN_REQ6 = 0x83,
90
d6657781
HS		 91 CPL_TX_TLS_PDU = 0x88,
92 CPL_TX_SEC_PDU = 0x8A,
93 CPL_TX_TLS_ACK = 0x8B,
94
bbc02c7e
DM		 95 CPL_RDMA_TERMINATE = 0xA2,
96 CPL_RDMA_WRITE = 0xA4,
97 CPL_SGE_EGR_UPDATE = 0xA5,
a4569504 98 CPL_RX_MPS_PKT = 0xAF,
bbc02c7e
DM		 99
100 CPL_TRACE_PKT = 0xB0,
a2b81b35 101 CPL_ISCSI_DATA = 0xB2,
bbc02c7e
DM		 102
103 CPL_FW4_MSG = 0xC0,
104 CPL_FW4_PLD = 0xC1,
105 CPL_FW4_ACK = 0xC3,
a3cdaa69 106 CPL_SRQ_TABLE_RPL = 0xCC,
bbc02c7e 107
d6657781
HS		 108 CPL_RX_PHYS_DSGL = 0xD0,
109
bbc02c7e
DM		 110 CPL_FW6_MSG = 0xE0,
111 CPL_FW6_PLD = 0xE1,
ef0fd85a 112 CPL_TX_TNL_LSO = 0xEC,
bbc02c7e
DM		 113 CPL_TX_PKT_LSO = 0xED,
114 CPL_TX_PKT_XT = 0xEE,
115
116 NUM_CPL_CMDS
117};
118
119enum CPL_error {
120 CPL_ERR_NONE = 0,
4c72efef
H		 121 CPL_ERR_TCAM_PARITY = 1,
122 CPL_ERR_TCAM_MISS = 2,
bbc02c7e
DM		 123 CPL_ERR_TCAM_FULL = 3,
124 CPL_ERR_BAD_LENGTH = 15,
125 CPL_ERR_BAD_ROUTE = 18,
126 CPL_ERR_CONN_RESET = 20,
127 CPL_ERR_CONN_EXIST_SYNRECV = 21,
128 CPL_ERR_CONN_EXIST = 22,
129 CPL_ERR_ARP_MISS = 23,
130 CPL_ERR_BAD_SYN = 24,
131 CPL_ERR_CONN_TIMEDOUT = 30,
132 CPL_ERR_XMIT_TIMEDOUT = 31,
133 CPL_ERR_PERSIST_TIMEDOUT = 32,
134 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
135 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
136 CPL_ERR_RTX_NEG_ADVICE = 35,
137 CPL_ERR_PERSIST_NEG_ADVICE = 36,
7a2cea2a 138 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
bbc02c7e
DM		 139 CPL_ERR_ABORT_FAILED = 42,
140 CPL_ERR_IWARP_FLM = 50,
a3cdaa69
RR		 141 CPL_CONTAINS_READ_RPL = 60,
142 CPL_CONTAINS_WRITE_RPL = 61,
bbc02c7e
DM		 143};
144
6c53e938
HS		 145enum {
146 CPL_CONN_POLICY_AUTO = 0,
147 CPL_CONN_POLICY_ASK = 1,
148 CPL_CONN_POLICY_FILTER = 2,
149 CPL_CONN_POLICY_DENY = 3
150};
151
bbc02c7e
DM		 152enum {
153 ULP_MODE_NONE = 0,
154 ULP_MODE_ISCSI = 2,
155 ULP_MODE_RDMA = 4,
b48f3b9c 156 ULP_MODE_TCPDDP = 5,
bbc02c7e
DM		 157 ULP_MODE_FCOE = 6,
158};
159
160enum {
161 ULP_CRC_HEADER = 1 << 0,
162 ULP_CRC_DATA = 1 << 1
163};
164
165enum {
166 CPL_ABORT_SEND_RST = 0,
167 CPL_ABORT_NO_RST,
168};
169
170enum { /* TX_PKT_XT checksum types */
171 TX_CSUM_TCP = 0,
172 TX_CSUM_UDP = 1,
173 TX_CSUM_CRC16 = 4,
174 TX_CSUM_CRC32 = 5,
175 TX_CSUM_CRC32C = 6,
176 TX_CSUM_FCOE = 7,
177 TX_CSUM_TCPIP = 8,
178 TX_CSUM_UDPIP = 9,
179 TX_CSUM_TCPIP6 = 10,
180 TX_CSUM_UDPIP6 = 11,
181 TX_CSUM_IP = 12,
182};
183
184union opcode_tid {
185 __be32 opcode_tid;
186 u8 opcode;
187};
188
6c53e938
HS		 189#define CPL_OPCODE_S 24
190#define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
191#define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
192#define TID_G(x) ((x) & 0xFFFFFF)
193
194/* tid is assumed to be 24-bits */
195#define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
196
bbc02c7e 197#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
6c53e938
HS		 198
199/* extract the TID from a CPL command */
200#define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
bbc02c7e
DM		 201
202/* partitioning of TID fields that also carry a queue id */
6c53e938
HS		 203#define TID_TID_S 0
204#define TID_TID_M 0x3fff
a3cdaa69 205#define TID_TID_V(x) ((x) << TID_TID_S)
6c53e938
HS		 206#define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
207
208#define TID_QID_S 14
209#define TID_QID_M 0x3ff
210#define TID_QID_V(x) ((x) << TID_QID_S)
211#define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
bbc02c7e
DM		 212
213struct rss_header {
214 u8 opcode;
215#if defined(__LITTLE_ENDIAN_BITFIELD)
216 u8 channel:2;
217 u8 filter_hit:1;
218 u8 filter_tid:1;
219 u8 hash_type:2;
220 u8 ipv6:1;
221 u8 send2fw:1;
222#else
223 u8 send2fw:1;
224 u8 ipv6:1;
225 u8 hash_type:2;
226 u8 filter_tid:1;
227 u8 filter_hit:1;
228 u8 channel:2;
229#endif
230 __be16 qid;
231 __be32 hash_val;
232};
233
234struct work_request_hdr {
235 __be32 wr_hi;
236 __be32 wr_mid;
237 __be64 wr_lo;
238};
239
5be78ee9 240/* wr_hi fields */
6c53e938
HS		 241#define WR_OP_S 24
242#define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
5be78ee9 243
bbc02c7e
DM		 244#define WR_HDR struct work_request_hdr wr
245
1cab775c 246/* option 0 fields */
d7990b0c
AB		 247#define TX_CHAN_S 2
248#define TX_CHAN_V(x) ((x) << TX_CHAN_S)
249
250#define ULP_MODE_S 8
251#define ULP_MODE_V(x) ((x) << ULP_MODE_S)
252
253#define RCV_BUFSIZ_S 12
254#define RCV_BUFSIZ_M 0x3FFU
255#define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
256
257#define SMAC_SEL_S 28
258#define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
259
260#define L2T_IDX_S 36
261#define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
262
263#define WND_SCALE_S 50
264#define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
265
266#define KEEP_ALIVE_S 54
267#define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
268#define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
269
270#define MSS_IDX_S 60
271#define MSS_IDX_M 0xF
272#define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
273#define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
1cab775c
VP		 274
275/* option 2 fields */
d7990b0c
AB		 276#define RSS_QUEUE_S 0
277#define RSS_QUEUE_M 0x3FF
278#define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
279#define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
280
281#define RSS_QUEUE_VALID_S 10
282#define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
283#define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
284
285#define RX_FC_DISABLE_S 20
286#define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
287#define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
288
289#define RX_FC_VALID_S 22
290#define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
291#define RX_FC_VALID_F RX_FC_VALID_V(1U)
292
293#define RX_CHANNEL_S 26
294#define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
12b276fb 295#define RX_CHANNEL_F RX_CHANNEL_V(1U)
d7990b0c
AB		 296
297#define WND_SCALE_EN_S 28
298#define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
299#define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
300
301#define T5_OPT_2_VALID_S 31
302#define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
303#define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
1cab775c 304
bbc02c7e
DM		 305struct cpl_pass_open_req {
306 WR_HDR;
307 union opcode_tid ot;
308 __be16 local_port;
309 __be16 peer_port;
310 __be32 local_ip;
311 __be32 peer_ip;
312 __be64 opt0;
bbc02c7e 313 __be64 opt1;
bbc02c7e
DM		 314};
315
6c53e938
HS		 316/* option 0 fields */
317#define NO_CONG_S 4
318#define NO_CONG_V(x) ((x) << NO_CONG_S)
319#define NO_CONG_F NO_CONG_V(1U)
320
321#define DELACK_S 5
322#define DELACK_V(x) ((x) << DELACK_S)
323#define DELACK_F DELACK_V(1U)
324
12b276fb
KS		 325#define NON_OFFLOAD_S 7
326#define NON_OFFLOAD_V(x) ((x) << NON_OFFLOAD_S)
327#define NON_OFFLOAD_F NON_OFFLOAD_V(1U)
328
6c53e938
HS		 329#define DSCP_S 22
330#define DSCP_M 0x3F
331#define DSCP_V(x) ((x) << DSCP_S)
332#define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
333
334#define TCAM_BYPASS_S 48
335#define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
336#define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
337
338#define NAGLE_S 49
339#define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
340#define NAGLE_F NAGLE_V(1ULL)
341
342/* option 1 fields */
343#define SYN_RSS_ENABLE_S 0
344#define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
345#define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
346
347#define SYN_RSS_QUEUE_S 2
348#define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
349
350#define CONN_POLICY_S 22
351#define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
352
bbc02c7e
DM		 353struct cpl_pass_open_req6 {
354 WR_HDR;
355 union opcode_tid ot;
356 __be16 local_port;
357 __be16 peer_port;
358 __be64 local_ip_hi;
359 __be64 local_ip_lo;
360 __be64 peer_ip_hi;
361 __be64 peer_ip_lo;
362 __be64 opt0;
363 __be64 opt1;
364};
365
366struct cpl_pass_open_rpl {
367 union opcode_tid ot;
368 u8 rsvd[3];
369 u8 status;
370};
371
a84f0e13
VP		 372struct tcp_options {
373 __be16 mss;
374 __u8 wsf;
375#if defined(__LITTLE_ENDIAN_BITFIELD)
376 __u8:4;
377 __u8 unknown:1;
378 __u8:1;
379 __u8 sack:1;
380 __u8 tstamp:1;
381#else
382 __u8 tstamp:1;
383 __u8 sack:1;
384 __u8:1;
385 __u8 unknown:1;
386 __u8:4;
387#endif
388};
389
390struct cpl_pass_accept_req {
391 union opcode_tid ot;
392 __be16 rsvd;
393 __be16 len;
394 __be32 hdr_len;
395 __be16 vlan;
396 __be16 l2info;
397 __be32 tos_stid;
398 struct tcp_options tcpopt;
399};
400
401/* cpl_pass_accept_req.hdr_len fields */
402#define SYN_RX_CHAN_S 0
403#define SYN_RX_CHAN_M 0xF
404#define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
405#define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
406
407#define TCP_HDR_LEN_S 10
408#define TCP_HDR_LEN_M 0x3F
409#define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
410#define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
411
412#define IP_HDR_LEN_S 16
413#define IP_HDR_LEN_M 0x3FF
414#define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
415#define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
416
417#define ETH_HDR_LEN_S 26
418#define ETH_HDR_LEN_M 0x1F
419#define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
420#define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
421
422/* cpl_pass_accept_req.l2info fields */
423#define SYN_MAC_IDX_S 0
424#define SYN_MAC_IDX_M 0x1FF
425#define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
426#define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
427
428#define SYN_XACT_MATCH_S 9
429#define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
430#define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
431
432#define SYN_INTF_S 12
433#define SYN_INTF_M 0xF
434#define SYN_INTF_V(x) ((x) << SYN_INTF_S)
435#define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
436
437enum { /* TCP congestion control algorithms */
438 CONG_ALG_RENO,
439 CONG_ALG_TAHOE,
440 CONG_ALG_NEWRENO,
441 CONG_ALG_HIGHSPEED
442};
443
444#define CONG_CNTRL_S 14
445#define CONG_CNTRL_M 0x3
446#define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
447#define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
448
449#define T5_ISS_S 18
450#define T5_ISS_V(x) ((x) << T5_ISS_S)
451#define T5_ISS_F T5_ISS_V(1U)
452
bbc02c7e
DM		 453struct cpl_pass_accept_rpl {
454 WR_HDR;
455 union opcode_tid ot;
456 __be32 opt2;
bbc02c7e
DM		 457 __be64 opt0;
458};
459
6c53e938
HS		 460/* option 2 fields */
461#define RX_COALESCE_VALID_S 11
462#define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
463#define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
464
465#define RX_COALESCE_S 12
466#define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
467
468#define PACE_S 16
469#define PACE_V(x) ((x) << PACE_S)
470
471#define TX_QUEUE_S 23
472#define TX_QUEUE_M 0x7
473#define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
474#define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
475
476#define CCTRL_ECN_S 27
477#define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
478#define CCTRL_ECN_F CCTRL_ECN_V(1U)
479
480#define TSTAMPS_EN_S 29
481#define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
482#define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
483
484#define SACK_EN_S 30
485#define SACK_EN_V(x) ((x) << SACK_EN_S)
486#define SACK_EN_F SACK_EN_V(1U)
487
92e7ae71
HS		 488struct cpl_t5_pass_accept_rpl {
489 WR_HDR;
490 union opcode_tid ot;
491 __be32 opt2;
492 __be64 opt0;
493 __be32 iss;
494 __be32 rsvd;
495};
496
bbc02c7e
DM		 497struct cpl_act_open_req {
498 WR_HDR;
499 union opcode_tid ot;
500 __be16 local_port;
501 __be16 peer_port;
502 __be32 local_ip;
503 __be32 peer_ip;
504 __be64 opt0;
505 __be32 params;
506 __be32 opt2;
507};
508
d7990b0c
AB		 509#define FILTER_TUPLE_S 24
510#define FILTER_TUPLE_M 0xFFFFFFFFFF
511#define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
512#define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
2422d9a3
SR		 513struct cpl_t5_act_open_req {
514 WR_HDR;
515 union opcode_tid ot;
516 __be16 local_port;
517 __be16 peer_port;
518 __be32 local_ip;
519 __be32 peer_ip;
520 __be64 opt0;
521 __be32 rsvd;
522 __be32 opt2;
523 __be64 params;
524};
525
27999805
H		 526struct cpl_t6_act_open_req {
527 WR_HDR;
528 union opcode_tid ot;
529 __be16 local_port;
530 __be16 peer_port;
531 __be32 local_ip;
532 __be32 peer_ip;
533 __be64 opt0;
534 __be32 rsvd;
535 __be32 opt2;
536 __be64 params;
537 __be32 rsvd2;
538 __be32 opt3;
539};
540
bbc02c7e
DM		 541struct cpl_act_open_req6 {
542 WR_HDR;
543 union opcode_tid ot;
544 __be16 local_port;
545 __be16 peer_port;
546 __be64 local_ip_hi;
547 __be64 local_ip_lo;
548 __be64 peer_ip_hi;
549 __be64 peer_ip_lo;
550 __be64 opt0;
551 __be32 params;
552 __be32 opt2;
553};
554
80f40c1f
VP		 555struct cpl_t5_act_open_req6 {
556 WR_HDR;
557 union opcode_tid ot;
558 __be16 local_port;
559 __be16 peer_port;
560 __be64 local_ip_hi;
561 __be64 local_ip_lo;
562 __be64 peer_ip_hi;
563 __be64 peer_ip_lo;
564 __be64 opt0;
565 __be32 rsvd;
566 __be32 opt2;
567 __be64 params;
568};
569
27999805
H		 570struct cpl_t6_act_open_req6 {
571 WR_HDR;
572 union opcode_tid ot;
573 __be16 local_port;
574 __be16 peer_port;
575 __be64 local_ip_hi;
576 __be64 local_ip_lo;
577 __be64 peer_ip_hi;
578 __be64 peer_ip_lo;
579 __be64 opt0;
580 __be32 rsvd;
581 __be32 opt2;
582 __be64 params;
583 __be32 rsvd2;
584 __be32 opt3;
585};
586
bbc02c7e
DM		 587struct cpl_act_open_rpl {
588 union opcode_tid ot;
589 __be32 atid_status;
bbc02c7e
DM		 590};
591
6c53e938
HS		 592/* cpl_act_open_rpl.atid_status fields */
593#define AOPEN_STATUS_S 0
594#define AOPEN_STATUS_M 0xFF
595#define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
596
597#define AOPEN_ATID_S 8
598#define AOPEN_ATID_M 0xFFFFFF
599#define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
600
bbc02c7e
DM		 601struct cpl_pass_establish {
602 union opcode_tid ot;
603 __be32 rsvd;
604 __be32 tos_stid;
bbc02c7e
DM		 605 __be16 mac_idx;
606 __be16 tcp_opt;
bbc02c7e
DM		 607 __be32 snd_isn;
608 __be32 rcv_isn;
609};
610
6c53e938
HS		 611/* cpl_pass_establish.tos_stid fields */
612#define PASS_OPEN_TID_S 0
613#define PASS_OPEN_TID_M 0xFFFFFF
614#define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
615#define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
616
617#define PASS_OPEN_TOS_S 24
618#define PASS_OPEN_TOS_M 0xFF
619#define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
620#define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
621
622/* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
623#define TCPOPT_WSCALE_OK_S 5
624#define TCPOPT_WSCALE_OK_M 0x1
625#define TCPOPT_WSCALE_OK_G(x) \
626 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
627
628#define TCPOPT_SACK_S 6
629#define TCPOPT_SACK_M 0x1
630#define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
631
632#define TCPOPT_TSTAMP_S 7
633#define TCPOPT_TSTAMP_M 0x1
634#define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
635
636#define TCPOPT_SND_WSCALE_S 8
637#define TCPOPT_SND_WSCALE_M 0xF
638#define TCPOPT_SND_WSCALE_G(x) \
639 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
640
641#define TCPOPT_MSS_S 12
642#define TCPOPT_MSS_M 0xF
643#define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
644
27999805
H		 645#define T6_TCP_HDR_LEN_S 8
646#define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
647#define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
648
649#define T6_IP_HDR_LEN_S 14
650#define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
651#define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
652
653#define T6_ETH_HDR_LEN_S 24
654#define T6_ETH_HDR_LEN_M 0xFF
655#define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
656#define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
657
bbc02c7e
DM		 658struct cpl_act_establish {
659 union opcode_tid ot;
660 __be32 rsvd;
661 __be32 tos_atid;
662 __be16 mac_idx;
663 __be16 tcp_opt;
664 __be32 snd_isn;
665 __be32 rcv_isn;
666};
667
668struct cpl_get_tcb {
669 WR_HDR;
670 union opcode_tid ot;
671 __be16 reply_ctrl;
bbc02c7e
DM		 672 __be16 cookie;
673};
674
bdc590b9
HS		 675/* cpl_get_tcb.reply_ctrl fields */
676#define QUEUENO_S 0
677#define QUEUENO_V(x) ((x) << QUEUENO_S)
678
679#define REPLY_CHAN_S 14
680#define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
681#define REPLY_CHAN_F REPLY_CHAN_V(1U)
682
683#define NO_REPLY_S 15
684#define NO_REPLY_V(x) ((x) << NO_REPLY_S)
685#define NO_REPLY_F NO_REPLY_V(1U)
686
bbc02c7e
DM		 687struct cpl_set_tcb_field {
688 WR_HDR;
689 union opcode_tid ot;
690 __be16 reply_ctrl;
691 __be16 word_cookie;
bbc02c7e
DM		 692 __be64 mask;
693 __be64 val;
694};
695
bdc590b9 696/* cpl_set_tcb_field.word_cookie fields */
3bdb376e
KS		 697#define TCB_WORD_S 0
698#define TCB_WORD_V(x) ((x) << TCB_WORD_S)
bdc590b9
HS		 699
700#define TCB_COOKIE_S 5
701#define TCB_COOKIE_M 0x7
702#define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
703#define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
704
bbc02c7e
DM		 705struct cpl_set_tcb_rpl {
706 union opcode_tid ot;
707 __be16 rsvd;
708 u8 cookie;
709 u8 status;
710 __be64 oldval;
711};
712
713struct cpl_close_con_req {
714 WR_HDR;
715 union opcode_tid ot;
716 __be32 rsvd;
717};
718
719struct cpl_close_con_rpl {
720 union opcode_tid ot;
721 u8 rsvd[3];
722 u8 status;
723 __be32 snd_nxt;
724 __be32 rcv_nxt;
725};
726
727struct cpl_close_listsvr_req {
728 WR_HDR;
729 union opcode_tid ot;
730 __be16 reply_ctrl;
bbc02c7e
DM		 731 __be16 rsvd;
732};
733
bdc590b9
HS		 734/* additional cpl_close_listsvr_req.reply_ctrl field */
735#define LISTSVR_IPV6_S 14
736#define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
737#define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
738
bbc02c7e
DM		 739struct cpl_close_listsvr_rpl {
740 union opcode_tid ot;
741 u8 rsvd[3];
742 u8 status;
743};
744
745struct cpl_abort_req_rss {
746 union opcode_tid ot;
747 u8 rsvd[3];
748 u8 status;
749};
750
a3cdaa69
RR		 751struct cpl_abort_req_rss6 {
752 WR_HDR;
753 union opcode_tid ot;
754 __u32 srqidx_status;
755};
756
757#define ABORT_RSS_STATUS_S 0
758#define ABORT_RSS_STATUS_M 0xff
759#define ABORT_RSS_STATUS_V(x) ((x) << ABORT_RSS_STATUS_S)
760#define ABORT_RSS_STATUS_G(x) (((x) >> ABORT_RSS_STATUS_S) & ABORT_RSS_STATUS_M)
761
762#define ABORT_RSS_SRQIDX_S 8
763#define ABORT_RSS_SRQIDX_M 0xffffff
764#define ABORT_RSS_SRQIDX_V(x) ((x) << ABORT_RSS_SRQIDX_S)
765#define ABORT_RSS_SRQIDX_G(x) (((x) >> ABORT_RSS_SRQIDX_S) & ABORT_RSS_SRQIDX_M)
766
bbc02c7e
DM		 767struct cpl_abort_req {
768 WR_HDR;
769 union opcode_tid ot;
770 __be32 rsvd0;
771 u8 rsvd1;
772 u8 cmd;
773 u8 rsvd2[6];
774};
775
776struct cpl_abort_rpl_rss {
777 union opcode_tid ot;
778 u8 rsvd[3];
779 u8 status;
780};
781
a3cdaa69
RR		 782struct cpl_abort_rpl_rss6 {
783 union opcode_tid ot;
784 __u32 srqidx_status;
785};
786
bbc02c7e
DM		 787struct cpl_abort_rpl {
788 WR_HDR;
789 union opcode_tid ot;
790 __be32 rsvd0;
791 u8 rsvd1;
792 u8 cmd;
793 u8 rsvd2[6];
794};
795
796struct cpl_peer_close {
797 union opcode_tid ot;
798 __be32 rcv_nxt;
799};
800
801struct cpl_tid_release {
802 WR_HDR;
803 union opcode_tid ot;
804 __be32 rsvd;
805};
806
807struct cpl_tx_pkt_core {
808 __be32 ctrl0;
bbc02c7e
DM		 809 __be16 pack;
810 __be16 len;
811 __be64 ctrl1;
bbc02c7e
DM		 812};
813
814struct cpl_tx_pkt {
815 WR_HDR;
816 struct cpl_tx_pkt_core c;
817};
818
819#define cpl_tx_pkt_xt cpl_tx_pkt
820
1ecc7b7a
HS		 821/* cpl_tx_pkt_core.ctrl0 fields */
822#define TXPKT_VF_S 0
823#define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
824
825#define TXPKT_PF_S 8
826#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
827
828#define TXPKT_VF_VLD_S 11
829#define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
830#define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
831
832#define TXPKT_OVLAN_IDX_S 12
833#define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
834
397665da
AB		 835#define TXPKT_T5_OVLAN_IDX_S 12
836#define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
837
1ecc7b7a
HS		 838#define TXPKT_INTF_S 16
839#define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
840
841#define TXPKT_INS_OVLAN_S 21
842#define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
843#define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
844
a4569504
AG		 845#define TXPKT_TSTAMP_S 23
846#define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S)
847#define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL)
848
1ecc7b7a
HS		 849#define TXPKT_OPCODE_S 24
850#define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
851
852/* cpl_tx_pkt_core.ctrl1 fields */
853#define TXPKT_CSUM_END_S 12
854#define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
855
856#define TXPKT_CSUM_START_S 20
857#define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
858
859#define TXPKT_IPHDR_LEN_S 20
860#define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
861
862#define TXPKT_CSUM_LOC_S 30
863#define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
864
865#define TXPKT_ETHHDR_LEN_S 34
866#define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
867
3ccc6cf7
HS		 868#define T6_TXPKT_ETHHDR_LEN_S 32
869#define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
870
1ecc7b7a
HS		 871#define TXPKT_CSUM_TYPE_S 40
872#define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
873
874#define TXPKT_VLAN_S 44
875#define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
876
877#define TXPKT_VLAN_VLD_S 60
878#define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
879#define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
880
881#define TXPKT_IPCSUM_DIS_S 62
882#define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
883#define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
884
885#define TXPKT_L4CSUM_DIS_S 63
886#define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
887#define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
888
1704d748 889struct cpl_tx_pkt_lso_core {
bbc02c7e 890 __be32 lso_ctrl;
bbc02c7e
DM		 891 __be16 ipid_ofst;
892 __be16 mss;
893 __be32 seqno_offset;
894 __be32 len;
895 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
896};
897
bdc590b9
HS		 898/* cpl_tx_pkt_lso_core.lso_ctrl fields */
899#define LSO_TCPHDR_LEN_S 0
900#define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
901
902#define LSO_IPHDR_LEN_S 4
903#define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
904
905#define LSO_ETHHDR_LEN_S 16
906#define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
907
908#define LSO_IPV6_S 20
909#define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
910#define LSO_IPV6_F LSO_IPV6_V(1U)
911
912#define LSO_LAST_SLICE_S 22
913#define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
914#define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
915
916#define LSO_FIRST_SLICE_S 23
917#define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
918#define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
919
920#define LSO_OPCODE_S 24
921#define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
922
923#define LSO_T5_XFER_SIZE_S 0
924#define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
925
1704d748
CL		 926struct cpl_tx_pkt_lso {
927 WR_HDR;
928 struct cpl_tx_pkt_lso_core c;
929 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
930};
931
bbc02c7e
DM		 932struct cpl_iscsi_hdr {
933 union opcode_tid ot;
934 __be16 pdu_len_ddp;
bbc02c7e
DM		 935 __be16 len;
936 __be32 seq;
937 __be16 urg;
938 u8 rsvd;
939 u8 status;
940};
941
bdc590b9
HS		 942/* cpl_iscsi_hdr.pdu_len_ddp fields */
943#define ISCSI_PDU_LEN_S 0
944#define ISCSI_PDU_LEN_M 0x7FFF
945#define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
946#define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
947
948#define ISCSI_DDP_S 15
949#define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
950#define ISCSI_DDP_F ISCSI_DDP_V(1U)
951
76c144bd
VP		 952struct cpl_rx_data_ddp {
953 union opcode_tid ot;
954 __be16 urg;
955 __be16 len;
956 __be32 seq;
957 union {
958 __be32 nxt_seq;
959 __be32 ddp_report;
960 };
961 __be32 ulp_crc;
962 __be32 ddpvld;
963};
964
965#define cpl_rx_iscsi_ddp cpl_rx_data_ddp
966
b96c5cbb
VP		 967struct cpl_iscsi_data {
968 union opcode_tid ot;
969 __u8 rsvd0[2];
970 __be16 len;
971 __be32 seq;
972 __be16 urg;
973 __u8 rsvd1;
974 __u8 status;
975};
976
44830d8f
VP		 977struct cpl_rx_iscsi_cmp {
978 union opcode_tid ot;
979 __be16 pdu_len_ddp;
980 __be16 len;
981 __be32 seq;
982 __be16 urg;
983 __u8 rsvd;
984 __u8 status;
985 __be32 ulp_crc;
986 __be32 ddpvld;
987};
988
b96c5cbb
VP		 989struct cpl_tx_data_iso {
990 __be32 op_to_scsi;
991 __u8 reserved1;
992 __u8 ahs_len;
993 __be16 mpdu;
994 __be32 burst_size;
995 __be32 len;
996 __be32 reserved2_seglen_offset;
997 __be32 datasn_offset;
998 __be32 buffer_offset;
999 __be32 reserved3;
1000
1001 /* encapsulated CPL_TX_DATA follows here */
1002};
1003
1004/* cpl_tx_data_iso.op_to_scsi fields */
1005#define CPL_TX_DATA_ISO_OP_S 24
1006#define CPL_TX_DATA_ISO_OP_M 0xff
1007#define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S)
1008#define CPL_TX_DATA_ISO_OP_G(x) \
1009 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M)
1010
1011#define CPL_TX_DATA_ISO_FIRST_S 23
1012#define CPL_TX_DATA_ISO_FIRST_M 0x1
1013#define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S)
1014#define CPL_TX_DATA_ISO_FIRST_G(x) \
1015 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M)
1016#define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U)
1017
1018#define CPL_TX_DATA_ISO_LAST_S 22
1019#define CPL_TX_DATA_ISO_LAST_M 0x1
1020#define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S)
1021#define CPL_TX_DATA_ISO_LAST_G(x) \
1022 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M)
1023#define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U)
1024
1025#define CPL_TX_DATA_ISO_CPLHDRLEN_S 21
1026#define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1
1027#define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S)
1028#define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \
1029 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M)
1030#define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U)
1031
1032#define CPL_TX_DATA_ISO_HDRCRC_S 20
1033#define CPL_TX_DATA_ISO_HDRCRC_M 0x1
1034#define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S)
1035#define CPL_TX_DATA_ISO_HDRCRC_G(x) \
1036 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M)
1037#define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U)
1038
1039#define CPL_TX_DATA_ISO_PLDCRC_S 19
1040#define CPL_TX_DATA_ISO_PLDCRC_M 0x1
1041#define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S)
1042#define CPL_TX_DATA_ISO_PLDCRC_G(x) \
1043 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M)
1044#define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U)
1045
1046#define CPL_TX_DATA_ISO_IMMEDIATE_S 18
1047#define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1
1048#define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S)
1049#define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \
1050 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M)
1051#define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U)
1052
1053#define CPL_TX_DATA_ISO_SCSI_S 16
1054#define CPL_TX_DATA_ISO_SCSI_M 0x3
1055#define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S)
1056#define CPL_TX_DATA_ISO_SCSI_G(x) \
1057 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M)
1058
1059/* cpl_tx_data_iso.reserved2_seglen_offset fields */
1060#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0
1061#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff
1062#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \
1063 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S)
1064#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \
1065 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \
1066 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M)
1067
bbc02c7e
DM		 1068struct cpl_rx_data {
1069 union opcode_tid ot;
1070 __be16 rsvd;
1071 __be16 len;
1072 __be32 seq;
1073 __be16 urg;
1074#if defined(__LITTLE_ENDIAN_BITFIELD)
1075 u8 dack_mode:2;
1076 u8 psh:1;
1077 u8 heartbeat:1;
1078 u8 ddp_off:1;
1079 u8 :3;
1080#else
1081 u8 :3;
1082 u8 ddp_off:1;
1083 u8 heartbeat:1;
1084 u8 psh:1;
1085 u8 dack_mode:2;
1086#endif
1087 u8 status;
1088};
1089
1090struct cpl_rx_data_ack {
1091 WR_HDR;
1092 union opcode_tid ot;
1093 __be32 credit_dack;
bbc02c7e
DM		 1094};
1095
d7990b0c
AB		 1096/* cpl_rx_data_ack.ack_seq fields */
1097#define RX_CREDITS_S 0
1098#define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
1099
1100#define RX_FORCE_ACK_S 28
1101#define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
1102#define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
1103
cb6a8ff0
VP		 1104#define RX_DACK_MODE_S 29
1105#define RX_DACK_MODE_M 0x3
1106#define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)
1107#define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)
1108
1109#define RX_DACK_CHANGE_S 31
1110#define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)
1111#define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U)
1112
bbc02c7e 1113struct cpl_rx_pkt {
87b6cf51 1114 struct rss_header rsshdr;
bbc02c7e
DM		 1115 u8 opcode;
1116#if defined(__LITTLE_ENDIAN_BITFIELD)
1117 u8 iff:4;
1118 u8 csum_calc:1;
1119 u8 ipmi_pkt:1;
1120 u8 vlan_ex:1;
1121 u8 ip_frag:1;
1122#else
1123 u8 ip_frag:1;
1124 u8 vlan_ex:1;
1125 u8 ipmi_pkt:1;
1126 u8 csum_calc:1;
1127 u8 iff:4;
1128#endif
1129 __be16 csum;
1130 __be16 vlan;
1131 __be16 len;
1132 __be32 l2info;
bbc02c7e
DM		 1133 __be16 hdr_len;
1134 __be16 err_vec;
1135};
1136
27999805
H		 1137#define RX_T6_ETHHDR_LEN_M 0xFF
1138#define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
1139
76fed8a9
VP		 1140#define RXF_PSH_S 20
1141#define RXF_PSH_V(x) ((x) << RXF_PSH_S)
1142#define RXF_PSH_F RXF_PSH_V(1U)
1143
1144#define RXF_SYN_S 21
1145#define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1146#define RXF_SYN_F RXF_SYN_V(1U)
1147
bdc590b9
HS		 1148#define RXF_UDP_S 22
1149#define RXF_UDP_V(x) ((x) << RXF_UDP_S)
1150#define RXF_UDP_F RXF_UDP_V(1U)
1151
1152#define RXF_TCP_S 23
1153#define RXF_TCP_V(x) ((x) << RXF_TCP_S)
1154#define RXF_TCP_F RXF_TCP_V(1U)
1155
1156#define RXF_IP_S 24
1157#define RXF_IP_V(x) ((x) << RXF_IP_S)
1158#define RXF_IP_F RXF_IP_V(1U)
1159
1160#define RXF_IP6_S 25
1161#define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1162#define RXF_IP6_F RXF_IP6_V(1U)
1163
76fed8a9
VP		 1164#define RXF_SYN_COOKIE_S 26
1165#define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1166#define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1167
1168#define RXF_FCOE_S 26
1169#define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1170#define RXF_FCOE_F RXF_FCOE_V(1U)
1171
1172#define RXF_LRO_S 27
1173#define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1174#define RXF_LRO_F RXF_LRO_V(1U)
1175
1cab775c 1176/* rx_pkt.l2info fields */
bdc590b9
HS		 1177#define RX_ETHHDR_LEN_S 0
1178#define RX_ETHHDR_LEN_M 0x1F
1179#define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1180#define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1181
1182#define RX_T5_ETHHDR_LEN_S 0
1183#define RX_T5_ETHHDR_LEN_M 0x3F
1184#define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1185#define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1186
1187#define RX_MACIDX_S 8
1188#define RX_MACIDX_M 0x1FF
1189#define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1190#define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1191
1192#define RXF_SYN_S 21
1193#define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1194#define RXF_SYN_F RXF_SYN_V(1U)
1195
1196#define RX_CHAN_S 28
1197#define RX_CHAN_M 0xF
1198#define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1199#define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1cab775c
VP		 1200
1201/* rx_pkt.hdr_len fields */
bdc590b9
HS		 1202#define RX_TCPHDR_LEN_S 0
1203#define RX_TCPHDR_LEN_M 0x3F
1204#define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1205#define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1cab775c 1206
bdc590b9
HS		 1207#define RX_IPHDR_LEN_S 6
1208#define RX_IPHDR_LEN_M 0x3FF
1209#define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1210#define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1cab775c 1211
76fed8a9
VP		 1212/* rx_pkt.err_vec fields */
1213#define RXERR_CSUM_S 13
1214#define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1215#define RXERR_CSUM_F RXERR_CSUM_V(1U)
1216
8eb9f2f9
A		 1217#define T6_COMPR_RXERR_LEN_S 1
1218#define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1219#define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U)
1220
1221#define T6_COMPR_RXERR_VEC_S 0
1222#define T6_COMPR_RXERR_VEC_M 0x3F
1223#define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1224#define T6_COMPR_RXERR_VEC_G(x) \
1225 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M)
1226
1227/* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */
1228#define T6_COMPR_RXERR_SUM_S 4
1229#define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S)
1230#define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U)
1231
bbc02c7e
DM		 1232struct cpl_trace_pkt {
1233 u8 opcode;
1234 u8 intf;
1235#if defined(__LITTLE_ENDIAN_BITFIELD)
1236 u8 runt:4;
1237 u8 filter_hit:4;
1238 u8 :6;
1239 u8 err:1;
1240 u8 trunc:1;
1241#else
1242 u8 filter_hit:4;
1243 u8 runt:4;
1244 u8 trunc:1;
1245 u8 err:1;
1246 u8 :6;
1247#endif
1248 __be16 rsvd;
1249 __be16 len;
1250 __be64 tstamp;
1251};
1252
2422d9a3
SR		 1253struct cpl_t5_trace_pkt {
1254 __u8 opcode;
1255 __u8 intf;
1256#if defined(__LITTLE_ENDIAN_BITFIELD)
1257 __u8 runt:4;
1258 __u8 filter_hit:4;
1259 __u8:6;
1260 __u8 err:1;
1261 __u8 trunc:1;
1262#else
1263 __u8 filter_hit:4;
1264 __u8 runt:4;
1265 __u8 trunc:1;
1266 __u8 err:1;
1267 __u8:6;
1268#endif
1269 __be16 rsvd;
1270 __be16 len;
1271 __be64 tstamp;
1272 __be64 rsvd1;
1273};
1274
bbc02c7e
DM		 1275struct cpl_l2t_write_req {
1276 WR_HDR;
1277 union opcode_tid ot;
1278 __be16 params;
bbc02c7e
DM		 1279 __be16 l2t_idx;
1280 __be16 vlan;
1281 u8 dst_mac[6];
1282};
1283
bdc590b9
HS		 1284/* cpl_l2t_write_req.params fields */
1285#define L2T_W_INFO_S 2
1286#define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1287
1288#define L2T_W_PORT_S 8
1289#define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1290
1291#define L2T_W_NOREPLY_S 15
1292#define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1293#define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1294
ac8e4c69
H		 1295#define CPL_L2T_VLAN_NONE 0xfff
1296
bbc02c7e
DM		 1297struct cpl_l2t_write_rpl {
1298 union opcode_tid ot;
1299 u8 status;
1300 u8 rsvd[3];
1301};
1302
3bdb376e
KS		 1303struct cpl_smt_write_req {
1304 WR_HDR;
1305 union opcode_tid ot;
1306 __be32 params;
1307 __be16 pfvf1;
1308 u8 src_mac1[6];
1309 __be16 pfvf0;
1310 u8 src_mac0[6];
1311};
1312
1313struct cpl_t6_smt_write_req {
1314 WR_HDR;
1315 union opcode_tid ot;
1316 __be32 params;
1317 __be64 tag;
1318 __be16 pfvf0;
1319 u8 src_mac0[6];
1320 __be32 local_ip;
1321 __be32 rsvd;
1322};
1323
1324struct cpl_smt_write_rpl {
1325 union opcode_tid ot;
1326 u8 status;
1327 u8 rsvd[3];
1328};
1329
1330/* cpl_smt_{read,write}_req.params fields */
1331#define SMTW_OVLAN_IDX_S 16
1332#define SMTW_OVLAN_IDX_V(x) ((x) << SMTW_OVLAN_IDX_S)
1333
1334#define SMTW_IDX_S 20
1335#define SMTW_IDX_V(x) ((x) << SMTW_IDX_S)
1336
1337#define SMTW_NORPL_S 31
1338#define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S)
1339#define SMTW_NORPL_F SMTW_NORPL_V(1U)
1340
bbc02c7e
DM		 1341struct cpl_rdma_terminate {
1342 union opcode_tid ot;
1343 __be16 rsvd;
1344 __be16 len;
1345};
1346
1347struct cpl_sge_egr_update {
1348 __be32 opcode_qid;
bbc02c7e
DM		 1349 __be16 cidx;
1350 __be16 pidx;
1351};
1352
bdc590b9
HS		 1353/* cpl_sge_egr_update.ot fields */
1354#define EGR_QID_S 0
1355#define EGR_QID_M 0x1FFFF
1356#define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1357
b407a4a9
VP		 1358/* cpl_fw*.type values */
1359enum {
1360 FW_TYPE_CMD_RPL = 0,
1361 FW_TYPE_WR_RPL = 1,
1362 FW_TYPE_CQE = 2,
1363 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1364 FW_TYPE_RSSCPL = 4,
1365};
1366
bbc02c7e
DM		 1367struct cpl_fw4_pld {
1368 u8 opcode;
1369 u8 rsvd0[3];
1370 u8 type;
1371 u8 rsvd1;
1372 __be16 len;
1373 __be64 data;
1374 __be64 rsvd2;
1375};
1376
1377struct cpl_fw6_pld {
1378 u8 opcode;
1379 u8 rsvd[5];
1380 __be16 len;
1381 __be64 data[4];
1382};
1383
1384struct cpl_fw4_msg {
1385 u8 opcode;
1386 u8 type;
1387 __be16 rsvd0;
1388 __be32 rsvd1;
1389 __be64 data[2];
1390};
1391
1392struct cpl_fw4_ack {
1393 union opcode_tid ot;
1394 u8 credits;
1395 u8 rsvd0[2];
1396 u8 seq_vld;
1397 __be32 snd_nxt;
1398 __be32 snd_una;
1399 __be64 rsvd1;
1400};
1401
b96c5cbb
VP		 1402enum {
1403 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
1404 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
1405 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
1406};
1407
bbc02c7e
DM		 1408struct cpl_fw6_msg {
1409 u8 opcode;
1410 u8 type;
1411 __be16 rsvd0;
1412 __be32 rsvd1;
1413 __be64 data[4];
1414};
1415
1704d748
CL		 1416/* cpl_fw6_msg.type values */
1417enum {
1418 FW6_TYPE_CMD_RPL = 0,
5be78ee9
VP		 1419 FW6_TYPE_WR_RPL = 1,
1420 FW6_TYPE_CQE = 2,
1421 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
b407a4a9 1422 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
5be78ee9
VP		 1423};
1424
1425struct cpl_fw6_msg_ofld_connection_wr_rpl {
1426 __u64 cookie;
1427 __be32 tid; /* or atid in case of active failure */
1428 __u8 t_state;
1429 __u8 retval;
1430 __u8 rsvd[2];
1704d748
CL		 1431};
1432
b96c5cbb
VP		 1433struct cpl_tx_data {
1434 union opcode_tid ot;
1435 __be32 len;
1436 __be32 rsvd;
1437 __be32 flags;
1438};
1439
1440/* cpl_tx_data.flags field */
1441#define TX_FORCE_S 13
1442#define TX_FORCE_V(x) ((x) << TX_FORCE_S)
1443
bdec5188
VP		 1444#define T6_TX_FORCE_S 20
1445#define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S)
1446#define T6_TX_FORCE_F T6_TX_FORCE_V(1U)
1447
bbc02c7e
DM		 1448enum {
1449 ULP_TX_MEM_READ = 2,
1450 ULP_TX_MEM_WRITE = 3,
1451 ULP_TX_PKT = 4
1452};
1453
1454enum {
1455 ULP_TX_SC_NOOP = 0x80,
1456 ULP_TX_SC_IMM = 0x81,
1457 ULP_TX_SC_DSGL = 0x82,
1458 ULP_TX_SC_ISGL = 0x83
1459};
1460
d7990b0c
AB		 1461#define ULPTX_CMD_S 24
1462#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1463
bbc02c7e
DM		 1464struct ulptx_sge_pair {
1465 __be32 len[2];
1466 __be64 addr[2];
1467};
1468
1469struct ulptx_sgl {
1470 __be32 cmd_nsge;
bbc02c7e
DM		 1471 __be32 len0;
1472 __be64 addr0;
1473 struct ulptx_sge_pair sge[0];
1474};
1475
40c46635
VP		 1476struct ulptx_idata {
1477 __be32 cmd_more;
1478 __be32 len;
1479};
1480
d6657781
HS		 1481struct ulp_txpkt {
1482 __be32 cmd_dest;
1483 __be32 len;
1484};
1485
1486#define ULPTX_CMD_S 24
1487#define ULPTX_CMD_M 0xFF
1488#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1489
bdc590b9
HS		 1490#define ULPTX_NSGE_S 0
1491#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1492
1493#define ULPTX_MORE_S 23
1494#define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1495#define ULPTX_MORE_F ULPTX_MORE_V(1U)
1496
d6657781
HS		 1497#define ULP_TXPKT_DEST_S 16
1498#define ULP_TXPKT_DEST_M 0x3
1499#define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
1500
1501#define ULP_TXPKT_FID_S 4
1502#define ULP_TXPKT_FID_M 0x7ff
1503#define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S)
1504
1505#define ULP_TXPKT_RO_S 3
1506#define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
1507#define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
1508
ef0fd85a
GG		 1509enum cpl_tx_tnl_lso_type {
1510 TX_TNL_TYPE_OPAQUE,
1511 TX_TNL_TYPE_NVGRE,
1512 TX_TNL_TYPE_VXLAN,
1513 TX_TNL_TYPE_GENEVE,
1514};
1515
1516struct cpl_tx_tnl_lso {
1517 __be32 op_to_IpIdSplitOut;
1518 __be16 IpIdOffsetOut;
1519 __be16 UdpLenSetOut_to_TnlHdrLen;
1520 __be64 r1;
1521 __be32 Flow_to_TcpHdrLen;
1522 __be16 IpIdOffset;
1523 __be16 IpIdSplit_to_Mss;
1524 __be32 TCPSeqOffset;
1525 __be32 EthLenOffset_Size;
1526 /* encapsulated CPL (TX_PKT_XT) follows here */
1527};
1528
1529#define CPL_TX_TNL_LSO_OPCODE_S 24
1530#define CPL_TX_TNL_LSO_OPCODE_M 0xff
1531#define CPL_TX_TNL_LSO_OPCODE_V(x) ((x) << CPL_TX_TNL_LSO_OPCODE_S)
1532#define CPL_TX_TNL_LSO_OPCODE_G(x) \
1533 (((x) >> CPL_TX_TNL_LSO_OPCODE_S) & CPL_TX_TNL_LSO_OPCODE_M)
1534
1535#define CPL_TX_TNL_LSO_FIRST_S 23
1536#define CPL_TX_TNL_LSO_FIRST_M 0x1
1537#define CPL_TX_TNL_LSO_FIRST_V(x) ((x) << CPL_TX_TNL_LSO_FIRST_S)
1538#define CPL_TX_TNL_LSO_FIRST_G(x) \
1539 (((x) >> CPL_TX_TNL_LSO_FIRST_S) & CPL_TX_TNL_LSO_FIRST_M)
1540#define CPL_TX_TNL_LSO_FIRST_F CPL_TX_TNL_LSO_FIRST_V(1U)
1541
1542#define CPL_TX_TNL_LSO_LAST_S 22
1543#define CPL_TX_TNL_LSO_LAST_M 0x1
1544#define CPL_TX_TNL_LSO_LAST_V(x) ((x) << CPL_TX_TNL_LSO_LAST_S)
1545#define CPL_TX_TNL_LSO_LAST_G(x) \
1546 (((x) >> CPL_TX_TNL_LSO_LAST_S) & CPL_TX_TNL_LSO_LAST_M)
1547#define CPL_TX_TNL_LSO_LAST_F CPL_TX_TNL_LSO_LAST_V(1U)
1548
1549#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_S 21
1550#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_M 0x1
1551#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(x) \
1552 ((x) << CPL_TX_TNL_LSO_ETHHDRLENXOUT_S)
1553#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_G(x) \
1554 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENXOUT_S) & \
1555 CPL_TX_TNL_LSO_ETHHDRLENXOUT_M)
1556#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_F CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(1U)
1557
1558#define CPL_TX_TNL_LSO_IPV6OUT_S 20
1559#define CPL_TX_TNL_LSO_IPV6OUT_M 0x1
1560#define CPL_TX_TNL_LSO_IPV6OUT_V(x) ((x) << CPL_TX_TNL_LSO_IPV6OUT_S)
1561#define CPL_TX_TNL_LSO_IPV6OUT_G(x) \
1562 (((x) >> CPL_TX_TNL_LSO_IPV6OUT_S) & CPL_TX_TNL_LSO_IPV6OUT_M)
1563#define CPL_TX_TNL_LSO_IPV6OUT_F CPL_TX_TNL_LSO_IPV6OUT_V(1U)
1564
1565#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16
1566#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf
1567#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S)
1568#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \
1569 (((x) >> CPL_TX_TNL_LSO_ETHHDRLEN_S) & CPL_TX_TNL_LSO_ETHHDRLEN_M)
1570
1571#define CPL_TX_TNL_LSO_IPHDRLEN_S 4
1572#define CPL_TX_TNL_LSO_IPHDRLEN_M 0xfff
1573#define CPL_TX_TNL_LSO_IPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLEN_S)
1574#define CPL_TX_TNL_LSO_IPHDRLEN_G(x) \
1575 (((x) >> CPL_TX_TNL_LSO_IPHDRLEN_S) & CPL_TX_TNL_LSO_IPHDRLEN_M)
1576
1577#define CPL_TX_TNL_LSO_TCPHDRLEN_S 0
1578#define CPL_TX_TNL_LSO_TCPHDRLEN_M 0xf
1579#define CPL_TX_TNL_LSO_TCPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TCPHDRLEN_S)
1580#define CPL_TX_TNL_LSO_TCPHDRLEN_G(x) \
1581 (((x) >> CPL_TX_TNL_LSO_TCPHDRLEN_S) & CPL_TX_TNL_LSO_TCPHDRLEN_M)
1582
1583#define CPL_TX_TNL_LSO_MSS_S 0
1584#define CPL_TX_TNL_LSO_MSS_M 0x3fff
1585#define CPL_TX_TNL_LSO_MSS_V(x) ((x) << CPL_TX_TNL_LSO_MSS_S)
1586#define CPL_TX_TNL_LSO_MSS_G(x) \
1587 (((x) >> CPL_TX_TNL_LSO_MSS_S) & CPL_TX_TNL_LSO_MSS_M)
1588
1589#define CPL_TX_TNL_LSO_SIZE_S 0
1590#define CPL_TX_TNL_LSO_SIZE_M 0xfffffff
1591#define CPL_TX_TNL_LSO_SIZE_V(x) ((x) << CPL_TX_TNL_LSO_SIZE_S)
1592#define CPL_TX_TNL_LSO_SIZE_G(x) \
1593 (((x) >> CPL_TX_TNL_LSO_SIZE_S) & CPL_TX_TNL_LSO_SIZE_M)
1594
1595#define CPL_TX_TNL_LSO_ETHHDRLENOUT_S 16
1596#define CPL_TX_TNL_LSO_ETHHDRLENOUT_M 0xf
1597#define CPL_TX_TNL_LSO_ETHHDRLENOUT_V(x) \
1598 ((x) << CPL_TX_TNL_LSO_ETHHDRLENOUT_S)
1599#define CPL_TX_TNL_LSO_ETHHDRLENOUT_G(x) \
1600 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENOUT_S) & CPL_TX_TNL_LSO_ETHHDRLENOUT_M)
1601
1602#define CPL_TX_TNL_LSO_IPHDRLENOUT_S 4
1603#define CPL_TX_TNL_LSO_IPHDRLENOUT_M 0xfff
1604#define CPL_TX_TNL_LSO_IPHDRLENOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLENOUT_S)
1605#define CPL_TX_TNL_LSO_IPHDRLENOUT_G(x) \
1606 (((x) >> CPL_TX_TNL_LSO_IPHDRLENOUT_S) & CPL_TX_TNL_LSO_IPHDRLENOUT_M)
1607
1608#define CPL_TX_TNL_LSO_IPHDRCHKOUT_S 3
1609#define CPL_TX_TNL_LSO_IPHDRCHKOUT_M 0x1
1610#define CPL_TX_TNL_LSO_IPHDRCHKOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRCHKOUT_S)
1611#define CPL_TX_TNL_LSO_IPHDRCHKOUT_G(x) \
1612 (((x) >> CPL_TX_TNL_LSO_IPHDRCHKOUT_S) & CPL_TX_TNL_LSO_IPHDRCHKOUT_M)
1613#define CPL_TX_TNL_LSO_IPHDRCHKOUT_F CPL_TX_TNL_LSO_IPHDRCHKOUT_V(1U)
1614
1615#define CPL_TX_TNL_LSO_IPLENSETOUT_S 2
1616#define CPL_TX_TNL_LSO_IPLENSETOUT_M 0x1
1617#define CPL_TX_TNL_LSO_IPLENSETOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPLENSETOUT_S)
1618#define CPL_TX_TNL_LSO_IPLENSETOUT_G(x) \
1619 (((x) >> CPL_TX_TNL_LSO_IPLENSETOUT_S) & CPL_TX_TNL_LSO_IPLENSETOUT_M)
1620#define CPL_TX_TNL_LSO_IPLENSETOUT_F CPL_TX_TNL_LSO_IPLENSETOUT_V(1U)
1621
1622#define CPL_TX_TNL_LSO_IPIDINCOUT_S 1
1623#define CPL_TX_TNL_LSO_IPIDINCOUT_M 0x1
1624#define CPL_TX_TNL_LSO_IPIDINCOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPIDINCOUT_S)
1625#define CPL_TX_TNL_LSO_IPIDINCOUT_G(x) \
1626 (((x) >> CPL_TX_TNL_LSO_IPIDINCOUT_S) & CPL_TX_TNL_LSO_IPIDINCOUT_M)
1627#define CPL_TX_TNL_LSO_IPIDINCOUT_F CPL_TX_TNL_LSO_IPIDINCOUT_V(1U)
1628
1629#define CPL_TX_TNL_LSO_UDPCHKCLROUT_S 14
1630#define CPL_TX_TNL_LSO_UDPCHKCLROUT_M 0x1
1631#define CPL_TX_TNL_LSO_UDPCHKCLROUT_V(x) \
1632 ((x) << CPL_TX_TNL_LSO_UDPCHKCLROUT_S)
1633#define CPL_TX_TNL_LSO_UDPCHKCLROUT_G(x) \
1634 (((x) >> CPL_TX_TNL_LSO_UDPCHKCLROUT_S) & \
1635 CPL_TX_TNL_LSO_UDPCHKCLROUT_M)
1636#define CPL_TX_TNL_LSO_UDPCHKCLROUT_F CPL_TX_TNL_LSO_UDPCHKCLROUT_V(1U)
1637
1638#define CPL_TX_TNL_LSO_UDPLENSETOUT_S 15
1639#define CPL_TX_TNL_LSO_UDPLENSETOUT_M 0x1
1640#define CPL_TX_TNL_LSO_UDPLENSETOUT_V(x) \
1641 ((x) << CPL_TX_TNL_LSO_UDPLENSETOUT_S)
1642#define CPL_TX_TNL_LSO_UDPLENSETOUT_G(x) \
1643 (((x) >> CPL_TX_TNL_LSO_UDPLENSETOUT_S) & \
1644 CPL_TX_TNL_LSO_UDPLENSETOUT_M)
1645#define CPL_TX_TNL_LSO_UDPLENSETOUT_F CPL_TX_TNL_LSO_UDPLENSETOUT_V(1U)
1646
1647#define CPL_TX_TNL_LSO_TNLTYPE_S 12
1648#define CPL_TX_TNL_LSO_TNLTYPE_M 0x3
1649#define CPL_TX_TNL_LSO_TNLTYPE_V(x) ((x) << CPL_TX_TNL_LSO_TNLTYPE_S)
1650#define CPL_TX_TNL_LSO_TNLTYPE_G(x) \
1651 (((x) >> CPL_TX_TNL_LSO_TNLTYPE_S) & CPL_TX_TNL_LSO_TNLTYPE_M)
1652
1653#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
1654#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
1655#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
1656#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
1657 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
1658
1659#define CPL_TX_TNL_LSO_TNLHDRLEN_S 0
1660#define CPL_TX_TNL_LSO_TNLHDRLEN_M 0xfff
1661#define CPL_TX_TNL_LSO_TNLHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TNLHDRLEN_S)
1662#define CPL_TX_TNL_LSO_TNLHDRLEN_G(x) \
1663 (((x) >> CPL_TX_TNL_LSO_TNLHDRLEN_S) & CPL_TX_TNL_LSO_TNLHDRLEN_M)
1664
1665#define CPL_TX_TNL_LSO_IPV6_S 20
1666#define CPL_TX_TNL_LSO_IPV6_M 0x1
1667#define CPL_TX_TNL_LSO_IPV6_V(x) ((x) << CPL_TX_TNL_LSO_IPV6_S)
1668#define CPL_TX_TNL_LSO_IPV6_G(x) \
1669 (((x) >> CPL_TX_TNL_LSO_IPV6_S) & CPL_TX_TNL_LSO_IPV6_M)
1670#define CPL_TX_TNL_LSO_IPV6_F CPL_TX_TNL_LSO_IPV6_V(1U)
1671
d6657781
HS		 1672#define ULP_TX_SC_MORE_S 23
1673#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1674#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1675
bbc02c7e
DM		 1676struct ulp_mem_io {
1677 WR_HDR;
1678 __be32 cmd;
bbc02c7e
DM		 1679 __be32 len16; /* command length */
1680 __be32 dlen; /* data length in 32-byte units */
bbc02c7e 1681 __be32 lock_addr;
bbc02c7e
DM		 1682};
1683
bdc590b9
HS		 1684#define ULP_MEMIO_LOCK_S 31
1685#define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1686#define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1687
d7990b0c
AB		 1688/* additional ulp_mem_io.cmd fields */
1689#define ULP_MEMIO_ORDER_S 23
1690#define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1691#define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1692
1693#define T5_ULP_MEMIO_IMM_S 23
1694#define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1695#define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1696
bdc590b9
HS		 1697#define T5_ULP_MEMIO_ORDER_S 22
1698#define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1699#define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
42b6a949 1700
92f850ec
H		 1701#define T5_ULP_MEMIO_FID_S 4
1702#define T5_ULP_MEMIO_FID_M 0x7ff
1703#define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S)
1704
d7990b0c
AB		 1705/* ulp_mem_io.lock_addr fields */
1706#define ULP_MEMIO_ADDR_S 0
1707#define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1708
1709/* ulp_mem_io.dlen fields */
1710#define ULP_MEMIO_DATA_LEN_S 0
1711#define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1712
d6657781
HS		 1713#define ULPTX_NSGE_S 0
1714#define ULPTX_NSGE_M 0xFFFF
1715#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1716#define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
1717
1718struct ulptx_sc_memrd {
1719 __be32 cmd_to_len;
1720 __be32 addr;
1721};
1722
1723#define ULP_TXPKT_DATAMODIFY_S 23
1724#define ULP_TXPKT_DATAMODIFY_M 0x1
1725#define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S)
1726#define ULP_TXPKT_DATAMODIFY_G(x) \
1727 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
1728#define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U)
1729
1730#define ULP_TXPKT_CHANNELID_S 22
1731#define ULP_TXPKT_CHANNELID_M 0x1
1732#define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
1733#define ULP_TXPKT_CHANNELID_G(x) \
1734 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
1735#define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U)
1736
1737#define SCMD_SEQ_NO_CTRL_S 29
1738#define SCMD_SEQ_NO_CTRL_M 0x3
1739#define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S)
1740#define SCMD_SEQ_NO_CTRL_G(x) \
1741 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
1742
1743/* StsFieldPrsnt- Status field at the end of the TLS PDU */
1744#define SCMD_STATUS_PRESENT_S 28
1745#define SCMD_STATUS_PRESENT_M 0x1
1746#define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S)
1747#define SCMD_STATUS_PRESENT_G(x) \
1748 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
1749#define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U)
1750
1751/* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
1752 * 3-15: Reserved.
1753 */
1754#define SCMD_PROTO_VERSION_S 24
1755#define SCMD_PROTO_VERSION_M 0xf
1756#define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
1757#define SCMD_PROTO_VERSION_G(x) \
1758 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
1759
1760/* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
1761#define SCMD_ENC_DEC_CTRL_S 23
1762#define SCMD_ENC_DEC_CTRL_M 0x1
1763#define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S)
1764#define SCMD_ENC_DEC_CTRL_G(x) \
1765 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
1766#define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
1767
1768/* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */
1769#define SCMD_CIPH_AUTH_SEQ_CTRL_S 22
1770#define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1
1771#define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \
1772 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S)
1773#define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \
1774 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M)
1775#define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U)
1776
1777/* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR,
1778 * 4:Generic-AES, 5-15: Reserved.
1779 */
1780#define SCMD_CIPH_MODE_S 18
1781#define SCMD_CIPH_MODE_M 0xf
1782#define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S)
1783#define SCMD_CIPH_MODE_G(x) \
1784 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M)
1785
1786/* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256
1787 * 4-15: Reserved
1788 */
1789#define SCMD_AUTH_MODE_S 14
1790#define SCMD_AUTH_MODE_M 0xf
1791#define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S)
1792#define SCMD_AUTH_MODE_G(x) \
1793 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M)
1794
1795/* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation
1796 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved
1797 */
1798#define SCMD_HMAC_CTRL_S 11
1799#define SCMD_HMAC_CTRL_M 0x7
1800#define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S)
1801#define SCMD_HMAC_CTRL_G(x) \
1802 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M)
1803
1804/* IvSize - IV size in units of 2 bytes */
1805#define SCMD_IV_SIZE_S 7
1806#define SCMD_IV_SIZE_M 0xf
1807#define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S)
1808#define SCMD_IV_SIZE_G(x) \
1809 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M)
1810
1811/* NumIVs - Number of IVs */
1812#define SCMD_NUM_IVS_S 0
1813#define SCMD_NUM_IVS_M 0x7f
1814#define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S)
1815#define SCMD_NUM_IVS_G(x) \
1816 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M)
1817
1818/* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber
1819 * (below) are used as Cid (connection id for debug status), these
1820 * bits are padded to zero for forming the 64 bit
1821 * sequence number for TLS
1822 */
1823#define SCMD_ENB_DBGID_S 31
1824#define SCMD_ENB_DBGID_M 0x1
1825#define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S)
1826#define SCMD_ENB_DBGID_G(x) \
1827 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M)
1828
1829/* IV generation in SW. */
1830#define SCMD_IV_GEN_CTRL_S 30
1831#define SCMD_IV_GEN_CTRL_M 0x1
1832#define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S)
1833#define SCMD_IV_GEN_CTRL_G(x) \
1834 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M)
1835#define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U)
1836
1837/* More frags */
1838#define SCMD_MORE_FRAGS_S 20
1839#define SCMD_MORE_FRAGS_M 0x1
1840#define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S)
1841#define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M)
1842
1843/*last frag */
1844#define SCMD_LAST_FRAG_S 19
1845#define SCMD_LAST_FRAG_M 0x1
1846#define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S)
1847#define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M)
1848
1849/* TlsCompPdu */
1850#define SCMD_TLS_COMPPDU_S 18
1851#define SCMD_TLS_COMPPDU_M 0x1
1852#define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S)
1853#define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M)
1854
1855/* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/
1856#define SCMD_KEY_CTX_INLINE_S 17
1857#define SCMD_KEY_CTX_INLINE_M 0x1
1858#define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S)
1859#define SCMD_KEY_CTX_INLINE_G(x) \
1860 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M)
1861#define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U)
1862
1863/* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */
1864#define SCMD_TLS_FRAG_ENABLE_S 16
1865#define SCMD_TLS_FRAG_ENABLE_M 0x1
1866#define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S)
1867#define SCMD_TLS_FRAG_ENABLE_G(x) \
1868 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M)
1869#define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U)
1870
1871/* MacOnly - Only send the MAC and discard PDU. This is valid for hash only
1872 * modes, in this case TLS_TX will drop the PDU and only
1873 * send back the MAC bytes.
1874 */
1875#define SCMD_MAC_ONLY_S 15
1876#define SCMD_MAC_ONLY_M 0x1
1877#define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S)
1878#define SCMD_MAC_ONLY_G(x) \
1879 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M)
1880#define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U)
1881
1882/* AadIVDrop - Drop the AAD and IV fields. Useful in protocols
1883 * which have complex AAD and IV formations Eg:AES-CCM
1884 */
1885#define SCMD_AADIVDROP_S 14
1886#define SCMD_AADIVDROP_M 0x1
1887#define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S)
1888#define SCMD_AADIVDROP_G(x) \
1889 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M)
1890#define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U)
1891
1892/* HdrLength - Length of all headers excluding TLS header
1893 * present before start of crypto PDU/payload.
1894 */
1895#define SCMD_HDR_LEN_S 0
1896#define SCMD_HDR_LEN_M 0x3fff
1897#define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S)
1898#define SCMD_HDR_LEN_G(x) \
1899 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M)
1900
1901struct cpl_tx_sec_pdu {
1902 __be32 op_ivinsrtofst;
1903 __be32 pldlen;
1904 __be32 aadstart_cipherstop_hi;
1905 __be32 cipherstop_lo_authinsert;
1906 __be32 seqno_numivs;
1907 __be32 ivgen_hdrlen;
1908 __be64 scmd1;
1909};
1910
1911#define CPL_TX_SEC_PDU_OPCODE_S 24
1912#define CPL_TX_SEC_PDU_OPCODE_M 0xff
1913#define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S)
1914#define CPL_TX_SEC_PDU_OPCODE_G(x) \
1915 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M)
1916
1917/* RX Channel Id */
1918#define CPL_TX_SEC_PDU_RXCHID_S 22
1919#define CPL_TX_SEC_PDU_RXCHID_M 0x1
1920#define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S)
1921#define CPL_TX_SEC_PDU_RXCHID_G(x) \
1922 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M)
1923#define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U)
1924
1925/* Ack Follows */
1926#define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21
1927#define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1
1928#define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S)
1929#define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \
1930 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M)
1931#define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U)
1932
1933/* Loopback bit in cpl_tx_sec_pdu */
1934#define CPL_TX_SEC_PDU_ULPTXLPBK_S 20
1935#define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1
1936#define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S)
1937#define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \
1938 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M)
1939#define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U)
1940
1941/* Length of cpl header encapsulated */
1942#define CPL_TX_SEC_PDU_CPLLEN_S 16
1943#define CPL_TX_SEC_PDU_CPLLEN_M 0xf
1944#define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S)
1945#define CPL_TX_SEC_PDU_CPLLEN_G(x) \
1946 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M)
1947
1948/* PlaceHolder */
1949#define CPL_TX_SEC_PDU_PLACEHOLDER_S 10
1950#define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1
1951#define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S)
1952#define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \
1953 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \
1954 CPL_TX_SEC_PDU_PLACEHOLDER_M)
1955
1956/* IvInsrtOffset: Insertion location for IV */
1957#define CPL_TX_SEC_PDU_IVINSRTOFST_S 0
1958#define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff
1959#define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S)
1960#define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \
1961 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \
1962 CPL_TX_SEC_PDU_IVINSRTOFST_M)
1963
1964/* AadStartOffset: Offset in bytes for AAD start from
1965 * the first byte following the pkt headers (0-255 bytes)
1966 */
1967#define CPL_TX_SEC_PDU_AADSTART_S 24
1968#define CPL_TX_SEC_PDU_AADSTART_M 0xff
1969#define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S)
1970#define CPL_TX_SEC_PDU_AADSTART_G(x) \
1971 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \
1972 CPL_TX_SEC_PDU_AADSTART_M)
1973
1974/* AadStopOffset: offset in bytes for AAD stop/end from the first byte following
1975 * the pkt headers (0-511 bytes)
1976 */
1977#define CPL_TX_SEC_PDU_AADSTOP_S 15
1978#define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff
1979#define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S)
1980#define CPL_TX_SEC_PDU_AADSTOP_G(x) \
1981 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M)
1982
1983/* CipherStartOffset: offset in bytes for encryption/decryption start from the
1984 * first byte following the pkt headers (0-1023 bytes)
1985 */
1986#define CPL_TX_SEC_PDU_CIPHERSTART_S 5
1987#define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff
1988#define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S)
1989#define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \
1990 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \
1991 CPL_TX_SEC_PDU_CIPHERSTART_M)
1992
1993/* CipherStopOffset: offset in bytes for encryption/decryption end
1994 * from end of the payload of this command (0-511 bytes)
1995 */
1996#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0
1997#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f
1998#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \
1999 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S)
2000#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \
2001 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \
2002 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M)
2003
2004#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28
2005#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf
2006#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \
2007 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S)
2008#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \
2009 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \
2010 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M)
2011
2012/* AuthStartOffset: offset in bytes for authentication start from
2013 * the first byte following the pkt headers (0-1023)
2014 */
2015#define CPL_TX_SEC_PDU_AUTHSTART_S 18
2016#define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff
2017#define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S)
2018#define CPL_TX_SEC_PDU_AUTHSTART_G(x) \
2019 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \
2020 CPL_TX_SEC_PDU_AUTHSTART_M)
2021
2022/* AuthStopOffset: offset in bytes for authentication
2023 * end from end of the payload of this command (0-511 Bytes)
2024 */
2025#define CPL_TX_SEC_PDU_AUTHSTOP_S 9
2026#define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff
2027#define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S)
2028#define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \
2029 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \
2030 CPL_TX_SEC_PDU_AUTHSTOP_M)
2031
2032/* AuthInsrtOffset: offset in bytes for authentication insertion
2033 * from end of the payload of this command (0-511 bytes)
2034 */
2035#define CPL_TX_SEC_PDU_AUTHINSERT_S 0
2036#define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff
2037#define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S)
2038#define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \
2039 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \
2040 CPL_TX_SEC_PDU_AUTHINSERT_M)
2041
2042struct cpl_rx_phys_dsgl {
2043 __be32 op_to_tid;
2044 __be32 pcirlxorder_to_noofsgentr;
2045 struct rss_header rss_hdr_int;
2046};
2047
2048#define CPL_RX_PHYS_DSGL_OPCODE_S 24
2049#define CPL_RX_PHYS_DSGL_OPCODE_M 0xff
2050#define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S)
2051#define CPL_RX_PHYS_DSGL_OPCODE_G(x) \
2052 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M)
2053
2054#define CPL_RX_PHYS_DSGL_ISRDMA_S 23
2055#define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1
2056#define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S)
2057#define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \
2058 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M)
2059#define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U)
2060
2061#define CPL_RX_PHYS_DSGL_RSVD1_S 20
2062#define CPL_RX_PHYS_DSGL_RSVD1_M 0x7
2063#define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S)
2064#define CPL_RX_PHYS_DSGL_RSVD1_G(x) \
2065 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \
2066 CPL_RX_PHYS_DSGL_RSVD1_M)
2067
2068#define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31
2069#define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1
2070#define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \
2071 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S)
2072#define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \
2073 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \
2074 CPL_RX_PHYS_DSGL_PCIRLXORDER_M)
2075#define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)
2076
2077#define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30
2078#define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1
2079#define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \
2080 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S)
2081#define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \
2082 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \
2083 CPL_RX_PHYS_DSGL_PCINOSNOOP_M)
2084
2085#define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U)
2086
2087#define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29
2088#define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1
2089#define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \
2090 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S)
2091#define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \
2092 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \
2093 CPL_RX_PHYS_DSGL_PCITPHNTENB_M)
2094#define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U)
2095
2096#define CPL_RX_PHYS_DSGL_PCITPHNT_S 27
2097#define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3
2098#define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S)
2099#define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \
2100 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \
2101 CPL_RX_PHYS_DSGL_PCITPHNT_M)
2102
2103#define CPL_RX_PHYS_DSGL_DCAID_S 16
2104#define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff
2105#define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S)
2106#define CPL_RX_PHYS_DSGL_DCAID_G(x) \
2107 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \
2108 CPL_RX_PHYS_DSGL_DCAID_M)
2109
2110#define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0
2111#define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff
2112#define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \
2113 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S)
2114#define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \
2115 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \
2116 CPL_RX_PHYS_DSGL_NOOFSGENTR_M)
2117
a4569504
AG		 2118struct cpl_rx_mps_pkt {
2119 __be32 op_to_r1_hi;
2120 __be32 r1_lo_length;
2121};
2122
2123#define CPL_RX_MPS_PKT_OP_S 24
2124#define CPL_RX_MPS_PKT_OP_M 0xff
2125#define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S)
2126#define CPL_RX_MPS_PKT_OP_G(x) \
2127 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M)
2128
2129#define CPL_RX_MPS_PKT_TYPE_S 20
2130#define CPL_RX_MPS_PKT_TYPE_M 0xf
2131#define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S)
2132#define CPL_RX_MPS_PKT_TYPE_G(x) \
2133 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M)
2134
2135enum {
2136 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0,
2137 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1,
2138 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2,
2139 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3
2140};
a3cdaa69
RR		 2141
2142struct cpl_srq_table_req {
2143 WR_HDR;
2144 union opcode_tid ot;
2145 __u8 status;
2146 __u8 rsvd[2];
2147 __u8 idx;
2148 __be64 rsvd_pdid;
2149 __be32 qlen_qbase;
2150 __be16 cur_msn;
2151 __be16 max_msn;
2152};
2153
2154struct cpl_srq_table_rpl {
2155 union opcode_tid ot;
2156 __u8 status;
2157 __u8 rsvd[2];
2158 __u8 idx;
2159 __be64 rsvd_pdid;
2160 __be32 qlen_qbase;
2161 __be16 cur_msn;
2162 __be16 max_msn;
2163};
2164
2165/* cpl_srq_table_{req,rpl}.params fields */
2166#define SRQT_QLEN_S 28
2167#define SRQT_QLEN_M 0xF
2168#define SRQT_QLEN_V(x) ((x) << SRQT_QLEN_S)
2169#define SRQT_QLEN_G(x) (((x) >> SRQT_QLEN_S) & SRQT_QLEN_M)
2170
2171#define SRQT_QBASE_S 0
2172#define SRQT_QBASE_M 0x3FFFFFF
2173#define SRQT_QBASE_V(x) ((x) << SRQT_QBASE_S)
2174#define SRQT_QBASE_G(x) (((x) >> SRQT_QBASE_S) & SRQT_QBASE_M)
2175
2176#define SRQT_PDID_S 0
2177#define SRQT_PDID_M 0xFF
2178#define SRQT_PDID_V(x) ((x) << SRQT_PDID_S)
2179#define SRQT_PDID_G(x) (((x) >> SRQT_PDID_S) & SRQT_PDID_M)
2180
2181#define SRQT_IDX_S 0
2182#define SRQT_IDX_M 0xF
2183#define SRQT_IDX_V(x) ((x) << SRQT_IDX_S)
2184#define SRQT_IDX_G(x) (((x) >> SRQT_IDX_S) & SRQT_IDX_M)
2185
bbc02c7e 2186#endif /* __T4_MSG_H */
Ubuntu Eoan Linux kernel mirror