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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / cisco / enic / enic_main.c
CommitLineData
01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF		 27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF		 32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF		 34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
7c2ce6e6 41#include <linux/ktime.h>
b6e97c13
GV		 42#ifdef CONFIG_RFS_ACCEL
43#include <linux/cpu_rmap.h>
44#endif
14747cd9
GV		 45#ifdef CONFIG_NET_RX_BUSY_POLL
46#include <net/busy_poll.h>
47#endif
3f255dcc 48#include <linux/crash_dump.h>
01f2e4ea
SF		 49
50#include "cq_enet_desc.h"
51#include "vnic_dev.h"
52#include "vnic_intr.h"
53#include "vnic_stats.h"
f8bd9091 54#include "vnic_vic.h"
01f2e4ea
SF		 55#include "enic_res.h"
56#include "enic.h"
51987461 57#include "enic_dev.h"
b3abfbd2 58#include "enic_pp.h"
a145df23 59#include "enic_clsf.h"
01f2e4ea
SF		 60
61#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
SF		 62#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
63#define MAX_TSO (1 << 16)
64#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
65
66#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 67#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 68#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea 69
a03bb56e
GV		 70#define RX_COPYBREAK_DEFAULT 256
71
01f2e4ea 72/* Supported devices */
9baa3c34 73static const struct pci_device_id enic_id_table[] = {
ea0d7d91 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 76 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF		 77 { 0, } /* end of table */
78};
79
80MODULE_DESCRIPTION(DRV_DESCRIPTION);
81MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_VERSION);
84MODULE_DEVICE_TABLE(pci, enic_id_table);
85
7c2ce6e6
SS		 86#define ENIC_LARGE_PKT_THRESHOLD 1000
87#define ENIC_MAX_COALESCE_TIMERS 10
88/* Interrupt moderation table, which will be used to decide the
89 * coalescing timer values
90 * {rx_rate in Mbps, mapping percentage of the range}
91 */
57ae84a0 92static struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
7c2ce6e6
SS		 93 {4000, 0},
94 {4400, 10},
95 {5060, 20},
96 {5230, 30},
97 {5540, 40},
98 {5820, 50},
99 {6120, 60},
100 {6435, 70},
101 {6745, 80},
102 {7000, 90},
103 {0xFFFFFFFF, 100}
104};
105
106/* This table helps the driver to pick different ranges for rx coalescing
107 * timer depending on the link speed.
108 */
57ae84a0 109static struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
7c2ce6e6
SS		 110 {0, 0}, /* 0 - 4 Gbps */
111 {0, 3}, /* 4 - 10 Gbps */
112 {3, 6}, /* 10 - 40 Gbps */
113};
114
3f192795 115int enic_is_dynamic(struct enic *enic)
f8bd9091
SF		 116{
117 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
118}
119
8749b427
RP		 120int enic_sriov_enabled(struct enic *enic)
121{
122 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
123}
124
3a4adef5
RP		 125static int enic_is_sriov_vf(struct enic *enic)
126{
127 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
128}
129
889d13f5
RP		 130int enic_is_valid_vf(struct enic *enic, int vf)
131{
132#ifdef CONFIG_PCI_IOV
133 return vf >= 0 && vf < enic->num_vfs;
134#else
135 return 0;
136#endif
137}
138
01f2e4ea
SF		 139static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
140{
141 struct enic *enic = vnic_dev_priv(wq->vdev);
142
143 if (buf->sop)
144 pci_unmap_single(enic->pdev, buf->dma_addr,
145 buf->len, PCI_DMA_TODEVICE);
146 else
147 pci_unmap_page(enic->pdev, buf->dma_addr,
148 buf->len, PCI_DMA_TODEVICE);
149
150 if (buf->os_buf)
151 dev_kfree_skb_any(buf->os_buf);
152}
153
154static void enic_wq_free_buf(struct vnic_wq *wq,
155 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
156{
157 enic_free_wq_buf(wq, buf);
158}
159
160static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
161 u8 type, u16 q_number, u16 completed_index, void *opaque)
162{
163 struct enic *enic = vnic_dev_priv(vdev);
164
165 spin_lock(&enic->wq_lock[q_number]);
166
167 vnic_wq_service(&enic->wq[q_number], cq_desc,
168 completed_index, enic_wq_free_buf,
169 opaque);
170
822473b6 171 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
SF		 172 vnic_wq_desc_avail(&enic->wq[q_number]) >=
173 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 174 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF		 175
176 spin_unlock(&enic->wq_lock[q_number]);
177
178 return 0;
179}
180
181static void enic_log_q_error(struct enic *enic)
182{
183 unsigned int i;
184 u32 error_status;
185
186 for (i = 0; i < enic->wq_count; i++) {
187 error_status = vnic_wq_error_status(&enic->wq[i]);
188 if (error_status)
a7a79deb
VK		 189 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
190 i, error_status);
01f2e4ea
SF		 191 }
192
193 for (i = 0; i < enic->rq_count; i++) {
194 error_status = vnic_rq_error_status(&enic->rq[i]);
195 if (error_status)
a7a79deb
VK		 196 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
197 i, error_status);
01f2e4ea
SF		 198 }
199}
200
383ab92f 201static void enic_msglvl_check(struct enic *enic)
01f2e4ea 202{
383ab92f 203 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 204
383ab92f 205 if (msg_enable != enic->msg_enable) {
a7a79deb
VK		 206 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
207 enic->msg_enable, msg_enable);
383ab92f 208 enic->msg_enable = msg_enable;
01f2e4ea
SF		 209 }
210}
211
212static void enic_mtu_check(struct enic *enic)
213{
214 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 215 struct net_device *netdev = enic->netdev;
01f2e4ea 216
491598a4 217 if (mtu && mtu != enic->port_mtu) {
7c844599 218 enic->port_mtu = mtu;
7335903c 219 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP		 220 mtu = max_t(int, ENIC_MIN_MTU,
221 min_t(int, ENIC_MAX_MTU, mtu));
222 if (mtu != netdev->mtu)
223 schedule_work(&enic->change_mtu_work);
224 } else {
225 if (mtu < netdev->mtu)
226 netdev_warn(netdev,
227 "interface MTU (%d) set higher "
228 "than switch port MTU (%d)\n",
229 netdev->mtu, mtu);
230 }
01f2e4ea
SF		 231 }
232}
233
383ab92f 234static void enic_link_check(struct enic *enic)
01f2e4ea 235{
383ab92f
VK		 236 int link_status = vnic_dev_link_status(enic->vdev);
237 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 238
383ab92f 239 if (link_status && !carrier_ok) {
a7a79deb 240 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK		 241 netif_carrier_on(enic->netdev);
242 } else if (!link_status && carrier_ok) {
a7a79deb 243 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 244 netif_carrier_off(enic->netdev);
01f2e4ea
SF		 245 }
246}
247
248static void enic_notify_check(struct enic *enic)
249{
250 enic_msglvl_check(enic);
251 enic_mtu_check(enic);
252 enic_link_check(enic);
253}
254
255#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
256
257static irqreturn_t enic_isr_legacy(int irq, void *data)
258{
259 struct net_device *netdev = data;
260 struct enic *enic = netdev_priv(netdev);
717258ba
VK		 261 unsigned int io_intr = enic_legacy_io_intr();
262 unsigned int err_intr = enic_legacy_err_intr();
263 unsigned int notify_intr = enic_legacy_notify_intr();
01f2e4ea
SF		 264 u32 pba;
265
717258ba 266 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
SF		 267
268 pba = vnic_intr_legacy_pba(enic->legacy_pba);
269 if (!pba) {
717258ba 270 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 271 return IRQ_NONE; /* not our interrupt */
272 }
273
717258ba 274 if (ENIC_TEST_INTR(pba, notify_intr)) {
01f2e4ea 275 enic_notify_check(enic);
2b0c2e2d 276 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
ed8af6b2 277 }
01f2e4ea 278
717258ba
VK		 279 if (ENIC_TEST_INTR(pba, err_intr)) {
280 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
SF		 281 enic_log_q_error(enic);
282 /* schedule recovery from WQ/RQ error */
283 schedule_work(&enic->reset);
284 return IRQ_HANDLED;
285 }
286
db40b3f5
GV		 287 if (ENIC_TEST_INTR(pba, io_intr))
288 napi_schedule_irqoff(&enic->napi[0]);
289 else
717258ba 290 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 291
292 return IRQ_HANDLED;
293}
294
295static irqreturn_t enic_isr_msi(int irq, void *data)
296{
297 struct enic *enic = data;
298
299 /* With MSI, there is no sharing of interrupts, so this is
300 * our interrupt and there is no need to ack it. The device
301 * is not providing per-vector masking, so the OS will not
302 * write to PCI config space to mask/unmask the interrupt.
303 * We're using mask_on_assertion for MSI, so the device
304 * automatically masks the interrupt when the interrupt is
305 * generated. Later, when exiting polling, the interrupt
306 * will be unmasked (see enic_poll).
307 *
308 * Also, the device uses the same PCIe Traffic Class (TC)
309 * for Memory Write data and MSI, so there are no ordering
310 * issues; the MSI will always arrive at the Root Complex
311 * _after_ corresponding Memory Writes (i.e. descriptor
312 * writes).
313 */
314
db40b3f5 315 napi_schedule_irqoff(&enic->napi[0]);
01f2e4ea
SF		 316
317 return IRQ_HANDLED;
318}
319
4cfe8785 320static irqreturn_t enic_isr_msix(int irq, void *data)
01f2e4ea 321{
717258ba 322 struct napi_struct *napi = data;
01f2e4ea 323
db40b3f5 324 napi_schedule_irqoff(napi);
01f2e4ea
SF		 325
326 return IRQ_HANDLED;
327}
328
01f2e4ea
SF		 329static irqreturn_t enic_isr_msix_err(int irq, void *data)
330{
331 struct enic *enic = data;
717258ba 332 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 333
717258ba 334 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 335
01f2e4ea
SF		 336 enic_log_q_error(enic);
337
338 /* schedule recovery from WQ/RQ error */
339 schedule_work(&enic->reset);
340
341 return IRQ_HANDLED;
342}
343
344static irqreturn_t enic_isr_msix_notify(int irq, void *data)
345{
346 struct enic *enic = data;
717258ba 347 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea
SF		 348
349 enic_notify_check(enic);
2b0c2e2d 350 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea
SF		 351
352 return IRQ_HANDLED;
353}
354
065df159
GV		 355static int enic_queue_wq_skb_cont(struct enic *enic, struct vnic_wq *wq,
356 struct sk_buff *skb, unsigned int len_left,
357 int loopback)
01f2e4ea 358{
9e903e08 359 const skb_frag_t *frag;
065df159 360 dma_addr_t dma_addr;
01f2e4ea
SF		 361
362 /* Queue additional data fragments */
363 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 364 len_left -= skb_frag_size(frag);
065df159
GV		 365 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 0,
366 skb_frag_size(frag),
367 DMA_TO_DEVICE);
368 if (unlikely(enic_dma_map_check(enic, dma_addr)))
369 return -ENOMEM;
370 enic_queue_wq_desc_cont(wq, skb, dma_addr, skb_frag_size(frag),
371 (len_left == 0), /* EOP? */
372 loopback);
01f2e4ea 373 }
065df159
GV		 374
375 return 0;
01f2e4ea
SF		 376}
377
065df159
GV		 378static int enic_queue_wq_skb_vlan(struct enic *enic, struct vnic_wq *wq,
379 struct sk_buff *skb, int vlan_tag_insert,
380 unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 381{
382 unsigned int head_len = skb_headlen(skb);
383 unsigned int len_left = skb->len - head_len;
384 int eop = (len_left == 0);
065df159
GV		 385 dma_addr_t dma_addr;
386 int err = 0;
387
388 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
389 PCI_DMA_TODEVICE);
390 if (unlikely(enic_dma_map_check(enic, dma_addr)))
391 return -ENOMEM;
01f2e4ea 392
ea0d7d91
SF		 393 /* Queue the main skb fragment. The fragments are no larger
394 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
395 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
396 * per fragment is queued.
397 */
065df159
GV		 398 enic_queue_wq_desc(wq, skb, dma_addr, head_len, vlan_tag_insert,
399 vlan_tag, eop, loopback);
01f2e4ea
SF		 400
401 if (!eop)
065df159
GV		 402 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
403
404 return err;
01f2e4ea
SF		 405}
406
065df159
GV		 407static int enic_queue_wq_skb_csum_l4(struct enic *enic, struct vnic_wq *wq,
408 struct sk_buff *skb, int vlan_tag_insert,
409 unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 410{
411 unsigned int head_len = skb_headlen(skb);
412 unsigned int len_left = skb->len - head_len;
0d0b1672 413 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF		 414 unsigned int csum_offset = hdr_len + skb->csum_offset;
415 int eop = (len_left == 0);
065df159
GV		 416 dma_addr_t dma_addr;
417 int err = 0;
418
419 dma_addr = pci_map_single(enic->pdev, skb->data, head_len,
420 PCI_DMA_TODEVICE);
421 if (unlikely(enic_dma_map_check(enic, dma_addr)))
422 return -ENOMEM;
01f2e4ea 423
ea0d7d91
SF		 424 /* Queue the main skb fragment. The fragments are no larger
425 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
426 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
427 * per fragment is queued.
428 */
065df159
GV		 429 enic_queue_wq_desc_csum_l4(wq, skb, dma_addr, head_len, csum_offset,
430 hdr_len, vlan_tag_insert, vlan_tag, eop,
431 loopback);
01f2e4ea
SF		 432
433 if (!eop)
065df159
GV		 434 err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
435
436 return err;
01f2e4ea
SF		 437}
438
065df159
GV		 439static int enic_queue_wq_skb_tso(struct enic *enic, struct vnic_wq *wq,
440 struct sk_buff *skb, unsigned int mss,
441 int vlan_tag_insert, unsigned int vlan_tag,
442 int loopback)
01f2e4ea 443{
ea0d7d91
SF		 444 unsigned int frag_len_left = skb_headlen(skb);
445 unsigned int len_left = skb->len - frag_len_left;
01f2e4ea
SF		 446 unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
447 int eop = (len_left == 0);
ea0d7d91
SF		 448 unsigned int len;
449 dma_addr_t dma_addr;
450 unsigned int offset = 0;
451 skb_frag_t *frag;
01f2e4ea
SF		 452
453 /* Preload TCP csum field with IP pseudo hdr calculated
454 * with IP length set to zero. HW will later add in length
455 * to each TCP segment resulting from the TSO.
456 */
457
09640e63 458 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF		 459 ip_hdr(skb)->check = 0;
460 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
461 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 462 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
01f2e4ea
SF		 463 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
464 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
465 }
466
ea0d7d91
SF		 467 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
468 * for the main skb fragment
469 */
470 while (frag_len_left) {
471 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
065df159
GV		 472 dma_addr = pci_map_single(enic->pdev, skb->data + offset, len,
473 PCI_DMA_TODEVICE);
474 if (unlikely(enic_dma_map_check(enic, dma_addr)))
475 return -ENOMEM;
476 enic_queue_wq_desc_tso(wq, skb, dma_addr, len, mss, hdr_len,
477 vlan_tag_insert, vlan_tag,
478 eop && (len == frag_len_left), loopback);
ea0d7d91
SF		 479 frag_len_left -= len;
480 offset += len;
481 }
01f2e4ea 482
ea0d7d91 483 if (eop)
065df159 484 return 0;
ea0d7d91
SF		 485
486 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
487 * for additional data fragments
488 */
489 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED		 490 len_left -= skb_frag_size(frag);
491 frag_len_left = skb_frag_size(frag);
4bf5adbf 492 offset = 0;
ea0d7d91
SF		 493
494 while (frag_len_left) {
495 len = min(frag_len_left,
496 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC		 497 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
498 offset, len,
5d6bcdfe 499 DMA_TO_DEVICE);
065df159
GV		 500 if (unlikely(enic_dma_map_check(enic, dma_addr)))
501 return -ENOMEM;
502 enic_queue_wq_desc_cont(wq, skb, dma_addr, len,
503 (len_left == 0) &&
504 (len == frag_len_left),/*EOP*/
505 loopback);
ea0d7d91
SF		 506 frag_len_left -= len;
507 offset += len;
508 }
509 }
065df159
GV		 510
511 return 0;
01f2e4ea
SF		 512}
513
514static inline void enic_queue_wq_skb(struct enic *enic,
515 struct vnic_wq *wq, struct sk_buff *skb)
516{
517 unsigned int mss = skb_shinfo(skb)->gso_size;
518 unsigned int vlan_tag = 0;
519 int vlan_tag_insert = 0;
1825aca6 520 int loopback = 0;
065df159 521 int err;
01f2e4ea 522
df8a39de 523 if (skb_vlan_tag_present(skb)) {
01f2e4ea
SF		 524 /* VLAN tag from trunking driver */
525 vlan_tag_insert = 1;
df8a39de 526 vlan_tag = skb_vlan_tag_get(skb);
1825aca6
VK		 527 } else if (enic->loop_enable) {
528 vlan_tag = enic->loop_tag;
529 loopback = 1;
01f2e4ea
SF		 530 }
531
532 if (mss)
065df159
GV		 533 err = enic_queue_wq_skb_tso(enic, wq, skb, mss,
534 vlan_tag_insert, vlan_tag,
535 loopback);
01f2e4ea 536 else if (skb->ip_summed == CHECKSUM_PARTIAL)
065df159
GV		 537 err = enic_queue_wq_skb_csum_l4(enic, wq, skb, vlan_tag_insert,
538 vlan_tag, loopback);
01f2e4ea 539 else
065df159
GV		 540 err = enic_queue_wq_skb_vlan(enic, wq, skb, vlan_tag_insert,
541 vlan_tag, loopback);
542 if (unlikely(err)) {
543 struct vnic_wq_buf *buf;
544
545 buf = wq->to_use->prev;
546 /* while not EOP of previous pkt && queue not empty.
547 * For all non EOP bufs, os_buf is NULL.
548 */
549 while (!buf->os_buf && (buf->next != wq->to_clean)) {
550 enic_free_wq_buf(wq, buf);
551 wq->ring.desc_avail++;
552 buf = buf->prev;
553 }
554 wq->to_use = buf->next;
555 dev_kfree_skb(skb);
556 }
01f2e4ea
SF		 557}
558
ed8af6b2 559/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 560static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 561 struct net_device *netdev)
01f2e4ea
SF		 562{
563 struct enic *enic = netdev_priv(netdev);
822473b6 564 struct vnic_wq *wq;
822473b6 565 unsigned int txq_map;
f8e34d24 566 struct netdev_queue *txq;
01f2e4ea
SF		 567
568 if (skb->len <= 0) {
98d8a65d 569 dev_kfree_skb_any(skb);
01f2e4ea
SF		 570 return NETDEV_TX_OK;
571 }
572
822473b6 573 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
574 wq = &enic->wq[txq_map];
f8e34d24 575 txq = netdev_get_tx_queue(netdev, txq_map);
822473b6 576
01f2e4ea
SF		 577 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
578 * which is very likely. In the off chance it's going to take
579 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
580 */
581
582 if (skb_shinfo(skb)->gso_size == 0 &&
583 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
584 skb_linearize(skb)) {
98d8a65d 585 dev_kfree_skb_any(skb);
01f2e4ea
SF		 586 return NETDEV_TX_OK;
587 }
588
78e2045d 589 spin_lock(&enic->wq_lock[txq_map]);
01f2e4ea 590
ea0d7d91
SF		 591 if (vnic_wq_desc_avail(wq) <
592 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
f8e34d24 593 netif_tx_stop_queue(txq);
01f2e4ea 594 /* This is a hard error, log it */
a7a79deb 595 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
78e2045d 596 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 597 return NETDEV_TX_BUSY;
598 }
599
600 enic_queue_wq_skb(enic, wq, skb);
601
ea0d7d91 602 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
f8e34d24
GV		 603 netif_tx_stop_queue(txq);
604 if (!skb->xmit_more || netif_xmit_stopped(txq))
605 vnic_wq_doorbell(wq);
01f2e4ea 606
78e2045d 607 spin_unlock(&enic->wq_lock[txq_map]);
01f2e4ea
SF		 608
609 return NETDEV_TX_OK;
610}
611
612/* dev_base_lock rwlock held, nominally process context */
f20530bc 613static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev,
614 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF		 615{
616 struct enic *enic = netdev_priv(netdev);
617 struct vnic_stats *stats;
618
383ab92f 619 enic_dev_stats_dump(enic, &stats);
01f2e4ea 620
25f0a061
SF		 621 net_stats->tx_packets = stats->tx.tx_frames_ok;
622 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
623 net_stats->tx_errors = stats->tx.tx_errors;
624 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 625
25f0a061
SF		 626 net_stats->rx_packets = stats->rx.rx_frames_ok;
627 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
628 net_stats->rx_errors = stats->rx.rx_errors;
629 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 630 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 631 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 632 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea 633
25f0a061 634 return net_stats;
01f2e4ea
SF		 635}
636
f009618a
AD		 637static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
638{
639 struct enic *enic = netdev_priv(netdev);
640
641 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
642 unsigned int mc_count = netdev_mc_count(netdev);
643
644 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
645 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
646
647 return -ENOSPC;
648 }
649
650 enic_dev_add_addr(enic, mc_addr);
651 enic->mc_count++;
652
653 return 0;
654}
655
656static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
657{
658 struct enic *enic = netdev_priv(netdev);
659
660 enic_dev_del_addr(enic, mc_addr);
661 enic->mc_count--;
662
663 return 0;
664}
665
666static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
667{
668 struct enic *enic = netdev_priv(netdev);
669
670 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
671 unsigned int uc_count = netdev_uc_count(netdev);
672
673 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
674 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
675
676 return -ENOSPC;
677 }
678
679 enic_dev_add_addr(enic, uc_addr);
680 enic->uc_count++;
681
682 return 0;
683}
684
685static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
686{
687 struct enic *enic = netdev_priv(netdev);
688
689 enic_dev_del_addr(enic, uc_addr);
690 enic->uc_count--;
691
692 return 0;
693}
694
b3abfbd2 695void enic_reset_addr_lists(struct enic *enic)
01f2e4ea 696{
f009618a
AD		 697 struct net_device *netdev = enic->netdev;
698
699 __dev_uc_unsync(netdev, NULL);
700 __dev_mc_unsync(netdev, NULL);
701
01f2e4ea 702 enic->mc_count = 0;
e0afe53f 703 enic->uc_count = 0;
99ef5639 704 enic->flags = 0;
01f2e4ea
SF		 705}
706
707static int enic_set_mac_addr(struct net_device *netdev, char *addr)
708{
f8bd9091
SF		 709 struct enic *enic = netdev_priv(netdev);
710
7335903c 711 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF		 712 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
713 return -EADDRNOTAVAIL;
714 } else {
715 if (!is_valid_ether_addr(addr))
716 return -EADDRNOTAVAIL;
717 }
01f2e4ea
SF		 718
719 memcpy(netdev->dev_addr, addr, netdev->addr_len);
720
721 return 0;
722}
723
f8bd9091
SF		 724static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
725{
726 struct enic *enic = netdev_priv(netdev);
727 struct sockaddr *saddr = p;
728 char *addr = saddr->sa_data;
729 int err;
730
731 if (netif_running(enic->netdev)) {
732 err = enic_dev_del_station_addr(enic);
733 if (err)
734 return err;
735 }
736
737 err = enic_set_mac_addr(netdev, addr);
738 if (err)
739 return err;
740
741 if (netif_running(enic->netdev)) {
742 err = enic_dev_add_station_addr(enic);
743 if (err)
744 return err;
745 }
746
747 return err;
748}
749
750static int enic_set_mac_address(struct net_device *netdev, void *p)
751{
294dab25 752 struct sockaddr *saddr = p;
c76fd32d
VK		 753 char *addr = saddr->sa_data;
754 struct enic *enic = netdev_priv(netdev);
755 int err;
756
757 err = enic_dev_del_station_addr(enic);
758 if (err)
759 return err;
760
761 err = enic_set_mac_addr(netdev, addr);
762 if (err)
763 return err;
294dab25 764
c76fd32d 765 return enic_dev_add_station_addr(enic);
f8bd9091
SF		 766}
767
319d7e84
RP		 768/* netif_tx_lock held, BHs disabled */
769static void enic_set_rx_mode(struct net_device *netdev)
770{
771 struct enic *enic = netdev_priv(netdev);
772 int directed = 1;
773 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
774 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
775 int promisc = (netdev->flags & IFF_PROMISC) ||
776 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
777 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
778 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
779 unsigned int flags = netdev->flags |
780 (allmulti ? IFF_ALLMULTI : 0) |
781 (promisc ? IFF_PROMISC : 0);
782
783 if (enic->flags != flags) {
784 enic->flags = flags;
785 enic_dev_packet_filter(enic, directed,
786 multicast, broadcast, promisc, allmulti);
787 }
788
789 if (!promisc) {
f009618a 790 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
319d7e84 791 if (!allmulti)
f009618a 792 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
319d7e84
RP		 793 }
794}
795
01f2e4ea
SF		 796/* netif_tx_lock held, BHs disabled */
797static void enic_tx_timeout(struct net_device *netdev)
798{
799 struct enic *enic = netdev_priv(netdev);
800 schedule_work(&enic->reset);
801}
802
0b1c00fc
RP		 803static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
804{
805 struct enic *enic = netdev_priv(netdev);
3f192795
RP		 806 struct enic_port_profile *pp;
807 int err;
0b1c00fc 808
3f192795
RP		 809 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
810 if (err)
811 return err;
0b1c00fc 812
b8622cbd 813 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP		 814 if (vf == PORT_SELF_VF) {
815 memcpy(pp->vf_mac, mac, ETH_ALEN);
816 return 0;
817 } else {
818 /*
819 * For sriov vf's set the mac in hw
820 */
821 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
822 vnic_dev_set_mac_addr, mac);
823 return enic_dev_status_to_errno(err);
824 }
0b1c00fc
RP		 825 } else
826 return -EINVAL;
827}
828
f8bd9091
SF		 829static int enic_set_vf_port(struct net_device *netdev, int vf,
830 struct nlattr *port[])
831{
832 struct enic *enic = netdev_priv(netdev);
b3abfbd2 833 struct enic_port_profile prev_pp;
3f192795 834 struct enic_port_profile *pp;
b3abfbd2 835 int err = 0, restore_pp = 1;
08f382eb 836
3f192795
RP		 837 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
838 if (err)
839 return err;
08f382eb 840
b3abfbd2
RP		 841 if (!port[IFLA_PORT_REQUEST])
842 return -EOPNOTSUPP;
843
3f192795
RP		 844 memcpy(&prev_pp, pp, sizeof(*enic->pp));
845 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 846
3f192795
RP		 847 pp->set |= ENIC_SET_REQUEST;
848 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF		 849
850 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP		 851 pp->set |= ENIC_SET_NAME;
852 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF		 853 PORT_PROFILE_MAX);
854 }
855
856 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP		 857 pp->set |= ENIC_SET_INSTANCE;
858 memcpy(pp->instance_uuid,
08f382eb
SF		 859 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
860 }
861
862 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP		 863 pp->set |= ENIC_SET_HOST;
864 memcpy(pp->host_uuid,
08f382eb
SF		 865 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
866 }
f8bd9091 867
b4765833
RP		 868 if (vf == PORT_SELF_VF) {
869 /* Special case handling: mac came from IFLA_VF_MAC */
870 if (!is_zero_ether_addr(prev_pp.vf_mac))
871 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 872
b4765833
RP		 873 if (is_zero_ether_addr(netdev->dev_addr))
874 eth_hw_addr_random(netdev);
875 } else {
876 /* SR-IOV VF: get mac from adapter */
877 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
878 vnic_dev_get_mac_addr, pp->mac_addr);
879 if (err) {
880 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
881 memcpy(pp, &prev_pp, sizeof(*pp));
882 return enic_dev_status_to_errno(err);
883 }
884 }
f8bd9091 885
3f192795 886 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP		 887 if (err) {
888 if (restore_pp) {
889 /* Things are still the way they were: Implicit
890 * DISASSOCIATE failed
891 */
3f192795 892 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 893 } else {
3f192795
RP		 894 memset(pp, 0, sizeof(*pp));
895 if (vf == PORT_SELF_VF)
c7bf7169 896 eth_zero_addr(netdev->dev_addr);
b3abfbd2
RP		 897 }
898 } else {
899 /* Set flag to indicate that the port assoc/disassoc
900 * request has been sent out to fw
901 */
3f192795 902 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP		 903
904 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795 905 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
c7bf7169 906 eth_zero_addr(pp->mac_addr);
3f192795 907 if (vf == PORT_SELF_VF)
c7bf7169 908 eth_zero_addr(netdev->dev_addr);
b3abfbd2
RP		 909 }
910 }
29639059 911
b4765833 912 if (vf == PORT_SELF_VF)
c7bf7169 913 eth_zero_addr(pp->vf_mac);
29639059 914
29639059 915 return err;
f8bd9091
SF		 916}
917
918static int enic_get_vf_port(struct net_device *netdev, int vf,
919 struct sk_buff *skb)
920{
921 struct enic *enic = netdev_priv(netdev);
f8bd9091 922 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 923 struct enic_port_profile *pp;
b3abfbd2 924 int err;
f8bd9091 925
3f192795
RP		 926 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
927 if (err)
928 return err;
929
930 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 931 return -ENODATA;
f8bd9091 932
3f192795 933 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 934 if (err)
b3abfbd2 935 return err;
f8bd9091 936
1a106de6
DM		 937 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
938 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
939 ((pp->set & ENIC_SET_NAME) &&
940 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
941 ((pp->set & ENIC_SET_INSTANCE) &&
942 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
943 pp->instance_uuid)) ||
944 ((pp->set & ENIC_SET_HOST) &&
945 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
946 goto nla_put_failure;
f8bd9091
SF		 947 return 0;
948
949nla_put_failure:
950 return -EMSGSIZE;
951}
952
01f2e4ea
SF		 953static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
954{
955 struct enic *enic = vnic_dev_priv(rq->vdev);
956
957 if (!buf->os_buf)
958 return;
959
960 pci_unmap_single(enic->pdev, buf->dma_addr,
961 buf->len, PCI_DMA_FROMDEVICE);
962 dev_kfree_skb_any(buf->os_buf);
a03bb56e 963 buf->os_buf = NULL;
01f2e4ea
SF		 964}
965
01f2e4ea
SF		 966static int enic_rq_alloc_buf(struct vnic_rq *rq)
967{
968 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 969 struct net_device *netdev = enic->netdev;
01f2e4ea 970 struct sk_buff *skb;
1825aca6 971 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF		 972 unsigned int os_buf_index = 0;
973 dma_addr_t dma_addr;
a03bb56e
GV		 974 struct vnic_rq_buf *buf = rq->to_use;
975
976 if (buf->os_buf) {
f6b7734b
GV		 977 enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
978 buf->len);
01f2e4ea 979
a03bb56e
GV		 980 return 0;
981 }
89d71a66 982 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF		 983 if (!skb)
984 return -ENOMEM;
985
065df159
GV		 986 dma_addr = pci_map_single(enic->pdev, skb->data, len,
987 PCI_DMA_FROMDEVICE);
988 if (unlikely(enic_dma_map_check(enic, dma_addr))) {
989 dev_kfree_skb(skb);
990 return -ENOMEM;
991 }
01f2e4ea
SF		 992
993 enic_queue_rq_desc(rq, skb, os_buf_index,
994 dma_addr, len);
995
996 return 0;
997}
998
7c2ce6e6
SS		 999static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
1000 u32 pkt_len)
1001{
1002 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
1003 pkt_size->large_pkt_bytes_cnt += pkt_len;
1004 else
1005 pkt_size->small_pkt_bytes_cnt += pkt_len;
1006}
1007
a03bb56e
GV		 1008static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
1009 struct vnic_rq_buf *buf, u16 len)
1010{
1011 struct enic *enic = netdev_priv(netdev);
1012 struct sk_buff *new_skb;
1013
1014 if (len > enic->rx_copybreak)
1015 return false;
1016 new_skb = netdev_alloc_skb_ip_align(netdev, len);
1017 if (!new_skb)
1018 return false;
1019 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
1020 DMA_FROM_DEVICE);
1021 memcpy(new_skb->data, (*skb)->data, len);
1022 *skb = new_skb;
1023
1024 return true;
1025}
1026
01f2e4ea
SF		 1027static void enic_rq_indicate_buf(struct vnic_rq *rq,
1028 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
1029 int skipped, void *opaque)
1030{
1031 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 1032 struct net_device *netdev = enic->netdev;
01f2e4ea 1033 struct sk_buff *skb;
7c2ce6e6 1034 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
01f2e4ea
SF		 1035
1036 u8 type, color, eop, sop, ingress_port, vlan_stripped;
1037 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
1038 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
1039 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
1040 u8 packet_error;
f8cac14a 1041 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea
SF		 1042 u32 rss_hash;
1043
1044 if (skipped)
1045 return;
1046
1047 skb = buf->os_buf;
01f2e4ea
SF		 1048
1049 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
1050 &type, &color, &q_number, &completed_index,
1051 &ingress_port, &fcoe, &eop, &sop, &rss_type,
1052 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 1053 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF		 1054 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
1055 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
1056 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
1057 &fcs_ok);
1058
1059 if (packet_error) {
1060
350991e1
SF		 1061 if (!fcs_ok) {
1062 if (bytes_written > 0)
1063 enic->rq_bad_fcs++;
1064 else if (bytes_written == 0)
1065 enic->rq_truncated_pkts++;
1066 }
01f2e4ea 1067
44aa91ab
GV		 1068 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1069 PCI_DMA_FROMDEVICE);
01f2e4ea 1070 dev_kfree_skb_any(skb);
44aa91ab 1071 buf->os_buf = NULL;
01f2e4ea
SF		 1072
1073 return;
1074 }
1075
1076 if (eop && bytes_written > 0) {
1077
1078 /* Good receive
1079 */
1080
a03bb56e
GV		 1081 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
1082 buf->os_buf = NULL;
1083 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1084 PCI_DMA_FROMDEVICE);
1085 }
1086 prefetch(skb->data - NET_IP_ALIGN);
1087
01f2e4ea 1088 skb_put(skb, bytes_written);
86ca9db7 1089 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1090 skb_record_rx_queue(skb, q_number);
1091 if (netdev->features & NETIF_F_RXHASH) {
3739acdd
TH		 1092 skb_set_hash(skb, rss_hash,
1093 (rss_type &
1094 (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX |
1095 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 |
1096 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ?
1097 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
bf751ba8 1098 }
01f2e4ea 1099
17e96834
GV		 1100 /* Hardware does not provide whole packet checksum. It only
1101 * provides pseudo checksum. Since hw validates the packet
1102 * checksum but not provide us the checksum value. use
1103 * CHECSUM_UNNECESSARY.
1104 */
1105 if ((netdev->features & NETIF_F_RXCSUM) && tcp_udp_csum_ok &&
1106 ipv4_csum_ok)
1107 skb->ip_summed = CHECKSUM_UNNECESSARY;
01f2e4ea 1108
6ede746b 1109 if (vlan_stripped)
86a9bad3 1110 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1111
14747cd9
GV		 1112 skb_mark_napi_id(skb, &enic->napi[rq->index]);
1113 if (enic_poll_busy_polling(rq) ||
1114 !(netdev->features & NETIF_F_GRO))
6ede746b 1115 netif_receive_skb(skb);
14747cd9
GV		 1116 else
1117 napi_gro_receive(&enic->napi[q_number], skb);
7c2ce6e6
SS		 1118 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1119 enic_intr_update_pkt_size(&cq->pkt_size_counter,
1120 bytes_written);
01f2e4ea
SF		 1121 } else {
1122
1123 /* Buffer overflow
1124 */
1125
44aa91ab
GV		 1126 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
1127 PCI_DMA_FROMDEVICE);
01f2e4ea 1128 dev_kfree_skb_any(skb);
44aa91ab 1129 buf->os_buf = NULL;
01f2e4ea
SF		 1130 }
1131}
1132
1133static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1134 u8 type, u16 q_number, u16 completed_index, void *opaque)
1135{
1136 struct enic *enic = vnic_dev_priv(vdev);
1137
1138 vnic_rq_service(&enic->rq[q_number], cq_desc,
1139 completed_index, VNIC_RQ_RETURN_DESC,
1140 enic_rq_indicate_buf, opaque);
1141
1142 return 0;
1143}
1144
01f2e4ea
SF		 1145static int enic_poll(struct napi_struct *napi, int budget)
1146{
717258ba
VK		 1147 struct net_device *netdev = napi->dev;
1148 struct enic *enic = netdev_priv(netdev);
1149 unsigned int cq_rq = enic_cq_rq(enic, 0);
1150 unsigned int cq_wq = enic_cq_wq(enic, 0);
1151 unsigned int intr = enic_legacy_io_intr();
01f2e4ea
SF		 1152 unsigned int rq_work_to_do = budget;
1153 unsigned int wq_work_to_do = -1; /* no limit */
4c502549 1154 unsigned int work_done, rq_work_done = 0, wq_work_done;
2d6ddced 1155 int err;
01f2e4ea 1156
14747cd9
GV		 1157 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
1158 enic_wq_service, NULL);
1159
1160 if (!enic_poll_lock_napi(&enic->rq[cq_rq])) {
1161 if (wq_work_done > 0)
1162 vnic_intr_return_credits(&enic->intr[intr],
1163 wq_work_done,
1164 0 /* dont unmask intr */,
1165 0 /* dont reset intr timer */);
1166 return rq_work_done;
1167 }
01f2e4ea 1168
4c502549
EB		 1169 if (budget > 0)
1170 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
1171 rq_work_to_do, enic_rq_service, NULL);
01f2e4ea 1172
01f2e4ea
SF		 1173 /* Accumulate intr event credits for this polling
1174 * cycle. An intr event is the completion of a
1175 * a WQ or RQ packet.
1176 */
1177
1178 work_done = rq_work_done + wq_work_done;
1179
1180 if (work_done > 0)
717258ba 1181 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1182 work_done,
1183 0 /* don't unmask intr */,
1184 0 /* don't reset intr timer */);
1185
0eb26022 1186 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1187
2d6ddced
SF		 1188 /* Buffer allocation failed. Stay in polling
1189 * mode so we can try to fill the ring again.
1190 */
01f2e4ea 1191
2d6ddced
SF		 1192 if (err)
1193 rq_work_done = rq_work_to_do;
01f2e4ea 1194
2d6ddced 1195 if (rq_work_done < rq_work_to_do) {
01f2e4ea 1196
2d6ddced 1197 /* Some work done, but not enough to stay in polling,
88132f55 1198 * exit polling
01f2e4ea
SF		 1199 */
1200
288379f0 1201 napi_complete(napi);
717258ba 1202 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1203 }
14747cd9 1204 enic_poll_unlock_napi(&enic->rq[cq_rq]);
01f2e4ea
SF		 1205
1206 return rq_work_done;
1207}
1208
7c2ce6e6
SS		 1209static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
1210{
1211 unsigned int intr = enic_msix_rq_intr(enic, rq->index);
1212 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1213 u32 timer = cq->tobe_rx_coal_timeval;
1214
1215 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
1216 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
1217 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
1218 }
1219}
1220
1221static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
1222{
1223 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1224 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1225 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
1226 int index;
1227 u32 timer;
1228 u32 range_start;
1229 u32 traffic;
1230 u64 delta;
1231 ktime_t now = ktime_get();
1232
1233 delta = ktime_us_delta(now, cq->prev_ts);
1234 if (delta < ENIC_AIC_TS_BREAK)
1235 return;
1236 cq->prev_ts = now;
1237
1238 traffic = pkt_size_counter->large_pkt_bytes_cnt +
1239 pkt_size_counter->small_pkt_bytes_cnt;
1240 /* The table takes Mbps
1241 * traffic *= 8 => bits
1242 * traffic *= (10^6 / delta) => bps
1243 * traffic /= 10^6 => Mbps
1244 *
1245 * Combining, traffic *= (8 / delta)
1246 */
1247
1248 traffic <<= 3;
958c492c 1249 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
7c2ce6e6
SS		 1250
1251 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
1252 if (traffic < mod_table[index].rx_rate)
1253 break;
1254 range_start = (pkt_size_counter->small_pkt_bytes_cnt >
1255 pkt_size_counter->large_pkt_bytes_cnt << 1) ?
1256 rx_coal->small_pkt_range_start :
1257 rx_coal->large_pkt_range_start;
1258 timer = range_start + ((rx_coal->range_end - range_start) *
1259 mod_table[index].range_percent / 100);
1260 /* Damping */
1261 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
1262
1263 pkt_size_counter->large_pkt_bytes_cnt = 0;
1264 pkt_size_counter->small_pkt_bytes_cnt = 0;
1265}
1266
b6e97c13
GV		 1267#ifdef CONFIG_RFS_ACCEL
1268static void enic_free_rx_cpu_rmap(struct enic *enic)
1269{
1270 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
1271 enic->netdev->rx_cpu_rmap = NULL;
1272}
1273
1274static void enic_set_rx_cpu_rmap(struct enic *enic)
1275{
1276 int i, res;
1277
1278 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
1279 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
1280 if (unlikely(!enic->netdev->rx_cpu_rmap))
1281 return;
1282 for (i = 0; i < enic->rq_count; i++) {
1283 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
1284 enic->msix_entry[i].vector);
1285 if (unlikely(res)) {
1286 enic_free_rx_cpu_rmap(enic);
1287 return;
1288 }
1289 }
1290 }
1291}
1292
1293#else
1294
1295static void enic_free_rx_cpu_rmap(struct enic *enic)
1296{
1297}
1298
1299static void enic_set_rx_cpu_rmap(struct enic *enic)
1300{
1301}
1302
1303#endif /* CONFIG_RFS_ACCEL */
1304
14747cd9 1305#ifdef CONFIG_NET_RX_BUSY_POLL
57ae84a0 1306static int enic_busy_poll(struct napi_struct *napi)
14747cd9
GV		 1307{
1308 struct net_device *netdev = napi->dev;
1309 struct enic *enic = netdev_priv(netdev);
1310 unsigned int rq = (napi - &enic->napi[0]);
1311 unsigned int cq = enic_cq_rq(enic, rq);
1312 unsigned int intr = enic_msix_rq_intr(enic, rq);
1313 unsigned int work_to_do = -1; /* clean all pkts possible */
1314 unsigned int work_done;
1315
1316 if (!enic_poll_lock_poll(&enic->rq[rq]))
1317 return LL_FLUSH_BUSY;
1318 work_done = vnic_cq_service(&enic->cq[cq], work_to_do,
1319 enic_rq_service, NULL);
1320
1321 if (work_done > 0)
1322 vnic_intr_return_credits(&enic->intr[intr],
1323 work_done, 0, 0);
1324 vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
1325 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1326 enic_calc_int_moderation(enic, &enic->rq[rq]);
1327 enic_poll_unlock_poll(&enic->rq[rq]);
1328
1329 return work_done;
1330}
1331#endif /* CONFIG_NET_RX_BUSY_POLL */
1332
4cfe8785
GV		 1333static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
1334{
1335 struct net_device *netdev = napi->dev;
1336 struct enic *enic = netdev_priv(netdev);
1337 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
1338 struct vnic_wq *wq = &enic->wq[wq_index];
1339 unsigned int cq;
1340 unsigned int intr;
1341 unsigned int wq_work_to_do = -1; /* clean all desc possible */
1342 unsigned int wq_work_done;
1343 unsigned int wq_irq;
1344
1345 wq_irq = wq->index;
1346 cq = enic_cq_wq(enic, wq_irq);
1347 intr = enic_msix_wq_intr(enic, wq_irq);
1348 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
1349 enic_wq_service, NULL);
1350
1351 vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
1352 0 /* don't unmask intr */,
1353 1 /* reset intr timer */);
1354 if (!wq_work_done) {
1355 napi_complete(napi);
1356 vnic_intr_unmask(&enic->intr[intr]);
f41281d0 1357 return 0;
4cfe8785
GV		 1358 }
1359
f41281d0 1360 return budget;
4cfe8785
GV		 1361}
1362
1363static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
01f2e4ea 1364{
717258ba
VK		 1365 struct net_device *netdev = napi->dev;
1366 struct enic *enic = netdev_priv(netdev);
1367 unsigned int rq = (napi - &enic->napi[0]);
1368 unsigned int cq = enic_cq_rq(enic, rq);
1369 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea 1370 unsigned int work_to_do = budget;
4c502549 1371 unsigned int work_done = 0;
2d6ddced 1372 int err;
01f2e4ea 1373
14747cd9 1374 if (!enic_poll_lock_napi(&enic->rq[rq]))
f104fedc 1375 return budget;
01f2e4ea
SF		 1376 /* Service RQ
1377 */
1378
4c502549
EB		 1379 if (budget > 0)
1380 work_done = vnic_cq_service(&enic->cq[cq],
1381 work_to_do, enic_rq_service, NULL);
01f2e4ea 1382
2d6ddced
SF		 1383 /* Return intr event credits for this polling
1384 * cycle. An intr event is the completion of a
1385 * RQ packet.
1386 */
01f2e4ea 1387
2d6ddced 1388 if (work_done > 0)
717258ba 1389 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1390 work_done,
1391 0 /* don't unmask intr */,
1392 0 /* don't reset intr timer */);
01f2e4ea 1393
0eb26022 1394 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF		 1395
1396 /* Buffer allocation failed. Stay in polling mode
1397 * so we can try to fill the ring again.
1398 */
1399
1400 if (err)
1401 work_done = work_to_do;
7c2ce6e6
SS		 1402 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1403 /* Call the function which refreshes
1404 * the intr coalescing timer value based on
1405 * the traffic. This is supported only in
1406 * the case of MSI-x mode
1407 */
1408 enic_calc_int_moderation(enic, &enic->rq[rq]);
2d6ddced
SF		 1409
1410 if (work_done < work_to_do) {
1411
1412 /* Some work done, but not enough to stay in polling,
88132f55 1413 * exit polling
01f2e4ea
SF		 1414 */
1415
288379f0 1416 napi_complete(napi);
7c2ce6e6
SS		 1417 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1418 enic_set_int_moderation(enic, &enic->rq[rq]);
717258ba 1419 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1420 }
14747cd9 1421 enic_poll_unlock_napi(&enic->rq[rq]);
01f2e4ea
SF		 1422
1423 return work_done;
1424}
1425
1426static void enic_notify_timer(unsigned long data)
1427{
1428 struct enic *enic = (struct enic *)data;
1429
1430 enic_notify_check(enic);
1431
25f0a061
SF		 1432 mod_timer(&enic->notify_timer,
1433 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF		 1434}
1435
1436static void enic_free_intr(struct enic *enic)
1437{
1438 struct net_device *netdev = enic->netdev;
1439 unsigned int i;
1440
b6e97c13 1441 enic_free_rx_cpu_rmap(enic);
01f2e4ea
SF		 1442 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1443 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF		 1444 free_irq(enic->pdev->irq, netdev);
1445 break;
8f4d248c
SF		 1446 case VNIC_DEV_INTR_MODE_MSI:
1447 free_irq(enic->pdev->irq, enic);
1448 break;
01f2e4ea
SF		 1449 case VNIC_DEV_INTR_MODE_MSIX:
1450 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1451 if (enic->msix[i].requested)
1452 free_irq(enic->msix_entry[i].vector,
1453 enic->msix[i].devid);
1454 break;
1455 default:
1456 break;
1457 }
1458}
1459
1460static int enic_request_intr(struct enic *enic)
1461{
1462 struct net_device *netdev = enic->netdev;
717258ba 1463 unsigned int i, intr;
01f2e4ea
SF		 1464 int err = 0;
1465
b6e97c13 1466 enic_set_rx_cpu_rmap(enic);
01f2e4ea
SF		 1467 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1468
1469 case VNIC_DEV_INTR_MODE_INTX:
1470
1471 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1472 IRQF_SHARED, netdev->name, netdev);
1473 break;
1474
1475 case VNIC_DEV_INTR_MODE_MSI:
1476
1477 err = request_irq(enic->pdev->irq, enic_isr_msi,
1478 0, netdev->name, enic);
1479 break;
1480
1481 case VNIC_DEV_INTR_MODE_MSIX:
1482
717258ba
VK		 1483 for (i = 0; i < enic->rq_count; i++) {
1484 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC		 1485 snprintf(enic->msix[intr].devname,
1486 sizeof(enic->msix[intr].devname),
717258ba 1487 "%.11s-rx-%d", netdev->name, i);
4cfe8785 1488 enic->msix[intr].isr = enic_isr_msix;
717258ba
VK		 1489 enic->msix[intr].devid = &enic->napi[i];
1490 }
01f2e4ea 1491
717258ba 1492 for (i = 0; i < enic->wq_count; i++) {
4cfe8785
GV		 1493 int wq = enic_cq_wq(enic, i);
1494
717258ba 1495 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC		 1496 snprintf(enic->msix[intr].devname,
1497 sizeof(enic->msix[intr].devname),
717258ba 1498 "%.11s-tx-%d", netdev->name, i);
4cfe8785
GV		 1499 enic->msix[intr].isr = enic_isr_msix;
1500 enic->msix[intr].devid = &enic->napi[wq];
717258ba 1501 }
01f2e4ea 1502
717258ba 1503 intr = enic_msix_err_intr(enic);
4505f40a
DC		 1504 snprintf(enic->msix[intr].devname,
1505 sizeof(enic->msix[intr].devname),
01f2e4ea 1506 "%.11s-err", netdev->name);
717258ba
VK		 1507 enic->msix[intr].isr = enic_isr_msix_err;
1508 enic->msix[intr].devid = enic;
01f2e4ea 1509
717258ba 1510 intr = enic_msix_notify_intr(enic);
4505f40a
DC		 1511 snprintf(enic->msix[intr].devname,
1512 sizeof(enic->msix[intr].devname),
01f2e4ea 1513 "%.11s-notify", netdev->name);
717258ba
VK		 1514 enic->msix[intr].isr = enic_isr_msix_notify;
1515 enic->msix[intr].devid = enic;
1516
1517 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1518 enic->msix[i].requested = 0;
01f2e4ea 1519
717258ba 1520 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF		 1521 err = request_irq(enic->msix_entry[i].vector,
1522 enic->msix[i].isr, 0,
1523 enic->msix[i].devname,
1524 enic->msix[i].devid);
1525 if (err) {
1526 enic_free_intr(enic);
1527 break;
1528 }
1529 enic->msix[i].requested = 1;
1530 }
1531
1532 break;
1533
1534 default:
1535 break;
1536 }
1537
1538 return err;
1539}
1540
b3d18d19
SF		 1541static void enic_synchronize_irqs(struct enic *enic)
1542{
1543 unsigned int i;
1544
1545 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1546 case VNIC_DEV_INTR_MODE_INTX:
1547 case VNIC_DEV_INTR_MODE_MSI:
1548 synchronize_irq(enic->pdev->irq);
1549 break;
1550 case VNIC_DEV_INTR_MODE_MSIX:
1551 for (i = 0; i < enic->intr_count; i++)
1552 synchronize_irq(enic->msix_entry[i].vector);
1553 break;
1554 default:
1555 break;
1556 }
1557}
1558
7c2ce6e6
SS		 1559static void enic_set_rx_coal_setting(struct enic *enic)
1560{
1561 unsigned int speed;
1562 int index = -1;
1563 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1564
1565 /* If intr mode is not MSIX, do not do adaptive coalescing */
1566 if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) {
1567 netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing");
1568 return;
1569 }
1570
1571 /* 1. Read the link speed from fw
1572 * 2. Pick the default range for the speed
1573 * 3. Update it in enic->rx_coalesce_setting
1574 */
1575 speed = vnic_dev_port_speed(enic->vdev);
1576 if (ENIC_LINK_SPEED_10G < speed)
1577 index = ENIC_LINK_40G_INDEX;
1578 else if (ENIC_LINK_SPEED_4G < speed)
1579 index = ENIC_LINK_10G_INDEX;
1580 else
1581 index = ENIC_LINK_4G_INDEX;
1582
1583 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
1584 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
1585 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
1586
1587 /* Start with the value provided by UCSM */
1588 for (index = 0; index < enic->rq_count; index++)
1589 enic->cq[index].cur_rx_coal_timeval =
1590 enic->config.intr_timer_usec;
1591
1592 rx_coal->use_adaptive_rx_coalesce = 1;
1593}
1594
383ab92f 1595static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF		 1596{
1597 int err;
1598
8e091340 1599 spin_lock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1600 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1601 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK		 1602 err = vnic_dev_notify_set(enic->vdev,
1603 enic_legacy_notify_intr());
01f2e4ea
SF		 1604 break;
1605 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1606 err = vnic_dev_notify_set(enic->vdev,
1607 enic_msix_notify_intr(enic));
01f2e4ea
SF		 1608 break;
1609 default:
1610 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1611 break;
1612 }
8e091340 1613 spin_unlock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1614
1615 return err;
1616}
1617
1618static void enic_notify_timer_start(struct enic *enic)
1619{
1620 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1621 case VNIC_DEV_INTR_MODE_MSI:
1622 mod_timer(&enic->notify_timer, jiffies);
1623 break;
1624 default:
1625 /* Using intr for notification for INTx/MSI-X */
1626 break;
6403eab1 1627 }
01f2e4ea
SF		 1628}
1629
1630/* rtnl lock is held, process context */
1631static int enic_open(struct net_device *netdev)
1632{
1633 struct enic *enic = netdev_priv(netdev);
1634 unsigned int i;
1635 int err;
1636
4b75a442
SF		 1637 err = enic_request_intr(enic);
1638 if (err) {
a7a79deb 1639 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF		 1640 return err;
1641 }
1642
383ab92f 1643 err = enic_dev_notify_set(enic);
4b75a442 1644 if (err) {
a7a79deb
VK		 1645 netdev_err(netdev,
1646 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF		 1647 goto err_out_free_intr;
1648 }
1649
01f2e4ea 1650 for (i = 0; i < enic->rq_count; i++) {
0eb26022 1651 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF		 1652 /* Need at least one buffer on ring to get going */
1653 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1654 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1655 err = -ENOMEM;
9dac6232 1656 goto err_out_free_rq;
01f2e4ea
SF		 1657 }
1658 }
1659
1660 for (i = 0; i < enic->wq_count; i++)
1661 vnic_wq_enable(&enic->wq[i]);
1662 for (i = 0; i < enic->rq_count; i++)
1663 vnic_rq_enable(&enic->rq[i]);
1664
7335903c 1665 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1666 enic_dev_add_station_addr(enic);
3f192795 1667
319d7e84 1668 enic_set_rx_mode(netdev);
01f2e4ea 1669
822473b6 1670 netif_tx_wake_all_queues(netdev);
717258ba 1671
14747cd9
GV		 1672 for (i = 0; i < enic->rq_count; i++) {
1673 enic_busy_poll_init_lock(&enic->rq[i]);
717258ba 1674 napi_enable(&enic->napi[i]);
14747cd9 1675 }
4cfe8785
GV		 1676 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1677 for (i = 0; i < enic->wq_count; i++)
1678 napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
383ab92f 1679 enic_dev_enable(enic);
01f2e4ea
SF		 1680
1681 for (i = 0; i < enic->intr_count; i++)
1682 vnic_intr_unmask(&enic->intr[i]);
1683
1684 enic_notify_timer_start(enic);
a145df23 1685 enic_rfs_flw_tbl_init(enic);
01f2e4ea
SF		 1686
1687 return 0;
4b75a442 1688
9dac6232
GV		 1689err_out_free_rq:
1690 for (i = 0; i < enic->rq_count; i++)
1691 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
383ab92f 1692 enic_dev_notify_unset(enic);
4b75a442
SF		 1693err_out_free_intr:
1694 enic_free_intr(enic);
1695
1696 return err;
01f2e4ea
SF		 1697}
1698
1699/* rtnl lock is held, process context */
1700static int enic_stop(struct net_device *netdev)
1701{
1702 struct enic *enic = netdev_priv(netdev);
1703 unsigned int i;
1704 int err;
1705
29046f9b 1706 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 1707 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK		 1708 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
1709 }
b3d18d19
SF		 1710
1711 enic_synchronize_irqs(enic);
1712
01f2e4ea 1713 del_timer_sync(&enic->notify_timer);
a145df23 1714 enic_rfs_flw_tbl_free(enic);
01f2e4ea 1715
383ab92f 1716 enic_dev_disable(enic);
717258ba 1717
14747cd9 1718 for (i = 0; i < enic->rq_count; i++) {
717258ba 1719 napi_disable(&enic->napi[i]);
39dc90c1 1720 local_bh_disable();
14747cd9
GV		 1721 while (!enic_poll_lock_napi(&enic->rq[i]))
1722 mdelay(1);
39dc90c1 1723 local_bh_enable();
14747cd9 1724 }
717258ba 1725
b3d18d19
SF		 1726 netif_carrier_off(netdev);
1727 netif_tx_disable(netdev);
4cfe8785
GV		 1728 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1729 for (i = 0; i < enic->wq_count; i++)
1730 napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
3f192795 1731
7335903c 1732 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1733 enic_dev_del_station_addr(enic);
f8bd9091 1734
01f2e4ea
SF		 1735 for (i = 0; i < enic->wq_count; i++) {
1736 err = vnic_wq_disable(&enic->wq[i]);
1737 if (err)
1738 return err;
1739 }
1740 for (i = 0; i < enic->rq_count; i++) {
1741 err = vnic_rq_disable(&enic->rq[i]);
1742 if (err)
1743 return err;
1744 }
1745
383ab92f 1746 enic_dev_notify_unset(enic);
4b75a442
SF		 1747 enic_free_intr(enic);
1748
01f2e4ea
SF		 1749 for (i = 0; i < enic->wq_count; i++)
1750 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
1751 for (i = 0; i < enic->rq_count; i++)
1752 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
1753 for (i = 0; i < enic->cq_count; i++)
1754 vnic_cq_clean(&enic->cq[i]);
1755 for (i = 0; i < enic->intr_count; i++)
1756 vnic_intr_clean(&enic->intr[i]);
1757
1758 return 0;
1759}
1760
1761static int enic_change_mtu(struct net_device *netdev, int new_mtu)
1762{
1763 struct enic *enic = netdev_priv(netdev);
1764 int running = netif_running(netdev);
1765
25f0a061
SF		 1766 if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU)
1767 return -EINVAL;
1768
7335903c 1769 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP		 1770 return -EOPNOTSUPP;
1771
01f2e4ea
SF		 1772 if (running)
1773 enic_stop(netdev);
1774
01f2e4ea
SF		 1775 netdev->mtu = new_mtu;
1776
1777 if (netdev->mtu > enic->port_mtu)
a7a79deb
VK		 1778 netdev_warn(netdev,
1779 "interface MTU (%d) set higher than port MTU (%d)\n",
1780 netdev->mtu, enic->port_mtu);
01f2e4ea
SF		 1781
1782 if (running)
1783 enic_open(netdev);
1784
1785 return 0;
1786}
1787
c97c894d
RP		 1788static void enic_change_mtu_work(struct work_struct *work)
1789{
1790 struct enic *enic = container_of(work, struct enic, change_mtu_work);
1791 struct net_device *netdev = enic->netdev;
1792 int new_mtu = vnic_dev_mtu(enic->vdev);
1793 int err;
1794 unsigned int i;
1795
1796 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
1797
1798 rtnl_lock();
1799
1800 /* Stop RQ */
1801 del_timer_sync(&enic->notify_timer);
1802
1803 for (i = 0; i < enic->rq_count; i++)
1804 napi_disable(&enic->napi[i]);
1805
1806 vnic_intr_mask(&enic->intr[0]);
1807 enic_synchronize_irqs(enic);
1808 err = vnic_rq_disable(&enic->rq[0]);
1809 if (err) {
e057590b 1810 rtnl_unlock();
c97c894d
RP		 1811 netdev_err(netdev, "Unable to disable RQ.\n");
1812 return;
1813 }
1814 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
1815 vnic_cq_clean(&enic->cq[0]);
1816 vnic_intr_clean(&enic->intr[0]);
1817
1818 /* Fill RQ with new_mtu-sized buffers */
1819 netdev->mtu = new_mtu;
1820 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
1821 /* Need at least one buffer on ring to get going */
1822 if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
e057590b 1823 rtnl_unlock();
c97c894d
RP		 1824 netdev_err(netdev, "Unable to alloc receive buffers.\n");
1825 return;
1826 }
1827
1828 /* Start RQ */
1829 vnic_rq_enable(&enic->rq[0]);
1830 napi_enable(&enic->napi[0]);
1831 vnic_intr_unmask(&enic->intr[0]);
1832 enic_notify_timer_start(enic);
1833
1834 rtnl_unlock();
1835
1836 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
1837}
1838
01f2e4ea
SF		 1839#ifdef CONFIG_NET_POLL_CONTROLLER
1840static void enic_poll_controller(struct net_device *netdev)
1841{
1842 struct enic *enic = netdev_priv(netdev);
1843 struct vnic_dev *vdev = enic->vdev;
717258ba 1844 unsigned int i, intr;
01f2e4ea
SF		 1845
1846 switch (vnic_dev_get_intr_mode(vdev)) {
1847 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1848 for (i = 0; i < enic->rq_count; i++) {
1849 intr = enic_msix_rq_intr(enic, i);
4cfe8785
GV		 1850 enic_isr_msix(enic->msix_entry[intr].vector,
1851 &enic->napi[i]);
717258ba 1852 }
b880a954
VK		 1853
1854 for (i = 0; i < enic->wq_count; i++) {
1855 intr = enic_msix_wq_intr(enic, i);
4cfe8785
GV		 1856 enic_isr_msix(enic->msix_entry[intr].vector,
1857 &enic->napi[enic_cq_wq(enic, i)]);
b880a954
VK		 1858 }
1859
01f2e4ea
SF		 1860 break;
1861 case VNIC_DEV_INTR_MODE_MSI:
1862 enic_isr_msi(enic->pdev->irq, enic);
1863 break;
1864 case VNIC_DEV_INTR_MODE_INTX:
1865 enic_isr_legacy(enic->pdev->irq, netdev);
1866 break;
1867 default:
1868 break;
1869 }
1870}
1871#endif
1872
1873static int enic_dev_wait(struct vnic_dev *vdev,
1874 int (*start)(struct vnic_dev *, int),
1875 int (*finished)(struct vnic_dev *, int *),
1876 int arg)
1877{
1878 unsigned long time;
1879 int done;
1880 int err;
1881
1882 BUG_ON(in_interrupt());
1883
1884 err = start(vdev, arg);
1885 if (err)
1886 return err;
1887
1888 /* Wait for func to complete...2 seconds max
1889 */
1890
1891 time = jiffies + (HZ * 2);
1892 do {
1893
1894 err = finished(vdev, &done);
1895 if (err)
1896 return err;
1897
1898 if (done)
1899 return 0;
1900
1901 schedule_timeout_uninterruptible(HZ / 10);
1902
1903 } while (time_after(time, jiffies));
1904
1905 return -ETIMEDOUT;
1906}
1907
1908static int enic_dev_open(struct enic *enic)
1909{
1910 int err;
1911
1912 err = enic_dev_wait(enic->vdev, vnic_dev_open,
1913 vnic_dev_open_done, 0);
1914 if (err)
a7a79deb
VK		 1915 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
1916 err);
01f2e4ea
SF		 1917
1918 return err;
1919}
1920
99ef5639 1921static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF		 1922{
1923 int err;
1924
99ef5639
VK		 1925 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
1926 vnic_dev_hang_reset_done, 0);
01f2e4ea 1927 if (err)
a7a79deb
VK		 1928 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
1929 err);
01f2e4ea
SF		 1930
1931 return err;
1932}
1933
4f675eb2 1934int __enic_set_rsskey(struct enic *enic)
717258ba 1935{
c33d23c2 1936 union vnic_rss_key *rss_key_buf_va;
1f4f067f 1937 dma_addr_t rss_key_buf_pa;
c33d23c2 1938 int i, kidx, bidx, err;
717258ba 1939
c33d23c2
ED		 1940 rss_key_buf_va = pci_zalloc_consistent(enic->pdev,
1941 sizeof(union vnic_rss_key),
1942 &rss_key_buf_pa);
717258ba
VK		 1943 if (!rss_key_buf_va)
1944 return -ENOMEM;
1945
c33d23c2
ED		 1946 for (i = 0; i < ENIC_RSS_LEN; i++) {
1947 kidx = i / ENIC_RSS_BYTES_PER_KEY;
1948 bidx = i % ENIC_RSS_BYTES_PER_KEY;
4f675eb2 1949 rss_key_buf_va->key[kidx].b[bidx] = enic->rss_key[i];
c33d23c2 1950 }
8e091340 1951 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1952 err = enic_set_rss_key(enic,
1953 rss_key_buf_pa,
1954 sizeof(union vnic_rss_key));
8e091340 1955 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1956
1957 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
1958 rss_key_buf_va, rss_key_buf_pa);
1959
1960 return err;
1961}
1962
4f675eb2
GV		 1963static int enic_set_rsskey(struct enic *enic)
1964{
1965 netdev_rss_key_fill(enic->rss_key, ENIC_RSS_LEN);
1966
1967 return __enic_set_rsskey(enic);
1968}
1969
717258ba
VK		 1970static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
1971{
1f4f067f 1972 dma_addr_t rss_cpu_buf_pa;
717258ba
VK		 1973 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
1974 unsigned int i;
1975 int err;
1976
1977 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
1978 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
1979 if (!rss_cpu_buf_va)
1980 return -ENOMEM;
1981
1982 for (i = 0; i < (1 << rss_hash_bits); i++)
1983 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
1984
8e091340 1985 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1986 err = enic_set_rss_cpu(enic,
1987 rss_cpu_buf_pa,
1988 sizeof(union vnic_rss_cpu));
8e091340 1989 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1990
1991 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
1992 rss_cpu_buf_va, rss_cpu_buf_pa);
1993
1994 return err;
1995}
1996
1997static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
1998 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 1999{
68f71708
SF		 2000 const u8 tso_ipid_split_en = 0;
2001 const u8 ig_vlan_strip_en = 1;
383ab92f 2002 int err;
68f71708 2003
717258ba
VK		 2004 /* Enable VLAN tag stripping.
2005 */
68f71708 2006
8e091340 2007 spin_lock_bh(&enic->devcmd_lock);
383ab92f 2008 err = enic_set_nic_cfg(enic,
68f71708
SF		 2009 rss_default_cpu, rss_hash_type,
2010 rss_hash_bits, rss_base_cpu,
2011 rss_enable, tso_ipid_split_en,
2012 ig_vlan_strip_en);
8e091340 2013 spin_unlock_bh(&enic->devcmd_lock);
383ab92f
VK		 2014
2015 return err;
2016}
2017
717258ba
VK		 2018static int enic_set_rss_nic_cfg(struct enic *enic)
2019{
2020 struct device *dev = enic_get_dev(enic);
2021 const u8 rss_default_cpu = 0;
2022 const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
2023 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
2024 NIC_CFG_RSS_HASH_TYPE_IPV6 |
2025 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
2026 const u8 rss_hash_bits = 7;
2027 const u8 rss_base_cpu = 0;
2028 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
2029
2030 if (rss_enable) {
2031 if (!enic_set_rsskey(enic)) {
2032 if (enic_set_rsscpu(enic, rss_hash_bits)) {
2033 rss_enable = 0;
2034 dev_warn(dev, "RSS disabled, "
2035 "Failed to set RSS cpu indirection table.");
2036 }
2037 } else {
2038 rss_enable = 0;
2039 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
2040 }
2041 }
2042
2043 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
2044 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK		 2045}
2046
01f2e4ea
SF		 2047static void enic_reset(struct work_struct *work)
2048{
2049 struct enic *enic = container_of(work, struct enic, reset);
2050
2051 if (!netif_running(enic->netdev))
2052 return;
2053
2054 rtnl_lock();
2055
0b038566 2056 spin_lock(&enic->enic_api_lock);
383ab92f 2057 enic_dev_hang_notify(enic);
01f2e4ea 2058 enic_stop(enic->netdev);
99ef5639 2059 enic_dev_hang_reset(enic);
e0afe53f 2060 enic_reset_addr_lists(enic);
01f2e4ea 2061 enic_init_vnic_resources(enic);
717258ba 2062 enic_set_rss_nic_cfg(enic);
f8cac14a 2063 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 2064 enic_open(enic->netdev);
0b038566 2065 spin_unlock(&enic->enic_api_lock);
d765bb41 2066 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF		 2067
2068 rtnl_unlock();
2069}
2070
2071static int enic_set_intr_mode(struct enic *enic)
2072{
717258ba 2073 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 2074 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF		 2075 unsigned int i;
2076
2077 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 2078 * on system capabilities.
01f2e4ea
SF		 2079 *
2080 * Try MSI-X first
2081 *
2082 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
2083 * (the second to last INTR is used for WQ/RQ errors)
2084 * (the last INTR is used for notifications)
2085 */
2086
2087 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
2088 for (i = 0; i < n + m + 2; i++)
2089 enic->msix_entry[i].entry = i;
2090
717258ba
VK		 2091 /* Use multiple RQs if RSS is enabled
2092 */
2093
2094 if (ENIC_SETTING(enic, RSS) &&
2095 enic->config.intr_mode < 1 &&
01f2e4ea
SF		 2096 enic->rq_count >= n &&
2097 enic->wq_count >= m &&
2098 enic->cq_count >= n + m &&
717258ba 2099 enic->intr_count >= n + m + 2) {
01f2e4ea 2100
abbb6a37
AG		 2101 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2102 n + m + 2, n + m + 2) > 0) {
01f2e4ea 2103
717258ba
VK		 2104 enic->rq_count = n;
2105 enic->wq_count = m;
2106 enic->cq_count = n + m;
2107 enic->intr_count = n + m + 2;
01f2e4ea 2108
717258ba
VK		 2109 vnic_dev_set_intr_mode(enic->vdev,
2110 VNIC_DEV_INTR_MODE_MSIX);
2111
2112 return 0;
2113 }
2114 }
2115
2116 if (enic->config.intr_mode < 1 &&
2117 enic->rq_count >= 1 &&
2118 enic->wq_count >= m &&
2119 enic->cq_count >= 1 + m &&
2120 enic->intr_count >= 1 + m + 2) {
abbb6a37
AG		 2121 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2122 1 + m + 2, 1 + m + 2) > 0) {
717258ba
VK		 2123
2124 enic->rq_count = 1;
2125 enic->wq_count = m;
2126 enic->cq_count = 1 + m;
2127 enic->intr_count = 1 + m + 2;
2128
2129 vnic_dev_set_intr_mode(enic->vdev,
2130 VNIC_DEV_INTR_MODE_MSIX);
2131
2132 return 0;
2133 }
01f2e4ea
SF		 2134 }
2135
2136 /* Next try MSI
2137 *
2138 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
2139 */
2140
2141 if (enic->config.intr_mode < 2 &&
2142 enic->rq_count >= 1 &&
2143 enic->wq_count >= 1 &&
2144 enic->cq_count >= 2 &&
2145 enic->intr_count >= 1 &&
2146 !pci_enable_msi(enic->pdev)) {
2147
2148 enic->rq_count = 1;
2149 enic->wq_count = 1;
2150 enic->cq_count = 2;
2151 enic->intr_count = 1;
2152
2153 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
2154
2155 return 0;
2156 }
2157
2158 /* Next try INTx
2159 *
2160 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
2161 * (the first INTR is used for WQ/RQ)
2162 * (the second INTR is used for WQ/RQ errors)
2163 * (the last INTR is used for notifications)
2164 */
2165
2166 if (enic->config.intr_mode < 3 &&
2167 enic->rq_count >= 1 &&
2168 enic->wq_count >= 1 &&
2169 enic->cq_count >= 2 &&
2170 enic->intr_count >= 3) {
2171
2172 enic->rq_count = 1;
2173 enic->wq_count = 1;
2174 enic->cq_count = 2;
2175 enic->intr_count = 3;
2176
2177 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
2178
2179 return 0;
2180 }
2181
2182 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2183
2184 return -EINVAL;
2185}
2186
2187static void enic_clear_intr_mode(struct enic *enic)
2188{
2189 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2190 case VNIC_DEV_INTR_MODE_MSIX:
2191 pci_disable_msix(enic->pdev);
2192 break;
2193 case VNIC_DEV_INTR_MODE_MSI:
2194 pci_disable_msi(enic->pdev);
2195 break;
2196 default:
2197 break;
2198 }
2199
2200 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2201}
2202
f8bd9091
SF		 2203static const struct net_device_ops enic_netdev_dynamic_ops = {
2204 .ndo_open = enic_open,
2205 .ndo_stop = enic_stop,
2206 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2207 .ndo_get_stats64 = enic_get_stats,
f8bd9091 2208 .ndo_validate_addr = eth_validate_addr,
319d7e84 2209 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF		 2210 .ndo_set_mac_address = enic_set_mac_address_dynamic,
2211 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF		 2212 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2213 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2214 .ndo_tx_timeout = enic_tx_timeout,
2215 .ndo_set_vf_port = enic_set_vf_port,
2216 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 2217 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF		 2218#ifdef CONFIG_NET_POLL_CONTROLLER
2219 .ndo_poll_controller = enic_poll_controller,
2220#endif
a145df23
GV		 2221#ifdef CONFIG_RFS_ACCEL
2222 .ndo_rx_flow_steer = enic_rx_flow_steer,
2223#endif
14747cd9
GV		 2224#ifdef CONFIG_NET_RX_BUSY_POLL
2225 .ndo_busy_poll = enic_busy_poll,
2226#endif
f8bd9091
SF		 2227};
2228
afe29f7a
SH		 2229static const struct net_device_ops enic_netdev_ops = {
2230 .ndo_open = enic_open,
2231 .ndo_stop = enic_stop,
00829823 2232 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2233 .ndo_get_stats64 = enic_get_stats,
afe29f7a 2234 .ndo_validate_addr = eth_validate_addr,
f8bd9091 2235 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 2236 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 2237 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH		 2238 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2239 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2240 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP		 2241 .ndo_set_vf_port = enic_set_vf_port,
2242 .ndo_get_vf_port = enic_get_vf_port,
2243 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH		 2244#ifdef CONFIG_NET_POLL_CONTROLLER
2245 .ndo_poll_controller = enic_poll_controller,
2246#endif
a145df23
GV		 2247#ifdef CONFIG_RFS_ACCEL
2248 .ndo_rx_flow_steer = enic_rx_flow_steer,
2249#endif
14747cd9
GV		 2250#ifdef CONFIG_NET_RX_BUSY_POLL
2251 .ndo_busy_poll = enic_busy_poll,
2252#endif
afe29f7a
SH		 2253};
2254
2fdba388 2255static void enic_dev_deinit(struct enic *enic)
6fdfa970 2256{
717258ba
VK		 2257 unsigned int i;
2258
14747cd9
GV		 2259 for (i = 0; i < enic->rq_count; i++) {
2260 napi_hash_del(&enic->napi[i]);
717258ba 2261 netif_napi_del(&enic->napi[i]);
14747cd9 2262 }
4cfe8785
GV		 2263 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2264 for (i = 0; i < enic->wq_count; i++)
2265 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
717258ba 2266
6fdfa970
SF		 2267 enic_free_vnic_resources(enic);
2268 enic_clear_intr_mode(enic);
2269}
2270
3f255dcc
GV		 2271static void enic_kdump_kernel_config(struct enic *enic)
2272{
2273 if (is_kdump_kernel()) {
2274 dev_info(enic_get_dev(enic), "Running from within kdump kernel. Using minimal resources\n");
2275 enic->rq_count = 1;
2276 enic->wq_count = 1;
2277 enic->config.rq_desc_count = ENIC_MIN_RQ_DESCS;
2278 enic->config.wq_desc_count = ENIC_MIN_WQ_DESCS;
2279 enic->config.mtu = min_t(u16, 1500, enic->config.mtu);
2280 }
2281}
2282
2fdba388 2283static int enic_dev_init(struct enic *enic)
6fdfa970 2284{
a7a79deb 2285 struct device *dev = enic_get_dev(enic);
6fdfa970 2286 struct net_device *netdev = enic->netdev;
717258ba 2287 unsigned int i;
6fdfa970
SF		 2288 int err;
2289
ea7ea65a
VK		 2290 /* Get interrupt coalesce timer info */
2291 err = enic_dev_intr_coal_timer_info(enic);
2292 if (err) {
2293 dev_warn(dev, "Using default conversion factor for "
2294 "interrupt coalesce timer\n");
2295 vnic_dev_intr_coal_timer_info_default(enic->vdev);
2296 }
2297
6fdfa970
SF		 2298 /* Get vNIC configuration
2299 */
2300
2301 err = enic_get_vnic_config(enic);
2302 if (err) {
a7a79deb 2303 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF		 2304 return err;
2305 }
2306
2307 /* Get available resource counts
2308 */
2309
2310 enic_get_res_counts(enic);
2311
3f255dcc
GV		 2312 /* modify resource count if we are in kdump_kernel
2313 */
2314 enic_kdump_kernel_config(enic);
2315
6fdfa970
SF		 2316 /* Set interrupt mode based on resource counts and system
2317 * capabilities
2318 */
2319
2320 err = enic_set_intr_mode(enic);
2321 if (err) {
a7a79deb
VK		 2322 dev_err(dev, "Failed to set intr mode based on resource "
2323 "counts and system capabilities, aborting\n");
6fdfa970
SF		 2324 return err;
2325 }
2326
2327 /* Allocate and configure vNIC resources
2328 */
2329
2330 err = enic_alloc_vnic_resources(enic);
2331 if (err) {
a7a79deb 2332 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF		 2333 goto err_out_free_vnic_resources;
2334 }
2335
2336 enic_init_vnic_resources(enic);
2337
717258ba 2338 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2339 if (err) {
a7a79deb 2340 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF		 2341 goto err_out_free_vnic_resources;
2342 }
2343
2344 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2345 default:
717258ba 2346 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
14747cd9 2347 napi_hash_add(&enic->napi[0]);
6fdfa970
SF		 2348 break;
2349 case VNIC_DEV_INTR_MODE_MSIX:
14747cd9 2350 for (i = 0; i < enic->rq_count; i++) {
717258ba 2351 netif_napi_add(netdev, &enic->napi[i],
4cfe8785 2352 enic_poll_msix_rq, NAPI_POLL_WEIGHT);
14747cd9
GV		 2353 napi_hash_add(&enic->napi[i]);
2354 }
4cfe8785
GV		 2355 for (i = 0; i < enic->wq_count; i++)
2356 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
2357 enic_poll_msix_wq, NAPI_POLL_WEIGHT);
6fdfa970
SF		 2358 break;
2359 }
2360
2361 return 0;
2362
2363err_out_free_vnic_resources:
2364 enic_clear_intr_mode(enic);
2365 enic_free_vnic_resources(enic);
2366
2367 return err;
2368}
2369
27e6c7d3
SF		 2370static void enic_iounmap(struct enic *enic)
2371{
2372 unsigned int i;
2373
2374 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2375 if (enic->bar[i].vaddr)
2376 iounmap(enic->bar[i].vaddr);
2377}
2378
1dd06ae8 2379static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2380{
a7a79deb 2381 struct device *dev = &pdev->dev;
01f2e4ea
SF		 2382 struct net_device *netdev;
2383 struct enic *enic;
2384 int using_dac = 0;
2385 unsigned int i;
2386 int err;
8749b427
RP		 2387#ifdef CONFIG_PCI_IOV
2388 int pos = 0;
2389#endif
b67f231d 2390 int num_pps = 1;
01f2e4ea 2391
01f2e4ea
SF		 2392 /* Allocate net device structure and initialize. Private
2393 * instance data is initialized to zero.
2394 */
2395
822473b6 2396 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2397 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2398 if (!netdev)
01f2e4ea 2399 return -ENOMEM;
01f2e4ea 2400
01f2e4ea
SF		 2401 pci_set_drvdata(pdev, netdev);
2402
2403 SET_NETDEV_DEV(netdev, &pdev->dev);
2404
2405 enic = netdev_priv(netdev);
2406 enic->netdev = netdev;
2407 enic->pdev = pdev;
2408
2409 /* Setup PCI resources
2410 */
2411
29046f9b 2412 err = pci_enable_device_mem(pdev);
01f2e4ea 2413 if (err) {
a7a79deb 2414 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF		 2415 goto err_out_free_netdev;
2416 }
2417
2418 err = pci_request_regions(pdev, DRV_NAME);
2419 if (err) {
a7a79deb 2420 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF		 2421 goto err_out_disable_device;
2422 }
2423
2424 pci_set_master(pdev);
2425
2426 /* Query PCI controller on system for DMA addressing
624dbf55 2427 * limitation for the device. Try 64-bit first, and
01f2e4ea
SF		 2428 * fail to 32-bit.
2429 */
2430
624dbf55 2431 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2432 if (err) {
284901a9 2433 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2434 if (err) {
a7a79deb 2435 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF		 2436 goto err_out_release_regions;
2437 }
284901a9 2438 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2439 if (err) {
a7a79deb
VK		 2440 dev_err(dev, "Unable to obtain %u-bit DMA "
2441 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF		 2442 goto err_out_release_regions;
2443 }
2444 } else {
624dbf55 2445 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2446 if (err) {
a7a79deb 2447 dev_err(dev, "Unable to obtain %u-bit DMA "
624dbf55 2448 "for consistent allocations, aborting\n", 64);
01f2e4ea
SF		 2449 goto err_out_release_regions;
2450 }
2451 using_dac = 1;
2452 }
2453
27e6c7d3 2454 /* Map vNIC resources from BAR0-5
01f2e4ea
SF		 2455 */
2456
27e6c7d3
SF		 2457 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2458 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2459 continue;
2460 enic->bar[i].len = pci_resource_len(pdev, i);
2461 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2462 if (!enic->bar[i].vaddr) {
a7a79deb 2463 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF		 2464 err = -ENODEV;
2465 goto err_out_iounmap;
2466 }
2467 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF		 2468 }
2469
2470 /* Register vNIC device
2471 */
2472
27e6c7d3
SF		 2473 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2474 ARRAY_SIZE(enic->bar));
01f2e4ea 2475 if (!enic->vdev) {
a7a79deb 2476 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF		 2477 err = -ENODEV;
2478 goto err_out_iounmap;
2479 }
2480
8749b427
RP		 2481#ifdef CONFIG_PCI_IOV
2482 /* Get number of subvnics */
2483 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2484 if (pos) {
2485 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2486 &enic->num_vfs);
8749b427
RP		 2487 if (enic->num_vfs) {
2488 err = pci_enable_sriov(pdev, enic->num_vfs);
2489 if (err) {
2490 dev_err(dev, "SRIOV enable failed, aborting."
2491 " pci_enable_sriov() returned %d\n",
2492 err);
2493 goto err_out_vnic_unregister;
2494 }
2495 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2496 num_pps = enic->num_vfs;
8749b427
RP		 2497 }
2498 }
8749b427 2499#endif
ca2b721d 2500
3f192795 2501 /* Allocate structure for port profiles */
a1de2219 2502 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2503 if (!enic->pp) {
3f192795 2504 err = -ENOMEM;
ca2b721d 2505 goto err_out_disable_sriov_pp;
3f192795
RP		 2506 }
2507
01f2e4ea
SF		 2508 /* Issue device open to get device in known state
2509 */
2510
2511 err = enic_dev_open(enic);
2512 if (err) {
a7a79deb 2513 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2514 goto err_out_disable_sriov;
01f2e4ea
SF		 2515 }
2516
69161425
VK		 2517 /* Setup devcmd lock
2518 */
2519
2520 spin_lock_init(&enic->devcmd_lock);
0b038566 2521 spin_lock_init(&enic->enic_api_lock);
69161425
VK		 2522
2523 /*
2524 * Set ingress vlan rewrite mode before vnic initialization
2525 */
2526
2527 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2528 if (err) {
2529 dev_err(dev,
2530 "Failed to set ingress vlan rewrite mode, aborting.\n");
2531 goto err_out_dev_close;
2532 }
2533
01f2e4ea
SF		 2534 /* Issue device init to initialize the vnic-to-switch link.
2535 * We'll start with carrier off and wait for link UP
2536 * notification later to turn on carrier. We don't need
2537 * to wait here for the vnic-to-switch link initialization
2538 * to complete; link UP notification is the indication that
2539 * the process is complete.
2540 */
2541
2542 netif_carrier_off(netdev);
2543
a7a79deb
VK		 2544 /* Do not call dev_init for a dynamic vnic.
2545 * For a dynamic vnic, init_prov_info will be
2546 * called later by an upper layer.
2547 */
2548
2b68c181 2549 if (!enic_is_dynamic(enic)) {
f8bd9091
SF		 2550 err = vnic_dev_init(enic->vdev, 0);
2551 if (err) {
a7a79deb 2552 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF		 2553 goto err_out_dev_close;
2554 }
01f2e4ea
SF		 2555 }
2556
6fdfa970 2557 err = enic_dev_init(enic);
01f2e4ea 2558 if (err) {
a7a79deb 2559 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF		 2560 goto err_out_dev_close;
2561 }
2562
822473b6 2563 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2564 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2565
383ab92f 2566 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF		 2567 */
2568
2569 init_timer(&enic->notify_timer);
2570 enic->notify_timer.function = enic_notify_timer;
2571 enic->notify_timer.data = (unsigned long)enic;
2572
7c2ce6e6 2573 enic_set_rx_coal_setting(enic);
01f2e4ea 2574 INIT_WORK(&enic->reset, enic_reset);
c97c894d 2575 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF		 2576
2577 for (i = 0; i < enic->wq_count; i++)
2578 spin_lock_init(&enic->wq_lock[i]);
2579
01f2e4ea
SF		 2580 /* Register net device
2581 */
2582
2583 enic->port_mtu = enic->config.mtu;
2584 (void)enic_change_mtu(netdev, enic->port_mtu);
2585
2586 err = enic_set_mac_addr(netdev, enic->mac_addr);
2587 if (err) {
a7a79deb 2588 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2589 goto err_out_dev_deinit;
01f2e4ea
SF		 2590 }
2591
7c844599 2592 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
7c2ce6e6
SS		 2593 /* rx coalesce time already got initialized. This gets used
2594 * if adaptive coal is turned off
2595 */
7c844599
SF		 2596 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2597
7335903c 2598 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF		 2599 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2600 else
2601 netdev->netdev_ops = &enic_netdev_ops;
2602
01f2e4ea 2603 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2604 enic_set_ethtool_ops(netdev);
01f2e4ea 2605
f646968f 2606 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2607 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2608 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK		 2609 enic->loop_enable = 1;
2610 enic->loop_tag = enic->config.loop_tag;
2611 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2612 }
01f2e4ea 2613 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2614 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2615 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2616 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2617 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2618 if (ENIC_SETTING(enic, RSS))
2619 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM		 2620 if (ENIC_SETTING(enic, RXCSUM))
2621 netdev->hw_features |= NETIF_F_RXCSUM;
2622
2623 netdev->features |= netdev->hw_features;
2624
a145df23
GV		 2625#ifdef CONFIG_RFS_ACCEL
2626 netdev->hw_features |= NETIF_F_NTUPLE;
2627#endif
2628
01f2e4ea
SF		 2629 if (using_dac)
2630 netdev->features |= NETIF_F_HIGHDMA;
2631
01789349
JP		 2632 netdev->priv_flags |= IFF_UNICAST_FLT;
2633
01f2e4ea
SF		 2634 err = register_netdev(netdev);
2635 if (err) {
a7a79deb 2636 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 2637 goto err_out_dev_deinit;
01f2e4ea 2638 }
a03bb56e 2639 enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
01f2e4ea
SF		 2640
2641 return 0;
2642
6fdfa970
SF		 2643err_out_dev_deinit:
2644 enic_dev_deinit(enic);
01f2e4ea
SF		 2645err_out_dev_close:
2646 vnic_dev_close(enic->vdev);
8749b427 2647err_out_disable_sriov:
ca2b721d
RP		 2648 kfree(enic->pp);
2649err_out_disable_sriov_pp:
8749b427
RP		 2650#ifdef CONFIG_PCI_IOV
2651 if (enic_sriov_enabled(enic)) {
2652 pci_disable_sriov(pdev);
2653 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2654 }
01f2e4ea 2655err_out_vnic_unregister:
8749b427 2656#endif
35d87e33 2657 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF		 2658err_out_iounmap:
2659 enic_iounmap(enic);
2660err_out_release_regions:
2661 pci_release_regions(pdev);
2662err_out_disable_device:
2663 pci_disable_device(pdev);
2664err_out_free_netdev:
01f2e4ea
SF		 2665 free_netdev(netdev);
2666
2667 return err;
2668}
2669
854de92f 2670static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF		 2671{
2672 struct net_device *netdev = pci_get_drvdata(pdev);
2673
2674 if (netdev) {
2675 struct enic *enic = netdev_priv(netdev);
2676
23f333a2 2677 cancel_work_sync(&enic->reset);
c97c894d 2678 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 2679 unregister_netdev(netdev);
6fdfa970 2680 enic_dev_deinit(enic);
01f2e4ea 2681 vnic_dev_close(enic->vdev);
8749b427
RP		 2682#ifdef CONFIG_PCI_IOV
2683 if (enic_sriov_enabled(enic)) {
2684 pci_disable_sriov(pdev);
2685 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2686 }
2687#endif
3f192795 2688 kfree(enic->pp);
01f2e4ea
SF		 2689 vnic_dev_unregister(enic->vdev);
2690 enic_iounmap(enic);
2691 pci_release_regions(pdev);
2692 pci_disable_device(pdev);
01f2e4ea
SF		 2693 free_netdev(netdev);
2694 }
2695}
2696
2697static struct pci_driver enic_driver = {
2698 .name = DRV_NAME,
2699 .id_table = enic_id_table,
2700 .probe = enic_probe,
854de92f 2701 .remove = enic_remove,
01f2e4ea
SF		 2702};
2703
2704static int __init enic_init_module(void)
2705{
a7a79deb 2706 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
01f2e4ea
SF		 2707
2708 return pci_register_driver(&enic_driver);
2709}
2710
2711static void __exit enic_cleanup_module(void)
2712{
2713 pci_unregister_driver(&enic_driver);
2714}
2715
2716module_init(enic_init_module);
2717module_exit(enic_cleanup_module);
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