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01f2e4ea | 1 | /* |
29046f9b | 2 | * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. |
01f2e4ea SF |
3 | * Copyright 2007 Nuova Systems, Inc. All rights reserved. |
4 | * | |
5 | * This program is free software; you may redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
10 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
11 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
12 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
13 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
15 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
16 | * SOFTWARE. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/string.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/init.h> | |
a6b7a407 | 26 | #include <linux/interrupt.h> |
01f2e4ea SF |
27 | #include <linux/workqueue.h> |
28 | #include <linux/pci.h> | |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/etherdevice.h> | |
01789349 | 31 | #include <linux/if.h> |
01f2e4ea SF |
32 | #include <linux/if_ether.h> |
33 | #include <linux/if_vlan.h> | |
01f2e4ea SF |
34 | #include <linux/in.h> |
35 | #include <linux/ip.h> | |
36 | #include <linux/ipv6.h> | |
37 | #include <linux/tcp.h> | |
29046f9b | 38 | #include <linux/rtnetlink.h> |
70c71606 | 39 | #include <linux/prefetch.h> |
b7c6bfb7 | 40 | #include <net/ip6_checksum.h> |
7c2ce6e6 | 41 | #include <linux/ktime.h> |
b6e97c13 GV |
42 | #ifdef CONFIG_RFS_ACCEL |
43 | #include <linux/cpu_rmap.h> | |
44 | #endif | |
14747cd9 GV |
45 | #ifdef CONFIG_NET_RX_BUSY_POLL |
46 | #include <net/busy_poll.h> | |
47 | #endif | |
3f255dcc | 48 | #include <linux/crash_dump.h> |
01f2e4ea SF |
49 | |
50 | #include "cq_enet_desc.h" | |
51 | #include "vnic_dev.h" | |
52 | #include "vnic_intr.h" | |
53 | #include "vnic_stats.h" | |
f8bd9091 | 54 | #include "vnic_vic.h" |
01f2e4ea SF |
55 | #include "enic_res.h" |
56 | #include "enic.h" | |
51987461 | 57 | #include "enic_dev.h" |
b3abfbd2 | 58 | #include "enic_pp.h" |
a145df23 | 59 | #include "enic_clsf.h" |
01f2e4ea SF |
60 | |
61 | #define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ) | |
ea0d7d91 SF |
62 | #define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS) |
63 | #define MAX_TSO (1 << 16) | |
64 | #define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1) | |
65 | ||
66 | #define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */ | |
f8bd9091 | 67 | #define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */ |
3a4adef5 | 68 | #define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */ |
01f2e4ea | 69 | |
a03bb56e GV |
70 | #define RX_COPYBREAK_DEFAULT 256 |
71 | ||
01f2e4ea | 72 | /* Supported devices */ |
9baa3c34 | 73 | static const struct pci_device_id enic_id_table[] = { |
ea0d7d91 | 74 | { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) }, |
f8bd9091 | 75 | { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) }, |
3a4adef5 | 76 | { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) }, |
01f2e4ea SF |
77 | { 0, } /* end of table */ |
78 | }; | |
79 | ||
80 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
81 | MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>"); | |
82 | MODULE_LICENSE("GPL"); | |
83 | MODULE_VERSION(DRV_VERSION); | |
84 | MODULE_DEVICE_TABLE(pci, enic_id_table); | |
85 | ||
7c2ce6e6 SS |
86 | #define ENIC_LARGE_PKT_THRESHOLD 1000 |
87 | #define ENIC_MAX_COALESCE_TIMERS 10 | |
88 | /* Interrupt moderation table, which will be used to decide the | |
89 | * coalescing timer values | |
90 | * {rx_rate in Mbps, mapping percentage of the range} | |
91 | */ | |
57ae84a0 | 92 | static struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = { |
7c2ce6e6 SS |
93 | {4000, 0}, |
94 | {4400, 10}, | |
95 | {5060, 20}, | |
96 | {5230, 30}, | |
97 | {5540, 40}, | |
98 | {5820, 50}, | |
99 | {6120, 60}, | |
100 | {6435, 70}, | |
101 | {6745, 80}, | |
102 | {7000, 90}, | |
103 | {0xFFFFFFFF, 100} | |
104 | }; | |
105 | ||
106 | /* This table helps the driver to pick different ranges for rx coalescing | |
107 | * timer depending on the link speed. | |
108 | */ | |
57ae84a0 | 109 | static struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = { |
7c2ce6e6 SS |
110 | {0, 0}, /* 0 - 4 Gbps */ |
111 | {0, 3}, /* 4 - 10 Gbps */ | |
112 | {3, 6}, /* 10 - 40 Gbps */ | |
113 | }; | |
114 | ||
3f192795 | 115 | int enic_is_dynamic(struct enic *enic) |
f8bd9091 SF |
116 | { |
117 | return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN; | |
118 | } | |
119 | ||
8749b427 RP |
120 | int enic_sriov_enabled(struct enic *enic) |
121 | { | |
122 | return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0; | |
123 | } | |
124 | ||
3a4adef5 RP |
125 | static int enic_is_sriov_vf(struct enic *enic) |
126 | { | |
127 | return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF; | |
128 | } | |
129 | ||
889d13f5 RP |
130 | int enic_is_valid_vf(struct enic *enic, int vf) |
131 | { | |
132 | #ifdef CONFIG_PCI_IOV | |
133 | return vf >= 0 && vf < enic->num_vfs; | |
134 | #else | |
135 | return 0; | |
136 | #endif | |
137 | } | |
138 | ||
01f2e4ea SF |
139 | static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf) |
140 | { | |
141 | struct enic *enic = vnic_dev_priv(wq->vdev); | |
142 | ||
143 | if (buf->sop) | |
144 | pci_unmap_single(enic->pdev, buf->dma_addr, | |
145 | buf->len, PCI_DMA_TODEVICE); | |
146 | else | |
147 | pci_unmap_page(enic->pdev, buf->dma_addr, | |
148 | buf->len, PCI_DMA_TODEVICE); | |
149 | ||
150 | if (buf->os_buf) | |
151 | dev_kfree_skb_any(buf->os_buf); | |
152 | } | |
153 | ||
154 | static void enic_wq_free_buf(struct vnic_wq *wq, | |
155 | struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque) | |
156 | { | |
157 | enic_free_wq_buf(wq, buf); | |
158 | } | |
159 | ||
160 | static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc, | |
161 | u8 type, u16 q_number, u16 completed_index, void *opaque) | |
162 | { | |
163 | struct enic *enic = vnic_dev_priv(vdev); | |
164 | ||
165 | spin_lock(&enic->wq_lock[q_number]); | |
166 | ||
167 | vnic_wq_service(&enic->wq[q_number], cq_desc, | |
168 | completed_index, enic_wq_free_buf, | |
169 | opaque); | |
170 | ||
822473b6 | 171 | if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) && |
ea0d7d91 SF |
172 | vnic_wq_desc_avail(&enic->wq[q_number]) >= |
173 | (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)) | |
822473b6 | 174 | netif_wake_subqueue(enic->netdev, q_number); |
01f2e4ea SF |
175 | |
176 | spin_unlock(&enic->wq_lock[q_number]); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static void enic_log_q_error(struct enic *enic) | |
182 | { | |
183 | unsigned int i; | |
184 | u32 error_status; | |
185 | ||
186 | for (i = 0; i < enic->wq_count; i++) { | |
187 | error_status = vnic_wq_error_status(&enic->wq[i]); | |
188 | if (error_status) | |
a7a79deb VK |
189 | netdev_err(enic->netdev, "WQ[%d] error_status %d\n", |
190 | i, error_status); | |
01f2e4ea SF |
191 | } |
192 | ||
193 | for (i = 0; i < enic->rq_count; i++) { | |
194 | error_status = vnic_rq_error_status(&enic->rq[i]); | |
195 | if (error_status) | |
a7a79deb VK |
196 | netdev_err(enic->netdev, "RQ[%d] error_status %d\n", |
197 | i, error_status); | |
01f2e4ea SF |
198 | } |
199 | } | |
200 | ||
383ab92f | 201 | static void enic_msglvl_check(struct enic *enic) |
01f2e4ea | 202 | { |
383ab92f | 203 | u32 msg_enable = vnic_dev_msg_lvl(enic->vdev); |
01f2e4ea | 204 | |
383ab92f | 205 | if (msg_enable != enic->msg_enable) { |
a7a79deb VK |
206 | netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n", |
207 | enic->msg_enable, msg_enable); | |
383ab92f | 208 | enic->msg_enable = msg_enable; |
01f2e4ea SF |
209 | } |
210 | } | |
211 | ||
212 | static void enic_mtu_check(struct enic *enic) | |
213 | { | |
214 | u32 mtu = vnic_dev_mtu(enic->vdev); | |
a7a79deb | 215 | struct net_device *netdev = enic->netdev; |
01f2e4ea | 216 | |
491598a4 | 217 | if (mtu && mtu != enic->port_mtu) { |
7c844599 | 218 | enic->port_mtu = mtu; |
7335903c | 219 | if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) { |
c97c894d RP |
220 | mtu = max_t(int, ENIC_MIN_MTU, |
221 | min_t(int, ENIC_MAX_MTU, mtu)); | |
222 | if (mtu != netdev->mtu) | |
223 | schedule_work(&enic->change_mtu_work); | |
224 | } else { | |
225 | if (mtu < netdev->mtu) | |
226 | netdev_warn(netdev, | |
227 | "interface MTU (%d) set higher " | |
228 | "than switch port MTU (%d)\n", | |
229 | netdev->mtu, mtu); | |
230 | } | |
01f2e4ea SF |
231 | } |
232 | } | |
233 | ||
383ab92f | 234 | static void enic_link_check(struct enic *enic) |
01f2e4ea | 235 | { |
383ab92f VK |
236 | int link_status = vnic_dev_link_status(enic->vdev); |
237 | int carrier_ok = netif_carrier_ok(enic->netdev); | |
01f2e4ea | 238 | |
383ab92f | 239 | if (link_status && !carrier_ok) { |
a7a79deb | 240 | netdev_info(enic->netdev, "Link UP\n"); |
383ab92f VK |
241 | netif_carrier_on(enic->netdev); |
242 | } else if (!link_status && carrier_ok) { | |
a7a79deb | 243 | netdev_info(enic->netdev, "Link DOWN\n"); |
383ab92f | 244 | netif_carrier_off(enic->netdev); |
01f2e4ea SF |
245 | } |
246 | } | |
247 | ||
248 | static void enic_notify_check(struct enic *enic) | |
249 | { | |
250 | enic_msglvl_check(enic); | |
251 | enic_mtu_check(enic); | |
252 | enic_link_check(enic); | |
253 | } | |
254 | ||
255 | #define ENIC_TEST_INTR(pba, i) (pba & (1 << i)) | |
256 | ||
257 | static irqreturn_t enic_isr_legacy(int irq, void *data) | |
258 | { | |
259 | struct net_device *netdev = data; | |
260 | struct enic *enic = netdev_priv(netdev); | |
717258ba VK |
261 | unsigned int io_intr = enic_legacy_io_intr(); |
262 | unsigned int err_intr = enic_legacy_err_intr(); | |
263 | unsigned int notify_intr = enic_legacy_notify_intr(); | |
01f2e4ea SF |
264 | u32 pba; |
265 | ||
717258ba | 266 | vnic_intr_mask(&enic->intr[io_intr]); |
01f2e4ea SF |
267 | |
268 | pba = vnic_intr_legacy_pba(enic->legacy_pba); | |
269 | if (!pba) { | |
717258ba | 270 | vnic_intr_unmask(&enic->intr[io_intr]); |
01f2e4ea SF |
271 | return IRQ_NONE; /* not our interrupt */ |
272 | } | |
273 | ||
717258ba | 274 | if (ENIC_TEST_INTR(pba, notify_intr)) { |
01f2e4ea | 275 | enic_notify_check(enic); |
2b0c2e2d | 276 | vnic_intr_return_all_credits(&enic->intr[notify_intr]); |
ed8af6b2 | 277 | } |
01f2e4ea | 278 | |
717258ba VK |
279 | if (ENIC_TEST_INTR(pba, err_intr)) { |
280 | vnic_intr_return_all_credits(&enic->intr[err_intr]); | |
01f2e4ea SF |
281 | enic_log_q_error(enic); |
282 | /* schedule recovery from WQ/RQ error */ | |
283 | schedule_work(&enic->reset); | |
284 | return IRQ_HANDLED; | |
285 | } | |
286 | ||
db40b3f5 GV |
287 | if (ENIC_TEST_INTR(pba, io_intr)) |
288 | napi_schedule_irqoff(&enic->napi[0]); | |
289 | else | |
717258ba | 290 | vnic_intr_unmask(&enic->intr[io_intr]); |
01f2e4ea SF |
291 | |
292 | return IRQ_HANDLED; | |
293 | } | |
294 | ||
295 | static irqreturn_t enic_isr_msi(int irq, void *data) | |
296 | { | |
297 | struct enic *enic = data; | |
298 | ||
299 | /* With MSI, there is no sharing of interrupts, so this is | |
300 | * our interrupt and there is no need to ack it. The device | |
301 | * is not providing per-vector masking, so the OS will not | |
302 | * write to PCI config space to mask/unmask the interrupt. | |
303 | * We're using mask_on_assertion for MSI, so the device | |
304 | * automatically masks the interrupt when the interrupt is | |
305 | * generated. Later, when exiting polling, the interrupt | |
306 | * will be unmasked (see enic_poll). | |
307 | * | |
308 | * Also, the device uses the same PCIe Traffic Class (TC) | |
309 | * for Memory Write data and MSI, so there are no ordering | |
310 | * issues; the MSI will always arrive at the Root Complex | |
311 | * _after_ corresponding Memory Writes (i.e. descriptor | |
312 | * writes). | |
313 | */ | |
314 | ||
db40b3f5 | 315 | napi_schedule_irqoff(&enic->napi[0]); |
01f2e4ea SF |
316 | |
317 | return IRQ_HANDLED; | |
318 | } | |
319 | ||
4cfe8785 | 320 | static irqreturn_t enic_isr_msix(int irq, void *data) |
01f2e4ea | 321 | { |
717258ba | 322 | struct napi_struct *napi = data; |
01f2e4ea | 323 | |
db40b3f5 | 324 | napi_schedule_irqoff(napi); |
01f2e4ea SF |
325 | |
326 | return IRQ_HANDLED; | |
327 | } | |
328 | ||
01f2e4ea SF |
329 | static irqreturn_t enic_isr_msix_err(int irq, void *data) |
330 | { | |
331 | struct enic *enic = data; | |
717258ba | 332 | unsigned int intr = enic_msix_err_intr(enic); |
01f2e4ea | 333 | |
717258ba | 334 | vnic_intr_return_all_credits(&enic->intr[intr]); |
ed8af6b2 | 335 | |
01f2e4ea SF |
336 | enic_log_q_error(enic); |
337 | ||
338 | /* schedule recovery from WQ/RQ error */ | |
339 | schedule_work(&enic->reset); | |
340 | ||
341 | return IRQ_HANDLED; | |
342 | } | |
343 | ||
344 | static irqreturn_t enic_isr_msix_notify(int irq, void *data) | |
345 | { | |
346 | struct enic *enic = data; | |
717258ba | 347 | unsigned int intr = enic_msix_notify_intr(enic); |
01f2e4ea SF |
348 | |
349 | enic_notify_check(enic); | |
2b0c2e2d | 350 | vnic_intr_return_all_credits(&enic->intr[intr]); |
01f2e4ea SF |
351 | |
352 | return IRQ_HANDLED; | |
353 | } | |
354 | ||
065df159 GV |
355 | static int enic_queue_wq_skb_cont(struct enic *enic, struct vnic_wq *wq, |
356 | struct sk_buff *skb, unsigned int len_left, | |
357 | int loopback) | |
01f2e4ea | 358 | { |
9e903e08 | 359 | const skb_frag_t *frag; |
065df159 | 360 | dma_addr_t dma_addr; |
01f2e4ea SF |
361 | |
362 | /* Queue additional data fragments */ | |
363 | for (frag = skb_shinfo(skb)->frags; len_left; frag++) { | |
9e903e08 | 364 | len_left -= skb_frag_size(frag); |
065df159 GV |
365 | dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 0, |
366 | skb_frag_size(frag), | |
367 | DMA_TO_DEVICE); | |
368 | if (unlikely(enic_dma_map_check(enic, dma_addr))) | |
369 | return -ENOMEM; | |
370 | enic_queue_wq_desc_cont(wq, skb, dma_addr, skb_frag_size(frag), | |
371 | (len_left == 0), /* EOP? */ | |
372 | loopback); | |
01f2e4ea | 373 | } |
065df159 GV |
374 | |
375 | return 0; | |
01f2e4ea SF |
376 | } |
377 | ||
065df159 GV |
378 | static int enic_queue_wq_skb_vlan(struct enic *enic, struct vnic_wq *wq, |
379 | struct sk_buff *skb, int vlan_tag_insert, | |
380 | unsigned int vlan_tag, int loopback) | |
01f2e4ea SF |
381 | { |
382 | unsigned int head_len = skb_headlen(skb); | |
383 | unsigned int len_left = skb->len - head_len; | |
384 | int eop = (len_left == 0); | |
065df159 GV |
385 | dma_addr_t dma_addr; |
386 | int err = 0; | |
387 | ||
388 | dma_addr = pci_map_single(enic->pdev, skb->data, head_len, | |
389 | PCI_DMA_TODEVICE); | |
390 | if (unlikely(enic_dma_map_check(enic, dma_addr))) | |
391 | return -ENOMEM; | |
01f2e4ea | 392 | |
ea0d7d91 SF |
393 | /* Queue the main skb fragment. The fragments are no larger |
394 | * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less | |
395 | * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor | |
396 | * per fragment is queued. | |
397 | */ | |
065df159 GV |
398 | enic_queue_wq_desc(wq, skb, dma_addr, head_len, vlan_tag_insert, |
399 | vlan_tag, eop, loopback); | |
01f2e4ea SF |
400 | |
401 | if (!eop) | |
065df159 GV |
402 | err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback); |
403 | ||
404 | return err; | |
01f2e4ea SF |
405 | } |
406 | ||
065df159 GV |
407 | static int enic_queue_wq_skb_csum_l4(struct enic *enic, struct vnic_wq *wq, |
408 | struct sk_buff *skb, int vlan_tag_insert, | |
409 | unsigned int vlan_tag, int loopback) | |
01f2e4ea SF |
410 | { |
411 | unsigned int head_len = skb_headlen(skb); | |
412 | unsigned int len_left = skb->len - head_len; | |
0d0b1672 | 413 | unsigned int hdr_len = skb_checksum_start_offset(skb); |
01f2e4ea SF |
414 | unsigned int csum_offset = hdr_len + skb->csum_offset; |
415 | int eop = (len_left == 0); | |
065df159 GV |
416 | dma_addr_t dma_addr; |
417 | int err = 0; | |
418 | ||
419 | dma_addr = pci_map_single(enic->pdev, skb->data, head_len, | |
420 | PCI_DMA_TODEVICE); | |
421 | if (unlikely(enic_dma_map_check(enic, dma_addr))) | |
422 | return -ENOMEM; | |
01f2e4ea | 423 | |
ea0d7d91 SF |
424 | /* Queue the main skb fragment. The fragments are no larger |
425 | * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less | |
426 | * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor | |
427 | * per fragment is queued. | |
428 | */ | |
065df159 GV |
429 | enic_queue_wq_desc_csum_l4(wq, skb, dma_addr, head_len, csum_offset, |
430 | hdr_len, vlan_tag_insert, vlan_tag, eop, | |
431 | loopback); | |
01f2e4ea SF |
432 | |
433 | if (!eop) | |
065df159 GV |
434 | err = enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback); |
435 | ||
436 | return err; | |
01f2e4ea SF |
437 | } |
438 | ||
065df159 GV |
439 | static int enic_queue_wq_skb_tso(struct enic *enic, struct vnic_wq *wq, |
440 | struct sk_buff *skb, unsigned int mss, | |
441 | int vlan_tag_insert, unsigned int vlan_tag, | |
442 | int loopback) | |
01f2e4ea | 443 | { |
ea0d7d91 SF |
444 | unsigned int frag_len_left = skb_headlen(skb); |
445 | unsigned int len_left = skb->len - frag_len_left; | |
01f2e4ea SF |
446 | unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
447 | int eop = (len_left == 0); | |
ea0d7d91 SF |
448 | unsigned int len; |
449 | dma_addr_t dma_addr; | |
450 | unsigned int offset = 0; | |
451 | skb_frag_t *frag; | |
01f2e4ea SF |
452 | |
453 | /* Preload TCP csum field with IP pseudo hdr calculated | |
454 | * with IP length set to zero. HW will later add in length | |
455 | * to each TCP segment resulting from the TSO. | |
456 | */ | |
457 | ||
09640e63 | 458 | if (skb->protocol == cpu_to_be16(ETH_P_IP)) { |
01f2e4ea SF |
459 | ip_hdr(skb)->check = 0; |
460 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr, | |
461 | ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); | |
09640e63 | 462 | } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { |
01f2e4ea SF |
463 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, |
464 | &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); | |
465 | } | |
466 | ||
ea0d7d91 SF |
467 | /* Queue WQ_ENET_MAX_DESC_LEN length descriptors |
468 | * for the main skb fragment | |
469 | */ | |
470 | while (frag_len_left) { | |
471 | len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN); | |
065df159 GV |
472 | dma_addr = pci_map_single(enic->pdev, skb->data + offset, len, |
473 | PCI_DMA_TODEVICE); | |
474 | if (unlikely(enic_dma_map_check(enic, dma_addr))) | |
475 | return -ENOMEM; | |
476 | enic_queue_wq_desc_tso(wq, skb, dma_addr, len, mss, hdr_len, | |
477 | vlan_tag_insert, vlan_tag, | |
478 | eop && (len == frag_len_left), loopback); | |
ea0d7d91 SF |
479 | frag_len_left -= len; |
480 | offset += len; | |
481 | } | |
01f2e4ea | 482 | |
ea0d7d91 | 483 | if (eop) |
065df159 | 484 | return 0; |
ea0d7d91 SF |
485 | |
486 | /* Queue WQ_ENET_MAX_DESC_LEN length descriptors | |
487 | * for additional data fragments | |
488 | */ | |
489 | for (frag = skb_shinfo(skb)->frags; len_left; frag++) { | |
9e903e08 ED |
490 | len_left -= skb_frag_size(frag); |
491 | frag_len_left = skb_frag_size(frag); | |
4bf5adbf | 492 | offset = 0; |
ea0d7d91 SF |
493 | |
494 | while (frag_len_left) { | |
495 | len = min(frag_len_left, | |
496 | (unsigned int)WQ_ENET_MAX_DESC_LEN); | |
4bf5adbf IC |
497 | dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, |
498 | offset, len, | |
5d6bcdfe | 499 | DMA_TO_DEVICE); |
065df159 GV |
500 | if (unlikely(enic_dma_map_check(enic, dma_addr))) |
501 | return -ENOMEM; | |
502 | enic_queue_wq_desc_cont(wq, skb, dma_addr, len, | |
503 | (len_left == 0) && | |
504 | (len == frag_len_left),/*EOP*/ | |
505 | loopback); | |
ea0d7d91 SF |
506 | frag_len_left -= len; |
507 | offset += len; | |
508 | } | |
509 | } | |
065df159 GV |
510 | |
511 | return 0; | |
01f2e4ea SF |
512 | } |
513 | ||
514 | static inline void enic_queue_wq_skb(struct enic *enic, | |
515 | struct vnic_wq *wq, struct sk_buff *skb) | |
516 | { | |
517 | unsigned int mss = skb_shinfo(skb)->gso_size; | |
518 | unsigned int vlan_tag = 0; | |
519 | int vlan_tag_insert = 0; | |
1825aca6 | 520 | int loopback = 0; |
065df159 | 521 | int err; |
01f2e4ea | 522 | |
df8a39de | 523 | if (skb_vlan_tag_present(skb)) { |
01f2e4ea SF |
524 | /* VLAN tag from trunking driver */ |
525 | vlan_tag_insert = 1; | |
df8a39de | 526 | vlan_tag = skb_vlan_tag_get(skb); |
1825aca6 VK |
527 | } else if (enic->loop_enable) { |
528 | vlan_tag = enic->loop_tag; | |
529 | loopback = 1; | |
01f2e4ea SF |
530 | } |
531 | ||
532 | if (mss) | |
065df159 GV |
533 | err = enic_queue_wq_skb_tso(enic, wq, skb, mss, |
534 | vlan_tag_insert, vlan_tag, | |
535 | loopback); | |
01f2e4ea | 536 | else if (skb->ip_summed == CHECKSUM_PARTIAL) |
065df159 GV |
537 | err = enic_queue_wq_skb_csum_l4(enic, wq, skb, vlan_tag_insert, |
538 | vlan_tag, loopback); | |
01f2e4ea | 539 | else |
065df159 GV |
540 | err = enic_queue_wq_skb_vlan(enic, wq, skb, vlan_tag_insert, |
541 | vlan_tag, loopback); | |
542 | if (unlikely(err)) { | |
543 | struct vnic_wq_buf *buf; | |
544 | ||
545 | buf = wq->to_use->prev; | |
546 | /* while not EOP of previous pkt && queue not empty. | |
547 | * For all non EOP bufs, os_buf is NULL. | |
548 | */ | |
549 | while (!buf->os_buf && (buf->next != wq->to_clean)) { | |
550 | enic_free_wq_buf(wq, buf); | |
551 | wq->ring.desc_avail++; | |
552 | buf = buf->prev; | |
553 | } | |
554 | wq->to_use = buf->next; | |
555 | dev_kfree_skb(skb); | |
556 | } | |
01f2e4ea SF |
557 | } |
558 | ||
ed8af6b2 | 559 | /* netif_tx_lock held, process context with BHs disabled, or BH */ |
61357325 | 560 | static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb, |
d87fd25d | 561 | struct net_device *netdev) |
01f2e4ea SF |
562 | { |
563 | struct enic *enic = netdev_priv(netdev); | |
822473b6 | 564 | struct vnic_wq *wq; |
822473b6 | 565 | unsigned int txq_map; |
f8e34d24 | 566 | struct netdev_queue *txq; |
01f2e4ea SF |
567 | |
568 | if (skb->len <= 0) { | |
98d8a65d | 569 | dev_kfree_skb_any(skb); |
01f2e4ea SF |
570 | return NETDEV_TX_OK; |
571 | } | |
572 | ||
822473b6 | 573 | txq_map = skb_get_queue_mapping(skb) % enic->wq_count; |
574 | wq = &enic->wq[txq_map]; | |
f8e34d24 | 575 | txq = netdev_get_tx_queue(netdev, txq_map); |
822473b6 | 576 | |
01f2e4ea SF |
577 | /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs, |
578 | * which is very likely. In the off chance it's going to take | |
579 | * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb. | |
580 | */ | |
581 | ||
582 | if (skb_shinfo(skb)->gso_size == 0 && | |
583 | skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC && | |
584 | skb_linearize(skb)) { | |
98d8a65d | 585 | dev_kfree_skb_any(skb); |
01f2e4ea SF |
586 | return NETDEV_TX_OK; |
587 | } | |
588 | ||
78e2045d | 589 | spin_lock(&enic->wq_lock[txq_map]); |
01f2e4ea | 590 | |
ea0d7d91 SF |
591 | if (vnic_wq_desc_avail(wq) < |
592 | skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) { | |
f8e34d24 | 593 | netif_tx_stop_queue(txq); |
01f2e4ea | 594 | /* This is a hard error, log it */ |
a7a79deb | 595 | netdev_err(netdev, "BUG! Tx ring full when queue awake!\n"); |
78e2045d | 596 | spin_unlock(&enic->wq_lock[txq_map]); |
01f2e4ea SF |
597 | return NETDEV_TX_BUSY; |
598 | } | |
599 | ||
600 | enic_queue_wq_skb(enic, wq, skb); | |
601 | ||
ea0d7d91 | 602 | if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS) |
f8e34d24 GV |
603 | netif_tx_stop_queue(txq); |
604 | if (!skb->xmit_more || netif_xmit_stopped(txq)) | |
605 | vnic_wq_doorbell(wq); | |
01f2e4ea | 606 | |
78e2045d | 607 | spin_unlock(&enic->wq_lock[txq_map]); |
01f2e4ea SF |
608 | |
609 | return NETDEV_TX_OK; | |
610 | } | |
611 | ||
612 | /* dev_base_lock rwlock held, nominally process context */ | |
f20530bc | 613 | static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev, |
614 | struct rtnl_link_stats64 *net_stats) | |
01f2e4ea SF |
615 | { |
616 | struct enic *enic = netdev_priv(netdev); | |
617 | struct vnic_stats *stats; | |
19b596bd | 618 | int err; |
01f2e4ea | 619 | |
19b596bd GV |
620 | err = enic_dev_stats_dump(enic, &stats); |
621 | /* return only when pci_zalloc_consistent fails in vnic_dev_stats_dump | |
622 | * For other failures, like devcmd failure, we return previously | |
623 | * recorded stats. | |
624 | */ | |
625 | if (err == -ENOMEM) | |
626 | return net_stats; | |
01f2e4ea | 627 | |
25f0a061 SF |
628 | net_stats->tx_packets = stats->tx.tx_frames_ok; |
629 | net_stats->tx_bytes = stats->tx.tx_bytes_ok; | |
630 | net_stats->tx_errors = stats->tx.tx_errors; | |
631 | net_stats->tx_dropped = stats->tx.tx_drops; | |
01f2e4ea | 632 | |
25f0a061 SF |
633 | net_stats->rx_packets = stats->rx.rx_frames_ok; |
634 | net_stats->rx_bytes = stats->rx.rx_bytes_ok; | |
635 | net_stats->rx_errors = stats->rx.rx_errors; | |
636 | net_stats->multicast = stats->rx.rx_multicast_frames_ok; | |
350991e1 | 637 | net_stats->rx_over_errors = enic->rq_truncated_pkts; |
bd9fb1a4 | 638 | net_stats->rx_crc_errors = enic->rq_bad_fcs; |
350991e1 | 639 | net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop; |
01f2e4ea | 640 | |
25f0a061 | 641 | return net_stats; |
01f2e4ea SF |
642 | } |
643 | ||
f009618a AD |
644 | static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr) |
645 | { | |
646 | struct enic *enic = netdev_priv(netdev); | |
647 | ||
648 | if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) { | |
649 | unsigned int mc_count = netdev_mc_count(netdev); | |
650 | ||
651 | netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n", | |
652 | ENIC_MULTICAST_PERFECT_FILTERS, mc_count); | |
653 | ||
654 | return -ENOSPC; | |
655 | } | |
656 | ||
657 | enic_dev_add_addr(enic, mc_addr); | |
658 | enic->mc_count++; | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr) | |
664 | { | |
665 | struct enic *enic = netdev_priv(netdev); | |
666 | ||
667 | enic_dev_del_addr(enic, mc_addr); | |
668 | enic->mc_count--; | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr) | |
674 | { | |
675 | struct enic *enic = netdev_priv(netdev); | |
676 | ||
677 | if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) { | |
678 | unsigned int uc_count = netdev_uc_count(netdev); | |
679 | ||
680 | netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n", | |
681 | ENIC_UNICAST_PERFECT_FILTERS, uc_count); | |
682 | ||
683 | return -ENOSPC; | |
684 | } | |
685 | ||
686 | enic_dev_add_addr(enic, uc_addr); | |
687 | enic->uc_count++; | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr) | |
693 | { | |
694 | struct enic *enic = netdev_priv(netdev); | |
695 | ||
696 | enic_dev_del_addr(enic, uc_addr); | |
697 | enic->uc_count--; | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
b3abfbd2 | 702 | void enic_reset_addr_lists(struct enic *enic) |
01f2e4ea | 703 | { |
f009618a AD |
704 | struct net_device *netdev = enic->netdev; |
705 | ||
706 | __dev_uc_unsync(netdev, NULL); | |
707 | __dev_mc_unsync(netdev, NULL); | |
708 | ||
01f2e4ea | 709 | enic->mc_count = 0; |
e0afe53f | 710 | enic->uc_count = 0; |
99ef5639 | 711 | enic->flags = 0; |
01f2e4ea SF |
712 | } |
713 | ||
714 | static int enic_set_mac_addr(struct net_device *netdev, char *addr) | |
715 | { | |
f8bd9091 SF |
716 | struct enic *enic = netdev_priv(netdev); |
717 | ||
7335903c | 718 | if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) { |
f8bd9091 SF |
719 | if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr)) |
720 | return -EADDRNOTAVAIL; | |
721 | } else { | |
722 | if (!is_valid_ether_addr(addr)) | |
723 | return -EADDRNOTAVAIL; | |
724 | } | |
01f2e4ea SF |
725 | |
726 | memcpy(netdev->dev_addr, addr, netdev->addr_len); | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
f8bd9091 SF |
731 | static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p) |
732 | { | |
733 | struct enic *enic = netdev_priv(netdev); | |
734 | struct sockaddr *saddr = p; | |
735 | char *addr = saddr->sa_data; | |
736 | int err; | |
737 | ||
738 | if (netif_running(enic->netdev)) { | |
739 | err = enic_dev_del_station_addr(enic); | |
740 | if (err) | |
741 | return err; | |
742 | } | |
743 | ||
744 | err = enic_set_mac_addr(netdev, addr); | |
745 | if (err) | |
746 | return err; | |
747 | ||
748 | if (netif_running(enic->netdev)) { | |
749 | err = enic_dev_add_station_addr(enic); | |
750 | if (err) | |
751 | return err; | |
752 | } | |
753 | ||
754 | return err; | |
755 | } | |
756 | ||
757 | static int enic_set_mac_address(struct net_device *netdev, void *p) | |
758 | { | |
294dab25 | 759 | struct sockaddr *saddr = p; |
c76fd32d VK |
760 | char *addr = saddr->sa_data; |
761 | struct enic *enic = netdev_priv(netdev); | |
762 | int err; | |
763 | ||
764 | err = enic_dev_del_station_addr(enic); | |
765 | if (err) | |
766 | return err; | |
767 | ||
768 | err = enic_set_mac_addr(netdev, addr); | |
769 | if (err) | |
770 | return err; | |
294dab25 | 771 | |
c76fd32d | 772 | return enic_dev_add_station_addr(enic); |
f8bd9091 SF |
773 | } |
774 | ||
319d7e84 RP |
775 | /* netif_tx_lock held, BHs disabled */ |
776 | static void enic_set_rx_mode(struct net_device *netdev) | |
777 | { | |
778 | struct enic *enic = netdev_priv(netdev); | |
779 | int directed = 1; | |
780 | int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0; | |
781 | int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0; | |
782 | int promisc = (netdev->flags & IFF_PROMISC) || | |
783 | netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS; | |
784 | int allmulti = (netdev->flags & IFF_ALLMULTI) || | |
785 | netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS; | |
786 | unsigned int flags = netdev->flags | | |
787 | (allmulti ? IFF_ALLMULTI : 0) | | |
788 | (promisc ? IFF_PROMISC : 0); | |
789 | ||
790 | if (enic->flags != flags) { | |
791 | enic->flags = flags; | |
792 | enic_dev_packet_filter(enic, directed, | |
793 | multicast, broadcast, promisc, allmulti); | |
794 | } | |
795 | ||
796 | if (!promisc) { | |
f009618a | 797 | __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync); |
319d7e84 | 798 | if (!allmulti) |
f009618a | 799 | __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync); |
319d7e84 RP |
800 | } |
801 | } | |
802 | ||
01f2e4ea SF |
803 | /* netif_tx_lock held, BHs disabled */ |
804 | static void enic_tx_timeout(struct net_device *netdev) | |
805 | { | |
806 | struct enic *enic = netdev_priv(netdev); | |
807 | schedule_work(&enic->reset); | |
808 | } | |
809 | ||
0b1c00fc RP |
810 | static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
811 | { | |
812 | struct enic *enic = netdev_priv(netdev); | |
3f192795 RP |
813 | struct enic_port_profile *pp; |
814 | int err; | |
0b1c00fc | 815 | |
3f192795 RP |
816 | ENIC_PP_BY_INDEX(enic, vf, pp, &err); |
817 | if (err) | |
818 | return err; | |
0b1c00fc | 819 | |
b8622cbd | 820 | if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) { |
b4765833 RP |
821 | if (vf == PORT_SELF_VF) { |
822 | memcpy(pp->vf_mac, mac, ETH_ALEN); | |
823 | return 0; | |
824 | } else { | |
825 | /* | |
826 | * For sriov vf's set the mac in hw | |
827 | */ | |
828 | ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic, | |
829 | vnic_dev_set_mac_addr, mac); | |
830 | return enic_dev_status_to_errno(err); | |
831 | } | |
0b1c00fc RP |
832 | } else |
833 | return -EINVAL; | |
834 | } | |
835 | ||
f8bd9091 SF |
836 | static int enic_set_vf_port(struct net_device *netdev, int vf, |
837 | struct nlattr *port[]) | |
838 | { | |
839 | struct enic *enic = netdev_priv(netdev); | |
b3abfbd2 | 840 | struct enic_port_profile prev_pp; |
3f192795 | 841 | struct enic_port_profile *pp; |
b3abfbd2 | 842 | int err = 0, restore_pp = 1; |
08f382eb | 843 | |
3f192795 RP |
844 | ENIC_PP_BY_INDEX(enic, vf, pp, &err); |
845 | if (err) | |
846 | return err; | |
08f382eb | 847 | |
b3abfbd2 RP |
848 | if (!port[IFLA_PORT_REQUEST]) |
849 | return -EOPNOTSUPP; | |
850 | ||
3f192795 RP |
851 | memcpy(&prev_pp, pp, sizeof(*enic->pp)); |
852 | memset(pp, 0, sizeof(*enic->pp)); | |
b3abfbd2 | 853 | |
3f192795 RP |
854 | pp->set |= ENIC_SET_REQUEST; |
855 | pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]); | |
08f382eb SF |
856 | |
857 | if (port[IFLA_PORT_PROFILE]) { | |
3f192795 RP |
858 | pp->set |= ENIC_SET_NAME; |
859 | memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]), | |
08f382eb SF |
860 | PORT_PROFILE_MAX); |
861 | } | |
862 | ||
863 | if (port[IFLA_PORT_INSTANCE_UUID]) { | |
3f192795 RP |
864 | pp->set |= ENIC_SET_INSTANCE; |
865 | memcpy(pp->instance_uuid, | |
08f382eb SF |
866 | nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX); |
867 | } | |
868 | ||
869 | if (port[IFLA_PORT_HOST_UUID]) { | |
3f192795 RP |
870 | pp->set |= ENIC_SET_HOST; |
871 | memcpy(pp->host_uuid, | |
08f382eb SF |
872 | nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX); |
873 | } | |
f8bd9091 | 874 | |
b4765833 RP |
875 | if (vf == PORT_SELF_VF) { |
876 | /* Special case handling: mac came from IFLA_VF_MAC */ | |
877 | if (!is_zero_ether_addr(prev_pp.vf_mac)) | |
878 | memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN); | |
418c437d | 879 | |
b4765833 RP |
880 | if (is_zero_ether_addr(netdev->dev_addr)) |
881 | eth_hw_addr_random(netdev); | |
882 | } else { | |
883 | /* SR-IOV VF: get mac from adapter */ | |
884 | ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic, | |
885 | vnic_dev_get_mac_addr, pp->mac_addr); | |
886 | if (err) { | |
887 | netdev_err(netdev, "Error getting mac for vf %d\n", vf); | |
888 | memcpy(pp, &prev_pp, sizeof(*pp)); | |
889 | return enic_dev_status_to_errno(err); | |
890 | } | |
891 | } | |
f8bd9091 | 892 | |
3f192795 | 893 | err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp); |
b3abfbd2 RP |
894 | if (err) { |
895 | if (restore_pp) { | |
896 | /* Things are still the way they were: Implicit | |
897 | * DISASSOCIATE failed | |
898 | */ | |
3f192795 | 899 | memcpy(pp, &prev_pp, sizeof(*pp)); |
b3abfbd2 | 900 | } else { |
3f192795 RP |
901 | memset(pp, 0, sizeof(*pp)); |
902 | if (vf == PORT_SELF_VF) | |
c7bf7169 | 903 | eth_zero_addr(netdev->dev_addr); |
b3abfbd2 RP |
904 | } |
905 | } else { | |
906 | /* Set flag to indicate that the port assoc/disassoc | |
907 | * request has been sent out to fw | |
908 | */ | |
3f192795 | 909 | pp->set |= ENIC_PORT_REQUEST_APPLIED; |
b3abfbd2 RP |
910 | |
911 | /* If DISASSOCIATE, clean up all assigned/saved macaddresses */ | |
3f192795 | 912 | if (pp->request == PORT_REQUEST_DISASSOCIATE) { |
c7bf7169 | 913 | eth_zero_addr(pp->mac_addr); |
3f192795 | 914 | if (vf == PORT_SELF_VF) |
c7bf7169 | 915 | eth_zero_addr(netdev->dev_addr); |
b3abfbd2 RP |
916 | } |
917 | } | |
29639059 | 918 | |
b4765833 | 919 | if (vf == PORT_SELF_VF) |
c7bf7169 | 920 | eth_zero_addr(pp->vf_mac); |
29639059 | 921 | |
29639059 | 922 | return err; |
f8bd9091 SF |
923 | } |
924 | ||
925 | static int enic_get_vf_port(struct net_device *netdev, int vf, | |
926 | struct sk_buff *skb) | |
927 | { | |
928 | struct enic *enic = netdev_priv(netdev); | |
f8bd9091 | 929 | u16 response = PORT_PROFILE_RESPONSE_SUCCESS; |
3f192795 | 930 | struct enic_port_profile *pp; |
b3abfbd2 | 931 | int err; |
f8bd9091 | 932 | |
3f192795 RP |
933 | ENIC_PP_BY_INDEX(enic, vf, pp, &err); |
934 | if (err) | |
935 | return err; | |
936 | ||
937 | if (!(pp->set & ENIC_PORT_REQUEST_APPLIED)) | |
08f382eb | 938 | return -ENODATA; |
f8bd9091 | 939 | |
3f192795 | 940 | err = enic_process_get_pp_request(enic, vf, pp->request, &response); |
f8bd9091 | 941 | if (err) |
b3abfbd2 | 942 | return err; |
f8bd9091 | 943 | |
1a106de6 DM |
944 | if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) || |
945 | nla_put_u16(skb, IFLA_PORT_RESPONSE, response) || | |
946 | ((pp->set & ENIC_SET_NAME) && | |
947 | nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) || | |
948 | ((pp->set & ENIC_SET_INSTANCE) && | |
949 | nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX, | |
950 | pp->instance_uuid)) || | |
951 | ((pp->set & ENIC_SET_HOST) && | |
952 | nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid))) | |
953 | goto nla_put_failure; | |
f8bd9091 SF |
954 | return 0; |
955 | ||
956 | nla_put_failure: | |
957 | return -EMSGSIZE; | |
958 | } | |
959 | ||
01f2e4ea SF |
960 | static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf) |
961 | { | |
962 | struct enic *enic = vnic_dev_priv(rq->vdev); | |
963 | ||
964 | if (!buf->os_buf) | |
965 | return; | |
966 | ||
967 | pci_unmap_single(enic->pdev, buf->dma_addr, | |
968 | buf->len, PCI_DMA_FROMDEVICE); | |
969 | dev_kfree_skb_any(buf->os_buf); | |
a03bb56e | 970 | buf->os_buf = NULL; |
01f2e4ea SF |
971 | } |
972 | ||
01f2e4ea SF |
973 | static int enic_rq_alloc_buf(struct vnic_rq *rq) |
974 | { | |
975 | struct enic *enic = vnic_dev_priv(rq->vdev); | |
d19e22dc | 976 | struct net_device *netdev = enic->netdev; |
01f2e4ea | 977 | struct sk_buff *skb; |
1825aca6 | 978 | unsigned int len = netdev->mtu + VLAN_ETH_HLEN; |
01f2e4ea SF |
979 | unsigned int os_buf_index = 0; |
980 | dma_addr_t dma_addr; | |
a03bb56e GV |
981 | struct vnic_rq_buf *buf = rq->to_use; |
982 | ||
983 | if (buf->os_buf) { | |
f6b7734b GV |
984 | enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr, |
985 | buf->len); | |
01f2e4ea | 986 | |
a03bb56e GV |
987 | return 0; |
988 | } | |
89d71a66 | 989 | skb = netdev_alloc_skb_ip_align(netdev, len); |
01f2e4ea SF |
990 | if (!skb) |
991 | return -ENOMEM; | |
992 | ||
065df159 GV |
993 | dma_addr = pci_map_single(enic->pdev, skb->data, len, |
994 | PCI_DMA_FROMDEVICE); | |
995 | if (unlikely(enic_dma_map_check(enic, dma_addr))) { | |
996 | dev_kfree_skb(skb); | |
997 | return -ENOMEM; | |
998 | } | |
01f2e4ea SF |
999 | |
1000 | enic_queue_rq_desc(rq, skb, os_buf_index, | |
1001 | dma_addr, len); | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
7c2ce6e6 SS |
1006 | static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size, |
1007 | u32 pkt_len) | |
1008 | { | |
1009 | if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len) | |
1010 | pkt_size->large_pkt_bytes_cnt += pkt_len; | |
1011 | else | |
1012 | pkt_size->small_pkt_bytes_cnt += pkt_len; | |
1013 | } | |
1014 | ||
a03bb56e GV |
1015 | static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb, |
1016 | struct vnic_rq_buf *buf, u16 len) | |
1017 | { | |
1018 | struct enic *enic = netdev_priv(netdev); | |
1019 | struct sk_buff *new_skb; | |
1020 | ||
1021 | if (len > enic->rx_copybreak) | |
1022 | return false; | |
1023 | new_skb = netdev_alloc_skb_ip_align(netdev, len); | |
1024 | if (!new_skb) | |
1025 | return false; | |
1026 | pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len, | |
1027 | DMA_FROM_DEVICE); | |
1028 | memcpy(new_skb->data, (*skb)->data, len); | |
1029 | *skb = new_skb; | |
1030 | ||
1031 | return true; | |
1032 | } | |
1033 | ||
01f2e4ea SF |
1034 | static void enic_rq_indicate_buf(struct vnic_rq *rq, |
1035 | struct cq_desc *cq_desc, struct vnic_rq_buf *buf, | |
1036 | int skipped, void *opaque) | |
1037 | { | |
1038 | struct enic *enic = vnic_dev_priv(rq->vdev); | |
86ca9db7 | 1039 | struct net_device *netdev = enic->netdev; |
01f2e4ea | 1040 | struct sk_buff *skb; |
7c2ce6e6 | 1041 | struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; |
01f2e4ea SF |
1042 | |
1043 | u8 type, color, eop, sop, ingress_port, vlan_stripped; | |
1044 | u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof; | |
1045 | u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok; | |
1046 | u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc; | |
1047 | u8 packet_error; | |
f8cac14a | 1048 | u16 q_number, completed_index, bytes_written, vlan_tci, checksum; |
01f2e4ea SF |
1049 | u32 rss_hash; |
1050 | ||
1051 | if (skipped) | |
1052 | return; | |
1053 | ||
1054 | skb = buf->os_buf; | |
01f2e4ea SF |
1055 | |
1056 | cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc, | |
1057 | &type, &color, &q_number, &completed_index, | |
1058 | &ingress_port, &fcoe, &eop, &sop, &rss_type, | |
1059 | &csum_not_calc, &rss_hash, &bytes_written, | |
f8cac14a | 1060 | &packet_error, &vlan_stripped, &vlan_tci, &checksum, |
01f2e4ea SF |
1061 | &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error, |
1062 | &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp, | |
1063 | &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment, | |
1064 | &fcs_ok); | |
1065 | ||
1066 | if (packet_error) { | |
1067 | ||
350991e1 SF |
1068 | if (!fcs_ok) { |
1069 | if (bytes_written > 0) | |
1070 | enic->rq_bad_fcs++; | |
1071 | else if (bytes_written == 0) | |
1072 | enic->rq_truncated_pkts++; | |
1073 | } | |
01f2e4ea | 1074 | |
44aa91ab GV |
1075 | pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, |
1076 | PCI_DMA_FROMDEVICE); | |
01f2e4ea | 1077 | dev_kfree_skb_any(skb); |
44aa91ab | 1078 | buf->os_buf = NULL; |
01f2e4ea SF |
1079 | |
1080 | return; | |
1081 | } | |
1082 | ||
1083 | if (eop && bytes_written > 0) { | |
1084 | ||
1085 | /* Good receive | |
1086 | */ | |
1087 | ||
a03bb56e GV |
1088 | if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) { |
1089 | buf->os_buf = NULL; | |
1090 | pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, | |
1091 | PCI_DMA_FROMDEVICE); | |
1092 | } | |
1093 | prefetch(skb->data - NET_IP_ALIGN); | |
1094 | ||
01f2e4ea | 1095 | skb_put(skb, bytes_written); |
86ca9db7 | 1096 | skb->protocol = eth_type_trans(skb, netdev); |
bf751ba8 | 1097 | skb_record_rx_queue(skb, q_number); |
1098 | if (netdev->features & NETIF_F_RXHASH) { | |
3739acdd TH |
1099 | skb_set_hash(skb, rss_hash, |
1100 | (rss_type & | |
1101 | (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX | | |
1102 | NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 | | |
1103 | NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ? | |
1104 | PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); | |
bf751ba8 | 1105 | } |
01f2e4ea | 1106 | |
17e96834 GV |
1107 | /* Hardware does not provide whole packet checksum. It only |
1108 | * provides pseudo checksum. Since hw validates the packet | |
1109 | * checksum but not provide us the checksum value. use | |
1110 | * CHECSUM_UNNECESSARY. | |
1111 | */ | |
1112 | if ((netdev->features & NETIF_F_RXCSUM) && tcp_udp_csum_ok && | |
1113 | ipv4_csum_ok) | |
1114 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
01f2e4ea | 1115 | |
6ede746b | 1116 | if (vlan_stripped) |
86a9bad3 | 1117 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci); |
01f2e4ea | 1118 | |
14747cd9 GV |
1119 | skb_mark_napi_id(skb, &enic->napi[rq->index]); |
1120 | if (enic_poll_busy_polling(rq) || | |
1121 | !(netdev->features & NETIF_F_GRO)) | |
6ede746b | 1122 | netif_receive_skb(skb); |
14747cd9 GV |
1123 | else |
1124 | napi_gro_receive(&enic->napi[q_number], skb); | |
7c2ce6e6 SS |
1125 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) |
1126 | enic_intr_update_pkt_size(&cq->pkt_size_counter, | |
1127 | bytes_written); | |
01f2e4ea SF |
1128 | } else { |
1129 | ||
1130 | /* Buffer overflow | |
1131 | */ | |
1132 | ||
44aa91ab GV |
1133 | pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, |
1134 | PCI_DMA_FROMDEVICE); | |
01f2e4ea | 1135 | dev_kfree_skb_any(skb); |
44aa91ab | 1136 | buf->os_buf = NULL; |
01f2e4ea SF |
1137 | } |
1138 | } | |
1139 | ||
1140 | static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc, | |
1141 | u8 type, u16 q_number, u16 completed_index, void *opaque) | |
1142 | { | |
1143 | struct enic *enic = vnic_dev_priv(vdev); | |
1144 | ||
1145 | vnic_rq_service(&enic->rq[q_number], cq_desc, | |
1146 | completed_index, VNIC_RQ_RETURN_DESC, | |
1147 | enic_rq_indicate_buf, opaque); | |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
01f2e4ea SF |
1152 | static int enic_poll(struct napi_struct *napi, int budget) |
1153 | { | |
717258ba VK |
1154 | struct net_device *netdev = napi->dev; |
1155 | struct enic *enic = netdev_priv(netdev); | |
1156 | unsigned int cq_rq = enic_cq_rq(enic, 0); | |
1157 | unsigned int cq_wq = enic_cq_wq(enic, 0); | |
1158 | unsigned int intr = enic_legacy_io_intr(); | |
01f2e4ea SF |
1159 | unsigned int rq_work_to_do = budget; |
1160 | unsigned int wq_work_to_do = -1; /* no limit */ | |
4c502549 | 1161 | unsigned int work_done, rq_work_done = 0, wq_work_done; |
2d6ddced | 1162 | int err; |
01f2e4ea | 1163 | |
14747cd9 GV |
1164 | wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do, |
1165 | enic_wq_service, NULL); | |
1166 | ||
1167 | if (!enic_poll_lock_napi(&enic->rq[cq_rq])) { | |
1168 | if (wq_work_done > 0) | |
1169 | vnic_intr_return_credits(&enic->intr[intr], | |
1170 | wq_work_done, | |
1171 | 0 /* dont unmask intr */, | |
1172 | 0 /* dont reset intr timer */); | |
1173 | return rq_work_done; | |
1174 | } | |
01f2e4ea | 1175 | |
4c502549 EB |
1176 | if (budget > 0) |
1177 | rq_work_done = vnic_cq_service(&enic->cq[cq_rq], | |
1178 | rq_work_to_do, enic_rq_service, NULL); | |
01f2e4ea | 1179 | |
01f2e4ea SF |
1180 | /* Accumulate intr event credits for this polling |
1181 | * cycle. An intr event is the completion of a | |
1182 | * a WQ or RQ packet. | |
1183 | */ | |
1184 | ||
1185 | work_done = rq_work_done + wq_work_done; | |
1186 | ||
1187 | if (work_done > 0) | |
717258ba | 1188 | vnic_intr_return_credits(&enic->intr[intr], |
01f2e4ea SF |
1189 | work_done, |
1190 | 0 /* don't unmask intr */, | |
1191 | 0 /* don't reset intr timer */); | |
1192 | ||
0eb26022 | 1193 | err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf); |
01f2e4ea | 1194 | |
2d6ddced SF |
1195 | /* Buffer allocation failed. Stay in polling |
1196 | * mode so we can try to fill the ring again. | |
1197 | */ | |
01f2e4ea | 1198 | |
2d6ddced SF |
1199 | if (err) |
1200 | rq_work_done = rq_work_to_do; | |
01f2e4ea | 1201 | |
2d6ddced | 1202 | if (rq_work_done < rq_work_to_do) { |
01f2e4ea | 1203 | |
2d6ddced | 1204 | /* Some work done, but not enough to stay in polling, |
88132f55 | 1205 | * exit polling |
01f2e4ea SF |
1206 | */ |
1207 | ||
288379f0 | 1208 | napi_complete(napi); |
717258ba | 1209 | vnic_intr_unmask(&enic->intr[intr]); |
01f2e4ea | 1210 | } |
14747cd9 | 1211 | enic_poll_unlock_napi(&enic->rq[cq_rq]); |
01f2e4ea SF |
1212 | |
1213 | return rq_work_done; | |
1214 | } | |
1215 | ||
7c2ce6e6 SS |
1216 | static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq) |
1217 | { | |
1218 | unsigned int intr = enic_msix_rq_intr(enic, rq->index); | |
1219 | struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; | |
1220 | u32 timer = cq->tobe_rx_coal_timeval; | |
1221 | ||
1222 | if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) { | |
1223 | vnic_intr_coalescing_timer_set(&enic->intr[intr], timer); | |
1224 | cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval; | |
1225 | } | |
1226 | } | |
1227 | ||
1228 | static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq) | |
1229 | { | |
1230 | struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting; | |
1231 | struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; | |
1232 | struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter; | |
1233 | int index; | |
1234 | u32 timer; | |
1235 | u32 range_start; | |
1236 | u32 traffic; | |
1237 | u64 delta; | |
1238 | ktime_t now = ktime_get(); | |
1239 | ||
1240 | delta = ktime_us_delta(now, cq->prev_ts); | |
1241 | if (delta < ENIC_AIC_TS_BREAK) | |
1242 | return; | |
1243 | cq->prev_ts = now; | |
1244 | ||
1245 | traffic = pkt_size_counter->large_pkt_bytes_cnt + | |
1246 | pkt_size_counter->small_pkt_bytes_cnt; | |
1247 | /* The table takes Mbps | |
1248 | * traffic *= 8 => bits | |
1249 | * traffic *= (10^6 / delta) => bps | |
1250 | * traffic /= 10^6 => Mbps | |
1251 | * | |
1252 | * Combining, traffic *= (8 / delta) | |
1253 | */ | |
1254 | ||
1255 | traffic <<= 3; | |
958c492c | 1256 | traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta; |
7c2ce6e6 SS |
1257 | |
1258 | for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++) | |
1259 | if (traffic < mod_table[index].rx_rate) | |
1260 | break; | |
1261 | range_start = (pkt_size_counter->small_pkt_bytes_cnt > | |
1262 | pkt_size_counter->large_pkt_bytes_cnt << 1) ? | |
1263 | rx_coal->small_pkt_range_start : | |
1264 | rx_coal->large_pkt_range_start; | |
1265 | timer = range_start + ((rx_coal->range_end - range_start) * | |
1266 | mod_table[index].range_percent / 100); | |
1267 | /* Damping */ | |
1268 | cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1; | |
1269 | ||
1270 | pkt_size_counter->large_pkt_bytes_cnt = 0; | |
1271 | pkt_size_counter->small_pkt_bytes_cnt = 0; | |
1272 | } | |
1273 | ||
b6e97c13 GV |
1274 | #ifdef CONFIG_RFS_ACCEL |
1275 | static void enic_free_rx_cpu_rmap(struct enic *enic) | |
1276 | { | |
1277 | free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap); | |
1278 | enic->netdev->rx_cpu_rmap = NULL; | |
1279 | } | |
1280 | ||
1281 | static void enic_set_rx_cpu_rmap(struct enic *enic) | |
1282 | { | |
1283 | int i, res; | |
1284 | ||
1285 | if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) { | |
1286 | enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count); | |
1287 | if (unlikely(!enic->netdev->rx_cpu_rmap)) | |
1288 | return; | |
1289 | for (i = 0; i < enic->rq_count; i++) { | |
1290 | res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap, | |
1291 | enic->msix_entry[i].vector); | |
1292 | if (unlikely(res)) { | |
1293 | enic_free_rx_cpu_rmap(enic); | |
1294 | return; | |
1295 | } | |
1296 | } | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | #else | |
1301 | ||
1302 | static void enic_free_rx_cpu_rmap(struct enic *enic) | |
1303 | { | |
1304 | } | |
1305 | ||
1306 | static void enic_set_rx_cpu_rmap(struct enic *enic) | |
1307 | { | |
1308 | } | |
1309 | ||
1310 | #endif /* CONFIG_RFS_ACCEL */ | |
1311 | ||
14747cd9 | 1312 | #ifdef CONFIG_NET_RX_BUSY_POLL |
57ae84a0 | 1313 | static int enic_busy_poll(struct napi_struct *napi) |
14747cd9 GV |
1314 | { |
1315 | struct net_device *netdev = napi->dev; | |
1316 | struct enic *enic = netdev_priv(netdev); | |
1317 | unsigned int rq = (napi - &enic->napi[0]); | |
1318 | unsigned int cq = enic_cq_rq(enic, rq); | |
1319 | unsigned int intr = enic_msix_rq_intr(enic, rq); | |
1320 | unsigned int work_to_do = -1; /* clean all pkts possible */ | |
1321 | unsigned int work_done; | |
1322 | ||
1323 | if (!enic_poll_lock_poll(&enic->rq[rq])) | |
1324 | return LL_FLUSH_BUSY; | |
1325 | work_done = vnic_cq_service(&enic->cq[cq], work_to_do, | |
1326 | enic_rq_service, NULL); | |
1327 | ||
1328 | if (work_done > 0) | |
1329 | vnic_intr_return_credits(&enic->intr[intr], | |
1330 | work_done, 0, 0); | |
1331 | vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf); | |
1332 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) | |
1333 | enic_calc_int_moderation(enic, &enic->rq[rq]); | |
1334 | enic_poll_unlock_poll(&enic->rq[rq]); | |
1335 | ||
1336 | return work_done; | |
1337 | } | |
1338 | #endif /* CONFIG_NET_RX_BUSY_POLL */ | |
1339 | ||
4cfe8785 GV |
1340 | static int enic_poll_msix_wq(struct napi_struct *napi, int budget) |
1341 | { | |
1342 | struct net_device *netdev = napi->dev; | |
1343 | struct enic *enic = netdev_priv(netdev); | |
1344 | unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count; | |
1345 | struct vnic_wq *wq = &enic->wq[wq_index]; | |
1346 | unsigned int cq; | |
1347 | unsigned int intr; | |
1348 | unsigned int wq_work_to_do = -1; /* clean all desc possible */ | |
1349 | unsigned int wq_work_done; | |
1350 | unsigned int wq_irq; | |
1351 | ||
1352 | wq_irq = wq->index; | |
1353 | cq = enic_cq_wq(enic, wq_irq); | |
1354 | intr = enic_msix_wq_intr(enic, wq_irq); | |
1355 | wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do, | |
1356 | enic_wq_service, NULL); | |
1357 | ||
1358 | vnic_intr_return_credits(&enic->intr[intr], wq_work_done, | |
1359 | 0 /* don't unmask intr */, | |
1360 | 1 /* reset intr timer */); | |
1361 | if (!wq_work_done) { | |
1362 | napi_complete(napi); | |
1363 | vnic_intr_unmask(&enic->intr[intr]); | |
f41281d0 | 1364 | return 0; |
4cfe8785 GV |
1365 | } |
1366 | ||
f41281d0 | 1367 | return budget; |
4cfe8785 GV |
1368 | } |
1369 | ||
1370 | static int enic_poll_msix_rq(struct napi_struct *napi, int budget) | |
01f2e4ea | 1371 | { |
717258ba VK |
1372 | struct net_device *netdev = napi->dev; |
1373 | struct enic *enic = netdev_priv(netdev); | |
1374 | unsigned int rq = (napi - &enic->napi[0]); | |
1375 | unsigned int cq = enic_cq_rq(enic, rq); | |
1376 | unsigned int intr = enic_msix_rq_intr(enic, rq); | |
01f2e4ea | 1377 | unsigned int work_to_do = budget; |
4c502549 | 1378 | unsigned int work_done = 0; |
2d6ddced | 1379 | int err; |
01f2e4ea | 1380 | |
14747cd9 | 1381 | if (!enic_poll_lock_napi(&enic->rq[rq])) |
f104fedc | 1382 | return budget; |
01f2e4ea SF |
1383 | /* Service RQ |
1384 | */ | |
1385 | ||
4c502549 EB |
1386 | if (budget > 0) |
1387 | work_done = vnic_cq_service(&enic->cq[cq], | |
1388 | work_to_do, enic_rq_service, NULL); | |
01f2e4ea | 1389 | |
2d6ddced SF |
1390 | /* Return intr event credits for this polling |
1391 | * cycle. An intr event is the completion of a | |
1392 | * RQ packet. | |
1393 | */ | |
01f2e4ea | 1394 | |
2d6ddced | 1395 | if (work_done > 0) |
717258ba | 1396 | vnic_intr_return_credits(&enic->intr[intr], |
01f2e4ea SF |
1397 | work_done, |
1398 | 0 /* don't unmask intr */, | |
1399 | 0 /* don't reset intr timer */); | |
01f2e4ea | 1400 | |
0eb26022 | 1401 | err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf); |
2d6ddced SF |
1402 | |
1403 | /* Buffer allocation failed. Stay in polling mode | |
1404 | * so we can try to fill the ring again. | |
1405 | */ | |
1406 | ||
1407 | if (err) | |
1408 | work_done = work_to_do; | |
7c2ce6e6 SS |
1409 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) |
1410 | /* Call the function which refreshes | |
1411 | * the intr coalescing timer value based on | |
1412 | * the traffic. This is supported only in | |
1413 | * the case of MSI-x mode | |
1414 | */ | |
1415 | enic_calc_int_moderation(enic, &enic->rq[rq]); | |
2d6ddced | 1416 | |
6286e828 | 1417 | enic_poll_unlock_napi(&enic->rq[rq]); |
2d6ddced SF |
1418 | if (work_done < work_to_do) { |
1419 | ||
1420 | /* Some work done, but not enough to stay in polling, | |
88132f55 | 1421 | * exit polling |
01f2e4ea SF |
1422 | */ |
1423 | ||
288379f0 | 1424 | napi_complete(napi); |
7c2ce6e6 SS |
1425 | if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) |
1426 | enic_set_int_moderation(enic, &enic->rq[rq]); | |
717258ba | 1427 | vnic_intr_unmask(&enic->intr[intr]); |
01f2e4ea SF |
1428 | } |
1429 | ||
1430 | return work_done; | |
1431 | } | |
1432 | ||
1433 | static void enic_notify_timer(unsigned long data) | |
1434 | { | |
1435 | struct enic *enic = (struct enic *)data; | |
1436 | ||
1437 | enic_notify_check(enic); | |
1438 | ||
25f0a061 SF |
1439 | mod_timer(&enic->notify_timer, |
1440 | round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD)); | |
01f2e4ea SF |
1441 | } |
1442 | ||
1443 | static void enic_free_intr(struct enic *enic) | |
1444 | { | |
1445 | struct net_device *netdev = enic->netdev; | |
1446 | unsigned int i; | |
1447 | ||
b6e97c13 | 1448 | enic_free_rx_cpu_rmap(enic); |
01f2e4ea SF |
1449 | switch (vnic_dev_get_intr_mode(enic->vdev)) { |
1450 | case VNIC_DEV_INTR_MODE_INTX: | |
01f2e4ea SF |
1451 | free_irq(enic->pdev->irq, netdev); |
1452 | break; | |
8f4d248c SF |
1453 | case VNIC_DEV_INTR_MODE_MSI: |
1454 | free_irq(enic->pdev->irq, enic); | |
1455 | break; | |
01f2e4ea SF |
1456 | case VNIC_DEV_INTR_MODE_MSIX: |
1457 | for (i = 0; i < ARRAY_SIZE(enic->msix); i++) | |
1458 | if (enic->msix[i].requested) | |
1459 | free_irq(enic->msix_entry[i].vector, | |
1460 | enic->msix[i].devid); | |
1461 | break; | |
1462 | default: | |
1463 | break; | |
1464 | } | |
1465 | } | |
1466 | ||
1467 | static int enic_request_intr(struct enic *enic) | |
1468 | { | |
1469 | struct net_device *netdev = enic->netdev; | |
717258ba | 1470 | unsigned int i, intr; |
01f2e4ea SF |
1471 | int err = 0; |
1472 | ||
b6e97c13 | 1473 | enic_set_rx_cpu_rmap(enic); |
01f2e4ea SF |
1474 | switch (vnic_dev_get_intr_mode(enic->vdev)) { |
1475 | ||
1476 | case VNIC_DEV_INTR_MODE_INTX: | |
1477 | ||
1478 | err = request_irq(enic->pdev->irq, enic_isr_legacy, | |
1479 | IRQF_SHARED, netdev->name, netdev); | |
1480 | break; | |
1481 | ||
1482 | case VNIC_DEV_INTR_MODE_MSI: | |
1483 | ||
1484 | err = request_irq(enic->pdev->irq, enic_isr_msi, | |
1485 | 0, netdev->name, enic); | |
1486 | break; | |
1487 | ||
1488 | case VNIC_DEV_INTR_MODE_MSIX: | |
1489 | ||
717258ba VK |
1490 | for (i = 0; i < enic->rq_count; i++) { |
1491 | intr = enic_msix_rq_intr(enic, i); | |
4505f40a DC |
1492 | snprintf(enic->msix[intr].devname, |
1493 | sizeof(enic->msix[intr].devname), | |
717258ba | 1494 | "%.11s-rx-%d", netdev->name, i); |
4cfe8785 | 1495 | enic->msix[intr].isr = enic_isr_msix; |
717258ba VK |
1496 | enic->msix[intr].devid = &enic->napi[i]; |
1497 | } | |
01f2e4ea | 1498 | |
717258ba | 1499 | for (i = 0; i < enic->wq_count; i++) { |
4cfe8785 GV |
1500 | int wq = enic_cq_wq(enic, i); |
1501 | ||
717258ba | 1502 | intr = enic_msix_wq_intr(enic, i); |
4505f40a DC |
1503 | snprintf(enic->msix[intr].devname, |
1504 | sizeof(enic->msix[intr].devname), | |
717258ba | 1505 | "%.11s-tx-%d", netdev->name, i); |
4cfe8785 GV |
1506 | enic->msix[intr].isr = enic_isr_msix; |
1507 | enic->msix[intr].devid = &enic->napi[wq]; | |
717258ba | 1508 | } |
01f2e4ea | 1509 | |
717258ba | 1510 | intr = enic_msix_err_intr(enic); |
4505f40a DC |
1511 | snprintf(enic->msix[intr].devname, |
1512 | sizeof(enic->msix[intr].devname), | |
01f2e4ea | 1513 | "%.11s-err", netdev->name); |
717258ba VK |
1514 | enic->msix[intr].isr = enic_isr_msix_err; |
1515 | enic->msix[intr].devid = enic; | |
01f2e4ea | 1516 | |
717258ba | 1517 | intr = enic_msix_notify_intr(enic); |
4505f40a DC |
1518 | snprintf(enic->msix[intr].devname, |
1519 | sizeof(enic->msix[intr].devname), | |
01f2e4ea | 1520 | "%.11s-notify", netdev->name); |
717258ba VK |
1521 | enic->msix[intr].isr = enic_isr_msix_notify; |
1522 | enic->msix[intr].devid = enic; | |
1523 | ||
1524 | for (i = 0; i < ARRAY_SIZE(enic->msix); i++) | |
1525 | enic->msix[i].requested = 0; | |
01f2e4ea | 1526 | |
717258ba | 1527 | for (i = 0; i < enic->intr_count; i++) { |
01f2e4ea SF |
1528 | err = request_irq(enic->msix_entry[i].vector, |
1529 | enic->msix[i].isr, 0, | |
1530 | enic->msix[i].devname, | |
1531 | enic->msix[i].devid); | |
1532 | if (err) { | |
1533 | enic_free_intr(enic); | |
1534 | break; | |
1535 | } | |
1536 | enic->msix[i].requested = 1; | |
1537 | } | |
1538 | ||
1539 | break; | |
1540 | ||
1541 | default: | |
1542 | break; | |
1543 | } | |
1544 | ||
1545 | return err; | |
1546 | } | |
1547 | ||
b3d18d19 SF |
1548 | static void enic_synchronize_irqs(struct enic *enic) |
1549 | { | |
1550 | unsigned int i; | |
1551 | ||
1552 | switch (vnic_dev_get_intr_mode(enic->vdev)) { | |
1553 | case VNIC_DEV_INTR_MODE_INTX: | |
1554 | case VNIC_DEV_INTR_MODE_MSI: | |
1555 | synchronize_irq(enic->pdev->irq); | |
1556 | break; | |
1557 | case VNIC_DEV_INTR_MODE_MSIX: | |
1558 | for (i = 0; i < enic->intr_count; i++) | |
1559 | synchronize_irq(enic->msix_entry[i].vector); | |
1560 | break; | |
1561 | default: | |
1562 | break; | |
1563 | } | |
1564 | } | |
1565 | ||
7c2ce6e6 SS |
1566 | static void enic_set_rx_coal_setting(struct enic *enic) |
1567 | { | |
1568 | unsigned int speed; | |
1569 | int index = -1; | |
1570 | struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting; | |
1571 | ||
1572 | /* If intr mode is not MSIX, do not do adaptive coalescing */ | |
1573 | if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) { | |
1574 | netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing"); | |
1575 | return; | |
1576 | } | |
1577 | ||
1578 | /* 1. Read the link speed from fw | |
1579 | * 2. Pick the default range for the speed | |
1580 | * 3. Update it in enic->rx_coalesce_setting | |
1581 | */ | |
1582 | speed = vnic_dev_port_speed(enic->vdev); | |
1583 | if (ENIC_LINK_SPEED_10G < speed) | |
1584 | index = ENIC_LINK_40G_INDEX; | |
1585 | else if (ENIC_LINK_SPEED_4G < speed) | |
1586 | index = ENIC_LINK_10G_INDEX; | |
1587 | else | |
1588 | index = ENIC_LINK_4G_INDEX; | |
1589 | ||
1590 | rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start; | |
1591 | rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start; | |
1592 | rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END; | |
1593 | ||
1594 | /* Start with the value provided by UCSM */ | |
1595 | for (index = 0; index < enic->rq_count; index++) | |
1596 | enic->cq[index].cur_rx_coal_timeval = | |
1597 | enic->config.intr_timer_usec; | |
1598 | ||
1599 | rx_coal->use_adaptive_rx_coalesce = 1; | |
1600 | } | |
1601 | ||
383ab92f | 1602 | static int enic_dev_notify_set(struct enic *enic) |
01f2e4ea SF |
1603 | { |
1604 | int err; | |
1605 | ||
8e091340 | 1606 | spin_lock_bh(&enic->devcmd_lock); |
01f2e4ea SF |
1607 | switch (vnic_dev_get_intr_mode(enic->vdev)) { |
1608 | case VNIC_DEV_INTR_MODE_INTX: | |
717258ba VK |
1609 | err = vnic_dev_notify_set(enic->vdev, |
1610 | enic_legacy_notify_intr()); | |
01f2e4ea SF |
1611 | break; |
1612 | case VNIC_DEV_INTR_MODE_MSIX: | |
717258ba VK |
1613 | err = vnic_dev_notify_set(enic->vdev, |
1614 | enic_msix_notify_intr(enic)); | |
01f2e4ea SF |
1615 | break; |
1616 | default: | |
1617 | err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */); | |
1618 | break; | |
1619 | } | |
8e091340 | 1620 | spin_unlock_bh(&enic->devcmd_lock); |
01f2e4ea SF |
1621 | |
1622 | return err; | |
1623 | } | |
1624 | ||
1625 | static void enic_notify_timer_start(struct enic *enic) | |
1626 | { | |
1627 | switch (vnic_dev_get_intr_mode(enic->vdev)) { | |
1628 | case VNIC_DEV_INTR_MODE_MSI: | |
1629 | mod_timer(&enic->notify_timer, jiffies); | |
1630 | break; | |
1631 | default: | |
1632 | /* Using intr for notification for INTx/MSI-X */ | |
1633 | break; | |
6403eab1 | 1634 | } |
01f2e4ea SF |
1635 | } |
1636 | ||
1637 | /* rtnl lock is held, process context */ | |
1638 | static int enic_open(struct net_device *netdev) | |
1639 | { | |
1640 | struct enic *enic = netdev_priv(netdev); | |
1641 | unsigned int i; | |
1642 | int err; | |
1643 | ||
4b75a442 SF |
1644 | err = enic_request_intr(enic); |
1645 | if (err) { | |
a7a79deb | 1646 | netdev_err(netdev, "Unable to request irq.\n"); |
4b75a442 SF |
1647 | return err; |
1648 | } | |
1649 | ||
383ab92f | 1650 | err = enic_dev_notify_set(enic); |
4b75a442 | 1651 | if (err) { |
a7a79deb VK |
1652 | netdev_err(netdev, |
1653 | "Failed to alloc notify buffer, aborting.\n"); | |
4b75a442 SF |
1654 | goto err_out_free_intr; |
1655 | } | |
1656 | ||
01f2e4ea | 1657 | for (i = 0; i < enic->rq_count; i++) { |
0eb26022 | 1658 | vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf); |
2d6ddced SF |
1659 | /* Need at least one buffer on ring to get going */ |
1660 | if (vnic_rq_desc_used(&enic->rq[i]) == 0) { | |
a7a79deb | 1661 | netdev_err(netdev, "Unable to alloc receive buffers\n"); |
2d6ddced | 1662 | err = -ENOMEM; |
9dac6232 | 1663 | goto err_out_free_rq; |
01f2e4ea SF |
1664 | } |
1665 | } | |
1666 | ||
1667 | for (i = 0; i < enic->wq_count; i++) | |
1668 | vnic_wq_enable(&enic->wq[i]); | |
1669 | for (i = 0; i < enic->rq_count; i++) | |
1670 | vnic_rq_enable(&enic->rq[i]); | |
1671 | ||
7335903c | 1672 | if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic)) |
29639059 | 1673 | enic_dev_add_station_addr(enic); |
3f192795 | 1674 | |
319d7e84 | 1675 | enic_set_rx_mode(netdev); |
01f2e4ea | 1676 | |
822473b6 | 1677 | netif_tx_wake_all_queues(netdev); |
717258ba | 1678 | |
14747cd9 GV |
1679 | for (i = 0; i < enic->rq_count; i++) { |
1680 | enic_busy_poll_init_lock(&enic->rq[i]); | |
717258ba | 1681 | napi_enable(&enic->napi[i]); |
14747cd9 | 1682 | } |
4cfe8785 GV |
1683 | if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) |
1684 | for (i = 0; i < enic->wq_count; i++) | |
1685 | napi_enable(&enic->napi[enic_cq_wq(enic, i)]); | |
383ab92f | 1686 | enic_dev_enable(enic); |
01f2e4ea SF |
1687 | |
1688 | for (i = 0; i < enic->intr_count; i++) | |
1689 | vnic_intr_unmask(&enic->intr[i]); | |
1690 | ||
1691 | enic_notify_timer_start(enic); | |
a145df23 | 1692 | enic_rfs_flw_tbl_init(enic); |
01f2e4ea SF |
1693 | |
1694 | return 0; | |
4b75a442 | 1695 | |
9dac6232 GV |
1696 | err_out_free_rq: |
1697 | for (i = 0; i < enic->rq_count; i++) | |
1698 | vnic_rq_clean(&enic->rq[i], enic_free_rq_buf); | |
383ab92f | 1699 | enic_dev_notify_unset(enic); |
4b75a442 SF |
1700 | err_out_free_intr: |
1701 | enic_free_intr(enic); | |
1702 | ||
1703 | return err; | |
01f2e4ea SF |
1704 | } |
1705 | ||
1706 | /* rtnl lock is held, process context */ | |
1707 | static int enic_stop(struct net_device *netdev) | |
1708 | { | |
1709 | struct enic *enic = netdev_priv(netdev); | |
1710 | unsigned int i; | |
1711 | int err; | |
1712 | ||
29046f9b | 1713 | for (i = 0; i < enic->intr_count; i++) { |
b3d18d19 | 1714 | vnic_intr_mask(&enic->intr[i]); |
29046f9b VK |
1715 | (void)vnic_intr_masked(&enic->intr[i]); /* flush write */ |
1716 | } | |
b3d18d19 SF |
1717 | |
1718 | enic_synchronize_irqs(enic); | |
1719 | ||
01f2e4ea | 1720 | del_timer_sync(&enic->notify_timer); |
a145df23 | 1721 | enic_rfs_flw_tbl_free(enic); |
01f2e4ea | 1722 | |
383ab92f | 1723 | enic_dev_disable(enic); |
717258ba | 1724 | |
14747cd9 | 1725 | for (i = 0; i < enic->rq_count; i++) { |
717258ba | 1726 | napi_disable(&enic->napi[i]); |
39dc90c1 | 1727 | local_bh_disable(); |
14747cd9 GV |
1728 | while (!enic_poll_lock_napi(&enic->rq[i])) |
1729 | mdelay(1); | |
39dc90c1 | 1730 | local_bh_enable(); |
14747cd9 | 1731 | } |
717258ba | 1732 | |
b3d18d19 SF |
1733 | netif_carrier_off(netdev); |
1734 | netif_tx_disable(netdev); | |
4cfe8785 GV |
1735 | if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) |
1736 | for (i = 0; i < enic->wq_count; i++) | |
1737 | napi_disable(&enic->napi[enic_cq_wq(enic, i)]); | |
3f192795 | 1738 | |
7335903c | 1739 | if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic)) |
29639059 | 1740 | enic_dev_del_station_addr(enic); |
f8bd9091 | 1741 | |
01f2e4ea SF |
1742 | for (i = 0; i < enic->wq_count; i++) { |
1743 | err = vnic_wq_disable(&enic->wq[i]); | |
1744 | if (err) | |
1745 | return err; | |
1746 | } | |
1747 | for (i = 0; i < enic->rq_count; i++) { | |
1748 | err = vnic_rq_disable(&enic->rq[i]); | |
1749 | if (err) | |
1750 | return err; | |
1751 | } | |
1752 | ||
383ab92f | 1753 | enic_dev_notify_unset(enic); |
4b75a442 SF |
1754 | enic_free_intr(enic); |
1755 | ||
01f2e4ea SF |
1756 | for (i = 0; i < enic->wq_count; i++) |
1757 | vnic_wq_clean(&enic->wq[i], enic_free_wq_buf); | |
1758 | for (i = 0; i < enic->rq_count; i++) | |
1759 | vnic_rq_clean(&enic->rq[i], enic_free_rq_buf); | |
1760 | for (i = 0; i < enic->cq_count; i++) | |
1761 | vnic_cq_clean(&enic->cq[i]); | |
1762 | for (i = 0; i < enic->intr_count; i++) | |
1763 | vnic_intr_clean(&enic->intr[i]); | |
1764 | ||
1765 | return 0; | |
1766 | } | |
1767 | ||
1768 | static int enic_change_mtu(struct net_device *netdev, int new_mtu) | |
1769 | { | |
1770 | struct enic *enic = netdev_priv(netdev); | |
1771 | int running = netif_running(netdev); | |
1772 | ||
25f0a061 SF |
1773 | if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU) |
1774 | return -EINVAL; | |
1775 | ||
7335903c | 1776 | if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) |
c97c894d RP |
1777 | return -EOPNOTSUPP; |
1778 | ||
01f2e4ea SF |
1779 | if (running) |
1780 | enic_stop(netdev); | |
1781 | ||
01f2e4ea SF |
1782 | netdev->mtu = new_mtu; |
1783 | ||
1784 | if (netdev->mtu > enic->port_mtu) | |
a7a79deb VK |
1785 | netdev_warn(netdev, |
1786 | "interface MTU (%d) set higher than port MTU (%d)\n", | |
1787 | netdev->mtu, enic->port_mtu); | |
01f2e4ea SF |
1788 | |
1789 | if (running) | |
1790 | enic_open(netdev); | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | ||
c97c894d RP |
1795 | static void enic_change_mtu_work(struct work_struct *work) |
1796 | { | |
1797 | struct enic *enic = container_of(work, struct enic, change_mtu_work); | |
1798 | struct net_device *netdev = enic->netdev; | |
1799 | int new_mtu = vnic_dev_mtu(enic->vdev); | |
1800 | int err; | |
1801 | unsigned int i; | |
1802 | ||
1803 | new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu)); | |
1804 | ||
1805 | rtnl_lock(); | |
1806 | ||
1807 | /* Stop RQ */ | |
1808 | del_timer_sync(&enic->notify_timer); | |
1809 | ||
1810 | for (i = 0; i < enic->rq_count; i++) | |
1811 | napi_disable(&enic->napi[i]); | |
1812 | ||
1813 | vnic_intr_mask(&enic->intr[0]); | |
1814 | enic_synchronize_irqs(enic); | |
1815 | err = vnic_rq_disable(&enic->rq[0]); | |
1816 | if (err) { | |
e057590b | 1817 | rtnl_unlock(); |
c97c894d RP |
1818 | netdev_err(netdev, "Unable to disable RQ.\n"); |
1819 | return; | |
1820 | } | |
1821 | vnic_rq_clean(&enic->rq[0], enic_free_rq_buf); | |
1822 | vnic_cq_clean(&enic->cq[0]); | |
1823 | vnic_intr_clean(&enic->intr[0]); | |
1824 | ||
1825 | /* Fill RQ with new_mtu-sized buffers */ | |
1826 | netdev->mtu = new_mtu; | |
1827 | vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf); | |
1828 | /* Need at least one buffer on ring to get going */ | |
1829 | if (vnic_rq_desc_used(&enic->rq[0]) == 0) { | |
e057590b | 1830 | rtnl_unlock(); |
c97c894d RP |
1831 | netdev_err(netdev, "Unable to alloc receive buffers.\n"); |
1832 | return; | |
1833 | } | |
1834 | ||
1835 | /* Start RQ */ | |
1836 | vnic_rq_enable(&enic->rq[0]); | |
1837 | napi_enable(&enic->napi[0]); | |
1838 | vnic_intr_unmask(&enic->intr[0]); | |
1839 | enic_notify_timer_start(enic); | |
1840 | ||
1841 | rtnl_unlock(); | |
1842 | ||
1843 | netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu); | |
1844 | } | |
1845 | ||
01f2e4ea SF |
1846 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1847 | static void enic_poll_controller(struct net_device *netdev) | |
1848 | { | |
1849 | struct enic *enic = netdev_priv(netdev); | |
1850 | struct vnic_dev *vdev = enic->vdev; | |
717258ba | 1851 | unsigned int i, intr; |
01f2e4ea SF |
1852 | |
1853 | switch (vnic_dev_get_intr_mode(vdev)) { | |
1854 | case VNIC_DEV_INTR_MODE_MSIX: | |
717258ba VK |
1855 | for (i = 0; i < enic->rq_count; i++) { |
1856 | intr = enic_msix_rq_intr(enic, i); | |
4cfe8785 GV |
1857 | enic_isr_msix(enic->msix_entry[intr].vector, |
1858 | &enic->napi[i]); | |
717258ba | 1859 | } |
b880a954 VK |
1860 | |
1861 | for (i = 0; i < enic->wq_count; i++) { | |
1862 | intr = enic_msix_wq_intr(enic, i); | |
4cfe8785 GV |
1863 | enic_isr_msix(enic->msix_entry[intr].vector, |
1864 | &enic->napi[enic_cq_wq(enic, i)]); | |
b880a954 VK |
1865 | } |
1866 | ||
01f2e4ea SF |
1867 | break; |
1868 | case VNIC_DEV_INTR_MODE_MSI: | |
1869 | enic_isr_msi(enic->pdev->irq, enic); | |
1870 | break; | |
1871 | case VNIC_DEV_INTR_MODE_INTX: | |
1872 | enic_isr_legacy(enic->pdev->irq, netdev); | |
1873 | break; | |
1874 | default: | |
1875 | break; | |
1876 | } | |
1877 | } | |
1878 | #endif | |
1879 | ||
1880 | static int enic_dev_wait(struct vnic_dev *vdev, | |
1881 | int (*start)(struct vnic_dev *, int), | |
1882 | int (*finished)(struct vnic_dev *, int *), | |
1883 | int arg) | |
1884 | { | |
1885 | unsigned long time; | |
1886 | int done; | |
1887 | int err; | |
1888 | ||
1889 | BUG_ON(in_interrupt()); | |
1890 | ||
1891 | err = start(vdev, arg); | |
1892 | if (err) | |
1893 | return err; | |
1894 | ||
1895 | /* Wait for func to complete...2 seconds max | |
1896 | */ | |
1897 | ||
1898 | time = jiffies + (HZ * 2); | |
1899 | do { | |
1900 | ||
1901 | err = finished(vdev, &done); | |
1902 | if (err) | |
1903 | return err; | |
1904 | ||
1905 | if (done) | |
1906 | return 0; | |
1907 | ||
1908 | schedule_timeout_uninterruptible(HZ / 10); | |
1909 | ||
1910 | } while (time_after(time, jiffies)); | |
1911 | ||
1912 | return -ETIMEDOUT; | |
1913 | } | |
1914 | ||
1915 | static int enic_dev_open(struct enic *enic) | |
1916 | { | |
1917 | int err; | |
1918 | ||
1919 | err = enic_dev_wait(enic->vdev, vnic_dev_open, | |
1920 | vnic_dev_open_done, 0); | |
1921 | if (err) | |
a7a79deb VK |
1922 | dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n", |
1923 | err); | |
01f2e4ea SF |
1924 | |
1925 | return err; | |
1926 | } | |
1927 | ||
99ef5639 | 1928 | static int enic_dev_hang_reset(struct enic *enic) |
01f2e4ea SF |
1929 | { |
1930 | int err; | |
1931 | ||
99ef5639 VK |
1932 | err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset, |
1933 | vnic_dev_hang_reset_done, 0); | |
01f2e4ea | 1934 | if (err) |
a7a79deb VK |
1935 | netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n", |
1936 | err); | |
01f2e4ea SF |
1937 | |
1938 | return err; | |
1939 | } | |
1940 | ||
4f675eb2 | 1941 | int __enic_set_rsskey(struct enic *enic) |
717258ba | 1942 | { |
c33d23c2 | 1943 | union vnic_rss_key *rss_key_buf_va; |
1f4f067f | 1944 | dma_addr_t rss_key_buf_pa; |
c33d23c2 | 1945 | int i, kidx, bidx, err; |
717258ba | 1946 | |
c33d23c2 ED |
1947 | rss_key_buf_va = pci_zalloc_consistent(enic->pdev, |
1948 | sizeof(union vnic_rss_key), | |
1949 | &rss_key_buf_pa); | |
717258ba VK |
1950 | if (!rss_key_buf_va) |
1951 | return -ENOMEM; | |
1952 | ||
c33d23c2 ED |
1953 | for (i = 0; i < ENIC_RSS_LEN; i++) { |
1954 | kidx = i / ENIC_RSS_BYTES_PER_KEY; | |
1955 | bidx = i % ENIC_RSS_BYTES_PER_KEY; | |
4f675eb2 | 1956 | rss_key_buf_va->key[kidx].b[bidx] = enic->rss_key[i]; |
c33d23c2 | 1957 | } |
8e091340 | 1958 | spin_lock_bh(&enic->devcmd_lock); |
717258ba VK |
1959 | err = enic_set_rss_key(enic, |
1960 | rss_key_buf_pa, | |
1961 | sizeof(union vnic_rss_key)); | |
8e091340 | 1962 | spin_unlock_bh(&enic->devcmd_lock); |
717258ba VK |
1963 | |
1964 | pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key), | |
1965 | rss_key_buf_va, rss_key_buf_pa); | |
1966 | ||
1967 | return err; | |
1968 | } | |
1969 | ||
4f675eb2 GV |
1970 | static int enic_set_rsskey(struct enic *enic) |
1971 | { | |
1972 | netdev_rss_key_fill(enic->rss_key, ENIC_RSS_LEN); | |
1973 | ||
1974 | return __enic_set_rsskey(enic); | |
1975 | } | |
1976 | ||
717258ba VK |
1977 | static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits) |
1978 | { | |
1f4f067f | 1979 | dma_addr_t rss_cpu_buf_pa; |
717258ba VK |
1980 | union vnic_rss_cpu *rss_cpu_buf_va = NULL; |
1981 | unsigned int i; | |
1982 | int err; | |
1983 | ||
1984 | rss_cpu_buf_va = pci_alloc_consistent(enic->pdev, | |
1985 | sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa); | |
1986 | if (!rss_cpu_buf_va) | |
1987 | return -ENOMEM; | |
1988 | ||
1989 | for (i = 0; i < (1 << rss_hash_bits); i++) | |
1990 | (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count; | |
1991 | ||
8e091340 | 1992 | spin_lock_bh(&enic->devcmd_lock); |
717258ba VK |
1993 | err = enic_set_rss_cpu(enic, |
1994 | rss_cpu_buf_pa, | |
1995 | sizeof(union vnic_rss_cpu)); | |
8e091340 | 1996 | spin_unlock_bh(&enic->devcmd_lock); |
717258ba VK |
1997 | |
1998 | pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu), | |
1999 | rss_cpu_buf_va, rss_cpu_buf_pa); | |
2000 | ||
2001 | return err; | |
2002 | } | |
2003 | ||
2004 | static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu, | |
2005 | u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable) | |
68f71708 | 2006 | { |
68f71708 SF |
2007 | const u8 tso_ipid_split_en = 0; |
2008 | const u8 ig_vlan_strip_en = 1; | |
383ab92f | 2009 | int err; |
68f71708 | 2010 | |
717258ba VK |
2011 | /* Enable VLAN tag stripping. |
2012 | */ | |
68f71708 | 2013 | |
8e091340 | 2014 | spin_lock_bh(&enic->devcmd_lock); |
383ab92f | 2015 | err = enic_set_nic_cfg(enic, |
68f71708 SF |
2016 | rss_default_cpu, rss_hash_type, |
2017 | rss_hash_bits, rss_base_cpu, | |
2018 | rss_enable, tso_ipid_split_en, | |
2019 | ig_vlan_strip_en); | |
8e091340 | 2020 | spin_unlock_bh(&enic->devcmd_lock); |
383ab92f VK |
2021 | |
2022 | return err; | |
2023 | } | |
2024 | ||
717258ba VK |
2025 | static int enic_set_rss_nic_cfg(struct enic *enic) |
2026 | { | |
2027 | struct device *dev = enic_get_dev(enic); | |
2028 | const u8 rss_default_cpu = 0; | |
2029 | const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 | | |
2030 | NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 | | |
2031 | NIC_CFG_RSS_HASH_TYPE_IPV6 | | |
2032 | NIC_CFG_RSS_HASH_TYPE_TCP_IPV6; | |
2033 | const u8 rss_hash_bits = 7; | |
2034 | const u8 rss_base_cpu = 0; | |
2035 | u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1); | |
2036 | ||
2037 | if (rss_enable) { | |
2038 | if (!enic_set_rsskey(enic)) { | |
2039 | if (enic_set_rsscpu(enic, rss_hash_bits)) { | |
2040 | rss_enable = 0; | |
2041 | dev_warn(dev, "RSS disabled, " | |
2042 | "Failed to set RSS cpu indirection table."); | |
2043 | } | |
2044 | } else { | |
2045 | rss_enable = 0; | |
2046 | dev_warn(dev, "RSS disabled, Failed to set RSS key.\n"); | |
2047 | } | |
2048 | } | |
2049 | ||
2050 | return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type, | |
2051 | rss_hash_bits, rss_base_cpu, rss_enable); | |
f8cac14a VK |
2052 | } |
2053 | ||
01f2e4ea SF |
2054 | static void enic_reset(struct work_struct *work) |
2055 | { | |
2056 | struct enic *enic = container_of(work, struct enic, reset); | |
2057 | ||
2058 | if (!netif_running(enic->netdev)) | |
2059 | return; | |
2060 | ||
2061 | rtnl_lock(); | |
2062 | ||
0b038566 | 2063 | spin_lock(&enic->enic_api_lock); |
383ab92f | 2064 | enic_dev_hang_notify(enic); |
01f2e4ea | 2065 | enic_stop(enic->netdev); |
99ef5639 | 2066 | enic_dev_hang_reset(enic); |
e0afe53f | 2067 | enic_reset_addr_lists(enic); |
01f2e4ea | 2068 | enic_init_vnic_resources(enic); |
717258ba | 2069 | enic_set_rss_nic_cfg(enic); |
f8cac14a | 2070 | enic_dev_set_ig_vlan_rewrite_mode(enic); |
01f2e4ea | 2071 | enic_open(enic->netdev); |
0b038566 | 2072 | spin_unlock(&enic->enic_api_lock); |
d765bb41 | 2073 | call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev); |
01f2e4ea SF |
2074 | |
2075 | rtnl_unlock(); | |
2076 | } | |
2077 | ||
2078 | static int enic_set_intr_mode(struct enic *enic) | |
2079 | { | |
717258ba | 2080 | unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX); |
1cbb1a61 | 2081 | unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX); |
01f2e4ea SF |
2082 | unsigned int i; |
2083 | ||
2084 | /* Set interrupt mode (INTx, MSI, MSI-X) depending | |
717258ba | 2085 | * on system capabilities. |
01f2e4ea SF |
2086 | * |
2087 | * Try MSI-X first | |
2088 | * | |
2089 | * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs | |
2090 | * (the second to last INTR is used for WQ/RQ errors) | |
2091 | * (the last INTR is used for notifications) | |
2092 | */ | |
2093 | ||
2094 | BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2); | |
2095 | for (i = 0; i < n + m + 2; i++) | |
2096 | enic->msix_entry[i].entry = i; | |
2097 | ||
717258ba VK |
2098 | /* Use multiple RQs if RSS is enabled |
2099 | */ | |
2100 | ||
2101 | if (ENIC_SETTING(enic, RSS) && | |
2102 | enic->config.intr_mode < 1 && | |
01f2e4ea SF |
2103 | enic->rq_count >= n && |
2104 | enic->wq_count >= m && | |
2105 | enic->cq_count >= n + m && | |
717258ba | 2106 | enic->intr_count >= n + m + 2) { |
01f2e4ea | 2107 | |
abbb6a37 AG |
2108 | if (pci_enable_msix_range(enic->pdev, enic->msix_entry, |
2109 | n + m + 2, n + m + 2) > 0) { | |
01f2e4ea | 2110 | |
717258ba VK |
2111 | enic->rq_count = n; |
2112 | enic->wq_count = m; | |
2113 | enic->cq_count = n + m; | |
2114 | enic->intr_count = n + m + 2; | |
01f2e4ea | 2115 | |
717258ba VK |
2116 | vnic_dev_set_intr_mode(enic->vdev, |
2117 | VNIC_DEV_INTR_MODE_MSIX); | |
2118 | ||
2119 | return 0; | |
2120 | } | |
2121 | } | |
2122 | ||
2123 | if (enic->config.intr_mode < 1 && | |
2124 | enic->rq_count >= 1 && | |
2125 | enic->wq_count >= m && | |
2126 | enic->cq_count >= 1 + m && | |
2127 | enic->intr_count >= 1 + m + 2) { | |
abbb6a37 AG |
2128 | if (pci_enable_msix_range(enic->pdev, enic->msix_entry, |
2129 | 1 + m + 2, 1 + m + 2) > 0) { | |
717258ba VK |
2130 | |
2131 | enic->rq_count = 1; | |
2132 | enic->wq_count = m; | |
2133 | enic->cq_count = 1 + m; | |
2134 | enic->intr_count = 1 + m + 2; | |
2135 | ||
2136 | vnic_dev_set_intr_mode(enic->vdev, | |
2137 | VNIC_DEV_INTR_MODE_MSIX); | |
2138 | ||
2139 | return 0; | |
2140 | } | |
01f2e4ea SF |
2141 | } |
2142 | ||
2143 | /* Next try MSI | |
2144 | * | |
2145 | * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR | |
2146 | */ | |
2147 | ||
2148 | if (enic->config.intr_mode < 2 && | |
2149 | enic->rq_count >= 1 && | |
2150 | enic->wq_count >= 1 && | |
2151 | enic->cq_count >= 2 && | |
2152 | enic->intr_count >= 1 && | |
2153 | !pci_enable_msi(enic->pdev)) { | |
2154 | ||
2155 | enic->rq_count = 1; | |
2156 | enic->wq_count = 1; | |
2157 | enic->cq_count = 2; | |
2158 | enic->intr_count = 1; | |
2159 | ||
2160 | vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI); | |
2161 | ||
2162 | return 0; | |
2163 | } | |
2164 | ||
2165 | /* Next try INTx | |
2166 | * | |
2167 | * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs | |
2168 | * (the first INTR is used for WQ/RQ) | |
2169 | * (the second INTR is used for WQ/RQ errors) | |
2170 | * (the last INTR is used for notifications) | |
2171 | */ | |
2172 | ||
2173 | if (enic->config.intr_mode < 3 && | |
2174 | enic->rq_count >= 1 && | |
2175 | enic->wq_count >= 1 && | |
2176 | enic->cq_count >= 2 && | |
2177 | enic->intr_count >= 3) { | |
2178 | ||
2179 | enic->rq_count = 1; | |
2180 | enic->wq_count = 1; | |
2181 | enic->cq_count = 2; | |
2182 | enic->intr_count = 3; | |
2183 | ||
2184 | vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX); | |
2185 | ||
2186 | return 0; | |
2187 | } | |
2188 | ||
2189 | vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN); | |
2190 | ||
2191 | return -EINVAL; | |
2192 | } | |
2193 | ||
2194 | static void enic_clear_intr_mode(struct enic *enic) | |
2195 | { | |
2196 | switch (vnic_dev_get_intr_mode(enic->vdev)) { | |
2197 | case VNIC_DEV_INTR_MODE_MSIX: | |
2198 | pci_disable_msix(enic->pdev); | |
2199 | break; | |
2200 | case VNIC_DEV_INTR_MODE_MSI: | |
2201 | pci_disable_msi(enic->pdev); | |
2202 | break; | |
2203 | default: | |
2204 | break; | |
2205 | } | |
2206 | ||
2207 | vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN); | |
2208 | } | |
2209 | ||
f8bd9091 SF |
2210 | static const struct net_device_ops enic_netdev_dynamic_ops = { |
2211 | .ndo_open = enic_open, | |
2212 | .ndo_stop = enic_stop, | |
2213 | .ndo_start_xmit = enic_hard_start_xmit, | |
f20530bc | 2214 | .ndo_get_stats64 = enic_get_stats, |
f8bd9091 | 2215 | .ndo_validate_addr = eth_validate_addr, |
319d7e84 | 2216 | .ndo_set_rx_mode = enic_set_rx_mode, |
f8bd9091 SF |
2217 | .ndo_set_mac_address = enic_set_mac_address_dynamic, |
2218 | .ndo_change_mtu = enic_change_mtu, | |
f8bd9091 SF |
2219 | .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid, |
2220 | .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid, | |
2221 | .ndo_tx_timeout = enic_tx_timeout, | |
2222 | .ndo_set_vf_port = enic_set_vf_port, | |
2223 | .ndo_get_vf_port = enic_get_vf_port, | |
0b1c00fc | 2224 | .ndo_set_vf_mac = enic_set_vf_mac, |
f8bd9091 SF |
2225 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2226 | .ndo_poll_controller = enic_poll_controller, | |
2227 | #endif | |
a145df23 GV |
2228 | #ifdef CONFIG_RFS_ACCEL |
2229 | .ndo_rx_flow_steer = enic_rx_flow_steer, | |
2230 | #endif | |
14747cd9 GV |
2231 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2232 | .ndo_busy_poll = enic_busy_poll, | |
2233 | #endif | |
f8bd9091 SF |
2234 | }; |
2235 | ||
afe29f7a SH |
2236 | static const struct net_device_ops enic_netdev_ops = { |
2237 | .ndo_open = enic_open, | |
2238 | .ndo_stop = enic_stop, | |
00829823 | 2239 | .ndo_start_xmit = enic_hard_start_xmit, |
f20530bc | 2240 | .ndo_get_stats64 = enic_get_stats, |
afe29f7a | 2241 | .ndo_validate_addr = eth_validate_addr, |
f8bd9091 | 2242 | .ndo_set_mac_address = enic_set_mac_address, |
319d7e84 | 2243 | .ndo_set_rx_mode = enic_set_rx_mode, |
afe29f7a | 2244 | .ndo_change_mtu = enic_change_mtu, |
afe29f7a SH |
2245 | .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid, |
2246 | .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid, | |
2247 | .ndo_tx_timeout = enic_tx_timeout, | |
3f192795 RP |
2248 | .ndo_set_vf_port = enic_set_vf_port, |
2249 | .ndo_get_vf_port = enic_get_vf_port, | |
2250 | .ndo_set_vf_mac = enic_set_vf_mac, | |
afe29f7a SH |
2251 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2252 | .ndo_poll_controller = enic_poll_controller, | |
2253 | #endif | |
a145df23 GV |
2254 | #ifdef CONFIG_RFS_ACCEL |
2255 | .ndo_rx_flow_steer = enic_rx_flow_steer, | |
2256 | #endif | |
14747cd9 GV |
2257 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2258 | .ndo_busy_poll = enic_busy_poll, | |
2259 | #endif | |
afe29f7a SH |
2260 | }; |
2261 | ||
2fdba388 | 2262 | static void enic_dev_deinit(struct enic *enic) |
6fdfa970 | 2263 | { |
717258ba VK |
2264 | unsigned int i; |
2265 | ||
14747cd9 GV |
2266 | for (i = 0; i < enic->rq_count; i++) { |
2267 | napi_hash_del(&enic->napi[i]); | |
717258ba | 2268 | netif_napi_del(&enic->napi[i]); |
14747cd9 | 2269 | } |
4cfe8785 GV |
2270 | if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) |
2271 | for (i = 0; i < enic->wq_count; i++) | |
2272 | netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]); | |
717258ba | 2273 | |
6fdfa970 SF |
2274 | enic_free_vnic_resources(enic); |
2275 | enic_clear_intr_mode(enic); | |
2276 | } | |
2277 | ||
3f255dcc GV |
2278 | static void enic_kdump_kernel_config(struct enic *enic) |
2279 | { | |
2280 | if (is_kdump_kernel()) { | |
2281 | dev_info(enic_get_dev(enic), "Running from within kdump kernel. Using minimal resources\n"); | |
2282 | enic->rq_count = 1; | |
2283 | enic->wq_count = 1; | |
2284 | enic->config.rq_desc_count = ENIC_MIN_RQ_DESCS; | |
2285 | enic->config.wq_desc_count = ENIC_MIN_WQ_DESCS; | |
2286 | enic->config.mtu = min_t(u16, 1500, enic->config.mtu); | |
2287 | } | |
2288 | } | |
2289 | ||
2fdba388 | 2290 | static int enic_dev_init(struct enic *enic) |
6fdfa970 | 2291 | { |
a7a79deb | 2292 | struct device *dev = enic_get_dev(enic); |
6fdfa970 | 2293 | struct net_device *netdev = enic->netdev; |
717258ba | 2294 | unsigned int i; |
6fdfa970 SF |
2295 | int err; |
2296 | ||
ea7ea65a VK |
2297 | /* Get interrupt coalesce timer info */ |
2298 | err = enic_dev_intr_coal_timer_info(enic); | |
2299 | if (err) { | |
2300 | dev_warn(dev, "Using default conversion factor for " | |
2301 | "interrupt coalesce timer\n"); | |
2302 | vnic_dev_intr_coal_timer_info_default(enic->vdev); | |
2303 | } | |
2304 | ||
6fdfa970 SF |
2305 | /* Get vNIC configuration |
2306 | */ | |
2307 | ||
2308 | err = enic_get_vnic_config(enic); | |
2309 | if (err) { | |
a7a79deb | 2310 | dev_err(dev, "Get vNIC configuration failed, aborting\n"); |
6fdfa970 SF |
2311 | return err; |
2312 | } | |
2313 | ||
2314 | /* Get available resource counts | |
2315 | */ | |
2316 | ||
2317 | enic_get_res_counts(enic); | |
2318 | ||
3f255dcc GV |
2319 | /* modify resource count if we are in kdump_kernel |
2320 | */ | |
2321 | enic_kdump_kernel_config(enic); | |
2322 | ||
6fdfa970 SF |
2323 | /* Set interrupt mode based on resource counts and system |
2324 | * capabilities | |
2325 | */ | |
2326 | ||
2327 | err = enic_set_intr_mode(enic); | |
2328 | if (err) { | |
a7a79deb VK |
2329 | dev_err(dev, "Failed to set intr mode based on resource " |
2330 | "counts and system capabilities, aborting\n"); | |
6fdfa970 SF |
2331 | return err; |
2332 | } | |
2333 | ||
2334 | /* Allocate and configure vNIC resources | |
2335 | */ | |
2336 | ||
2337 | err = enic_alloc_vnic_resources(enic); | |
2338 | if (err) { | |
a7a79deb | 2339 | dev_err(dev, "Failed to alloc vNIC resources, aborting\n"); |
6fdfa970 SF |
2340 | goto err_out_free_vnic_resources; |
2341 | } | |
2342 | ||
2343 | enic_init_vnic_resources(enic); | |
2344 | ||
717258ba | 2345 | err = enic_set_rss_nic_cfg(enic); |
6fdfa970 | 2346 | if (err) { |
a7a79deb | 2347 | dev_err(dev, "Failed to config nic, aborting\n"); |
6fdfa970 SF |
2348 | goto err_out_free_vnic_resources; |
2349 | } | |
2350 | ||
2351 | switch (vnic_dev_get_intr_mode(enic->vdev)) { | |
2352 | default: | |
717258ba | 2353 | netif_napi_add(netdev, &enic->napi[0], enic_poll, 64); |
14747cd9 | 2354 | napi_hash_add(&enic->napi[0]); |
6fdfa970 SF |
2355 | break; |
2356 | case VNIC_DEV_INTR_MODE_MSIX: | |
14747cd9 | 2357 | for (i = 0; i < enic->rq_count; i++) { |
717258ba | 2358 | netif_napi_add(netdev, &enic->napi[i], |
4cfe8785 | 2359 | enic_poll_msix_rq, NAPI_POLL_WEIGHT); |
14747cd9 GV |
2360 | napi_hash_add(&enic->napi[i]); |
2361 | } | |
4cfe8785 GV |
2362 | for (i = 0; i < enic->wq_count; i++) |
2363 | netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)], | |
2364 | enic_poll_msix_wq, NAPI_POLL_WEIGHT); | |
6fdfa970 SF |
2365 | break; |
2366 | } | |
2367 | ||
2368 | return 0; | |
2369 | ||
2370 | err_out_free_vnic_resources: | |
2371 | enic_clear_intr_mode(enic); | |
2372 | enic_free_vnic_resources(enic); | |
2373 | ||
2374 | return err; | |
2375 | } | |
2376 | ||
27e6c7d3 SF |
2377 | static void enic_iounmap(struct enic *enic) |
2378 | { | |
2379 | unsigned int i; | |
2380 | ||
2381 | for (i = 0; i < ARRAY_SIZE(enic->bar); i++) | |
2382 | if (enic->bar[i].vaddr) | |
2383 | iounmap(enic->bar[i].vaddr); | |
2384 | } | |
2385 | ||
1dd06ae8 | 2386 | static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
01f2e4ea | 2387 | { |
a7a79deb | 2388 | struct device *dev = &pdev->dev; |
01f2e4ea SF |
2389 | struct net_device *netdev; |
2390 | struct enic *enic; | |
2391 | int using_dac = 0; | |
2392 | unsigned int i; | |
2393 | int err; | |
8749b427 RP |
2394 | #ifdef CONFIG_PCI_IOV |
2395 | int pos = 0; | |
2396 | #endif | |
b67f231d | 2397 | int num_pps = 1; |
01f2e4ea | 2398 | |
01f2e4ea SF |
2399 | /* Allocate net device structure and initialize. Private |
2400 | * instance data is initialized to zero. | |
2401 | */ | |
2402 | ||
822473b6 | 2403 | netdev = alloc_etherdev_mqs(sizeof(struct enic), |
2404 | ENIC_RQ_MAX, ENIC_WQ_MAX); | |
41de8d4c | 2405 | if (!netdev) |
01f2e4ea | 2406 | return -ENOMEM; |
01f2e4ea | 2407 | |
01f2e4ea SF |
2408 | pci_set_drvdata(pdev, netdev); |
2409 | ||
2410 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
2411 | ||
2412 | enic = netdev_priv(netdev); | |
2413 | enic->netdev = netdev; | |
2414 | enic->pdev = pdev; | |
2415 | ||
2416 | /* Setup PCI resources | |
2417 | */ | |
2418 | ||
29046f9b | 2419 | err = pci_enable_device_mem(pdev); |
01f2e4ea | 2420 | if (err) { |
a7a79deb | 2421 | dev_err(dev, "Cannot enable PCI device, aborting\n"); |
01f2e4ea SF |
2422 | goto err_out_free_netdev; |
2423 | } | |
2424 | ||
2425 | err = pci_request_regions(pdev, DRV_NAME); | |
2426 | if (err) { | |
a7a79deb | 2427 | dev_err(dev, "Cannot request PCI regions, aborting\n"); |
01f2e4ea SF |
2428 | goto err_out_disable_device; |
2429 | } | |
2430 | ||
2431 | pci_set_master(pdev); | |
2432 | ||
2433 | /* Query PCI controller on system for DMA addressing | |
624dbf55 | 2434 | * limitation for the device. Try 64-bit first, and |
01f2e4ea SF |
2435 | * fail to 32-bit. |
2436 | */ | |
2437 | ||
624dbf55 | 2438 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
01f2e4ea | 2439 | if (err) { |
284901a9 | 2440 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
01f2e4ea | 2441 | if (err) { |
a7a79deb | 2442 | dev_err(dev, "No usable DMA configuration, aborting\n"); |
01f2e4ea SF |
2443 | goto err_out_release_regions; |
2444 | } | |
284901a9 | 2445 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
01f2e4ea | 2446 | if (err) { |
a7a79deb VK |
2447 | dev_err(dev, "Unable to obtain %u-bit DMA " |
2448 | "for consistent allocations, aborting\n", 32); | |
01f2e4ea SF |
2449 | goto err_out_release_regions; |
2450 | } | |
2451 | } else { | |
624dbf55 | 2452 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
01f2e4ea | 2453 | if (err) { |
a7a79deb | 2454 | dev_err(dev, "Unable to obtain %u-bit DMA " |
624dbf55 | 2455 | "for consistent allocations, aborting\n", 64); |
01f2e4ea SF |
2456 | goto err_out_release_regions; |
2457 | } | |
2458 | using_dac = 1; | |
2459 | } | |
2460 | ||
27e6c7d3 | 2461 | /* Map vNIC resources from BAR0-5 |
01f2e4ea SF |
2462 | */ |
2463 | ||
27e6c7d3 SF |
2464 | for (i = 0; i < ARRAY_SIZE(enic->bar); i++) { |
2465 | if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM)) | |
2466 | continue; | |
2467 | enic->bar[i].len = pci_resource_len(pdev, i); | |
2468 | enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len); | |
2469 | if (!enic->bar[i].vaddr) { | |
a7a79deb | 2470 | dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i); |
27e6c7d3 SF |
2471 | err = -ENODEV; |
2472 | goto err_out_iounmap; | |
2473 | } | |
2474 | enic->bar[i].bus_addr = pci_resource_start(pdev, i); | |
01f2e4ea SF |
2475 | } |
2476 | ||
2477 | /* Register vNIC device | |
2478 | */ | |
2479 | ||
27e6c7d3 SF |
2480 | enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar, |
2481 | ARRAY_SIZE(enic->bar)); | |
01f2e4ea | 2482 | if (!enic->vdev) { |
a7a79deb | 2483 | dev_err(dev, "vNIC registration failed, aborting\n"); |
01f2e4ea SF |
2484 | err = -ENODEV; |
2485 | goto err_out_iounmap; | |
2486 | } | |
2487 | ||
8749b427 RP |
2488 | #ifdef CONFIG_PCI_IOV |
2489 | /* Get number of subvnics */ | |
2490 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); | |
2491 | if (pos) { | |
2492 | pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, | |
413708bb | 2493 | &enic->num_vfs); |
8749b427 RP |
2494 | if (enic->num_vfs) { |
2495 | err = pci_enable_sriov(pdev, enic->num_vfs); | |
2496 | if (err) { | |
2497 | dev_err(dev, "SRIOV enable failed, aborting." | |
2498 | " pci_enable_sriov() returned %d\n", | |
2499 | err); | |
2500 | goto err_out_vnic_unregister; | |
2501 | } | |
2502 | enic->priv_flags |= ENIC_SRIOV_ENABLED; | |
b67f231d | 2503 | num_pps = enic->num_vfs; |
8749b427 RP |
2504 | } |
2505 | } | |
8749b427 | 2506 | #endif |
ca2b721d | 2507 | |
3f192795 | 2508 | /* Allocate structure for port profiles */ |
a1de2219 | 2509 | enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL); |
3f192795 | 2510 | if (!enic->pp) { |
3f192795 | 2511 | err = -ENOMEM; |
ca2b721d | 2512 | goto err_out_disable_sriov_pp; |
3f192795 RP |
2513 | } |
2514 | ||
01f2e4ea SF |
2515 | /* Issue device open to get device in known state |
2516 | */ | |
2517 | ||
2518 | err = enic_dev_open(enic); | |
2519 | if (err) { | |
a7a79deb | 2520 | dev_err(dev, "vNIC dev open failed, aborting\n"); |
ca2b721d | 2521 | goto err_out_disable_sriov; |
01f2e4ea SF |
2522 | } |
2523 | ||
69161425 VK |
2524 | /* Setup devcmd lock |
2525 | */ | |
2526 | ||
2527 | spin_lock_init(&enic->devcmd_lock); | |
0b038566 | 2528 | spin_lock_init(&enic->enic_api_lock); |
69161425 VK |
2529 | |
2530 | /* | |
2531 | * Set ingress vlan rewrite mode before vnic initialization | |
2532 | */ | |
2533 | ||
2534 | err = enic_dev_set_ig_vlan_rewrite_mode(enic); | |
2535 | if (err) { | |
2536 | dev_err(dev, | |
2537 | "Failed to set ingress vlan rewrite mode, aborting.\n"); | |
2538 | goto err_out_dev_close; | |
2539 | } | |
2540 | ||
01f2e4ea SF |
2541 | /* Issue device init to initialize the vnic-to-switch link. |
2542 | * We'll start with carrier off and wait for link UP | |
2543 | * notification later to turn on carrier. We don't need | |
2544 | * to wait here for the vnic-to-switch link initialization | |
2545 | * to complete; link UP notification is the indication that | |
2546 | * the process is complete. | |
2547 | */ | |
2548 | ||
2549 | netif_carrier_off(netdev); | |
2550 | ||
a7a79deb VK |
2551 | /* Do not call dev_init for a dynamic vnic. |
2552 | * For a dynamic vnic, init_prov_info will be | |
2553 | * called later by an upper layer. | |
2554 | */ | |
2555 | ||
2b68c181 | 2556 | if (!enic_is_dynamic(enic)) { |
f8bd9091 SF |
2557 | err = vnic_dev_init(enic->vdev, 0); |
2558 | if (err) { | |
a7a79deb | 2559 | dev_err(dev, "vNIC dev init failed, aborting\n"); |
f8bd9091 SF |
2560 | goto err_out_dev_close; |
2561 | } | |
01f2e4ea SF |
2562 | } |
2563 | ||
6fdfa970 | 2564 | err = enic_dev_init(enic); |
01f2e4ea | 2565 | if (err) { |
a7a79deb | 2566 | dev_err(dev, "Device initialization failed, aborting\n"); |
01f2e4ea SF |
2567 | goto err_out_dev_close; |
2568 | } | |
2569 | ||
822473b6 | 2570 | netif_set_real_num_tx_queues(netdev, enic->wq_count); |
bf751ba8 | 2571 | netif_set_real_num_rx_queues(netdev, enic->rq_count); |
822473b6 | 2572 | |
383ab92f | 2573 | /* Setup notification timer, HW reset task, and wq locks |
01f2e4ea SF |
2574 | */ |
2575 | ||
2576 | init_timer(&enic->notify_timer); | |
2577 | enic->notify_timer.function = enic_notify_timer; | |
2578 | enic->notify_timer.data = (unsigned long)enic; | |
2579 | ||
7c2ce6e6 | 2580 | enic_set_rx_coal_setting(enic); |
01f2e4ea | 2581 | INIT_WORK(&enic->reset, enic_reset); |
c97c894d | 2582 | INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work); |
01f2e4ea SF |
2583 | |
2584 | for (i = 0; i < enic->wq_count; i++) | |
2585 | spin_lock_init(&enic->wq_lock[i]); | |
2586 | ||
01f2e4ea SF |
2587 | /* Register net device |
2588 | */ | |
2589 | ||
2590 | enic->port_mtu = enic->config.mtu; | |
2591 | (void)enic_change_mtu(netdev, enic->port_mtu); | |
2592 | ||
2593 | err = enic_set_mac_addr(netdev, enic->mac_addr); | |
2594 | if (err) { | |
a7a79deb | 2595 | dev_err(dev, "Invalid MAC address, aborting\n"); |
6fdfa970 | 2596 | goto err_out_dev_deinit; |
01f2e4ea SF |
2597 | } |
2598 | ||
7c844599 | 2599 | enic->tx_coalesce_usecs = enic->config.intr_timer_usec; |
7c2ce6e6 SS |
2600 | /* rx coalesce time already got initialized. This gets used |
2601 | * if adaptive coal is turned off | |
2602 | */ | |
7c844599 SF |
2603 | enic->rx_coalesce_usecs = enic->tx_coalesce_usecs; |
2604 | ||
7335903c | 2605 | if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) |
f8bd9091 SF |
2606 | netdev->netdev_ops = &enic_netdev_dynamic_ops; |
2607 | else | |
2608 | netdev->netdev_ops = &enic_netdev_ops; | |
2609 | ||
01f2e4ea | 2610 | netdev->watchdog_timeo = 2 * HZ; |
f13bbc2f | 2611 | enic_set_ethtool_ops(netdev); |
01f2e4ea | 2612 | |
f646968f | 2613 | netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
1825aca6 | 2614 | if (ENIC_SETTING(enic, LOOP)) { |
f646968f | 2615 | netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
1825aca6 VK |
2616 | enic->loop_enable = 1; |
2617 | enic->loop_tag = enic->config.loop_tag; | |
2618 | dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag); | |
2619 | } | |
01f2e4ea | 2620 | if (ENIC_SETTING(enic, TXCSUM)) |
5ec8f9b8 | 2621 | netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM; |
01f2e4ea | 2622 | if (ENIC_SETTING(enic, TSO)) |
5ec8f9b8 | 2623 | netdev->hw_features |= NETIF_F_TSO | |
01f2e4ea | 2624 | NETIF_F_TSO6 | NETIF_F_TSO_ECN; |
bf751ba8 | 2625 | if (ENIC_SETTING(enic, RSS)) |
2626 | netdev->hw_features |= NETIF_F_RXHASH; | |
5ec8f9b8 MM |
2627 | if (ENIC_SETTING(enic, RXCSUM)) |
2628 | netdev->hw_features |= NETIF_F_RXCSUM; | |
2629 | ||
2630 | netdev->features |= netdev->hw_features; | |
2631 | ||
a145df23 GV |
2632 | #ifdef CONFIG_RFS_ACCEL |
2633 | netdev->hw_features |= NETIF_F_NTUPLE; | |
2634 | #endif | |
2635 | ||
01f2e4ea SF |
2636 | if (using_dac) |
2637 | netdev->features |= NETIF_F_HIGHDMA; | |
2638 | ||
01789349 JP |
2639 | netdev->priv_flags |= IFF_UNICAST_FLT; |
2640 | ||
01f2e4ea SF |
2641 | err = register_netdev(netdev); |
2642 | if (err) { | |
a7a79deb | 2643 | dev_err(dev, "Cannot register net device, aborting\n"); |
6fdfa970 | 2644 | goto err_out_dev_deinit; |
01f2e4ea | 2645 | } |
a03bb56e | 2646 | enic->rx_copybreak = RX_COPYBREAK_DEFAULT; |
01f2e4ea SF |
2647 | |
2648 | return 0; | |
2649 | ||
6fdfa970 SF |
2650 | err_out_dev_deinit: |
2651 | enic_dev_deinit(enic); | |
01f2e4ea SF |
2652 | err_out_dev_close: |
2653 | vnic_dev_close(enic->vdev); | |
8749b427 | 2654 | err_out_disable_sriov: |
ca2b721d RP |
2655 | kfree(enic->pp); |
2656 | err_out_disable_sriov_pp: | |
8749b427 RP |
2657 | #ifdef CONFIG_PCI_IOV |
2658 | if (enic_sriov_enabled(enic)) { | |
2659 | pci_disable_sriov(pdev); | |
2660 | enic->priv_flags &= ~ENIC_SRIOV_ENABLED; | |
2661 | } | |
01f2e4ea | 2662 | err_out_vnic_unregister: |
8749b427 | 2663 | #endif |
35d87e33 | 2664 | vnic_dev_unregister(enic->vdev); |
01f2e4ea SF |
2665 | err_out_iounmap: |
2666 | enic_iounmap(enic); | |
2667 | err_out_release_regions: | |
2668 | pci_release_regions(pdev); | |
2669 | err_out_disable_device: | |
2670 | pci_disable_device(pdev); | |
2671 | err_out_free_netdev: | |
01f2e4ea SF |
2672 | free_netdev(netdev); |
2673 | ||
2674 | return err; | |
2675 | } | |
2676 | ||
854de92f | 2677 | static void enic_remove(struct pci_dev *pdev) |
01f2e4ea SF |
2678 | { |
2679 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2680 | ||
2681 | if (netdev) { | |
2682 | struct enic *enic = netdev_priv(netdev); | |
2683 | ||
23f333a2 | 2684 | cancel_work_sync(&enic->reset); |
c97c894d | 2685 | cancel_work_sync(&enic->change_mtu_work); |
01f2e4ea | 2686 | unregister_netdev(netdev); |
6fdfa970 | 2687 | enic_dev_deinit(enic); |
01f2e4ea | 2688 | vnic_dev_close(enic->vdev); |
8749b427 RP |
2689 | #ifdef CONFIG_PCI_IOV |
2690 | if (enic_sriov_enabled(enic)) { | |
2691 | pci_disable_sriov(pdev); | |
2692 | enic->priv_flags &= ~ENIC_SRIOV_ENABLED; | |
2693 | } | |
2694 | #endif | |
3f192795 | 2695 | kfree(enic->pp); |
01f2e4ea SF |
2696 | vnic_dev_unregister(enic->vdev); |
2697 | enic_iounmap(enic); | |
2698 | pci_release_regions(pdev); | |
2699 | pci_disable_device(pdev); | |
01f2e4ea SF |
2700 | free_netdev(netdev); |
2701 | } | |
2702 | } | |
2703 | ||
2704 | static struct pci_driver enic_driver = { | |
2705 | .name = DRV_NAME, | |
2706 | .id_table = enic_id_table, | |
2707 | .probe = enic_probe, | |
854de92f | 2708 | .remove = enic_remove, |
01f2e4ea SF |
2709 | }; |
2710 | ||
2711 | static int __init enic_init_module(void) | |
2712 | { | |
a7a79deb | 2713 | pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION); |
01f2e4ea SF |
2714 | |
2715 | return pci_register_driver(&enic_driver); | |
2716 | } | |
2717 | ||
2718 | static void __exit enic_cleanup_module(void) | |
2719 | { | |
2720 | pci_unregister_driver(&enic_driver); | |
2721 | } | |
2722 | ||
2723 | module_init(enic_init_module); | |
2724 | module_exit(enic_cleanup_module); |