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cxgb4vf: Use pci_enable_msix_range() instead of pci_enable_msix()
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / cisco / enic / enic_main.c
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01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF
27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF
32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
01f2e4ea
SF
41
42#include "cq_enet_desc.h"
43#include "vnic_dev.h"
44#include "vnic_intr.h"
45#include "vnic_stats.h"
f8bd9091 46#include "vnic_vic.h"
01f2e4ea
SF
47#include "enic_res.h"
48#include "enic.h"
51987461 49#include "enic_dev.h"
b3abfbd2 50#include "enic_pp.h"
01f2e4ea
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51
52#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
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53#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
54#define MAX_TSO (1 << 16)
55#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
56
57#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 58#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 59#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea
SF
60
61/* Supported devices */
a3aa1884 62static DEFINE_PCI_DEVICE_TABLE(enic_id_table) = {
ea0d7d91 63 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 64 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 65 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF
66 { 0, } /* end of table */
67};
68
69MODULE_DESCRIPTION(DRV_DESCRIPTION);
70MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
71MODULE_LICENSE("GPL");
72MODULE_VERSION(DRV_VERSION);
73MODULE_DEVICE_TABLE(pci, enic_id_table);
74
3f192795 75int enic_is_dynamic(struct enic *enic)
f8bd9091
SF
76{
77 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
78}
79
8749b427
RP
80int enic_sriov_enabled(struct enic *enic)
81{
82 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
83}
84
3a4adef5
RP
85static int enic_is_sriov_vf(struct enic *enic)
86{
87 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
88}
89
889d13f5
RP
90int enic_is_valid_vf(struct enic *enic, int vf)
91{
92#ifdef CONFIG_PCI_IOV
93 return vf >= 0 && vf < enic->num_vfs;
94#else
95 return 0;
96#endif
97}
98
01f2e4ea
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99static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
100{
101 struct enic *enic = vnic_dev_priv(wq->vdev);
102
103 if (buf->sop)
104 pci_unmap_single(enic->pdev, buf->dma_addr,
105 buf->len, PCI_DMA_TODEVICE);
106 else
107 pci_unmap_page(enic->pdev, buf->dma_addr,
108 buf->len, PCI_DMA_TODEVICE);
109
110 if (buf->os_buf)
111 dev_kfree_skb_any(buf->os_buf);
112}
113
114static void enic_wq_free_buf(struct vnic_wq *wq,
115 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
116{
117 enic_free_wq_buf(wq, buf);
118}
119
120static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
121 u8 type, u16 q_number, u16 completed_index, void *opaque)
122{
123 struct enic *enic = vnic_dev_priv(vdev);
124
125 spin_lock(&enic->wq_lock[q_number]);
126
127 vnic_wq_service(&enic->wq[q_number], cq_desc,
128 completed_index, enic_wq_free_buf,
129 opaque);
130
822473b6 131 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
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132 vnic_wq_desc_avail(&enic->wq[q_number]) >=
133 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 134 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF
135
136 spin_unlock(&enic->wq_lock[q_number]);
137
138 return 0;
139}
140
141static void enic_log_q_error(struct enic *enic)
142{
143 unsigned int i;
144 u32 error_status;
145
146 for (i = 0; i < enic->wq_count; i++) {
147 error_status = vnic_wq_error_status(&enic->wq[i]);
148 if (error_status)
a7a79deb
VK
149 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
150 i, error_status);
01f2e4ea
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151 }
152
153 for (i = 0; i < enic->rq_count; i++) {
154 error_status = vnic_rq_error_status(&enic->rq[i]);
155 if (error_status)
a7a79deb
VK
156 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
157 i, error_status);
01f2e4ea
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158 }
159}
160
383ab92f 161static void enic_msglvl_check(struct enic *enic)
01f2e4ea 162{
383ab92f 163 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 164
383ab92f 165 if (msg_enable != enic->msg_enable) {
a7a79deb
VK
166 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
167 enic->msg_enable, msg_enable);
383ab92f 168 enic->msg_enable = msg_enable;
01f2e4ea
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169 }
170}
171
172static void enic_mtu_check(struct enic *enic)
173{
174 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 175 struct net_device *netdev = enic->netdev;
01f2e4ea 176
491598a4 177 if (mtu && mtu != enic->port_mtu) {
7c844599 178 enic->port_mtu = mtu;
7335903c 179 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP
180 mtu = max_t(int, ENIC_MIN_MTU,
181 min_t(int, ENIC_MAX_MTU, mtu));
182 if (mtu != netdev->mtu)
183 schedule_work(&enic->change_mtu_work);
184 } else {
185 if (mtu < netdev->mtu)
186 netdev_warn(netdev,
187 "interface MTU (%d) set higher "
188 "than switch port MTU (%d)\n",
189 netdev->mtu, mtu);
190 }
01f2e4ea
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191 }
192}
193
383ab92f 194static void enic_link_check(struct enic *enic)
01f2e4ea 195{
383ab92f
VK
196 int link_status = vnic_dev_link_status(enic->vdev);
197 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 198
383ab92f 199 if (link_status && !carrier_ok) {
a7a79deb 200 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK
201 netif_carrier_on(enic->netdev);
202 } else if (!link_status && carrier_ok) {
a7a79deb 203 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 204 netif_carrier_off(enic->netdev);
01f2e4ea
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205 }
206}
207
208static void enic_notify_check(struct enic *enic)
209{
210 enic_msglvl_check(enic);
211 enic_mtu_check(enic);
212 enic_link_check(enic);
213}
214
215#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
216
217static irqreturn_t enic_isr_legacy(int irq, void *data)
218{
219 struct net_device *netdev = data;
220 struct enic *enic = netdev_priv(netdev);
717258ba
VK
221 unsigned int io_intr = enic_legacy_io_intr();
222 unsigned int err_intr = enic_legacy_err_intr();
223 unsigned int notify_intr = enic_legacy_notify_intr();
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224 u32 pba;
225
717258ba 226 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
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227
228 pba = vnic_intr_legacy_pba(enic->legacy_pba);
229 if (!pba) {
717258ba 230 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
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231 return IRQ_NONE; /* not our interrupt */
232 }
233
717258ba
VK
234 if (ENIC_TEST_INTR(pba, notify_intr)) {
235 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
01f2e4ea 236 enic_notify_check(enic);
ed8af6b2 237 }
01f2e4ea 238
717258ba
VK
239 if (ENIC_TEST_INTR(pba, err_intr)) {
240 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
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241 enic_log_q_error(enic);
242 /* schedule recovery from WQ/RQ error */
243 schedule_work(&enic->reset);
244 return IRQ_HANDLED;
245 }
246
717258ba
VK
247 if (ENIC_TEST_INTR(pba, io_intr)) {
248 if (napi_schedule_prep(&enic->napi[0]))
249 __napi_schedule(&enic->napi[0]);
01f2e4ea 250 } else {
717258ba 251 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF
252 }
253
254 return IRQ_HANDLED;
255}
256
257static irqreturn_t enic_isr_msi(int irq, void *data)
258{
259 struct enic *enic = data;
260
261 /* With MSI, there is no sharing of interrupts, so this is
262 * our interrupt and there is no need to ack it. The device
263 * is not providing per-vector masking, so the OS will not
264 * write to PCI config space to mask/unmask the interrupt.
265 * We're using mask_on_assertion for MSI, so the device
266 * automatically masks the interrupt when the interrupt is
267 * generated. Later, when exiting polling, the interrupt
268 * will be unmasked (see enic_poll).
269 *
270 * Also, the device uses the same PCIe Traffic Class (TC)
271 * for Memory Write data and MSI, so there are no ordering
272 * issues; the MSI will always arrive at the Root Complex
273 * _after_ corresponding Memory Writes (i.e. descriptor
274 * writes).
275 */
276
717258ba 277 napi_schedule(&enic->napi[0]);
01f2e4ea
SF
278
279 return IRQ_HANDLED;
280}
281
282static irqreturn_t enic_isr_msix_rq(int irq, void *data)
283{
717258ba 284 struct napi_struct *napi = data;
01f2e4ea
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285
286 /* schedule NAPI polling for RQ cleanup */
717258ba 287 napi_schedule(napi);
01f2e4ea
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288
289 return IRQ_HANDLED;
290}
291
292static irqreturn_t enic_isr_msix_wq(int irq, void *data)
293{
294 struct enic *enic = data;
822473b6 295 unsigned int cq;
296 unsigned int intr;
01f2e4ea
SF
297 unsigned int wq_work_to_do = -1; /* no limit */
298 unsigned int wq_work_done;
822473b6 299 unsigned int wq_irq;
300
301 wq_irq = (u32)irq - enic->msix_entry[enic_msix_wq_intr(enic, 0)].vector;
302 cq = enic_cq_wq(enic, wq_irq);
303 intr = enic_msix_wq_intr(enic, wq_irq);
01f2e4ea 304
717258ba 305 wq_work_done = vnic_cq_service(&enic->cq[cq],
01f2e4ea
SF
306 wq_work_to_do, enic_wq_service, NULL);
307
717258ba 308 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
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309 wq_work_done,
310 1 /* unmask intr */,
311 1 /* reset intr timer */);
312
313 return IRQ_HANDLED;
314}
315
316static irqreturn_t enic_isr_msix_err(int irq, void *data)
317{
318 struct enic *enic = data;
717258ba 319 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 320
717258ba 321 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 322
01f2e4ea
SF
323 enic_log_q_error(enic);
324
325 /* schedule recovery from WQ/RQ error */
326 schedule_work(&enic->reset);
327
328 return IRQ_HANDLED;
329}
330
331static irqreturn_t enic_isr_msix_notify(int irq, void *data)
332{
333 struct enic *enic = data;
717258ba 334 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea 335
717258ba 336 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea 337 enic_notify_check(enic);
01f2e4ea
SF
338
339 return IRQ_HANDLED;
340}
341
342static inline void enic_queue_wq_skb_cont(struct enic *enic,
343 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 344 unsigned int len_left, int loopback)
01f2e4ea 345{
9e903e08 346 const skb_frag_t *frag;
01f2e4ea
SF
347
348 /* Queue additional data fragments */
349 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 350 len_left -= skb_frag_size(frag);
01f2e4ea 351 enic_queue_wq_desc_cont(wq, skb,
4bf5adbf 352 skb_frag_dma_map(&enic->pdev->dev,
9e903e08 353 frag, 0, skb_frag_size(frag),
5d6bcdfe 354 DMA_TO_DEVICE),
9e903e08 355 skb_frag_size(frag),
1825aca6
VK
356 (len_left == 0), /* EOP? */
357 loopback);
01f2e4ea
SF
358 }
359}
360
361static inline void enic_queue_wq_skb_vlan(struct enic *enic,
362 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 363 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF
364{
365 unsigned int head_len = skb_headlen(skb);
366 unsigned int len_left = skb->len - head_len;
367 int eop = (len_left == 0);
368
ea0d7d91
SF
369 /* Queue the main skb fragment. The fragments are no larger
370 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
371 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
372 * per fragment is queued.
373 */
01f2e4ea
SF
374 enic_queue_wq_desc(wq, skb,
375 pci_map_single(enic->pdev, skb->data,
376 head_len, PCI_DMA_TODEVICE),
377 head_len,
378 vlan_tag_insert, vlan_tag,
1825aca6 379 eop, loopback);
01f2e4ea
SF
380
381 if (!eop)
1825aca6 382 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF
383}
384
385static inline void enic_queue_wq_skb_csum_l4(struct enic *enic,
386 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 387 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF
388{
389 unsigned int head_len = skb_headlen(skb);
390 unsigned int len_left = skb->len - head_len;
0d0b1672 391 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF
392 unsigned int csum_offset = hdr_len + skb->csum_offset;
393 int eop = (len_left == 0);
394
ea0d7d91
SF
395 /* Queue the main skb fragment. The fragments are no larger
396 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
397 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
398 * per fragment is queued.
399 */
01f2e4ea
SF
400 enic_queue_wq_desc_csum_l4(wq, skb,
401 pci_map_single(enic->pdev, skb->data,
402 head_len, PCI_DMA_TODEVICE),
403 head_len,
404 csum_offset,
405 hdr_len,
406 vlan_tag_insert, vlan_tag,
1825aca6 407 eop, loopback);
01f2e4ea
SF
408
409 if (!eop)
1825aca6 410 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF
411}
412
413static inline void enic_queue_wq_skb_tso(struct enic *enic,
414 struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss,
1825aca6 415 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea 416{
ea0d7d91
SF
417 unsigned int frag_len_left = skb_headlen(skb);
418 unsigned int len_left = skb->len - frag_len_left;
01f2e4ea
SF
419 unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
420 int eop = (len_left == 0);
ea0d7d91
SF
421 unsigned int len;
422 dma_addr_t dma_addr;
423 unsigned int offset = 0;
424 skb_frag_t *frag;
01f2e4ea
SF
425
426 /* Preload TCP csum field with IP pseudo hdr calculated
427 * with IP length set to zero. HW will later add in length
428 * to each TCP segment resulting from the TSO.
429 */
430
09640e63 431 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF
432 ip_hdr(skb)->check = 0;
433 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
434 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 435 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
01f2e4ea
SF
436 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
437 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
438 }
439
ea0d7d91
SF
440 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
441 * for the main skb fragment
442 */
443 while (frag_len_left) {
444 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
445 dma_addr = pci_map_single(enic->pdev, skb->data + offset,
446 len, PCI_DMA_TODEVICE);
447 enic_queue_wq_desc_tso(wq, skb,
448 dma_addr,
449 len,
450 mss, hdr_len,
451 vlan_tag_insert, vlan_tag,
1825aca6 452 eop && (len == frag_len_left), loopback);
ea0d7d91
SF
453 frag_len_left -= len;
454 offset += len;
455 }
01f2e4ea 456
ea0d7d91
SF
457 if (eop)
458 return;
459
460 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
461 * for additional data fragments
462 */
463 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED
464 len_left -= skb_frag_size(frag);
465 frag_len_left = skb_frag_size(frag);
4bf5adbf 466 offset = 0;
ea0d7d91
SF
467
468 while (frag_len_left) {
469 len = min(frag_len_left,
470 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC
471 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
472 offset, len,
5d6bcdfe 473 DMA_TO_DEVICE);
ea0d7d91
SF
474 enic_queue_wq_desc_cont(wq, skb,
475 dma_addr,
476 len,
477 (len_left == 0) &&
1825aca6
VK
478 (len == frag_len_left), /* EOP? */
479 loopback);
ea0d7d91
SF
480 frag_len_left -= len;
481 offset += len;
482 }
483 }
01f2e4ea
SF
484}
485
486static inline void enic_queue_wq_skb(struct enic *enic,
487 struct vnic_wq *wq, struct sk_buff *skb)
488{
489 unsigned int mss = skb_shinfo(skb)->gso_size;
490 unsigned int vlan_tag = 0;
491 int vlan_tag_insert = 0;
1825aca6 492 int loopback = 0;
01f2e4ea 493
eab6d18d 494 if (vlan_tx_tag_present(skb)) {
01f2e4ea
SF
495 /* VLAN tag from trunking driver */
496 vlan_tag_insert = 1;
497 vlan_tag = vlan_tx_tag_get(skb);
1825aca6
VK
498 } else if (enic->loop_enable) {
499 vlan_tag = enic->loop_tag;
500 loopback = 1;
01f2e4ea
SF
501 }
502
503 if (mss)
504 enic_queue_wq_skb_tso(enic, wq, skb, mss,
1825aca6 505 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF
506 else if (skb->ip_summed == CHECKSUM_PARTIAL)
507 enic_queue_wq_skb_csum_l4(enic, wq, skb,
1825aca6 508 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF
509 else
510 enic_queue_wq_skb_vlan(enic, wq, skb,
1825aca6 511 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF
512}
513
ed8af6b2 514/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 515static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 516 struct net_device *netdev)
01f2e4ea
SF
517{
518 struct enic *enic = netdev_priv(netdev);
822473b6 519 struct vnic_wq *wq;
01f2e4ea 520 unsigned long flags;
822473b6 521 unsigned int txq_map;
01f2e4ea
SF
522
523 if (skb->len <= 0) {
524 dev_kfree_skb(skb);
525 return NETDEV_TX_OK;
526 }
527
822473b6 528 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
529 wq = &enic->wq[txq_map];
530
01f2e4ea
SF
531 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
532 * which is very likely. In the off chance it's going to take
533 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
534 */
535
536 if (skb_shinfo(skb)->gso_size == 0 &&
537 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
538 skb_linearize(skb)) {
539 dev_kfree_skb(skb);
540 return NETDEV_TX_OK;
541 }
542
822473b6 543 spin_lock_irqsave(&enic->wq_lock[txq_map], flags);
01f2e4ea 544
ea0d7d91
SF
545 if (vnic_wq_desc_avail(wq) <
546 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
822473b6 547 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map));
01f2e4ea 548 /* This is a hard error, log it */
a7a79deb 549 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
822473b6 550 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
01f2e4ea
SF
551 return NETDEV_TX_BUSY;
552 }
553
554 enic_queue_wq_skb(enic, wq, skb);
555
ea0d7d91 556 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
822473b6 557 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map));
01f2e4ea 558
822473b6 559 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
01f2e4ea
SF
560
561 return NETDEV_TX_OK;
562}
563
564/* dev_base_lock rwlock held, nominally process context */
f20530bc 565static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev,
566 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF
567{
568 struct enic *enic = netdev_priv(netdev);
569 struct vnic_stats *stats;
570
383ab92f 571 enic_dev_stats_dump(enic, &stats);
01f2e4ea 572
25f0a061
SF
573 net_stats->tx_packets = stats->tx.tx_frames_ok;
574 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
575 net_stats->tx_errors = stats->tx.tx_errors;
576 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 577
25f0a061
SF
578 net_stats->rx_packets = stats->rx.rx_frames_ok;
579 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
580 net_stats->rx_errors = stats->rx.rx_errors;
581 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 582 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 583 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 584 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea 585
25f0a061 586 return net_stats;
01f2e4ea
SF
587}
588
b3abfbd2 589void enic_reset_addr_lists(struct enic *enic)
01f2e4ea
SF
590{
591 enic->mc_count = 0;
e0afe53f 592 enic->uc_count = 0;
99ef5639 593 enic->flags = 0;
01f2e4ea
SF
594}
595
596static int enic_set_mac_addr(struct net_device *netdev, char *addr)
597{
f8bd9091
SF
598 struct enic *enic = netdev_priv(netdev);
599
7335903c 600 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF
601 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
602 return -EADDRNOTAVAIL;
603 } else {
604 if (!is_valid_ether_addr(addr))
605 return -EADDRNOTAVAIL;
606 }
01f2e4ea
SF
607
608 memcpy(netdev->dev_addr, addr, netdev->addr_len);
609
610 return 0;
611}
612
f8bd9091
SF
613static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
614{
615 struct enic *enic = netdev_priv(netdev);
616 struct sockaddr *saddr = p;
617 char *addr = saddr->sa_data;
618 int err;
619
620 if (netif_running(enic->netdev)) {
621 err = enic_dev_del_station_addr(enic);
622 if (err)
623 return err;
624 }
625
626 err = enic_set_mac_addr(netdev, addr);
627 if (err)
628 return err;
629
630 if (netif_running(enic->netdev)) {
631 err = enic_dev_add_station_addr(enic);
632 if (err)
633 return err;
634 }
635
636 return err;
637}
638
639static int enic_set_mac_address(struct net_device *netdev, void *p)
640{
294dab25 641 struct sockaddr *saddr = p;
c76fd32d
VK
642 char *addr = saddr->sa_data;
643 struct enic *enic = netdev_priv(netdev);
644 int err;
645
646 err = enic_dev_del_station_addr(enic);
647 if (err)
648 return err;
649
650 err = enic_set_mac_addr(netdev, addr);
651 if (err)
652 return err;
294dab25 653
c76fd32d 654 return enic_dev_add_station_addr(enic);
f8bd9091
SF
655}
656
e0afe53f 657static void enic_update_multicast_addr_list(struct enic *enic)
01f2e4ea 658{
319d7e84 659 struct net_device *netdev = enic->netdev;
22bedad3 660 struct netdev_hw_addr *ha;
4cd24eaf 661 unsigned int mc_count = netdev_mc_count(netdev);
01f2e4ea 662 u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN];
01f2e4ea
SF
663 unsigned int i, j;
664
319d7e84
RP
665 if (mc_count > ENIC_MULTICAST_PERFECT_FILTERS) {
666 netdev_warn(netdev, "Registering only %d out of %d "
667 "multicast addresses\n",
668 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
01f2e4ea 669 mc_count = ENIC_MULTICAST_PERFECT_FILTERS;
9959a185 670 }
01f2e4ea
SF
671
672 /* Is there an easier way? Trying to minimize to
673 * calls to add/del multicast addrs. We keep the
674 * addrs from the last call in enic->mc_addr and
675 * look for changes to add/del.
676 */
677
48e2f183 678 i = 0;
22bedad3 679 netdev_for_each_mc_addr(ha, netdev) {
48e2f183
JP
680 if (i == mc_count)
681 break;
22bedad3 682 memcpy(mc_addr[i++], ha->addr, ETH_ALEN);
01f2e4ea
SF
683 }
684
685 for (i = 0; i < enic->mc_count; i++) {
686 for (j = 0; j < mc_count; j++)
2e42e474 687 if (ether_addr_equal(enic->mc_addr[i], mc_addr[j]))
01f2e4ea
SF
688 break;
689 if (j == mc_count)
319d7e84 690 enic_dev_del_addr(enic, enic->mc_addr[i]);
01f2e4ea
SF
691 }
692
693 for (i = 0; i < mc_count; i++) {
694 for (j = 0; j < enic->mc_count; j++)
2e42e474 695 if (ether_addr_equal(mc_addr[i], enic->mc_addr[j]))
01f2e4ea
SF
696 break;
697 if (j == enic->mc_count)
319d7e84 698 enic_dev_add_addr(enic, mc_addr[i]);
01f2e4ea
SF
699 }
700
701 /* Save the list to compare against next time
702 */
703
704 for (i = 0; i < mc_count; i++)
705 memcpy(enic->mc_addr[i], mc_addr[i], ETH_ALEN);
706
707 enic->mc_count = mc_count;
01f2e4ea
SF
708}
709
e0afe53f 710static void enic_update_unicast_addr_list(struct enic *enic)
319d7e84
RP
711{
712 struct net_device *netdev = enic->netdev;
713 struct netdev_hw_addr *ha;
714 unsigned int uc_count = netdev_uc_count(netdev);
715 u8 uc_addr[ENIC_UNICAST_PERFECT_FILTERS][ETH_ALEN];
716 unsigned int i, j;
717
718 if (uc_count > ENIC_UNICAST_PERFECT_FILTERS) {
719 netdev_warn(netdev, "Registering only %d out of %d "
720 "unicast addresses\n",
721 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
722 uc_count = ENIC_UNICAST_PERFECT_FILTERS;
723 }
724
725 /* Is there an easier way? Trying to minimize to
726 * calls to add/del unicast addrs. We keep the
727 * addrs from the last call in enic->uc_addr and
728 * look for changes to add/del.
729 */
730
731 i = 0;
732 netdev_for_each_uc_addr(ha, netdev) {
733 if (i == uc_count)
734 break;
735 memcpy(uc_addr[i++], ha->addr, ETH_ALEN);
736 }
737
738 for (i = 0; i < enic->uc_count; i++) {
739 for (j = 0; j < uc_count; j++)
2e42e474 740 if (ether_addr_equal(enic->uc_addr[i], uc_addr[j]))
319d7e84
RP
741 break;
742 if (j == uc_count)
743 enic_dev_del_addr(enic, enic->uc_addr[i]);
744 }
745
746 for (i = 0; i < uc_count; i++) {
747 for (j = 0; j < enic->uc_count; j++)
2e42e474 748 if (ether_addr_equal(uc_addr[i], enic->uc_addr[j]))
319d7e84
RP
749 break;
750 if (j == enic->uc_count)
751 enic_dev_add_addr(enic, uc_addr[i]);
752 }
753
754 /* Save the list to compare against next time
755 */
756
757 for (i = 0; i < uc_count; i++)
758 memcpy(enic->uc_addr[i], uc_addr[i], ETH_ALEN);
759
760 enic->uc_count = uc_count;
761}
762
763/* netif_tx_lock held, BHs disabled */
764static void enic_set_rx_mode(struct net_device *netdev)
765{
766 struct enic *enic = netdev_priv(netdev);
767 int directed = 1;
768 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
769 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
770 int promisc = (netdev->flags & IFF_PROMISC) ||
771 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
772 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
773 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
774 unsigned int flags = netdev->flags |
775 (allmulti ? IFF_ALLMULTI : 0) |
776 (promisc ? IFF_PROMISC : 0);
777
778 if (enic->flags != flags) {
779 enic->flags = flags;
780 enic_dev_packet_filter(enic, directed,
781 multicast, broadcast, promisc, allmulti);
782 }
783
784 if (!promisc) {
e0afe53f 785 enic_update_unicast_addr_list(enic);
319d7e84 786 if (!allmulti)
e0afe53f 787 enic_update_multicast_addr_list(enic);
319d7e84
RP
788 }
789}
790
01f2e4ea
SF
791/* netif_tx_lock held, BHs disabled */
792static void enic_tx_timeout(struct net_device *netdev)
793{
794 struct enic *enic = netdev_priv(netdev);
795 schedule_work(&enic->reset);
796}
797
0b1c00fc
RP
798static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
799{
800 struct enic *enic = netdev_priv(netdev);
3f192795
RP
801 struct enic_port_profile *pp;
802 int err;
0b1c00fc 803
3f192795
RP
804 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
805 if (err)
806 return err;
0b1c00fc 807
b8622cbd 808 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP
809 if (vf == PORT_SELF_VF) {
810 memcpy(pp->vf_mac, mac, ETH_ALEN);
811 return 0;
812 } else {
813 /*
814 * For sriov vf's set the mac in hw
815 */
816 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
817 vnic_dev_set_mac_addr, mac);
818 return enic_dev_status_to_errno(err);
819 }
0b1c00fc
RP
820 } else
821 return -EINVAL;
822}
823
f8bd9091
SF
824static int enic_set_vf_port(struct net_device *netdev, int vf,
825 struct nlattr *port[])
826{
827 struct enic *enic = netdev_priv(netdev);
b3abfbd2 828 struct enic_port_profile prev_pp;
3f192795 829 struct enic_port_profile *pp;
b3abfbd2 830 int err = 0, restore_pp = 1;
08f382eb 831
3f192795
RP
832 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
833 if (err)
834 return err;
08f382eb 835
b3abfbd2
RP
836 if (!port[IFLA_PORT_REQUEST])
837 return -EOPNOTSUPP;
838
3f192795
RP
839 memcpy(&prev_pp, pp, sizeof(*enic->pp));
840 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 841
3f192795
RP
842 pp->set |= ENIC_SET_REQUEST;
843 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF
844
845 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP
846 pp->set |= ENIC_SET_NAME;
847 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF
848 PORT_PROFILE_MAX);
849 }
850
851 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP
852 pp->set |= ENIC_SET_INSTANCE;
853 memcpy(pp->instance_uuid,
08f382eb
SF
854 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
855 }
856
857 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP
858 pp->set |= ENIC_SET_HOST;
859 memcpy(pp->host_uuid,
08f382eb
SF
860 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
861 }
f8bd9091 862
b4765833
RP
863 if (vf == PORT_SELF_VF) {
864 /* Special case handling: mac came from IFLA_VF_MAC */
865 if (!is_zero_ether_addr(prev_pp.vf_mac))
866 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 867
b4765833
RP
868 if (is_zero_ether_addr(netdev->dev_addr))
869 eth_hw_addr_random(netdev);
870 } else {
871 /* SR-IOV VF: get mac from adapter */
872 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
873 vnic_dev_get_mac_addr, pp->mac_addr);
874 if (err) {
875 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
876 memcpy(pp, &prev_pp, sizeof(*pp));
877 return enic_dev_status_to_errno(err);
878 }
879 }
f8bd9091 880
3f192795 881 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP
882 if (err) {
883 if (restore_pp) {
884 /* Things are still the way they were: Implicit
885 * DISASSOCIATE failed
886 */
3f192795 887 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 888 } else {
3f192795
RP
889 memset(pp, 0, sizeof(*pp));
890 if (vf == PORT_SELF_VF)
891 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP
892 }
893 } else {
894 /* Set flag to indicate that the port assoc/disassoc
895 * request has been sent out to fw
896 */
3f192795 897 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP
898
899 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795
RP
900 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
901 memset(pp->mac_addr, 0, ETH_ALEN);
902 if (vf == PORT_SELF_VF)
903 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP
904 }
905 }
29639059 906
b4765833
RP
907 if (vf == PORT_SELF_VF)
908 memset(pp->vf_mac, 0, ETH_ALEN);
29639059 909
29639059 910 return err;
f8bd9091
SF
911}
912
913static int enic_get_vf_port(struct net_device *netdev, int vf,
914 struct sk_buff *skb)
915{
916 struct enic *enic = netdev_priv(netdev);
f8bd9091 917 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 918 struct enic_port_profile *pp;
b3abfbd2 919 int err;
f8bd9091 920
3f192795
RP
921 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
922 if (err)
923 return err;
924
925 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 926 return -ENODATA;
f8bd9091 927
3f192795 928 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 929 if (err)
b3abfbd2 930 return err;
f8bd9091 931
1a106de6
DM
932 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
933 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
934 ((pp->set & ENIC_SET_NAME) &&
935 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
936 ((pp->set & ENIC_SET_INSTANCE) &&
937 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
938 pp->instance_uuid)) ||
939 ((pp->set & ENIC_SET_HOST) &&
940 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
941 goto nla_put_failure;
f8bd9091
SF
942 return 0;
943
944nla_put_failure:
945 return -EMSGSIZE;
946}
947
01f2e4ea
SF
948static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
949{
950 struct enic *enic = vnic_dev_priv(rq->vdev);
951
952 if (!buf->os_buf)
953 return;
954
955 pci_unmap_single(enic->pdev, buf->dma_addr,
956 buf->len, PCI_DMA_FROMDEVICE);
957 dev_kfree_skb_any(buf->os_buf);
958}
959
01f2e4ea
SF
960static int enic_rq_alloc_buf(struct vnic_rq *rq)
961{
962 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 963 struct net_device *netdev = enic->netdev;
01f2e4ea 964 struct sk_buff *skb;
1825aca6 965 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF
966 unsigned int os_buf_index = 0;
967 dma_addr_t dma_addr;
968
89d71a66 969 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF
970 if (!skb)
971 return -ENOMEM;
972
973 dma_addr = pci_map_single(enic->pdev, skb->data,
974 len, PCI_DMA_FROMDEVICE);
975
976 enic_queue_rq_desc(rq, skb, os_buf_index,
977 dma_addr, len);
978
979 return 0;
980}
981
01f2e4ea
SF
982static void enic_rq_indicate_buf(struct vnic_rq *rq,
983 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
984 int skipped, void *opaque)
985{
986 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 987 struct net_device *netdev = enic->netdev;
01f2e4ea
SF
988 struct sk_buff *skb;
989
990 u8 type, color, eop, sop, ingress_port, vlan_stripped;
991 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
992 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
993 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
994 u8 packet_error;
f8cac14a 995 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea
SF
996 u32 rss_hash;
997
998 if (skipped)
999 return;
1000
1001 skb = buf->os_buf;
1002 prefetch(skb->data - NET_IP_ALIGN);
1003 pci_unmap_single(enic->pdev, buf->dma_addr,
1004 buf->len, PCI_DMA_FROMDEVICE);
1005
1006 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
1007 &type, &color, &q_number, &completed_index,
1008 &ingress_port, &fcoe, &eop, &sop, &rss_type,
1009 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 1010 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF
1011 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
1012 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
1013 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
1014 &fcs_ok);
1015
1016 if (packet_error) {
1017
350991e1
SF
1018 if (!fcs_ok) {
1019 if (bytes_written > 0)
1020 enic->rq_bad_fcs++;
1021 else if (bytes_written == 0)
1022 enic->rq_truncated_pkts++;
1023 }
01f2e4ea
SF
1024
1025 dev_kfree_skb_any(skb);
1026
1027 return;
1028 }
1029
1030 if (eop && bytes_written > 0) {
1031
1032 /* Good receive
1033 */
1034
1035 skb_put(skb, bytes_written);
86ca9db7 1036 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1037 skb_record_rx_queue(skb, q_number);
1038 if (netdev->features & NETIF_F_RXHASH) {
3739acdd
TH
1039 skb_set_hash(skb, rss_hash,
1040 (rss_type &
1041 (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX |
1042 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 |
1043 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ?
1044 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
bf751ba8 1045 }
01f2e4ea 1046
5ec8f9b8 1047 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc) {
01f2e4ea
SF
1048 skb->csum = htons(checksum);
1049 skb->ip_summed = CHECKSUM_COMPLETE;
1050 }
1051
6ede746b 1052 if (vlan_stripped)
86a9bad3 1053 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1054
6ede746b
JP
1055 if (netdev->features & NETIF_F_GRO)
1056 napi_gro_receive(&enic->napi[q_number], skb);
1057 else
1058 netif_receive_skb(skb);
01f2e4ea
SF
1059 } else {
1060
1061 /* Buffer overflow
1062 */
1063
1064 dev_kfree_skb_any(skb);
1065 }
1066}
1067
1068static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1069 u8 type, u16 q_number, u16 completed_index, void *opaque)
1070{
1071 struct enic *enic = vnic_dev_priv(vdev);
1072
1073 vnic_rq_service(&enic->rq[q_number], cq_desc,
1074 completed_index, VNIC_RQ_RETURN_DESC,
1075 enic_rq_indicate_buf, opaque);
1076
1077 return 0;
1078}
1079
01f2e4ea
SF
1080static int enic_poll(struct napi_struct *napi, int budget)
1081{
717258ba
VK
1082 struct net_device *netdev = napi->dev;
1083 struct enic *enic = netdev_priv(netdev);
1084 unsigned int cq_rq = enic_cq_rq(enic, 0);
1085 unsigned int cq_wq = enic_cq_wq(enic, 0);
1086 unsigned int intr = enic_legacy_io_intr();
01f2e4ea
SF
1087 unsigned int rq_work_to_do = budget;
1088 unsigned int wq_work_to_do = -1; /* no limit */
1089 unsigned int work_done, rq_work_done, wq_work_done;
2d6ddced 1090 int err;
01f2e4ea
SF
1091
1092 /* Service RQ (first) and WQ
1093 */
1094
717258ba 1095 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
01f2e4ea
SF
1096 rq_work_to_do, enic_rq_service, NULL);
1097
717258ba 1098 wq_work_done = vnic_cq_service(&enic->cq[cq_wq],
01f2e4ea
SF
1099 wq_work_to_do, enic_wq_service, NULL);
1100
1101 /* Accumulate intr event credits for this polling
1102 * cycle. An intr event is the completion of a
1103 * a WQ or RQ packet.
1104 */
1105
1106 work_done = rq_work_done + wq_work_done;
1107
1108 if (work_done > 0)
717258ba 1109 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF
1110 work_done,
1111 0 /* don't unmask intr */,
1112 0 /* don't reset intr timer */);
1113
0eb26022 1114 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1115
2d6ddced
SF
1116 /* Buffer allocation failed. Stay in polling
1117 * mode so we can try to fill the ring again.
1118 */
01f2e4ea 1119
2d6ddced
SF
1120 if (err)
1121 rq_work_done = rq_work_to_do;
01f2e4ea 1122
2d6ddced 1123 if (rq_work_done < rq_work_to_do) {
01f2e4ea 1124
2d6ddced 1125 /* Some work done, but not enough to stay in polling,
88132f55 1126 * exit polling
01f2e4ea
SF
1127 */
1128
288379f0 1129 napi_complete(napi);
717258ba 1130 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea
SF
1131 }
1132
1133 return rq_work_done;
1134}
1135
1136static int enic_poll_msix(struct napi_struct *napi, int budget)
1137{
717258ba
VK
1138 struct net_device *netdev = napi->dev;
1139 struct enic *enic = netdev_priv(netdev);
1140 unsigned int rq = (napi - &enic->napi[0]);
1141 unsigned int cq = enic_cq_rq(enic, rq);
1142 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea
SF
1143 unsigned int work_to_do = budget;
1144 unsigned int work_done;
2d6ddced 1145 int err;
01f2e4ea
SF
1146
1147 /* Service RQ
1148 */
1149
717258ba 1150 work_done = vnic_cq_service(&enic->cq[cq],
01f2e4ea
SF
1151 work_to_do, enic_rq_service, NULL);
1152
2d6ddced
SF
1153 /* Return intr event credits for this polling
1154 * cycle. An intr event is the completion of a
1155 * RQ packet.
1156 */
01f2e4ea 1157
2d6ddced 1158 if (work_done > 0)
717258ba 1159 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF
1160 work_done,
1161 0 /* don't unmask intr */,
1162 0 /* don't reset intr timer */);
01f2e4ea 1163
0eb26022 1164 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF
1165
1166 /* Buffer allocation failed. Stay in polling mode
1167 * so we can try to fill the ring again.
1168 */
1169
1170 if (err)
1171 work_done = work_to_do;
1172
1173 if (work_done < work_to_do) {
1174
1175 /* Some work done, but not enough to stay in polling,
88132f55 1176 * exit polling
01f2e4ea
SF
1177 */
1178
288379f0 1179 napi_complete(napi);
717258ba 1180 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea
SF
1181 }
1182
1183 return work_done;
1184}
1185
1186static void enic_notify_timer(unsigned long data)
1187{
1188 struct enic *enic = (struct enic *)data;
1189
1190 enic_notify_check(enic);
1191
25f0a061
SF
1192 mod_timer(&enic->notify_timer,
1193 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF
1194}
1195
1196static void enic_free_intr(struct enic *enic)
1197{
1198 struct net_device *netdev = enic->netdev;
1199 unsigned int i;
1200
1201 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1202 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF
1203 free_irq(enic->pdev->irq, netdev);
1204 break;
8f4d248c
SF
1205 case VNIC_DEV_INTR_MODE_MSI:
1206 free_irq(enic->pdev->irq, enic);
1207 break;
01f2e4ea
SF
1208 case VNIC_DEV_INTR_MODE_MSIX:
1209 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1210 if (enic->msix[i].requested)
1211 free_irq(enic->msix_entry[i].vector,
1212 enic->msix[i].devid);
1213 break;
1214 default:
1215 break;
1216 }
1217}
1218
1219static int enic_request_intr(struct enic *enic)
1220{
1221 struct net_device *netdev = enic->netdev;
717258ba 1222 unsigned int i, intr;
01f2e4ea
SF
1223 int err = 0;
1224
1225 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1226
1227 case VNIC_DEV_INTR_MODE_INTX:
1228
1229 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1230 IRQF_SHARED, netdev->name, netdev);
1231 break;
1232
1233 case VNIC_DEV_INTR_MODE_MSI:
1234
1235 err = request_irq(enic->pdev->irq, enic_isr_msi,
1236 0, netdev->name, enic);
1237 break;
1238
1239 case VNIC_DEV_INTR_MODE_MSIX:
1240
717258ba
VK
1241 for (i = 0; i < enic->rq_count; i++) {
1242 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC
1243 snprintf(enic->msix[intr].devname,
1244 sizeof(enic->msix[intr].devname),
717258ba
VK
1245 "%.11s-rx-%d", netdev->name, i);
1246 enic->msix[intr].isr = enic_isr_msix_rq;
1247 enic->msix[intr].devid = &enic->napi[i];
1248 }
01f2e4ea 1249
717258ba
VK
1250 for (i = 0; i < enic->wq_count; i++) {
1251 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC
1252 snprintf(enic->msix[intr].devname,
1253 sizeof(enic->msix[intr].devname),
717258ba
VK
1254 "%.11s-tx-%d", netdev->name, i);
1255 enic->msix[intr].isr = enic_isr_msix_wq;
1256 enic->msix[intr].devid = enic;
1257 }
01f2e4ea 1258
717258ba 1259 intr = enic_msix_err_intr(enic);
4505f40a
DC
1260 snprintf(enic->msix[intr].devname,
1261 sizeof(enic->msix[intr].devname),
01f2e4ea 1262 "%.11s-err", netdev->name);
717258ba
VK
1263 enic->msix[intr].isr = enic_isr_msix_err;
1264 enic->msix[intr].devid = enic;
01f2e4ea 1265
717258ba 1266 intr = enic_msix_notify_intr(enic);
4505f40a
DC
1267 snprintf(enic->msix[intr].devname,
1268 sizeof(enic->msix[intr].devname),
01f2e4ea 1269 "%.11s-notify", netdev->name);
717258ba
VK
1270 enic->msix[intr].isr = enic_isr_msix_notify;
1271 enic->msix[intr].devid = enic;
1272
1273 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1274 enic->msix[i].requested = 0;
01f2e4ea 1275
717258ba 1276 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF
1277 err = request_irq(enic->msix_entry[i].vector,
1278 enic->msix[i].isr, 0,
1279 enic->msix[i].devname,
1280 enic->msix[i].devid);
1281 if (err) {
1282 enic_free_intr(enic);
1283 break;
1284 }
1285 enic->msix[i].requested = 1;
1286 }
1287
1288 break;
1289
1290 default:
1291 break;
1292 }
1293
1294 return err;
1295}
1296
b3d18d19
SF
1297static void enic_synchronize_irqs(struct enic *enic)
1298{
1299 unsigned int i;
1300
1301 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1302 case VNIC_DEV_INTR_MODE_INTX:
1303 case VNIC_DEV_INTR_MODE_MSI:
1304 synchronize_irq(enic->pdev->irq);
1305 break;
1306 case VNIC_DEV_INTR_MODE_MSIX:
1307 for (i = 0; i < enic->intr_count; i++)
1308 synchronize_irq(enic->msix_entry[i].vector);
1309 break;
1310 default:
1311 break;
1312 }
1313}
1314
383ab92f 1315static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF
1316{
1317 int err;
1318
56ac88b3 1319 spin_lock(&enic->devcmd_lock);
01f2e4ea
SF
1320 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1321 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK
1322 err = vnic_dev_notify_set(enic->vdev,
1323 enic_legacy_notify_intr());
01f2e4ea
SF
1324 break;
1325 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK
1326 err = vnic_dev_notify_set(enic->vdev,
1327 enic_msix_notify_intr(enic));
01f2e4ea
SF
1328 break;
1329 default:
1330 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1331 break;
1332 }
56ac88b3 1333 spin_unlock(&enic->devcmd_lock);
01f2e4ea
SF
1334
1335 return err;
1336}
1337
1338static void enic_notify_timer_start(struct enic *enic)
1339{
1340 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1341 case VNIC_DEV_INTR_MODE_MSI:
1342 mod_timer(&enic->notify_timer, jiffies);
1343 break;
1344 default:
1345 /* Using intr for notification for INTx/MSI-X */
1346 break;
6403eab1 1347 }
01f2e4ea
SF
1348}
1349
1350/* rtnl lock is held, process context */
1351static int enic_open(struct net_device *netdev)
1352{
1353 struct enic *enic = netdev_priv(netdev);
1354 unsigned int i;
1355 int err;
1356
4b75a442
SF
1357 err = enic_request_intr(enic);
1358 if (err) {
a7a79deb 1359 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF
1360 return err;
1361 }
1362
383ab92f 1363 err = enic_dev_notify_set(enic);
4b75a442 1364 if (err) {
a7a79deb
VK
1365 netdev_err(netdev,
1366 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF
1367 goto err_out_free_intr;
1368 }
1369
01f2e4ea 1370 for (i = 0; i < enic->rq_count; i++) {
0eb26022 1371 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF
1372 /* Need at least one buffer on ring to get going */
1373 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1374 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1375 err = -ENOMEM;
4b75a442 1376 goto err_out_notify_unset;
01f2e4ea
SF
1377 }
1378 }
1379
1380 for (i = 0; i < enic->wq_count; i++)
1381 vnic_wq_enable(&enic->wq[i]);
1382 for (i = 0; i < enic->rq_count; i++)
1383 vnic_rq_enable(&enic->rq[i]);
1384
7335903c 1385 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1386 enic_dev_add_station_addr(enic);
3f192795 1387
319d7e84 1388 enic_set_rx_mode(netdev);
01f2e4ea 1389
822473b6 1390 netif_tx_wake_all_queues(netdev);
717258ba
VK
1391
1392 for (i = 0; i < enic->rq_count; i++)
1393 napi_enable(&enic->napi[i]);
1394
383ab92f 1395 enic_dev_enable(enic);
01f2e4ea
SF
1396
1397 for (i = 0; i < enic->intr_count; i++)
1398 vnic_intr_unmask(&enic->intr[i]);
1399
1400 enic_notify_timer_start(enic);
1401
1402 return 0;
4b75a442
SF
1403
1404err_out_notify_unset:
383ab92f 1405 enic_dev_notify_unset(enic);
4b75a442
SF
1406err_out_free_intr:
1407 enic_free_intr(enic);
1408
1409 return err;
01f2e4ea
SF
1410}
1411
1412/* rtnl lock is held, process context */
1413static int enic_stop(struct net_device *netdev)
1414{
1415 struct enic *enic = netdev_priv(netdev);
1416 unsigned int i;
1417 int err;
1418
29046f9b 1419 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 1420 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK
1421 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
1422 }
b3d18d19
SF
1423
1424 enic_synchronize_irqs(enic);
1425
01f2e4ea
SF
1426 del_timer_sync(&enic->notify_timer);
1427
383ab92f 1428 enic_dev_disable(enic);
717258ba
VK
1429
1430 for (i = 0; i < enic->rq_count; i++)
1431 napi_disable(&enic->napi[i]);
1432
b3d18d19
SF
1433 netif_carrier_off(netdev);
1434 netif_tx_disable(netdev);
3f192795 1435
7335903c 1436 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1437 enic_dev_del_station_addr(enic);
f8bd9091 1438
01f2e4ea
SF
1439 for (i = 0; i < enic->wq_count; i++) {
1440 err = vnic_wq_disable(&enic->wq[i]);
1441 if (err)
1442 return err;
1443 }
1444 for (i = 0; i < enic->rq_count; i++) {
1445 err = vnic_rq_disable(&enic->rq[i]);
1446 if (err)
1447 return err;
1448 }
1449
383ab92f 1450 enic_dev_notify_unset(enic);
4b75a442
SF
1451 enic_free_intr(enic);
1452
01f2e4ea
SF
1453 for (i = 0; i < enic->wq_count; i++)
1454 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
1455 for (i = 0; i < enic->rq_count; i++)
1456 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
1457 for (i = 0; i < enic->cq_count; i++)
1458 vnic_cq_clean(&enic->cq[i]);
1459 for (i = 0; i < enic->intr_count; i++)
1460 vnic_intr_clean(&enic->intr[i]);
1461
1462 return 0;
1463}
1464
1465static int enic_change_mtu(struct net_device *netdev, int new_mtu)
1466{
1467 struct enic *enic = netdev_priv(netdev);
1468 int running = netif_running(netdev);
1469
25f0a061
SF
1470 if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU)
1471 return -EINVAL;
1472
7335903c 1473 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP
1474 return -EOPNOTSUPP;
1475
01f2e4ea
SF
1476 if (running)
1477 enic_stop(netdev);
1478
01f2e4ea
SF
1479 netdev->mtu = new_mtu;
1480
1481 if (netdev->mtu > enic->port_mtu)
a7a79deb
VK
1482 netdev_warn(netdev,
1483 "interface MTU (%d) set higher than port MTU (%d)\n",
1484 netdev->mtu, enic->port_mtu);
01f2e4ea
SF
1485
1486 if (running)
1487 enic_open(netdev);
1488
1489 return 0;
1490}
1491
c97c894d
RP
1492static void enic_change_mtu_work(struct work_struct *work)
1493{
1494 struct enic *enic = container_of(work, struct enic, change_mtu_work);
1495 struct net_device *netdev = enic->netdev;
1496 int new_mtu = vnic_dev_mtu(enic->vdev);
1497 int err;
1498 unsigned int i;
1499
1500 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
1501
1502 rtnl_lock();
1503
1504 /* Stop RQ */
1505 del_timer_sync(&enic->notify_timer);
1506
1507 for (i = 0; i < enic->rq_count; i++)
1508 napi_disable(&enic->napi[i]);
1509
1510 vnic_intr_mask(&enic->intr[0]);
1511 enic_synchronize_irqs(enic);
1512 err = vnic_rq_disable(&enic->rq[0]);
1513 if (err) {
e057590b 1514 rtnl_unlock();
c97c894d
RP
1515 netdev_err(netdev, "Unable to disable RQ.\n");
1516 return;
1517 }
1518 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
1519 vnic_cq_clean(&enic->cq[0]);
1520 vnic_intr_clean(&enic->intr[0]);
1521
1522 /* Fill RQ with new_mtu-sized buffers */
1523 netdev->mtu = new_mtu;
1524 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
1525 /* Need at least one buffer on ring to get going */
1526 if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
e057590b 1527 rtnl_unlock();
c97c894d
RP
1528 netdev_err(netdev, "Unable to alloc receive buffers.\n");
1529 return;
1530 }
1531
1532 /* Start RQ */
1533 vnic_rq_enable(&enic->rq[0]);
1534 napi_enable(&enic->napi[0]);
1535 vnic_intr_unmask(&enic->intr[0]);
1536 enic_notify_timer_start(enic);
1537
1538 rtnl_unlock();
1539
1540 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
1541}
1542
01f2e4ea
SF
1543#ifdef CONFIG_NET_POLL_CONTROLLER
1544static void enic_poll_controller(struct net_device *netdev)
1545{
1546 struct enic *enic = netdev_priv(netdev);
1547 struct vnic_dev *vdev = enic->vdev;
717258ba 1548 unsigned int i, intr;
01f2e4ea
SF
1549
1550 switch (vnic_dev_get_intr_mode(vdev)) {
1551 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK
1552 for (i = 0; i < enic->rq_count; i++) {
1553 intr = enic_msix_rq_intr(enic, i);
79aeec58
VK
1554 enic_isr_msix_rq(enic->msix_entry[intr].vector,
1555 &enic->napi[i]);
717258ba 1556 }
b880a954
VK
1557
1558 for (i = 0; i < enic->wq_count; i++) {
1559 intr = enic_msix_wq_intr(enic, i);
1560 enic_isr_msix_wq(enic->msix_entry[intr].vector, enic);
1561 }
1562
01f2e4ea
SF
1563 break;
1564 case VNIC_DEV_INTR_MODE_MSI:
1565 enic_isr_msi(enic->pdev->irq, enic);
1566 break;
1567 case VNIC_DEV_INTR_MODE_INTX:
1568 enic_isr_legacy(enic->pdev->irq, netdev);
1569 break;
1570 default:
1571 break;
1572 }
1573}
1574#endif
1575
1576static int enic_dev_wait(struct vnic_dev *vdev,
1577 int (*start)(struct vnic_dev *, int),
1578 int (*finished)(struct vnic_dev *, int *),
1579 int arg)
1580{
1581 unsigned long time;
1582 int done;
1583 int err;
1584
1585 BUG_ON(in_interrupt());
1586
1587 err = start(vdev, arg);
1588 if (err)
1589 return err;
1590
1591 /* Wait for func to complete...2 seconds max
1592 */
1593
1594 time = jiffies + (HZ * 2);
1595 do {
1596
1597 err = finished(vdev, &done);
1598 if (err)
1599 return err;
1600
1601 if (done)
1602 return 0;
1603
1604 schedule_timeout_uninterruptible(HZ / 10);
1605
1606 } while (time_after(time, jiffies));
1607
1608 return -ETIMEDOUT;
1609}
1610
1611static int enic_dev_open(struct enic *enic)
1612{
1613 int err;
1614
1615 err = enic_dev_wait(enic->vdev, vnic_dev_open,
1616 vnic_dev_open_done, 0);
1617 if (err)
a7a79deb
VK
1618 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
1619 err);
01f2e4ea
SF
1620
1621 return err;
1622}
1623
99ef5639 1624static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF
1625{
1626 int err;
1627
99ef5639
VK
1628 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
1629 vnic_dev_hang_reset_done, 0);
01f2e4ea 1630 if (err)
a7a79deb
VK
1631 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
1632 err);
01f2e4ea
SF
1633
1634 return err;
1635}
1636
717258ba
VK
1637static int enic_set_rsskey(struct enic *enic)
1638{
1f4f067f 1639 dma_addr_t rss_key_buf_pa;
717258ba
VK
1640 union vnic_rss_key *rss_key_buf_va = NULL;
1641 union vnic_rss_key rss_key = {
1642 .key[0].b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101},
1643 .key[1].b = {80, 65, 76, 79, 117, 110, 105, 113, 117, 101},
1644 .key[2].b = {76, 73, 78, 85, 88, 114, 111, 99, 107, 115},
1645 .key[3].b = {69, 78, 73, 67, 105, 115, 99, 111, 111, 108},
1646 };
1647 int err;
1648
1649 rss_key_buf_va = pci_alloc_consistent(enic->pdev,
1650 sizeof(union vnic_rss_key), &rss_key_buf_pa);
1651 if (!rss_key_buf_va)
1652 return -ENOMEM;
1653
1654 memcpy(rss_key_buf_va, &rss_key, sizeof(union vnic_rss_key));
1655
1656 spin_lock(&enic->devcmd_lock);
1657 err = enic_set_rss_key(enic,
1658 rss_key_buf_pa,
1659 sizeof(union vnic_rss_key));
1660 spin_unlock(&enic->devcmd_lock);
1661
1662 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
1663 rss_key_buf_va, rss_key_buf_pa);
1664
1665 return err;
1666}
1667
1668static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
1669{
1f4f067f 1670 dma_addr_t rss_cpu_buf_pa;
717258ba
VK
1671 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
1672 unsigned int i;
1673 int err;
1674
1675 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
1676 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
1677 if (!rss_cpu_buf_va)
1678 return -ENOMEM;
1679
1680 for (i = 0; i < (1 << rss_hash_bits); i++)
1681 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
1682
1683 spin_lock(&enic->devcmd_lock);
1684 err = enic_set_rss_cpu(enic,
1685 rss_cpu_buf_pa,
1686 sizeof(union vnic_rss_cpu));
1687 spin_unlock(&enic->devcmd_lock);
1688
1689 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
1690 rss_cpu_buf_va, rss_cpu_buf_pa);
1691
1692 return err;
1693}
1694
1695static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
1696 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 1697{
68f71708
SF
1698 const u8 tso_ipid_split_en = 0;
1699 const u8 ig_vlan_strip_en = 1;
383ab92f 1700 int err;
68f71708 1701
717258ba
VK
1702 /* Enable VLAN tag stripping.
1703 */
68f71708 1704
383ab92f
VK
1705 spin_lock(&enic->devcmd_lock);
1706 err = enic_set_nic_cfg(enic,
68f71708
SF
1707 rss_default_cpu, rss_hash_type,
1708 rss_hash_bits, rss_base_cpu,
1709 rss_enable, tso_ipid_split_en,
1710 ig_vlan_strip_en);
383ab92f
VK
1711 spin_unlock(&enic->devcmd_lock);
1712
1713 return err;
1714}
1715
717258ba
VK
1716static int enic_set_rss_nic_cfg(struct enic *enic)
1717{
1718 struct device *dev = enic_get_dev(enic);
1719 const u8 rss_default_cpu = 0;
1720 const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
1721 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
1722 NIC_CFG_RSS_HASH_TYPE_IPV6 |
1723 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
1724 const u8 rss_hash_bits = 7;
1725 const u8 rss_base_cpu = 0;
1726 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
1727
1728 if (rss_enable) {
1729 if (!enic_set_rsskey(enic)) {
1730 if (enic_set_rsscpu(enic, rss_hash_bits)) {
1731 rss_enable = 0;
1732 dev_warn(dev, "RSS disabled, "
1733 "Failed to set RSS cpu indirection table.");
1734 }
1735 } else {
1736 rss_enable = 0;
1737 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
1738 }
1739 }
1740
1741 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
1742 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK
1743}
1744
01f2e4ea
SF
1745static void enic_reset(struct work_struct *work)
1746{
1747 struct enic *enic = container_of(work, struct enic, reset);
1748
1749 if (!netif_running(enic->netdev))
1750 return;
1751
1752 rtnl_lock();
1753
0b038566 1754 spin_lock(&enic->enic_api_lock);
383ab92f 1755 enic_dev_hang_notify(enic);
01f2e4ea 1756 enic_stop(enic->netdev);
99ef5639 1757 enic_dev_hang_reset(enic);
e0afe53f 1758 enic_reset_addr_lists(enic);
01f2e4ea 1759 enic_init_vnic_resources(enic);
717258ba 1760 enic_set_rss_nic_cfg(enic);
f8cac14a 1761 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 1762 enic_open(enic->netdev);
0b038566 1763 spin_unlock(&enic->enic_api_lock);
d765bb41 1764 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF
1765
1766 rtnl_unlock();
1767}
1768
1769static int enic_set_intr_mode(struct enic *enic)
1770{
717258ba 1771 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 1772 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF
1773 unsigned int i;
1774
1775 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 1776 * on system capabilities.
01f2e4ea
SF
1777 *
1778 * Try MSI-X first
1779 *
1780 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
1781 * (the second to last INTR is used for WQ/RQ errors)
1782 * (the last INTR is used for notifications)
1783 */
1784
1785 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
1786 for (i = 0; i < n + m + 2; i++)
1787 enic->msix_entry[i].entry = i;
1788
717258ba
VK
1789 /* Use multiple RQs if RSS is enabled
1790 */
1791
1792 if (ENIC_SETTING(enic, RSS) &&
1793 enic->config.intr_mode < 1 &&
01f2e4ea
SF
1794 enic->rq_count >= n &&
1795 enic->wq_count >= m &&
1796 enic->cq_count >= n + m &&
717258ba 1797 enic->intr_count >= n + m + 2) {
01f2e4ea 1798
717258ba 1799 if (!pci_enable_msix(enic->pdev, enic->msix_entry, n + m + 2)) {
01f2e4ea 1800
717258ba
VK
1801 enic->rq_count = n;
1802 enic->wq_count = m;
1803 enic->cq_count = n + m;
1804 enic->intr_count = n + m + 2;
01f2e4ea 1805
717258ba
VK
1806 vnic_dev_set_intr_mode(enic->vdev,
1807 VNIC_DEV_INTR_MODE_MSIX);
1808
1809 return 0;
1810 }
1811 }
1812
1813 if (enic->config.intr_mode < 1 &&
1814 enic->rq_count >= 1 &&
1815 enic->wq_count >= m &&
1816 enic->cq_count >= 1 + m &&
1817 enic->intr_count >= 1 + m + 2) {
1818 if (!pci_enable_msix(enic->pdev, enic->msix_entry, 1 + m + 2)) {
1819
1820 enic->rq_count = 1;
1821 enic->wq_count = m;
1822 enic->cq_count = 1 + m;
1823 enic->intr_count = 1 + m + 2;
1824
1825 vnic_dev_set_intr_mode(enic->vdev,
1826 VNIC_DEV_INTR_MODE_MSIX);
1827
1828 return 0;
1829 }
01f2e4ea
SF
1830 }
1831
1832 /* Next try MSI
1833 *
1834 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
1835 */
1836
1837 if (enic->config.intr_mode < 2 &&
1838 enic->rq_count >= 1 &&
1839 enic->wq_count >= 1 &&
1840 enic->cq_count >= 2 &&
1841 enic->intr_count >= 1 &&
1842 !pci_enable_msi(enic->pdev)) {
1843
1844 enic->rq_count = 1;
1845 enic->wq_count = 1;
1846 enic->cq_count = 2;
1847 enic->intr_count = 1;
1848
1849 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
1850
1851 return 0;
1852 }
1853
1854 /* Next try INTx
1855 *
1856 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
1857 * (the first INTR is used for WQ/RQ)
1858 * (the second INTR is used for WQ/RQ errors)
1859 * (the last INTR is used for notifications)
1860 */
1861
1862 if (enic->config.intr_mode < 3 &&
1863 enic->rq_count >= 1 &&
1864 enic->wq_count >= 1 &&
1865 enic->cq_count >= 2 &&
1866 enic->intr_count >= 3) {
1867
1868 enic->rq_count = 1;
1869 enic->wq_count = 1;
1870 enic->cq_count = 2;
1871 enic->intr_count = 3;
1872
1873 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
1874
1875 return 0;
1876 }
1877
1878 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
1879
1880 return -EINVAL;
1881}
1882
1883static void enic_clear_intr_mode(struct enic *enic)
1884{
1885 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1886 case VNIC_DEV_INTR_MODE_MSIX:
1887 pci_disable_msix(enic->pdev);
1888 break;
1889 case VNIC_DEV_INTR_MODE_MSI:
1890 pci_disable_msi(enic->pdev);
1891 break;
1892 default:
1893 break;
1894 }
1895
1896 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
1897}
1898
f8bd9091
SF
1899static const struct net_device_ops enic_netdev_dynamic_ops = {
1900 .ndo_open = enic_open,
1901 .ndo_stop = enic_stop,
1902 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 1903 .ndo_get_stats64 = enic_get_stats,
f8bd9091 1904 .ndo_validate_addr = eth_validate_addr,
319d7e84 1905 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF
1906 .ndo_set_mac_address = enic_set_mac_address_dynamic,
1907 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF
1908 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
1909 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
1910 .ndo_tx_timeout = enic_tx_timeout,
1911 .ndo_set_vf_port = enic_set_vf_port,
1912 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 1913 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF
1914#ifdef CONFIG_NET_POLL_CONTROLLER
1915 .ndo_poll_controller = enic_poll_controller,
1916#endif
1917};
1918
afe29f7a
SH
1919static const struct net_device_ops enic_netdev_ops = {
1920 .ndo_open = enic_open,
1921 .ndo_stop = enic_stop,
00829823 1922 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 1923 .ndo_get_stats64 = enic_get_stats,
afe29f7a 1924 .ndo_validate_addr = eth_validate_addr,
f8bd9091 1925 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 1926 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 1927 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH
1928 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
1929 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
1930 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP
1931 .ndo_set_vf_port = enic_set_vf_port,
1932 .ndo_get_vf_port = enic_get_vf_port,
1933 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH
1934#ifdef CONFIG_NET_POLL_CONTROLLER
1935 .ndo_poll_controller = enic_poll_controller,
1936#endif
1937};
1938
2fdba388 1939static void enic_dev_deinit(struct enic *enic)
6fdfa970 1940{
717258ba
VK
1941 unsigned int i;
1942
1943 for (i = 0; i < enic->rq_count; i++)
1944 netif_napi_del(&enic->napi[i]);
1945
6fdfa970
SF
1946 enic_free_vnic_resources(enic);
1947 enic_clear_intr_mode(enic);
1948}
1949
2fdba388 1950static int enic_dev_init(struct enic *enic)
6fdfa970 1951{
a7a79deb 1952 struct device *dev = enic_get_dev(enic);
6fdfa970 1953 struct net_device *netdev = enic->netdev;
717258ba 1954 unsigned int i;
6fdfa970
SF
1955 int err;
1956
ea7ea65a
VK
1957 /* Get interrupt coalesce timer info */
1958 err = enic_dev_intr_coal_timer_info(enic);
1959 if (err) {
1960 dev_warn(dev, "Using default conversion factor for "
1961 "interrupt coalesce timer\n");
1962 vnic_dev_intr_coal_timer_info_default(enic->vdev);
1963 }
1964
6fdfa970
SF
1965 /* Get vNIC configuration
1966 */
1967
1968 err = enic_get_vnic_config(enic);
1969 if (err) {
a7a79deb 1970 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF
1971 return err;
1972 }
1973
1974 /* Get available resource counts
1975 */
1976
1977 enic_get_res_counts(enic);
1978
1979 /* Set interrupt mode based on resource counts and system
1980 * capabilities
1981 */
1982
1983 err = enic_set_intr_mode(enic);
1984 if (err) {
a7a79deb
VK
1985 dev_err(dev, "Failed to set intr mode based on resource "
1986 "counts and system capabilities, aborting\n");
6fdfa970
SF
1987 return err;
1988 }
1989
1990 /* Allocate and configure vNIC resources
1991 */
1992
1993 err = enic_alloc_vnic_resources(enic);
1994 if (err) {
a7a79deb 1995 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF
1996 goto err_out_free_vnic_resources;
1997 }
1998
1999 enic_init_vnic_resources(enic);
2000
717258ba 2001 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2002 if (err) {
a7a79deb 2003 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF
2004 goto err_out_free_vnic_resources;
2005 }
2006
2007 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2008 default:
717258ba 2009 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
6fdfa970
SF
2010 break;
2011 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK
2012 for (i = 0; i < enic->rq_count; i++)
2013 netif_napi_add(netdev, &enic->napi[i],
2014 enic_poll_msix, 64);
6fdfa970
SF
2015 break;
2016 }
2017
2018 return 0;
2019
2020err_out_free_vnic_resources:
2021 enic_clear_intr_mode(enic);
2022 enic_free_vnic_resources(enic);
2023
2024 return err;
2025}
2026
27e6c7d3
SF
2027static void enic_iounmap(struct enic *enic)
2028{
2029 unsigned int i;
2030
2031 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2032 if (enic->bar[i].vaddr)
2033 iounmap(enic->bar[i].vaddr);
2034}
2035
1dd06ae8 2036static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2037{
a7a79deb 2038 struct device *dev = &pdev->dev;
01f2e4ea
SF
2039 struct net_device *netdev;
2040 struct enic *enic;
2041 int using_dac = 0;
2042 unsigned int i;
2043 int err;
8749b427
RP
2044#ifdef CONFIG_PCI_IOV
2045 int pos = 0;
2046#endif
b67f231d 2047 int num_pps = 1;
01f2e4ea 2048
01f2e4ea
SF
2049 /* Allocate net device structure and initialize. Private
2050 * instance data is initialized to zero.
2051 */
2052
822473b6 2053 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2054 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2055 if (!netdev)
01f2e4ea 2056 return -ENOMEM;
01f2e4ea 2057
01f2e4ea
SF
2058 pci_set_drvdata(pdev, netdev);
2059
2060 SET_NETDEV_DEV(netdev, &pdev->dev);
2061
2062 enic = netdev_priv(netdev);
2063 enic->netdev = netdev;
2064 enic->pdev = pdev;
2065
2066 /* Setup PCI resources
2067 */
2068
29046f9b 2069 err = pci_enable_device_mem(pdev);
01f2e4ea 2070 if (err) {
a7a79deb 2071 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF
2072 goto err_out_free_netdev;
2073 }
2074
2075 err = pci_request_regions(pdev, DRV_NAME);
2076 if (err) {
a7a79deb 2077 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF
2078 goto err_out_disable_device;
2079 }
2080
2081 pci_set_master(pdev);
2082
2083 /* Query PCI controller on system for DMA addressing
624dbf55 2084 * limitation for the device. Try 64-bit first, and
01f2e4ea
SF
2085 * fail to 32-bit.
2086 */
2087
624dbf55 2088 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2089 if (err) {
284901a9 2090 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2091 if (err) {
a7a79deb 2092 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF
2093 goto err_out_release_regions;
2094 }
284901a9 2095 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2096 if (err) {
a7a79deb
VK
2097 dev_err(dev, "Unable to obtain %u-bit DMA "
2098 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF
2099 goto err_out_release_regions;
2100 }
2101 } else {
624dbf55 2102 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2103 if (err) {
a7a79deb 2104 dev_err(dev, "Unable to obtain %u-bit DMA "
624dbf55 2105 "for consistent allocations, aborting\n", 64);
01f2e4ea
SF
2106 goto err_out_release_regions;
2107 }
2108 using_dac = 1;
2109 }
2110
27e6c7d3 2111 /* Map vNIC resources from BAR0-5
01f2e4ea
SF
2112 */
2113
27e6c7d3
SF
2114 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2115 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2116 continue;
2117 enic->bar[i].len = pci_resource_len(pdev, i);
2118 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2119 if (!enic->bar[i].vaddr) {
a7a79deb 2120 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF
2121 err = -ENODEV;
2122 goto err_out_iounmap;
2123 }
2124 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF
2125 }
2126
2127 /* Register vNIC device
2128 */
2129
27e6c7d3
SF
2130 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2131 ARRAY_SIZE(enic->bar));
01f2e4ea 2132 if (!enic->vdev) {
a7a79deb 2133 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF
2134 err = -ENODEV;
2135 goto err_out_iounmap;
2136 }
2137
8749b427
RP
2138#ifdef CONFIG_PCI_IOV
2139 /* Get number of subvnics */
2140 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2141 if (pos) {
2142 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2143 &enic->num_vfs);
8749b427
RP
2144 if (enic->num_vfs) {
2145 err = pci_enable_sriov(pdev, enic->num_vfs);
2146 if (err) {
2147 dev_err(dev, "SRIOV enable failed, aborting."
2148 " pci_enable_sriov() returned %d\n",
2149 err);
2150 goto err_out_vnic_unregister;
2151 }
2152 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2153 num_pps = enic->num_vfs;
8749b427
RP
2154 }
2155 }
8749b427 2156#endif
ca2b721d 2157
3f192795 2158 /* Allocate structure for port profiles */
a1de2219 2159 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2160 if (!enic->pp) {
3f192795 2161 err = -ENOMEM;
ca2b721d 2162 goto err_out_disable_sriov_pp;
3f192795
RP
2163 }
2164
01f2e4ea
SF
2165 /* Issue device open to get device in known state
2166 */
2167
2168 err = enic_dev_open(enic);
2169 if (err) {
a7a79deb 2170 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2171 goto err_out_disable_sriov;
01f2e4ea
SF
2172 }
2173
69161425
VK
2174 /* Setup devcmd lock
2175 */
2176
2177 spin_lock_init(&enic->devcmd_lock);
0b038566 2178 spin_lock_init(&enic->enic_api_lock);
69161425
VK
2179
2180 /*
2181 * Set ingress vlan rewrite mode before vnic initialization
2182 */
2183
2184 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2185 if (err) {
2186 dev_err(dev,
2187 "Failed to set ingress vlan rewrite mode, aborting.\n");
2188 goto err_out_dev_close;
2189 }
2190
01f2e4ea
SF
2191 /* Issue device init to initialize the vnic-to-switch link.
2192 * We'll start with carrier off and wait for link UP
2193 * notification later to turn on carrier. We don't need
2194 * to wait here for the vnic-to-switch link initialization
2195 * to complete; link UP notification is the indication that
2196 * the process is complete.
2197 */
2198
2199 netif_carrier_off(netdev);
2200
a7a79deb
VK
2201 /* Do not call dev_init for a dynamic vnic.
2202 * For a dynamic vnic, init_prov_info will be
2203 * called later by an upper layer.
2204 */
2205
2b68c181 2206 if (!enic_is_dynamic(enic)) {
f8bd9091
SF
2207 err = vnic_dev_init(enic->vdev, 0);
2208 if (err) {
a7a79deb 2209 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF
2210 goto err_out_dev_close;
2211 }
01f2e4ea
SF
2212 }
2213
6fdfa970 2214 err = enic_dev_init(enic);
01f2e4ea 2215 if (err) {
a7a79deb 2216 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF
2217 goto err_out_dev_close;
2218 }
2219
822473b6 2220 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2221 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2222
383ab92f 2223 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF
2224 */
2225
2226 init_timer(&enic->notify_timer);
2227 enic->notify_timer.function = enic_notify_timer;
2228 enic->notify_timer.data = (unsigned long)enic;
2229
2230 INIT_WORK(&enic->reset, enic_reset);
c97c894d 2231 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF
2232
2233 for (i = 0; i < enic->wq_count; i++)
2234 spin_lock_init(&enic->wq_lock[i]);
2235
01f2e4ea
SF
2236 /* Register net device
2237 */
2238
2239 enic->port_mtu = enic->config.mtu;
2240 (void)enic_change_mtu(netdev, enic->port_mtu);
2241
2242 err = enic_set_mac_addr(netdev, enic->mac_addr);
2243 if (err) {
a7a79deb 2244 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2245 goto err_out_dev_deinit;
01f2e4ea
SF
2246 }
2247
7c844599
SF
2248 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
2249 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2250
7335903c 2251 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF
2252 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2253 else
2254 netdev->netdev_ops = &enic_netdev_ops;
2255
01f2e4ea 2256 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2257 enic_set_ethtool_ops(netdev);
01f2e4ea 2258
f646968f 2259 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2260 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2261 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK
2262 enic->loop_enable = 1;
2263 enic->loop_tag = enic->config.loop_tag;
2264 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2265 }
01f2e4ea 2266 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2267 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2268 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2269 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2270 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2271 if (ENIC_SETTING(enic, RSS))
2272 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM
2273 if (ENIC_SETTING(enic, RXCSUM))
2274 netdev->hw_features |= NETIF_F_RXCSUM;
2275
2276 netdev->features |= netdev->hw_features;
2277
01f2e4ea
SF
2278 if (using_dac)
2279 netdev->features |= NETIF_F_HIGHDMA;
2280
01789349
JP
2281 netdev->priv_flags |= IFF_UNICAST_FLT;
2282
01f2e4ea
SF
2283 err = register_netdev(netdev);
2284 if (err) {
a7a79deb 2285 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 2286 goto err_out_dev_deinit;
01f2e4ea
SF
2287 }
2288
2289 return 0;
2290
6fdfa970
SF
2291err_out_dev_deinit:
2292 enic_dev_deinit(enic);
01f2e4ea
SF
2293err_out_dev_close:
2294 vnic_dev_close(enic->vdev);
8749b427 2295err_out_disable_sriov:
ca2b721d
RP
2296 kfree(enic->pp);
2297err_out_disable_sriov_pp:
8749b427
RP
2298#ifdef CONFIG_PCI_IOV
2299 if (enic_sriov_enabled(enic)) {
2300 pci_disable_sriov(pdev);
2301 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2302 }
01f2e4ea 2303err_out_vnic_unregister:
8749b427 2304#endif
35d87e33 2305 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF
2306err_out_iounmap:
2307 enic_iounmap(enic);
2308err_out_release_regions:
2309 pci_release_regions(pdev);
2310err_out_disable_device:
2311 pci_disable_device(pdev);
2312err_out_free_netdev:
01f2e4ea
SF
2313 free_netdev(netdev);
2314
2315 return err;
2316}
2317
854de92f 2318static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF
2319{
2320 struct net_device *netdev = pci_get_drvdata(pdev);
2321
2322 if (netdev) {
2323 struct enic *enic = netdev_priv(netdev);
2324
23f333a2 2325 cancel_work_sync(&enic->reset);
c97c894d 2326 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 2327 unregister_netdev(netdev);
6fdfa970 2328 enic_dev_deinit(enic);
01f2e4ea 2329 vnic_dev_close(enic->vdev);
8749b427
RP
2330#ifdef CONFIG_PCI_IOV
2331 if (enic_sriov_enabled(enic)) {
2332 pci_disable_sriov(pdev);
2333 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2334 }
2335#endif
3f192795 2336 kfree(enic->pp);
01f2e4ea
SF
2337 vnic_dev_unregister(enic->vdev);
2338 enic_iounmap(enic);
2339 pci_release_regions(pdev);
2340 pci_disable_device(pdev);
01f2e4ea
SF
2341 free_netdev(netdev);
2342 }
2343}
2344
2345static struct pci_driver enic_driver = {
2346 .name = DRV_NAME,
2347 .id_table = enic_id_table,
2348 .probe = enic_probe,
854de92f 2349 .remove = enic_remove,
01f2e4ea
SF
2350};
2351
2352static int __init enic_init_module(void)
2353{
a7a79deb 2354 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
01f2e4ea
SF
2355
2356 return pci_register_driver(&enic_driver);
2357}
2358
2359static void __exit enic_cleanup_module(void)
2360{
2361 pci_unregister_driver(&enic_driver);
2362}
2363
2364module_init(enic_init_module);
2365module_exit(enic_cleanup_module);