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dev_ioctl: remove dev_load() CAP_SYS_MODULE message
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / cisco / enic / enic_main.c
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01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/types.h>
25#include <linux/init.h>
a6b7a407 26#include <linux/interrupt.h>
01f2e4ea
SF		 27#include <linux/workqueue.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
01789349 31#include <linux/if.h>
01f2e4ea
SF		 32#include <linux/if_ether.h>
33#include <linux/if_vlan.h>
01f2e4ea
SF		 34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
29046f9b 38#include <linux/rtnetlink.h>
70c71606 39#include <linux/prefetch.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
7c2ce6e6 41#include <linux/ktime.h>
b6e97c13
GV		 42#ifdef CONFIG_RFS_ACCEL
43#include <linux/cpu_rmap.h>
44#endif
14747cd9
GV		 45#ifdef CONFIG_NET_RX_BUSY_POLL
46#include <net/busy_poll.h>
47#endif
01f2e4ea
SF		 48
49#include "cq_enet_desc.h"
50#include "vnic_dev.h"
51#include "vnic_intr.h"
52#include "vnic_stats.h"
f8bd9091 53#include "vnic_vic.h"
01f2e4ea
SF		 54#include "enic_res.h"
55#include "enic.h"
51987461 56#include "enic_dev.h"
b3abfbd2 57#include "enic_pp.h"
a145df23 58#include "enic_clsf.h"
01f2e4ea
SF		 59
60#define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ)
ea0d7d91
SF		 61#define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS)
62#define MAX_TSO (1 << 16)
63#define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1)
64
65#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
f8bd9091 66#define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */
3a4adef5 67#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
01f2e4ea
SF		 68
69/* Supported devices */
9baa3c34 70static const struct pci_device_id enic_id_table[] = {
ea0d7d91 71 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
f8bd9091 72 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) },
3a4adef5 73 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
01f2e4ea
SF		 74 { 0, } /* end of table */
75};
76
77MODULE_DESCRIPTION(DRV_DESCRIPTION);
78MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>");
79MODULE_LICENSE("GPL");
80MODULE_VERSION(DRV_VERSION);
81MODULE_DEVICE_TABLE(pci, enic_id_table);
82
7c2ce6e6
SS		 83#define ENIC_LARGE_PKT_THRESHOLD 1000
84#define ENIC_MAX_COALESCE_TIMERS 10
85/* Interrupt moderation table, which will be used to decide the
86 * coalescing timer values
87 * {rx_rate in Mbps, mapping percentage of the range}
88 */
89struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = {
90 {4000, 0},
91 {4400, 10},
92 {5060, 20},
93 {5230, 30},
94 {5540, 40},
95 {5820, 50},
96 {6120, 60},
97 {6435, 70},
98 {6745, 80},
99 {7000, 90},
100 {0xFFFFFFFF, 100}
101};
102
103/* This table helps the driver to pick different ranges for rx coalescing
104 * timer depending on the link speed.
105 */
106struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = {
107 {0, 0}, /* 0 - 4 Gbps */
108 {0, 3}, /* 4 - 10 Gbps */
109 {3, 6}, /* 10 - 40 Gbps */
110};
111
3f192795 112int enic_is_dynamic(struct enic *enic)
f8bd9091
SF		 113{
114 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN;
115}
116
8749b427
RP		 117int enic_sriov_enabled(struct enic *enic)
118{
119 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0;
120}
121
3a4adef5
RP		 122static int enic_is_sriov_vf(struct enic *enic)
123{
124 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;
125}
126
889d13f5
RP		 127int enic_is_valid_vf(struct enic *enic, int vf)
128{
129#ifdef CONFIG_PCI_IOV
130 return vf >= 0 && vf < enic->num_vfs;
131#else
132 return 0;
133#endif
134}
135
01f2e4ea
SF		 136static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
137{
138 struct enic *enic = vnic_dev_priv(wq->vdev);
139
140 if (buf->sop)
141 pci_unmap_single(enic->pdev, buf->dma_addr,
142 buf->len, PCI_DMA_TODEVICE);
143 else
144 pci_unmap_page(enic->pdev, buf->dma_addr,
145 buf->len, PCI_DMA_TODEVICE);
146
147 if (buf->os_buf)
148 dev_kfree_skb_any(buf->os_buf);
149}
150
151static void enic_wq_free_buf(struct vnic_wq *wq,
152 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque)
153{
154 enic_free_wq_buf(wq, buf);
155}
156
157static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
158 u8 type, u16 q_number, u16 completed_index, void *opaque)
159{
160 struct enic *enic = vnic_dev_priv(vdev);
161
162 spin_lock(&enic->wq_lock[q_number]);
163
164 vnic_wq_service(&enic->wq[q_number], cq_desc,
165 completed_index, enic_wq_free_buf,
166 opaque);
167
822473b6 168 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) &&
ea0d7d91
SF		 169 vnic_wq_desc_avail(&enic->wq[q_number]) >=
170 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS))
822473b6 171 netif_wake_subqueue(enic->netdev, q_number);
01f2e4ea
SF		 172
173 spin_unlock(&enic->wq_lock[q_number]);
174
175 return 0;
176}
177
178static void enic_log_q_error(struct enic *enic)
179{
180 unsigned int i;
181 u32 error_status;
182
183 for (i = 0; i < enic->wq_count; i++) {
184 error_status = vnic_wq_error_status(&enic->wq[i]);
185 if (error_status)
a7a79deb
VK		 186 netdev_err(enic->netdev, "WQ[%d] error_status %d\n",
187 i, error_status);
01f2e4ea
SF		 188 }
189
190 for (i = 0; i < enic->rq_count; i++) {
191 error_status = vnic_rq_error_status(&enic->rq[i]);
192 if (error_status)
a7a79deb
VK		 193 netdev_err(enic->netdev, "RQ[%d] error_status %d\n",
194 i, error_status);
01f2e4ea
SF		 195 }
196}
197
383ab92f 198static void enic_msglvl_check(struct enic *enic)
01f2e4ea 199{
383ab92f 200 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev);
01f2e4ea 201
383ab92f 202 if (msg_enable != enic->msg_enable) {
a7a79deb
VK		 203 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n",
204 enic->msg_enable, msg_enable);
383ab92f 205 enic->msg_enable = msg_enable;
01f2e4ea
SF		 206 }
207}
208
209static void enic_mtu_check(struct enic *enic)
210{
211 u32 mtu = vnic_dev_mtu(enic->vdev);
a7a79deb 212 struct net_device *netdev = enic->netdev;
01f2e4ea 213
491598a4 214 if (mtu && mtu != enic->port_mtu) {
7c844599 215 enic->port_mtu = mtu;
7335903c 216 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
c97c894d
RP		 217 mtu = max_t(int, ENIC_MIN_MTU,
218 min_t(int, ENIC_MAX_MTU, mtu));
219 if (mtu != netdev->mtu)
220 schedule_work(&enic->change_mtu_work);
221 } else {
222 if (mtu < netdev->mtu)
223 netdev_warn(netdev,
224 "interface MTU (%d) set higher "
225 "than switch port MTU (%d)\n",
226 netdev->mtu, mtu);
227 }
01f2e4ea
SF		 228 }
229}
230
383ab92f 231static void enic_link_check(struct enic *enic)
01f2e4ea 232{
383ab92f
VK		 233 int link_status = vnic_dev_link_status(enic->vdev);
234 int carrier_ok = netif_carrier_ok(enic->netdev);
01f2e4ea 235
383ab92f 236 if (link_status && !carrier_ok) {
a7a79deb 237 netdev_info(enic->netdev, "Link UP\n");
383ab92f
VK		 238 netif_carrier_on(enic->netdev);
239 } else if (!link_status && carrier_ok) {
a7a79deb 240 netdev_info(enic->netdev, "Link DOWN\n");
383ab92f 241 netif_carrier_off(enic->netdev);
01f2e4ea
SF		 242 }
243}
244
245static void enic_notify_check(struct enic *enic)
246{
247 enic_msglvl_check(enic);
248 enic_mtu_check(enic);
249 enic_link_check(enic);
250}
251
252#define ENIC_TEST_INTR(pba, i) (pba & (1 << i))
253
254static irqreturn_t enic_isr_legacy(int irq, void *data)
255{
256 struct net_device *netdev = data;
257 struct enic *enic = netdev_priv(netdev);
717258ba
VK		 258 unsigned int io_intr = enic_legacy_io_intr();
259 unsigned int err_intr = enic_legacy_err_intr();
260 unsigned int notify_intr = enic_legacy_notify_intr();
01f2e4ea
SF		 261 u32 pba;
262
717258ba 263 vnic_intr_mask(&enic->intr[io_intr]);
01f2e4ea
SF		 264
265 pba = vnic_intr_legacy_pba(enic->legacy_pba);
266 if (!pba) {
717258ba 267 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 268 return IRQ_NONE; /* not our interrupt */
269 }
270
717258ba
VK		 271 if (ENIC_TEST_INTR(pba, notify_intr)) {
272 vnic_intr_return_all_credits(&enic->intr[notify_intr]);
01f2e4ea 273 enic_notify_check(enic);
ed8af6b2 274 }
01f2e4ea 275
717258ba
VK		 276 if (ENIC_TEST_INTR(pba, err_intr)) {
277 vnic_intr_return_all_credits(&enic->intr[err_intr]);
01f2e4ea
SF		 278 enic_log_q_error(enic);
279 /* schedule recovery from WQ/RQ error */
280 schedule_work(&enic->reset);
281 return IRQ_HANDLED;
282 }
283
717258ba
VK		 284 if (ENIC_TEST_INTR(pba, io_intr)) {
285 if (napi_schedule_prep(&enic->napi[0]))
286 __napi_schedule(&enic->napi[0]);
01f2e4ea 287 } else {
717258ba 288 vnic_intr_unmask(&enic->intr[io_intr]);
01f2e4ea
SF		 289 }
290
291 return IRQ_HANDLED;
292}
293
294static irqreturn_t enic_isr_msi(int irq, void *data)
295{
296 struct enic *enic = data;
297
298 /* With MSI, there is no sharing of interrupts, so this is
299 * our interrupt and there is no need to ack it. The device
300 * is not providing per-vector masking, so the OS will not
301 * write to PCI config space to mask/unmask the interrupt.
302 * We're using mask_on_assertion for MSI, so the device
303 * automatically masks the interrupt when the interrupt is
304 * generated. Later, when exiting polling, the interrupt
305 * will be unmasked (see enic_poll).
306 *
307 * Also, the device uses the same PCIe Traffic Class (TC)
308 * for Memory Write data and MSI, so there are no ordering
309 * issues; the MSI will always arrive at the Root Complex
310 * _after_ corresponding Memory Writes (i.e. descriptor
311 * writes).
312 */
313
717258ba 314 napi_schedule(&enic->napi[0]);
01f2e4ea
SF		 315
316 return IRQ_HANDLED;
317}
318
4cfe8785 319static irqreturn_t enic_isr_msix(int irq, void *data)
01f2e4ea 320{
717258ba 321 struct napi_struct *napi = data;
01f2e4ea 322
717258ba 323 napi_schedule(napi);
01f2e4ea
SF		 324
325 return IRQ_HANDLED;
326}
327
01f2e4ea
SF		 328static irqreturn_t enic_isr_msix_err(int irq, void *data)
329{
330 struct enic *enic = data;
717258ba 331 unsigned int intr = enic_msix_err_intr(enic);
01f2e4ea 332
717258ba 333 vnic_intr_return_all_credits(&enic->intr[intr]);
ed8af6b2 334
01f2e4ea
SF		 335 enic_log_q_error(enic);
336
337 /* schedule recovery from WQ/RQ error */
338 schedule_work(&enic->reset);
339
340 return IRQ_HANDLED;
341}
342
343static irqreturn_t enic_isr_msix_notify(int irq, void *data)
344{
345 struct enic *enic = data;
717258ba 346 unsigned int intr = enic_msix_notify_intr(enic);
01f2e4ea 347
717258ba 348 vnic_intr_return_all_credits(&enic->intr[intr]);
01f2e4ea 349 enic_notify_check(enic);
01f2e4ea
SF		 350
351 return IRQ_HANDLED;
352}
353
354static inline void enic_queue_wq_skb_cont(struct enic *enic,
355 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 356 unsigned int len_left, int loopback)
01f2e4ea 357{
9e903e08 358 const skb_frag_t *frag;
01f2e4ea
SF		 359
360 /* Queue additional data fragments */
361 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08 362 len_left -= skb_frag_size(frag);
01f2e4ea 363 enic_queue_wq_desc_cont(wq, skb,
4bf5adbf 364 skb_frag_dma_map(&enic->pdev->dev,
9e903e08 365 frag, 0, skb_frag_size(frag),
5d6bcdfe 366 DMA_TO_DEVICE),
9e903e08 367 skb_frag_size(frag),
1825aca6
VK		 368 (len_left == 0), /* EOP? */
369 loopback);
01f2e4ea
SF		 370 }
371}
372
373static inline void enic_queue_wq_skb_vlan(struct enic *enic,
374 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 375 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 376{
377 unsigned int head_len = skb_headlen(skb);
378 unsigned int len_left = skb->len - head_len;
379 int eop = (len_left == 0);
380
ea0d7d91
SF		 381 /* Queue the main skb fragment. The fragments are no larger
382 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
383 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
384 * per fragment is queued.
385 */
01f2e4ea
SF		 386 enic_queue_wq_desc(wq, skb,
387 pci_map_single(enic->pdev, skb->data,
388 head_len, PCI_DMA_TODEVICE),
389 head_len,
390 vlan_tag_insert, vlan_tag,
1825aca6 391 eop, loopback);
01f2e4ea
SF		 392
393 if (!eop)
1825aca6 394 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF		 395}
396
397static inline void enic_queue_wq_skb_csum_l4(struct enic *enic,
398 struct vnic_wq *wq, struct sk_buff *skb,
1825aca6 399 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea
SF		 400{
401 unsigned int head_len = skb_headlen(skb);
402 unsigned int len_left = skb->len - head_len;
0d0b1672 403 unsigned int hdr_len = skb_checksum_start_offset(skb);
01f2e4ea
SF		 404 unsigned int csum_offset = hdr_len + skb->csum_offset;
405 int eop = (len_left == 0);
406
ea0d7d91
SF		 407 /* Queue the main skb fragment. The fragments are no larger
408 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less
409 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor
410 * per fragment is queued.
411 */
01f2e4ea
SF		 412 enic_queue_wq_desc_csum_l4(wq, skb,
413 pci_map_single(enic->pdev, skb->data,
414 head_len, PCI_DMA_TODEVICE),
415 head_len,
416 csum_offset,
417 hdr_len,
418 vlan_tag_insert, vlan_tag,
1825aca6 419 eop, loopback);
01f2e4ea
SF		 420
421 if (!eop)
1825aca6 422 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback);
01f2e4ea
SF		 423}
424
425static inline void enic_queue_wq_skb_tso(struct enic *enic,
426 struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss,
1825aca6 427 int vlan_tag_insert, unsigned int vlan_tag, int loopback)
01f2e4ea 428{
ea0d7d91
SF		 429 unsigned int frag_len_left = skb_headlen(skb);
430 unsigned int len_left = skb->len - frag_len_left;
01f2e4ea
SF		 431 unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
432 int eop = (len_left == 0);
ea0d7d91
SF		 433 unsigned int len;
434 dma_addr_t dma_addr;
435 unsigned int offset = 0;
436 skb_frag_t *frag;
01f2e4ea
SF		 437
438 /* Preload TCP csum field with IP pseudo hdr calculated
439 * with IP length set to zero. HW will later add in length
440 * to each TCP segment resulting from the TSO.
441 */
442
09640e63 443 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
01f2e4ea
SF		 444 ip_hdr(skb)->check = 0;
445 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
446 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
09640e63 447 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
01f2e4ea
SF		 448 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
449 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
450 }
451
ea0d7d91
SF		 452 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
453 * for the main skb fragment
454 */
455 while (frag_len_left) {
456 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN);
457 dma_addr = pci_map_single(enic->pdev, skb->data + offset,
458 len, PCI_DMA_TODEVICE);
459 enic_queue_wq_desc_tso(wq, skb,
460 dma_addr,
461 len,
462 mss, hdr_len,
463 vlan_tag_insert, vlan_tag,
1825aca6 464 eop && (len == frag_len_left), loopback);
ea0d7d91
SF		 465 frag_len_left -= len;
466 offset += len;
467 }
01f2e4ea 468
ea0d7d91
SF		 469 if (eop)
470 return;
471
472 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors
473 * for additional data fragments
474 */
475 for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
9e903e08
ED		 476 len_left -= skb_frag_size(frag);
477 frag_len_left = skb_frag_size(frag);
4bf5adbf 478 offset = 0;
ea0d7d91
SF		 479
480 while (frag_len_left) {
481 len = min(frag_len_left,
482 (unsigned int)WQ_ENET_MAX_DESC_LEN);
4bf5adbf
IC		 483 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
484 offset, len,
5d6bcdfe 485 DMA_TO_DEVICE);
ea0d7d91
SF		 486 enic_queue_wq_desc_cont(wq, skb,
487 dma_addr,
488 len,
489 (len_left == 0) &&
1825aca6
VK		 490 (len == frag_len_left), /* EOP? */
491 loopback);
ea0d7d91
SF		 492 frag_len_left -= len;
493 offset += len;
494 }
495 }
01f2e4ea
SF		 496}
497
498static inline void enic_queue_wq_skb(struct enic *enic,
499 struct vnic_wq *wq, struct sk_buff *skb)
500{
501 unsigned int mss = skb_shinfo(skb)->gso_size;
502 unsigned int vlan_tag = 0;
503 int vlan_tag_insert = 0;
1825aca6 504 int loopback = 0;
01f2e4ea 505
eab6d18d 506 if (vlan_tx_tag_present(skb)) {
01f2e4ea
SF		 507 /* VLAN tag from trunking driver */
508 vlan_tag_insert = 1;
509 vlan_tag = vlan_tx_tag_get(skb);
1825aca6
VK		 510 } else if (enic->loop_enable) {
511 vlan_tag = enic->loop_tag;
512 loopback = 1;
01f2e4ea
SF		 513 }
514
515 if (mss)
516 enic_queue_wq_skb_tso(enic, wq, skb, mss,
1825aca6 517 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 518 else if (skb->ip_summed == CHECKSUM_PARTIAL)
519 enic_queue_wq_skb_csum_l4(enic, wq, skb,
1825aca6 520 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 521 else
522 enic_queue_wq_skb_vlan(enic, wq, skb,
1825aca6 523 vlan_tag_insert, vlan_tag, loopback);
01f2e4ea
SF		 524}
525
ed8af6b2 526/* netif_tx_lock held, process context with BHs disabled, or BH */
61357325 527static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb,
d87fd25d 528 struct net_device *netdev)
01f2e4ea
SF		 529{
530 struct enic *enic = netdev_priv(netdev);
822473b6 531 struct vnic_wq *wq;
01f2e4ea 532 unsigned long flags;
822473b6 533 unsigned int txq_map;
01f2e4ea
SF		 534
535 if (skb->len <= 0) {
98d8a65d 536 dev_kfree_skb_any(skb);
01f2e4ea
SF		 537 return NETDEV_TX_OK;
538 }
539
822473b6 540 txq_map = skb_get_queue_mapping(skb) % enic->wq_count;
541 wq = &enic->wq[txq_map];
542
01f2e4ea
SF		 543 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs,
544 * which is very likely. In the off chance it's going to take
545 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb.
546 */
547
548 if (skb_shinfo(skb)->gso_size == 0 &&
549 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC &&
550 skb_linearize(skb)) {
98d8a65d 551 dev_kfree_skb_any(skb);
01f2e4ea
SF		 552 return NETDEV_TX_OK;
553 }
554
822473b6 555 spin_lock_irqsave(&enic->wq_lock[txq_map], flags);
01f2e4ea 556
ea0d7d91
SF		 557 if (vnic_wq_desc_avail(wq) <
558 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) {
822473b6 559 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map));
01f2e4ea 560 /* This is a hard error, log it */
a7a79deb 561 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n");
822473b6 562 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
01f2e4ea
SF		 563 return NETDEV_TX_BUSY;
564 }
565
566 enic_queue_wq_skb(enic, wq, skb);
567
ea0d7d91 568 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)
822473b6 569 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map));
01f2e4ea 570
822473b6 571 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags);
01f2e4ea
SF		 572
573 return NETDEV_TX_OK;
574}
575
576/* dev_base_lock rwlock held, nominally process context */
f20530bc 577static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev,
578 struct rtnl_link_stats64 *net_stats)
01f2e4ea
SF		 579{
580 struct enic *enic = netdev_priv(netdev);
581 struct vnic_stats *stats;
582
383ab92f 583 enic_dev_stats_dump(enic, &stats);
01f2e4ea 584
25f0a061
SF		 585 net_stats->tx_packets = stats->tx.tx_frames_ok;
586 net_stats->tx_bytes = stats->tx.tx_bytes_ok;
587 net_stats->tx_errors = stats->tx.tx_errors;
588 net_stats->tx_dropped = stats->tx.tx_drops;
01f2e4ea 589
25f0a061
SF		 590 net_stats->rx_packets = stats->rx.rx_frames_ok;
591 net_stats->rx_bytes = stats->rx.rx_bytes_ok;
592 net_stats->rx_errors = stats->rx.rx_errors;
593 net_stats->multicast = stats->rx.rx_multicast_frames_ok;
350991e1 594 net_stats->rx_over_errors = enic->rq_truncated_pkts;
bd9fb1a4 595 net_stats->rx_crc_errors = enic->rq_bad_fcs;
350991e1 596 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop;
01f2e4ea 597
25f0a061 598 return net_stats;
01f2e4ea
SF		 599}
600
f009618a
AD		 601static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr)
602{
603 struct enic *enic = netdev_priv(netdev);
604
605 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) {
606 unsigned int mc_count = netdev_mc_count(netdev);
607
608 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n",
609 ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
610
611 return -ENOSPC;
612 }
613
614 enic_dev_add_addr(enic, mc_addr);
615 enic->mc_count++;
616
617 return 0;
618}
619
620static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr)
621{
622 struct enic *enic = netdev_priv(netdev);
623
624 enic_dev_del_addr(enic, mc_addr);
625 enic->mc_count--;
626
627 return 0;
628}
629
630static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr)
631{
632 struct enic *enic = netdev_priv(netdev);
633
634 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) {
635 unsigned int uc_count = netdev_uc_count(netdev);
636
637 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n",
638 ENIC_UNICAST_PERFECT_FILTERS, uc_count);
639
640 return -ENOSPC;
641 }
642
643 enic_dev_add_addr(enic, uc_addr);
644 enic->uc_count++;
645
646 return 0;
647}
648
649static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr)
650{
651 struct enic *enic = netdev_priv(netdev);
652
653 enic_dev_del_addr(enic, uc_addr);
654 enic->uc_count--;
655
656 return 0;
657}
658
b3abfbd2 659void enic_reset_addr_lists(struct enic *enic)
01f2e4ea 660{
f009618a
AD		 661 struct net_device *netdev = enic->netdev;
662
663 __dev_uc_unsync(netdev, NULL);
664 __dev_mc_unsync(netdev, NULL);
665
01f2e4ea 666 enic->mc_count = 0;
e0afe53f 667 enic->uc_count = 0;
99ef5639 668 enic->flags = 0;
01f2e4ea
SF		 669}
670
671static int enic_set_mac_addr(struct net_device *netdev, char *addr)
672{
f8bd9091
SF		 673 struct enic *enic = netdev_priv(netdev);
674
7335903c 675 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) {
f8bd9091
SF		 676 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr))
677 return -EADDRNOTAVAIL;
678 } else {
679 if (!is_valid_ether_addr(addr))
680 return -EADDRNOTAVAIL;
681 }
01f2e4ea
SF		 682
683 memcpy(netdev->dev_addr, addr, netdev->addr_len);
684
685 return 0;
686}
687
f8bd9091
SF		 688static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p)
689{
690 struct enic *enic = netdev_priv(netdev);
691 struct sockaddr *saddr = p;
692 char *addr = saddr->sa_data;
693 int err;
694
695 if (netif_running(enic->netdev)) {
696 err = enic_dev_del_station_addr(enic);
697 if (err)
698 return err;
699 }
700
701 err = enic_set_mac_addr(netdev, addr);
702 if (err)
703 return err;
704
705 if (netif_running(enic->netdev)) {
706 err = enic_dev_add_station_addr(enic);
707 if (err)
708 return err;
709 }
710
711 return err;
712}
713
714static int enic_set_mac_address(struct net_device *netdev, void *p)
715{
294dab25 716 struct sockaddr *saddr = p;
c76fd32d
VK		 717 char *addr = saddr->sa_data;
718 struct enic *enic = netdev_priv(netdev);
719 int err;
720
721 err = enic_dev_del_station_addr(enic);
722 if (err)
723 return err;
724
725 err = enic_set_mac_addr(netdev, addr);
726 if (err)
727 return err;
294dab25 728
c76fd32d 729 return enic_dev_add_station_addr(enic);
f8bd9091
SF		 730}
731
319d7e84
RP		 732/* netif_tx_lock held, BHs disabled */
733static void enic_set_rx_mode(struct net_device *netdev)
734{
735 struct enic *enic = netdev_priv(netdev);
736 int directed = 1;
737 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
738 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
739 int promisc = (netdev->flags & IFF_PROMISC) ||
740 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
741 int allmulti = (netdev->flags & IFF_ALLMULTI) ||
742 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
743 unsigned int flags = netdev->flags |
744 (allmulti ? IFF_ALLMULTI : 0) |
745 (promisc ? IFF_PROMISC : 0);
746
747 if (enic->flags != flags) {
748 enic->flags = flags;
749 enic_dev_packet_filter(enic, directed,
750 multicast, broadcast, promisc, allmulti);
751 }
752
753 if (!promisc) {
f009618a 754 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync);
319d7e84 755 if (!allmulti)
f009618a 756 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync);
319d7e84
RP		 757 }
758}
759
01f2e4ea
SF		 760/* netif_tx_lock held, BHs disabled */
761static void enic_tx_timeout(struct net_device *netdev)
762{
763 struct enic *enic = netdev_priv(netdev);
764 schedule_work(&enic->reset);
765}
766
0b1c00fc
RP		 767static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
768{
769 struct enic *enic = netdev_priv(netdev);
3f192795
RP		 770 struct enic_port_profile *pp;
771 int err;
0b1c00fc 772
3f192795
RP		 773 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
774 if (err)
775 return err;
0b1c00fc 776
b8622cbd 777 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) {
b4765833
RP		 778 if (vf == PORT_SELF_VF) {
779 memcpy(pp->vf_mac, mac, ETH_ALEN);
780 return 0;
781 } else {
782 /*
783 * For sriov vf's set the mac in hw
784 */
785 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
786 vnic_dev_set_mac_addr, mac);
787 return enic_dev_status_to_errno(err);
788 }
0b1c00fc
RP		 789 } else
790 return -EINVAL;
791}
792
f8bd9091
SF		 793static int enic_set_vf_port(struct net_device *netdev, int vf,
794 struct nlattr *port[])
795{
796 struct enic *enic = netdev_priv(netdev);
b3abfbd2 797 struct enic_port_profile prev_pp;
3f192795 798 struct enic_port_profile *pp;
b3abfbd2 799 int err = 0, restore_pp = 1;
08f382eb 800
3f192795
RP		 801 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
802 if (err)
803 return err;
08f382eb 804
b3abfbd2
RP		 805 if (!port[IFLA_PORT_REQUEST])
806 return -EOPNOTSUPP;
807
3f192795
RP		 808 memcpy(&prev_pp, pp, sizeof(*enic->pp));
809 memset(pp, 0, sizeof(*enic->pp));
b3abfbd2 810
3f192795
RP		 811 pp->set |= ENIC_SET_REQUEST;
812 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]);
08f382eb
SF		 813
814 if (port[IFLA_PORT_PROFILE]) {
3f192795
RP		 815 pp->set |= ENIC_SET_NAME;
816 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]),
08f382eb
SF		 817 PORT_PROFILE_MAX);
818 }
819
820 if (port[IFLA_PORT_INSTANCE_UUID]) {
3f192795
RP		 821 pp->set |= ENIC_SET_INSTANCE;
822 memcpy(pp->instance_uuid,
08f382eb
SF		 823 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
824 }
825
826 if (port[IFLA_PORT_HOST_UUID]) {
3f192795
RP		 827 pp->set |= ENIC_SET_HOST;
828 memcpy(pp->host_uuid,
08f382eb
SF		 829 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
830 }
f8bd9091 831
b4765833
RP		 832 if (vf == PORT_SELF_VF) {
833 /* Special case handling: mac came from IFLA_VF_MAC */
834 if (!is_zero_ether_addr(prev_pp.vf_mac))
835 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN);
418c437d 836
b4765833
RP		 837 if (is_zero_ether_addr(netdev->dev_addr))
838 eth_hw_addr_random(netdev);
839 } else {
840 /* SR-IOV VF: get mac from adapter */
841 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic,
842 vnic_dev_get_mac_addr, pp->mac_addr);
843 if (err) {
844 netdev_err(netdev, "Error getting mac for vf %d\n", vf);
845 memcpy(pp, &prev_pp, sizeof(*pp));
846 return enic_dev_status_to_errno(err);
847 }
848 }
f8bd9091 849
3f192795 850 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp);
b3abfbd2
RP		 851 if (err) {
852 if (restore_pp) {
853 /* Things are still the way they were: Implicit
854 * DISASSOCIATE failed
855 */
3f192795 856 memcpy(pp, &prev_pp, sizeof(*pp));
b3abfbd2 857 } else {
3f192795
RP		 858 memset(pp, 0, sizeof(*pp));
859 if (vf == PORT_SELF_VF)
860 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP		 861 }
862 } else {
863 /* Set flag to indicate that the port assoc/disassoc
864 * request has been sent out to fw
865 */
3f192795 866 pp->set |= ENIC_PORT_REQUEST_APPLIED;
b3abfbd2
RP		 867
868 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */
3f192795
RP		 869 if (pp->request == PORT_REQUEST_DISASSOCIATE) {
870 memset(pp->mac_addr, 0, ETH_ALEN);
871 if (vf == PORT_SELF_VF)
872 memset(netdev->dev_addr, 0, ETH_ALEN);
b3abfbd2
RP		 873 }
874 }
29639059 875
b4765833
RP		 876 if (vf == PORT_SELF_VF)
877 memset(pp->vf_mac, 0, ETH_ALEN);
29639059 878
29639059 879 return err;
f8bd9091
SF		 880}
881
882static int enic_get_vf_port(struct net_device *netdev, int vf,
883 struct sk_buff *skb)
884{
885 struct enic *enic = netdev_priv(netdev);
f8bd9091 886 u16 response = PORT_PROFILE_RESPONSE_SUCCESS;
3f192795 887 struct enic_port_profile *pp;
b3abfbd2 888 int err;
f8bd9091 889
3f192795
RP		 890 ENIC_PP_BY_INDEX(enic, vf, pp, &err);
891 if (err)
892 return err;
893
894 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED))
08f382eb 895 return -ENODATA;
f8bd9091 896
3f192795 897 err = enic_process_get_pp_request(enic, vf, pp->request, &response);
f8bd9091 898 if (err)
b3abfbd2 899 return err;
f8bd9091 900
1a106de6
DM		 901 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) ||
902 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) ||
903 ((pp->set & ENIC_SET_NAME) &&
904 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) ||
905 ((pp->set & ENIC_SET_INSTANCE) &&
906 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX,
907 pp->instance_uuid)) ||
908 ((pp->set & ENIC_SET_HOST) &&
909 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid)))
910 goto nla_put_failure;
f8bd9091
SF		 911 return 0;
912
913nla_put_failure:
914 return -EMSGSIZE;
915}
916
01f2e4ea
SF		 917static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
918{
919 struct enic *enic = vnic_dev_priv(rq->vdev);
920
921 if (!buf->os_buf)
922 return;
923
924 pci_unmap_single(enic->pdev, buf->dma_addr,
925 buf->len, PCI_DMA_FROMDEVICE);
926 dev_kfree_skb_any(buf->os_buf);
927}
928
01f2e4ea
SF		 929static int enic_rq_alloc_buf(struct vnic_rq *rq)
930{
931 struct enic *enic = vnic_dev_priv(rq->vdev);
d19e22dc 932 struct net_device *netdev = enic->netdev;
01f2e4ea 933 struct sk_buff *skb;
1825aca6 934 unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
01f2e4ea
SF		 935 unsigned int os_buf_index = 0;
936 dma_addr_t dma_addr;
937
89d71a66 938 skb = netdev_alloc_skb_ip_align(netdev, len);
01f2e4ea
SF		 939 if (!skb)
940 return -ENOMEM;
941
942 dma_addr = pci_map_single(enic->pdev, skb->data,
943 len, PCI_DMA_FROMDEVICE);
944
945 enic_queue_rq_desc(rq, skb, os_buf_index,
946 dma_addr, len);
947
948 return 0;
949}
950
7c2ce6e6
SS		 951static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
952 u32 pkt_len)
953{
954 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len)
955 pkt_size->large_pkt_bytes_cnt += pkt_len;
956 else
957 pkt_size->small_pkt_bytes_cnt += pkt_len;
958}
959
01f2e4ea
SF		 960static void enic_rq_indicate_buf(struct vnic_rq *rq,
961 struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
962 int skipped, void *opaque)
963{
964 struct enic *enic = vnic_dev_priv(rq->vdev);
86ca9db7 965 struct net_device *netdev = enic->netdev;
01f2e4ea 966 struct sk_buff *skb;
7c2ce6e6 967 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
01f2e4ea
SF		 968
969 u8 type, color, eop, sop, ingress_port, vlan_stripped;
970 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;
971 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;
972 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;
973 u8 packet_error;
f8cac14a 974 u16 q_number, completed_index, bytes_written, vlan_tci, checksum;
01f2e4ea
SF		 975 u32 rss_hash;
976
977 if (skipped)
978 return;
979
980 skb = buf->os_buf;
981 prefetch(skb->data - NET_IP_ALIGN);
982 pci_unmap_single(enic->pdev, buf->dma_addr,
983 buf->len, PCI_DMA_FROMDEVICE);
984
985 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
986 &type, &color, &q_number, &completed_index,
987 &ingress_port, &fcoe, &eop, &sop, &rss_type,
988 &csum_not_calc, &rss_hash, &bytes_written,
f8cac14a 989 &packet_error, &vlan_stripped, &vlan_tci, &checksum,
01f2e4ea
SF		 990 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,
991 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,
992 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,
993 &fcs_ok);
994
995 if (packet_error) {
996
350991e1
SF		 997 if (!fcs_ok) {
998 if (bytes_written > 0)
999 enic->rq_bad_fcs++;
1000 else if (bytes_written == 0)
1001 enic->rq_truncated_pkts++;
1002 }
01f2e4ea
SF		 1003
1004 dev_kfree_skb_any(skb);
1005
1006 return;
1007 }
1008
1009 if (eop && bytes_written > 0) {
1010
1011 /* Good receive
1012 */
1013
1014 skb_put(skb, bytes_written);
86ca9db7 1015 skb->protocol = eth_type_trans(skb, netdev);
bf751ba8 1016 skb_record_rx_queue(skb, q_number);
1017 if (netdev->features & NETIF_F_RXHASH) {
3739acdd
TH		 1018 skb_set_hash(skb, rss_hash,
1019 (rss_type &
1020 (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX |
1021 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 |
1022 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ?
1023 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
bf751ba8 1024 }
01f2e4ea 1025
5ec8f9b8 1026 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc) {
01f2e4ea
SF		 1027 skb->csum = htons(checksum);
1028 skb->ip_summed = CHECKSUM_COMPLETE;
1029 }
1030
6ede746b 1031 if (vlan_stripped)
86a9bad3 1032 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
01f2e4ea 1033
14747cd9
GV		 1034 skb_mark_napi_id(skb, &enic->napi[rq->index]);
1035 if (enic_poll_busy_polling(rq) ||
1036 !(netdev->features & NETIF_F_GRO))
6ede746b 1037 netif_receive_skb(skb);
14747cd9
GV		 1038 else
1039 napi_gro_receive(&enic->napi[q_number], skb);
7c2ce6e6
SS		 1040 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1041 enic_intr_update_pkt_size(&cq->pkt_size_counter,
1042 bytes_written);
01f2e4ea
SF		 1043 } else {
1044
1045 /* Buffer overflow
1046 */
1047
1048 dev_kfree_skb_any(skb);
1049 }
1050}
1051
1052static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
1053 u8 type, u16 q_number, u16 completed_index, void *opaque)
1054{
1055 struct enic *enic = vnic_dev_priv(vdev);
1056
1057 vnic_rq_service(&enic->rq[q_number], cq_desc,
1058 completed_index, VNIC_RQ_RETURN_DESC,
1059 enic_rq_indicate_buf, opaque);
1060
1061 return 0;
1062}
1063
01f2e4ea
SF		 1064static int enic_poll(struct napi_struct *napi, int budget)
1065{
717258ba
VK		 1066 struct net_device *netdev = napi->dev;
1067 struct enic *enic = netdev_priv(netdev);
1068 unsigned int cq_rq = enic_cq_rq(enic, 0);
1069 unsigned int cq_wq = enic_cq_wq(enic, 0);
1070 unsigned int intr = enic_legacy_io_intr();
01f2e4ea
SF		 1071 unsigned int rq_work_to_do = budget;
1072 unsigned int wq_work_to_do = -1; /* no limit */
4c502549 1073 unsigned int work_done, rq_work_done = 0, wq_work_done;
2d6ddced 1074 int err;
01f2e4ea 1075
14747cd9
GV		 1076 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do,
1077 enic_wq_service, NULL);
1078
1079 if (!enic_poll_lock_napi(&enic->rq[cq_rq])) {
1080 if (wq_work_done > 0)
1081 vnic_intr_return_credits(&enic->intr[intr],
1082 wq_work_done,
1083 0 /* dont unmask intr */,
1084 0 /* dont reset intr timer */);
1085 return rq_work_done;
1086 }
01f2e4ea 1087
4c502549
EB		 1088 if (budget > 0)
1089 rq_work_done = vnic_cq_service(&enic->cq[cq_rq],
1090 rq_work_to_do, enic_rq_service, NULL);
01f2e4ea 1091
01f2e4ea
SF		 1092 /* Accumulate intr event credits for this polling
1093 * cycle. An intr event is the completion of a
1094 * a WQ or RQ packet.
1095 */
1096
1097 work_done = rq_work_done + wq_work_done;
1098
1099 if (work_done > 0)
717258ba 1100 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1101 work_done,
1102 0 /* don't unmask intr */,
1103 0 /* don't reset intr timer */);
1104
0eb26022 1105 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
01f2e4ea 1106
2d6ddced
SF		 1107 /* Buffer allocation failed. Stay in polling
1108 * mode so we can try to fill the ring again.
1109 */
01f2e4ea 1110
2d6ddced
SF		 1111 if (err)
1112 rq_work_done = rq_work_to_do;
01f2e4ea 1113
2d6ddced 1114 if (rq_work_done < rq_work_to_do) {
01f2e4ea 1115
2d6ddced 1116 /* Some work done, but not enough to stay in polling,
88132f55 1117 * exit polling
01f2e4ea
SF		 1118 */
1119
288379f0 1120 napi_complete(napi);
717258ba 1121 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1122 }
14747cd9 1123 enic_poll_unlock_napi(&enic->rq[cq_rq]);
01f2e4ea
SF		 1124
1125 return rq_work_done;
1126}
1127
7c2ce6e6
SS		 1128static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq)
1129{
1130 unsigned int intr = enic_msix_rq_intr(enic, rq->index);
1131 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1132 u32 timer = cq->tobe_rx_coal_timeval;
1133
1134 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) {
1135 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer);
1136 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval;
1137 }
1138}
1139
1140static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq)
1141{
1142 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1143 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)];
1144 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter;
1145 int index;
1146 u32 timer;
1147 u32 range_start;
1148 u32 traffic;
1149 u64 delta;
1150 ktime_t now = ktime_get();
1151
1152 delta = ktime_us_delta(now, cq->prev_ts);
1153 if (delta < ENIC_AIC_TS_BREAK)
1154 return;
1155 cq->prev_ts = now;
1156
1157 traffic = pkt_size_counter->large_pkt_bytes_cnt +
1158 pkt_size_counter->small_pkt_bytes_cnt;
1159 /* The table takes Mbps
1160 * traffic *= 8 => bits
1161 * traffic *= (10^6 / delta) => bps
1162 * traffic /= 10^6 => Mbps
1163 *
1164 * Combining, traffic *= (8 / delta)
1165 */
1166
1167 traffic <<= 3;
958c492c 1168 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta;
7c2ce6e6
SS		 1169
1170 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++)
1171 if (traffic < mod_table[index].rx_rate)
1172 break;
1173 range_start = (pkt_size_counter->small_pkt_bytes_cnt >
1174 pkt_size_counter->large_pkt_bytes_cnt << 1) ?
1175 rx_coal->small_pkt_range_start :
1176 rx_coal->large_pkt_range_start;
1177 timer = range_start + ((rx_coal->range_end - range_start) *
1178 mod_table[index].range_percent / 100);
1179 /* Damping */
1180 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1;
1181
1182 pkt_size_counter->large_pkt_bytes_cnt = 0;
1183 pkt_size_counter->small_pkt_bytes_cnt = 0;
1184}
1185
b6e97c13
GV		 1186#ifdef CONFIG_RFS_ACCEL
1187static void enic_free_rx_cpu_rmap(struct enic *enic)
1188{
1189 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap);
1190 enic->netdev->rx_cpu_rmap = NULL;
1191}
1192
1193static void enic_set_rx_cpu_rmap(struct enic *enic)
1194{
1195 int i, res;
1196
1197 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) {
1198 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count);
1199 if (unlikely(!enic->netdev->rx_cpu_rmap))
1200 return;
1201 for (i = 0; i < enic->rq_count; i++) {
1202 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap,
1203 enic->msix_entry[i].vector);
1204 if (unlikely(res)) {
1205 enic_free_rx_cpu_rmap(enic);
1206 return;
1207 }
1208 }
1209 }
1210}
1211
1212#else
1213
1214static void enic_free_rx_cpu_rmap(struct enic *enic)
1215{
1216}
1217
1218static void enic_set_rx_cpu_rmap(struct enic *enic)
1219{
1220}
1221
1222#endif /* CONFIG_RFS_ACCEL */
1223
14747cd9
GV		 1224#ifdef CONFIG_NET_RX_BUSY_POLL
1225int enic_busy_poll(struct napi_struct *napi)
1226{
1227 struct net_device *netdev = napi->dev;
1228 struct enic *enic = netdev_priv(netdev);
1229 unsigned int rq = (napi - &enic->napi[0]);
1230 unsigned int cq = enic_cq_rq(enic, rq);
1231 unsigned int intr = enic_msix_rq_intr(enic, rq);
1232 unsigned int work_to_do = -1; /* clean all pkts possible */
1233 unsigned int work_done;
1234
1235 if (!enic_poll_lock_poll(&enic->rq[rq]))
1236 return LL_FLUSH_BUSY;
1237 work_done = vnic_cq_service(&enic->cq[cq], work_to_do,
1238 enic_rq_service, NULL);
1239
1240 if (work_done > 0)
1241 vnic_intr_return_credits(&enic->intr[intr],
1242 work_done, 0, 0);
1243 vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
1244 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1245 enic_calc_int_moderation(enic, &enic->rq[rq]);
1246 enic_poll_unlock_poll(&enic->rq[rq]);
1247
1248 return work_done;
1249}
1250#endif /* CONFIG_NET_RX_BUSY_POLL */
1251
4cfe8785
GV		 1252static int enic_poll_msix_wq(struct napi_struct *napi, int budget)
1253{
1254 struct net_device *netdev = napi->dev;
1255 struct enic *enic = netdev_priv(netdev);
1256 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count;
1257 struct vnic_wq *wq = &enic->wq[wq_index];
1258 unsigned int cq;
1259 unsigned int intr;
1260 unsigned int wq_work_to_do = -1; /* clean all desc possible */
1261 unsigned int wq_work_done;
1262 unsigned int wq_irq;
1263
1264 wq_irq = wq->index;
1265 cq = enic_cq_wq(enic, wq_irq);
1266 intr = enic_msix_wq_intr(enic, wq_irq);
1267 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do,
1268 enic_wq_service, NULL);
1269
1270 vnic_intr_return_credits(&enic->intr[intr], wq_work_done,
1271 0 /* don't unmask intr */,
1272 1 /* reset intr timer */);
1273 if (!wq_work_done) {
1274 napi_complete(napi);
1275 vnic_intr_unmask(&enic->intr[intr]);
1276 }
1277
1278 return 0;
1279}
1280
1281static int enic_poll_msix_rq(struct napi_struct *napi, int budget)
01f2e4ea 1282{
717258ba
VK		 1283 struct net_device *netdev = napi->dev;
1284 struct enic *enic = netdev_priv(netdev);
1285 unsigned int rq = (napi - &enic->napi[0]);
1286 unsigned int cq = enic_cq_rq(enic, rq);
1287 unsigned int intr = enic_msix_rq_intr(enic, rq);
01f2e4ea 1288 unsigned int work_to_do = budget;
4c502549 1289 unsigned int work_done = 0;
2d6ddced 1290 int err;
01f2e4ea 1291
14747cd9
GV		 1292 if (!enic_poll_lock_napi(&enic->rq[rq]))
1293 return work_done;
01f2e4ea
SF		 1294 /* Service RQ
1295 */
1296
4c502549
EB		 1297 if (budget > 0)
1298 work_done = vnic_cq_service(&enic->cq[cq],
1299 work_to_do, enic_rq_service, NULL);
01f2e4ea 1300
2d6ddced
SF		 1301 /* Return intr event credits for this polling
1302 * cycle. An intr event is the completion of a
1303 * RQ packet.
1304 */
01f2e4ea 1305
2d6ddced 1306 if (work_done > 0)
717258ba 1307 vnic_intr_return_credits(&enic->intr[intr],
01f2e4ea
SF		 1308 work_done,
1309 0 /* don't unmask intr */,
1310 0 /* don't reset intr timer */);
01f2e4ea 1311
0eb26022 1312 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf);
2d6ddced
SF		 1313
1314 /* Buffer allocation failed. Stay in polling mode
1315 * so we can try to fill the ring again.
1316 */
1317
1318 if (err)
1319 work_done = work_to_do;
7c2ce6e6
SS		 1320 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1321 /* Call the function which refreshes
1322 * the intr coalescing timer value based on
1323 * the traffic. This is supported only in
1324 * the case of MSI-x mode
1325 */
1326 enic_calc_int_moderation(enic, &enic->rq[rq]);
2d6ddced
SF		 1327
1328 if (work_done < work_to_do) {
1329
1330 /* Some work done, but not enough to stay in polling,
88132f55 1331 * exit polling
01f2e4ea
SF		 1332 */
1333
288379f0 1334 napi_complete(napi);
7c2ce6e6
SS		 1335 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce)
1336 enic_set_int_moderation(enic, &enic->rq[rq]);
717258ba 1337 vnic_intr_unmask(&enic->intr[intr]);
01f2e4ea 1338 }
14747cd9 1339 enic_poll_unlock_napi(&enic->rq[rq]);
01f2e4ea
SF		 1340
1341 return work_done;
1342}
1343
1344static void enic_notify_timer(unsigned long data)
1345{
1346 struct enic *enic = (struct enic *)data;
1347
1348 enic_notify_check(enic);
1349
25f0a061
SF		 1350 mod_timer(&enic->notify_timer,
1351 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD));
01f2e4ea
SF		 1352}
1353
1354static void enic_free_intr(struct enic *enic)
1355{
1356 struct net_device *netdev = enic->netdev;
1357 unsigned int i;
1358
b6e97c13 1359 enic_free_rx_cpu_rmap(enic);
01f2e4ea
SF		 1360 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1361 case VNIC_DEV_INTR_MODE_INTX:
01f2e4ea
SF		 1362 free_irq(enic->pdev->irq, netdev);
1363 break;
8f4d248c
SF		 1364 case VNIC_DEV_INTR_MODE_MSI:
1365 free_irq(enic->pdev->irq, enic);
1366 break;
01f2e4ea
SF		 1367 case VNIC_DEV_INTR_MODE_MSIX:
1368 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1369 if (enic->msix[i].requested)
1370 free_irq(enic->msix_entry[i].vector,
1371 enic->msix[i].devid);
1372 break;
1373 default:
1374 break;
1375 }
1376}
1377
1378static int enic_request_intr(struct enic *enic)
1379{
1380 struct net_device *netdev = enic->netdev;
717258ba 1381 unsigned int i, intr;
01f2e4ea
SF		 1382 int err = 0;
1383
b6e97c13 1384 enic_set_rx_cpu_rmap(enic);
01f2e4ea
SF		 1385 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1386
1387 case VNIC_DEV_INTR_MODE_INTX:
1388
1389 err = request_irq(enic->pdev->irq, enic_isr_legacy,
1390 IRQF_SHARED, netdev->name, netdev);
1391 break;
1392
1393 case VNIC_DEV_INTR_MODE_MSI:
1394
1395 err = request_irq(enic->pdev->irq, enic_isr_msi,
1396 0, netdev->name, enic);
1397 break;
1398
1399 case VNIC_DEV_INTR_MODE_MSIX:
1400
717258ba
VK		 1401 for (i = 0; i < enic->rq_count; i++) {
1402 intr = enic_msix_rq_intr(enic, i);
4505f40a
DC		 1403 snprintf(enic->msix[intr].devname,
1404 sizeof(enic->msix[intr].devname),
717258ba 1405 "%.11s-rx-%d", netdev->name, i);
4cfe8785 1406 enic->msix[intr].isr = enic_isr_msix;
717258ba
VK		 1407 enic->msix[intr].devid = &enic->napi[i];
1408 }
01f2e4ea 1409
717258ba 1410 for (i = 0; i < enic->wq_count; i++) {
4cfe8785
GV		 1411 int wq = enic_cq_wq(enic, i);
1412
717258ba 1413 intr = enic_msix_wq_intr(enic, i);
4505f40a
DC		 1414 snprintf(enic->msix[intr].devname,
1415 sizeof(enic->msix[intr].devname),
717258ba 1416 "%.11s-tx-%d", netdev->name, i);
4cfe8785
GV		 1417 enic->msix[intr].isr = enic_isr_msix;
1418 enic->msix[intr].devid = &enic->napi[wq];
717258ba 1419 }
01f2e4ea 1420
717258ba 1421 intr = enic_msix_err_intr(enic);
4505f40a
DC		 1422 snprintf(enic->msix[intr].devname,
1423 sizeof(enic->msix[intr].devname),
01f2e4ea 1424 "%.11s-err", netdev->name);
717258ba
VK		 1425 enic->msix[intr].isr = enic_isr_msix_err;
1426 enic->msix[intr].devid = enic;
01f2e4ea 1427
717258ba 1428 intr = enic_msix_notify_intr(enic);
4505f40a
DC		 1429 snprintf(enic->msix[intr].devname,
1430 sizeof(enic->msix[intr].devname),
01f2e4ea 1431 "%.11s-notify", netdev->name);
717258ba
VK		 1432 enic->msix[intr].isr = enic_isr_msix_notify;
1433 enic->msix[intr].devid = enic;
1434
1435 for (i = 0; i < ARRAY_SIZE(enic->msix); i++)
1436 enic->msix[i].requested = 0;
01f2e4ea 1437
717258ba 1438 for (i = 0; i < enic->intr_count; i++) {
01f2e4ea
SF		 1439 err = request_irq(enic->msix_entry[i].vector,
1440 enic->msix[i].isr, 0,
1441 enic->msix[i].devname,
1442 enic->msix[i].devid);
1443 if (err) {
1444 enic_free_intr(enic);
1445 break;
1446 }
1447 enic->msix[i].requested = 1;
1448 }
1449
1450 break;
1451
1452 default:
1453 break;
1454 }
1455
1456 return err;
1457}
1458
b3d18d19
SF		 1459static void enic_synchronize_irqs(struct enic *enic)
1460{
1461 unsigned int i;
1462
1463 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1464 case VNIC_DEV_INTR_MODE_INTX:
1465 case VNIC_DEV_INTR_MODE_MSI:
1466 synchronize_irq(enic->pdev->irq);
1467 break;
1468 case VNIC_DEV_INTR_MODE_MSIX:
1469 for (i = 0; i < enic->intr_count; i++)
1470 synchronize_irq(enic->msix_entry[i].vector);
1471 break;
1472 default:
1473 break;
1474 }
1475}
1476
7c2ce6e6
SS		 1477static void enic_set_rx_coal_setting(struct enic *enic)
1478{
1479 unsigned int speed;
1480 int index = -1;
1481 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting;
1482
1483 /* If intr mode is not MSIX, do not do adaptive coalescing */
1484 if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) {
1485 netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing");
1486 return;
1487 }
1488
1489 /* 1. Read the link speed from fw
1490 * 2. Pick the default range for the speed
1491 * 3. Update it in enic->rx_coalesce_setting
1492 */
1493 speed = vnic_dev_port_speed(enic->vdev);
1494 if (ENIC_LINK_SPEED_10G < speed)
1495 index = ENIC_LINK_40G_INDEX;
1496 else if (ENIC_LINK_SPEED_4G < speed)
1497 index = ENIC_LINK_10G_INDEX;
1498 else
1499 index = ENIC_LINK_4G_INDEX;
1500
1501 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start;
1502 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start;
1503 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END;
1504
1505 /* Start with the value provided by UCSM */
1506 for (index = 0; index < enic->rq_count; index++)
1507 enic->cq[index].cur_rx_coal_timeval =
1508 enic->config.intr_timer_usec;
1509
1510 rx_coal->use_adaptive_rx_coalesce = 1;
1511}
1512
383ab92f 1513static int enic_dev_notify_set(struct enic *enic)
01f2e4ea
SF		 1514{
1515 int err;
1516
8e091340 1517 spin_lock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1518 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1519 case VNIC_DEV_INTR_MODE_INTX:
717258ba
VK		 1520 err = vnic_dev_notify_set(enic->vdev,
1521 enic_legacy_notify_intr());
01f2e4ea
SF		 1522 break;
1523 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1524 err = vnic_dev_notify_set(enic->vdev,
1525 enic_msix_notify_intr(enic));
01f2e4ea
SF		 1526 break;
1527 default:
1528 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */);
1529 break;
1530 }
8e091340 1531 spin_unlock_bh(&enic->devcmd_lock);
01f2e4ea
SF		 1532
1533 return err;
1534}
1535
1536static void enic_notify_timer_start(struct enic *enic)
1537{
1538 switch (vnic_dev_get_intr_mode(enic->vdev)) {
1539 case VNIC_DEV_INTR_MODE_MSI:
1540 mod_timer(&enic->notify_timer, jiffies);
1541 break;
1542 default:
1543 /* Using intr for notification for INTx/MSI-X */
1544 break;
6403eab1 1545 }
01f2e4ea
SF		 1546}
1547
1548/* rtnl lock is held, process context */
1549static int enic_open(struct net_device *netdev)
1550{
1551 struct enic *enic = netdev_priv(netdev);
1552 unsigned int i;
1553 int err;
1554
4b75a442
SF		 1555 err = enic_request_intr(enic);
1556 if (err) {
a7a79deb 1557 netdev_err(netdev, "Unable to request irq.\n");
4b75a442
SF		 1558 return err;
1559 }
1560
383ab92f 1561 err = enic_dev_notify_set(enic);
4b75a442 1562 if (err) {
a7a79deb
VK		 1563 netdev_err(netdev,
1564 "Failed to alloc notify buffer, aborting.\n");
4b75a442
SF		 1565 goto err_out_free_intr;
1566 }
1567
01f2e4ea 1568 for (i = 0; i < enic->rq_count; i++) {
0eb26022 1569 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf);
2d6ddced
SF		 1570 /* Need at least one buffer on ring to get going */
1571 if (vnic_rq_desc_used(&enic->rq[i]) == 0) {
a7a79deb 1572 netdev_err(netdev, "Unable to alloc receive buffers\n");
2d6ddced 1573 err = -ENOMEM;
4b75a442 1574 goto err_out_notify_unset;
01f2e4ea
SF		 1575 }
1576 }
1577
1578 for (i = 0; i < enic->wq_count; i++)
1579 vnic_wq_enable(&enic->wq[i]);
1580 for (i = 0; i < enic->rq_count; i++)
1581 vnic_rq_enable(&enic->rq[i]);
1582
7335903c 1583 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1584 enic_dev_add_station_addr(enic);
3f192795 1585
319d7e84 1586 enic_set_rx_mode(netdev);
01f2e4ea 1587
822473b6 1588 netif_tx_wake_all_queues(netdev);
717258ba 1589
14747cd9
GV		 1590 for (i = 0; i < enic->rq_count; i++) {
1591 enic_busy_poll_init_lock(&enic->rq[i]);
717258ba 1592 napi_enable(&enic->napi[i]);
14747cd9 1593 }
4cfe8785
GV		 1594 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1595 for (i = 0; i < enic->wq_count; i++)
1596 napi_enable(&enic->napi[enic_cq_wq(enic, i)]);
383ab92f 1597 enic_dev_enable(enic);
01f2e4ea
SF		 1598
1599 for (i = 0; i < enic->intr_count; i++)
1600 vnic_intr_unmask(&enic->intr[i]);
1601
1602 enic_notify_timer_start(enic);
a145df23 1603 enic_rfs_flw_tbl_init(enic);
01f2e4ea
SF		 1604
1605 return 0;
4b75a442
SF		 1606
1607err_out_notify_unset:
383ab92f 1608 enic_dev_notify_unset(enic);
4b75a442
SF		 1609err_out_free_intr:
1610 enic_free_intr(enic);
1611
1612 return err;
01f2e4ea
SF		 1613}
1614
1615/* rtnl lock is held, process context */
1616static int enic_stop(struct net_device *netdev)
1617{
1618 struct enic *enic = netdev_priv(netdev);
1619 unsigned int i;
1620 int err;
1621
29046f9b 1622 for (i = 0; i < enic->intr_count; i++) {
b3d18d19 1623 vnic_intr_mask(&enic->intr[i]);
29046f9b
VK		 1624 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */
1625 }
b3d18d19
SF		 1626
1627 enic_synchronize_irqs(enic);
1628
01f2e4ea 1629 del_timer_sync(&enic->notify_timer);
a145df23 1630 enic_rfs_flw_tbl_free(enic);
01f2e4ea 1631
383ab92f 1632 enic_dev_disable(enic);
717258ba 1633
14747cd9
GV		 1634 local_bh_disable();
1635 for (i = 0; i < enic->rq_count; i++) {
717258ba 1636 napi_disable(&enic->napi[i]);
14747cd9
GV		 1637 while (!enic_poll_lock_napi(&enic->rq[i]))
1638 mdelay(1);
1639 }
1640 local_bh_enable();
717258ba 1641
b3d18d19
SF		 1642 netif_carrier_off(netdev);
1643 netif_tx_disable(netdev);
4cfe8785
GV		 1644 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
1645 for (i = 0; i < enic->wq_count; i++)
1646 napi_disable(&enic->napi[enic_cq_wq(enic, i)]);
3f192795 1647
7335903c 1648 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic))
29639059 1649 enic_dev_del_station_addr(enic);
f8bd9091 1650
01f2e4ea
SF		 1651 for (i = 0; i < enic->wq_count; i++) {
1652 err = vnic_wq_disable(&enic->wq[i]);
1653 if (err)
1654 return err;
1655 }
1656 for (i = 0; i < enic->rq_count; i++) {
1657 err = vnic_rq_disable(&enic->rq[i]);
1658 if (err)
1659 return err;
1660 }
1661
383ab92f 1662 enic_dev_notify_unset(enic);
4b75a442
SF		 1663 enic_free_intr(enic);
1664
01f2e4ea
SF		 1665 for (i = 0; i < enic->wq_count; i++)
1666 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf);
1667 for (i = 0; i < enic->rq_count; i++)
1668 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf);
1669 for (i = 0; i < enic->cq_count; i++)
1670 vnic_cq_clean(&enic->cq[i]);
1671 for (i = 0; i < enic->intr_count; i++)
1672 vnic_intr_clean(&enic->intr[i]);
1673
1674 return 0;
1675}
1676
1677static int enic_change_mtu(struct net_device *netdev, int new_mtu)
1678{
1679 struct enic *enic = netdev_priv(netdev);
1680 int running = netif_running(netdev);
1681
25f0a061
SF		 1682 if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU)
1683 return -EINVAL;
1684
7335903c 1685 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
c97c894d
RP		 1686 return -EOPNOTSUPP;
1687
01f2e4ea
SF		 1688 if (running)
1689 enic_stop(netdev);
1690
01f2e4ea
SF		 1691 netdev->mtu = new_mtu;
1692
1693 if (netdev->mtu > enic->port_mtu)
a7a79deb
VK		 1694 netdev_warn(netdev,
1695 "interface MTU (%d) set higher than port MTU (%d)\n",
1696 netdev->mtu, enic->port_mtu);
01f2e4ea
SF		 1697
1698 if (running)
1699 enic_open(netdev);
1700
1701 return 0;
1702}
1703
c97c894d
RP		 1704static void enic_change_mtu_work(struct work_struct *work)
1705{
1706 struct enic *enic = container_of(work, struct enic, change_mtu_work);
1707 struct net_device *netdev = enic->netdev;
1708 int new_mtu = vnic_dev_mtu(enic->vdev);
1709 int err;
1710 unsigned int i;
1711
1712 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu));
1713
1714 rtnl_lock();
1715
1716 /* Stop RQ */
1717 del_timer_sync(&enic->notify_timer);
1718
1719 for (i = 0; i < enic->rq_count; i++)
1720 napi_disable(&enic->napi[i]);
1721
1722 vnic_intr_mask(&enic->intr[0]);
1723 enic_synchronize_irqs(enic);
1724 err = vnic_rq_disable(&enic->rq[0]);
1725 if (err) {
e057590b 1726 rtnl_unlock();
c97c894d
RP		 1727 netdev_err(netdev, "Unable to disable RQ.\n");
1728 return;
1729 }
1730 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf);
1731 vnic_cq_clean(&enic->cq[0]);
1732 vnic_intr_clean(&enic->intr[0]);
1733
1734 /* Fill RQ with new_mtu-sized buffers */
1735 netdev->mtu = new_mtu;
1736 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf);
1737 /* Need at least one buffer on ring to get going */
1738 if (vnic_rq_desc_used(&enic->rq[0]) == 0) {
e057590b 1739 rtnl_unlock();
c97c894d
RP		 1740 netdev_err(netdev, "Unable to alloc receive buffers.\n");
1741 return;
1742 }
1743
1744 /* Start RQ */
1745 vnic_rq_enable(&enic->rq[0]);
1746 napi_enable(&enic->napi[0]);
1747 vnic_intr_unmask(&enic->intr[0]);
1748 enic_notify_timer_start(enic);
1749
1750 rtnl_unlock();
1751
1752 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu);
1753}
1754
01f2e4ea
SF		 1755#ifdef CONFIG_NET_POLL_CONTROLLER
1756static void enic_poll_controller(struct net_device *netdev)
1757{
1758 struct enic *enic = netdev_priv(netdev);
1759 struct vnic_dev *vdev = enic->vdev;
717258ba 1760 unsigned int i, intr;
01f2e4ea
SF		 1761
1762 switch (vnic_dev_get_intr_mode(vdev)) {
1763 case VNIC_DEV_INTR_MODE_MSIX:
717258ba
VK		 1764 for (i = 0; i < enic->rq_count; i++) {
1765 intr = enic_msix_rq_intr(enic, i);
4cfe8785
GV		 1766 enic_isr_msix(enic->msix_entry[intr].vector,
1767 &enic->napi[i]);
717258ba 1768 }
b880a954
VK		 1769
1770 for (i = 0; i < enic->wq_count; i++) {
1771 intr = enic_msix_wq_intr(enic, i);
4cfe8785
GV		 1772 enic_isr_msix(enic->msix_entry[intr].vector,
1773 &enic->napi[enic_cq_wq(enic, i)]);
b880a954
VK		 1774 }
1775
01f2e4ea
SF		 1776 break;
1777 case VNIC_DEV_INTR_MODE_MSI:
1778 enic_isr_msi(enic->pdev->irq, enic);
1779 break;
1780 case VNIC_DEV_INTR_MODE_INTX:
1781 enic_isr_legacy(enic->pdev->irq, netdev);
1782 break;
1783 default:
1784 break;
1785 }
1786}
1787#endif
1788
1789static int enic_dev_wait(struct vnic_dev *vdev,
1790 int (*start)(struct vnic_dev *, int),
1791 int (*finished)(struct vnic_dev *, int *),
1792 int arg)
1793{
1794 unsigned long time;
1795 int done;
1796 int err;
1797
1798 BUG_ON(in_interrupt());
1799
1800 err = start(vdev, arg);
1801 if (err)
1802 return err;
1803
1804 /* Wait for func to complete...2 seconds max
1805 */
1806
1807 time = jiffies + (HZ * 2);
1808 do {
1809
1810 err = finished(vdev, &done);
1811 if (err)
1812 return err;
1813
1814 if (done)
1815 return 0;
1816
1817 schedule_timeout_uninterruptible(HZ / 10);
1818
1819 } while (time_after(time, jiffies));
1820
1821 return -ETIMEDOUT;
1822}
1823
1824static int enic_dev_open(struct enic *enic)
1825{
1826 int err;
1827
1828 err = enic_dev_wait(enic->vdev, vnic_dev_open,
1829 vnic_dev_open_done, 0);
1830 if (err)
a7a79deb
VK		 1831 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n",
1832 err);
01f2e4ea
SF		 1833
1834 return err;
1835}
1836
99ef5639 1837static int enic_dev_hang_reset(struct enic *enic)
01f2e4ea
SF		 1838{
1839 int err;
1840
99ef5639
VK		 1841 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset,
1842 vnic_dev_hang_reset_done, 0);
01f2e4ea 1843 if (err)
a7a79deb
VK		 1844 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n",
1845 err);
01f2e4ea
SF		 1846
1847 return err;
1848}
1849
717258ba
VK		 1850static int enic_set_rsskey(struct enic *enic)
1851{
1f4f067f 1852 dma_addr_t rss_key_buf_pa;
717258ba
VK		 1853 union vnic_rss_key *rss_key_buf_va = NULL;
1854 union vnic_rss_key rss_key = {
1855 .key[0].b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101},
1856 .key[1].b = {80, 65, 76, 79, 117, 110, 105, 113, 117, 101},
1857 .key[2].b = {76, 73, 78, 85, 88, 114, 111, 99, 107, 115},
1858 .key[3].b = {69, 78, 73, 67, 105, 115, 99, 111, 111, 108},
1859 };
1860 int err;
1861
1862 rss_key_buf_va = pci_alloc_consistent(enic->pdev,
1863 sizeof(union vnic_rss_key), &rss_key_buf_pa);
1864 if (!rss_key_buf_va)
1865 return -ENOMEM;
1866
1867 memcpy(rss_key_buf_va, &rss_key, sizeof(union vnic_rss_key));
1868
8e091340 1869 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1870 err = enic_set_rss_key(enic,
1871 rss_key_buf_pa,
1872 sizeof(union vnic_rss_key));
8e091340 1873 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1874
1875 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key),
1876 rss_key_buf_va, rss_key_buf_pa);
1877
1878 return err;
1879}
1880
1881static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
1882{
1f4f067f 1883 dma_addr_t rss_cpu_buf_pa;
717258ba
VK		 1884 union vnic_rss_cpu *rss_cpu_buf_va = NULL;
1885 unsigned int i;
1886 int err;
1887
1888 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev,
1889 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa);
1890 if (!rss_cpu_buf_va)
1891 return -ENOMEM;
1892
1893 for (i = 0; i < (1 << rss_hash_bits); i++)
1894 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
1895
8e091340 1896 spin_lock_bh(&enic->devcmd_lock);
717258ba
VK		 1897 err = enic_set_rss_cpu(enic,
1898 rss_cpu_buf_pa,
1899 sizeof(union vnic_rss_cpu));
8e091340 1900 spin_unlock_bh(&enic->devcmd_lock);
717258ba
VK		 1901
1902 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),
1903 rss_cpu_buf_va, rss_cpu_buf_pa);
1904
1905 return err;
1906}
1907
1908static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,
1909 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)
68f71708 1910{
68f71708
SF		 1911 const u8 tso_ipid_split_en = 0;
1912 const u8 ig_vlan_strip_en = 1;
383ab92f 1913 int err;
68f71708 1914
717258ba
VK		 1915 /* Enable VLAN tag stripping.
1916 */
68f71708 1917
8e091340 1918 spin_lock_bh(&enic->devcmd_lock);
383ab92f 1919 err = enic_set_nic_cfg(enic,
68f71708
SF		 1920 rss_default_cpu, rss_hash_type,
1921 rss_hash_bits, rss_base_cpu,
1922 rss_enable, tso_ipid_split_en,
1923 ig_vlan_strip_en);
8e091340 1924 spin_unlock_bh(&enic->devcmd_lock);
383ab92f
VK		 1925
1926 return err;
1927}
1928
717258ba
VK		 1929static int enic_set_rss_nic_cfg(struct enic *enic)
1930{
1931 struct device *dev = enic_get_dev(enic);
1932 const u8 rss_default_cpu = 0;
1933 const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |
1934 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |
1935 NIC_CFG_RSS_HASH_TYPE_IPV6 |
1936 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;
1937 const u8 rss_hash_bits = 7;
1938 const u8 rss_base_cpu = 0;
1939 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);
1940
1941 if (rss_enable) {
1942 if (!enic_set_rsskey(enic)) {
1943 if (enic_set_rsscpu(enic, rss_hash_bits)) {
1944 rss_enable = 0;
1945 dev_warn(dev, "RSS disabled, "
1946 "Failed to set RSS cpu indirection table.");
1947 }
1948 } else {
1949 rss_enable = 0;
1950 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n");
1951 }
1952 }
1953
1954 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,
1955 rss_hash_bits, rss_base_cpu, rss_enable);
f8cac14a
VK		 1956}
1957
01f2e4ea
SF		 1958static void enic_reset(struct work_struct *work)
1959{
1960 struct enic *enic = container_of(work, struct enic, reset);
1961
1962 if (!netif_running(enic->netdev))
1963 return;
1964
1965 rtnl_lock();
1966
0b038566 1967 spin_lock(&enic->enic_api_lock);
383ab92f 1968 enic_dev_hang_notify(enic);
01f2e4ea 1969 enic_stop(enic->netdev);
99ef5639 1970 enic_dev_hang_reset(enic);
e0afe53f 1971 enic_reset_addr_lists(enic);
01f2e4ea 1972 enic_init_vnic_resources(enic);
717258ba 1973 enic_set_rss_nic_cfg(enic);
f8cac14a 1974 enic_dev_set_ig_vlan_rewrite_mode(enic);
01f2e4ea 1975 enic_open(enic->netdev);
0b038566 1976 spin_unlock(&enic->enic_api_lock);
d765bb41 1977 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev);
01f2e4ea
SF		 1978
1979 rtnl_unlock();
1980}
1981
1982static int enic_set_intr_mode(struct enic *enic)
1983{
717258ba 1984 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX);
1cbb1a61 1985 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX);
01f2e4ea
SF		 1986 unsigned int i;
1987
1988 /* Set interrupt mode (INTx, MSI, MSI-X) depending
717258ba 1989 * on system capabilities.
01f2e4ea
SF		 1990 *
1991 * Try MSI-X first
1992 *
1993 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs
1994 * (the second to last INTR is used for WQ/RQ errors)
1995 * (the last INTR is used for notifications)
1996 */
1997
1998 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2);
1999 for (i = 0; i < n + m + 2; i++)
2000 enic->msix_entry[i].entry = i;
2001
717258ba
VK		 2002 /* Use multiple RQs if RSS is enabled
2003 */
2004
2005 if (ENIC_SETTING(enic, RSS) &&
2006 enic->config.intr_mode < 1 &&
01f2e4ea
SF		 2007 enic->rq_count >= n &&
2008 enic->wq_count >= m &&
2009 enic->cq_count >= n + m &&
717258ba 2010 enic->intr_count >= n + m + 2) {
01f2e4ea 2011
abbb6a37
AG		 2012 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2013 n + m + 2, n + m + 2) > 0) {
01f2e4ea 2014
717258ba
VK		 2015 enic->rq_count = n;
2016 enic->wq_count = m;
2017 enic->cq_count = n + m;
2018 enic->intr_count = n + m + 2;
01f2e4ea 2019
717258ba
VK		 2020 vnic_dev_set_intr_mode(enic->vdev,
2021 VNIC_DEV_INTR_MODE_MSIX);
2022
2023 return 0;
2024 }
2025 }
2026
2027 if (enic->config.intr_mode < 1 &&
2028 enic->rq_count >= 1 &&
2029 enic->wq_count >= m &&
2030 enic->cq_count >= 1 + m &&
2031 enic->intr_count >= 1 + m + 2) {
abbb6a37
AG		 2032 if (pci_enable_msix_range(enic->pdev, enic->msix_entry,
2033 1 + m + 2, 1 + m + 2) > 0) {
717258ba
VK		 2034
2035 enic->rq_count = 1;
2036 enic->wq_count = m;
2037 enic->cq_count = 1 + m;
2038 enic->intr_count = 1 + m + 2;
2039
2040 vnic_dev_set_intr_mode(enic->vdev,
2041 VNIC_DEV_INTR_MODE_MSIX);
2042
2043 return 0;
2044 }
01f2e4ea
SF		 2045 }
2046
2047 /* Next try MSI
2048 *
2049 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR
2050 */
2051
2052 if (enic->config.intr_mode < 2 &&
2053 enic->rq_count >= 1 &&
2054 enic->wq_count >= 1 &&
2055 enic->cq_count >= 2 &&
2056 enic->intr_count >= 1 &&
2057 !pci_enable_msi(enic->pdev)) {
2058
2059 enic->rq_count = 1;
2060 enic->wq_count = 1;
2061 enic->cq_count = 2;
2062 enic->intr_count = 1;
2063
2064 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI);
2065
2066 return 0;
2067 }
2068
2069 /* Next try INTx
2070 *
2071 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs
2072 * (the first INTR is used for WQ/RQ)
2073 * (the second INTR is used for WQ/RQ errors)
2074 * (the last INTR is used for notifications)
2075 */
2076
2077 if (enic->config.intr_mode < 3 &&
2078 enic->rq_count >= 1 &&
2079 enic->wq_count >= 1 &&
2080 enic->cq_count >= 2 &&
2081 enic->intr_count >= 3) {
2082
2083 enic->rq_count = 1;
2084 enic->wq_count = 1;
2085 enic->cq_count = 2;
2086 enic->intr_count = 3;
2087
2088 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX);
2089
2090 return 0;
2091 }
2092
2093 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2094
2095 return -EINVAL;
2096}
2097
2098static void enic_clear_intr_mode(struct enic *enic)
2099{
2100 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2101 case VNIC_DEV_INTR_MODE_MSIX:
2102 pci_disable_msix(enic->pdev);
2103 break;
2104 case VNIC_DEV_INTR_MODE_MSI:
2105 pci_disable_msi(enic->pdev);
2106 break;
2107 default:
2108 break;
2109 }
2110
2111 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
2112}
2113
f8bd9091
SF		 2114static const struct net_device_ops enic_netdev_dynamic_ops = {
2115 .ndo_open = enic_open,
2116 .ndo_stop = enic_stop,
2117 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2118 .ndo_get_stats64 = enic_get_stats,
f8bd9091 2119 .ndo_validate_addr = eth_validate_addr,
319d7e84 2120 .ndo_set_rx_mode = enic_set_rx_mode,
f8bd9091
SF		 2121 .ndo_set_mac_address = enic_set_mac_address_dynamic,
2122 .ndo_change_mtu = enic_change_mtu,
f8bd9091
SF		 2123 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2124 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2125 .ndo_tx_timeout = enic_tx_timeout,
2126 .ndo_set_vf_port = enic_set_vf_port,
2127 .ndo_get_vf_port = enic_get_vf_port,
0b1c00fc 2128 .ndo_set_vf_mac = enic_set_vf_mac,
f8bd9091
SF		 2129#ifdef CONFIG_NET_POLL_CONTROLLER
2130 .ndo_poll_controller = enic_poll_controller,
2131#endif
a145df23
GV		 2132#ifdef CONFIG_RFS_ACCEL
2133 .ndo_rx_flow_steer = enic_rx_flow_steer,
2134#endif
14747cd9
GV		 2135#ifdef CONFIG_NET_RX_BUSY_POLL
2136 .ndo_busy_poll = enic_busy_poll,
2137#endif
f8bd9091
SF		 2138};
2139
afe29f7a
SH		 2140static const struct net_device_ops enic_netdev_ops = {
2141 .ndo_open = enic_open,
2142 .ndo_stop = enic_stop,
00829823 2143 .ndo_start_xmit = enic_hard_start_xmit,
f20530bc 2144 .ndo_get_stats64 = enic_get_stats,
afe29f7a 2145 .ndo_validate_addr = eth_validate_addr,
f8bd9091 2146 .ndo_set_mac_address = enic_set_mac_address,
319d7e84 2147 .ndo_set_rx_mode = enic_set_rx_mode,
afe29f7a 2148 .ndo_change_mtu = enic_change_mtu,
afe29f7a
SH		 2149 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid,
2150 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid,
2151 .ndo_tx_timeout = enic_tx_timeout,
3f192795
RP		 2152 .ndo_set_vf_port = enic_set_vf_port,
2153 .ndo_get_vf_port = enic_get_vf_port,
2154 .ndo_set_vf_mac = enic_set_vf_mac,
afe29f7a
SH		 2155#ifdef CONFIG_NET_POLL_CONTROLLER
2156 .ndo_poll_controller = enic_poll_controller,
2157#endif
a145df23
GV		 2158#ifdef CONFIG_RFS_ACCEL
2159 .ndo_rx_flow_steer = enic_rx_flow_steer,
2160#endif
14747cd9
GV		 2161#ifdef CONFIG_NET_RX_BUSY_POLL
2162 .ndo_busy_poll = enic_busy_poll,
2163#endif
afe29f7a
SH		 2164};
2165
2fdba388 2166static void enic_dev_deinit(struct enic *enic)
6fdfa970 2167{
717258ba
VK		 2168 unsigned int i;
2169
14747cd9
GV		 2170 for (i = 0; i < enic->rq_count; i++) {
2171 napi_hash_del(&enic->napi[i]);
717258ba 2172 netif_napi_del(&enic->napi[i]);
14747cd9 2173 }
4cfe8785
GV		 2174 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX)
2175 for (i = 0; i < enic->wq_count; i++)
2176 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]);
717258ba 2177
6fdfa970
SF		 2178 enic_free_vnic_resources(enic);
2179 enic_clear_intr_mode(enic);
2180}
2181
2fdba388 2182static int enic_dev_init(struct enic *enic)
6fdfa970 2183{
a7a79deb 2184 struct device *dev = enic_get_dev(enic);
6fdfa970 2185 struct net_device *netdev = enic->netdev;
717258ba 2186 unsigned int i;
6fdfa970
SF		 2187 int err;
2188
ea7ea65a
VK		 2189 /* Get interrupt coalesce timer info */
2190 err = enic_dev_intr_coal_timer_info(enic);
2191 if (err) {
2192 dev_warn(dev, "Using default conversion factor for "
2193 "interrupt coalesce timer\n");
2194 vnic_dev_intr_coal_timer_info_default(enic->vdev);
2195 }
2196
6fdfa970
SF		 2197 /* Get vNIC configuration
2198 */
2199
2200 err = enic_get_vnic_config(enic);
2201 if (err) {
a7a79deb 2202 dev_err(dev, "Get vNIC configuration failed, aborting\n");
6fdfa970
SF		 2203 return err;
2204 }
2205
2206 /* Get available resource counts
2207 */
2208
2209 enic_get_res_counts(enic);
2210
2211 /* Set interrupt mode based on resource counts and system
2212 * capabilities
2213 */
2214
2215 err = enic_set_intr_mode(enic);
2216 if (err) {
a7a79deb
VK		 2217 dev_err(dev, "Failed to set intr mode based on resource "
2218 "counts and system capabilities, aborting\n");
6fdfa970
SF		 2219 return err;
2220 }
2221
2222 /* Allocate and configure vNIC resources
2223 */
2224
2225 err = enic_alloc_vnic_resources(enic);
2226 if (err) {
a7a79deb 2227 dev_err(dev, "Failed to alloc vNIC resources, aborting\n");
6fdfa970
SF		 2228 goto err_out_free_vnic_resources;
2229 }
2230
2231 enic_init_vnic_resources(enic);
2232
717258ba 2233 err = enic_set_rss_nic_cfg(enic);
6fdfa970 2234 if (err) {
a7a79deb 2235 dev_err(dev, "Failed to config nic, aborting\n");
6fdfa970
SF		 2236 goto err_out_free_vnic_resources;
2237 }
2238
2239 switch (vnic_dev_get_intr_mode(enic->vdev)) {
2240 default:
717258ba 2241 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64);
14747cd9 2242 napi_hash_add(&enic->napi[0]);
6fdfa970
SF		 2243 break;
2244 case VNIC_DEV_INTR_MODE_MSIX:
14747cd9 2245 for (i = 0; i < enic->rq_count; i++) {
717258ba 2246 netif_napi_add(netdev, &enic->napi[i],
4cfe8785 2247 enic_poll_msix_rq, NAPI_POLL_WEIGHT);
14747cd9
GV		 2248 napi_hash_add(&enic->napi[i]);
2249 }
4cfe8785
GV		 2250 for (i = 0; i < enic->wq_count; i++)
2251 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)],
2252 enic_poll_msix_wq, NAPI_POLL_WEIGHT);
6fdfa970
SF		 2253 break;
2254 }
2255
2256 return 0;
2257
2258err_out_free_vnic_resources:
2259 enic_clear_intr_mode(enic);
2260 enic_free_vnic_resources(enic);
2261
2262 return err;
2263}
2264
27e6c7d3
SF		 2265static void enic_iounmap(struct enic *enic)
2266{
2267 unsigned int i;
2268
2269 for (i = 0; i < ARRAY_SIZE(enic->bar); i++)
2270 if (enic->bar[i].vaddr)
2271 iounmap(enic->bar[i].vaddr);
2272}
2273
1dd06ae8 2274static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
01f2e4ea 2275{
a7a79deb 2276 struct device *dev = &pdev->dev;
01f2e4ea
SF		 2277 struct net_device *netdev;
2278 struct enic *enic;
2279 int using_dac = 0;
2280 unsigned int i;
2281 int err;
8749b427
RP		 2282#ifdef CONFIG_PCI_IOV
2283 int pos = 0;
2284#endif
b67f231d 2285 int num_pps = 1;
01f2e4ea 2286
01f2e4ea
SF		 2287 /* Allocate net device structure and initialize. Private
2288 * instance data is initialized to zero.
2289 */
2290
822473b6 2291 netdev = alloc_etherdev_mqs(sizeof(struct enic),
2292 ENIC_RQ_MAX, ENIC_WQ_MAX);
41de8d4c 2293 if (!netdev)
01f2e4ea 2294 return -ENOMEM;
01f2e4ea 2295
01f2e4ea
SF		 2296 pci_set_drvdata(pdev, netdev);
2297
2298 SET_NETDEV_DEV(netdev, &pdev->dev);
2299
2300 enic = netdev_priv(netdev);
2301 enic->netdev = netdev;
2302 enic->pdev = pdev;
2303
2304 /* Setup PCI resources
2305 */
2306
29046f9b 2307 err = pci_enable_device_mem(pdev);
01f2e4ea 2308 if (err) {
a7a79deb 2309 dev_err(dev, "Cannot enable PCI device, aborting\n");
01f2e4ea
SF		 2310 goto err_out_free_netdev;
2311 }
2312
2313 err = pci_request_regions(pdev, DRV_NAME);
2314 if (err) {
a7a79deb 2315 dev_err(dev, "Cannot request PCI regions, aborting\n");
01f2e4ea
SF		 2316 goto err_out_disable_device;
2317 }
2318
2319 pci_set_master(pdev);
2320
2321 /* Query PCI controller on system for DMA addressing
624dbf55 2322 * limitation for the device. Try 64-bit first, and
01f2e4ea
SF		 2323 * fail to 32-bit.
2324 */
2325
624dbf55 2326 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2327 if (err) {
284901a9 2328 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2329 if (err) {
a7a79deb 2330 dev_err(dev, "No usable DMA configuration, aborting\n");
01f2e4ea
SF		 2331 goto err_out_release_regions;
2332 }
284901a9 2333 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
01f2e4ea 2334 if (err) {
a7a79deb
VK		 2335 dev_err(dev, "Unable to obtain %u-bit DMA "
2336 "for consistent allocations, aborting\n", 32);
01f2e4ea
SF		 2337 goto err_out_release_regions;
2338 }
2339 } else {
624dbf55 2340 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
01f2e4ea 2341 if (err) {
a7a79deb 2342 dev_err(dev, "Unable to obtain %u-bit DMA "
624dbf55 2343 "for consistent allocations, aborting\n", 64);
01f2e4ea
SF		 2344 goto err_out_release_regions;
2345 }
2346 using_dac = 1;
2347 }
2348
27e6c7d3 2349 /* Map vNIC resources from BAR0-5
01f2e4ea
SF		 2350 */
2351
27e6c7d3
SF		 2352 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) {
2353 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
2354 continue;
2355 enic->bar[i].len = pci_resource_len(pdev, i);
2356 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
2357 if (!enic->bar[i].vaddr) {
a7a79deb 2358 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i);
27e6c7d3
SF		 2359 err = -ENODEV;
2360 goto err_out_iounmap;
2361 }
2362 enic->bar[i].bus_addr = pci_resource_start(pdev, i);
01f2e4ea
SF		 2363 }
2364
2365 /* Register vNIC device
2366 */
2367
27e6c7d3
SF		 2368 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar,
2369 ARRAY_SIZE(enic->bar));
01f2e4ea 2370 if (!enic->vdev) {
a7a79deb 2371 dev_err(dev, "vNIC registration failed, aborting\n");
01f2e4ea
SF		 2372 err = -ENODEV;
2373 goto err_out_iounmap;
2374 }
2375
8749b427
RP		 2376#ifdef CONFIG_PCI_IOV
2377 /* Get number of subvnics */
2378 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
2379 if (pos) {
2380 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF,
413708bb 2381 &enic->num_vfs);
8749b427
RP		 2382 if (enic->num_vfs) {
2383 err = pci_enable_sriov(pdev, enic->num_vfs);
2384 if (err) {
2385 dev_err(dev, "SRIOV enable failed, aborting."
2386 " pci_enable_sriov() returned %d\n",
2387 err);
2388 goto err_out_vnic_unregister;
2389 }
2390 enic->priv_flags |= ENIC_SRIOV_ENABLED;
b67f231d 2391 num_pps = enic->num_vfs;
8749b427
RP		 2392 }
2393 }
8749b427 2394#endif
ca2b721d 2395
3f192795 2396 /* Allocate structure for port profiles */
a1de2219 2397 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL);
3f192795 2398 if (!enic->pp) {
3f192795 2399 err = -ENOMEM;
ca2b721d 2400 goto err_out_disable_sriov_pp;
3f192795
RP		 2401 }
2402
01f2e4ea
SF		 2403 /* Issue device open to get device in known state
2404 */
2405
2406 err = enic_dev_open(enic);
2407 if (err) {
a7a79deb 2408 dev_err(dev, "vNIC dev open failed, aborting\n");
ca2b721d 2409 goto err_out_disable_sriov;
01f2e4ea
SF		 2410 }
2411
69161425
VK		 2412 /* Setup devcmd lock
2413 */
2414
2415 spin_lock_init(&enic->devcmd_lock);
0b038566 2416 spin_lock_init(&enic->enic_api_lock);
69161425
VK		 2417
2418 /*
2419 * Set ingress vlan rewrite mode before vnic initialization
2420 */
2421
2422 err = enic_dev_set_ig_vlan_rewrite_mode(enic);
2423 if (err) {
2424 dev_err(dev,
2425 "Failed to set ingress vlan rewrite mode, aborting.\n");
2426 goto err_out_dev_close;
2427 }
2428
01f2e4ea
SF		 2429 /* Issue device init to initialize the vnic-to-switch link.
2430 * We'll start with carrier off and wait for link UP
2431 * notification later to turn on carrier. We don't need
2432 * to wait here for the vnic-to-switch link initialization
2433 * to complete; link UP notification is the indication that
2434 * the process is complete.
2435 */
2436
2437 netif_carrier_off(netdev);
2438
a7a79deb
VK		 2439 /* Do not call dev_init for a dynamic vnic.
2440 * For a dynamic vnic, init_prov_info will be
2441 * called later by an upper layer.
2442 */
2443
2b68c181 2444 if (!enic_is_dynamic(enic)) {
f8bd9091
SF		 2445 err = vnic_dev_init(enic->vdev, 0);
2446 if (err) {
a7a79deb 2447 dev_err(dev, "vNIC dev init failed, aborting\n");
f8bd9091
SF		 2448 goto err_out_dev_close;
2449 }
01f2e4ea
SF		 2450 }
2451
6fdfa970 2452 err = enic_dev_init(enic);
01f2e4ea 2453 if (err) {
a7a79deb 2454 dev_err(dev, "Device initialization failed, aborting\n");
01f2e4ea
SF		 2455 goto err_out_dev_close;
2456 }
2457
822473b6 2458 netif_set_real_num_tx_queues(netdev, enic->wq_count);
bf751ba8 2459 netif_set_real_num_rx_queues(netdev, enic->rq_count);
822473b6 2460
383ab92f 2461 /* Setup notification timer, HW reset task, and wq locks
01f2e4ea
SF		 2462 */
2463
2464 init_timer(&enic->notify_timer);
2465 enic->notify_timer.function = enic_notify_timer;
2466 enic->notify_timer.data = (unsigned long)enic;
2467
7c2ce6e6 2468 enic_set_rx_coal_setting(enic);
01f2e4ea 2469 INIT_WORK(&enic->reset, enic_reset);
c97c894d 2470 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work);
01f2e4ea
SF		 2471
2472 for (i = 0; i < enic->wq_count; i++)
2473 spin_lock_init(&enic->wq_lock[i]);
2474
01f2e4ea
SF		 2475 /* Register net device
2476 */
2477
2478 enic->port_mtu = enic->config.mtu;
2479 (void)enic_change_mtu(netdev, enic->port_mtu);
2480
2481 err = enic_set_mac_addr(netdev, enic->mac_addr);
2482 if (err) {
a7a79deb 2483 dev_err(dev, "Invalid MAC address, aborting\n");
6fdfa970 2484 goto err_out_dev_deinit;
01f2e4ea
SF		 2485 }
2486
7c844599 2487 enic->tx_coalesce_usecs = enic->config.intr_timer_usec;
7c2ce6e6
SS		 2488 /* rx coalesce time already got initialized. This gets used
2489 * if adaptive coal is turned off
2490 */
7c844599
SF		 2491 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs;
2492
7335903c 2493 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic))
f8bd9091
SF		 2494 netdev->netdev_ops = &enic_netdev_dynamic_ops;
2495 else
2496 netdev->netdev_ops = &enic_netdev_ops;
2497
01f2e4ea 2498 netdev->watchdog_timeo = 2 * HZ;
f13bbc2f 2499 enic_set_ethtool_ops(netdev);
01f2e4ea 2500
f646968f 2501 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1825aca6 2502 if (ENIC_SETTING(enic, LOOP)) {
f646968f 2503 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1825aca6
VK		 2504 enic->loop_enable = 1;
2505 enic->loop_tag = enic->config.loop_tag;
2506 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag);
2507 }
01f2e4ea 2508 if (ENIC_SETTING(enic, TXCSUM))
5ec8f9b8 2509 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM;
01f2e4ea 2510 if (ENIC_SETTING(enic, TSO))
5ec8f9b8 2511 netdev->hw_features |= NETIF_F_TSO |
01f2e4ea 2512 NETIF_F_TSO6 | NETIF_F_TSO_ECN;
bf751ba8 2513 if (ENIC_SETTING(enic, RSS))
2514 netdev->hw_features |= NETIF_F_RXHASH;
5ec8f9b8
MM		 2515 if (ENIC_SETTING(enic, RXCSUM))
2516 netdev->hw_features |= NETIF_F_RXCSUM;
2517
2518 netdev->features |= netdev->hw_features;
2519
a145df23
GV		 2520#ifdef CONFIG_RFS_ACCEL
2521 netdev->hw_features |= NETIF_F_NTUPLE;
2522#endif
2523
01f2e4ea
SF		 2524 if (using_dac)
2525 netdev->features |= NETIF_F_HIGHDMA;
2526
01789349
JP		 2527 netdev->priv_flags |= IFF_UNICAST_FLT;
2528
01f2e4ea
SF		 2529 err = register_netdev(netdev);
2530 if (err) {
a7a79deb 2531 dev_err(dev, "Cannot register net device, aborting\n");
6fdfa970 2532 goto err_out_dev_deinit;
01f2e4ea
SF		 2533 }
2534
2535 return 0;
2536
6fdfa970
SF		 2537err_out_dev_deinit:
2538 enic_dev_deinit(enic);
01f2e4ea
SF		 2539err_out_dev_close:
2540 vnic_dev_close(enic->vdev);
8749b427 2541err_out_disable_sriov:
ca2b721d
RP		 2542 kfree(enic->pp);
2543err_out_disable_sriov_pp:
8749b427
RP		 2544#ifdef CONFIG_PCI_IOV
2545 if (enic_sriov_enabled(enic)) {
2546 pci_disable_sriov(pdev);
2547 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2548 }
01f2e4ea 2549err_out_vnic_unregister:
8749b427 2550#endif
35d87e33 2551 vnic_dev_unregister(enic->vdev);
01f2e4ea
SF		 2552err_out_iounmap:
2553 enic_iounmap(enic);
2554err_out_release_regions:
2555 pci_release_regions(pdev);
2556err_out_disable_device:
2557 pci_disable_device(pdev);
2558err_out_free_netdev:
01f2e4ea
SF		 2559 free_netdev(netdev);
2560
2561 return err;
2562}
2563
854de92f 2564static void enic_remove(struct pci_dev *pdev)
01f2e4ea
SF		 2565{
2566 struct net_device *netdev = pci_get_drvdata(pdev);
2567
2568 if (netdev) {
2569 struct enic *enic = netdev_priv(netdev);
2570
23f333a2 2571 cancel_work_sync(&enic->reset);
c97c894d 2572 cancel_work_sync(&enic->change_mtu_work);
01f2e4ea 2573 unregister_netdev(netdev);
6fdfa970 2574 enic_dev_deinit(enic);
01f2e4ea 2575 vnic_dev_close(enic->vdev);
8749b427
RP		 2576#ifdef CONFIG_PCI_IOV
2577 if (enic_sriov_enabled(enic)) {
2578 pci_disable_sriov(pdev);
2579 enic->priv_flags &= ~ENIC_SRIOV_ENABLED;
2580 }
2581#endif
3f192795 2582 kfree(enic->pp);
01f2e4ea
SF		 2583 vnic_dev_unregister(enic->vdev);
2584 enic_iounmap(enic);
2585 pci_release_regions(pdev);
2586 pci_disable_device(pdev);
01f2e4ea
SF		 2587 free_netdev(netdev);
2588 }
2589}
2590
2591static struct pci_driver enic_driver = {
2592 .name = DRV_NAME,
2593 .id_table = enic_id_table,
2594 .probe = enic_probe,
854de92f 2595 .remove = enic_remove,
01f2e4ea
SF		 2596};
2597
2598static int __init enic_init_module(void)
2599{
a7a79deb 2600 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION);
01f2e4ea
SF		 2601
2602 return pci_register_driver(&enic_driver);
2603}
2604
2605static void __exit enic_cleanup_module(void)
2606{
2607 pci_unregister_driver(&enic_driver);
2608}
2609
2610module_init(enic_init_module);
2611module_exit(enic_cleanup_module);
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