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enic: Fix sparse warning in vnic_devcmd_init().
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / cisco / enic / vnic_dev.c
CommitLineData
01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF		 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/delay.h>
25#include <linux/if_ether.h>
26
27#include "vnic_resource.h"
28#include "vnic_devcmd.h"
29#include "vnic_dev.h"
373fb087 30#include "vnic_wq.h"
01f2e4ea 31#include "vnic_stats.h"
6a3c2f83 32#include "enic.h"
01f2e4ea 33
01f2e4ea
SF		 34#define VNIC_MAX_RES_HDR_SIZE \
35 (sizeof(struct vnic_resource_header) + \
36 sizeof(struct vnic_resource) * RES_TYPE_MAX)
37#define VNIC_RES_STRIDE 128
38
39void *vnic_dev_priv(struct vnic_dev *vdev)
40{
41 return vdev->priv;
42}
43
44static int vnic_dev_discover_res(struct vnic_dev *vdev,
27e6c7d3 45 struct vnic_dev_bar *bar, unsigned int num_bars)
01f2e4ea
SF		 46{
47 struct vnic_resource_header __iomem *rh;
90cf0b53 48 struct mgmt_barmap_hdr __iomem *mrh;
01f2e4ea
SF		 49 struct vnic_resource __iomem *r;
50 u8 type;
51
27e6c7d3
SF		 52 if (num_bars == 0)
53 return -EINVAL;
54
01f2e4ea 55 if (bar->len < VNIC_MAX_RES_HDR_SIZE) {
6a3c2f83 56 vdev_err("vNIC BAR0 res hdr length error\n");
01f2e4ea
SF		 57 return -EINVAL;
58 }
59
90cf0b53
RP		 60 rh = bar->vaddr;
61 mrh = bar->vaddr;
01f2e4ea 62 if (!rh) {
6a3c2f83 63 vdev_err("vNIC BAR0 res hdr not mem-mapped\n");
01f2e4ea
SF		 64 return -EINVAL;
65 }
66
90cf0b53
RP		 67 /* Check for mgmt vnic in addition to normal vnic */
68 if ((ioread32(&rh->magic) != VNIC_RES_MAGIC) ||
69 (ioread32(&rh->version) != VNIC_RES_VERSION)) {
70 if ((ioread32(&mrh->magic) != MGMTVNIC_MAGIC) ||
71 (ioread32(&mrh->version) != MGMTVNIC_VERSION)) {
6a3c2f83
GV		 72 vdev_err("vNIC BAR0 res magic/version error exp (%lx/%lx) or (%lx/%lx), curr (%x/%x)\n",
73 VNIC_RES_MAGIC, VNIC_RES_VERSION,
74 MGMTVNIC_MAGIC, MGMTVNIC_VERSION,
75 ioread32(&rh->magic), ioread32(&rh->version));
90cf0b53
RP		 76 return -EINVAL;
77 }
01f2e4ea
SF		 78 }
79
90cf0b53
RP		 80 if (ioread32(&mrh->magic) == MGMTVNIC_MAGIC)
81 r = (struct vnic_resource __iomem *)(mrh + 1);
82 else
83 r = (struct vnic_resource __iomem *)(rh + 1);
84
01f2e4ea
SF		 85
86 while ((type = ioread8(&r->type)) != RES_TYPE_EOL) {
87
88 u8 bar_num = ioread8(&r->bar);
89 u32 bar_offset = ioread32(&r->bar_offset);
90 u32 count = ioread32(&r->count);
91 u32 len;
92
93 r++;
94
27e6c7d3
SF		 95 if (bar_num >= num_bars)
96 continue;
97
98 if (!bar[bar_num].len || !bar[bar_num].vaddr)
01f2e4ea
SF		 99 continue;
100
101 switch (type) {
102 case RES_TYPE_WQ:
103 case RES_TYPE_RQ:
104 case RES_TYPE_CQ:
105 case RES_TYPE_INTR_CTRL:
106 /* each count is stride bytes long */
107 len = count * VNIC_RES_STRIDE;
27e6c7d3 108 if (len + bar_offset > bar[bar_num].len) {
6a3c2f83
GV		 109 vdev_err("vNIC BAR0 resource %d out-of-bounds, offset 0x%x + size 0x%x > bar len 0x%lx\n",
110 type, bar_offset, len,
111 bar[bar_num].len);
01f2e4ea
SF		 112 return -EINVAL;
113 }
114 break;
115 case RES_TYPE_INTR_PBA_LEGACY:
116 case RES_TYPE_DEVCMD:
373fb087 117 case RES_TYPE_DEVCMD2:
01f2e4ea
SF		 118 len = count;
119 break;
120 default:
121 continue;
122 }
123
124 vdev->res[type].count = count;
27e6c7d3
SF		 125 vdev->res[type].vaddr = (char __iomem *)bar[bar_num].vaddr +
126 bar_offset;
127 vdev->res[type].bus_addr = bar[bar_num].bus_addr + bar_offset;
01f2e4ea
SF		 128 }
129
130 return 0;
131}
132
133unsigned int vnic_dev_get_res_count(struct vnic_dev *vdev,
134 enum vnic_res_type type)
135{
136 return vdev->res[type].count;
137}
4a50ddfd 138EXPORT_SYMBOL(vnic_dev_get_res_count);
01f2e4ea
SF		 139
140void __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,
141 unsigned int index)
142{
143 if (!vdev->res[type].vaddr)
144 return NULL;
145
146 switch (type) {
147 case RES_TYPE_WQ:
148 case RES_TYPE_RQ:
149 case RES_TYPE_CQ:
150 case RES_TYPE_INTR_CTRL:
151 return (char __iomem *)vdev->res[type].vaddr +
152 index * VNIC_RES_STRIDE;
153 default:
154 return (char __iomem *)vdev->res[type].vaddr;
155 }
156}
4a50ddfd 157EXPORT_SYMBOL(vnic_dev_get_res);
01f2e4ea 158
2fdba388 159static unsigned int vnic_dev_desc_ring_size(struct vnic_dev_ring *ring,
01f2e4ea
SF		 160 unsigned int desc_count, unsigned int desc_size)
161{
162 /* The base address of the desc rings must be 512 byte aligned.
163 * Descriptor count is aligned to groups of 32 descriptors. A
164 * count of 0 means the maximum 4096 descriptors. Descriptor
165 * size is aligned to 16 bytes.
166 */
167
168 unsigned int count_align = 32;
169 unsigned int desc_align = 16;
170
171 ring->base_align = 512;
172
173 if (desc_count == 0)
174 desc_count = 4096;
175
176 ring->desc_count = ALIGN(desc_count, count_align);
177
178 ring->desc_size = ALIGN(desc_size, desc_align);
179
180 ring->size = ring->desc_count * ring->desc_size;
181 ring->size_unaligned = ring->size + ring->base_align;
182
183 return ring->size_unaligned;
184}
185
186void vnic_dev_clear_desc_ring(struct vnic_dev_ring *ring)
187{
188 memset(ring->descs, 0, ring->size);
189}
190
191int vnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,
192 unsigned int desc_count, unsigned int desc_size)
193{
194 vnic_dev_desc_ring_size(ring, desc_count, desc_size);
195
196 ring->descs_unaligned = pci_alloc_consistent(vdev->pdev,
197 ring->size_unaligned,
198 &ring->base_addr_unaligned);
199
200 if (!ring->descs_unaligned) {
6a3c2f83
GV		 201 vdev_err("Failed to allocate ring (size=%d), aborting\n",
202 (int)ring->size);
01f2e4ea
SF		 203 return -ENOMEM;
204 }
205
206 ring->base_addr = ALIGN(ring->base_addr_unaligned,
207 ring->base_align);
208 ring->descs = (u8 *)ring->descs_unaligned +
209 (ring->base_addr - ring->base_addr_unaligned);
210
211 vnic_dev_clear_desc_ring(ring);
212
213 ring->desc_avail = ring->desc_count - 1;
214
215 return 0;
216}
217
218void vnic_dev_free_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring)
219{
220 if (ring->descs) {
221 pci_free_consistent(vdev->pdev,
222 ring->size_unaligned,
223 ring->descs_unaligned,
224 ring->base_addr_unaligned);
225 ring->descs = NULL;
226 }
227}
228
70feadf3
VK		 229static int _vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
230 int wait)
01f2e4ea
SF		 231{
232 struct vnic_devcmd __iomem *devcmd = vdev->devcmd;
70feadf3 233 unsigned int i;
01f2e4ea
SF		 234 int delay;
235 u32 status;
01f2e4ea
SF		 236 int err;
237
238 status = ioread32(&devcmd->status);
506e1198
VK		 239 if (status == 0xFFFFFFFF) {
240 /* PCI-e target device is gone */
241 return -ENODEV;
242 }
01f2e4ea 243 if (status & STAT_BUSY) {
6a3c2f83 244 vdev_neterr("Busy devcmd %d\n", _CMD_N(cmd));
01f2e4ea
SF		 245 return -EBUSY;
246 }
247
248 if (_CMD_DIR(cmd) & _CMD_DIR_WRITE) {
70feadf3
VK		 249 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
250 writeq(vdev->args[i], &devcmd->args[i]);
01f2e4ea
SF		 251 wmb();
252 }
253
254 iowrite32(cmd, &devcmd->cmd);
255
256 if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
27e6c7d3 257 return 0;
01f2e4ea
SF		 258
259 for (delay = 0; delay < wait; delay++) {
260
261 udelay(100);
262
263 status = ioread32(&devcmd->status);
506e1198
VK		 264 if (status == 0xFFFFFFFF) {
265 /* PCI-e target device is gone */
266 return -ENODEV;
267 }
70feadf3 268
01f2e4ea
SF		 269 if (!(status & STAT_BUSY)) {
270
271 if (status & STAT_ERROR) {
27372bf5 272 err = (int)readq(&devcmd->args[0]);
07783f39
SA		 273 if (err == ERR_EINVAL &&
274 cmd == CMD_CAPABILITY)
10cc8844 275 return -err;
27372bf5
SF		 276 if (err != ERR_ECMDUNKNOWN ||
277 cmd != CMD_CAPABILITY)
6a3c2f83
GV		 278 vdev_neterr("Error %d devcmd %d\n",
279 err, _CMD_N(cmd));
10cc8844 280 return -err;
01f2e4ea
SF		 281 }
282
283 if (_CMD_DIR(cmd) & _CMD_DIR_READ) {
284 rmb();
70feadf3
VK		 285 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
286 vdev->args[i] = readq(&devcmd->args[i]);
01f2e4ea
SF		 287 }
288
289 return 0;
290 }
291 }
292
6a3c2f83 293 vdev_neterr("Timedout devcmd %d\n", _CMD_N(cmd));
01f2e4ea
SF		 294 return -ETIMEDOUT;
295}
296
373fb087
GV		 297static int _vnic_dev_cmd2(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
298 int wait)
299{
300 struct devcmd2_controller *dc2c = vdev->devcmd2;
301 struct devcmd2_result *result = dc2c->result + dc2c->next_result;
302 unsigned int i;
303 int delay, err;
304 u32 fetch_index, posted, new_posted;
305
306 posted = ioread32(&dc2c->wq_ctrl->posted_index);
307 fetch_index = ioread32(&dc2c->wq_ctrl->fetch_index);
308
309 if (posted == 0xFFFFFFFF || fetch_index == 0xFFFFFFFF)
310 return -ENODEV;
311
312 new_posted = (posted + 1) % DEVCMD2_RING_SIZE;
313
314 if (new_posted == fetch_index) {
315 vdev_neterr("devcmd2 %d: wq is full. fetch index: %u, posted index: %u\n",
316 _CMD_N(cmd), fetch_index, posted);
317 return -EBUSY;
318 }
319 dc2c->cmd_ring[posted].cmd = cmd;
320 dc2c->cmd_ring[posted].flags = 0;
321
322 if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
323 dc2c->cmd_ring[posted].flags |= DEVCMD2_FNORESULT;
324 if (_CMD_DIR(cmd) & _CMD_DIR_WRITE)
325 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
326 dc2c->cmd_ring[posted].args[i] = vdev->args[i];
327
328 /* Adding write memory barrier prevents compiler and/or CPU reordering,
329 * thus avoiding descriptor posting before descriptor is initialized.
330 * Otherwise, hardware can read stale descriptor fields.
331 */
332 wmb();
333 iowrite32(new_posted, &dc2c->wq_ctrl->posted_index);
334
335 if (dc2c->cmd_ring[posted].flags & DEVCMD2_FNORESULT)
336 return 0;
337
338 for (delay = 0; delay < wait; delay++) {
339 if (result->color == dc2c->color) {
340 dc2c->next_result++;
341 if (dc2c->next_result == dc2c->result_size) {
342 dc2c->next_result = 0;
343 dc2c->color = dc2c->color ? 0 : 1;
344 }
345 if (result->error) {
346 err = result->error;
347 if (err != ERR_ECMDUNKNOWN ||
348 cmd != CMD_CAPABILITY)
349 vdev_neterr("Error %d devcmd %d\n",
350 err, _CMD_N(cmd));
351 return -err;
352 }
353 if (_CMD_DIR(cmd) & _CMD_DIR_READ)
354 for (i = 0; i < VNIC_DEVCMD2_NARGS; i++)
355 vdev->args[i] = result->results[i];
356
357 return 0;
358 }
359 udelay(100);
360 }
361
362 vdev_neterr("devcmd %d timed out\n", _CMD_N(cmd));
363
364 return -ETIMEDOUT;
365}
366
367static int vnic_dev_init_devcmd1(struct vnic_dev *vdev)
368{
369 vdev->devcmd = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD, 0);
370 if (!vdev->devcmd)
371 return -ENODEV;
372 vdev->devcmd_rtn = _vnic_dev_cmd;
373
374 return 0;
375}
376
377static int vnic_dev_init_devcmd2(struct vnic_dev *vdev)
378{
379 int err;
380 unsigned int fetch_index;
381
382 if (vdev->devcmd2)
383 return 0;
384
385 vdev->devcmd2 = kzalloc(sizeof(*vdev->devcmd2), GFP_KERNEL);
386 if (!vdev->devcmd2)
387 return -ENOMEM;
388
389 vdev->devcmd2->color = 1;
390 vdev->devcmd2->result_size = DEVCMD2_RING_SIZE;
391 err = vnic_wq_devcmd2_alloc(vdev, &vdev->devcmd2->wq, DEVCMD2_RING_SIZE,
392 DEVCMD2_DESC_SIZE);
393 if (err)
394 goto err_free_devcmd2;
395
396 fetch_index = ioread32(&vdev->devcmd2->wq.ctrl->fetch_index);
397 if (fetch_index == 0xFFFFFFFF) { /* check for hardware gone */
398 vdev_err("Fatal error in devcmd2 init - hardware surprise removal");
399
400 return -ENODEV;
401 }
402
403 vnic_wq_init_start(&vdev->devcmd2->wq, 0, fetch_index, fetch_index, 0,
404 0);
405 vnic_wq_enable(&vdev->devcmd2->wq);
406
407 err = vnic_dev_alloc_desc_ring(vdev, &vdev->devcmd2->results_ring,
408 DEVCMD2_RING_SIZE, DEVCMD2_DESC_SIZE);
409 if (err)
410 goto err_free_wq;
411
412 vdev->devcmd2->result = vdev->devcmd2->results_ring.descs;
413 vdev->devcmd2->cmd_ring = vdev->devcmd2->wq.ring.descs;
414 vdev->devcmd2->wq_ctrl = vdev->devcmd2->wq.ctrl;
415 vdev->args[0] = (u64)vdev->devcmd2->results_ring.base_addr |
416 VNIC_PADDR_TARGET;
417 vdev->args[1] = DEVCMD2_RING_SIZE;
418
419 err = _vnic_dev_cmd2(vdev, CMD_INITIALIZE_DEVCMD2, 1000);
420 if (err)
421 goto err_free_desc_ring;
422
423 vdev->devcmd_rtn = _vnic_dev_cmd2;
424
425 return 0;
426
427err_free_desc_ring:
428 vnic_dev_free_desc_ring(vdev, &vdev->devcmd2->results_ring);
429err_free_wq:
430 vnic_wq_disable(&vdev->devcmd2->wq);
431 vnic_wq_free(&vdev->devcmd2->wq);
432err_free_devcmd2:
433 kfree(vdev->devcmd2);
434 vdev->devcmd2 = NULL;
435
436 return err;
437}
438
439static void vnic_dev_deinit_devcmd2(struct vnic_dev *vdev)
440{
441 vnic_dev_free_desc_ring(vdev, &vdev->devcmd2->results_ring);
442 vnic_wq_disable(&vdev->devcmd2->wq);
443 vnic_wq_free(&vdev->devcmd2->wq);
444 kfree(vdev->devcmd2);
445}
446
889d13f5
RP		 447static int vnic_dev_cmd_proxy(struct vnic_dev *vdev,
448 enum vnic_devcmd_cmd proxy_cmd, enum vnic_devcmd_cmd cmd,
449 u64 *a0, u64 *a1, int wait)
70feadf3
VK		 450{
451 u32 status;
452 int err;
453
454 memset(vdev->args, 0, sizeof(vdev->args));
455
889d13f5 456 vdev->args[0] = vdev->proxy_index;
70feadf3
VK		 457 vdev->args[1] = cmd;
458 vdev->args[2] = *a0;
459 vdev->args[3] = *a1;
460
373fb087 461 err = vdev->devcmd_rtn(vdev, proxy_cmd, wait);
70feadf3
VK		 462 if (err)
463 return err;
464
465 status = (u32)vdev->args[0];
466 if (status & STAT_ERROR) {
467 err = (int)vdev->args[1];
468 if (err != ERR_ECMDUNKNOWN ||
469 cmd != CMD_CAPABILITY)
6a3c2f83
GV		 470 vdev_neterr("Error %d proxy devcmd %d\n", err,
471 _CMD_N(cmd));
70feadf3
VK		 472 return err;
473 }
474
475 *a0 = vdev->args[1];
476 *a1 = vdev->args[2];
477
478 return 0;
479}
480
481static int vnic_dev_cmd_no_proxy(struct vnic_dev *vdev,
482 enum vnic_devcmd_cmd cmd, u64 *a0, u64 *a1, int wait)
483{
484 int err;
485
486 vdev->args[0] = *a0;
487 vdev->args[1] = *a1;
488
373fb087 489 err = vdev->devcmd_rtn(vdev, cmd, wait);
70feadf3
VK		 490
491 *a0 = vdev->args[0];
492 *a1 = vdev->args[1];
493
494 return err;
495}
496
889d13f5
RP		 497void vnic_dev_cmd_proxy_by_index_start(struct vnic_dev *vdev, u16 index)
498{
499 vdev->proxy = PROXY_BY_INDEX;
500 vdev->proxy_index = index;
501}
502
503void vnic_dev_cmd_proxy_end(struct vnic_dev *vdev)
504{
505 vdev->proxy = PROXY_NONE;
506 vdev->proxy_index = 0;
507}
508
70feadf3
VK		 509int vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
510 u64 *a0, u64 *a1, int wait)
511{
512 memset(vdev->args, 0, sizeof(vdev->args));
513
514 switch (vdev->proxy) {
889d13f5
RP		 515 case PROXY_BY_INDEX:
516 return vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_INDEX, cmd,
517 a0, a1, wait);
70feadf3 518 case PROXY_BY_BDF:
889d13f5
RP		 519 return vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_BDF, cmd,
520 a0, a1, wait);
70feadf3
VK		 521 case PROXY_NONE:
522 default:
523 return vnic_dev_cmd_no_proxy(vdev, cmd, a0, a1, wait);
524 }
525}
526
5e4232ee 527static int vnic_dev_capable(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd)
27372bf5
SF		 528{
529 u64 a0 = (u32)cmd, a1 = 0;
530 int wait = 1000;
531 int err;
532
533 err = vnic_dev_cmd(vdev, CMD_CAPABILITY, &a0, &a1, wait);
534
535 return !(err || a0);
536}
537
01f2e4ea
SF		 538int vnic_dev_fw_info(struct vnic_dev *vdev,
539 struct vnic_devcmd_fw_info **fw_info)
540{
541 u64 a0, a1 = 0;
542 int wait = 1000;
543 int err = 0;
544
545 if (!vdev->fw_info) {
87f44b4e
JP		 546 vdev->fw_info = pci_zalloc_consistent(vdev->pdev,
547 sizeof(struct vnic_devcmd_fw_info),
548 &vdev->fw_info_pa);
01f2e4ea
SF		 549 if (!vdev->fw_info)
550 return -ENOMEM;
551
552 a0 = vdev->fw_info_pa;
ea0f0d8b 553 a1 = sizeof(struct vnic_devcmd_fw_info);
01f2e4ea
SF		 554
555 /* only get fw_info once and cache it */
f8a6dd59
NP		 556 if (vnic_dev_capable(vdev, CMD_MCPU_FW_INFO))
557 err = vnic_dev_cmd(vdev, CMD_MCPU_FW_INFO,
558 &a0, &a1, wait);
559 else
ea0f0d8b
VK		 560 err = vnic_dev_cmd(vdev, CMD_MCPU_FW_INFO_OLD,
561 &a0, &a1, wait);
01f2e4ea
SF		 562 }
563
564 *fw_info = vdev->fw_info;
565
566 return err;
567}
568
569int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,
570 void *value)
571{
572 u64 a0, a1;
573 int wait = 1000;
574 int err;
575
576 a0 = offset;
577 a1 = size;
578
579 err = vnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);
580
581 switch (size) {
582 case 1: *(u8 *)value = (u8)a0; break;
583 case 2: *(u16 *)value = (u16)a0; break;
584 case 4: *(u32 *)value = (u32)a0; break;
585 case 8: *(u64 *)value = a0; break;
586 default: BUG(); break;
587 }
588
589 return err;
590}
591
01f2e4ea
SF		 592int vnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats)
593{
594 u64 a0, a1;
595 int wait = 1000;
596
597 if (!vdev->stats) {
598 vdev->stats = pci_alloc_consistent(vdev->pdev,
599 sizeof(struct vnic_stats), &vdev->stats_pa);
600 if (!vdev->stats)
601 return -ENOMEM;
602 }
603
604 *stats = vdev->stats;
605 a0 = vdev->stats_pa;
606 a1 = sizeof(struct vnic_stats);
607
608 return vnic_dev_cmd(vdev, CMD_STATS_DUMP, &a0, &a1, wait);
609}
610
611int vnic_dev_close(struct vnic_dev *vdev)
612{
613 u64 a0 = 0, a1 = 0;
614 int wait = 1000;
615 return vnic_dev_cmd(vdev, CMD_CLOSE, &a0, &a1, wait);
616}
617
2db77e0f 618int vnic_dev_enable_wait(struct vnic_dev *vdev)
01f2e4ea
SF		 619{
620 u64 a0 = 0, a1 = 0;
621 int wait = 1000;
2db77e0f 622
f8a6dd59
NP		 623 if (vnic_dev_capable(vdev, CMD_ENABLE_WAIT))
624 return vnic_dev_cmd(vdev, CMD_ENABLE_WAIT, &a0, &a1, wait);
625 else
2db77e0f 626 return vnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);
01f2e4ea
SF		 627}
628
629int vnic_dev_disable(struct vnic_dev *vdev)
630{
631 u64 a0 = 0, a1 = 0;
632 int wait = 1000;
633 return vnic_dev_cmd(vdev, CMD_DISABLE, &a0, &a1, wait);
634}
635
636int vnic_dev_open(struct vnic_dev *vdev, int arg)
637{
638 u64 a0 = (u32)arg, a1 = 0;
639 int wait = 1000;
640 return vnic_dev_cmd(vdev, CMD_OPEN, &a0, &a1, wait);
641}
642
643int vnic_dev_open_done(struct vnic_dev *vdev, int *done)
644{
645 u64 a0 = 0, a1 = 0;
646 int wait = 1000;
647 int err;
648
649 *done = 0;
650
651 err = vnic_dev_cmd(vdev, CMD_OPEN_STATUS, &a0, &a1, wait);
652 if (err)
653 return err;
654
655 *done = (a0 == 0);
656
657 return 0;
658}
659
2fdba388 660static int vnic_dev_soft_reset(struct vnic_dev *vdev, int arg)
01f2e4ea
SF		 661{
662 u64 a0 = (u32)arg, a1 = 0;
663 int wait = 1000;
664 return vnic_dev_cmd(vdev, CMD_SOFT_RESET, &a0, &a1, wait);
665}
666
2fdba388 667static int vnic_dev_soft_reset_done(struct vnic_dev *vdev, int *done)
01f2e4ea
SF		 668{
669 u64 a0 = 0, a1 = 0;
670 int wait = 1000;
671 int err;
672
673 *done = 0;
674
675 err = vnic_dev_cmd(vdev, CMD_SOFT_RESET_STATUS, &a0, &a1, wait);
676 if (err)
677 return err;
678
679 *done = (a0 == 0);
680
681 return 0;
682}
683
99ef5639
VK		 684int vnic_dev_hang_reset(struct vnic_dev *vdev, int arg)
685{
686 u64 a0 = (u32)arg, a1 = 0;
687 int wait = 1000;
688 int err;
689
f8a6dd59
NP		 690 if (vnic_dev_capable(vdev, CMD_HANG_RESET)) {
691 return vnic_dev_cmd(vdev, CMD_HANG_RESET,
692 &a0, &a1, wait);
693 } else {
99ef5639
VK		 694 err = vnic_dev_soft_reset(vdev, arg);
695 if (err)
696 return err;
99ef5639
VK		 697 return vnic_dev_init(vdev, 0);
698 }
99ef5639
VK		 699}
700
701int vnic_dev_hang_reset_done(struct vnic_dev *vdev, int *done)
702{
703 u64 a0 = 0, a1 = 0;
704 int wait = 1000;
705 int err;
706
707 *done = 0;
708
f8a6dd59
NP		 709 if (vnic_dev_capable(vdev, CMD_HANG_RESET_STATUS)) {
710 err = vnic_dev_cmd(vdev, CMD_HANG_RESET_STATUS,
711 &a0, &a1, wait);
712 if (err)
713 return err;
714 } else {
715 return vnic_dev_soft_reset_done(vdev, done);
99ef5639
VK		 716 }
717
718 *done = (a0 == 0);
719
720 return 0;
721}
722
01f2e4ea
SF		 723int vnic_dev_hang_notify(struct vnic_dev *vdev)
724{
725 u64 a0, a1;
726 int wait = 1000;
727 return vnic_dev_cmd(vdev, CMD_HANG_NOTIFY, &a0, &a1, wait);
728}
729
b13423ee 730int vnic_dev_get_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)
01f2e4ea
SF		 731{
732 u64 a0, a1;
733 int wait = 1000;
734 int err, i;
735
736 for (i = 0; i < ETH_ALEN; i++)
737 mac_addr[i] = 0;
738
b13423ee 739 err = vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);
01f2e4ea
SF		 740 if (err)
741 return err;
742
743 for (i = 0; i < ETH_ALEN; i++)
744 mac_addr[i] = ((u8 *)&a0)[i];
745
746 return 0;
747}
748
383ab92f 749int vnic_dev_packet_filter(struct vnic_dev *vdev, int directed, int multicast,
01f2e4ea
SF		 750 int broadcast, int promisc, int allmulti)
751{
752 u64 a0, a1 = 0;
753 int wait = 1000;
754 int err;
755
756 a0 = (directed ? CMD_PFILTER_DIRECTED : 0) |
757 (multicast ? CMD_PFILTER_MULTICAST : 0) |
758 (broadcast ? CMD_PFILTER_BROADCAST : 0) |
759 (promisc ? CMD_PFILTER_PROMISCUOUS : 0) |
760 (allmulti ? CMD_PFILTER_ALL_MULTICAST : 0);
761
762 err = vnic_dev_cmd(vdev, CMD_PACKET_FILTER, &a0, &a1, wait);
763 if (err)
6a3c2f83 764 vdev_neterr("Can't set packet filter\n");
383ab92f
VK		 765
766 return err;
01f2e4ea
SF		 767}
768
f009618a 769int vnic_dev_add_addr(struct vnic_dev *vdev, const u8 *addr)
01f2e4ea
SF		 770{
771 u64 a0 = 0, a1 = 0;
772 int wait = 1000;
773 int err;
774 int i;
775
776 for (i = 0; i < ETH_ALEN; i++)
777 ((u8 *)&a0)[i] = addr[i];
778
779 err = vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);
780 if (err)
6a3c2f83 781 vdev_neterr("Can't add addr [%pM], %d\n", addr, err);
f8bd9091
SF		 782
783 return err;
01f2e4ea
SF		 784}
785
f009618a 786int vnic_dev_del_addr(struct vnic_dev *vdev, const u8 *addr)
01f2e4ea
SF		 787{
788 u64 a0 = 0, a1 = 0;
789 int wait = 1000;
790 int err;
791 int i;
792
793 for (i = 0; i < ETH_ALEN; i++)
794 ((u8 *)&a0)[i] = addr[i];
795
796 err = vnic_dev_cmd(vdev, CMD_ADDR_DEL, &a0, &a1, wait);
797 if (err)
6a3c2f83 798 vdev_neterr("Can't del addr [%pM], %d\n", addr, err);
f8bd9091
SF		 799
800 return err;
01f2e4ea
SF		 801}
802
f8cac14a
VK		 803int vnic_dev_set_ig_vlan_rewrite_mode(struct vnic_dev *vdev,
804 u8 ig_vlan_rewrite_mode)
805{
806 u64 a0 = ig_vlan_rewrite_mode, a1 = 0;
807 int wait = 1000;
f8cac14a 808
f8a6dd59
NP		 809 if (vnic_dev_capable(vdev, CMD_IG_VLAN_REWRITE_MODE))
810 return vnic_dev_cmd(vdev, CMD_IG_VLAN_REWRITE_MODE,
811 &a0, &a1, wait);
812 else
f8cac14a 813 return 0;
f8cac14a
VK		 814}
815
2fdba388 816static int vnic_dev_notify_setcmd(struct vnic_dev *vdev,
d883aa76 817 void *notify_addr, dma_addr_t notify_pa, u16 intr)
01f2e4ea
SF		 818{
819 u64 a0, a1;
820 int wait = 1000;
27372bf5 821 int r;
01f2e4ea 822
d883aa76
VK		 823 memset(notify_addr, 0, sizeof(struct vnic_devcmd_notify));
824 vdev->notify = notify_addr;
825 vdev->notify_pa = notify_pa;
01f2e4ea 826
d883aa76 827 a0 = (u64)notify_pa;
01f2e4ea
SF		 828 a1 = ((u64)intr << 32) & 0x0000ffff00000000ULL;
829 a1 += sizeof(struct vnic_devcmd_notify);
830
27372bf5
SF		 831 r = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
832 vdev->notify_sz = (r == 0) ? (u32)a1 : 0;
833 return r;
01f2e4ea
SF		 834}
835
d883aa76
VK		 836int vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr)
837{
838 void *notify_addr;
839 dma_addr_t notify_pa;
840
841 if (vdev->notify || vdev->notify_pa) {
6a3c2f83 842 vdev_neterr("notify block %p still allocated", vdev->notify);
d883aa76
VK		 843 return -EINVAL;
844 }
845
846 notify_addr = pci_alloc_consistent(vdev->pdev,
847 sizeof(struct vnic_devcmd_notify),
848 &notify_pa);
849 if (!notify_addr)
850 return -ENOMEM;
851
852 return vnic_dev_notify_setcmd(vdev, notify_addr, notify_pa, intr);
853}
854
2fdba388 855static int vnic_dev_notify_unsetcmd(struct vnic_dev *vdev)
01f2e4ea
SF		 856{
857 u64 a0, a1;
858 int wait = 1000;
383ab92f 859 int err;
01f2e4ea
SF		 860
861 a0 = 0; /* paddr = 0 to unset notify buffer */
862 a1 = 0x0000ffff00000000ULL; /* intr num = -1 to unreg for intr */
863 a1 += sizeof(struct vnic_devcmd_notify);
864
383ab92f 865 err = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
d883aa76
VK		 866 vdev->notify = NULL;
867 vdev->notify_pa = 0;
27372bf5 868 vdev->notify_sz = 0;
383ab92f
VK		 869
870 return err;
01f2e4ea
SF		 871}
872
383ab92f 873int vnic_dev_notify_unset(struct vnic_dev *vdev)
d883aa76
VK		 874{
875 if (vdev->notify) {
876 pci_free_consistent(vdev->pdev,
877 sizeof(struct vnic_devcmd_notify),
878 vdev->notify,
879 vdev->notify_pa);
880 }
881
383ab92f 882 return vnic_dev_notify_unsetcmd(vdev);
d883aa76
VK		 883}
884
01f2e4ea
SF		 885static int vnic_dev_notify_ready(struct vnic_dev *vdev)
886{
887 u32 *words;
27372bf5 888 unsigned int nwords = vdev->notify_sz / 4;
01f2e4ea
SF		 889 unsigned int i;
890 u32 csum;
891
27372bf5 892 if (!vdev->notify || !vdev->notify_sz)
01f2e4ea
SF		 893 return 0;
894
895 do {
896 csum = 0;
27372bf5 897 memcpy(&vdev->notify_copy, vdev->notify, vdev->notify_sz);
01f2e4ea
SF		 898 words = (u32 *)&vdev->notify_copy;
899 for (i = 1; i < nwords; i++)
900 csum += words[i];
901 } while (csum != words[0]);
902
903 return 1;
904}
905
906int vnic_dev_init(struct vnic_dev *vdev, int arg)
907{
908 u64 a0 = (u32)arg, a1 = 0;
909 int wait = 1000;
4cdc44a2 910 int r = 0;
27372bf5 911
29046f9b 912 if (vnic_dev_capable(vdev, CMD_INIT))
27372bf5
SF		 913 r = vnic_dev_cmd(vdev, CMD_INIT, &a0, &a1, wait);
914 else {
915 vnic_dev_cmd(vdev, CMD_INIT_v1, &a0, &a1, wait);
916 if (a0 & CMD_INITF_DEFAULT_MAC) {
70feadf3
VK		 917 /* Emulate these for old CMD_INIT_v1 which
918 * didn't pass a0 so no CMD_INITF_*.
919 */
b13423ee 920 vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);
27372bf5
SF		 921 vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);
922 }
4cdc44a2
SF		 923 }
924 return r;
01f2e4ea
SF		 925}
926
f8bd9091
SF		 927int vnic_dev_deinit(struct vnic_dev *vdev)
928{
929 u64 a0 = 0, a1 = 0;
930 int wait = 1000;
931
932 return vnic_dev_cmd(vdev, CMD_DEINIT, &a0, &a1, wait);
933}
934
ea7ea65a
VK		 935void vnic_dev_intr_coal_timer_info_default(struct vnic_dev *vdev)
936{
937 /* Default: hardware intr coal timer is in units of 1.5 usecs */
938 vdev->intr_coal_timer_info.mul = 2;
939 vdev->intr_coal_timer_info.div = 3;
940 vdev->intr_coal_timer_info.max_usec =
941 vnic_dev_intr_coal_timer_hw_to_usec(vdev, 0xffff);
942}
943
944int vnic_dev_intr_coal_timer_info(struct vnic_dev *vdev)
945{
946 int wait = 1000;
947 int err;
948
949 memset(vdev->args, 0, sizeof(vdev->args));
950
f8a6dd59 951 if (vnic_dev_capable(vdev, CMD_INTR_COAL_CONVERT))
373fb087 952 err = vdev->devcmd_rtn(vdev, CMD_INTR_COAL_CONVERT, wait);
f8a6dd59
NP		 953 else
954 err = ERR_ECMDUNKNOWN;
ea7ea65a
VK		 955
956 /* Use defaults when firmware doesn't support the devcmd at all or
957 * supports it for only specific hardware
958 */
959 if ((err == ERR_ECMDUNKNOWN) ||
960 (!err && !(vdev->args[0] && vdev->args[1] && vdev->args[2]))) {
6a3c2f83 961 vdev_netwarn("Using default conversion factor for interrupt coalesce timer\n");
ea7ea65a
VK		 962 vnic_dev_intr_coal_timer_info_default(vdev);
963 return 0;
964 }
965
f8a6dd59
NP		 966 if (!err) {
967 vdev->intr_coal_timer_info.mul = (u32) vdev->args[0];
968 vdev->intr_coal_timer_info.div = (u32) vdev->args[1];
969 vdev->intr_coal_timer_info.max_usec = (u32) vdev->args[2];
970 }
ea7ea65a
VK		 971
972 return err;
973}
974
01f2e4ea
SF		 975int vnic_dev_link_status(struct vnic_dev *vdev)
976{
01f2e4ea
SF		 977 if (!vnic_dev_notify_ready(vdev))
978 return 0;
979
980 return vdev->notify_copy.link_state;
981}
982
983u32 vnic_dev_port_speed(struct vnic_dev *vdev)
984{
985 if (!vnic_dev_notify_ready(vdev))
986 return 0;
987
988 return vdev->notify_copy.port_speed;
989}
990
991u32 vnic_dev_msg_lvl(struct vnic_dev *vdev)
992{
993 if (!vnic_dev_notify_ready(vdev))
994 return 0;
995
996 return vdev->notify_copy.msglvl;
997}
998
999u32 vnic_dev_mtu(struct vnic_dev *vdev)
1000{
1001 if (!vnic_dev_notify_ready(vdev))
1002 return 0;
1003
1004 return vdev->notify_copy.mtu;
1005}
1006
1007void vnic_dev_set_intr_mode(struct vnic_dev *vdev,
1008 enum vnic_dev_intr_mode intr_mode)
1009{
1010 vdev->intr_mode = intr_mode;
1011}
1012
1013enum vnic_dev_intr_mode vnic_dev_get_intr_mode(
1014 struct vnic_dev *vdev)
1015{
1016 return vdev->intr_mode;
1017}
1018
ea7ea65a
VK		 1019u32 vnic_dev_intr_coal_timer_usec_to_hw(struct vnic_dev *vdev, u32 usec)
1020{
1021 return (usec * vdev->intr_coal_timer_info.mul) /
1022 vdev->intr_coal_timer_info.div;
1023}
1024
1025u32 vnic_dev_intr_coal_timer_hw_to_usec(struct vnic_dev *vdev, u32 hw_cycles)
1026{
1027 return (hw_cycles * vdev->intr_coal_timer_info.div) /
1028 vdev->intr_coal_timer_info.mul;
1029}
1030
1031u32 vnic_dev_get_intr_coal_timer_max(struct vnic_dev *vdev)
1032{
1033 return vdev->intr_coal_timer_info.max_usec;
1034}
1035
01f2e4ea
SF		 1036void vnic_dev_unregister(struct vnic_dev *vdev)
1037{
1038 if (vdev) {
1039 if (vdev->notify)
1040 pci_free_consistent(vdev->pdev,
1041 sizeof(struct vnic_devcmd_notify),
1042 vdev->notify,
1043 vdev->notify_pa);
01f2e4ea
SF		 1044 if (vdev->stats)
1045 pci_free_consistent(vdev->pdev,
29046f9b 1046 sizeof(struct vnic_stats),
01f2e4ea
SF		 1047 vdev->stats, vdev->stats_pa);
1048 if (vdev->fw_info)
1049 pci_free_consistent(vdev->pdev,
1050 sizeof(struct vnic_devcmd_fw_info),
1051 vdev->fw_info, vdev->fw_info_pa);
373fb087
GV		 1052 if (vdev->devcmd2)
1053 vnic_dev_deinit_devcmd2(vdev);
1054
01f2e4ea
SF		 1055 kfree(vdev);
1056 }
1057}
4a50ddfd 1058EXPORT_SYMBOL(vnic_dev_unregister);
01f2e4ea
SF		 1059
1060struct vnic_dev *vnic_dev_register(struct vnic_dev *vdev,
27e6c7d3
SF		 1061 void *priv, struct pci_dev *pdev, struct vnic_dev_bar *bar,
1062 unsigned int num_bars)
01f2e4ea
SF		 1063{
1064 if (!vdev) {
1065 vdev = kzalloc(sizeof(struct vnic_dev), GFP_ATOMIC);
1066 if (!vdev)
1067 return NULL;
1068 }
1069
1070 vdev->priv = priv;
1071 vdev->pdev = pdev;
1072
27e6c7d3 1073 if (vnic_dev_discover_res(vdev, bar, num_bars))
01f2e4ea
SF		 1074 goto err_out;
1075
01f2e4ea
SF		 1076 return vdev;
1077
1078err_out:
1079 vnic_dev_unregister(vdev);
1080 return NULL;
1081}
4a50ddfd 1082EXPORT_SYMBOL(vnic_dev_register);
1083
1084struct pci_dev *vnic_dev_get_pdev(struct vnic_dev *vdev)
1085{
1086 return vdev->pdev;
1087}
1088EXPORT_SYMBOL(vnic_dev_get_pdev);
01f2e4ea 1089
373fb087
GV		 1090int vnic_devcmd_init(struct vnic_dev *vdev)
1091{
f376d4ad 1092 void __iomem *res;
373fb087 1093 int err;
373fb087
GV		 1094
1095 res = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);
1096 if (res) {
1097 err = vnic_dev_init_devcmd2(vdev);
1098 if (err)
1099 vdev_warn("DEVCMD2 init failed: %d, Using DEVCMD1",
1100 err);
1101 else
1102 return 0;
1103 } else {
1104 vdev_warn("DEVCMD2 resource not found (old firmware?) Using DEVCMD1\n");
1105 }
1106 err = vnic_dev_init_devcmd1(vdev);
1107 if (err)
1108 vdev_err("DEVCMD1 initialization failed: %d", err);
1109
1110 return err;
1111}
1112
9085fd09
RP		 1113int vnic_dev_init_prov2(struct vnic_dev *vdev, u8 *buf, u32 len)
1114{
1115 u64 a0, a1 = len;
1116 int wait = 1000;
1117 dma_addr_t prov_pa;
1118 void *prov_buf;
1119 int ret;
1120
1121 prov_buf = pci_alloc_consistent(vdev->pdev, len, &prov_pa);
1122 if (!prov_buf)
1123 return -ENOMEM;
27372bf5 1124
9085fd09
RP		 1125 memcpy(prov_buf, buf, len);
1126
1127 a0 = prov_pa;
1128
1129 ret = vnic_dev_cmd(vdev, CMD_INIT_PROV_INFO2, &a0, &a1, wait);
1130
1131 pci_free_consistent(vdev->pdev, len, prov_buf, prov_pa);
1132
1133 return ret;
1134}
1135
1136int vnic_dev_enable2(struct vnic_dev *vdev, int active)
1137{
1138 u64 a0, a1 = 0;
1139 int wait = 1000;
1140
1141 a0 = (active ? CMD_ENABLE2_ACTIVE : 0);
1142
1143 return vnic_dev_cmd(vdev, CMD_ENABLE2, &a0, &a1, wait);
1144}
1145
1146static int vnic_dev_cmd_status(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
1147 int *status)
1148{
1149 u64 a0 = cmd, a1 = 0;
1150 int wait = 1000;
1151 int ret;
1152
1153 ret = vnic_dev_cmd(vdev, CMD_STATUS, &a0, &a1, wait);
1154 if (!ret)
1155 *status = (int)a0;
1156
1157 return ret;
1158}
1159
1160int vnic_dev_enable2_done(struct vnic_dev *vdev, int *status)
1161{
1162 return vnic_dev_cmd_status(vdev, CMD_ENABLE2, status);
1163}
1164
1165int vnic_dev_deinit_done(struct vnic_dev *vdev, int *status)
1166{
1167 return vnic_dev_cmd_status(vdev, CMD_DEINIT, status);
1168}
d6c81bc6
RP		 1169
1170int vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)
1171{
1172 u64 a0, a1;
1173 int wait = 1000;
1174 int i;
1175
1176 for (i = 0; i < ETH_ALEN; i++)
1177 ((u8 *)&a0)[i] = mac_addr[i];
1178
1179 return vnic_dev_cmd(vdev, CMD_SET_MAC_ADDR, &a0, &a1, wait);
1180}
63118527
GV		 1181
1182/* vnic_dev_classifier: Add/Delete classifier entries
1183 * @vdev: vdev of the device
1184 * @cmd: CLSF_ADD for Add filter
1185 * CLSF_DEL for Delete filter
1186 * @entry: In case of ADD filter, the caller passes the RQ number in this
1187 * variable.
1188 *
1189 * This function stores the filter_id returned by the firmware in the
1190 * same variable before return;
1191 *
1192 * In case of DEL filter, the caller passes the RQ number. Return
1193 * value is irrelevant.
1194 * @data: filter data
1195 */
1196int vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,
1197 struct filter *data)
1198{
1199 u64 a0, a1;
1200 int wait = 1000;
1201 dma_addr_t tlv_pa;
1202 int ret = -EINVAL;
1203 struct filter_tlv *tlv, *tlv_va;
1204 struct filter_action *action;
1205 u64 tlv_size;
1206
1207 if (cmd == CLSF_ADD) {
1208 tlv_size = sizeof(struct filter) +
1209 sizeof(struct filter_action) +
1210 2 * sizeof(struct filter_tlv);
1211 tlv_va = pci_alloc_consistent(vdev->pdev, tlv_size, &tlv_pa);
1212 if (!tlv_va)
1213 return -ENOMEM;
1214 tlv = tlv_va;
1215 a0 = tlv_pa;
1216 a1 = tlv_size;
1217 memset(tlv, 0, tlv_size);
1218 tlv->type = CLSF_TLV_FILTER;
1219 tlv->length = sizeof(struct filter);
1220 *(struct filter *)&tlv->val = *data;
1221
1222 tlv = (struct filter_tlv *)((char *)tlv +
1223 sizeof(struct filter_tlv) +
1224 sizeof(struct filter));
1225
1226 tlv->type = CLSF_TLV_ACTION;
1227 tlv->length = sizeof(struct filter_action);
1228 action = (struct filter_action *)&tlv->val;
1229 action->type = FILTER_ACTION_RQ_STEERING;
1230 action->u.rq_idx = *entry;
1231
1232 ret = vnic_dev_cmd(vdev, CMD_ADD_FILTER, &a0, &a1, wait);
1233 *entry = (u16)a0;
1234 pci_free_consistent(vdev->pdev, tlv_size, tlv_va, tlv_pa);
1235 } else if (cmd == CLSF_DEL) {
1236 a0 = *entry;
1237 ret = vnic_dev_cmd(vdev, CMD_DEL_FILTER, &a0, &a1, wait);
1238 }
1239
1240 return ret;
1241}
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