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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / cisco / enic / vnic_dev.c
CommitLineData
01f2e4ea 1/*
29046f9b 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea
SF
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 *
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/delay.h>
25#include <linux/if_ether.h>
26
27#include "vnic_resource.h"
28#include "vnic_devcmd.h"
29#include "vnic_dev.h"
373fb087 30#include "vnic_wq.h"
01f2e4ea 31#include "vnic_stats.h"
6a3c2f83 32#include "enic.h"
01f2e4ea 33
01f2e4ea
SF
34#define VNIC_MAX_RES_HDR_SIZE \
35 (sizeof(struct vnic_resource_header) + \
36 sizeof(struct vnic_resource) * RES_TYPE_MAX)
37#define VNIC_RES_STRIDE 128
38
39void *vnic_dev_priv(struct vnic_dev *vdev)
40{
41 return vdev->priv;
42}
43
44static int vnic_dev_discover_res(struct vnic_dev *vdev,
27e6c7d3 45 struct vnic_dev_bar *bar, unsigned int num_bars)
01f2e4ea
SF
46{
47 struct vnic_resource_header __iomem *rh;
90cf0b53 48 struct mgmt_barmap_hdr __iomem *mrh;
01f2e4ea
SF
49 struct vnic_resource __iomem *r;
50 u8 type;
51
27e6c7d3
SF
52 if (num_bars == 0)
53 return -EINVAL;
54
01f2e4ea 55 if (bar->len < VNIC_MAX_RES_HDR_SIZE) {
e327f4e1 56 vdev_err(vdev, "vNIC BAR0 res hdr length error\n");
01f2e4ea
SF
57 return -EINVAL;
58 }
59
90cf0b53
RP
60 rh = bar->vaddr;
61 mrh = bar->vaddr;
01f2e4ea 62 if (!rh) {
e327f4e1 63 vdev_err(vdev, "vNIC BAR0 res hdr not mem-mapped\n");
01f2e4ea
SF
64 return -EINVAL;
65 }
66
90cf0b53
RP
67 /* Check for mgmt vnic in addition to normal vnic */
68 if ((ioread32(&rh->magic) != VNIC_RES_MAGIC) ||
69 (ioread32(&rh->version) != VNIC_RES_VERSION)) {
70 if ((ioread32(&mrh->magic) != MGMTVNIC_MAGIC) ||
71 (ioread32(&mrh->version) != MGMTVNIC_VERSION)) {
e327f4e1 72 vdev_err(vdev, "vNIC BAR0 res magic/version error exp (%lx/%lx) or (%lx/%lx), curr (%x/%x)\n",
6a3c2f83
GV
73 VNIC_RES_MAGIC, VNIC_RES_VERSION,
74 MGMTVNIC_MAGIC, MGMTVNIC_VERSION,
75 ioread32(&rh->magic), ioread32(&rh->version));
90cf0b53
RP
76 return -EINVAL;
77 }
01f2e4ea
SF
78 }
79
90cf0b53
RP
80 if (ioread32(&mrh->magic) == MGMTVNIC_MAGIC)
81 r = (struct vnic_resource __iomem *)(mrh + 1);
82 else
83 r = (struct vnic_resource __iomem *)(rh + 1);
84
01f2e4ea
SF
85
86 while ((type = ioread8(&r->type)) != RES_TYPE_EOL) {
87
88 u8 bar_num = ioread8(&r->bar);
89 u32 bar_offset = ioread32(&r->bar_offset);
90 u32 count = ioread32(&r->count);
91 u32 len;
92
93 r++;
94
27e6c7d3
SF
95 if (bar_num >= num_bars)
96 continue;
97
98 if (!bar[bar_num].len || !bar[bar_num].vaddr)
01f2e4ea
SF
99 continue;
100
101 switch (type) {
102 case RES_TYPE_WQ:
103 case RES_TYPE_RQ:
104 case RES_TYPE_CQ:
105 case RES_TYPE_INTR_CTRL:
106 /* each count is stride bytes long */
107 len = count * VNIC_RES_STRIDE;
27e6c7d3 108 if (len + bar_offset > bar[bar_num].len) {
e327f4e1 109 vdev_err(vdev, "vNIC BAR0 resource %d out-of-bounds, offset 0x%x + size 0x%x > bar len 0x%lx\n",
6a3c2f83
GV
110 type, bar_offset, len,
111 bar[bar_num].len);
01f2e4ea
SF
112 return -EINVAL;
113 }
114 break;
115 case RES_TYPE_INTR_PBA_LEGACY:
116 case RES_TYPE_DEVCMD:
373fb087 117 case RES_TYPE_DEVCMD2:
01f2e4ea
SF
118 len = count;
119 break;
120 default:
121 continue;
122 }
123
124 vdev->res[type].count = count;
27e6c7d3
SF
125 vdev->res[type].vaddr = (char __iomem *)bar[bar_num].vaddr +
126 bar_offset;
127 vdev->res[type].bus_addr = bar[bar_num].bus_addr + bar_offset;
01f2e4ea
SF
128 }
129
130 return 0;
131}
132
133unsigned int vnic_dev_get_res_count(struct vnic_dev *vdev,
134 enum vnic_res_type type)
135{
136 return vdev->res[type].count;
137}
4a50ddfd 138EXPORT_SYMBOL(vnic_dev_get_res_count);
01f2e4ea
SF
139
140void __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,
141 unsigned int index)
142{
143 if (!vdev->res[type].vaddr)
144 return NULL;
145
146 switch (type) {
147 case RES_TYPE_WQ:
148 case RES_TYPE_RQ:
149 case RES_TYPE_CQ:
150 case RES_TYPE_INTR_CTRL:
151 return (char __iomem *)vdev->res[type].vaddr +
152 index * VNIC_RES_STRIDE;
153 default:
154 return (char __iomem *)vdev->res[type].vaddr;
155 }
156}
4a50ddfd 157EXPORT_SYMBOL(vnic_dev_get_res);
01f2e4ea 158
2fdba388 159static unsigned int vnic_dev_desc_ring_size(struct vnic_dev_ring *ring,
01f2e4ea
SF
160 unsigned int desc_count, unsigned int desc_size)
161{
162 /* The base address of the desc rings must be 512 byte aligned.
163 * Descriptor count is aligned to groups of 32 descriptors. A
164 * count of 0 means the maximum 4096 descriptors. Descriptor
165 * size is aligned to 16 bytes.
166 */
167
168 unsigned int count_align = 32;
169 unsigned int desc_align = 16;
170
171 ring->base_align = 512;
172
173 if (desc_count == 0)
174 desc_count = 4096;
175
176 ring->desc_count = ALIGN(desc_count, count_align);
177
178 ring->desc_size = ALIGN(desc_size, desc_align);
179
180 ring->size = ring->desc_count * ring->desc_size;
181 ring->size_unaligned = ring->size + ring->base_align;
182
183 return ring->size_unaligned;
184}
185
186void vnic_dev_clear_desc_ring(struct vnic_dev_ring *ring)
187{
188 memset(ring->descs, 0, ring->size);
189}
190
191int vnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,
192 unsigned int desc_count, unsigned int desc_size)
193{
194 vnic_dev_desc_ring_size(ring, desc_count, desc_size);
195
196 ring->descs_unaligned = pci_alloc_consistent(vdev->pdev,
197 ring->size_unaligned,
198 &ring->base_addr_unaligned);
199
200 if (!ring->descs_unaligned) {
e327f4e1 201 vdev_err(vdev, "Failed to allocate ring (size=%d), aborting\n",
6a3c2f83 202 (int)ring->size);
01f2e4ea
SF
203 return -ENOMEM;
204 }
205
206 ring->base_addr = ALIGN(ring->base_addr_unaligned,
207 ring->base_align);
208 ring->descs = (u8 *)ring->descs_unaligned +
209 (ring->base_addr - ring->base_addr_unaligned);
210
211 vnic_dev_clear_desc_ring(ring);
212
213 ring->desc_avail = ring->desc_count - 1;
214
215 return 0;
216}
217
218void vnic_dev_free_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring)
219{
220 if (ring->descs) {
221 pci_free_consistent(vdev->pdev,
222 ring->size_unaligned,
223 ring->descs_unaligned,
224 ring->base_addr_unaligned);
225 ring->descs = NULL;
226 }
227}
228
70feadf3
VK
229static int _vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
230 int wait)
01f2e4ea
SF
231{
232 struct vnic_devcmd __iomem *devcmd = vdev->devcmd;
70feadf3 233 unsigned int i;
01f2e4ea
SF
234 int delay;
235 u32 status;
01f2e4ea
SF
236 int err;
237
238 status = ioread32(&devcmd->status);
506e1198
VK
239 if (status == 0xFFFFFFFF) {
240 /* PCI-e target device is gone */
241 return -ENODEV;
242 }
01f2e4ea 243 if (status & STAT_BUSY) {
e327f4e1 244 vdev_neterr(vdev, "Busy devcmd %d\n", _CMD_N(cmd));
01f2e4ea
SF
245 return -EBUSY;
246 }
247
248 if (_CMD_DIR(cmd) & _CMD_DIR_WRITE) {
70feadf3
VK
249 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
250 writeq(vdev->args[i], &devcmd->args[i]);
01f2e4ea
SF
251 wmb();
252 }
253
254 iowrite32(cmd, &devcmd->cmd);
255
256 if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
27e6c7d3 257 return 0;
01f2e4ea
SF
258
259 for (delay = 0; delay < wait; delay++) {
260
261 udelay(100);
262
263 status = ioread32(&devcmd->status);
506e1198
VK
264 if (status == 0xFFFFFFFF) {
265 /* PCI-e target device is gone */
266 return -ENODEV;
267 }
70feadf3 268
01f2e4ea
SF
269 if (!(status & STAT_BUSY)) {
270
271 if (status & STAT_ERROR) {
27372bf5 272 err = (int)readq(&devcmd->args[0]);
07783f39
SA
273 if (err == ERR_EINVAL &&
274 cmd == CMD_CAPABILITY)
10cc8844 275 return -err;
27372bf5
SF
276 if (err != ERR_ECMDUNKNOWN ||
277 cmd != CMD_CAPABILITY)
e327f4e1 278 vdev_neterr(vdev, "Error %d devcmd %d\n",
6a3c2f83 279 err, _CMD_N(cmd));
10cc8844 280 return -err;
01f2e4ea
SF
281 }
282
283 if (_CMD_DIR(cmd) & _CMD_DIR_READ) {
284 rmb();
70feadf3
VK
285 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
286 vdev->args[i] = readq(&devcmd->args[i]);
01f2e4ea
SF
287 }
288
289 return 0;
290 }
291 }
292
e327f4e1 293 vdev_neterr(vdev, "Timedout devcmd %d\n", _CMD_N(cmd));
01f2e4ea
SF
294 return -ETIMEDOUT;
295}
296
373fb087
GV
297static int _vnic_dev_cmd2(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
298 int wait)
299{
300 struct devcmd2_controller *dc2c = vdev->devcmd2;
ca7f41a4
SP
301 struct devcmd2_result *result;
302 u8 color;
373fb087
GV
303 unsigned int i;
304 int delay, err;
dafc2199
GV
305 u32 fetch_index, new_posted;
306 u32 posted = dc2c->posted;
373fb087 307
373fb087
GV
308 fetch_index = ioread32(&dc2c->wq_ctrl->fetch_index);
309
dafc2199 310 if (fetch_index == 0xFFFFFFFF)
373fb087
GV
311 return -ENODEV;
312
313 new_posted = (posted + 1) % DEVCMD2_RING_SIZE;
314
315 if (new_posted == fetch_index) {
e327f4e1 316 vdev_neterr(vdev, "devcmd2 %d: wq is full. fetch index: %u, posted index: %u\n",
373fb087
GV
317 _CMD_N(cmd), fetch_index, posted);
318 return -EBUSY;
319 }
320 dc2c->cmd_ring[posted].cmd = cmd;
321 dc2c->cmd_ring[posted].flags = 0;
322
323 if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
324 dc2c->cmd_ring[posted].flags |= DEVCMD2_FNORESULT;
325 if (_CMD_DIR(cmd) & _CMD_DIR_WRITE)
326 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
327 dc2c->cmd_ring[posted].args[i] = vdev->args[i];
328
329 /* Adding write memory barrier prevents compiler and/or CPU reordering,
330 * thus avoiding descriptor posting before descriptor is initialized.
331 * Otherwise, hardware can read stale descriptor fields.
332 */
333 wmb();
334 iowrite32(new_posted, &dc2c->wq_ctrl->posted_index);
dafc2199 335 dc2c->posted = new_posted;
373fb087
GV
336
337 if (dc2c->cmd_ring[posted].flags & DEVCMD2_FNORESULT)
338 return 0;
339
ca7f41a4
SP
340 result = dc2c->result + dc2c->next_result;
341 color = dc2c->color;
342
343 dc2c->next_result++;
344 if (dc2c->next_result == dc2c->result_size) {
345 dc2c->next_result = 0;
346 dc2c->color = dc2c->color ? 0 : 1;
347 }
348
373fb087 349 for (delay = 0; delay < wait; delay++) {
ca7f41a4 350 if (result->color == color) {
373fb087
GV
351 if (result->error) {
352 err = result->error;
353 if (err != ERR_ECMDUNKNOWN ||
354 cmd != CMD_CAPABILITY)
e327f4e1 355 vdev_neterr(vdev, "Error %d devcmd %d\n",
373fb087
GV
356 err, _CMD_N(cmd));
357 return -err;
358 }
359 if (_CMD_DIR(cmd) & _CMD_DIR_READ)
360 for (i = 0; i < VNIC_DEVCMD2_NARGS; i++)
361 vdev->args[i] = result->results[i];
362
363 return 0;
364 }
365 udelay(100);
366 }
367
e327f4e1 368 vdev_neterr(vdev, "devcmd %d timed out\n", _CMD_N(cmd));
373fb087
GV
369
370 return -ETIMEDOUT;
371}
372
373static int vnic_dev_init_devcmd1(struct vnic_dev *vdev)
374{
375 vdev->devcmd = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD, 0);
376 if (!vdev->devcmd)
377 return -ENODEV;
378 vdev->devcmd_rtn = _vnic_dev_cmd;
379
380 return 0;
381}
382
383static int vnic_dev_init_devcmd2(struct vnic_dev *vdev)
384{
385 int err;
386 unsigned int fetch_index;
387
388 if (vdev->devcmd2)
389 return 0;
390
391 vdev->devcmd2 = kzalloc(sizeof(*vdev->devcmd2), GFP_KERNEL);
392 if (!vdev->devcmd2)
393 return -ENOMEM;
394
395 vdev->devcmd2->color = 1;
396 vdev->devcmd2->result_size = DEVCMD2_RING_SIZE;
3dc33e23 397 err = enic_wq_devcmd2_alloc(vdev, &vdev->devcmd2->wq, DEVCMD2_RING_SIZE,
373fb087
GV
398 DEVCMD2_DESC_SIZE);
399 if (err)
400 goto err_free_devcmd2;
401
402 fetch_index = ioread32(&vdev->devcmd2->wq.ctrl->fetch_index);
403 if (fetch_index == 0xFFFFFFFF) { /* check for hardware gone */
e327f4e1 404 vdev_err(vdev, "Fatal error in devcmd2 init - hardware surprise removal\n");
373fb087
GV
405
406 return -ENODEV;
407 }
408
3dc33e23 409 enic_wq_init_start(&vdev->devcmd2->wq, 0, fetch_index, fetch_index, 0,
373fb087 410 0);
dafc2199 411 vdev->devcmd2->posted = fetch_index;
373fb087
GV
412 vnic_wq_enable(&vdev->devcmd2->wq);
413
414 err = vnic_dev_alloc_desc_ring(vdev, &vdev->devcmd2->results_ring,
415 DEVCMD2_RING_SIZE, DEVCMD2_DESC_SIZE);
416 if (err)
417 goto err_free_wq;
418
419 vdev->devcmd2->result = vdev->devcmd2->results_ring.descs;
420 vdev->devcmd2->cmd_ring = vdev->devcmd2->wq.ring.descs;
421 vdev->devcmd2->wq_ctrl = vdev->devcmd2->wq.ctrl;
422 vdev->args[0] = (u64)vdev->devcmd2->results_ring.base_addr |
423 VNIC_PADDR_TARGET;
424 vdev->args[1] = DEVCMD2_RING_SIZE;
425
426 err = _vnic_dev_cmd2(vdev, CMD_INITIALIZE_DEVCMD2, 1000);
427 if (err)
428 goto err_free_desc_ring;
429
430 vdev->devcmd_rtn = _vnic_dev_cmd2;
431
432 return 0;
433
434err_free_desc_ring:
435 vnic_dev_free_desc_ring(vdev, &vdev->devcmd2->results_ring);
436err_free_wq:
437 vnic_wq_disable(&vdev->devcmd2->wq);
438 vnic_wq_free(&vdev->devcmd2->wq);
439err_free_devcmd2:
440 kfree(vdev->devcmd2);
441 vdev->devcmd2 = NULL;
442
443 return err;
444}
445
446static void vnic_dev_deinit_devcmd2(struct vnic_dev *vdev)
447{
448 vnic_dev_free_desc_ring(vdev, &vdev->devcmd2->results_ring);
449 vnic_wq_disable(&vdev->devcmd2->wq);
450 vnic_wq_free(&vdev->devcmd2->wq);
451 kfree(vdev->devcmd2);
452}
453
889d13f5
RP
454static int vnic_dev_cmd_proxy(struct vnic_dev *vdev,
455 enum vnic_devcmd_cmd proxy_cmd, enum vnic_devcmd_cmd cmd,
456 u64 *a0, u64 *a1, int wait)
70feadf3
VK
457{
458 u32 status;
459 int err;
460
461 memset(vdev->args, 0, sizeof(vdev->args));
462
889d13f5 463 vdev->args[0] = vdev->proxy_index;
70feadf3
VK
464 vdev->args[1] = cmd;
465 vdev->args[2] = *a0;
466 vdev->args[3] = *a1;
467
373fb087 468 err = vdev->devcmd_rtn(vdev, proxy_cmd, wait);
70feadf3
VK
469 if (err)
470 return err;
471
472 status = (u32)vdev->args[0];
473 if (status & STAT_ERROR) {
474 err = (int)vdev->args[1];
475 if (err != ERR_ECMDUNKNOWN ||
476 cmd != CMD_CAPABILITY)
e327f4e1
JP
477 vdev_neterr(vdev, "Error %d proxy devcmd %d\n",
478 err, _CMD_N(cmd));
70feadf3
VK
479 return err;
480 }
481
482 *a0 = vdev->args[1];
483 *a1 = vdev->args[2];
484
485 return 0;
486}
487
488static int vnic_dev_cmd_no_proxy(struct vnic_dev *vdev,
489 enum vnic_devcmd_cmd cmd, u64 *a0, u64 *a1, int wait)
490{
491 int err;
492
493 vdev->args[0] = *a0;
494 vdev->args[1] = *a1;
495
373fb087 496 err = vdev->devcmd_rtn(vdev, cmd, wait);
70feadf3
VK
497
498 *a0 = vdev->args[0];
499 *a1 = vdev->args[1];
500
501 return err;
502}
503
889d13f5
RP
504void vnic_dev_cmd_proxy_by_index_start(struct vnic_dev *vdev, u16 index)
505{
506 vdev->proxy = PROXY_BY_INDEX;
507 vdev->proxy_index = index;
508}
509
510void vnic_dev_cmd_proxy_end(struct vnic_dev *vdev)
511{
512 vdev->proxy = PROXY_NONE;
513 vdev->proxy_index = 0;
514}
515
70feadf3
VK
516int vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
517 u64 *a0, u64 *a1, int wait)
518{
519 memset(vdev->args, 0, sizeof(vdev->args));
520
521 switch (vdev->proxy) {
889d13f5
RP
522 case PROXY_BY_INDEX:
523 return vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_INDEX, cmd,
524 a0, a1, wait);
70feadf3 525 case PROXY_BY_BDF:
889d13f5
RP
526 return vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_BDF, cmd,
527 a0, a1, wait);
70feadf3
VK
528 case PROXY_NONE:
529 default:
530 return vnic_dev_cmd_no_proxy(vdev, cmd, a0, a1, wait);
531 }
532}
533
5e4232ee 534static int vnic_dev_capable(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd)
27372bf5
SF
535{
536 u64 a0 = (u32)cmd, a1 = 0;
537 int wait = 1000;
538 int err;
539
540 err = vnic_dev_cmd(vdev, CMD_CAPABILITY, &a0, &a1, wait);
541
542 return !(err || a0);
543}
544
01f2e4ea
SF
545int vnic_dev_fw_info(struct vnic_dev *vdev,
546 struct vnic_devcmd_fw_info **fw_info)
547{
548 u64 a0, a1 = 0;
549 int wait = 1000;
550 int err = 0;
551
552 if (!vdev->fw_info) {
87f44b4e
JP
553 vdev->fw_info = pci_zalloc_consistent(vdev->pdev,
554 sizeof(struct vnic_devcmd_fw_info),
555 &vdev->fw_info_pa);
01f2e4ea
SF
556 if (!vdev->fw_info)
557 return -ENOMEM;
558
559 a0 = vdev->fw_info_pa;
ea0f0d8b 560 a1 = sizeof(struct vnic_devcmd_fw_info);
01f2e4ea
SF
561
562 /* only get fw_info once and cache it */
f8a6dd59
NP
563 if (vnic_dev_capable(vdev, CMD_MCPU_FW_INFO))
564 err = vnic_dev_cmd(vdev, CMD_MCPU_FW_INFO,
565 &a0, &a1, wait);
566 else
ea0f0d8b
VK
567 err = vnic_dev_cmd(vdev, CMD_MCPU_FW_INFO_OLD,
568 &a0, &a1, wait);
01f2e4ea
SF
569 }
570
571 *fw_info = vdev->fw_info;
572
573 return err;
574}
575
576int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,
577 void *value)
578{
579 u64 a0, a1;
580 int wait = 1000;
581 int err;
582
583 a0 = offset;
584 a1 = size;
585
586 err = vnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);
587
588 switch (size) {
589 case 1: *(u8 *)value = (u8)a0; break;
590 case 2: *(u16 *)value = (u16)a0; break;
591 case 4: *(u32 *)value = (u32)a0; break;
592 case 8: *(u64 *)value = a0; break;
593 default: BUG(); break;
594 }
595
596 return err;
597}
598
01f2e4ea
SF
599int vnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats)
600{
601 u64 a0, a1;
602 int wait = 1000;
603
604 if (!vdev->stats) {
605 vdev->stats = pci_alloc_consistent(vdev->pdev,
606 sizeof(struct vnic_stats), &vdev->stats_pa);
607 if (!vdev->stats)
608 return -ENOMEM;
609 }
610
611 *stats = vdev->stats;
612 a0 = vdev->stats_pa;
613 a1 = sizeof(struct vnic_stats);
614
615 return vnic_dev_cmd(vdev, CMD_STATS_DUMP, &a0, &a1, wait);
616}
617
618int vnic_dev_close(struct vnic_dev *vdev)
619{
620 u64 a0 = 0, a1 = 0;
621 int wait = 1000;
622 return vnic_dev_cmd(vdev, CMD_CLOSE, &a0, &a1, wait);
623}
624
2db77e0f 625int vnic_dev_enable_wait(struct vnic_dev *vdev)
01f2e4ea
SF
626{
627 u64 a0 = 0, a1 = 0;
628 int wait = 1000;
2db77e0f 629
f8a6dd59
NP
630 if (vnic_dev_capable(vdev, CMD_ENABLE_WAIT))
631 return vnic_dev_cmd(vdev, CMD_ENABLE_WAIT, &a0, &a1, wait);
632 else
2db77e0f 633 return vnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);
01f2e4ea
SF
634}
635
636int vnic_dev_disable(struct vnic_dev *vdev)
637{
638 u64 a0 = 0, a1 = 0;
639 int wait = 1000;
640 return vnic_dev_cmd(vdev, CMD_DISABLE, &a0, &a1, wait);
641}
642
643int vnic_dev_open(struct vnic_dev *vdev, int arg)
644{
645 u64 a0 = (u32)arg, a1 = 0;
646 int wait = 1000;
647 return vnic_dev_cmd(vdev, CMD_OPEN, &a0, &a1, wait);
648}
649
650int vnic_dev_open_done(struct vnic_dev *vdev, int *done)
651{
652 u64 a0 = 0, a1 = 0;
653 int wait = 1000;
654 int err;
655
656 *done = 0;
657
658 err = vnic_dev_cmd(vdev, CMD_OPEN_STATUS, &a0, &a1, wait);
659 if (err)
660 return err;
661
662 *done = (a0 == 0);
663
664 return 0;
665}
666
937317c7 667int vnic_dev_soft_reset(struct vnic_dev *vdev, int arg)
01f2e4ea
SF
668{
669 u64 a0 = (u32)arg, a1 = 0;
670 int wait = 1000;
671 return vnic_dev_cmd(vdev, CMD_SOFT_RESET, &a0, &a1, wait);
672}
673
937317c7 674int vnic_dev_soft_reset_done(struct vnic_dev *vdev, int *done)
01f2e4ea
SF
675{
676 u64 a0 = 0, a1 = 0;
677 int wait = 1000;
678 int err;
679
680 *done = 0;
681
682 err = vnic_dev_cmd(vdev, CMD_SOFT_RESET_STATUS, &a0, &a1, wait);
683 if (err)
684 return err;
685
686 *done = (a0 == 0);
687
688 return 0;
689}
690
99ef5639
VK
691int vnic_dev_hang_reset(struct vnic_dev *vdev, int arg)
692{
693 u64 a0 = (u32)arg, a1 = 0;
694 int wait = 1000;
695 int err;
696
f8a6dd59
NP
697 if (vnic_dev_capable(vdev, CMD_HANG_RESET)) {
698 return vnic_dev_cmd(vdev, CMD_HANG_RESET,
699 &a0, &a1, wait);
700 } else {
99ef5639
VK
701 err = vnic_dev_soft_reset(vdev, arg);
702 if (err)
703 return err;
99ef5639
VK
704 return vnic_dev_init(vdev, 0);
705 }
99ef5639
VK
706}
707
708int vnic_dev_hang_reset_done(struct vnic_dev *vdev, int *done)
709{
710 u64 a0 = 0, a1 = 0;
711 int wait = 1000;
712 int err;
713
714 *done = 0;
715
f8a6dd59
NP
716 if (vnic_dev_capable(vdev, CMD_HANG_RESET_STATUS)) {
717 err = vnic_dev_cmd(vdev, CMD_HANG_RESET_STATUS,
718 &a0, &a1, wait);
719 if (err)
720 return err;
721 } else {
722 return vnic_dev_soft_reset_done(vdev, done);
99ef5639
VK
723 }
724
725 *done = (a0 == 0);
726
727 return 0;
728}
729
01f2e4ea
SF
730int vnic_dev_hang_notify(struct vnic_dev *vdev)
731{
732 u64 a0, a1;
733 int wait = 1000;
734 return vnic_dev_cmd(vdev, CMD_HANG_NOTIFY, &a0, &a1, wait);
735}
736
b13423ee 737int vnic_dev_get_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)
01f2e4ea
SF
738{
739 u64 a0, a1;
740 int wait = 1000;
741 int err, i;
742
743 for (i = 0; i < ETH_ALEN; i++)
744 mac_addr[i] = 0;
745
b13423ee 746 err = vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);
01f2e4ea
SF
747 if (err)
748 return err;
749
750 for (i = 0; i < ETH_ALEN; i++)
751 mac_addr[i] = ((u8 *)&a0)[i];
752
753 return 0;
754}
755
383ab92f 756int vnic_dev_packet_filter(struct vnic_dev *vdev, int directed, int multicast,
01f2e4ea
SF
757 int broadcast, int promisc, int allmulti)
758{
759 u64 a0, a1 = 0;
760 int wait = 1000;
761 int err;
762
763 a0 = (directed ? CMD_PFILTER_DIRECTED : 0) |
764 (multicast ? CMD_PFILTER_MULTICAST : 0) |
765 (broadcast ? CMD_PFILTER_BROADCAST : 0) |
766 (promisc ? CMD_PFILTER_PROMISCUOUS : 0) |
767 (allmulti ? CMD_PFILTER_ALL_MULTICAST : 0);
768
769 err = vnic_dev_cmd(vdev, CMD_PACKET_FILTER, &a0, &a1, wait);
770 if (err)
e327f4e1 771 vdev_neterr(vdev, "Can't set packet filter\n");
383ab92f
VK
772
773 return err;
01f2e4ea
SF
774}
775
f009618a 776int vnic_dev_add_addr(struct vnic_dev *vdev, const u8 *addr)
01f2e4ea
SF
777{
778 u64 a0 = 0, a1 = 0;
779 int wait = 1000;
780 int err;
781 int i;
782
783 for (i = 0; i < ETH_ALEN; i++)
784 ((u8 *)&a0)[i] = addr[i];
785
786 err = vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);
787 if (err)
e327f4e1 788 vdev_neterr(vdev, "Can't add addr [%pM], %d\n", addr, err);
f8bd9091
SF
789
790 return err;
01f2e4ea
SF
791}
792
f009618a 793int vnic_dev_del_addr(struct vnic_dev *vdev, const u8 *addr)
01f2e4ea
SF
794{
795 u64 a0 = 0, a1 = 0;
796 int wait = 1000;
797 int err;
798 int i;
799
800 for (i = 0; i < ETH_ALEN; i++)
801 ((u8 *)&a0)[i] = addr[i];
802
803 err = vnic_dev_cmd(vdev, CMD_ADDR_DEL, &a0, &a1, wait);
804 if (err)
e327f4e1 805 vdev_neterr(vdev, "Can't del addr [%pM], %d\n", addr, err);
f8bd9091
SF
806
807 return err;
01f2e4ea
SF
808}
809
f8cac14a
VK
810int vnic_dev_set_ig_vlan_rewrite_mode(struct vnic_dev *vdev,
811 u8 ig_vlan_rewrite_mode)
812{
813 u64 a0 = ig_vlan_rewrite_mode, a1 = 0;
814 int wait = 1000;
f8cac14a 815
f8a6dd59
NP
816 if (vnic_dev_capable(vdev, CMD_IG_VLAN_REWRITE_MODE))
817 return vnic_dev_cmd(vdev, CMD_IG_VLAN_REWRITE_MODE,
818 &a0, &a1, wait);
819 else
f8cac14a 820 return 0;
f8cac14a
VK
821}
822
2fdba388 823static int vnic_dev_notify_setcmd(struct vnic_dev *vdev,
d883aa76 824 void *notify_addr, dma_addr_t notify_pa, u16 intr)
01f2e4ea
SF
825{
826 u64 a0, a1;
827 int wait = 1000;
27372bf5 828 int r;
01f2e4ea 829
d883aa76
VK
830 memset(notify_addr, 0, sizeof(struct vnic_devcmd_notify));
831 vdev->notify = notify_addr;
832 vdev->notify_pa = notify_pa;
01f2e4ea 833
d883aa76 834 a0 = (u64)notify_pa;
01f2e4ea
SF
835 a1 = ((u64)intr << 32) & 0x0000ffff00000000ULL;
836 a1 += sizeof(struct vnic_devcmd_notify);
837
27372bf5
SF
838 r = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
839 vdev->notify_sz = (r == 0) ? (u32)a1 : 0;
840 return r;
01f2e4ea
SF
841}
842
d883aa76
VK
843int vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr)
844{
845 void *notify_addr;
846 dma_addr_t notify_pa;
847
848 if (vdev->notify || vdev->notify_pa) {
e327f4e1
JP
849 vdev_neterr(vdev, "notify block %p still allocated\n",
850 vdev->notify);
d883aa76
VK
851 return -EINVAL;
852 }
853
854 notify_addr = pci_alloc_consistent(vdev->pdev,
855 sizeof(struct vnic_devcmd_notify),
856 &notify_pa);
857 if (!notify_addr)
858 return -ENOMEM;
859
860 return vnic_dev_notify_setcmd(vdev, notify_addr, notify_pa, intr);
861}
862
2fdba388 863static int vnic_dev_notify_unsetcmd(struct vnic_dev *vdev)
01f2e4ea
SF
864{
865 u64 a0, a1;
866 int wait = 1000;
383ab92f 867 int err;
01f2e4ea
SF
868
869 a0 = 0; /* paddr = 0 to unset notify buffer */
870 a1 = 0x0000ffff00000000ULL; /* intr num = -1 to unreg for intr */
871 a1 += sizeof(struct vnic_devcmd_notify);
872
383ab92f 873 err = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
d883aa76
VK
874 vdev->notify = NULL;
875 vdev->notify_pa = 0;
27372bf5 876 vdev->notify_sz = 0;
383ab92f
VK
877
878 return err;
01f2e4ea
SF
879}
880
383ab92f 881int vnic_dev_notify_unset(struct vnic_dev *vdev)
d883aa76
VK
882{
883 if (vdev->notify) {
884 pci_free_consistent(vdev->pdev,
885 sizeof(struct vnic_devcmd_notify),
886 vdev->notify,
887 vdev->notify_pa);
888 }
889
383ab92f 890 return vnic_dev_notify_unsetcmd(vdev);
d883aa76
VK
891}
892
01f2e4ea
SF
893static int vnic_dev_notify_ready(struct vnic_dev *vdev)
894{
895 u32 *words;
27372bf5 896 unsigned int nwords = vdev->notify_sz / 4;
01f2e4ea
SF
897 unsigned int i;
898 u32 csum;
899
27372bf5 900 if (!vdev->notify || !vdev->notify_sz)
01f2e4ea
SF
901 return 0;
902
903 do {
904 csum = 0;
27372bf5 905 memcpy(&vdev->notify_copy, vdev->notify, vdev->notify_sz);
01f2e4ea
SF
906 words = (u32 *)&vdev->notify_copy;
907 for (i = 1; i < nwords; i++)
908 csum += words[i];
909 } while (csum != words[0]);
910
911 return 1;
912}
913
914int vnic_dev_init(struct vnic_dev *vdev, int arg)
915{
916 u64 a0 = (u32)arg, a1 = 0;
917 int wait = 1000;
4cdc44a2 918 int r = 0;
27372bf5 919
29046f9b 920 if (vnic_dev_capable(vdev, CMD_INIT))
27372bf5
SF
921 r = vnic_dev_cmd(vdev, CMD_INIT, &a0, &a1, wait);
922 else {
923 vnic_dev_cmd(vdev, CMD_INIT_v1, &a0, &a1, wait);
924 if (a0 & CMD_INITF_DEFAULT_MAC) {
70feadf3
VK
925 /* Emulate these for old CMD_INIT_v1 which
926 * didn't pass a0 so no CMD_INITF_*.
927 */
b13423ee 928 vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);
27372bf5
SF
929 vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);
930 }
4cdc44a2
SF
931 }
932 return r;
01f2e4ea
SF
933}
934
f8bd9091
SF
935int vnic_dev_deinit(struct vnic_dev *vdev)
936{
937 u64 a0 = 0, a1 = 0;
938 int wait = 1000;
939
940 return vnic_dev_cmd(vdev, CMD_DEINIT, &a0, &a1, wait);
941}
942
ea7ea65a
VK
943void vnic_dev_intr_coal_timer_info_default(struct vnic_dev *vdev)
944{
945 /* Default: hardware intr coal timer is in units of 1.5 usecs */
946 vdev->intr_coal_timer_info.mul = 2;
947 vdev->intr_coal_timer_info.div = 3;
948 vdev->intr_coal_timer_info.max_usec =
949 vnic_dev_intr_coal_timer_hw_to_usec(vdev, 0xffff);
950}
951
952int vnic_dev_intr_coal_timer_info(struct vnic_dev *vdev)
953{
954 int wait = 1000;
955 int err;
956
957 memset(vdev->args, 0, sizeof(vdev->args));
958
f8a6dd59 959 if (vnic_dev_capable(vdev, CMD_INTR_COAL_CONVERT))
373fb087 960 err = vdev->devcmd_rtn(vdev, CMD_INTR_COAL_CONVERT, wait);
f8a6dd59
NP
961 else
962 err = ERR_ECMDUNKNOWN;
ea7ea65a
VK
963
964 /* Use defaults when firmware doesn't support the devcmd at all or
965 * supports it for only specific hardware
966 */
967 if ((err == ERR_ECMDUNKNOWN) ||
968 (!err && !(vdev->args[0] && vdev->args[1] && vdev->args[2]))) {
e327f4e1 969 vdev_netwarn(vdev, "Using default conversion factor for interrupt coalesce timer\n");
ea7ea65a
VK
970 vnic_dev_intr_coal_timer_info_default(vdev);
971 return 0;
972 }
973
f8a6dd59
NP
974 if (!err) {
975 vdev->intr_coal_timer_info.mul = (u32) vdev->args[0];
976 vdev->intr_coal_timer_info.div = (u32) vdev->args[1];
977 vdev->intr_coal_timer_info.max_usec = (u32) vdev->args[2];
978 }
ea7ea65a
VK
979
980 return err;
981}
982
01f2e4ea
SF
983int vnic_dev_link_status(struct vnic_dev *vdev)
984{
01f2e4ea
SF
985 if (!vnic_dev_notify_ready(vdev))
986 return 0;
987
988 return vdev->notify_copy.link_state;
989}
990
991u32 vnic_dev_port_speed(struct vnic_dev *vdev)
992{
993 if (!vnic_dev_notify_ready(vdev))
994 return 0;
995
996 return vdev->notify_copy.port_speed;
997}
998
999u32 vnic_dev_msg_lvl(struct vnic_dev *vdev)
1000{
1001 if (!vnic_dev_notify_ready(vdev))
1002 return 0;
1003
1004 return vdev->notify_copy.msglvl;
1005}
1006
1007u32 vnic_dev_mtu(struct vnic_dev *vdev)
1008{
1009 if (!vnic_dev_notify_ready(vdev))
1010 return 0;
1011
1012 return vdev->notify_copy.mtu;
1013}
1014
1015void vnic_dev_set_intr_mode(struct vnic_dev *vdev,
1016 enum vnic_dev_intr_mode intr_mode)
1017{
1018 vdev->intr_mode = intr_mode;
1019}
1020
1021enum vnic_dev_intr_mode vnic_dev_get_intr_mode(
1022 struct vnic_dev *vdev)
1023{
1024 return vdev->intr_mode;
1025}
1026
ea7ea65a
VK
1027u32 vnic_dev_intr_coal_timer_usec_to_hw(struct vnic_dev *vdev, u32 usec)
1028{
1029 return (usec * vdev->intr_coal_timer_info.mul) /
1030 vdev->intr_coal_timer_info.div;
1031}
1032
1033u32 vnic_dev_intr_coal_timer_hw_to_usec(struct vnic_dev *vdev, u32 hw_cycles)
1034{
1035 return (hw_cycles * vdev->intr_coal_timer_info.div) /
1036 vdev->intr_coal_timer_info.mul;
1037}
1038
1039u32 vnic_dev_get_intr_coal_timer_max(struct vnic_dev *vdev)
1040{
1041 return vdev->intr_coal_timer_info.max_usec;
1042}
1043
01f2e4ea
SF
1044void vnic_dev_unregister(struct vnic_dev *vdev)
1045{
1046 if (vdev) {
1047 if (vdev->notify)
1048 pci_free_consistent(vdev->pdev,
1049 sizeof(struct vnic_devcmd_notify),
1050 vdev->notify,
1051 vdev->notify_pa);
01f2e4ea
SF
1052 if (vdev->stats)
1053 pci_free_consistent(vdev->pdev,
29046f9b 1054 sizeof(struct vnic_stats),
01f2e4ea
SF
1055 vdev->stats, vdev->stats_pa);
1056 if (vdev->fw_info)
1057 pci_free_consistent(vdev->pdev,
1058 sizeof(struct vnic_devcmd_fw_info),
1059 vdev->fw_info, vdev->fw_info_pa);
373fb087
GV
1060 if (vdev->devcmd2)
1061 vnic_dev_deinit_devcmd2(vdev);
1062
01f2e4ea
SF
1063 kfree(vdev);
1064 }
1065}
4a50ddfd 1066EXPORT_SYMBOL(vnic_dev_unregister);
01f2e4ea
SF
1067
1068struct vnic_dev *vnic_dev_register(struct vnic_dev *vdev,
27e6c7d3
SF
1069 void *priv, struct pci_dev *pdev, struct vnic_dev_bar *bar,
1070 unsigned int num_bars)
01f2e4ea
SF
1071{
1072 if (!vdev) {
1073 vdev = kzalloc(sizeof(struct vnic_dev), GFP_ATOMIC);
1074 if (!vdev)
1075 return NULL;
1076 }
1077
1078 vdev->priv = priv;
1079 vdev->pdev = pdev;
1080
27e6c7d3 1081 if (vnic_dev_discover_res(vdev, bar, num_bars))
01f2e4ea
SF
1082 goto err_out;
1083
01f2e4ea
SF
1084 return vdev;
1085
1086err_out:
1087 vnic_dev_unregister(vdev);
1088 return NULL;
1089}
4a50ddfd 1090EXPORT_SYMBOL(vnic_dev_register);
1091
1092struct pci_dev *vnic_dev_get_pdev(struct vnic_dev *vdev)
1093{
1094 return vdev->pdev;
1095}
1096EXPORT_SYMBOL(vnic_dev_get_pdev);
01f2e4ea 1097
373fb087
GV
1098int vnic_devcmd_init(struct vnic_dev *vdev)
1099{
f376d4ad 1100 void __iomem *res;
373fb087 1101 int err;
373fb087
GV
1102
1103 res = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);
1104 if (res) {
1105 err = vnic_dev_init_devcmd2(vdev);
1106 if (err)
e327f4e1 1107 vdev_warn(vdev, "DEVCMD2 init failed: %d, Using DEVCMD1\n",
373fb087
GV
1108 err);
1109 else
1110 return 0;
1111 } else {
e327f4e1 1112 vdev_warn(vdev, "DEVCMD2 resource not found (old firmware?) Using DEVCMD1\n");
373fb087
GV
1113 }
1114 err = vnic_dev_init_devcmd1(vdev);
1115 if (err)
e327f4e1 1116 vdev_err(vdev, "DEVCMD1 initialization failed: %d\n", err);
373fb087
GV
1117
1118 return err;
1119}
1120
9085fd09
RP
1121int vnic_dev_init_prov2(struct vnic_dev *vdev, u8 *buf, u32 len)
1122{
1123 u64 a0, a1 = len;
1124 int wait = 1000;
1125 dma_addr_t prov_pa;
1126 void *prov_buf;
1127 int ret;
1128
1129 prov_buf = pci_alloc_consistent(vdev->pdev, len, &prov_pa);
1130 if (!prov_buf)
1131 return -ENOMEM;
27372bf5 1132
9085fd09
RP
1133 memcpy(prov_buf, buf, len);
1134
1135 a0 = prov_pa;
1136
1137 ret = vnic_dev_cmd(vdev, CMD_INIT_PROV_INFO2, &a0, &a1, wait);
1138
1139 pci_free_consistent(vdev->pdev, len, prov_buf, prov_pa);
1140
1141 return ret;
1142}
1143
1144int vnic_dev_enable2(struct vnic_dev *vdev, int active)
1145{
1146 u64 a0, a1 = 0;
1147 int wait = 1000;
1148
1149 a0 = (active ? CMD_ENABLE2_ACTIVE : 0);
1150
1151 return vnic_dev_cmd(vdev, CMD_ENABLE2, &a0, &a1, wait);
1152}
1153
1154static int vnic_dev_cmd_status(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
1155 int *status)
1156{
1157 u64 a0 = cmd, a1 = 0;
1158 int wait = 1000;
1159 int ret;
1160
1161 ret = vnic_dev_cmd(vdev, CMD_STATUS, &a0, &a1, wait);
1162 if (!ret)
1163 *status = (int)a0;
1164
1165 return ret;
1166}
1167
1168int vnic_dev_enable2_done(struct vnic_dev *vdev, int *status)
1169{
1170 return vnic_dev_cmd_status(vdev, CMD_ENABLE2, status);
1171}
1172
1173int vnic_dev_deinit_done(struct vnic_dev *vdev, int *status)
1174{
1175 return vnic_dev_cmd_status(vdev, CMD_DEINIT, status);
1176}
d6c81bc6
RP
1177
1178int vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)
1179{
1180 u64 a0, a1;
1181 int wait = 1000;
1182 int i;
1183
1184 for (i = 0; i < ETH_ALEN; i++)
1185 ((u8 *)&a0)[i] = mac_addr[i];
1186
1187 return vnic_dev_cmd(vdev, CMD_SET_MAC_ADDR, &a0, &a1, wait);
1188}
63118527
GV
1189
1190/* vnic_dev_classifier: Add/Delete classifier entries
1191 * @vdev: vdev of the device
1192 * @cmd: CLSF_ADD for Add filter
1193 * CLSF_DEL for Delete filter
1194 * @entry: In case of ADD filter, the caller passes the RQ number in this
1195 * variable.
1196 *
1197 * This function stores the filter_id returned by the firmware in the
1198 * same variable before return;
1199 *
1200 * In case of DEL filter, the caller passes the RQ number. Return
1201 * value is irrelevant.
1202 * @data: filter data
1203 */
1204int vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,
1205 struct filter *data)
1206{
1207 u64 a0, a1;
1208 int wait = 1000;
1209 dma_addr_t tlv_pa;
1210 int ret = -EINVAL;
1211 struct filter_tlv *tlv, *tlv_va;
1212 struct filter_action *action;
1213 u64 tlv_size;
1214
1215 if (cmd == CLSF_ADD) {
1216 tlv_size = sizeof(struct filter) +
1217 sizeof(struct filter_action) +
1218 2 * sizeof(struct filter_tlv);
1219 tlv_va = pci_alloc_consistent(vdev->pdev, tlv_size, &tlv_pa);
1220 if (!tlv_va)
1221 return -ENOMEM;
1222 tlv = tlv_va;
1223 a0 = tlv_pa;
1224 a1 = tlv_size;
1225 memset(tlv, 0, tlv_size);
1226 tlv->type = CLSF_TLV_FILTER;
1227 tlv->length = sizeof(struct filter);
1228 *(struct filter *)&tlv->val = *data;
1229
1230 tlv = (struct filter_tlv *)((char *)tlv +
1231 sizeof(struct filter_tlv) +
1232 sizeof(struct filter));
1233
1234 tlv->type = CLSF_TLV_ACTION;
1235 tlv->length = sizeof(struct filter_action);
1236 action = (struct filter_action *)&tlv->val;
1237 action->type = FILTER_ACTION_RQ_STEERING;
1238 action->u.rq_idx = *entry;
1239
1240 ret = vnic_dev_cmd(vdev, CMD_ADD_FILTER, &a0, &a1, wait);
1241 *entry = (u16)a0;
1242 pci_free_consistent(vdev->pdev, tlv_size, tlv_va, tlv_pa);
1243 } else if (cmd == CLSF_DEL) {
1244 a0 = *entry;
1245 ret = vnic_dev_cmd(vdev, CMD_DEL_FILTER, &a0, &a1, wait);
1246 }
1247
1248 return ret;
1249}