[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / cisco / enic / vnic_rq.c

/*
 * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.
 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
 *
 * This program is free software; you may redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/slab.h>

#include "vnic_dev.h"
#include "vnic_rq.h"
#include "enic.h"

static int vnic_rq_alloc_bufs(struct vnic_rq *rq)
{
	struct vnic_rq_buf *buf;
	unsigned int i, j, count = rq->ring.desc_count;
	unsigned int blks = VNIC_RQ_BUF_BLKS_NEEDED(count);

	for (i = 0; i < blks; i++) {
		rq->bufs[i] = kzalloc(VNIC_RQ_BUF_BLK_SZ(count), GFP_ATOMIC);
		if (!rq->bufs[i])
			return -ENOMEM;
	}

	for (i = 0; i < blks; i++) {
		buf = rq->bufs[i];
		for (j = 0; j < VNIC_RQ_BUF_BLK_ENTRIES(count); j++) {
			buf->index = i * VNIC_RQ_BUF_BLK_ENTRIES(count) + j;
			buf->desc = (u8 *)rq->ring.descs +
				rq->ring.desc_size * buf->index;
			if (buf->index + 1 == count) {
				buf->next = rq->bufs[0];
				break;
			} else if (j + 1 == VNIC_RQ_BUF_BLK_ENTRIES(count)) {
				buf->next = rq->bufs[i + 1];
			} else {
				buf->next = buf + 1;
				buf++;
			}
		}
	}

	rq->to_use = rq->to_clean = rq->bufs[0];

	return 0;
}

void vnic_rq_free(struct vnic_rq *rq)
{
	struct vnic_dev *vdev;
	unsigned int i;

	vdev = rq->vdev;

	vnic_dev_free_desc_ring(vdev, &rq->ring);

	for (i = 0; i < VNIC_RQ_BUF_BLKS_MAX; i++) {
		if (rq->bufs[i]) {
			kfree(rq->bufs[i]);
			rq->bufs[i] = NULL;
		}
	}

	rq->ctrl = NULL;
}

int vnic_rq_alloc(struct vnic_dev *vdev, struct vnic_rq *rq, unsigned int index,
	unsigned int desc_count, unsigned int desc_size)
{
	int err;

	rq->index = index;
	rq->vdev = vdev;

	rq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_RQ, index);
	if (!rq->ctrl) {
		vdev_err(vdev, "Failed to hook RQ[%d] resource\n", index);
		return -EINVAL;
	}

	vnic_rq_disable(rq);

	err = vnic_dev_alloc_desc_ring(vdev, &rq->ring, desc_count, desc_size);
	if (err)
		return err;

	err = vnic_rq_alloc_bufs(rq);
	if (err) {
		vnic_rq_free(rq);
		return err;
	}

	return 0;
}

static void vnic_rq_init_start(struct vnic_rq *rq, unsigned int cq_index,
	unsigned int fetch_index, unsigned int posted_index,
	unsigned int error_interrupt_enable,
	unsigned int error_interrupt_offset)
{
	u64 paddr;
	unsigned int count = rq->ring.desc_count;

	paddr = (u64)rq->ring.base_addr | VNIC_PADDR_TARGET;
	writeq(paddr, &rq->ctrl->ring_base);
	iowrite32(count, &rq->ctrl->ring_size);
	iowrite32(cq_index, &rq->ctrl->cq_index);
	iowrite32(error_interrupt_enable, &rq->ctrl->error_interrupt_enable);
	iowrite32(error_interrupt_offset, &rq->ctrl->error_interrupt_offset);
	iowrite32(0, &rq->ctrl->dropped_packet_count);
	iowrite32(0, &rq->ctrl->error_status);
	iowrite32(fetch_index, &rq->ctrl->fetch_index);
	iowrite32(posted_index, &rq->ctrl->posted_index);

	rq->to_use = rq->to_clean =
		&rq->bufs[fetch_index / VNIC_RQ_BUF_BLK_ENTRIES(count)]
			[fetch_index % VNIC_RQ_BUF_BLK_ENTRIES(count)];
}

void vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,
	unsigned int error_interrupt_enable,
	unsigned int error_interrupt_offset)
{
	u32 fetch_index = 0;

	/* Use current fetch_index as the ring starting point */
	fetch_index = ioread32(&rq->ctrl->fetch_index);

	if (fetch_index == 0xFFFFFFFF) { /* check for hardware gone  */
		/* Hardware surprise removal: reset fetch_index */
		fetch_index = 0;
	}

	vnic_rq_init_start(rq, cq_index,
		fetch_index, fetch_index,
		error_interrupt_enable,
		error_interrupt_offset);
}

unsigned int vnic_rq_error_status(struct vnic_rq *rq)
{
	return ioread32(&rq->ctrl->error_status);
}

void vnic_rq_enable(struct vnic_rq *rq)
{
	iowrite32(1, &rq->ctrl->enable);
}

int vnic_rq_disable(struct vnic_rq *rq)
{
	unsigned int wait;
	struct vnic_dev *vdev = rq->vdev;
	int i;

	/* Due to a race condition with clearing RQ "mini-cache" in hw, we need
	 * to disable the RQ twice to guarantee that stale descriptors are not
	 * used when this RQ is re-enabled.
	 */
	for (i = 0; i < 2; i++) {
		iowrite32(0, &rq->ctrl->enable);

		/* Wait for HW to ACK disable request */
		for (wait = 20000; wait > 0; wait--)
			if (!ioread32(&rq->ctrl->running))
				break;
		if (!wait) {
			vdev_neterr(vdev, "Failed to disable RQ[%d]\n",
				    rq->index);

			return -ETIMEDOUT;
		}
	}

	return 0;
}

void vnic_rq_clean(struct vnic_rq *rq,
	void (*buf_clean)(struct vnic_rq *rq, struct vnic_rq_buf *buf))
{
	struct vnic_rq_buf *buf;
	u32 fetch_index;
	unsigned int count = rq->ring.desc_count;
	int i;

	buf = rq->to_clean;

	for (i = 0; i < rq->ring.desc_count; i++) {
		(*buf_clean)(rq, buf);
		buf = buf->next;
	}
	rq->ring.desc_avail = rq->ring.desc_count - 1;

	/* Use current fetch_index as the ring starting point */
	fetch_index = ioread32(&rq->ctrl->fetch_index);

	if (fetch_index == 0xFFFFFFFF) { /* check for hardware gone  */
		/* Hardware surprise removal: reset fetch_index */
		fetch_index = 0;
	}
	rq->to_use = rq->to_clean =
		&rq->bufs[fetch_index / VNIC_RQ_BUF_BLK_ENTRIES(count)]
			[fetch_index % VNIC_RQ_BUF_BLK_ENTRIES(count)];
	iowrite32(fetch_index, &rq->ctrl->posted_index);

	/* Anytime we write fetch_index, we need to re-write 0 to rq->enable
	 * to re-sync internal VIC state.
	 */
	iowrite32(0, &rq->ctrl->enable);

	vnic_dev_clear_desc_ring(&rq->ring);
}
Commit	Line	Data
01f2e4ea	1	/*
29046f9b	2	* Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
01f2e4ea SF	3	* Copyright 2007 Nuova Systems, Inc. All rights reserved.
	4	*
	5	* This program is free software; you may redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	10	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	11	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	12	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	13	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	14	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	15	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	16	* SOFTWARE.
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/errno.h>
	22	#include <linux/types.h>
	23	#include <linux/pci.h>
	24	#include <linux/delay.h>
5a0e3ad6	25	#include <linux/slab.h>
01f2e4ea SF	26
	27	#include "vnic_dev.h"
	28	#include "vnic_rq.h"
6a3c2f83	29	#include "enic.h"
01f2e4ea SF	30
	31	static int vnic_rq_alloc_bufs(struct vnic_rq *rq)
	32	{
	33	struct vnic_rq_buf *buf;
01f2e4ea SF	34	unsigned int i, j, count = rq->ring.desc_count;
	35	unsigned int blks = VNIC_RQ_BUF_BLKS_NEEDED(count);
	36
01f2e4ea	37	for (i = 0; i < blks; i++) {
b5bab85c	38	rq->bufs[i] = kzalloc(VNIC_RQ_BUF_BLK_SZ(count), GFP_ATOMIC);
e404decb	39	if (!rq->bufs[i])
01f2e4ea	40	return -ENOMEM;
01f2e4ea SF	41	}
	42
	43	for (i = 0; i < blks; i++) {
	44	buf = rq->bufs[i];
b5bab85c VK	45	for (j = 0; j < VNIC_RQ_BUF_BLK_ENTRIES(count); j++) {
b5bab85c VK	46	buf->index = i * VNIC_RQ_BUF_BLK_ENTRIES(count) + j;
01f2e4ea SF	47	buf->desc = (u8 *)rq->ring.descs +
	48	rq->ring.desc_size * buf->index;
	49	if (buf->index + 1 == count) {
	50	buf->next = rq->bufs[0];
	51	break;
b5bab85c	52	} else if (j + 1 == VNIC_RQ_BUF_BLK_ENTRIES(count)) {
01f2e4ea SF	53	buf->next = rq->bufs[i + 1];
	54	} else {
	55	buf->next = buf + 1;
	56	buf++;
	57	}
	58	}
	59	}
	60
	61	rq->to_use = rq->to_clean = rq->bufs[0];
01f2e4ea SF	62
	63	return 0;
	64	}
	65
	66	void vnic_rq_free(struct vnic_rq *rq)
	67	{
	68	struct vnic_dev *vdev;
	69	unsigned int i;
	70
	71	vdev = rq->vdev;
	72
	73	vnic_dev_free_desc_ring(vdev, &rq->ring);
	74
	75	for (i = 0; i < VNIC_RQ_BUF_BLKS_MAX; i++) {
83217790 RP	76	if (rq->bufs[i]) {
	77	kfree(rq->bufs[i]);
	78	rq->bufs[i] = NULL;
	79	}
01f2e4ea SF	80	}
	81
	82	rq->ctrl = NULL;
	83	}
	84
	85	int vnic_rq_alloc(struct vnic_dev vdev, struct vnic_rq rq, unsigned int index,
	86	unsigned int desc_count, unsigned int desc_size)
	87	{
	88	int err;
	89
	90	rq->index = index;
	91	rq->vdev = vdev;
	92
	93	rq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_RQ, index);
	94	if (!rq->ctrl) {
e327f4e1	95	vdev_err(vdev, "Failed to hook RQ[%d] resource\n", index);
01f2e4ea SF	96	return -EINVAL;
	97	}
	98
	99	vnic_rq_disable(rq);
	100
	101	err = vnic_dev_alloc_desc_ring(vdev, &rq->ring, desc_count, desc_size);
	102	if (err)
	103	return err;
	104
	105	err = vnic_rq_alloc_bufs(rq);
	106	if (err) {
	107	vnic_rq_free(rq);
	108	return err;
	109	}
	110
	111	return 0;
	112	}
	113
2fdba388	114	static void vnic_rq_init_start(struct vnic_rq *rq, unsigned int cq_index,
6fdfa970	115	unsigned int fetch_index, unsigned int posted_index,
01f2e4ea SF	116	unsigned int error_interrupt_enable,
	117	unsigned int error_interrupt_offset)
	118	{
	119	u64 paddr;
b5bab85c	120	unsigned int count = rq->ring.desc_count;
01f2e4ea SF	121
	122	paddr = (u64)rq->ring.base_addr \| VNIC_PADDR_TARGET;
	123	writeq(paddr, &rq->ctrl->ring_base);
b5bab85c	124	iowrite32(count, &rq->ctrl->ring_size);
01f2e4ea SF	125	iowrite32(cq_index, &rq->ctrl->cq_index);
	126	iowrite32(error_interrupt_enable, &rq->ctrl->error_interrupt_enable);
	127	iowrite32(error_interrupt_offset, &rq->ctrl->error_interrupt_offset);
	128	iowrite32(0, &rq->ctrl->dropped_packet_count);
	129	iowrite32(0, &rq->ctrl->error_status);
6fdfa970 SF	130	iowrite32(fetch_index, &rq->ctrl->fetch_index);
6fdfa970 SF	131	iowrite32(posted_index, &rq->ctrl->posted_index);
01f2e4ea	132
01f2e4ea	133	rq->to_use = rq->to_clean =
b5bab85c VK	134	&rq->bufs[fetch_index / VNIC_RQ_BUF_BLK_ENTRIES(count)]
b5bab85c VK	135	[fetch_index % VNIC_RQ_BUF_BLK_ENTRIES(count)];
6fdfa970 SF	136	}
	137
	138	void vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,
	139	unsigned int error_interrupt_enable,
	140	unsigned int error_interrupt_offset)
	141	{
92e2b469	142	u32 fetch_index = 0;
01f2e4ea	143
6fdfa970 SF	144	/* Use current fetch_index as the ring starting point */
	145	fetch_index = ioread32(&rq->ctrl->fetch_index);
	146
506e1198 VK	147	if (fetch_index == 0xFFFFFFFF) { /* check for hardware gone */
	148	/* Hardware surprise removal: reset fetch_index */
	149	fetch_index = 0;
	150	}
	151
6fdfa970 SF	152	vnic_rq_init_start(rq, cq_index,
	153	fetch_index, fetch_index,
	154	error_interrupt_enable,
	155	error_interrupt_offset);
01f2e4ea SF	156	}
	157
	158	unsigned int vnic_rq_error_status(struct vnic_rq *rq)
	159	{
	160	return ioread32(&rq->ctrl->error_status);
	161	}
	162
	163	void vnic_rq_enable(struct vnic_rq *rq)
	164	{
	165	iowrite32(1, &rq->ctrl->enable);
	166	}
	167
	168	int vnic_rq_disable(struct vnic_rq *rq)
	169	{
	170	unsigned int wait;
6a3c2f83	171	struct vnic_dev *vdev = rq->vdev;
9fe1c98a	172	int i;
01f2e4ea	173
9fe1c98a GV	174	/* Due to a race condition with clearing RQ "mini-cache" in hw, we need
	175	* to disable the RQ twice to guarantee that stale descriptors are not
	176	* used when this RQ is re-enabled.
	177	*/
	178	for (i = 0; i < 2; i++) {
	179	iowrite32(0, &rq->ctrl->enable);
01f2e4ea	180
9fe1c98a GV	181	/* Wait for HW to ACK disable request */
	182	for (wait = 20000; wait > 0; wait--)
	183	if (!ioread32(&rq->ctrl->running))
	184	break;
	185	if (!wait) {
	186	vdev_neterr(vdev, "Failed to disable RQ[%d]\n",
	187	rq->index);
01f2e4ea	188
9fe1c98a GV	189	return -ETIMEDOUT;
	190	}
	191	}
01f2e4ea	192
9fe1c98a	193	return 0;
01f2e4ea SF	194	}
	195
	196	void vnic_rq_clean(struct vnic_rq *rq,
	197	void (buf_clean)(struct vnic_rq rq, struct vnic_rq_buf *buf))
	198	{
	199	struct vnic_rq_buf *buf;
	200	u32 fetch_index;
b5bab85c	201	unsigned int count = rq->ring.desc_count;
8b13b4e0	202	int i;
01f2e4ea	203
01f2e4ea SF	204	buf = rq->to_clean;
01f2e4ea SF	205
8b13b4e0	206	for (i = 0; i < rq->ring.desc_count; i++) {
01f2e4ea	207	(*buf_clean)(rq, buf);
8b13b4e0	208	buf = buf->next;
01f2e4ea	209	}
8b13b4e0	210	rq->ring.desc_avail = rq->ring.desc_count - 1;
01f2e4ea SF	211
	212	/* Use current fetch_index as the ring starting point */
	213	fetch_index = ioread32(&rq->ctrl->fetch_index);
506e1198 VK	214
	215	if (fetch_index == 0xFFFFFFFF) { /* check for hardware gone */
	216	/* Hardware surprise removal: reset fetch_index */
	217	fetch_index = 0;
	218	}
01f2e4ea	219	rq->to_use = rq->to_clean =
b5bab85c VK	220	&rq->bufs[fetch_index / VNIC_RQ_BUF_BLK_ENTRIES(count)]
b5bab85c VK	221	[fetch_index % VNIC_RQ_BUF_BLK_ENTRIES(count)];
01f2e4ea SF	222	iowrite32(fetch_index, &rq->ctrl->posted_index);
01f2e4ea SF	223
9fe1c98a GV	224	/* Anytime we write fetch_index, we need to re-write 0 to rq->enable
	225	* to re-sync internal VIC state.
	226	*/
	227	iowrite32(0, &rq->ctrl->enable);
	228
01f2e4ea SF	229	vnic_dev_clear_desc_ring(&rq->ring);
	230	}
	231