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net: introduce IFF_UNICAST_FLT private flag
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / dec / tulip / uli526x.c
CommitLineData
4689ced9
PC		 1/*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
f3b197ac 12
4689ced9
PC		 13*/
14
e02fb7aa
JP		 15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
4689ced9
PC		 17#define DRV_NAME "uli526x"
18#define DRV_VERSION "0.9.3"
19#define DRV_RELDATE "2005-7-29"
20
21#include <linux/module.h>
22
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/timer.h>
4689ced9
PC		 26#include <linux/errno.h>
27#include <linux/ioport.h>
4689ced9
PC		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/skbuff.h>
35#include <linux/delay.h>
36#include <linux/spinlock.h>
6cafa99f 37#include <linux/dma-mapping.h>
1977f032 38#include <linux/bitops.h>
4689ced9
PC		 39
40#include <asm/processor.h>
4689ced9
PC		 41#include <asm/io.h>
42#include <asm/dma.h>
43#include <asm/uaccess.h>
44
45
46/* Board/System/Debug information/definition ---------------- */
47#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
48#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
49
50#define ULI526X_IO_SIZE 0x100
51#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
52#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
53#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
54#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
55#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
56#define TX_BUF_ALLOC 0x600
57#define RX_ALLOC_SIZE 0x620
58#define ULI526X_RESET 1
59#define CR0_DEFAULT 0
945a7876 60#define CR6_DEFAULT 0x22200000
4689ced9
PC		 61#define CR7_DEFAULT 0x180c1
62#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
63#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
64#define MAX_PACKET_SIZE 1514
65#define ULI5261_MAX_MULTICAST 14
66#define RX_COPY_SIZE 100
67#define MAX_CHECK_PACKET 0x8000
68
69#define ULI526X_10MHF 0
70#define ULI526X_100MHF 1
71#define ULI526X_10MFD 4
72#define ULI526X_100MFD 5
73#define ULI526X_AUTO 8
74
75#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
76#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
77#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
78#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
79#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
80#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
81
82#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
83#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
84#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
85
e02fb7aa
JP		 86#define ULI526X_DBUG(dbug_now, msg, value) \
87do { \
88 if (uli526x_debug || (dbug_now)) \
89 pr_err("%s %lx\n", (msg), (long) (value)); \
90} while (0)
4689ced9 91
e02fb7aa
JP		 92#define SHOW_MEDIA_TYPE(mode) \
93 pr_err("Change Speed to %sMhz %s duplex\n", \
94 mode & 1 ? "100" : "10", \
95 mode & 4 ? "full" : "half");
4689ced9
PC		 96
97
98/* CR9 definition: SROM/MII */
99#define CR9_SROM_READ 0x4800
100#define CR9_SRCS 0x1
101#define CR9_SRCLK 0x2
102#define CR9_CRDOUT 0x8
103#define SROM_DATA_0 0x0
104#define SROM_DATA_1 0x4
105#define PHY_DATA_1 0x20000
106#define PHY_DATA_0 0x00000
107#define MDCLKH 0x10000
108
109#define PHY_POWER_DOWN 0x800
110
111#define SROM_V41_CODE 0x14
112
945a7876
PC		 113#define SROM_CLK_WRITE(data, ioaddr) \
114 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
115 udelay(5); \
116 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
117 udelay(5); \
118 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
119 udelay(5);
4689ced9
PC		 120
121/* Structure/enum declaration ------------------------------- */
122struct tx_desc {
c559a5bc 123 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
4689ced9
PC		 124 char *tx_buf_ptr; /* Data for us */
125 struct tx_desc *next_tx_desc;
126} __attribute__(( aligned(32) ));
127
128struct rx_desc {
c559a5bc 129 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
4689ced9
PC		 130 struct sk_buff *rx_skb_ptr; /* Data for us */
131 struct rx_desc *next_rx_desc;
132} __attribute__(( aligned(32) ));
133
134struct uli526x_board_info {
135 u32 chip_id; /* Chip vendor/Device ID */
945a7876 136 struct net_device *next_dev; /* next device */
4689ced9
PC		 137 struct pci_dev *pdev; /* PCI device */
138 spinlock_t lock;
139
140 long ioaddr; /* I/O base address */
141 u32 cr0_data;
142 u32 cr5_data;
143 u32 cr6_data;
144 u32 cr7_data;
145 u32 cr15_data;
146
147 /* pointer for memory physical address */
148 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
149 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
150 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
151 dma_addr_t first_tx_desc_dma;
152 dma_addr_t first_rx_desc_dma;
153
154 /* descriptor pointer */
155 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
156 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
157 unsigned char *desc_pool_ptr; /* descriptor pool memory */
158 struct tx_desc *first_tx_desc;
159 struct tx_desc *tx_insert_ptr;
160 struct tx_desc *tx_remove_ptr;
161 struct rx_desc *first_rx_desc;
162 struct rx_desc *rx_insert_ptr;
163 struct rx_desc *rx_ready_ptr; /* packet come pointer */
164 unsigned long tx_packet_cnt; /* transmitted packet count */
165 unsigned long rx_avail_cnt; /* available rx descriptor count */
166 unsigned long interval_rx_cnt; /* rx packet count a callback time */
167
168 u16 dbug_cnt;
169 u16 NIC_capability; /* NIC media capability */
170 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
171
172 u8 media_mode; /* user specify media mode */
173 u8 op_mode; /* real work media mode */
174 u8 phy_addr;
175 u8 link_failed; /* Ever link failed */
176 u8 wait_reset; /* Hardware failed, need to reset */
177 struct timer_list timer;
178
4689ced9
PC		 179 /* Driver defined statistic counter */
180 unsigned long tx_fifo_underrun;
181 unsigned long tx_loss_carrier;
182 unsigned long tx_no_carrier;
183 unsigned long tx_late_collision;
184 unsigned long tx_excessive_collision;
185 unsigned long tx_jabber_timeout;
186 unsigned long reset_count;
187 unsigned long reset_cr8;
188 unsigned long reset_fatal;
189 unsigned long reset_TXtimeout;
190
191 /* NIC SROM data */
192 unsigned char srom[128];
f3b197ac 193 u8 init;
4689ced9
PC		 194};
195
196enum uli526x_offsets {
197 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
198 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
199 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
200 DCR15 = 0x78
201};
202
203enum uli526x_CR6_bits {
204 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
205 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
206 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
207};
208
209/* Global variable declaration ----------------------------- */
210static int __devinitdata printed_version;
03f54b3d 211static const char version[] __devinitconst =
1c3319fb 212 "ULi M5261/M5263 net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
4689ced9
PC		 213
214static int uli526x_debug;
215static unsigned char uli526x_media_mode = ULI526X_AUTO;
216static u32 uli526x_cr6_user_set;
217
218/* For module input parameter */
219static int debug;
220static u32 cr6set;
99bb2579 221static int mode = 8;
4689ced9
PC		 222
223/* function declaration ------------------------------------- */
945a7876 224static int uli526x_open(struct net_device *);
ad096463
SH		 225static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
226 struct net_device *);
945a7876 227static int uli526x_stop(struct net_device *);
945a7876 228static void uli526x_set_filter_mode(struct net_device *);
7282d491 229static const struct ethtool_ops netdev_ethtool_ops;
945a7876 230static u16 read_srom_word(long, int);
7d12e780 231static irqreturn_t uli526x_interrupt(int, void *);
7fa0cba3
AV		 232#ifdef CONFIG_NET_POLL_CONTROLLER
233static void uli526x_poll(struct net_device *dev);
234#endif
4689ced9
PC		 235static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
236static void allocate_rx_buffer(struct uli526x_board_info *);
237static void update_cr6(u32, unsigned long);
945a7876 238static void send_filter_frame(struct net_device *, int);
4689ced9
PC		 239static u16 phy_read(unsigned long, u8, u8, u32);
240static u16 phy_readby_cr10(unsigned long, u8, u8);
241static void phy_write(unsigned long, u8, u8, u16, u32);
242static void phy_writeby_cr10(unsigned long, u8, u8, u16);
243static void phy_write_1bit(unsigned long, u32, u32);
244static u16 phy_read_1bit(unsigned long, u32);
245static u8 uli526x_sense_speed(struct uli526x_board_info *);
246static void uli526x_process_mode(struct uli526x_board_info *);
247static void uli526x_timer(unsigned long);
945a7876
PC		 248static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
249static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
4689ced9 250static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
945a7876 251static void uli526x_dynamic_reset(struct net_device *);
4689ced9 252static void uli526x_free_rxbuffer(struct uli526x_board_info *);
945a7876 253static void uli526x_init(struct net_device *);
4689ced9
PC		 254static void uli526x_set_phyxcer(struct uli526x_board_info *);
255
945a7876 256/* ULI526X network board routine ---------------------------- */
4689ced9 257
dfefe02b
SH		 258static const struct net_device_ops netdev_ops = {
259 .ndo_open = uli526x_open,
260 .ndo_stop = uli526x_stop,
261 .ndo_start_xmit = uli526x_start_xmit,
262 .ndo_set_multicast_list = uli526x_set_filter_mode,
263 .ndo_change_mtu = eth_change_mtu,
264 .ndo_set_mac_address = eth_mac_addr,
265 .ndo_validate_addr = eth_validate_addr,
266#ifdef CONFIG_NET_POLL_CONTROLLER
267 .ndo_poll_controller = uli526x_poll,
268#endif
269};
270
4689ced9 271/*
945a7876 272 * Search ULI526X board, allocate space and register it
4689ced9
PC		 273 */
274
275static int __devinit uli526x_init_one (struct pci_dev *pdev,
276 const struct pci_device_id *ent)
277{
278 struct uli526x_board_info *db; /* board information structure */
279 struct net_device *dev;
280 int i, err;
f3b197ac 281
4689ced9
PC		 282 ULI526X_DBUG(0, "uli526x_init_one()", 0);
283
284 if (!printed_version++)
1c3319fb 285 pr_info("%s\n", version);
4689ced9
PC		 286
287 /* Init network device */
288 dev = alloc_etherdev(sizeof(*db));
289 if (dev == NULL)
290 return -ENOMEM;
4689ced9
PC		 291 SET_NETDEV_DEV(dev, &pdev->dev);
292
284901a9 293 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
163ef0b5 294 pr_warn("32-bit PCI DMA not available\n");
4689ced9
PC		 295 err = -ENODEV;
296 goto err_out_free;
297 }
298
299 /* Enable Master/IO access, Disable memory access */
300 err = pci_enable_device(pdev);
301 if (err)
302 goto err_out_free;
303
304 if (!pci_resource_start(pdev, 0)) {
e02fb7aa 305 pr_err("I/O base is zero\n");
4689ced9
PC		 306 err = -ENODEV;
307 goto err_out_disable;
308 }
309
310 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
e02fb7aa 311 pr_err("Allocated I/O size too small\n");
4689ced9
PC		 312 err = -ENODEV;
313 goto err_out_disable;
314 }
315
316 if (pci_request_regions(pdev, DRV_NAME)) {
e02fb7aa 317 pr_err("Failed to request PCI regions\n");
4689ced9
PC		 318 err = -ENODEV;
319 goto err_out_disable;
320 }
321
4689ced9
PC		 322 /* Init system & device */
323 db = netdev_priv(dev);
324
325 /* Allocate Tx/Rx descriptor memory */
326 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
945a7876
PC		 327 if(db->desc_pool_ptr == NULL)
328 {
329 err = -ENOMEM;
330 goto err_out_nomem;
331 }
4689ced9 332 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
945a7876
PC		 333 if(db->buf_pool_ptr == NULL)
334 {
335 err = -ENOMEM;
336 goto err_out_nomem;
337 }
f3b197ac 338
4689ced9
PC		 339 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
340 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
341 db->buf_pool_start = db->buf_pool_ptr;
342 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
343
344 db->chip_id = ent->driver_data;
345 db->ioaddr = pci_resource_start(pdev, 0);
f3b197ac 346
4689ced9
PC		 347 db->pdev = pdev;
348 db->init = 1;
f3b197ac 349
4689ced9
PC		 350 dev->base_addr = db->ioaddr;
351 dev->irq = pdev->irq;
352 pci_set_drvdata(pdev, dev);
f3b197ac 353
4689ced9 354 /* Register some necessary functions */
dfefe02b 355 dev->netdev_ops = &netdev_ops;
4689ced9 356 dev->ethtool_ops = &netdev_ethtool_ops;
dfefe02b 357
4689ced9
PC		 358 spin_lock_init(&db->lock);
359
f3b197ac 360
4689ced9
PC		 361 /* read 64 word srom data */
362 for (i = 0; i < 64; i++)
c559a5bc 363 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
4689ced9
PC		 364
365 /* Set Node address */
945a7876 366 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
4689ced9
PC		 367 {
368 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
369 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
370 outl(0, db->ioaddr + DCR14); //Clear reset port
371 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
372 outl(0, db->ioaddr + DCR14); //Clear reset port
373 outl(0, db->ioaddr + DCR13); //Clear CR13
374 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
375 //Read MAC address from CR14
376 for (i = 0; i < 6; i++)
377 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
378 //Read end
379 outl(0, db->ioaddr + DCR13); //Clear CR13
380 outl(0, db->ioaddr + DCR0); //Clear CR0
381 udelay(10);
382 }
383 else /*Exist SROM*/
384 {
385 for (i = 0; i < 6; i++)
386 dev->dev_addr[i] = db->srom[20 + i];
387 }
388 err = register_netdev (dev);
389 if (err)
390 goto err_out_res;
391
163ef0b5
JP		 392 netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
393 ent->driver_data >> 16, pci_name(pdev),
394 dev->dev_addr, dev->irq);
4689ced9
PC		 395
396 pci_set_master(pdev);
397
398 return 0;
399
400err_out_res:
401 pci_release_regions(pdev);
945a7876
PC		 402err_out_nomem:
403 if(db->desc_pool_ptr)
404 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
405 db->desc_pool_ptr, db->desc_pool_dma_ptr);
f3b197ac 406
945a7876
PC		 407 if(db->buf_pool_ptr != NULL)
408 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
409 db->buf_pool_ptr, db->buf_pool_dma_ptr);
4689ced9
PC		 410err_out_disable:
411 pci_disable_device(pdev);
412err_out_free:
413 pci_set_drvdata(pdev, NULL);
414 free_netdev(dev);
415
416 return err;
417}
418
419
420static void __devexit uli526x_remove_one (struct pci_dev *pdev)
421{
422 struct net_device *dev = pci_get_drvdata(pdev);
423 struct uli526x_board_info *db = netdev_priv(dev);
424
425 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
426
945a7876
PC		 427 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
428 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
429 db->desc_pool_dma_ptr);
430 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
431 db->buf_pool_ptr, db->buf_pool_dma_ptr);
432 unregister_netdev(dev);
433 pci_release_regions(pdev);
434 free_netdev(dev); /* free board information */
435 pci_set_drvdata(pdev, NULL);
436 pci_disable_device(pdev);
4689ced9
PC		 437 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
438}
439
440
441/*
442 * Open the interface.
945a7876 443 * The interface is opened whenever "ifconfig" activates it.
4689ced9
PC		 444 */
445
945a7876 446static int uli526x_open(struct net_device *dev)
4689ced9
PC		 447{
448 int ret;
449 struct uli526x_board_info *db = netdev_priv(dev);
f3b197ac 450
4689ced9
PC		 451 ULI526X_DBUG(0, "uli526x_open", 0);
452
4689ced9
PC		 453 /* system variable init */
454 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
4689ced9
PC		 455 db->tx_packet_cnt = 0;
456 db->rx_avail_cnt = 0;
457 db->link_failed = 1;
458 netif_carrier_off(dev);
459 db->wait_reset = 0;
460
461 db->NIC_capability = 0xf; /* All capability*/
462 db->PHY_reg4 = 0x1e0;
463
464 /* CR6 operation mode decision */
465 db->cr6_data |= ULI526X_TXTH_256;
466 db->cr0_data = CR0_DEFAULT;
f3b197ac 467
945a7876 468 /* Initialize ULI526X board */
4689ced9
PC		 469 uli526x_init(dev);
470
a0607fd3 471 ret = request_irq(dev->irq, uli526x_interrupt, IRQF_SHARED, dev->name, dev);
afd8e399
AV		 472 if (ret)
473 return ret;
474
4689ced9
PC		 475 /* Active System Interface */
476 netif_wake_queue(dev);
477
478 /* set and active a timer process */
479 init_timer(&db->timer);
480 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
481 db->timer.data = (unsigned long)dev;
c061b18d 482 db->timer.function = uli526x_timer;
4689ced9
PC		 483 add_timer(&db->timer);
484
485 return 0;
486}
487
488
945a7876 489/* Initialize ULI526X board
4689ced9 490 * Reset ULI526X board
945a7876 491 * Initialize TX/Rx descriptor chain structure
4689ced9
PC		 492 * Send the set-up frame
493 * Enable Tx/Rx machine
494 */
495
945a7876 496static void uli526x_init(struct net_device *dev)
4689ced9
PC		 497{
498 struct uli526x_board_info *db = netdev_priv(dev);
499 unsigned long ioaddr = db->ioaddr;
500 u8 phy_tmp;
7a7d23da 501 u8 timeout;
4689ced9
PC		 502 u16 phy_value;
503 u16 phy_reg_reset;
504
7a7d23da 505
4689ced9
PC		 506 ULI526X_DBUG(0, "uli526x_init()", 0);
507
508 /* Reset M526x MAC controller */
509 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
510 udelay(100);
511 outl(db->cr0_data, ioaddr + DCR0);
512 udelay(5);
513
514 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
515 db->phy_addr = 1;
516 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
517 {
518 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
519 if(phy_value != 0xffff&&phy_value!=0)
520 {
521 db->phy_addr = phy_tmp;
522 break;
523 }
524 }
525 if(phy_tmp == 32)
163ef0b5 526 pr_warn("Can not find the phy address!!!\n");
4689ced9
PC		 527 /* Parser SROM and media mode */
528 db->media_mode = uli526x_media_mode;
529
7a7d23da 530 /* phyxcer capability setting */
4689ced9
PC		 531 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
532 phy_reg_reset = (phy_reg_reset | 0x8000);
533 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
7a7d23da
GG		 534
535 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
536 * functions") or phy data sheet for details on phy reset
537 */
4689ced9 538 udelay(500);
7a7d23da
GG		 539 timeout = 10;
540 while (timeout-- &&
541 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
542 udelay(100);
4689ced9
PC		 543
544 /* Process Phyxcer Media Mode */
545 uli526x_set_phyxcer(db);
546
547 /* Media Mode Process */
548 if ( !(db->media_mode & ULI526X_AUTO) )
549 db->op_mode = db->media_mode; /* Force Mode */
550
945a7876 551 /* Initialize Transmit/Receive decriptor and CR3/4 */
4689ced9
PC		 552 uli526x_descriptor_init(db, ioaddr);
553
554 /* Init CR6 to program M526X operation */
555 update_cr6(db->cr6_data, ioaddr);
556
557 /* Send setup frame */
4cd24eaf 558 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
4689ced9
PC		 559
560 /* Init CR7, interrupt active bit */
561 db->cr7_data = CR7_DEFAULT;
562 outl(db->cr7_data, ioaddr + DCR7);
563
564 /* Init CR15, Tx jabber and Rx watchdog timer */
565 outl(db->cr15_data, ioaddr + DCR15);
566
567 /* Enable ULI526X Tx/Rx function */
568 db->cr6_data |= CR6_RXSC | CR6_TXSC;
569 update_cr6(db->cr6_data, ioaddr);
570}
571
572
573/*
574 * Hardware start transmission.
575 * Send a packet to media from the upper layer.
576 */
577
ad096463
SH		 578static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
579 struct net_device *dev)
4689ced9
PC		 580{
581 struct uli526x_board_info *db = netdev_priv(dev);
582 struct tx_desc *txptr;
583 unsigned long flags;
584
585 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
586
587 /* Resource flag check */
588 netif_stop_queue(dev);
589
590 /* Too large packet check */
591 if (skb->len > MAX_PACKET_SIZE) {
163ef0b5 592 netdev_err(dev, "big packet = %d\n", (u16)skb->len);
4689ced9 593 dev_kfree_skb(skb);
6ed10654 594 return NETDEV_TX_OK;
4689ced9
PC		 595 }
596
597 spin_lock_irqsave(&db->lock, flags);
598
599 /* No Tx resource check, it never happen nromally */
600 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
601 spin_unlock_irqrestore(&db->lock, flags);
163ef0b5 602 netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
5b548140 603 return NETDEV_TX_BUSY;
4689ced9
PC		 604 }
605
606 /* Disable NIC interrupt */
607 outl(0, dev->base_addr + DCR7);
608
609 /* transmit this packet */
610 txptr = db->tx_insert_ptr;
d626f62b 611 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
4689ced9
PC		 612 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
613
614 /* Point to next transmit free descriptor */
615 db->tx_insert_ptr = txptr->next_tx_desc;
616
617 /* Transmit Packet Process */
618 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
619 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
620 db->tx_packet_cnt++; /* Ready to send */
621 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
622 dev->trans_start = jiffies; /* saved time stamp */
623 }
624
625 /* Tx resource check */
626 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
627 netif_wake_queue(dev);
628
629 /* Restore CR7 to enable interrupt */
630 spin_unlock_irqrestore(&db->lock, flags);
631 outl(db->cr7_data, dev->base_addr + DCR7);
f3b197ac 632
4689ced9
PC		 633 /* free this SKB */
634 dev_kfree_skb(skb);
635
6ed10654 636 return NETDEV_TX_OK;
4689ced9
PC		 637}
638
639
640/*
641 * Stop the interface.
642 * The interface is stopped when it is brought.
643 */
644
945a7876 645static int uli526x_stop(struct net_device *dev)
4689ced9
PC		 646{
647 struct uli526x_board_info *db = netdev_priv(dev);
648 unsigned long ioaddr = dev->base_addr;
649
650 ULI526X_DBUG(0, "uli526x_stop", 0);
651
652 /* disable system */
653 netif_stop_queue(dev);
654
655 /* deleted timer */
656 del_timer_sync(&db->timer);
657
658 /* Reset & stop ULI526X board */
659 outl(ULI526X_RESET, ioaddr + DCR0);
660 udelay(5);
661 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
662
663 /* free interrupt */
664 free_irq(dev->irq, dev);
665
666 /* free allocated rx buffer */
667 uli526x_free_rxbuffer(db);
668
4689ced9
PC		 669 return 0;
670}
671
672
673/*
674 * M5261/M5263 insterrupt handler
675 * receive the packet to upper layer, free the transmitted packet
676 */
677
7d12e780 678static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
4689ced9 679{
945a7876 680 struct net_device *dev = dev_id;
4689ced9
PC		 681 struct uli526x_board_info *db = netdev_priv(dev);
682 unsigned long ioaddr = dev->base_addr;
683 unsigned long flags;
684
4689ced9
PC		 685 spin_lock_irqsave(&db->lock, flags);
686 outl(0, ioaddr + DCR7);
687
688 /* Got ULI526X status */
689 db->cr5_data = inl(ioaddr + DCR5);
690 outl(db->cr5_data, ioaddr + DCR5);
691 if ( !(db->cr5_data & 0x180c1) ) {
7fa0cba3 692 /* Restore CR7 to enable interrupt mask */
4689ced9 693 outl(db->cr7_data, ioaddr + DCR7);
7fa0cba3 694 spin_unlock_irqrestore(&db->lock, flags);
4689ced9
PC		 695 return IRQ_HANDLED;
696 }
697
4689ced9
PC		 698 /* Check system status */
699 if (db->cr5_data & 0x2000) {
700 /* system bus error happen */
701 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
702 db->reset_fatal++;
703 db->wait_reset = 1; /* Need to RESET */
704 spin_unlock_irqrestore(&db->lock, flags);
705 return IRQ_HANDLED;
706 }
707
708 /* Received the coming packet */
709 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
710 uli526x_rx_packet(dev, db);
711
712 /* reallocate rx descriptor buffer */
713 if (db->rx_avail_cnt<RX_DESC_CNT)
714 allocate_rx_buffer(db);
715
716 /* Free the transmitted descriptor */
717 if ( db->cr5_data & 0x01)
718 uli526x_free_tx_pkt(dev, db);
719
720 /* Restore CR7 to enable interrupt mask */
721 outl(db->cr7_data, ioaddr + DCR7);
722
723 spin_unlock_irqrestore(&db->lock, flags);
724 return IRQ_HANDLED;
725}
726
7fa0cba3
AV		 727#ifdef CONFIG_NET_POLL_CONTROLLER
728static void uli526x_poll(struct net_device *dev)
729{
730 /* ISR grabs the irqsave lock, so this should be safe */
731 uli526x_interrupt(dev->irq, dev);
732}
733#endif
4689ced9
PC		 734
735/*
736 * Free TX resource after TX complete
737 */
738
dfefe02b
SH		 739static void uli526x_free_tx_pkt(struct net_device *dev,
740 struct uli526x_board_info * db)
4689ced9
PC		 741{
742 struct tx_desc *txptr;
4689ced9
PC		 743 u32 tdes0;
744
745 txptr = db->tx_remove_ptr;
746 while(db->tx_packet_cnt) {
747 tdes0 = le32_to_cpu(txptr->tdes0);
4689ced9
PC		 748 if (tdes0 & 0x80000000)
749 break;
750
751 /* A packet sent completed */
752 db->tx_packet_cnt--;
dfefe02b 753 dev->stats.tx_packets++;
4689ced9
PC		 754
755 /* Transmit statistic counter */
756 if ( tdes0 != 0x7fffffff ) {
dfefe02b
SH		 757 dev->stats.collisions += (tdes0 >> 3) & 0xf;
758 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
4689ced9 759 if (tdes0 & TDES0_ERR_MASK) {
dfefe02b 760 dev->stats.tx_errors++;
4689ced9
PC		 761 if (tdes0 & 0x0002) { /* UnderRun */
762 db->tx_fifo_underrun++;
763 if ( !(db->cr6_data & CR6_SFT) ) {
764 db->cr6_data = db->cr6_data | CR6_SFT;
765 update_cr6(db->cr6_data, db->ioaddr);
766 }
767 }
768 if (tdes0 & 0x0100)
769 db->tx_excessive_collision++;
770 if (tdes0 & 0x0200)
771 db->tx_late_collision++;
772 if (tdes0 & 0x0400)
773 db->tx_no_carrier++;
774 if (tdes0 & 0x0800)
775 db->tx_loss_carrier++;
776 if (tdes0 & 0x4000)
777 db->tx_jabber_timeout++;
778 }
779 }
780
781 txptr = txptr->next_tx_desc;
782 }/* End of while */
783
784 /* Update TX remove pointer to next */
785 db->tx_remove_ptr = txptr;
786
787 /* Resource available check */
788 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
789 netif_wake_queue(dev); /* Active upper layer, send again */
790}
791
792
793/*
794 * Receive the come packet and pass to upper layer
795 */
796
945a7876 797static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 798{
799 struct rx_desc *rxptr;
800 struct sk_buff *skb;
801 int rxlen;
802 u32 rdes0;
f3b197ac 803
4689ced9
PC		 804 rxptr = db->rx_ready_ptr;
805
806 while(db->rx_avail_cnt) {
807 rdes0 = le32_to_cpu(rxptr->rdes0);
808 if (rdes0 & 0x80000000) /* packet owner check */
809 {
810 break;
811 }
812
813 db->rx_avail_cnt--;
814 db->interval_rx_cnt++;
815
816 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
817 if ( (rdes0 & 0x300) != 0x300) {
818 /* A packet without First/Last flag */
819 /* reuse this SKB */
820 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
821 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
822 } else {
823 /* A packet with First/Last flag */
824 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
825
826 /* error summary bit check */
827 if (rdes0 & 0x8000) {
828 /* This is a error packet */
dfefe02b 829 dev->stats.rx_errors++;
4689ced9 830 if (rdes0 & 1)
dfefe02b 831 dev->stats.rx_fifo_errors++;
4689ced9 832 if (rdes0 & 2)
dfefe02b 833 dev->stats.rx_crc_errors++;
4689ced9 834 if (rdes0 & 0x80)
dfefe02b 835 dev->stats.rx_length_errors++;
4689ced9
PC		 836 }
837
838 if ( !(rdes0 & 0x8000) ||
839 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
ac90a149
KM		 840 struct sk_buff *new_skb = NULL;
841
4689ced9 842 skb = rxptr->rx_skb_ptr;
f3b197ac 843
4689ced9
PC		 844 /* Good packet, send to upper layer */
845 /* Shorst packet used new SKB */
ac90a149 846 if ((rxlen < RX_COPY_SIZE) &&
7855f761 847 (((new_skb = dev_alloc_skb(rxlen + 2)) != NULL))) {
ac90a149 848 skb = new_skb;
4689ced9 849 /* size less than COPY_SIZE, allocate a rxlen SKB */
4689ced9 850 skb_reserve(skb, 2); /* 16byte align */
27a884dc
ACM		 851 memcpy(skb_put(skb, rxlen),
852 skb_tail_pointer(rxptr->rx_skb_ptr),
853 rxlen);
4689ced9 854 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 855 } else
4689ced9 856 skb_put(skb, rxlen);
4c13eb66 857
4689ced9
PC		 858 skb->protocol = eth_type_trans(skb, dev);
859 netif_rx(skb);
dfefe02b
SH		 860 dev->stats.rx_packets++;
861 dev->stats.rx_bytes += rxlen;
f3b197ac 862
4689ced9
PC		 863 } else {
864 /* Reuse SKB buffer when the packet is error */
865 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
866 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
867 }
868 }
869
870 rxptr = rxptr->next_rx_desc;
871 }
872
873 db->rx_ready_ptr = rxptr;
874}
875
876
4689ced9
PC		 877/*
878 * Set ULI526X multicast address
879 */
880
945a7876 881static void uli526x_set_filter_mode(struct net_device * dev)
4689ced9 882{
8f15ea42 883 struct uli526x_board_info *db = netdev_priv(dev);
4689ced9
PC		 884 unsigned long flags;
885
886 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
887 spin_lock_irqsave(&db->lock, flags);
888
889 if (dev->flags & IFF_PROMISC) {
890 ULI526X_DBUG(0, "Enable PROM Mode", 0);
891 db->cr6_data |= CR6_PM | CR6_PBF;
892 update_cr6(db->cr6_data, db->ioaddr);
893 spin_unlock_irqrestore(&db->lock, flags);
894 return;
895 }
896
4cd24eaf
JP		 897 if (dev->flags & IFF_ALLMULTI ||
898 netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
899 ULI526X_DBUG(0, "Pass all multicast address",
900 netdev_mc_count(dev));
4689ced9
PC		 901 db->cr6_data &= ~(CR6_PM | CR6_PBF);
902 db->cr6_data |= CR6_PAM;
903 spin_unlock_irqrestore(&db->lock, flags);
904 return;
905 }
906
4cd24eaf
JP		 907 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
908 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
4689ced9
PC		 909 spin_unlock_irqrestore(&db->lock, flags);
910}
911
912static void
913ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
914{
945a7876
PC		 915 ecmd->supported = (SUPPORTED_10baseT_Half |
916 SUPPORTED_10baseT_Full |
917 SUPPORTED_100baseT_Half |
918 SUPPORTED_100baseT_Full |
919 SUPPORTED_Autoneg |
920 SUPPORTED_MII);
f3b197ac 921
945a7876
PC		 922 ecmd->advertising = (ADVERTISED_10baseT_Half |
923 ADVERTISED_10baseT_Full |
924 ADVERTISED_100baseT_Half |
925 ADVERTISED_100baseT_Full |
926 ADVERTISED_Autoneg |
927 ADVERTISED_MII);
4689ced9
PC		 928
929
945a7876
PC		 930 ecmd->port = PORT_MII;
931 ecmd->phy_address = db->phy_addr;
4689ced9 932
945a7876 933 ecmd->transceiver = XCVR_EXTERNAL;
f3b197ac 934
70739497 935 ethtool_cmd_speed_set(ecmd, SPEED_10);
4689ced9 936 ecmd->duplex = DUPLEX_HALF;
f3b197ac 937
4689ced9
PC		 938 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
939 {
70739497 940 ethtool_cmd_speed_set(ecmd, SPEED_100);
4689ced9
PC		 941 }
942 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
943 {
944 ecmd->duplex = DUPLEX_FULL;
945 }
946 if(db->link_failed)
947 {
70739497 948 ethtool_cmd_speed_set(ecmd, -1);
f3b197ac 949 ecmd->duplex = -1;
4689ced9 950 }
f3b197ac 951
4689ced9 952 if (db->media_mode & ULI526X_AUTO)
f3b197ac 953 {
4689ced9
PC		 954 ecmd->autoneg = AUTONEG_ENABLE;
955 }
4689ced9
PC		 956}
957
958static void netdev_get_drvinfo(struct net_device *dev,
959 struct ethtool_drvinfo *info)
960{
961 struct uli526x_board_info *np = netdev_priv(dev);
962
963 strcpy(info->driver, DRV_NAME);
964 strcpy(info->version, DRV_VERSION);
965 if (np->pdev)
966 strcpy(info->bus_info, pci_name(np->pdev));
967 else
968 sprintf(info->bus_info, "EISA 0x%lx %d",
969 dev->base_addr, dev->irq);
970}
971
972static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
973 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 974
4689ced9 975 ULi_ethtool_gset(np, cmd);
f3b197ac 976
4689ced9
PC		 977 return 0;
978}
979
980static u32 netdev_get_link(struct net_device *dev) {
981 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 982
4689ced9
PC		 983 if(np->link_failed)
984 return 0;
985 else
986 return 1;
987}
988
989static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
990{
991 wol->supported = WAKE_PHY | WAKE_MAGIC;
992 wol->wolopts = 0;
993}
994
7282d491 995static const struct ethtool_ops netdev_ethtool_ops = {
4689ced9
PC		 996 .get_drvinfo = netdev_get_drvinfo,
997 .get_settings = netdev_get_settings,
998 .get_link = netdev_get_link,
999 .get_wol = uli526x_get_wol,
1000};
1001
1002/*
1003 * A periodic timer routine
1004 * Dynamic media sense, allocate Rx buffer...
1005 */
1006
1007static void uli526x_timer(unsigned long data)
1008{
1009 u32 tmp_cr8;
1010 unsigned char tmp_cr12=0;
945a7876 1011 struct net_device *dev = (struct net_device *) data;
4689ced9
PC		 1012 struct uli526x_board_info *db = netdev_priv(dev);
1013 unsigned long flags;
f3b197ac 1014
4689ced9
PC		 1015 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1016 spin_lock_irqsave(&db->lock, flags);
1017
f3b197ac 1018
4689ced9
PC		 1019 /* Dynamic reset ULI526X : system error or transmit time-out */
1020 tmp_cr8 = inl(db->ioaddr + DCR8);
1021 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1022 db->reset_cr8++;
1023 db->wait_reset = 1;
1024 }
1025 db->interval_rx_cnt = 0;
1026
1027 /* TX polling kick monitor */
1028 if ( db->tx_packet_cnt &&
1ae5dc34 1029 time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
f3b197ac 1030 outl(0x1, dev->base_addr + DCR1); // Tx polling again
4689ced9 1031
f3b197ac 1032 // TX Timeout
1ae5dc34 1033 if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
4689ced9
PC		 1034 db->reset_TXtimeout++;
1035 db->wait_reset = 1;
1c3319fb 1036 netdev_err(dev, " Tx timeout - resetting\n");
4689ced9
PC		 1037 }
1038 }
1039
1040 if (db->wait_reset) {
1041 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1042 db->reset_count++;
1043 uli526x_dynamic_reset(dev);
1044 db->timer.expires = ULI526X_TIMER_WUT;
1045 add_timer(&db->timer);
1046 spin_unlock_irqrestore(&db->lock, flags);
1047 return;
1048 }
1049
1050 /* Link status check, Dynamic media type change */
1051 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1052 tmp_cr12 = 3;
1053
1054 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1055 /* Link Failed */
1056 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1057 netif_carrier_off(dev);
163ef0b5 1058 netdev_info(dev, "NIC Link is Down\n");
4689ced9
PC		 1059 db->link_failed = 1;
1060
1061 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1062 /* AUTO don't need */
1063 if ( !(db->media_mode & 0x8) )
1064 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1065
1066 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1067 if (db->media_mode & ULI526X_AUTO) {
1068 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1069 update_cr6(db->cr6_data, db->ioaddr);
1070 }
1071 } else
1072 if ((tmp_cr12 & 0x3) && db->link_failed) {
1073 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1074 db->link_failed = 0;
1075
1076 /* Auto Sense Speed */
1077 if ( (db->media_mode & ULI526X_AUTO) &&
1078 uli526x_sense_speed(db) )
1079 db->link_failed = 1;
1080 uli526x_process_mode(db);
f3b197ac 1081
4689ced9
PC		 1082 if(db->link_failed==0)
1083 {
163ef0b5
JP		 1084 netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1085 (db->op_mode == ULI526X_100MHF ||
1086 db->op_mode == ULI526X_100MFD)
1087 ? 100 : 10,
1088 (db->op_mode == ULI526X_10MFD ||
1089 db->op_mode == ULI526X_100MFD)
1090 ? "Full" : "Half");
4689ced9
PC		 1091 netif_carrier_on(dev);
1092 }
1093 /* SHOW_MEDIA_TYPE(db->op_mode); */
1094 }
1095 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1096 {
1097 if(db->init==1)
1098 {
163ef0b5 1099 netdev_info(dev, "NIC Link is Down\n");
4689ced9
PC		 1100 netif_carrier_off(dev);
1101 }
1102 }
1103 db->init=0;
1104
1105 /* Timer active again */
1106 db->timer.expires = ULI526X_TIMER_WUT;
1107 add_timer(&db->timer);
1108 spin_unlock_irqrestore(&db->lock, flags);
1109}
1110
1111
1112/*
4689ced9
PC		 1113 * Stop ULI526X board
1114 * Free Tx/Rx allocated memory
b6aec32a 1115 * Init system variable
4689ced9
PC		 1116 */
1117
b6aec32a 1118static void uli526x_reset_prepare(struct net_device *dev)
4689ced9
PC		 1119{
1120 struct uli526x_board_info *db = netdev_priv(dev);
1121
4689ced9
PC		 1122 /* Sopt MAC controller */
1123 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1124 update_cr6(db->cr6_data, dev->base_addr);
1125 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1126 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1127
1128 /* Disable upper layer interface */
1129 netif_stop_queue(dev);
1130
1131 /* Free Rx Allocate buffer */
1132 uli526x_free_rxbuffer(db);
1133
1134 /* system variable init */
1135 db->tx_packet_cnt = 0;
1136 db->rx_avail_cnt = 0;
1137 db->link_failed = 1;
1138 db->init=1;
1139 db->wait_reset = 0;
b6aec32a
RW		 1140}
1141
1142
1143/*
1144 * Dynamic reset the ULI526X board
1145 * Stop ULI526X board
1146 * Free Tx/Rx allocated memory
1147 * Reset ULI526X board
1148 * Re-initialize ULI526X board
1149 */
1150
1151static void uli526x_dynamic_reset(struct net_device *dev)
1152{
1153 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1154
1155 uli526x_reset_prepare(dev);
4689ced9 1156
945a7876 1157 /* Re-initialize ULI526X board */
4689ced9
PC		 1158 uli526x_init(dev);
1159
1160 /* Restart upper layer interface */
1161 netif_wake_queue(dev);
1162}
1163
1164
b6aec32a
RW		 1165#ifdef CONFIG_PM
1166
1167/*
1168 * Suspend the interface.
1169 */
1170
1171static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1172{
1173 struct net_device *dev = pci_get_drvdata(pdev);
1174 pci_power_t power_state;
1175 int err;
1176
1177 ULI526X_DBUG(0, "uli526x_suspend", 0);
1178
1179 if (!netdev_priv(dev))
1180 return 0;
1181
1182 pci_save_state(pdev);
1183
1184 if (!netif_running(dev))
1185 return 0;
1186
1187 netif_device_detach(dev);
1188 uli526x_reset_prepare(dev);
1189
1190 power_state = pci_choose_state(pdev, state);
1191 pci_enable_wake(pdev, power_state, 0);
1192 err = pci_set_power_state(pdev, power_state);
1193 if (err) {
1194 netif_device_attach(dev);
1195 /* Re-initialize ULI526X board */
1196 uli526x_init(dev);
1197 /* Restart upper layer interface */
1198 netif_wake_queue(dev);
1199 }
1200
1201 return err;
1202}
1203
1204/*
1205 * Resume the interface.
1206 */
1207
1208static int uli526x_resume(struct pci_dev *pdev)
1209{
1210 struct net_device *dev = pci_get_drvdata(pdev);
1211 int err;
1212
1213 ULI526X_DBUG(0, "uli526x_resume", 0);
1214
1215 if (!netdev_priv(dev))
1216 return 0;
1217
1218 pci_restore_state(pdev);
1219
1220 if (!netif_running(dev))
1221 return 0;
1222
1223 err = pci_set_power_state(pdev, PCI_D0);
1224 if (err) {
163ef0b5 1225 netdev_warn(dev, "Could not put device into D0\n");
b6aec32a
RW		 1226 return err;
1227 }
1228
1229 netif_device_attach(dev);
1230 /* Re-initialize ULI526X board */
1231 uli526x_init(dev);
1232 /* Restart upper layer interface */
1233 netif_wake_queue(dev);
1234
1235 return 0;
1236}
1237
1238#else /* !CONFIG_PM */
1239
1240#define uli526x_suspend NULL
1241#define uli526x_resume NULL
1242
1243#endif /* !CONFIG_PM */
1244
1245
4689ced9
PC		 1246/*
1247 * free all allocated rx buffer
1248 */
1249
1250static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1251{
1252 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1253
1254 /* free allocated rx buffer */
1255 while (db->rx_avail_cnt) {
1256 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1257 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1258 db->rx_avail_cnt--;
1259 }
1260}
1261
1262
1263/*
1264 * Reuse the SK buffer
1265 */
1266
1267static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1268{
1269 struct rx_desc *rxptr = db->rx_insert_ptr;
1270
1271 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1272 rxptr->rx_skb_ptr = skb;
27a884dc
ACM		 1273 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1274 skb_tail_pointer(skb),
1275 RX_ALLOC_SIZE,
1276 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1277 wmb();
1278 rxptr->rdes0 = cpu_to_le32(0x80000000);
1279 db->rx_avail_cnt++;
1280 db->rx_insert_ptr = rxptr->next_rx_desc;
1281 } else
1282 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1283}
1284
1285
1286/*
1287 * Initialize transmit/Receive descriptor
1288 * Using Chain structure, and allocate Tx/Rx buffer
1289 */
1290
1291static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1292{
1293 struct tx_desc *tmp_tx;
1294 struct rx_desc *tmp_rx;
1295 unsigned char *tmp_buf;
1296 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1297 dma_addr_t tmp_buf_dma;
1298 int i;
1299
1300 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1301
1302 /* tx descriptor start pointer */
1303 db->tx_insert_ptr = db->first_tx_desc;
1304 db->tx_remove_ptr = db->first_tx_desc;
1305 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1306
1307 /* rx descriptor start pointer */
1308 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1309 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1310 db->rx_insert_ptr = db->first_rx_desc;
1311 db->rx_ready_ptr = db->first_rx_desc;
1312 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1313
1314 /* Init Transmit chain */
1315 tmp_buf = db->buf_pool_start;
1316 tmp_buf_dma = db->buf_pool_dma_start;
1317 tmp_tx_dma = db->first_tx_desc_dma;
1318 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1319 tmp_tx->tx_buf_ptr = tmp_buf;
1320 tmp_tx->tdes0 = cpu_to_le32(0);
1321 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1322 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1323 tmp_tx_dma += sizeof(struct tx_desc);
1324 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1325 tmp_tx->next_tx_desc = tmp_tx + 1;
1326 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1327 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1328 }
1329 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1330 tmp_tx->next_tx_desc = db->first_tx_desc;
1331
1332 /* Init Receive descriptor chain */
1333 tmp_rx_dma=db->first_rx_desc_dma;
1334 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1335 tmp_rx->rdes0 = cpu_to_le32(0);
1336 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1337 tmp_rx_dma += sizeof(struct rx_desc);
1338 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1339 tmp_rx->next_rx_desc = tmp_rx + 1;
1340 }
1341 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1342 tmp_rx->next_rx_desc = db->first_rx_desc;
1343
1344 /* pre-allocate Rx buffer */
1345 allocate_rx_buffer(db);
1346}
1347
1348
1349/*
1350 * Update CR6 value
945a7876 1351 * Firstly stop ULI526X, then written value and start
4689ced9
PC		 1352 */
1353
1354static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1355{
1356
1357 outl(cr6_data, ioaddr + DCR6);
1358 udelay(5);
1359}
1360
1361
1362/*
1363 * Send a setup frame for M5261/M5263
945a7876 1364 * This setup frame initialize ULI526X address filter mode
4689ced9
PC		 1365 */
1366
e284e5c6
AV		 1367#ifdef __BIG_ENDIAN
1368#define FLT_SHIFT 16
1369#else
1370#define FLT_SHIFT 0
1371#endif
1372
945a7876 1373static void send_filter_frame(struct net_device *dev, int mc_cnt)
4689ced9
PC		 1374{
1375 struct uli526x_board_info *db = netdev_priv(dev);
22bedad3 1376 struct netdev_hw_addr *ha;
4689ced9
PC		 1377 struct tx_desc *txptr;
1378 u16 * addrptr;
1379 u32 * suptr;
1380 int i;
1381
1382 ULI526X_DBUG(0, "send_filter_frame()", 0);
1383
1384 txptr = db->tx_insert_ptr;
1385 suptr = (u32 *) txptr->tx_buf_ptr;
1386
1387 /* Node address */
1388 addrptr = (u16 *) dev->dev_addr;
e284e5c6
AV		 1389 *suptr++ = addrptr[0] << FLT_SHIFT;
1390 *suptr++ = addrptr[1] << FLT_SHIFT;
1391 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1392
1393 /* broadcast address */
e284e5c6
AV		 1394 *suptr++ = 0xffff << FLT_SHIFT;
1395 *suptr++ = 0xffff << FLT_SHIFT;
1396 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1397
1398 /* fit the multicast address */
22bedad3
JP		 1399 netdev_for_each_mc_addr(ha, dev) {
1400 addrptr = (u16 *) ha->addr;
e284e5c6
AV		 1401 *suptr++ = addrptr[0] << FLT_SHIFT;
1402 *suptr++ = addrptr[1] << FLT_SHIFT;
1403 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1404 }
1405
4302b67e 1406 for (i = netdev_mc_count(dev); i < 14; i++) {
e284e5c6
AV		 1407 *suptr++ = 0xffff << FLT_SHIFT;
1408 *suptr++ = 0xffff << FLT_SHIFT;
1409 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1410 }
1411
1412 /* prepare the setup frame */
1413 db->tx_insert_ptr = txptr->next_tx_desc;
1414 txptr->tdes1 = cpu_to_le32(0x890000c0);
1415
1416 /* Resource Check and Send the setup packet */
1417 if (db->tx_packet_cnt < TX_DESC_CNT) {
1418 /* Resource Empty */
1419 db->tx_packet_cnt++;
1420 txptr->tdes0 = cpu_to_le32(0x80000000);
1421 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1422 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1423 update_cr6(db->cr6_data, dev->base_addr);
1424 dev->trans_start = jiffies;
1425 } else
163ef0b5 1426 netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
4689ced9
PC		 1427}
1428
1429
1430/*
1431 * Allocate rx buffer,
1432 * As possible as allocate maxiumn Rx buffer
1433 */
1434
1435static void allocate_rx_buffer(struct uli526x_board_info *db)
1436{
1437 struct rx_desc *rxptr;
1438 struct sk_buff *skb;
1439
1440 rxptr = db->rx_insert_ptr;
1441
1442 while(db->rx_avail_cnt < RX_DESC_CNT) {
1443 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1444 break;
1445 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
27a884dc
ACM		 1446 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1447 skb_tail_pointer(skb),
1448 RX_ALLOC_SIZE,
1449 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1450 wmb();
1451 rxptr->rdes0 = cpu_to_le32(0x80000000);
1452 rxptr = rxptr->next_rx_desc;
1453 db->rx_avail_cnt++;
1454 }
1455
1456 db->rx_insert_ptr = rxptr;
1457}
1458
1459
1460/*
1461 * Read one word data from the serial ROM
1462 */
1463
1464static u16 read_srom_word(long ioaddr, int offset)
1465{
1466 int i;
1467 u16 srom_data = 0;
1468 long cr9_ioaddr = ioaddr + DCR9;
1469
1470 outl(CR9_SROM_READ, cr9_ioaddr);
1471 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1472
1473 /* Send the Read Command 110b */
1474 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1475 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1476 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1477
1478 /* Send the offset */
1479 for (i = 5; i >= 0; i--) {
1480 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1481 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1482 }
1483
1484 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1485
1486 for (i = 16; i > 0; i--) {
1487 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1488 udelay(5);
1489 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1490 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1491 udelay(5);
1492 }
1493
1494 outl(CR9_SROM_READ, cr9_ioaddr);
1495 return srom_data;
1496}
1497
1498
1499/*
1500 * Auto sense the media mode
1501 */
1502
1503static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1504{
1505 u8 ErrFlag = 0;
1506 u16 phy_mode;
1507
1508 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1509 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1510
1511 if ( (phy_mode & 0x24) == 0x24 ) {
f3b197ac 1512
4689ced9
PC		 1513 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1514 if(phy_mode&0x8000)
1515 phy_mode = 0x8000;
1516 else if(phy_mode&0x4000)
1517 phy_mode = 0x4000;
1518 else if(phy_mode&0x2000)
1519 phy_mode = 0x2000;
1520 else
1521 phy_mode = 0x1000;
f3b197ac 1522
4689ced9
PC		 1523 switch (phy_mode) {
1524 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1525 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1526 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1527 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1528 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1529 }
1530 } else {
1531 db->op_mode = ULI526X_10MHF;
1532 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1533 ErrFlag = 1;
1534 }
1535
1536 return ErrFlag;
1537}
1538
1539
1540/*
1541 * Set 10/100 phyxcer capability
1542 * AUTO mode : phyxcer register4 is NIC capability
1543 * Force mode: phyxcer register4 is the force media
1544 */
1545
1546static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1547{
1548 u16 phy_reg;
f3b197ac 1549
4689ced9
PC		 1550 /* Phyxcer capability setting */
1551 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1552
1553 if (db->media_mode & ULI526X_AUTO) {
1554 /* AUTO Mode */
1555 phy_reg |= db->PHY_reg4;
1556 } else {
1557 /* Force Mode */
1558 switch(db->media_mode) {
1559 case ULI526X_10MHF: phy_reg |= 0x20; break;
1560 case ULI526X_10MFD: phy_reg |= 0x40; break;
1561 case ULI526X_100MHF: phy_reg |= 0x80; break;
1562 case ULI526X_100MFD: phy_reg |= 0x100; break;
1563 }
f3b197ac 1564
4689ced9
PC		 1565 }
1566
1567 /* Write new capability to Phyxcer Reg4 */
1568 if ( !(phy_reg & 0x01e0)) {
1569 phy_reg|=db->PHY_reg4;
1570 db->media_mode|=ULI526X_AUTO;
1571 }
1572 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1573
1574 /* Restart Auto-Negotiation */
1575 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1576 udelay(50);
1577}
1578
1579
1580/*
1581 * Process op-mode
1582 AUTO mode : PHY controller in Auto-negotiation Mode
1583 * Force mode: PHY controller in force mode with HUB
1584 * N-way force capability with SWITCH
1585 */
1586
1587static void uli526x_process_mode(struct uli526x_board_info *db)
1588{
1589 u16 phy_reg;
1590
1591 /* Full Duplex Mode Check */
1592 if (db->op_mode & 0x4)
1593 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1594 else
1595 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1596
1597 update_cr6(db->cr6_data, db->ioaddr);
1598
1599 /* 10/100M phyxcer force mode need */
1600 if ( !(db->media_mode & 0x8)) {
1601 /* Forece Mode */
1602 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1603 if ( !(phy_reg & 0x1) ) {
1604 /* parter without N-Way capability */
1605 phy_reg = 0x0;
1606 switch(db->op_mode) {
1607 case ULI526X_10MHF: phy_reg = 0x0; break;
1608 case ULI526X_10MFD: phy_reg = 0x100; break;
1609 case ULI526X_100MHF: phy_reg = 0x2000; break;
1610 case ULI526X_100MFD: phy_reg = 0x2100; break;
1611 }
1612 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
4689ced9
PC		 1613 }
1614 }
1615}
1616
1617
1618/*
1619 * Write a word to Phy register
1620 */
1621
1622static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1623{
1624 u16 i;
1625 unsigned long ioaddr;
1626
1627 if(chip_id == PCI_ULI5263_ID)
1628 {
1629 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1630 return;
1631 }
1632 /* M5261/M5263 Chip */
1633 ioaddr = iobase + DCR9;
1634
1635 /* Send 33 synchronization clock to Phy controller */
1636 for (i = 0; i < 35; i++)
1637 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1638
1639 /* Send start command(01) to Phy */
1640 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1641 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1642
1643 /* Send write command(01) to Phy */
1644 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1645 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1646
1647 /* Send Phy address */
1648 for (i = 0x10; i > 0; i = i >> 1)
1649 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1650
1651 /* Send register address */
1652 for (i = 0x10; i > 0; i = i >> 1)
1653 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1654
1655 /* written trasnition */
1656 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1657 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1658
1659 /* Write a word data to PHY controller */
1660 for ( i = 0x8000; i > 0; i >>= 1)
1661 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
f3b197ac 1662
4689ced9
PC		 1663}
1664
1665
1666/*
1667 * Read a word data from phy register
1668 */
1669
1670static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1671{
1672 int i;
1673 u16 phy_data;
1674 unsigned long ioaddr;
1675
1676 if(chip_id == PCI_ULI5263_ID)
1677 return phy_readby_cr10(iobase, phy_addr, offset);
1678 /* M5261/M5263 Chip */
1679 ioaddr = iobase + DCR9;
f3b197ac 1680
4689ced9
PC		 1681 /* Send 33 synchronization clock to Phy controller */
1682 for (i = 0; i < 35; i++)
1683 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1684
1685 /* Send start command(01) to Phy */
1686 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1687 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1688
1689 /* Send read command(10) to Phy */
1690 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1691 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1692
1693 /* Send Phy address */
1694 for (i = 0x10; i > 0; i = i >> 1)
1695 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1696
1697 /* Send register address */
1698 for (i = 0x10; i > 0; i = i >> 1)
1699 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1700
1701 /* Skip transition state */
1702 phy_read_1bit(ioaddr, chip_id);
1703
1704 /* read 16bit data */
1705 for (phy_data = 0, i = 0; i < 16; i++) {
1706 phy_data <<= 1;
1707 phy_data |= phy_read_1bit(ioaddr, chip_id);
1708 }
1709
1710 return phy_data;
1711}
1712
1713static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1714{
1715 unsigned long ioaddr,cr10_value;
f3b197ac 1716
4689ced9
PC		 1717 ioaddr = iobase + DCR10;
1718 cr10_value = phy_addr;
1719 cr10_value = (cr10_value<<5) + offset;
1720 cr10_value = (cr10_value<<16) + 0x08000000;
1721 outl(cr10_value,ioaddr);
1722 udelay(1);
1723 while(1)
1724 {
1725 cr10_value = inl(ioaddr);
1726 if(cr10_value&0x10000000)
1727 break;
1728 }
807540ba 1729 return cr10_value & 0x0ffff;
4689ced9
PC		 1730}
1731
1732static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1733{
1734 unsigned long ioaddr,cr10_value;
f3b197ac 1735
4689ced9
PC		 1736 ioaddr = iobase + DCR10;
1737 cr10_value = phy_addr;
1738 cr10_value = (cr10_value<<5) + offset;
1739 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1740 outl(cr10_value,ioaddr);
1741 udelay(1);
1742}
1743/*
1744 * Write one bit data to Phy Controller
1745 */
1746
1747static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1748{
1749 outl(phy_data , ioaddr); /* MII Clock Low */
1750 udelay(1);
1751 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1752 udelay(1);
1753 outl(phy_data , ioaddr); /* MII Clock Low */
1754 udelay(1);
1755}
1756
1757
1758/*
1759 * Read one bit phy data from PHY controller
1760 */
1761
1762static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1763{
1764 u16 phy_data;
f3b197ac 1765
4689ced9
PC		 1766 outl(0x50000 , ioaddr);
1767 udelay(1);
1768 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1769 outl(0x40000 , ioaddr);
1770 udelay(1);
1771
1772 return phy_data;
1773}
1774
1775
a3aa1884 1776static DEFINE_PCI_DEVICE_TABLE(uli526x_pci_tbl) = {
4689ced9
PC		 1777 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1778 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1779 { 0, }
1780};
1781MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1782
1783
1784static struct pci_driver uli526x_driver = {
1785 .name = "uli526x",
1786 .id_table = uli526x_pci_tbl,
1787 .probe = uli526x_init_one,
1788 .remove = __devexit_p(uli526x_remove_one),
b6aec32a
RW		 1789 .suspend = uli526x_suspend,
1790 .resume = uli526x_resume,
4689ced9
PC		 1791};
1792
1793MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1794MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1795MODULE_LICENSE("GPL");
1796
c213460f
ES		 1797module_param(debug, int, 0644);
1798module_param(mode, int, 0);
1799module_param(cr6set, int, 0);
4689ced9
PC		 1800MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1801MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1802
1803/* Description:
1804 * when user used insmod to add module, system invoked init_module()
945a7876 1805 * to register the services.
4689ced9
PC		 1806 */
1807
1808static int __init uli526x_init_module(void)
1809{
4689ced9 1810
1c3319fb 1811 pr_info("%s\n", version);
4689ced9
PC		 1812 printed_version = 1;
1813
1814 ULI526X_DBUG(0, "init_module() ", debug);
1815
1816 if (debug)
1817 uli526x_debug = debug; /* set debug flag */
1818 if (cr6set)
1819 uli526x_cr6_user_set = cr6set;
1820
e1c3e501 1821 switch (mode) {
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PC		 1822 case ULI526X_10MHF:
1823 case ULI526X_100MHF:
1824 case ULI526X_10MFD:
1825 case ULI526X_100MFD:
1826 uli526x_media_mode = mode;
1827 break;
e1c3e501
HK		 1828 default:
1829 uli526x_media_mode = ULI526X_AUTO;
4689ced9
PC		 1830 break;
1831 }
1832
e1c3e501 1833 return pci_register_driver(&uli526x_driver);
4689ced9
PC		 1834}
1835
1836
1837/*
1838 * Description:
1839 * when user used rmmod to delete module, system invoked clean_module()
1840 * to un-register all registered services.
1841 */
1842
1843static void __exit uli526x_cleanup_module(void)
1844{
1845 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1846 pci_unregister_driver(&uli526x_driver);
1847}
1848
1849module_init(uli526x_init_module);
1850module_exit(uli526x_cleanup_module);
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