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Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
f3b197ac | 2 | * xircom_cb: A driver for the (tulip-like) Xircom Cardbus ethernet cards |
1da177e4 LT |
3 | * |
4 | * This software is (C) by the respective authors, and licensed under the GPL | |
5 | * License. | |
6 | * | |
7 | * Written by Arjan van de Ven for Red Hat, Inc. | |
f3b197ac | 8 | * Based on work by Jeff Garzik, Doug Ledford and Donald Becker |
1da177e4 LT |
9 | * |
10 | * This software may be used and distributed according to the terms | |
11 | * of the GNU General Public License, incorporated herein by reference. | |
12 | * | |
13 | * | |
14 | * $Id: xircom_cb.c,v 1.33 2001/03/19 14:02:07 arjanv Exp $ | |
15 | */ | |
16 | ||
44298ec0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/netdevice.h> | |
28 | #include <linux/etherdevice.h> | |
29 | #include <linux/skbuff.h> | |
30 | #include <linux/delay.h> | |
1da177e4 LT |
31 | #include <linux/bitops.h> |
32 | ||
33 | #include <asm/uaccess.h> | |
34 | #include <asm/io.h> | |
82729971 AV |
35 | #ifdef CONFIG_NET_POLL_CONTROLLER |
36 | #include <asm/irq.h> | |
37 | #endif | |
1da177e4 | 38 | |
1da177e4 LT |
39 | MODULE_DESCRIPTION("Xircom Cardbus ethernet driver"); |
40 | MODULE_AUTHOR("Arjan van de Ven <arjanv@redhat.com>"); | |
41 | MODULE_LICENSE("GPL"); | |
42 | ||
ebaf7f8f FR |
43 | #define xw32(reg, val) iowrite32(val, ioaddr + (reg)) |
44 | #define xr32(reg) ioread32(ioaddr + (reg)) | |
45 | #define xr8(reg) ioread8(ioaddr + (reg)) | |
1da177e4 LT |
46 | |
47 | /* IO registers on the card, offsets */ | |
48 | #define CSR0 0x00 | |
49 | #define CSR1 0x08 | |
50 | #define CSR2 0x10 | |
51 | #define CSR3 0x18 | |
52 | #define CSR4 0x20 | |
53 | #define CSR5 0x28 | |
54 | #define CSR6 0x30 | |
55 | #define CSR7 0x38 | |
56 | #define CSR8 0x40 | |
57 | #define CSR9 0x48 | |
58 | #define CSR10 0x50 | |
59 | #define CSR11 0x58 | |
60 | #define CSR12 0x60 | |
61 | #define CSR13 0x68 | |
62 | #define CSR14 0x70 | |
63 | #define CSR15 0x78 | |
64 | #define CSR16 0x80 | |
65 | ||
66 | /* PCI registers */ | |
67 | #define PCI_POWERMGMT 0x40 | |
68 | ||
69 | /* Offsets of the buffers within the descriptor pages, in bytes */ | |
70 | ||
71 | #define NUMDESCRIPTORS 4 | |
72 | ||
73 | static int bufferoffsets[NUMDESCRIPTORS] = {128,2048,4096,6144}; | |
74 | ||
75 | ||
76 | struct xircom_private { | |
77 | /* Send and receive buffers, kernel-addressable and dma addressable forms */ | |
78 | ||
6f35d5d5 AV |
79 | __le32 *rx_buffer; |
80 | __le32 *tx_buffer; | |
1da177e4 LT |
81 | |
82 | dma_addr_t rx_dma_handle; | |
83 | dma_addr_t tx_dma_handle; | |
84 | ||
85 | struct sk_buff *tx_skb[4]; | |
86 | ||
ebaf7f8f | 87 | void __iomem *ioaddr; |
1da177e4 | 88 | int open; |
f3b197ac | 89 | |
1da177e4 LT |
90 | /* transmit_used is the rotating counter that indicates which transmit |
91 | descriptor has to be used next */ | |
92 | int transmit_used; | |
93 | ||
94 | /* Spinlock to serialize register operations. | |
95 | It must be helt while manipulating the following registers: | |
96 | CSR0, CSR6, CSR7, CSR9, CSR10, CSR15 | |
97 | */ | |
98 | spinlock_t lock; | |
99 | ||
1da177e4 LT |
100 | struct pci_dev *pdev; |
101 | struct net_device *dev; | |
1da177e4 LT |
102 | }; |
103 | ||
104 | ||
105 | /* Function prototypes */ | |
106 | static int xircom_probe(struct pci_dev *pdev, const struct pci_device_id *id); | |
107 | static void xircom_remove(struct pci_dev *pdev); | |
7d12e780 | 108 | static irqreturn_t xircom_interrupt(int irq, void *dev_instance); |
ad096463 SH |
109 | static netdev_tx_t xircom_start_xmit(struct sk_buff *skb, |
110 | struct net_device *dev); | |
1da177e4 LT |
111 | static int xircom_open(struct net_device *dev); |
112 | static int xircom_close(struct net_device *dev); | |
113 | static void xircom_up(struct xircom_private *card); | |
3be034b6 | 114 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1da177e4 LT |
115 | static void xircom_poll_controller(struct net_device *dev); |
116 | #endif | |
117 | ||
118 | static void investigate_read_descriptor(struct net_device *dev,struct xircom_private *card, int descnr, unsigned int bufferoffset); | |
119 | static void investigate_write_descriptor(struct net_device *dev, struct xircom_private *card, int descnr, unsigned int bufferoffset); | |
120 | static void read_mac_address(struct xircom_private *card); | |
121 | static void transceiver_voodoo(struct xircom_private *card); | |
122 | static void initialize_card(struct xircom_private *card); | |
123 | static void trigger_transmit(struct xircom_private *card); | |
124 | static void trigger_receive(struct xircom_private *card); | |
125 | static void setup_descriptors(struct xircom_private *card); | |
126 | static void remove_descriptors(struct xircom_private *card); | |
127 | static int link_status_changed(struct xircom_private *card); | |
128 | static void activate_receiver(struct xircom_private *card); | |
129 | static void deactivate_receiver(struct xircom_private *card); | |
130 | static void activate_transmitter(struct xircom_private *card); | |
131 | static void deactivate_transmitter(struct xircom_private *card); | |
132 | static void enable_transmit_interrupt(struct xircom_private *card); | |
133 | static void enable_receive_interrupt(struct xircom_private *card); | |
134 | static void enable_link_interrupt(struct xircom_private *card); | |
135 | static void disable_all_interrupts(struct xircom_private *card); | |
136 | static int link_status(struct xircom_private *card); | |
137 | ||
138 | ||
139 | ||
9baa3c34 | 140 | static const struct pci_device_id xircom_pci_table[] = { |
ebaf7f8f | 141 | { PCI_VDEVICE(XIRCOM, 0x0003), }, |
1da177e4 LT |
142 | {0,}, |
143 | }; | |
144 | MODULE_DEVICE_TABLE(pci, xircom_pci_table); | |
145 | ||
146 | static struct pci_driver xircom_ops = { | |
f3b197ac JG |
147 | .name = "xircom_cb", |
148 | .id_table = xircom_pci_table, | |
149 | .probe = xircom_probe, | |
779c1a85 | 150 | .remove = xircom_remove, |
1da177e4 LT |
151 | }; |
152 | ||
153 | ||
54668b84 | 154 | #if defined DEBUG && DEBUG > 1 |
1da177e4 LT |
155 | static void print_binary(unsigned int number) |
156 | { | |
157 | int i,i2; | |
158 | char buffer[64]; | |
159 | memset(buffer,0,64); | |
160 | i2=0; | |
161 | for (i=31;i>=0;i--) { | |
162 | if (number & (1<<i)) | |
163 | buffer[i2++]='1'; | |
164 | else | |
165 | buffer[i2++]='0'; | |
f3b197ac | 166 | if ((i&3)==0) |
1da177e4 LT |
167 | buffer[i2++]=' '; |
168 | } | |
54668b84 | 169 | pr_debug("%s\n",buffer); |
1da177e4 LT |
170 | } |
171 | #endif | |
172 | ||
1034c9f6 SH |
173 | static const struct net_device_ops netdev_ops = { |
174 | .ndo_open = xircom_open, | |
175 | .ndo_stop = xircom_close, | |
176 | .ndo_start_xmit = xircom_start_xmit, | |
177 | .ndo_change_mtu = eth_change_mtu, | |
178 | .ndo_set_mac_address = eth_mac_addr, | |
179 | .ndo_validate_addr = eth_validate_addr, | |
180 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
181 | .ndo_poll_controller = xircom_poll_controller, | |
182 | #endif | |
183 | }; | |
184 | ||
1da177e4 LT |
185 | /* xircom_probe is the code that gets called on device insertion. |
186 | it sets up the hardware and registers the device to the networklayer. | |
f3b197ac | 187 | |
1da177e4 LT |
188 | TODO: Send 1 or 2 "dummy" packets here as the card seems to discard the |
189 | first two packets that get send, and pump hates that. | |
f3b197ac | 190 | |
1da177e4 | 191 | */ |
779c1a85 | 192 | static int xircom_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
1da177e4 | 193 | { |
d59a1881 | 194 | struct device *d = &pdev->dev; |
1da177e4 LT |
195 | struct net_device *dev = NULL; |
196 | struct xircom_private *private; | |
1da177e4 LT |
197 | unsigned long flags; |
198 | unsigned short tmp16; | |
d59a1881 | 199 | int rc; |
f3b197ac | 200 | |
1da177e4 LT |
201 | /* First do the PCI initialisation */ |
202 | ||
d59a1881 FR |
203 | rc = pci_enable_device(pdev); |
204 | if (rc < 0) | |
205 | goto out; | |
1da177e4 LT |
206 | |
207 | /* disable all powermanagement */ | |
208 | pci_write_config_dword(pdev, PCI_POWERMGMT, 0x0000); | |
f3b197ac | 209 | |
1da177e4 LT |
210 | pci_set_master(pdev); /* Why isn't this done by pci_enable_device ?*/ |
211 | ||
f3b197ac JG |
212 | /* clear PCI status, if any */ |
213 | pci_read_config_word (pdev,PCI_STATUS, &tmp16); | |
1da177e4 | 214 | pci_write_config_word (pdev, PCI_STATUS,tmp16); |
f3b197ac | 215 | |
d59a1881 FR |
216 | rc = pci_request_regions(pdev, "xircom_cb"); |
217 | if (rc < 0) { | |
44298ec0 | 218 | pr_err("%s: failed to allocate io-region\n", __func__); |
d59a1881 | 219 | goto err_disable; |
1da177e4 LT |
220 | } |
221 | ||
d59a1881 | 222 | rc = -ENOMEM; |
f3b197ac | 223 | /* |
1da177e4 LT |
224 | Before changing the hardware, allocate the memory. |
225 | This way, we can fail gracefully if not enough memory | |
f3b197ac | 226 | is available. |
1da177e4 LT |
227 | */ |
228 | dev = alloc_etherdev(sizeof(struct xircom_private)); | |
41de8d4c | 229 | if (!dev) |
d59a1881 | 230 | goto err_release; |
41de8d4c | 231 | |
1da177e4 | 232 | private = netdev_priv(dev); |
f3b197ac | 233 | |
1da177e4 | 234 | /* Allocate the send/receive buffers */ |
d59a1881 FR |
235 | private->rx_buffer = dma_alloc_coherent(d, 8192, |
236 | &private->rx_dma_handle, | |
237 | GFP_KERNEL); | |
d0320f75 | 238 | if (private->rx_buffer == NULL) |
1da177e4 | 239 | goto rx_buf_fail; |
d0320f75 | 240 | |
d59a1881 FR |
241 | private->tx_buffer = dma_alloc_coherent(d, 8192, |
242 | &private->tx_dma_handle, | |
243 | GFP_KERNEL); | |
d0320f75 | 244 | if (private->tx_buffer == NULL) |
1da177e4 | 245 | goto tx_buf_fail; |
1da177e4 | 246 | |
1da177e4 LT |
247 | SET_NETDEV_DEV(dev, &pdev->dev); |
248 | ||
249 | ||
250 | private->dev = dev; | |
251 | private->pdev = pdev; | |
ebaf7f8f FR |
252 | |
253 | /* IO range. */ | |
254 | private->ioaddr = pci_iomap(pdev, 0, 0); | |
255 | if (!private->ioaddr) | |
256 | goto reg_fail; | |
257 | ||
1da177e4 | 258 | spin_lock_init(&private->lock); |
f3b197ac | 259 | |
1da177e4 LT |
260 | initialize_card(private); |
261 | read_mac_address(private); | |
262 | setup_descriptors(private); | |
f3b197ac | 263 | |
1034c9f6 | 264 | dev->netdev_ops = &netdev_ops; |
1da177e4 LT |
265 | pci_set_drvdata(pdev, dev); |
266 | ||
d59a1881 FR |
267 | rc = register_netdev(dev); |
268 | if (rc < 0) { | |
44298ec0 | 269 | pr_err("%s: netdevice registration failed\n", __func__); |
ebaf7f8f | 270 | goto err_unmap; |
1da177e4 | 271 | } |
f3b197ac | 272 | |
163ef0b5 JP |
273 | netdev_info(dev, "Xircom cardbus revision %i at irq %i\n", |
274 | pdev->revision, pdev->irq); | |
1da177e4 LT |
275 | /* start the transmitter to get a heartbeat */ |
276 | /* TODO: send 2 dummy packets here */ | |
277 | transceiver_voodoo(private); | |
f3b197ac | 278 | |
1da177e4 LT |
279 | spin_lock_irqsave(&private->lock,flags); |
280 | activate_transmitter(private); | |
281 | activate_receiver(private); | |
282 | spin_unlock_irqrestore(&private->lock,flags); | |
f3b197ac | 283 | |
1da177e4 | 284 | trigger_receive(private); |
d59a1881 FR |
285 | out: |
286 | return rc; | |
1da177e4 | 287 | |
ebaf7f8f FR |
288 | err_unmap: |
289 | pci_iounmap(pdev, private->ioaddr); | |
1da177e4 | 290 | reg_fail: |
d59a1881 | 291 | dma_free_coherent(d, 8192, private->tx_buffer, private->tx_dma_handle); |
1da177e4 | 292 | tx_buf_fail: |
d59a1881 | 293 | dma_free_coherent(d, 8192, private->rx_buffer, private->rx_dma_handle); |
1da177e4 LT |
294 | rx_buf_fail: |
295 | free_netdev(dev); | |
d59a1881 FR |
296 | err_release: |
297 | pci_release_regions(pdev); | |
298 | err_disable: | |
299 | pci_disable_device(pdev); | |
300 | goto out; | |
1da177e4 LT |
301 | } |
302 | ||
303 | ||
304 | /* | |
305 | xircom_remove is called on module-unload or on device-eject. | |
306 | it unregisters the irq, io-region and network device. | |
307 | Interrupts and such are already stopped in the "ifconfig ethX down" | |
308 | code. | |
309 | */ | |
779c1a85 | 310 | static void xircom_remove(struct pci_dev *pdev) |
1da177e4 LT |
311 | { |
312 | struct net_device *dev = pci_get_drvdata(pdev); | |
313 | struct xircom_private *card = netdev_priv(dev); | |
d59a1881 | 314 | struct device *d = &pdev->dev; |
1da177e4 | 315 | |
1da177e4 | 316 | unregister_netdev(dev); |
ebaf7f8f | 317 | pci_iounmap(pdev, card->ioaddr); |
d59a1881 FR |
318 | dma_free_coherent(d, 8192, card->tx_buffer, card->tx_dma_handle); |
319 | dma_free_coherent(d, 8192, card->rx_buffer, card->rx_dma_handle); | |
320 | free_netdev(dev); | |
321 | pci_release_regions(pdev); | |
322 | pci_disable_device(pdev); | |
f3b197ac | 323 | } |
1da177e4 | 324 | |
7d12e780 | 325 | static irqreturn_t xircom_interrupt(int irq, void *dev_instance) |
1da177e4 LT |
326 | { |
327 | struct net_device *dev = (struct net_device *) dev_instance; | |
328 | struct xircom_private *card = netdev_priv(dev); | |
ebaf7f8f | 329 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 LT |
330 | unsigned int status; |
331 | int i; | |
332 | ||
1da177e4 | 333 | spin_lock(&card->lock); |
ebaf7f8f | 334 | status = xr32(CSR5); |
1da177e4 | 335 | |
54668b84 | 336 | #if defined DEBUG && DEBUG > 1 |
1da177e4 | 337 | print_binary(status); |
54668b84 JP |
338 | pr_debug("tx status 0x%08x 0x%08x\n", |
339 | card->tx_buffer[0], card->tx_buffer[4]); | |
340 | pr_debug("rx status 0x%08x 0x%08x\n", | |
341 | card->rx_buffer[0], card->rx_buffer[4]); | |
f3b197ac | 342 | #endif |
1da177e4 LT |
343 | /* Handle shared irq and hotplug */ |
344 | if (status == 0 || status == 0xffffffff) { | |
345 | spin_unlock(&card->lock); | |
346 | return IRQ_NONE; | |
347 | } | |
348 | ||
349 | if (link_status_changed(card)) { | |
350 | int newlink; | |
726b65ad | 351 | netdev_dbg(dev, "Link status has changed\n"); |
1da177e4 | 352 | newlink = link_status(card); |
163ef0b5 | 353 | netdev_info(dev, "Link is %d mbit\n", newlink); |
1da177e4 LT |
354 | if (newlink) |
355 | netif_carrier_on(dev); | |
356 | else | |
357 | netif_carrier_off(dev); | |
f3b197ac | 358 | |
1da177e4 LT |
359 | } |
360 | ||
f3b197ac | 361 | /* Clear all remaining interrupts */ |
1da177e4 LT |
362 | status |= 0xffffffff; /* FIXME: make this clear only the |
363 | real existing bits */ | |
ebaf7f8f | 364 | xw32(CSR5, status); |
1da177e4 | 365 | |
f3b197ac JG |
366 | |
367 | for (i=0;i<NUMDESCRIPTORS;i++) | |
1da177e4 | 368 | investigate_write_descriptor(dev,card,i,bufferoffsets[i]); |
f3b197ac | 369 | for (i=0;i<NUMDESCRIPTORS;i++) |
1da177e4 LT |
370 | investigate_read_descriptor(dev,card,i,bufferoffsets[i]); |
371 | ||
1da177e4 | 372 | spin_unlock(&card->lock); |
1da177e4 LT |
373 | return IRQ_HANDLED; |
374 | } | |
375 | ||
ad096463 SH |
376 | static netdev_tx_t xircom_start_xmit(struct sk_buff *skb, |
377 | struct net_device *dev) | |
1da177e4 LT |
378 | { |
379 | struct xircom_private *card; | |
380 | unsigned long flags; | |
381 | int nextdescriptor; | |
382 | int desc; | |
f3b197ac | 383 | |
1da177e4 LT |
384 | card = netdev_priv(dev); |
385 | spin_lock_irqsave(&card->lock,flags); | |
f3b197ac | 386 | |
1da177e4 | 387 | /* First see if we can free some descriptors */ |
f3b197ac | 388 | for (desc=0;desc<NUMDESCRIPTORS;desc++) |
1da177e4 | 389 | investigate_write_descriptor(dev,card,desc,bufferoffsets[desc]); |
f3b197ac JG |
390 | |
391 | ||
1da177e4 LT |
392 | nextdescriptor = (card->transmit_used +1) % (NUMDESCRIPTORS); |
393 | desc = card->transmit_used; | |
f3b197ac | 394 | |
1da177e4 LT |
395 | /* only send the packet if the descriptor is free */ |
396 | if (card->tx_buffer[4*desc]==0) { | |
397 | /* Copy the packet data; zero the memory first as the card | |
398 | sometimes sends more than you ask it to. */ | |
f3b197ac | 399 | |
1da177e4 | 400 | memset(&card->tx_buffer[bufferoffsets[desc]/4],0,1536); |
d626f62b ACM |
401 | skb_copy_from_linear_data(skb, |
402 | &(card->tx_buffer[bufferoffsets[desc] / 4]), | |
403 | skb->len); | |
1da177e4 LT |
404 | /* FIXME: The specification tells us that the length we send HAS to be a multiple of |
405 | 4 bytes. */ | |
f3b197ac | 406 | |
6f35d5d5 AV |
407 | card->tx_buffer[4*desc+1] = cpu_to_le32(skb->len); |
408 | if (desc == NUMDESCRIPTORS - 1) /* bit 25: last descriptor of the ring */ | |
409 | card->tx_buffer[4*desc+1] |= cpu_to_le32(1<<25); | |
1da177e4 | 410 | |
6f35d5d5 | 411 | card->tx_buffer[4*desc+1] |= cpu_to_le32(0xF0000000); |
f3b197ac | 412 | /* 0xF0... means want interrupts*/ |
1da177e4 | 413 | card->tx_skb[desc] = skb; |
f3b197ac | 414 | |
1da177e4 LT |
415 | wmb(); |
416 | /* This gives the descriptor to the card */ | |
6f35d5d5 | 417 | card->tx_buffer[4*desc] = cpu_to_le32(0x80000000); |
1da177e4 | 418 | trigger_transmit(card); |
6f35d5d5 AV |
419 | if (card->tx_buffer[nextdescriptor*4] & cpu_to_le32(0x8000000)) { |
420 | /* next descriptor is occupied... */ | |
1da177e4 LT |
421 | netif_stop_queue(dev); |
422 | } | |
423 | card->transmit_used = nextdescriptor; | |
1da177e4 | 424 | spin_unlock_irqrestore(&card->lock,flags); |
6ed10654 | 425 | return NETDEV_TX_OK; |
1da177e4 | 426 | } |
f3b197ac | 427 | |
1da177e4 LT |
428 | /* Uh oh... no free descriptor... drop the packet */ |
429 | netif_stop_queue(dev); | |
430 | spin_unlock_irqrestore(&card->lock,flags); | |
431 | trigger_transmit(card); | |
f3b197ac | 432 | |
06f7525b | 433 | return NETDEV_TX_BUSY; |
1da177e4 LT |
434 | } |
435 | ||
436 | ||
437 | ||
438 | ||
439 | static int xircom_open(struct net_device *dev) | |
440 | { | |
441 | struct xircom_private *xp = netdev_priv(dev); | |
ebaf7f8f | 442 | const int irq = xp->pdev->irq; |
1da177e4 | 443 | int retval; |
54668b84 | 444 | |
ebaf7f8f FR |
445 | netdev_info(dev, "xircom cardbus adaptor found, using irq %i\n", irq); |
446 | retval = request_irq(irq, xircom_interrupt, IRQF_SHARED, dev->name, dev); | |
54668b84 | 447 | if (retval) |
1da177e4 | 448 | return retval; |
f3b197ac | 449 | |
1da177e4 LT |
450 | xircom_up(xp); |
451 | xp->open = 1; | |
54668b84 | 452 | |
1da177e4 LT |
453 | return 0; |
454 | } | |
455 | ||
456 | static int xircom_close(struct net_device *dev) | |
457 | { | |
458 | struct xircom_private *card; | |
459 | unsigned long flags; | |
f3b197ac | 460 | |
1da177e4 LT |
461 | card = netdev_priv(dev); |
462 | netif_stop_queue(dev); /* we don't want new packets */ | |
463 | ||
f3b197ac | 464 | |
1da177e4 | 465 | spin_lock_irqsave(&card->lock,flags); |
f3b197ac | 466 | |
1da177e4 | 467 | disable_all_interrupts(card); |
f3b197ac | 468 | #if 0 |
1da177e4 LT |
469 | /* We can enable this again once we send dummy packets on ifconfig ethX up */ |
470 | deactivate_receiver(card); | |
471 | deactivate_transmitter(card); | |
f3b197ac | 472 | #endif |
1da177e4 | 473 | remove_descriptors(card); |
f3b197ac | 474 | |
1da177e4 | 475 | spin_unlock_irqrestore(&card->lock,flags); |
f3b197ac | 476 | |
1da177e4 | 477 | card->open = 0; |
ebaf7f8f | 478 | free_irq(card->pdev->irq, dev); |
f3b197ac | 479 | |
1da177e4 | 480 | return 0; |
f3b197ac | 481 | |
1da177e4 LT |
482 | } |
483 | ||
484 | ||
1da177e4 LT |
485 | #ifdef CONFIG_NET_POLL_CONTROLLER |
486 | static void xircom_poll_controller(struct net_device *dev) | |
487 | { | |
ebaf7f8f FR |
488 | struct xircom_private *xp = netdev_priv(dev); |
489 | const int irq = xp->pdev->irq; | |
490 | ||
491 | disable_irq(irq); | |
492 | xircom_interrupt(irq, dev); | |
493 | enable_irq(irq); | |
1da177e4 LT |
494 | } |
495 | #endif | |
496 | ||
497 | ||
498 | static void initialize_card(struct xircom_private *card) | |
499 | { | |
ebaf7f8f | 500 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 501 | unsigned long flags; |
ebaf7f8f | 502 | u32 val; |
1da177e4 LT |
503 | |
504 | spin_lock_irqsave(&card->lock, flags); | |
505 | ||
506 | /* First: reset the card */ | |
ebaf7f8f | 507 | val = xr32(CSR0); |
1da177e4 | 508 | val |= 0x01; /* Software reset */ |
ebaf7f8f | 509 | xw32(CSR0, val); |
1da177e4 LT |
510 | |
511 | udelay(100); /* give the card some time to reset */ | |
512 | ||
ebaf7f8f | 513 | val = xr32(CSR0); |
1da177e4 | 514 | val &= ~0x01; /* disable Software reset */ |
ebaf7f8f | 515 | xw32(CSR0, val); |
1da177e4 LT |
516 | |
517 | ||
f3b197ac | 518 | val = 0; /* Value 0x00 is a safe and conservative value |
1da177e4 | 519 | for the PCI configuration settings */ |
ebaf7f8f | 520 | xw32(CSR0, val); |
1da177e4 LT |
521 | |
522 | ||
523 | disable_all_interrupts(card); | |
524 | deactivate_receiver(card); | |
525 | deactivate_transmitter(card); | |
526 | ||
527 | spin_unlock_irqrestore(&card->lock, flags); | |
1da177e4 LT |
528 | } |
529 | ||
530 | /* | |
531 | trigger_transmit causes the card to check for frames to be transmitted. | |
532 | This is accomplished by writing to the CSR1 port. The documentation | |
533 | claims that the act of writing is sufficient and that the value is | |
534 | ignored; I chose zero. | |
535 | */ | |
536 | static void trigger_transmit(struct xircom_private *card) | |
537 | { | |
ebaf7f8f | 538 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 539 | |
ebaf7f8f | 540 | xw32(CSR1, 0); |
1da177e4 LT |
541 | } |
542 | ||
543 | /* | |
544 | trigger_receive causes the card to check for empty frames in the | |
545 | descriptor list in which packets can be received. | |
546 | This is accomplished by writing to the CSR2 port. The documentation | |
547 | claims that the act of writing is sufficient and that the value is | |
548 | ignored; I chose zero. | |
549 | */ | |
550 | static void trigger_receive(struct xircom_private *card) | |
551 | { | |
ebaf7f8f | 552 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 553 | |
ebaf7f8f | 554 | xw32(CSR2, 0); |
1da177e4 LT |
555 | } |
556 | ||
557 | /* | |
558 | setup_descriptors initializes the send and receive buffers to be valid | |
559 | descriptors and programs the addresses into the card. | |
560 | */ | |
561 | static void setup_descriptors(struct xircom_private *card) | |
562 | { | |
ebaf7f8f | 563 | void __iomem *ioaddr = card->ioaddr; |
6f35d5d5 | 564 | u32 address; |
1da177e4 | 565 | int i; |
1da177e4 | 566 | |
a707cd6e ES |
567 | BUG_ON(card->rx_buffer == NULL); |
568 | BUG_ON(card->tx_buffer == NULL); | |
1da177e4 LT |
569 | |
570 | /* Receive descriptors */ | |
571 | memset(card->rx_buffer, 0, 128); /* clear the descriptors */ | |
572 | for (i=0;i<NUMDESCRIPTORS;i++ ) { | |
573 | ||
574 | /* Rx Descr0: It's empty, let the card own it, no errors -> 0x80000000 */ | |
6f35d5d5 | 575 | card->rx_buffer[i*4 + 0] = cpu_to_le32(0x80000000); |
1da177e4 | 576 | /* Rx Descr1: buffer 1 is 1536 bytes, buffer 2 is 0 bytes */ |
6f35d5d5 AV |
577 | card->rx_buffer[i*4 + 1] = cpu_to_le32(1536); |
578 | if (i == NUMDESCRIPTORS - 1) /* bit 25 is "last descriptor" */ | |
579 | card->rx_buffer[i*4 + 1] |= cpu_to_le32(1 << 25); | |
1da177e4 LT |
580 | |
581 | /* Rx Descr2: address of the buffer | |
582 | we store the buffer at the 2nd half of the page */ | |
f3b197ac | 583 | |
6f35d5d5 | 584 | address = card->rx_dma_handle; |
1da177e4 LT |
585 | card->rx_buffer[i*4 + 2] = cpu_to_le32(address + bufferoffsets[i]); |
586 | /* Rx Desc3: address of 2nd buffer -> 0 */ | |
587 | card->rx_buffer[i*4 + 3] = 0; | |
588 | } | |
f3b197ac | 589 | |
1da177e4 LT |
590 | wmb(); |
591 | /* Write the receive descriptor ring address to the card */ | |
6f35d5d5 | 592 | address = card->rx_dma_handle; |
ebaf7f8f | 593 | xw32(CSR3, address); /* Receive descr list address */ |
1da177e4 LT |
594 | |
595 | ||
596 | /* transmit descriptors */ | |
597 | memset(card->tx_buffer, 0, 128); /* clear the descriptors */ | |
f3b197ac | 598 | |
1da177e4 LT |
599 | for (i=0;i<NUMDESCRIPTORS;i++ ) { |
600 | /* Tx Descr0: Empty, we own it, no errors -> 0x00000000 */ | |
601 | card->tx_buffer[i*4 + 0] = 0x00000000; | |
602 | /* Tx Descr1: buffer 1 is 1536 bytes, buffer 2 is 0 bytes */ | |
6f35d5d5 AV |
603 | card->tx_buffer[i*4 + 1] = cpu_to_le32(1536); |
604 | if (i == NUMDESCRIPTORS - 1) /* bit 25 is "last descriptor" */ | |
605 | card->tx_buffer[i*4 + 1] |= cpu_to_le32(1 << 25); | |
f3b197ac | 606 | |
1da177e4 LT |
607 | /* Tx Descr2: address of the buffer |
608 | we store the buffer at the 2nd half of the page */ | |
6f35d5d5 | 609 | address = card->tx_dma_handle; |
1da177e4 LT |
610 | card->tx_buffer[i*4 + 2] = cpu_to_le32(address + bufferoffsets[i]); |
611 | /* Tx Desc3: address of 2nd buffer -> 0 */ | |
612 | card->tx_buffer[i*4 + 3] = 0; | |
613 | } | |
614 | ||
615 | wmb(); | |
616 | /* wite the transmit descriptor ring to the card */ | |
6f35d5d5 | 617 | address = card->tx_dma_handle; |
ebaf7f8f | 618 | xw32(CSR4, address); /* xmit descr list address */ |
1da177e4 LT |
619 | } |
620 | ||
621 | /* | |
622 | remove_descriptors informs the card the descriptors are no longer | |
623 | valid by setting the address in the card to 0x00. | |
624 | */ | |
625 | static void remove_descriptors(struct xircom_private *card) | |
626 | { | |
ebaf7f8f | 627 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 628 | unsigned int val; |
1da177e4 LT |
629 | |
630 | val = 0; | |
ebaf7f8f FR |
631 | xw32(CSR3, val); /* Receive descriptor address */ |
632 | xw32(CSR4, val); /* Send descriptor address */ | |
1da177e4 LT |
633 | } |
634 | ||
635 | /* | |
636 | link_status_changed returns 1 if the card has indicated that | |
637 | the link status has changed. The new link status has to be read from CSR12. | |
638 | ||
639 | This function also clears the status-bit. | |
640 | */ | |
641 | static int link_status_changed(struct xircom_private *card) | |
642 | { | |
ebaf7f8f | 643 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 644 | unsigned int val; |
1da177e4 | 645 | |
ebaf7f8f FR |
646 | val = xr32(CSR5); /* Status register */ |
647 | if (!(val & (1 << 27))) /* no change */ | |
1da177e4 | 648 | return 0; |
1da177e4 LT |
649 | |
650 | /* clear the event by writing a 1 to the bit in the | |
651 | status register. */ | |
652 | val = (1 << 27); | |
ebaf7f8f | 653 | xw32(CSR5, val); |
1da177e4 | 654 | |
1da177e4 LT |
655 | return 1; |
656 | } | |
657 | ||
658 | ||
659 | /* | |
660 | transmit_active returns 1 if the transmitter on the card is | |
661 | in a non-stopped state. | |
662 | */ | |
663 | static int transmit_active(struct xircom_private *card) | |
664 | { | |
ebaf7f8f | 665 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 666 | |
ebaf7f8f | 667 | if (!(xr32(CSR5) & (7 << 20))) /* transmitter disabled */ |
1da177e4 | 668 | return 0; |
1da177e4 | 669 | |
1da177e4 LT |
670 | return 1; |
671 | } | |
672 | ||
673 | /* | |
674 | receive_active returns 1 if the receiver on the card is | |
675 | in a non-stopped state. | |
676 | */ | |
677 | static int receive_active(struct xircom_private *card) | |
678 | { | |
ebaf7f8f | 679 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 680 | |
ebaf7f8f | 681 | if (!(xr32(CSR5) & (7 << 17))) /* receiver disabled */ |
1da177e4 | 682 | return 0; |
1da177e4 | 683 | |
1da177e4 LT |
684 | return 1; |
685 | } | |
686 | ||
687 | /* | |
688 | activate_receiver enables the receiver on the card. | |
689 | Before being allowed to active the receiver, the receiver | |
690 | must be completely de-activated. To achieve this, | |
f3b197ac | 691 | this code actually disables the receiver first; then it waits for the |
1da177e4 LT |
692 | receiver to become inactive, then it activates the receiver and then |
693 | it waits for the receiver to be active. | |
694 | ||
695 | must be called with the lock held and interrupts disabled. | |
696 | */ | |
697 | static void activate_receiver(struct xircom_private *card) | |
698 | { | |
ebaf7f8f | 699 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 LT |
700 | unsigned int val; |
701 | int counter; | |
1da177e4 | 702 | |
ebaf7f8f | 703 | val = xr32(CSR6); /* Operation mode */ |
f3b197ac | 704 | |
1da177e4 LT |
705 | /* If the "active" bit is set and the receiver is already |
706 | active, no need to do the expensive thing */ | |
707 | if ((val&2) && (receive_active(card))) | |
708 | return; | |
f3b197ac JG |
709 | |
710 | ||
1da177e4 | 711 | val = val & ~2; /* disable the receiver */ |
ebaf7f8f | 712 | xw32(CSR6, val); |
1da177e4 LT |
713 | |
714 | counter = 10; | |
715 | while (counter > 0) { | |
716 | if (!receive_active(card)) | |
717 | break; | |
718 | /* wait a while */ | |
719 | udelay(50); | |
720 | counter--; | |
721 | if (counter <= 0) | |
163ef0b5 | 722 | netdev_err(card->dev, "Receiver failed to deactivate\n"); |
1da177e4 LT |
723 | } |
724 | ||
725 | /* enable the receiver */ | |
ebaf7f8f FR |
726 | val = xr32(CSR6); /* Operation mode */ |
727 | val = val | 2; /* enable the receiver */ | |
728 | xw32(CSR6, val); | |
1da177e4 LT |
729 | |
730 | /* now wait for the card to activate again */ | |
731 | counter = 10; | |
732 | while (counter > 0) { | |
733 | if (receive_active(card)) | |
734 | break; | |
735 | /* wait a while */ | |
736 | udelay(50); | |
737 | counter--; | |
738 | if (counter <= 0) | |
163ef0b5 JP |
739 | netdev_err(card->dev, |
740 | "Receiver failed to re-activate\n"); | |
1da177e4 | 741 | } |
1da177e4 LT |
742 | } |
743 | ||
744 | /* | |
745 | deactivate_receiver disables the receiver on the card. | |
f3b197ac | 746 | To achieve this this code disables the receiver first; |
1da177e4 LT |
747 | then it waits for the receiver to become inactive. |
748 | ||
749 | must be called with the lock held and interrupts disabled. | |
750 | */ | |
751 | static void deactivate_receiver(struct xircom_private *card) | |
752 | { | |
ebaf7f8f | 753 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 LT |
754 | unsigned int val; |
755 | int counter; | |
1da177e4 | 756 | |
ebaf7f8f FR |
757 | val = xr32(CSR6); /* Operation mode */ |
758 | val = val & ~2; /* disable the receiver */ | |
759 | xw32(CSR6, val); | |
1da177e4 LT |
760 | |
761 | counter = 10; | |
762 | while (counter > 0) { | |
763 | if (!receive_active(card)) | |
764 | break; | |
765 | /* wait a while */ | |
766 | udelay(50); | |
767 | counter--; | |
768 | if (counter <= 0) | |
163ef0b5 | 769 | netdev_err(card->dev, "Receiver failed to deactivate\n"); |
1da177e4 | 770 | } |
1da177e4 LT |
771 | } |
772 | ||
773 | ||
774 | /* | |
775 | activate_transmitter enables the transmitter on the card. | |
776 | Before being allowed to active the transmitter, the transmitter | |
777 | must be completely de-activated. To achieve this, | |
f3b197ac | 778 | this code actually disables the transmitter first; then it waits for the |
1da177e4 LT |
779 | transmitter to become inactive, then it activates the transmitter and then |
780 | it waits for the transmitter to be active again. | |
781 | ||
782 | must be called with the lock held and interrupts disabled. | |
783 | */ | |
784 | static void activate_transmitter(struct xircom_private *card) | |
785 | { | |
ebaf7f8f | 786 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 LT |
787 | unsigned int val; |
788 | int counter; | |
1da177e4 | 789 | |
ebaf7f8f | 790 | val = xr32(CSR6); /* Operation mode */ |
1da177e4 LT |
791 | |
792 | /* If the "active" bit is set and the receiver is already | |
f3b197ac | 793 | active, no need to do the expensive thing */ |
1da177e4 LT |
794 | if ((val&(1<<13)) && (transmit_active(card))) |
795 | return; | |
796 | ||
797 | val = val & ~(1 << 13); /* disable the transmitter */ | |
ebaf7f8f | 798 | xw32(CSR6, val); |
1da177e4 LT |
799 | |
800 | counter = 10; | |
801 | while (counter > 0) { | |
802 | if (!transmit_active(card)) | |
803 | break; | |
804 | /* wait a while */ | |
805 | udelay(50); | |
806 | counter--; | |
807 | if (counter <= 0) | |
163ef0b5 JP |
808 | netdev_err(card->dev, |
809 | "Transmitter failed to deactivate\n"); | |
1da177e4 LT |
810 | } |
811 | ||
812 | /* enable the transmitter */ | |
ebaf7f8f | 813 | val = xr32(CSR6); /* Operation mode */ |
1da177e4 | 814 | val = val | (1 << 13); /* enable the transmitter */ |
ebaf7f8f | 815 | xw32(CSR6, val); |
1da177e4 LT |
816 | |
817 | /* now wait for the card to activate again */ | |
818 | counter = 10; | |
819 | while (counter > 0) { | |
820 | if (transmit_active(card)) | |
821 | break; | |
822 | /* wait a while */ | |
823 | udelay(50); | |
824 | counter--; | |
825 | if (counter <= 0) | |
163ef0b5 JP |
826 | netdev_err(card->dev, |
827 | "Transmitter failed to re-activate\n"); | |
1da177e4 | 828 | } |
1da177e4 LT |
829 | } |
830 | ||
831 | /* | |
832 | deactivate_transmitter disables the transmitter on the card. | |
f3b197ac | 833 | To achieve this this code disables the transmitter first; |
1da177e4 LT |
834 | then it waits for the transmitter to become inactive. |
835 | ||
836 | must be called with the lock held and interrupts disabled. | |
837 | */ | |
838 | static void deactivate_transmitter(struct xircom_private *card) | |
839 | { | |
ebaf7f8f | 840 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 LT |
841 | unsigned int val; |
842 | int counter; | |
1da177e4 | 843 | |
ebaf7f8f | 844 | val = xr32(CSR6); /* Operation mode */ |
1da177e4 | 845 | val = val & ~2; /* disable the transmitter */ |
ebaf7f8f | 846 | xw32(CSR6, val); |
1da177e4 LT |
847 | |
848 | counter = 20; | |
849 | while (counter > 0) { | |
850 | if (!transmit_active(card)) | |
851 | break; | |
852 | /* wait a while */ | |
853 | udelay(50); | |
854 | counter--; | |
855 | if (counter <= 0) | |
163ef0b5 JP |
856 | netdev_err(card->dev, |
857 | "Transmitter failed to deactivate\n"); | |
1da177e4 | 858 | } |
1da177e4 LT |
859 | } |
860 | ||
861 | ||
862 | /* | |
863 | enable_transmit_interrupt enables the transmit interrupt | |
864 | ||
865 | must be called with the lock held and interrupts disabled. | |
866 | */ | |
867 | static void enable_transmit_interrupt(struct xircom_private *card) | |
868 | { | |
ebaf7f8f | 869 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 870 | unsigned int val; |
1da177e4 | 871 | |
ebaf7f8f FR |
872 | val = xr32(CSR7); /* Interrupt enable register */ |
873 | val |= 1; /* enable the transmit interrupt */ | |
874 | xw32(CSR7, val); | |
1da177e4 LT |
875 | } |
876 | ||
877 | ||
878 | /* | |
879 | enable_receive_interrupt enables the receive interrupt | |
880 | ||
881 | must be called with the lock held and interrupts disabled. | |
882 | */ | |
883 | static void enable_receive_interrupt(struct xircom_private *card) | |
884 | { | |
ebaf7f8f | 885 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 886 | unsigned int val; |
1da177e4 | 887 | |
ebaf7f8f FR |
888 | val = xr32(CSR7); /* Interrupt enable register */ |
889 | val = val | (1 << 6); /* enable the receive interrupt */ | |
890 | xw32(CSR7, val); | |
1da177e4 LT |
891 | } |
892 | ||
893 | /* | |
894 | enable_link_interrupt enables the link status change interrupt | |
895 | ||
896 | must be called with the lock held and interrupts disabled. | |
897 | */ | |
898 | static void enable_link_interrupt(struct xircom_private *card) | |
899 | { | |
ebaf7f8f | 900 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 901 | unsigned int val; |
1da177e4 | 902 | |
ebaf7f8f FR |
903 | val = xr32(CSR7); /* Interrupt enable register */ |
904 | val = val | (1 << 27); /* enable the link status chage interrupt */ | |
905 | xw32(CSR7, val); | |
1da177e4 LT |
906 | } |
907 | ||
908 | ||
909 | ||
910 | /* | |
911 | disable_all_interrupts disables all interrupts | |
912 | ||
913 | must be called with the lock held and interrupts disabled. | |
914 | */ | |
915 | static void disable_all_interrupts(struct xircom_private *card) | |
916 | { | |
ebaf7f8f | 917 | void __iomem *ioaddr = card->ioaddr; |
f3b197ac | 918 | |
ebaf7f8f | 919 | xw32(CSR7, 0); |
1da177e4 LT |
920 | } |
921 | ||
922 | /* | |
923 | enable_common_interrupts enables several weird interrupts | |
924 | ||
925 | must be called with the lock held and interrupts disabled. | |
926 | */ | |
927 | static void enable_common_interrupts(struct xircom_private *card) | |
928 | { | |
ebaf7f8f | 929 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 930 | unsigned int val; |
1da177e4 | 931 | |
ebaf7f8f | 932 | val = xr32(CSR7); /* Interrupt enable register */ |
1da177e4 LT |
933 | val |= (1<<16); /* Normal Interrupt Summary */ |
934 | val |= (1<<15); /* Abnormal Interrupt Summary */ | |
935 | val |= (1<<13); /* Fatal bus error */ | |
936 | val |= (1<<8); /* Receive Process Stopped */ | |
937 | val |= (1<<7); /* Receive Buffer Unavailable */ | |
938 | val |= (1<<5); /* Transmit Underflow */ | |
939 | val |= (1<<2); /* Transmit Buffer Unavailable */ | |
940 | val |= (1<<1); /* Transmit Process Stopped */ | |
ebaf7f8f | 941 | xw32(CSR7, val); |
1da177e4 LT |
942 | } |
943 | ||
944 | /* | |
945 | enable_promisc starts promisc mode | |
946 | ||
947 | must be called with the lock held and interrupts disabled. | |
948 | */ | |
949 | static int enable_promisc(struct xircom_private *card) | |
950 | { | |
ebaf7f8f | 951 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 952 | unsigned int val; |
1da177e4 | 953 | |
ebaf7f8f | 954 | val = xr32(CSR6); |
f3b197ac | 955 | val = val | (1 << 6); |
ebaf7f8f | 956 | xw32(CSR6, val); |
1da177e4 | 957 | |
1da177e4 LT |
958 | return 1; |
959 | } | |
960 | ||
961 | ||
962 | ||
963 | ||
f3b197ac | 964 | /* |
59c51591 | 965 | link_status() checks the links status and will return 0 for no link, 10 for 10mbit link and 100 for.. guess what. |
1da177e4 LT |
966 | |
967 | Must be called in locked state with interrupts disabled | |
968 | */ | |
969 | static int link_status(struct xircom_private *card) | |
970 | { | |
ebaf7f8f FR |
971 | void __iomem *ioaddr = card->ioaddr; |
972 | u8 val; | |
f3b197ac | 973 | |
ebaf7f8f | 974 | val = xr8(CSR12); |
f3b197ac | 975 | |
ebaf7f8f FR |
976 | /* bit 2 is 0 for 10mbit link, 1 for not an 10mbit link */ |
977 | if (!(val & (1 << 2))) | |
1da177e4 | 978 | return 10; |
ebaf7f8f FR |
979 | /* bit 1 is 0 for 100mbit link, 1 for not an 100mbit link */ |
980 | if (!(val & (1 << 1))) | |
1da177e4 | 981 | return 100; |
f3b197ac JG |
982 | |
983 | /* If we get here -> no link at all */ | |
1da177e4 | 984 | |
1da177e4 LT |
985 | return 0; |
986 | } | |
987 | ||
988 | ||
989 | ||
990 | ||
991 | ||
992 | /* | |
993 | read_mac_address() reads the MAC address from the NIC and stores it in the "dev" structure. | |
f3b197ac | 994 | |
1da177e4 LT |
995 | This function will take the spinlock itself and can, as a result, not be called with the lock helt. |
996 | */ | |
997 | static void read_mac_address(struct xircom_private *card) | |
998 | { | |
ebaf7f8f | 999 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 | 1000 | unsigned long flags; |
ebaf7f8f | 1001 | u8 link; |
1da177e4 LT |
1002 | int i; |
1003 | ||
1da177e4 LT |
1004 | spin_lock_irqsave(&card->lock, flags); |
1005 | ||
ebaf7f8f | 1006 | xw32(CSR9, 1 << 12); /* enable boot rom access */ |
1da177e4 | 1007 | for (i = 0x100; i < 0x1f7; i += link + 2) { |
ebaf7f8f FR |
1008 | u8 tuple, data_id, data_count; |
1009 | ||
1010 | xw32(CSR10, i); | |
1011 | tuple = xr32(CSR9); | |
1012 | xw32(CSR10, i + 1); | |
1013 | link = xr32(CSR9); | |
1014 | xw32(CSR10, i + 2); | |
1015 | data_id = xr32(CSR9); | |
1016 | xw32(CSR10, i + 3); | |
1017 | data_count = xr32(CSR9); | |
1da177e4 | 1018 | if ((tuple == 0x22) && (data_id == 0x04) && (data_count == 0x06)) { |
ebaf7f8f FR |
1019 | int j; |
1020 | ||
1da177e4 | 1021 | for (j = 0; j < 6; j++) { |
ebaf7f8f FR |
1022 | xw32(CSR10, i + j + 4); |
1023 | card->dev->dev_addr[j] = xr32(CSR9) & 0xff; | |
1da177e4 LT |
1024 | } |
1025 | break; | |
1026 | } else if (link == 0) { | |
1027 | break; | |
1028 | } | |
1029 | } | |
1030 | spin_unlock_irqrestore(&card->lock, flags); | |
e174961c | 1031 | pr_debug(" %pM\n", card->dev->dev_addr); |
1da177e4 LT |
1032 | } |
1033 | ||
1034 | ||
1035 | /* | |
1036 | transceiver_voodoo() enables the external UTP plug thingy. | |
1037 | it's called voodoo as I stole this code and cannot cross-reference | |
1038 | it with the specification. | |
1039 | */ | |
1040 | static void transceiver_voodoo(struct xircom_private *card) | |
1041 | { | |
ebaf7f8f | 1042 | void __iomem *ioaddr = card->ioaddr; |
1da177e4 LT |
1043 | unsigned long flags; |
1044 | ||
1da177e4 LT |
1045 | /* disable all powermanagement */ |
1046 | pci_write_config_dword(card->pdev, PCI_POWERMGMT, 0x0000); | |
1047 | ||
1048 | setup_descriptors(card); | |
1049 | ||
1050 | spin_lock_irqsave(&card->lock, flags); | |
1051 | ||
ebaf7f8f FR |
1052 | xw32(CSR15, 0x0008); |
1053 | udelay(25); | |
1054 | xw32(CSR15, 0xa8050000); | |
1055 | udelay(25); | |
1056 | xw32(CSR15, 0xa00f0000); | |
1057 | udelay(25); | |
f3b197ac | 1058 | |
ebaf7f8f | 1059 | spin_unlock_irqrestore(&card->lock, flags); |
1da177e4 LT |
1060 | |
1061 | netif_start_queue(card->dev); | |
1da177e4 LT |
1062 | } |
1063 | ||
1064 | ||
1065 | static void xircom_up(struct xircom_private *card) | |
1066 | { | |
1067 | unsigned long flags; | |
1068 | int i; | |
1069 | ||
1da177e4 LT |
1070 | /* disable all powermanagement */ |
1071 | pci_write_config_dword(card->pdev, PCI_POWERMGMT, 0x0000); | |
1072 | ||
1073 | setup_descriptors(card); | |
1074 | ||
1075 | spin_lock_irqsave(&card->lock, flags); | |
1076 | ||
f3b197ac | 1077 | |
1da177e4 LT |
1078 | enable_link_interrupt(card); |
1079 | enable_transmit_interrupt(card); | |
1080 | enable_receive_interrupt(card); | |
1081 | enable_common_interrupts(card); | |
1082 | enable_promisc(card); | |
f3b197ac | 1083 | |
1da177e4 | 1084 | /* The card can have received packets already, read them away now */ |
f3b197ac | 1085 | for (i=0;i<NUMDESCRIPTORS;i++) |
1da177e4 LT |
1086 | investigate_read_descriptor(card->dev,card,i,bufferoffsets[i]); |
1087 | ||
1088 | ||
1089 | spin_unlock_irqrestore(&card->lock, flags); | |
1090 | trigger_receive(card); | |
1091 | trigger_transmit(card); | |
1092 | netif_start_queue(card->dev); | |
1da177e4 LT |
1093 | } |
1094 | ||
1095 | /* Bufferoffset is in BYTES */ | |
163ef0b5 JP |
1096 | static void |
1097 | investigate_read_descriptor(struct net_device *dev, struct xircom_private *card, | |
1098 | int descnr, unsigned int bufferoffset) | |
1da177e4 | 1099 | { |
163ef0b5 | 1100 | int status; |
f3b197ac | 1101 | |
163ef0b5 | 1102 | status = le32_to_cpu(card->rx_buffer[4*descnr]); |
f3b197ac | 1103 | |
163ef0b5 | 1104 | if (status > 0) { /* packet received */ |
f3b197ac | 1105 | |
163ef0b5 | 1106 | /* TODO: discard error packets */ |
f3b197ac | 1107 | |
163ef0b5 JP |
1108 | short pkt_len = ((status >> 16) & 0x7ff) - 4; |
1109 | /* minus 4, we don't want the CRC */ | |
1110 | struct sk_buff *skb; | |
1da177e4 | 1111 | |
163ef0b5 JP |
1112 | if (pkt_len > 1518) { |
1113 | netdev_err(dev, "Packet length %i is bogus\n", pkt_len); | |
1114 | pkt_len = 1518; | |
1115 | } | |
1da177e4 | 1116 | |
21a4e469 | 1117 | skb = netdev_alloc_skb(dev, pkt_len + 2); |
163ef0b5 JP |
1118 | if (skb == NULL) { |
1119 | dev->stats.rx_dropped++; | |
1120 | goto out; | |
1da177e4 | 1121 | } |
163ef0b5 JP |
1122 | skb_reserve(skb, 2); |
1123 | skb_copy_to_linear_data(skb, | |
1124 | &card->rx_buffer[bufferoffset / 4], | |
1125 | pkt_len); | |
1126 | skb_put(skb, pkt_len); | |
1127 | skb->protocol = eth_type_trans(skb, dev); | |
1128 | netif_rx(skb); | |
1129 | dev->stats.rx_packets++; | |
1130 | dev->stats.rx_bytes += pkt_len; | |
1131 | ||
1132 | out: | |
1133 | /* give the buffer back to the card */ | |
1134 | card->rx_buffer[4*descnr] = cpu_to_le32(0x80000000); | |
1135 | trigger_receive(card); | |
1136 | } | |
1da177e4 LT |
1137 | } |
1138 | ||
1139 | ||
1140 | /* Bufferoffset is in BYTES */ | |
163ef0b5 JP |
1141 | static void |
1142 | investigate_write_descriptor(struct net_device *dev, | |
1143 | struct xircom_private *card, | |
1144 | int descnr, unsigned int bufferoffset) | |
1da177e4 | 1145 | { |
163ef0b5 | 1146 | int status; |
1da177e4 | 1147 | |
163ef0b5 | 1148 | status = le32_to_cpu(card->tx_buffer[4*descnr]); |
f3b197ac | 1149 | #if 0 |
163ef0b5 JP |
1150 | if (status & 0x8000) { /* Major error */ |
1151 | pr_err("Major transmit error status %x\n", status); | |
1152 | card->tx_buffer[4*descnr] = 0; | |
1153 | netif_wake_queue (dev); | |
1154 | } | |
1da177e4 | 1155 | #endif |
163ef0b5 JP |
1156 | if (status > 0) { /* bit 31 is 0 when done */ |
1157 | if (card->tx_skb[descnr]!=NULL) { | |
1158 | dev->stats.tx_bytes += card->tx_skb[descnr]->len; | |
1159 | dev_kfree_skb_irq(card->tx_skb[descnr]); | |
1da177e4 | 1160 | } |
163ef0b5 JP |
1161 | card->tx_skb[descnr] = NULL; |
1162 | /* Bit 8 in the status field is 1 if there was a collision */ | |
1163 | if (status & (1 << 8)) | |
1164 | dev->stats.collisions++; | |
1165 | card->tx_buffer[4*descnr] = 0; /* descriptor is free again */ | |
1166 | netif_wake_queue (dev); | |
1167 | dev->stats.tx_packets++; | |
1168 | } | |
1da177e4 LT |
1169 | } |
1170 | ||
31d60ebf | 1171 | module_pci_driver(xircom_ops); |