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Merge tag 'v4.4-rockchip-dts32-fixes1' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / dlink / dl2k.c
CommitLineData
1da177e4
LT		 1/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2/*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11*/
1da177e4 12
df950828
K		 13#define DRV_NAME "DL2000/TC902x-based linux driver"
14#define DRV_VERSION "v1.19"
15#define DRV_RELDATE "2007/08/12"
1da177e4 16#include "dl2k.h"
c4694c76 17#include <linux/dma-mapping.h>
1da177e4 18
5e3cc4e3
FR		 19#define dw32(reg, val) iowrite32(val, ioaddr + (reg))
20#define dw16(reg, val) iowrite16(val, ioaddr + (reg))
21#define dw8(reg, val) iowrite8(val, ioaddr + (reg))
22#define dr32(reg) ioread32(ioaddr + (reg))
23#define dr16(reg) ioread16(ioaddr + (reg))
24#define dr8(reg) ioread8(ioaddr + (reg))
25
64bc40de 26static char version[] =
6aa20a22 27 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
1da177e4
LT		 28#define MAX_UNITS 8
29static int mtu[MAX_UNITS];
30static int vlan[MAX_UNITS];
31static int jumbo[MAX_UNITS];
32static char *media[MAX_UNITS];
33static int tx_flow=-1;
34static int rx_flow=-1;
35static int copy_thresh;
36static int rx_coalesce=10; /* Rx frame count each interrupt */
37static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
38static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
39
40
41MODULE_AUTHOR ("Edward Peng");
42MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
43MODULE_LICENSE("GPL");
44module_param_array(mtu, int, NULL, 0);
45module_param_array(media, charp, NULL, 0);
46module_param_array(vlan, int, NULL, 0);
47module_param_array(jumbo, int, NULL, 0);
48module_param(tx_flow, int, 0);
49module_param(rx_flow, int, 0);
50module_param(copy_thresh, int, 0);
51module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
52module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
53module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
54
55
56/* Enable the default interrupts */
57#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
58 UpdateStats | LinkEvent)
5e3cc4e3
FR		 59
60static void dl2k_enable_int(struct netdev_private *np)
61{
62 void __iomem *ioaddr = np->ioaddr;
63
64 dw16(IntEnable, DEFAULT_INTR);
65}
1da177e4 66
f71e1309
AV		 67static const int max_intrloop = 50;
68static const int multicast_filter_limit = 0x40;
1da177e4
LT		 69
70static int rio_open (struct net_device *dev);
71static void rio_timer (unsigned long data);
72static void rio_tx_timeout (struct net_device *dev);
73static void alloc_list (struct net_device *dev);
61357325 74static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
7d12e780 75static irqreturn_t rio_interrupt (int irq, void *dev_instance);
1da177e4
LT		 76static void rio_free_tx (struct net_device *dev, int irq);
77static void tx_error (struct net_device *dev, int tx_status);
78static int receive_packet (struct net_device *dev);
79static void rio_error (struct net_device *dev, int int_status);
80static int change_mtu (struct net_device *dev, int new_mtu);
81static void set_multicast (struct net_device *dev);
82static struct net_device_stats *get_stats (struct net_device *dev);
83static int clear_stats (struct net_device *dev);
84static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
85static int rio_close (struct net_device *dev);
86static int find_miiphy (struct net_device *dev);
87static int parse_eeprom (struct net_device *dev);
5e3cc4e3 88static int read_eeprom (struct netdev_private *, int eep_addr);
1da177e4
LT		 89static int mii_wait_link (struct net_device *dev, int wait);
90static int mii_set_media (struct net_device *dev);
91static int mii_get_media (struct net_device *dev);
92static int mii_set_media_pcs (struct net_device *dev);
93static int mii_get_media_pcs (struct net_device *dev);
94static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
95static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
96 u16 data);
97
7282d491 98static const struct ethtool_ops ethtool_ops;
1da177e4 99
87652644
SH		 100static const struct net_device_ops netdev_ops = {
101 .ndo_open = rio_open,
102 .ndo_start_xmit = start_xmit,
103 .ndo_stop = rio_close,
104 .ndo_get_stats = get_stats,
105 .ndo_validate_addr = eth_validate_addr,
106 .ndo_set_mac_address = eth_mac_addr,
afc4b13d 107 .ndo_set_rx_mode = set_multicast,
87652644
SH		 108 .ndo_do_ioctl = rio_ioctl,
109 .ndo_tx_timeout = rio_tx_timeout,
110 .ndo_change_mtu = change_mtu,
111};
112
64bc40de 113static int
1da177e4
LT		 114rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
115{
116 struct net_device *dev;
117 struct netdev_private *np;
118 static int card_idx;
119 int chip_idx = ent->driver_data;
120 int err, irq;
5e3cc4e3 121 void __iomem *ioaddr;
1da177e4
LT		 122 static int version_printed;
123 void *ring_space;
124 dma_addr_t ring_dma;
125
126 if (!version_printed++)
127 printk ("%s", version);
128
129 err = pci_enable_device (pdev);
130 if (err)
131 return err;
132
133 irq = pdev->irq;
134 err = pci_request_regions (pdev, "dl2k");
135 if (err)
136 goto err_out_disable;
137
138 pci_set_master (pdev);
5e3cc4e3
FR		 139
140 err = -ENOMEM;
141
1da177e4 142 dev = alloc_etherdev (sizeof (*np));
5e3cc4e3 143 if (!dev)
1da177e4 144 goto err_out_res;
1da177e4
LT		 145 SET_NETDEV_DEV(dev, &pdev->dev);
146
5e3cc4e3
FR		 147 np = netdev_priv(dev);
148
149 /* IO registers range. */
150 ioaddr = pci_iomap(pdev, 0, 0);
151 if (!ioaddr)
1da177e4 152 goto err_out_dev;
5e3cc4e3
FR		 153 np->eeprom_addr = ioaddr;
154
155#ifdef MEM_MAPPING
156 /* MM registers range. */
157 ioaddr = pci_iomap(pdev, 1, 0);
158 if (!ioaddr)
159 goto err_out_iounmap;
1da177e4 160#endif
5e3cc4e3 161 np->ioaddr = ioaddr;
1da177e4
LT		 162 np->chip_id = chip_idx;
163 np->pdev = pdev;
164 spin_lock_init (&np->tx_lock);
165 spin_lock_init (&np->rx_lock);
166
167 /* Parse manual configuration */
168 np->an_enable = 1;
169 np->tx_coalesce = 1;
170 if (card_idx < MAX_UNITS) {
171 if (media[card_idx] != NULL) {
172 np->an_enable = 0;
173 if (strcmp (media[card_idx], "auto") == 0 ||
6aa20a22 174 strcmp (media[card_idx], "autosense") == 0 ||
1da177e4 175 strcmp (media[card_idx], "0") == 0 ) {
6aa20a22 176 np->an_enable = 2;
1da177e4
LT		 177 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
178 strcmp (media[card_idx], "4") == 0) {
179 np->speed = 100;
180 np->full_duplex = 1;
8e95a202
JP		 181 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
182 strcmp (media[card_idx], "3") == 0) {
1da177e4
LT		 183 np->speed = 100;
184 np->full_duplex = 0;
185 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
186 strcmp (media[card_idx], "2") == 0) {
187 np->speed = 10;
188 np->full_duplex = 1;
189 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
190 strcmp (media[card_idx], "1") == 0) {
191 np->speed = 10;
192 np->full_duplex = 0;
193 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
194 strcmp (media[card_idx], "6") == 0) {
195 np->speed=1000;
196 np->full_duplex=1;
197 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
198 strcmp (media[card_idx], "5") == 0) {
199 np->speed = 1000;
200 np->full_duplex = 0;
201 } else {
202 np->an_enable = 1;
203 }
204 }
205 if (jumbo[card_idx] != 0) {
206 np->jumbo = 1;
207 dev->mtu = MAX_JUMBO;
208 } else {
209 np->jumbo = 0;
210 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
211 dev->mtu = mtu[card_idx];
212 }
213 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
214 vlan[card_idx] : 0;
215 if (rx_coalesce > 0 && rx_timeout > 0) {
216 np->rx_coalesce = rx_coalesce;
217 np->rx_timeout = rx_timeout;
218 np->coalesce = 1;
219 }
220 np->tx_flow = (tx_flow == 0) ? 0 : 1;
221 np->rx_flow = (rx_flow == 0) ? 0 : 1;
222
223 if (tx_coalesce < 1)
224 tx_coalesce = 1;
225 else if (tx_coalesce > TX_RING_SIZE-1)
226 tx_coalesce = TX_RING_SIZE - 1;
227 }
87652644 228 dev->netdev_ops = &netdev_ops;
1da177e4 229 dev->watchdog_timeo = TX_TIMEOUT;
7ad24ea4 230 dev->ethtool_ops = &ethtool_ops;
1da177e4
LT		 231#if 0
232 dev->features = NETIF_F_IP_CSUM;
233#endif
234 pci_set_drvdata (pdev, dev);
235
236 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
237 if (!ring_space)
238 goto err_out_iounmap;
43d620c8 239 np->tx_ring = ring_space;
1da177e4
LT		 240 np->tx_ring_dma = ring_dma;
241
242 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
243 if (!ring_space)
244 goto err_out_unmap_tx;
43d620c8 245 np->rx_ring = ring_space;
1da177e4
LT		 246 np->rx_ring_dma = ring_dma;
247
248 /* Parse eeprom data */
249 parse_eeprom (dev);
250
251 /* Find PHY address */
252 err = find_miiphy (dev);
253 if (err)
254 goto err_out_unmap_rx;
6aa20a22 255
c3f45d32
OZ		 256 if (np->chip_id == CHIP_IP1000A &&
257 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
258 /* PHY magic taken from ipg driver, undocumented registers */
259 mii_write(dev, np->phy_addr, 31, 0x0001);
260 mii_write(dev, np->phy_addr, 27, 0x01e0);
261 mii_write(dev, np->phy_addr, 31, 0x0002);
262 mii_write(dev, np->phy_addr, 27, 0xeb8e);
263 mii_write(dev, np->phy_addr, 31, 0x0000);
264 mii_write(dev, np->phy_addr, 30, 0x005e);
265 /* advertise 1000BASE-T half & full duplex, prefer MASTER */
266 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
267 }
268
1da177e4 269 /* Fiber device? */
5e3cc4e3 270 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
1da177e4
LT		 271 np->link_status = 0;
272 /* Set media and reset PHY */
273 if (np->phy_media) {
274 /* default Auto-Negotiation for fiber deivices */
275 if (np->an_enable == 2) {
276 np->an_enable = 1;
277 }
278 mii_set_media_pcs (dev);
279 } else {
280 /* Auto-Negotiation is mandatory for 1000BASE-T,
281 IEEE 802.3ab Annex 28D page 14 */
282 if (np->speed == 1000)
283 np->an_enable = 1;
284 mii_set_media (dev);
285 }
1da177e4
LT		 286
287 err = register_netdev (dev);
288 if (err)
289 goto err_out_unmap_rx;
290
291 card_idx++;
292
e174961c
JB		 293 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
294 dev->name, np->name, dev->dev_addr, irq);
1da177e4 295 if (tx_coalesce > 1)
6aa20a22 296 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
1da177e4
LT		 297 tx_coalesce);
298 if (np->coalesce)
ad361c98
JP		 299 printk(KERN_INFO
300 "rx_coalesce:\t%d packets\n"
301 "rx_timeout: \t%d ns\n",
1da177e4
LT		 302 np->rx_coalesce, np->rx_timeout*640);
303 if (np->vlan)
304 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
305 return 0;
306
5e3cc4e3 307err_out_unmap_rx:
1da177e4 308 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
5e3cc4e3 309err_out_unmap_tx:
1da177e4 310 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
5e3cc4e3 311err_out_iounmap:
1da177e4 312#ifdef MEM_MAPPING
5e3cc4e3 313 pci_iounmap(pdev, np->ioaddr);
1da177e4 314#endif
5e3cc4e3
FR		 315 pci_iounmap(pdev, np->eeprom_addr);
316err_out_dev:
1da177e4 317 free_netdev (dev);
5e3cc4e3 318err_out_res:
1da177e4 319 pci_release_regions (pdev);
5e3cc4e3 320err_out_disable:
1da177e4
LT		 321 pci_disable_device (pdev);
322 return err;
323}
324
ddfce6bb 325static int
1da177e4
LT		 326find_miiphy (struct net_device *dev)
327{
5e3cc4e3 328 struct netdev_private *np = netdev_priv(dev);
1da177e4 329 int i, phy_found = 0;
1da177e4 330 np = netdev_priv(dev);
1da177e4
LT		 331 np->phy_addr = 1;
332
333 for (i = 31; i >= 0; i--) {
334 int mii_status = mii_read (dev, i, 1);
335 if (mii_status != 0xffff && mii_status != 0x0000) {
336 np->phy_addr = i;
337 phy_found++;
338 }
339 }
340 if (!phy_found) {
341 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
342 return -ENODEV;
343 }
344 return 0;
345}
346
ddfce6bb 347static int
1da177e4
LT		 348parse_eeprom (struct net_device *dev)
349{
5e3cc4e3
FR		 350 struct netdev_private *np = netdev_priv(dev);
351 void __iomem *ioaddr = np->ioaddr;
1da177e4 352 int i, j;
1da177e4
LT		 353 u8 sromdata[256];
354 u8 *psib;
355 u32 crc;
356 PSROM_t psrom = (PSROM_t) sromdata;
1da177e4
LT		 357
358 int cid, next;
359
5e3cc4e3
FR		 360 for (i = 0; i < 128; i++)
361 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
362
df950828
K		 363 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
364 /* Check CRC */
365 crc = ~ether_crc_le (256 - 4, sromdata);
06866bf5 366 if (psrom->crc != cpu_to_le32(crc)) {
df950828
K		 367 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
368 dev->name);
369 return -1;
370 }
1da177e4
LT		 371 }
372
373 /* Set MAC address */
374 for (i = 0; i < 6; i++)
375 dev->dev_addr[i] = psrom->mac_addr[i];
376
c3f45d32
OZ		 377 if (np->chip_id == CHIP_IP1000A) {
378 np->led_mode = psrom->led_mode;
379 return 0;
380 }
381
df950828
K		 382 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
383 return 0;
384 }
385
47bdd718 386 /* Parse Software Information Block */
1da177e4
LT		 387 i = 0x30;
388 psib = (u8 *) sromdata;
389 do {
390 cid = psib[i++];
391 next = psib[i++];
392 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
393 printk (KERN_ERR "Cell data error\n");
394 return -1;
395 }
396 switch (cid) {
397 case 0: /* Format version */
398 break;
399 case 1: /* End of cell */
400 return 0;
401 case 2: /* Duplex Polarity */
402 np->duplex_polarity = psib[i];
5e3cc4e3 403 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
1da177e4
LT		 404 break;
405 case 3: /* Wake Polarity */
406 np->wake_polarity = psib[i];
407 break;
408 case 9: /* Adapter description */
409 j = (next - i > 255) ? 255 : next - i;
410 memcpy (np->name, &(psib[i]), j);
411 break;
412 case 4:
413 case 5:
414 case 6:
415 case 7:
416 case 8: /* Reversed */
417 break;
418 default: /* Unknown cell */
419 return -1;
420 }
421 i = next;
422 } while (1);
423
424 return 0;
425}
426
c3f45d32
OZ		 427static void rio_set_led_mode(struct net_device *dev)
428{
429 struct netdev_private *np = netdev_priv(dev);
430 void __iomem *ioaddr = np->ioaddr;
431 u32 mode;
432
433 if (np->chip_id != CHIP_IP1000A)
434 return;
435
436 mode = dr32(ASICCtrl);
437 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
438
439 if (np->led_mode & 0x01)
440 mode |= IPG_AC_LED_MODE;
441 if (np->led_mode & 0x02)
442 mode |= IPG_AC_LED_MODE_BIT_1;
443 if (np->led_mode & 0x08)
444 mode |= IPG_AC_LED_SPEED;
445
446 dw32(ASICCtrl, mode);
447}
448
1da177e4
LT		 449static int
450rio_open (struct net_device *dev)
451{
452 struct netdev_private *np = netdev_priv(dev);
5e3cc4e3
FR		 453 void __iomem *ioaddr = np->ioaddr;
454 const int irq = np->pdev->irq;
1da177e4
LT		 455 int i;
456 u16 macctrl;
6aa20a22 457
5e3cc4e3 458 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 459 if (i)
460 return i;
6aa20a22 461
1da177e4 462 /* Reset all logic functions */
5e3cc4e3
FR		 463 dw16(ASICCtrl + 2,
464 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
1da177e4 465 mdelay(10);
6aa20a22 466
c3f45d32
OZ		 467 rio_set_led_mode(dev);
468
1da177e4 469 /* DebugCtrl bit 4, 5, 9 must set */
5e3cc4e3 470 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
1da177e4
LT		 471
472 /* Jumbo frame */
473 if (np->jumbo != 0)
5e3cc4e3 474 dw16(MaxFrameSize, MAX_JUMBO+14);
1da177e4
LT		 475
476 alloc_list (dev);
477
c3f45d32
OZ		 478 /* Set station address */
479 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
480 * too. However, it doesn't work on IP1000A so we use 16-bit access.
481 */
482 for (i = 0; i < 3; i++)
483 dw16(StationAddr0 + 2 * i,
484 cpu_to_le16(((u16 *)dev->dev_addr)[i]));
1da177e4
LT		 485
486 set_multicast (dev);
487 if (np->coalesce) {
5e3cc4e3 488 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
1da177e4
LT		 489 }
490 /* Set RIO to poll every N*320nsec. */
5e3cc4e3
FR		 491 dw8(RxDMAPollPeriod, 0x20);
492 dw8(TxDMAPollPeriod, 0xff);
493 dw8(RxDMABurstThresh, 0x30);
494 dw8(RxDMAUrgentThresh, 0x30);
495 dw32(RmonStatMask, 0x0007ffff);
1da177e4
LT		 496 /* clear statistics */
497 clear_stats (dev);
498
499 /* VLAN supported */
500 if (np->vlan) {
501 /* priority field in RxDMAIntCtrl */
5e3cc4e3 502 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
1da177e4 503 /* VLANId */
5e3cc4e3 504 dw16(VLANId, np->vlan);
1da177e4 505 /* Length/Type should be 0x8100 */
5e3cc4e3 506 dw32(VLANTag, 0x8100 << 16 | np->vlan);
1da177e4
LT		 507 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
508 VLAN information tagged by TFC' VID, CFI fields. */
5e3cc4e3 509 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
1da177e4
LT		 510 }
511
52e0b2b1 512 setup_timer(&np->timer, rio_timer, (unsigned long)dev);
1da177e4 513 np->timer.expires = jiffies + 1*HZ;
1da177e4
LT		 514 add_timer (&np->timer);
515
516 /* Start Tx/Rx */
5e3cc4e3 517 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
6aa20a22 518
1da177e4
LT		 519 macctrl = 0;
520 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
521 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
522 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
523 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
5e3cc4e3 524 dw16(MACCtrl, macctrl);
1da177e4
LT		 525
526 netif_start_queue (dev);
6aa20a22 527
5e3cc4e3 528 dl2k_enable_int(np);
1da177e4
LT		 529 return 0;
530}
531
6aa20a22 532static void
1da177e4
LT		 533rio_timer (unsigned long data)
534{
535 struct net_device *dev = (struct net_device *)data;
536 struct netdev_private *np = netdev_priv(dev);
537 unsigned int entry;
538 int next_tick = 1*HZ;
539 unsigned long flags;
540
541 spin_lock_irqsave(&np->rx_lock, flags);
542 /* Recover rx ring exhausted error */
543 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
544 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
545 /* Re-allocate skbuffs to fill the descriptor ring */
546 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
547 struct sk_buff *skb;
548 entry = np->old_rx % RX_RING_SIZE;
549 /* Dropped packets don't need to re-allocate */
550 if (np->rx_skbuff[entry] == NULL) {
89d71a66
ED		 551 skb = netdev_alloc_skb_ip_align(dev,
552 np->rx_buf_sz);
1da177e4
LT		 553 if (skb == NULL) {
554 np->rx_ring[entry].fraginfo = 0;
555 printk (KERN_INFO
556 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
557 dev->name, entry);
558 break;
559 }
560 np->rx_skbuff[entry] = skb;
1da177e4
LT		 561 np->rx_ring[entry].fraginfo =
562 cpu_to_le64 (pci_map_single
689be439 563 (np->pdev, skb->data, np->rx_buf_sz,
1da177e4
LT		 564 PCI_DMA_FROMDEVICE));
565 }
566 np->rx_ring[entry].fraginfo |=
78ce8d3d 567 cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 568 np->rx_ring[entry].status = 0;
569 } /* end for */
570 } /* end if */
571 spin_unlock_irqrestore (&np->rx_lock, flags);
572 np->timer.expires = jiffies + next_tick;
573 add_timer(&np->timer);
574}
6aa20a22 575
1da177e4
LT		 576static void
577rio_tx_timeout (struct net_device *dev)
578{
5e3cc4e3
FR		 579 struct netdev_private *np = netdev_priv(dev);
580 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 581
582 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
5e3cc4e3 583 dev->name, dr32(TxStatus));
1da177e4
LT		 584 rio_free_tx(dev, 0);
585 dev->if_port = 0;
cdd0db05 586 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 587}
588
589 /* allocate and initialize Tx and Rx descriptors */
590static void
591alloc_list (struct net_device *dev)
592{
593 struct netdev_private *np = netdev_priv(dev);
5e3cc4e3 594 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 595 int i;
596
597 np->cur_rx = np->cur_tx = 0;
598 np->old_rx = np->old_tx = 0;
599 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
600
601 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
602 for (i = 0; i < TX_RING_SIZE; i++) {
603 np->tx_skbuff[i] = NULL;
604 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
605 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
606 ((i+1)%TX_RING_SIZE) *
607 sizeof (struct netdev_desc));
608 }
609
610 /* Initialize Rx descriptors */
611 for (i = 0; i < RX_RING_SIZE; i++) {
612 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
613 ((i + 1) % RX_RING_SIZE) *
614 sizeof (struct netdev_desc));
615 np->rx_ring[i].status = 0;
616 np->rx_ring[i].fraginfo = 0;
617 np->rx_skbuff[i] = NULL;
618 }
619
620 /* Allocate the rx buffers */
621 for (i = 0; i < RX_RING_SIZE; i++) {
622 /* Allocated fixed size of skbuff */
89d71a66
ED		 623 struct sk_buff *skb;
624
625 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
1da177e4 626 np->rx_skbuff[i] = skb;
720a43ef 627 if (skb == NULL)
1da177e4 628 break;
720a43ef 629
1da177e4
LT		 630 /* Rubicon now supports 40 bits of addressing space. */
631 np->rx_ring[i].fraginfo =
632 cpu_to_le64 ( pci_map_single (
689be439 633 np->pdev, skb->data, np->rx_buf_sz,
1da177e4 634 PCI_DMA_FROMDEVICE));
78ce8d3d 635 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 636 }
637
638 /* Set RFDListPtr */
5e3cc4e3
FR		 639 dw32(RFDListPtr0, np->rx_ring_dma);
640 dw32(RFDListPtr1, 0);
1da177e4
LT		 641}
642
61357325 643static netdev_tx_t
1da177e4
LT		 644start_xmit (struct sk_buff *skb, struct net_device *dev)
645{
646 struct netdev_private *np = netdev_priv(dev);
5e3cc4e3 647 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 648 struct netdev_desc *txdesc;
649 unsigned entry;
1da177e4
LT		 650 u64 tfc_vlan_tag = 0;
651
652 if (np->link_status == 0) { /* Link Down */
653 dev_kfree_skb(skb);
cdd0db05 654 return NETDEV_TX_OK;
1da177e4 655 }
1da177e4
LT		 656 entry = np->cur_tx % TX_RING_SIZE;
657 np->tx_skbuff[entry] = skb;
658 txdesc = &np->tx_ring[entry];
659
660#if 0
84fa7933 661 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 662 txdesc->status |=
663 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
664 IPChecksumEnable);
665 }
666#endif
667 if (np->vlan) {
78ce8d3d
AV		 668 tfc_vlan_tag = VLANTagInsert |
669 ((u64)np->vlan << 32) |
670 ((u64)skb->priority << 45);
1da177e4
LT		 671 }
672 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
673 skb->len,
674 PCI_DMA_TODEVICE));
78ce8d3d 675 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
1da177e4
LT		 676
677 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
678 * Work around: Always use 1 descriptor in 10Mbps mode */
679 if (entry % np->tx_coalesce == 0 || np->speed == 10)
680 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
6aa20a22 681 WordAlignDisable |
1da177e4
LT		 682 TxDMAIndicate |
683 (1 << FragCountShift));
684 else
685 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
6aa20a22 686 WordAlignDisable |
1da177e4
LT		 687 (1 << FragCountShift));
688
689 /* TxDMAPollNow */
5e3cc4e3 690 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
1da177e4 691 /* Schedule ISR */
5e3cc4e3 692 dw32(CountDown, 10000);
1da177e4
LT		 693 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
694 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
695 < TX_QUEUE_LEN - 1 && np->speed != 10) {
696 /* do nothing */
697 } else if (!netif_queue_stopped(dev)) {
698 netif_stop_queue (dev);
699 }
700
701 /* The first TFDListPtr */
5e3cc4e3
FR		 702 if (!dr32(TFDListPtr0)) {
703 dw32(TFDListPtr0, np->tx_ring_dma +
704 entry * sizeof (struct netdev_desc));
705 dw32(TFDListPtr1, 0);
1da177e4 706 }
6aa20a22 707
cdd0db05 708 return NETDEV_TX_OK;
1da177e4
LT		 709}
710
711static irqreturn_t
7d12e780 712rio_interrupt (int irq, void *dev_instance)
1da177e4
LT		 713{
714 struct net_device *dev = dev_instance;
5e3cc4e3
FR		 715 struct netdev_private *np = netdev_priv(dev);
716 void __iomem *ioaddr = np->ioaddr;
1da177e4 717 unsigned int_status;
1da177e4
LT		 718 int cnt = max_intrloop;
719 int handled = 0;
720
1da177e4 721 while (1) {
5e3cc4e3
FR		 722 int_status = dr16(IntStatus);
723 dw16(IntStatus, int_status);
1da177e4
LT		 724 int_status &= DEFAULT_INTR;
725 if (int_status == 0 || --cnt < 0)
726 break;
727 handled = 1;
728 /* Processing received packets */
729 if (int_status & RxDMAComplete)
730 receive_packet (dev);
731 /* TxDMAComplete interrupt */
732 if ((int_status & (TxDMAComplete|IntRequested))) {
733 int tx_status;
5e3cc4e3 734 tx_status = dr32(TxStatus);
1da177e4
LT		 735 if (tx_status & 0x01)
736 tx_error (dev, tx_status);
737 /* Free used tx skbuffs */
6aa20a22 738 rio_free_tx (dev, 1);
1da177e4
LT		 739 }
740
741 /* Handle uncommon events */
742 if (int_status &
743 (HostError | LinkEvent | UpdateStats))
744 rio_error (dev, int_status);
745 }
746 if (np->cur_tx != np->old_tx)
5e3cc4e3 747 dw32(CountDown, 100);
1da177e4
LT		 748 return IRQ_RETVAL(handled);
749}
750
78ce8d3d
AV		 751static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
752{
e911e0d9 753 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
78ce8d3d
AV		 754}
755
6aa20a22
JG		 756static void
757rio_free_tx (struct net_device *dev, int irq)
1da177e4
LT		 758{
759 struct netdev_private *np = netdev_priv(dev);
760 int entry = np->old_tx % TX_RING_SIZE;
761 int tx_use = 0;
762 unsigned long flag = 0;
6aa20a22 763
1da177e4
LT		 764 if (irq)
765 spin_lock(&np->tx_lock);
766 else
767 spin_lock_irqsave(&np->tx_lock, flag);
6aa20a22 768
1da177e4
LT		 769 /* Free used tx skbuffs */
770 while (entry != np->cur_tx) {
771 struct sk_buff *skb;
772
78ce8d3d 773 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
1da177e4
LT		 774 break;
775 skb = np->tx_skbuff[entry];
776 pci_unmap_single (np->pdev,
78ce8d3d 777 desc_to_dma(&np->tx_ring[entry]),
1da177e4
LT		 778 skb->len, PCI_DMA_TODEVICE);
779 if (irq)
780 dev_kfree_skb_irq (skb);
781 else
782 dev_kfree_skb (skb);
783
784 np->tx_skbuff[entry] = NULL;
785 entry = (entry + 1) % TX_RING_SIZE;
786 tx_use++;
787 }
788 if (irq)
789 spin_unlock(&np->tx_lock);
790 else
791 spin_unlock_irqrestore(&np->tx_lock, flag);
792 np->old_tx = entry;
793
6aa20a22 794 /* If the ring is no longer full, clear tx_full and
1da177e4
LT		 795 call netif_wake_queue() */
796
797 if (netif_queue_stopped(dev) &&
6aa20a22 798 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
1da177e4
LT		 799 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
800 netif_wake_queue (dev);
801 }
802}
803
804static void
805tx_error (struct net_device *dev, int tx_status)
806{
5e3cc4e3
FR		 807 struct netdev_private *np = netdev_priv(dev);
808 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 809 int frame_id;
810 int i;
811
1da177e4
LT		 812 frame_id = (tx_status & 0xffff0000);
813 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
814 dev->name, tx_status, frame_id);
815 np->stats.tx_errors++;
816 /* Ttransmit Underrun */
817 if (tx_status & 0x10) {
818 np->stats.tx_fifo_errors++;
5e3cc4e3 819 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
1da177e4 820 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
5e3cc4e3
FR		 821 dw16(ASICCtrl + 2,
822 TxReset | DMAReset | FIFOReset | NetworkReset);
1da177e4
LT		 823 /* Wait for ResetBusy bit clear */
824 for (i = 50; i > 0; i--) {
5e3cc4e3 825 if (!(dr16(ASICCtrl + 2) & ResetBusy))
1da177e4
LT		 826 break;
827 mdelay (1);
828 }
c3f45d32 829 rio_set_led_mode(dev);
1da177e4
LT		 830 rio_free_tx (dev, 1);
831 /* Reset TFDListPtr */
5e3cc4e3
FR		 832 dw32(TFDListPtr0, np->tx_ring_dma +
833 np->old_tx * sizeof (struct netdev_desc));
834 dw32(TFDListPtr1, 0);
1da177e4
LT		 835
836 /* Let TxStartThresh stay default value */
837 }
838 /* Late Collision */
839 if (tx_status & 0x04) {
840 np->stats.tx_fifo_errors++;
841 /* TxReset and clear FIFO */
5e3cc4e3 842 dw16(ASICCtrl + 2, TxReset | FIFOReset);
1da177e4
LT		 843 /* Wait reset done */
844 for (i = 50; i > 0; i--) {
5e3cc4e3 845 if (!(dr16(ASICCtrl + 2) & ResetBusy))
1da177e4
LT		 846 break;
847 mdelay (1);
848 }
c3f45d32 849 rio_set_led_mode(dev);
1da177e4
LT		 850 /* Let TxStartThresh stay default value */
851 }
852 /* Maximum Collisions */
6aa20a22
JG		 853#ifdef ETHER_STATS
854 if (tx_status & 0x08)
1da177e4
LT		 855 np->stats.collisions16++;
856#else
6aa20a22 857 if (tx_status & 0x08)
1da177e4
LT		 858 np->stats.collisions++;
859#endif
860 /* Restart the Tx */
5e3cc4e3 861 dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
1da177e4
LT		 862}
863
864static int
865receive_packet (struct net_device *dev)
866{
867 struct netdev_private *np = netdev_priv(dev);
868 int entry = np->cur_rx % RX_RING_SIZE;
869 int cnt = 30;
870
871 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
872 while (1) {
873 struct netdev_desc *desc = &np->rx_ring[entry];
874 int pkt_len;
875 u64 frame_status;
876
78ce8d3d
AV		 877 if (!(desc->status & cpu_to_le64(RFDDone)) ||
878 !(desc->status & cpu_to_le64(FrameStart)) ||
879 !(desc->status & cpu_to_le64(FrameEnd)))
1da177e4
LT		 880 break;
881
882 /* Chip omits the CRC. */
78ce8d3d
AV		 883 frame_status = le64_to_cpu(desc->status);
884 pkt_len = frame_status & 0xffff;
1da177e4
LT		 885 if (--cnt < 0)
886 break;
887 /* Update rx error statistics, drop packet. */
888 if (frame_status & RFS_Errors) {
889 np->stats.rx_errors++;
890 if (frame_status & (RxRuntFrame | RxLengthError))
891 np->stats.rx_length_errors++;
892 if (frame_status & RxFCSError)
893 np->stats.rx_crc_errors++;
894 if (frame_status & RxAlignmentError && np->speed != 1000)
895 np->stats.rx_frame_errors++;
896 if (frame_status & RxFIFOOverrun)
897 np->stats.rx_fifo_errors++;
898 } else {
899 struct sk_buff *skb;
900
901 /* Small skbuffs for short packets */
902 if (pkt_len > copy_thresh) {
9ee09d9c 903 pci_unmap_single (np->pdev,
78ce8d3d 904 desc_to_dma(desc),
1da177e4
LT		 905 np->rx_buf_sz,
906 PCI_DMA_FROMDEVICE);
907 skb_put (skb = np->rx_skbuff[entry], pkt_len);
908 np->rx_skbuff[entry] = NULL;
89d71a66 909 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
1da177e4 910 pci_dma_sync_single_for_cpu(np->pdev,
78ce8d3d 911 desc_to_dma(desc),
1da177e4
LT		 912 np->rx_buf_sz,
913 PCI_DMA_FROMDEVICE);
8c7b7faa 914 skb_copy_to_linear_data (skb,
689be439 915 np->rx_skbuff[entry]->data,
8c7b7faa 916 pkt_len);
1da177e4
LT		 917 skb_put (skb, pkt_len);
918 pci_dma_sync_single_for_device(np->pdev,
78ce8d3d 919 desc_to_dma(desc),
1da177e4
LT		 920 np->rx_buf_sz,
921 PCI_DMA_FROMDEVICE);
922 }
923 skb->protocol = eth_type_trans (skb, dev);
6aa20a22 924#if 0
1da177e4 925 /* Checksum done by hw, but csum value unavailable. */
44c10138 926 if (np->pdev->pci_rev_id >= 0x0c &&
1da177e4
LT		 927 !(frame_status & (TCPError | UDPError | IPError))) {
928 skb->ip_summed = CHECKSUM_UNNECESSARY;
6aa20a22 929 }
1da177e4
LT		 930#endif
931 netif_rx (skb);
1da177e4
LT		 932 }
933 entry = (entry + 1) % RX_RING_SIZE;
934 }
935 spin_lock(&np->rx_lock);
936 np->cur_rx = entry;
937 /* Re-allocate skbuffs to fill the descriptor ring */
938 entry = np->old_rx;
939 while (entry != np->cur_rx) {
940 struct sk_buff *skb;
941 /* Dropped packets don't need to re-allocate */
942 if (np->rx_skbuff[entry] == NULL) {
89d71a66 943 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
1da177e4
LT		 944 if (skb == NULL) {
945 np->rx_ring[entry].fraginfo = 0;
946 printk (KERN_INFO
947 "%s: receive_packet: "
948 "Unable to re-allocate Rx skbuff.#%d\n",
949 dev->name, entry);
950 break;
951 }
952 np->rx_skbuff[entry] = skb;
1da177e4
LT		 953 np->rx_ring[entry].fraginfo =
954 cpu_to_le64 (pci_map_single
689be439 955 (np->pdev, skb->data, np->rx_buf_sz,
1da177e4
LT		 956 PCI_DMA_FROMDEVICE));
957 }
958 np->rx_ring[entry].fraginfo |=
78ce8d3d 959 cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 960 np->rx_ring[entry].status = 0;
961 entry = (entry + 1) % RX_RING_SIZE;
962 }
963 np->old_rx = entry;
964 spin_unlock(&np->rx_lock);
965 return 0;
966}
967
968static void
969rio_error (struct net_device *dev, int int_status)
970{
1da177e4 971 struct netdev_private *np = netdev_priv(dev);
5e3cc4e3 972 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 973 u16 macctrl;
974
975 /* Link change event */
976 if (int_status & LinkEvent) {
977 if (mii_wait_link (dev, 10) == 0) {
978 printk (KERN_INFO "%s: Link up\n", dev->name);
979 if (np->phy_media)
980 mii_get_media_pcs (dev);
981 else
982 mii_get_media (dev);
983 if (np->speed == 1000)
984 np->tx_coalesce = tx_coalesce;
6aa20a22 985 else
1da177e4
LT		 986 np->tx_coalesce = 1;
987 macctrl = 0;
988 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
989 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
6aa20a22 990 macctrl |= (np->tx_flow) ?
1da177e4 991 TxFlowControlEnable : 0;
6aa20a22 992 macctrl |= (np->rx_flow) ?
1da177e4 993 RxFlowControlEnable : 0;
5e3cc4e3 994 dw16(MACCtrl, macctrl);
1da177e4
LT		 995 np->link_status = 1;
996 netif_carrier_on(dev);
997 } else {
998 printk (KERN_INFO "%s: Link off\n", dev->name);
999 np->link_status = 0;
1000 netif_carrier_off(dev);
1001 }
1002 }
1003
1004 /* UpdateStats statistics registers */
1005 if (int_status & UpdateStats) {
1006 get_stats (dev);
1007 }
1008
6aa20a22 1009 /* PCI Error, a catastronphic error related to the bus interface
1da177e4
LT		 1010 occurs, set GlobalReset and HostReset to reset. */
1011 if (int_status & HostError) {
1012 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1013 dev->name, int_status);
5e3cc4e3 1014 dw16(ASICCtrl + 2, GlobalReset | HostReset);
1da177e4 1015 mdelay (500);
c3f45d32 1016 rio_set_led_mode(dev);
1da177e4
LT		 1017 }
1018}
1019
1020static struct net_device_stats *
1021get_stats (struct net_device *dev)
1022{
1da177e4 1023 struct netdev_private *np = netdev_priv(dev);
5e3cc4e3 1024 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 1025#ifdef MEM_MAPPING
1026 int i;
1027#endif
1028 unsigned int stat_reg;
1029
1030 /* All statistics registers need to be acknowledged,
1031 else statistic overflow could cause problems */
6aa20a22 1032
5e3cc4e3
FR		 1033 np->stats.rx_packets += dr32(FramesRcvOk);
1034 np->stats.tx_packets += dr32(FramesXmtOk);
1035 np->stats.rx_bytes += dr32(OctetRcvOk);
1036 np->stats.tx_bytes += dr32(OctetXmtOk);
1da177e4 1037
5e3cc4e3
FR		 1038 np->stats.multicast = dr32(McstFramesRcvdOk);
1039 np->stats.collisions += dr32(SingleColFrames)
1040 + dr32(MultiColFrames);
6aa20a22 1041
1da177e4 1042 /* detailed tx errors */
5e3cc4e3 1043 stat_reg = dr16(FramesAbortXSColls);
1da177e4
LT		 1044 np->stats.tx_aborted_errors += stat_reg;
1045 np->stats.tx_errors += stat_reg;
1046
5e3cc4e3 1047 stat_reg = dr16(CarrierSenseErrors);
1da177e4
LT		 1048 np->stats.tx_carrier_errors += stat_reg;
1049 np->stats.tx_errors += stat_reg;
1050
1051 /* Clear all other statistic register. */
5e3cc4e3
FR		 1052 dr32(McstOctetXmtOk);
1053 dr16(BcstFramesXmtdOk);
1054 dr32(McstFramesXmtdOk);
1055 dr16(BcstFramesRcvdOk);
1056 dr16(MacControlFramesRcvd);
1057 dr16(FrameTooLongErrors);
1058 dr16(InRangeLengthErrors);
1059 dr16(FramesCheckSeqErrors);
1060 dr16(FramesLostRxErrors);
1061 dr32(McstOctetXmtOk);
1062 dr32(BcstOctetXmtOk);
1063 dr32(McstFramesXmtdOk);
1064 dr32(FramesWDeferredXmt);
1065 dr32(LateCollisions);
1066 dr16(BcstFramesXmtdOk);
1067 dr16(MacControlFramesXmtd);
1068 dr16(FramesWEXDeferal);
1da177e4
LT		 1069
1070#ifdef MEM_MAPPING
1071 for (i = 0x100; i <= 0x150; i += 4)
5e3cc4e3 1072 dr32(i);
1da177e4 1073#endif
5e3cc4e3
FR		 1074 dr16(TxJumboFrames);
1075 dr16(RxJumboFrames);
1076 dr16(TCPCheckSumErrors);
1077 dr16(UDPCheckSumErrors);
1078 dr16(IPCheckSumErrors);
1da177e4
LT		 1079 return &np->stats;
1080}
1081
1082static int
1083clear_stats (struct net_device *dev)
1084{
5e3cc4e3
FR		 1085 struct netdev_private *np = netdev_priv(dev);
1086 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 1087#ifdef MEM_MAPPING
1088 int i;
6aa20a22 1089#endif
1da177e4
LT		 1090
1091 /* All statistics registers need to be acknowledged,
1092 else statistic overflow could cause problems */
5e3cc4e3
FR		 1093 dr32(FramesRcvOk);
1094 dr32(FramesXmtOk);
1095 dr32(OctetRcvOk);
1096 dr32(OctetXmtOk);
1097
1098 dr32(McstFramesRcvdOk);
1099 dr32(SingleColFrames);
1100 dr32(MultiColFrames);
1101 dr32(LateCollisions);
6aa20a22 1102 /* detailed rx errors */
5e3cc4e3
FR		 1103 dr16(FrameTooLongErrors);
1104 dr16(InRangeLengthErrors);
1105 dr16(FramesCheckSeqErrors);
1106 dr16(FramesLostRxErrors);
1da177e4
LT		 1107
1108 /* detailed tx errors */
5e3cc4e3
FR		 1109 dr16(FramesAbortXSColls);
1110 dr16(CarrierSenseErrors);
1da177e4
LT		 1111
1112 /* Clear all other statistic register. */
5e3cc4e3
FR		 1113 dr32(McstOctetXmtOk);
1114 dr16(BcstFramesXmtdOk);
1115 dr32(McstFramesXmtdOk);
1116 dr16(BcstFramesRcvdOk);
1117 dr16(MacControlFramesRcvd);
1118 dr32(McstOctetXmtOk);
1119 dr32(BcstOctetXmtOk);
1120 dr32(McstFramesXmtdOk);
1121 dr32(FramesWDeferredXmt);
1122 dr16(BcstFramesXmtdOk);
1123 dr16(MacControlFramesXmtd);
1124 dr16(FramesWEXDeferal);
1da177e4
LT		 1125#ifdef MEM_MAPPING
1126 for (i = 0x100; i <= 0x150; i += 4)
5e3cc4e3 1127 dr32(i);
6aa20a22 1128#endif
5e3cc4e3
FR		 1129 dr16(TxJumboFrames);
1130 dr16(RxJumboFrames);
1131 dr16(TCPCheckSumErrors);
1132 dr16(UDPCheckSumErrors);
1133 dr16(IPCheckSumErrors);
1da177e4
LT		 1134 return 0;
1135}
1136
1137
ddfce6bb 1138static int
1da177e4
LT		 1139change_mtu (struct net_device *dev, int new_mtu)
1140{
1141 struct netdev_private *np = netdev_priv(dev);
1142 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1143
1144 if ((new_mtu < 68) || (new_mtu > max)) {
1145 return -EINVAL;
1146 }
1147
1148 dev->mtu = new_mtu;
1149
1150 return 0;
1151}
1152
1153static void
1154set_multicast (struct net_device *dev)
1155{
5e3cc4e3
FR		 1156 struct netdev_private *np = netdev_priv(dev);
1157 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 1158 u32 hash_table[2];
1159 u16 rx_mode = 0;
6aa20a22 1160
1da177e4
LT		 1161 hash_table[0] = hash_table[1] = 0;
1162 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
78ce8d3d 1163 hash_table[1] |= 0x02000000;
1da177e4
LT		 1164 if (dev->flags & IFF_PROMISC) {
1165 /* Receive all frames promiscuously. */
1166 rx_mode = ReceiveAllFrames;
6aa20a22 1167 } else if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf 1168 (netdev_mc_count(dev) > multicast_filter_limit)) {
1da177e4
LT		 1169 /* Receive broadcast and multicast frames */
1170 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
4cd24eaf 1171 } else if (!netdev_mc_empty(dev)) {
22bedad3 1172 struct netdev_hw_addr *ha;
6aa20a22 1173 /* Receive broadcast frames and multicast frames filtering
1da177e4
LT		 1174 by Hashtable */
1175 rx_mode =
1176 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
22bedad3 1177 netdev_for_each_mc_addr(ha, dev) {
1da177e4 1178 int bit, index = 0;
22bedad3 1179 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1da177e4
LT		 1180 /* The inverted high significant 6 bits of CRC are
1181 used as an index to hashtable */
1182 for (bit = 0; bit < 6; bit++)
1183 if (crc & (1 << (31 - bit)))
1184 index |= (1 << bit);
1185 hash_table[index / 32] |= (1 << (index % 32));
1186 }
1187 } else {
1188 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1189 }
1190 if (np->vlan) {
1191 /* ReceiveVLANMatch field in ReceiveMode */
1192 rx_mode |= ReceiveVLANMatch;
1193 }
1194
5e3cc4e3
FR		 1195 dw32(HashTable0, hash_table[0]);
1196 dw32(HashTable1, hash_table[1]);
1197 dw16(ReceiveMode, rx_mode);
1da177e4
LT		 1198}
1199
1200static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1201{
1202 struct netdev_private *np = netdev_priv(dev);
7826d43f
JP		 1203
1204 strlcpy(info->driver, "dl2k", sizeof(info->driver));
1205 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1206 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
6aa20a22 1207}
1da177e4
LT		 1208
1209static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1210{
1211 struct netdev_private *np = netdev_priv(dev);
1212 if (np->phy_media) {
1213 /* fiber device */
1214 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1215 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1216 cmd->port = PORT_FIBRE;
6aa20a22 1217 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 1218 } else {
1219 /* copper device */
6aa20a22 1220 cmd->supported = SUPPORTED_10baseT_Half |
1da177e4
LT		 1221 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1222 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1223 SUPPORTED_Autoneg | SUPPORTED_MII;
1224 cmd->advertising = ADVERTISED_10baseT_Half |
1225 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1226 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1227 ADVERTISED_Autoneg | ADVERTISED_MII;
1228 cmd->port = PORT_MII;
1229 cmd->transceiver = XCVR_INTERNAL;
1230 }
6aa20a22 1231 if ( np->link_status ) {
70739497 1232 ethtool_cmd_speed_set(cmd, np->speed);
1da177e4
LT		 1233 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1234 } else {
537fae01
JP		 1235 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
1236 cmd->duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 1237 }
1238 if ( np->an_enable)
1239 cmd->autoneg = AUTONEG_ENABLE;
1240 else
1241 cmd->autoneg = AUTONEG_DISABLE;
6aa20a22 1242
1da177e4 1243 cmd->phy_address = np->phy_addr;
6aa20a22 1244 return 0;
1da177e4
LT		 1245}
1246
1247static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1248{
1249 struct netdev_private *np = netdev_priv(dev);
1250 netif_carrier_off(dev);
1251 if (cmd->autoneg == AUTONEG_ENABLE) {
1252 if (np->an_enable)
1253 return 0;
1254 else {
1255 np->an_enable = 1;
1256 mii_set_media(dev);
6aa20a22
JG		 1257 return 0;
1258 }
1da177e4
LT		 1259 } else {
1260 np->an_enable = 0;
1261 if (np->speed == 1000) {
25db0338 1262 ethtool_cmd_speed_set(cmd, SPEED_100);
1da177e4
LT		 1263 cmd->duplex = DUPLEX_FULL;
1264 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1265 }
25db0338
DD		 1266 switch (ethtool_cmd_speed(cmd)) {
1267 case SPEED_10:
1da177e4 1268 np->speed = 10;
25db0338 1269 np->full_duplex = (cmd->duplex == DUPLEX_FULL);
1da177e4 1270 break;
25db0338 1271 case SPEED_100:
1da177e4 1272 np->speed = 100;
25db0338 1273 np->full_duplex = (cmd->duplex == DUPLEX_FULL);
1da177e4 1274 break;
25db0338 1275 case SPEED_1000: /* not supported */
1da177e4 1276 default:
6aa20a22 1277 return -EINVAL;
1da177e4
LT		 1278 }
1279 mii_set_media(dev);
1280 }
1281 return 0;
1282}
1283
1284static u32 rio_get_link(struct net_device *dev)
1285{
1286 struct netdev_private *np = netdev_priv(dev);
1287 return np->link_status;
1288}
1289
7282d491 1290static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1291 .get_drvinfo = rio_get_drvinfo,
1292 .get_settings = rio_get_settings,
1293 .set_settings = rio_set_settings,
1294 .get_link = rio_get_link,
1295};
1296
1297static int
1298rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1299{
1300 int phy_addr;
1301 struct netdev_private *np = netdev_priv(dev);
1bb57e94 1302 struct mii_ioctl_data *miidata = if_mii(rq);
1da177e4
LT		 1303
1304 phy_addr = np->phy_addr;
1305 switch (cmd) {
1bb57e94
JM		 1306 case SIOCGMIIPHY:
1307 miidata->phy_id = phy_addr;
1da177e4 1308 break;
1bb57e94
JM		 1309 case SIOCGMIIREG:
1310 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
1da177e4 1311 break;
1bb57e94
JM		 1312 case SIOCSMIIREG:
1313 if (!capable(CAP_NET_ADMIN))
1314 return -EPERM;
1315 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
1da177e4 1316 break;
1da177e4
LT		 1317 default:
1318 return -EOPNOTSUPP;
1319 }
1320 return 0;
1321}
1322
1323#define EEP_READ 0x0200
1324#define EEP_BUSY 0x8000
1325/* Read the EEPROM word */
1326/* We use I/O instruction to read/write eeprom to avoid fail on some machines */
5e3cc4e3 1327static int read_eeprom(struct netdev_private *np, int eep_addr)
1da177e4 1328{
5e3cc4e3 1329 void __iomem *ioaddr = np->eeprom_addr;
1da177e4 1330 int i = 1000;
5e3cc4e3
FR		 1331
1332 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
1da177e4 1333 while (i-- > 0) {
5e3cc4e3
FR		 1334 if (!(dr16(EepromCtrl) & EEP_BUSY))
1335 return dr16(EepromData);
1da177e4
LT		 1336 }
1337 return 0;
1338}
1339
1340enum phy_ctrl_bits {
1341 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1342 MII_DUPLEX = 0x08,
1343};
1344
5e3cc4e3 1345#define mii_delay() dr8(PhyCtrl)
1da177e4
LT		 1346static void
1347mii_sendbit (struct net_device *dev, u32 data)
1348{
5e3cc4e3
FR		 1349 struct netdev_private *np = netdev_priv(dev);
1350 void __iomem *ioaddr = np->ioaddr;
1351
1352 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
1353 dw8(PhyCtrl, data);
1da177e4 1354 mii_delay ();
5e3cc4e3 1355 dw8(PhyCtrl, data | MII_CLK);
1da177e4
LT		 1356 mii_delay ();
1357}
1358
1359static int
1360mii_getbit (struct net_device *dev)
1361{
5e3cc4e3
FR		 1362 struct netdev_private *np = netdev_priv(dev);
1363 void __iomem *ioaddr = np->ioaddr;
1da177e4
LT		 1364 u8 data;
1365
5e3cc4e3
FR		 1366 data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
1367 dw8(PhyCtrl, data);
1da177e4 1368 mii_delay ();
5e3cc4e3 1369 dw8(PhyCtrl, data | MII_CLK);
1da177e4 1370 mii_delay ();
5e3cc4e3 1371 return (dr8(PhyCtrl) >> 1) & 1;
1da177e4
LT		 1372}
1373
1374static void
1375mii_send_bits (struct net_device *dev, u32 data, int len)
1376{
1377 int i;
5e3cc4e3 1378
1da177e4
LT		 1379 for (i = len - 1; i >= 0; i--) {
1380 mii_sendbit (dev, data & (1 << i));
1381 }
1382}
1383
1384static int
1385mii_read (struct net_device *dev, int phy_addr, int reg_num)
1386{
1387 u32 cmd;
1388 int i;
1389 u32 retval = 0;
1390
1391 /* Preamble */
1392 mii_send_bits (dev, 0xffffffff, 32);
1393 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1394 /* ST,OP = 0110'b for read operation */
1395 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1396 mii_send_bits (dev, cmd, 14);
1397 /* Turnaround */
1398 if (mii_getbit (dev))
1399 goto err_out;
1400 /* Read data */
1401 for (i = 0; i < 16; i++) {
1402 retval |= mii_getbit (dev);
1403 retval <<= 1;
1404 }
1405 /* End cycle */
1406 mii_getbit (dev);
1407 return (retval >> 1) & 0xffff;
1408
1409 err_out:
1410 return 0;
1411}
1412static int
1413mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1414{
1415 u32 cmd;
1416
1417 /* Preamble */
1418 mii_send_bits (dev, 0xffffffff, 32);
1419 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1420 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1421 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1422 mii_send_bits (dev, cmd, 32);
1423 /* End cycle */
1424 mii_getbit (dev);
1425 return 0;
1426}
1427static int
1428mii_wait_link (struct net_device *dev, int wait)
1429{
96d76851 1430 __u16 bmsr;
1da177e4
LT		 1431 int phy_addr;
1432 struct netdev_private *np;
1433
1434 np = netdev_priv(dev);
1435 phy_addr = np->phy_addr;
1436
1437 do {
96d76851 1438 bmsr = mii_read (dev, phy_addr, MII_BMSR);
78f6a6bd 1439 if (bmsr & BMSR_LSTATUS)
1da177e4
LT		 1440 return 0;
1441 mdelay (1);
1442 } while (--wait > 0);
1443 return -1;
1444}
1445static int
1446mii_get_media (struct net_device *dev)
1447{
21b645e4 1448 __u16 negotiate;
96d76851 1449 __u16 bmsr;
5b511916
AV		 1450 __u16 mscr;
1451 __u16 mssr;
1da177e4
LT		 1452 int phy_addr;
1453 struct netdev_private *np;
1454
1455 np = netdev_priv(dev);
1456 phy_addr = np->phy_addr;
1457
96d76851 1458 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1da177e4 1459 if (np->an_enable) {
78f6a6bd 1460 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1da177e4
LT		 1461 /* Auto-Negotiation not completed */
1462 return -1;
1463 }
78f6a6bd
FR		 1464 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1465 mii_read (dev, phy_addr, MII_LPA);
1466 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1467 mssr = mii_read (dev, phy_addr, MII_STAT1000);
1468 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
1da177e4
LT		 1469 np->speed = 1000;
1470 np->full_duplex = 1;
1471 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
78f6a6bd 1472 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
1da177e4
LT		 1473 np->speed = 1000;
1474 np->full_duplex = 0;
1475 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
78f6a6bd 1476 } else if (negotiate & ADVERTISE_100FULL) {
1da177e4
LT		 1477 np->speed = 100;
1478 np->full_duplex = 1;
1479 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
78f6a6bd 1480 } else if (negotiate & ADVERTISE_100HALF) {
1da177e4
LT		 1481 np->speed = 100;
1482 np->full_duplex = 0;
1483 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
78f6a6bd 1484 } else if (negotiate & ADVERTISE_10FULL) {
1da177e4
LT		 1485 np->speed = 10;
1486 np->full_duplex = 1;
1487 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
78f6a6bd 1488 } else if (negotiate & ADVERTISE_10HALF) {
1da177e4
LT		 1489 np->speed = 10;
1490 np->full_duplex = 0;
1491 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1492 }
78f6a6bd 1493 if (negotiate & ADVERTISE_PAUSE_CAP) {
1da177e4
LT		 1494 np->tx_flow &= 1;
1495 np->rx_flow &= 1;
78f6a6bd 1496 } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
1da177e4
LT		 1497 np->tx_flow = 0;
1498 np->rx_flow &= 1;
1499 }
1500 /* else tx_flow, rx_flow = user select */
1501 } else {
d50956af 1502 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
78f6a6bd
FR		 1503 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1504 case BMCR_SPEED1000:
d50956af
AV		 1505 printk (KERN_INFO "Operating at 1000 Mbps, ");
1506 break;
78f6a6bd 1507 case BMCR_SPEED100:
1da177e4 1508 printk (KERN_INFO "Operating at 100 Mbps, ");
d50956af
AV		 1509 break;
1510 case 0:
1da177e4 1511 printk (KERN_INFO "Operating at 10 Mbps, ");
1da177e4 1512 }
78f6a6bd 1513 if (bmcr & BMCR_FULLDPLX) {
ad361c98 1514 printk (KERN_CONT "Full duplex\n");
1da177e4 1515 } else {
ad361c98 1516 printk (KERN_CONT "Half duplex\n");
1da177e4
LT		 1517 }
1518 }
6aa20a22 1519 if (np->tx_flow)
1da177e4 1520 printk(KERN_INFO "Enable Tx Flow Control\n");
6aa20a22 1521 else
1da177e4
LT		 1522 printk(KERN_INFO "Disable Tx Flow Control\n");
1523 if (np->rx_flow)
1524 printk(KERN_INFO "Enable Rx Flow Control\n");
1525 else
1526 printk(KERN_INFO "Disable Rx Flow Control\n");
1527
1528 return 0;
1529}
1530
1531static int
1532mii_set_media (struct net_device *dev)
1533{
5b511916 1534 __u16 pscr;
d50956af 1535 __u16 bmcr;
96d76851 1536 __u16 bmsr;
21b645e4 1537 __u16 anar;
1da177e4
LT		 1538 int phy_addr;
1539 struct netdev_private *np;
1540 np = netdev_priv(dev);
1541 phy_addr = np->phy_addr;
1542
1543 /* Does user set speed? */
1544 if (np->an_enable) {
1545 /* Advertise capabilities */
96d76851 1546 bmsr = mii_read (dev, phy_addr, MII_BMSR);
78f6a6bd
FR		 1547 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1548 ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1549 ADVERTISE_100HALF | ADVERTISE_10HALF |
1550 ADVERTISE_100BASE4);
1551 if (bmsr & BMSR_100FULL)
1552 anar |= ADVERTISE_100FULL;
1553 if (bmsr & BMSR_100HALF)
1554 anar |= ADVERTISE_100HALF;
1555 if (bmsr & BMSR_100BASE4)
1556 anar |= ADVERTISE_100BASE4;
1557 if (bmsr & BMSR_10FULL)
1558 anar |= ADVERTISE_10FULL;
1559 if (bmsr & BMSR_10HALF)
1560 anar |= ADVERTISE_10HALF;
1561 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1562 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1da177e4
LT		 1563
1564 /* Enable Auto crossover */
5b511916
AV		 1565 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1566 pscr |= 3 << 5; /* 11'b */
1567 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
6aa20a22 1568
1da177e4 1569 /* Soft reset PHY */
78f6a6bd
FR		 1570 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1571 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
d50956af 1572 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1573 mdelay(1);
1574 } else {
1575 /* Force speed setting */
1576 /* 1) Disable Auto crossover */
5b511916
AV		 1577 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1578 pscr &= ~(3 << 5);
1579 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1da177e4
LT		 1580
1581 /* 2) PHY Reset */
d50956af 1582 bmcr = mii_read (dev, phy_addr, MII_BMCR);
78f6a6bd 1583 bmcr |= BMCR_RESET;
d50956af 1584 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1585
1586 /* 3) Power Down */
d50956af
AV		 1587 bmcr = 0x1940; /* must be 0x1940 */
1588 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1589 mdelay (100); /* wait a certain time */
1590
1591 /* 4) Advertise nothing */
78f6a6bd 1592 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1da177e4
LT		 1593
1594 /* 5) Set media and Power Up */
78f6a6bd 1595 bmcr = BMCR_PDOWN;
1da177e4 1596 if (np->speed == 100) {
78f6a6bd 1597 bmcr |= BMCR_SPEED100;
1da177e4
LT		 1598 printk (KERN_INFO "Manual 100 Mbps, ");
1599 } else if (np->speed == 10) {
1da177e4
LT		 1600 printk (KERN_INFO "Manual 10 Mbps, ");
1601 }
1602 if (np->full_duplex) {
78f6a6bd 1603 bmcr |= BMCR_FULLDPLX;
ad361c98 1604 printk (KERN_CONT "Full duplex\n");
1da177e4 1605 } else {
ad361c98 1606 printk (KERN_CONT "Half duplex\n");
1da177e4
LT		 1607 }
1608#if 0
1609 /* Set 1000BaseT Master/Slave setting */
78f6a6bd 1610 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
5b511916
AV		 1611 mscr |= MII_MSCR_CFG_ENABLE;
1612 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1da177e4 1613#endif
d50956af 1614 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1615 mdelay(10);
1616 }
1617 return 0;
1618}
1619
1620static int
1621mii_get_media_pcs (struct net_device *dev)
1622{
21b645e4 1623 __u16 negotiate;
96d76851 1624 __u16 bmsr;
1da177e4
LT		 1625 int phy_addr;
1626 struct netdev_private *np;
1627
1628 np = netdev_priv(dev);
1629 phy_addr = np->phy_addr;
1630
96d76851 1631 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1da177e4 1632 if (np->an_enable) {
78f6a6bd 1633 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1da177e4
LT		 1634 /* Auto-Negotiation not completed */
1635 return -1;
1636 }
21b645e4 1637 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1da177e4
LT		 1638 mii_read (dev, phy_addr, PCS_ANLPAR);
1639 np->speed = 1000;
21b645e4 1640 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1da177e4
LT		 1641 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1642 np->full_duplex = 1;
1643 } else {
1644 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1645 np->full_duplex = 0;
1646 }
21b645e4 1647 if (negotiate & PCS_ANAR_PAUSE) {
1da177e4
LT		 1648 np->tx_flow &= 1;
1649 np->rx_flow &= 1;
21b645e4 1650 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1da177e4
LT		 1651 np->tx_flow = 0;
1652 np->rx_flow &= 1;
1653 }
1654 /* else tx_flow, rx_flow = user select */
1655 } else {
d50956af 1656 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1da177e4 1657 printk (KERN_INFO "Operating at 1000 Mbps, ");
78f6a6bd 1658 if (bmcr & BMCR_FULLDPLX) {
ad361c98 1659 printk (KERN_CONT "Full duplex\n");
1da177e4 1660 } else {
ad361c98 1661 printk (KERN_CONT "Half duplex\n");
1da177e4
LT		 1662 }
1663 }
6aa20a22 1664 if (np->tx_flow)
1da177e4 1665 printk(KERN_INFO "Enable Tx Flow Control\n");
6aa20a22 1666 else
1da177e4
LT		 1667 printk(KERN_INFO "Disable Tx Flow Control\n");
1668 if (np->rx_flow)
1669 printk(KERN_INFO "Enable Rx Flow Control\n");
1670 else
1671 printk(KERN_INFO "Disable Rx Flow Control\n");
1672
1673 return 0;
1674}
1675
1676static int
1677mii_set_media_pcs (struct net_device *dev)
1678{
d50956af 1679 __u16 bmcr;
5b511916 1680 __u16 esr;
21b645e4 1681 __u16 anar;
1da177e4
LT		 1682 int phy_addr;
1683 struct netdev_private *np;
1684 np = netdev_priv(dev);
1685 phy_addr = np->phy_addr;
1686
1687 /* Auto-Negotiation? */
1688 if (np->an_enable) {
1689 /* Advertise capabilities */
5b511916 1690 esr = mii_read (dev, phy_addr, PCS_ESR);
78f6a6bd 1691 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
21b645e4
AV		 1692 ~PCS_ANAR_HALF_DUPLEX &
1693 ~PCS_ANAR_FULL_DUPLEX;
5b511916 1694 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
21b645e4 1695 anar |= PCS_ANAR_HALF_DUPLEX;
5b511916 1696 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
21b645e4
AV		 1697 anar |= PCS_ANAR_FULL_DUPLEX;
1698 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
78f6a6bd 1699 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1da177e4
LT		 1700
1701 /* Soft reset PHY */
78f6a6bd
FR		 1702 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1703 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
d50956af 1704 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1705 mdelay(1);
1706 } else {
1707 /* Force speed setting */
1708 /* PHY Reset */
78f6a6bd 1709 bmcr = BMCR_RESET;
d50956af 1710 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4 1711 mdelay(10);
1da177e4 1712 if (np->full_duplex) {
78f6a6bd 1713 bmcr = BMCR_FULLDPLX;
1da177e4
LT		 1714 printk (KERN_INFO "Manual full duplex\n");
1715 } else {
d50956af 1716 bmcr = 0;
1da177e4
LT		 1717 printk (KERN_INFO "Manual half duplex\n");
1718 }
d50956af 1719 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1720 mdelay(10);
1721
1722 /* Advertise nothing */
78f6a6bd 1723 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1da177e4
LT		 1724 }
1725 return 0;
1726}
1727
1728
1729static int
1730rio_close (struct net_device *dev)
1731{
1da177e4 1732 struct netdev_private *np = netdev_priv(dev);
5e3cc4e3
FR		 1733 void __iomem *ioaddr = np->ioaddr;
1734
1735 struct pci_dev *pdev = np->pdev;
1da177e4
LT		 1736 struct sk_buff *skb;
1737 int i;
1738
1739 netif_stop_queue (dev);
1740
1741 /* Disable interrupts */
5e3cc4e3 1742 dw16(IntEnable, 0);
1da177e4
LT		 1743
1744 /* Stop Tx and Rx logics */
5e3cc4e3 1745 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
be0976be 1746
5e3cc4e3 1747 free_irq(pdev->irq, dev);
1da177e4 1748 del_timer_sync (&np->timer);
6aa20a22 1749
1da177e4
LT		 1750 /* Free all the skbuffs in the queue. */
1751 for (i = 0; i < RX_RING_SIZE; i++) {
1da177e4
LT		 1752 skb = np->rx_skbuff[i];
1753 if (skb) {
5e3cc4e3 1754 pci_unmap_single(pdev, desc_to_dma(&np->rx_ring[i]),
9ee09d9c 1755 skb->len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1756 dev_kfree_skb (skb);
1757 np->rx_skbuff[i] = NULL;
1758 }
9eb71079
SG		 1759 np->rx_ring[i].status = 0;
1760 np->rx_ring[i].fraginfo = 0;
1da177e4
LT		 1761 }
1762 for (i = 0; i < TX_RING_SIZE; i++) {
1763 skb = np->tx_skbuff[i];
1764 if (skb) {
5e3cc4e3 1765 pci_unmap_single(pdev, desc_to_dma(&np->tx_ring[i]),
9ee09d9c 1766 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT		 1767 dev_kfree_skb (skb);
1768 np->tx_skbuff[i] = NULL;
1769 }
1770 }
1771
1772 return 0;
1773}
1774
64bc40de 1775static void
1da177e4
LT		 1776rio_remove1 (struct pci_dev *pdev)
1777{
1778 struct net_device *dev = pci_get_drvdata (pdev);
1779
1780 if (dev) {
1781 struct netdev_private *np = netdev_priv(dev);
1782
1783 unregister_netdev (dev);
1784 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1785 np->rx_ring_dma);
1786 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1787 np->tx_ring_dma);
1788#ifdef MEM_MAPPING
5e3cc4e3 1789 pci_iounmap(pdev, np->ioaddr);
1da177e4 1790#endif
5e3cc4e3 1791 pci_iounmap(pdev, np->eeprom_addr);
1da177e4
LT		 1792 free_netdev (dev);
1793 pci_release_regions (pdev);
1794 pci_disable_device (pdev);
1795 }
1da177e4
LT		 1796}
1797
1798static struct pci_driver rio_driver = {
1799 .name = "dl2k",
1800 .id_table = rio_pci_tbl,
1801 .probe = rio_probe1,
64bc40de 1802 .remove = rio_remove1,
1da177e4
LT		 1803};
1804
9add4d81 1805module_pci_driver(rio_driver);
1da177e4 1806/*
6aa20a22
JG		 1807
1808Compile command:
1809
1da177e4
LT		 1810gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1811
1812Read Documentation/networking/dl2k.txt for details.
1813
1814*/
1815
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