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6b7c5b94 | 1 | /* |
40263820 | 2 | * Copyright (C) 2005 - 2014 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
6b7c5b94 SP |
23 | #include <linux/delay.h> |
24 | #include <net/tcp.h> | |
25 | #include <net/ip.h> | |
26 | #include <net/ipv6.h> | |
27 | #include <linux/if_vlan.h> | |
28 | #include <linux/workqueue.h> | |
29 | #include <linux/interrupt.h> | |
84517482 | 30 | #include <linux/firmware.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ab1594e9 | 32 | #include <linux/u64_stats_sync.h> |
d658d98a | 33 | #include <linux/cpumask.h> |
6b7c5b94 SP |
34 | |
35 | #include "be_hw.h" | |
045508a8 | 36 | #include "be_roce.h" |
6b7c5b94 | 37 | |
c346e6e5 | 38 | #define DRV_VER "10.4u" |
6b7c5b94 | 39 | #define DRV_NAME "be2net" |
00d3d51e SB |
40 | #define BE_NAME "Emulex BladeEngine2" |
41 | #define BE3_NAME "Emulex BladeEngine3" | |
42 | #define OC_NAME "Emulex OneConnect" | |
fe6d2a38 SP |
43 | #define OC_NAME_BE OC_NAME "(be3)" |
44 | #define OC_NAME_LANCER OC_NAME "(Lancer)" | |
ecedb6ae | 45 | #define OC_NAME_SH OC_NAME "(Skyhawk)" |
f3effb45 | 46 | #define DRV_DESC "Emulex OneConnect NIC Driver" |
6b7c5b94 | 47 | |
c4ca2374 | 48 | #define BE_VENDOR_ID 0x19a2 |
fe6d2a38 | 49 | #define EMULEX_VENDOR_ID 0x10df |
c4ca2374 | 50 | #define BE_DEVICE_ID1 0x211 |
12d7ea2c | 51 | #define BE_DEVICE_ID2 0x221 |
fe6d2a38 SP |
52 | #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ |
53 | #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ | |
54 | #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ | |
12f4d0a8 | 55 | #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ |
ecedb6ae | 56 | #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ |
76b73530 | 57 | #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ |
4762f6ce AK |
58 | #define OC_SUBSYS_DEVICE_ID1 0xE602 |
59 | #define OC_SUBSYS_DEVICE_ID2 0xE642 | |
60 | #define OC_SUBSYS_DEVICE_ID3 0xE612 | |
61 | #define OC_SUBSYS_DEVICE_ID4 0xE652 | |
c4ca2374 | 62 | |
6b7c5b94 | 63 | /* Number of bytes of an RX frame that are copied to skb->data */ |
2e588f84 | 64 | #define BE_HDR_LEN ((u16) 64) |
bb349bb4 ED |
65 | /* allocate extra space to allow tunneling decapsulation without head reallocation */ |
66 | #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) | |
67 | ||
6b7c5b94 SP |
68 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 |
69 | #define BE_MIN_MTU 256 | |
0d3f5cce KA |
70 | #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ |
71 | (ETH_HLEN + ETH_FCS_LEN)) | |
6b7c5b94 SP |
72 | |
73 | #define BE_NUM_VLANS_SUPPORTED 64 | |
2632bafd | 74 | #define BE_MAX_EQD 128u |
6b7c5b94 SP |
75 | #define BE_MAX_TX_FRAG_COUNT 30 |
76 | ||
77 | #define EVNT_Q_LEN 1024 | |
78 | #define TX_Q_LEN 2048 | |
79 | #define TX_CQ_LEN 1024 | |
80 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
81 | #define RX_CQ_LEN 1024 | |
5fb379ee | 82 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
83 | #define MCC_CQ_LEN 256 |
84 | ||
10ef9ab4 | 85 | #define BE2_MAX_RSS_QS 4 |
68d7bdcb SP |
86 | #define BE3_MAX_RSS_QS 16 |
87 | #define BE3_MAX_TX_QS 16 | |
88 | #define BE3_MAX_EVT_QS 16 | |
e3dc867c | 89 | #define BE3_SRIOV_MAX_EVT_QS 8 |
68d7bdcb | 90 | |
f2858738 | 91 | #define MAX_RSS_IFACES 15 |
68d7bdcb SP |
92 | #define MAX_RX_QS 32 |
93 | #define MAX_EVT_QS 32 | |
94 | #define MAX_TX_QS 32 | |
10ef9ab4 | 95 | |
045508a8 | 96 | #define MAX_ROCE_EQS 5 |
68d7bdcb | 97 | #define MAX_MSIX_VECTORS 32 |
92bf14ab | 98 | #define MIN_MSIX_VECTORS 1 |
6b7c5b94 | 99 | #define BE_NAPI_WEIGHT 64 |
10ef9ab4 | 100 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ |
6b7c5b94 SP |
101 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) |
102 | ||
7c5a5242 | 103 | #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ |
8788fdc2 SP |
104 | #define FW_VER_LEN 32 |
105 | ||
e2557877 VD |
106 | #define RSS_INDIR_TABLE_LEN 128 |
107 | #define RSS_HASH_KEY_LEN 40 | |
108 | ||
6b7c5b94 SP |
109 | struct be_dma_mem { |
110 | void *va; | |
111 | dma_addr_t dma; | |
112 | u32 size; | |
113 | }; | |
114 | ||
115 | struct be_queue_info { | |
116 | struct be_dma_mem dma_mem; | |
117 | u16 len; | |
118 | u16 entry_size; /* Size of an element in the queue */ | |
119 | u16 id; | |
120 | u16 tail, head; | |
121 | bool created; | |
122 | atomic_t used; /* Number of valid elements in the queue */ | |
123 | }; | |
124 | ||
5fb379ee SP |
125 | static inline u32 MODULO(u16 val, u16 limit) |
126 | { | |
127 | BUG_ON(limit & (limit - 1)); | |
128 | return val & (limit - 1); | |
129 | } | |
130 | ||
131 | static inline void index_adv(u16 *index, u16 val, u16 limit) | |
132 | { | |
133 | *index = MODULO((*index + val), limit); | |
134 | } | |
135 | ||
136 | static inline void index_inc(u16 *index, u16 limit) | |
137 | { | |
138 | *index = MODULO((*index + 1), limit); | |
139 | } | |
140 | ||
141 | static inline void *queue_head_node(struct be_queue_info *q) | |
142 | { | |
143 | return q->dma_mem.va + q->head * q->entry_size; | |
144 | } | |
145 | ||
146 | static inline void *queue_tail_node(struct be_queue_info *q) | |
147 | { | |
148 | return q->dma_mem.va + q->tail * q->entry_size; | |
149 | } | |
150 | ||
3de09455 SK |
151 | static inline void *queue_index_node(struct be_queue_info *q, u16 index) |
152 | { | |
153 | return q->dma_mem.va + index * q->entry_size; | |
154 | } | |
155 | ||
5fb379ee SP |
156 | static inline void queue_head_inc(struct be_queue_info *q) |
157 | { | |
158 | index_inc(&q->head, q->len); | |
159 | } | |
160 | ||
652bf646 PR |
161 | static inline void index_dec(u16 *index, u16 limit) |
162 | { | |
163 | *index = MODULO((*index - 1), limit); | |
164 | } | |
165 | ||
5fb379ee SP |
166 | static inline void queue_tail_inc(struct be_queue_info *q) |
167 | { | |
168 | index_inc(&q->tail, q->len); | |
169 | } | |
170 | ||
5fb379ee SP |
171 | struct be_eq_obj { |
172 | struct be_queue_info q; | |
173 | char desc[32]; | |
174 | ||
175 | /* Adaptive interrupt coalescing (AIC) info */ | |
176 | bool enable_aic; | |
10ef9ab4 SP |
177 | u32 min_eqd; /* in usecs */ |
178 | u32 max_eqd; /* in usecs */ | |
179 | u32 eqd; /* configured val when aic is off */ | |
180 | u32 cur_eqd; /* in usecs */ | |
5fb379ee | 181 | |
10ef9ab4 | 182 | u8 idx; /* array index */ |
f2f781a7 | 183 | u8 msix_idx; |
d0b9cec3 | 184 | u16 spurious_intr; |
5fb379ee | 185 | struct napi_struct napi; |
10ef9ab4 | 186 | struct be_adapter *adapter; |
d658d98a | 187 | cpumask_var_t affinity_mask; |
6384a4d0 SP |
188 | |
189 | #ifdef CONFIG_NET_RX_BUSY_POLL | |
190 | #define BE_EQ_IDLE 0 | |
191 | #define BE_EQ_NAPI 1 /* napi owns this EQ */ | |
192 | #define BE_EQ_POLL 2 /* poll owns this EQ */ | |
193 | #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) | |
194 | #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ | |
195 | #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ | |
196 | #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) | |
197 | #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) | |
198 | unsigned int state; | |
199 | spinlock_t lock; /* lock to serialize napi and busy-poll */ | |
200 | #endif /* CONFIG_NET_RX_BUSY_POLL */ | |
10ef9ab4 | 201 | } ____cacheline_aligned_in_smp; |
5fb379ee | 202 | |
2632bafd SP |
203 | struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ |
204 | bool enable; | |
205 | u32 min_eqd; /* in usecs */ | |
206 | u32 max_eqd; /* in usecs */ | |
207 | u32 prev_eqd; /* in usecs */ | |
208 | u32 et_eqd; /* configured val when aic is off */ | |
209 | ulong jiffies; | |
210 | u64 rx_pkts_prev; /* Used to calculate RX pps */ | |
211 | u64 tx_reqs_prev; /* Used to calculate TX pps */ | |
212 | }; | |
213 | ||
6384a4d0 SP |
214 | enum { |
215 | NAPI_POLLING, | |
216 | BUSY_POLLING | |
217 | }; | |
218 | ||
5fb379ee SP |
219 | struct be_mcc_obj { |
220 | struct be_queue_info q; | |
221 | struct be_queue_info cq; | |
7a1e9b20 | 222 | bool rearm_cq; |
5fb379ee SP |
223 | }; |
224 | ||
3abcdeda | 225 | struct be_tx_stats { |
ac124ff9 SP |
226 | u64 tx_bytes; |
227 | u64 tx_pkts; | |
228 | u64 tx_reqs; | |
ac124ff9 SP |
229 | u64 tx_compl; |
230 | ulong tx_jiffies; | |
231 | u32 tx_stops; | |
bc617526 | 232 | u32 tx_drv_drops; /* pkts dropped by driver */ |
512bb8a2 KA |
233 | /* the error counters are described in be_ethtool.c */ |
234 | u32 tx_hdr_parse_err; | |
235 | u32 tx_dma_err; | |
236 | u32 tx_tso_err; | |
237 | u32 tx_spoof_check_err; | |
238 | u32 tx_qinq_err; | |
239 | u32 tx_internal_parity_err; | |
ab1594e9 SP |
240 | struct u64_stats_sync sync; |
241 | struct u64_stats_sync sync_compl; | |
6b7c5b94 SP |
242 | }; |
243 | ||
152ffe5b SB |
244 | /* Structure to hold some data of interest obtained from a TX CQE */ |
245 | struct be_tx_compl_info { | |
246 | u8 status; /* Completion status */ | |
247 | u16 end_index; /* Completed TXQ Index */ | |
248 | }; | |
249 | ||
6b7c5b94 | 250 | struct be_tx_obj { |
94d73aaa | 251 | u32 db_offset; |
6b7c5b94 SP |
252 | struct be_queue_info q; |
253 | struct be_queue_info cq; | |
152ffe5b | 254 | struct be_tx_compl_info txcp; |
6b7c5b94 SP |
255 | /* Remember the skbs that were transmitted */ |
256 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
3c8def97 | 257 | struct be_tx_stats stats; |
5f07b3c5 SP |
258 | u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ |
259 | u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ | |
260 | u16 last_req_hdr; /* index of the last req's hdr-wrb */ | |
10ef9ab4 | 261 | } ____cacheline_aligned_in_smp; |
6b7c5b94 SP |
262 | |
263 | /* Struct to remember the pages posted for rx frags */ | |
264 | struct be_rx_page_info { | |
265 | struct page *page; | |
e50287be | 266 | /* set to page-addr for last frag of the page & frag-addr otherwise */ |
fac6da5b | 267 | DEFINE_DMA_UNMAP_ADDR(bus); |
6b7c5b94 | 268 | u16 page_offset; |
e50287be | 269 | bool last_frag; /* last frag of the page */ |
6b7c5b94 SP |
270 | }; |
271 | ||
3abcdeda | 272 | struct be_rx_stats { |
3abcdeda | 273 | u64 rx_bytes; |
3abcdeda | 274 | u64 rx_pkts; |
ac124ff9 SP |
275 | u32 rx_drops_no_skbs; /* skb allocation errors */ |
276 | u32 rx_drops_no_frags; /* HW has no fetched frags */ | |
277 | u32 rx_post_fail; /* page post alloc failures */ | |
ac124ff9 | 278 | u32 rx_compl; |
3abcdeda | 279 | u32 rx_mcast_pkts; |
ac124ff9 | 280 | u32 rx_compl_err; /* completions with err set */ |
ab1594e9 | 281 | struct u64_stats_sync sync; |
3abcdeda SP |
282 | }; |
283 | ||
2e588f84 SP |
284 | struct be_rx_compl_info { |
285 | u32 rss_hash; | |
6709d952 | 286 | u16 vlan_tag; |
2e588f84 | 287 | u16 pkt_size; |
12004ae9 | 288 | u16 port; |
2e588f84 SP |
289 | u8 vlanf; |
290 | u8 num_rcvd; | |
291 | u8 err; | |
292 | u8 ipf; | |
293 | u8 tcpf; | |
294 | u8 udpf; | |
295 | u8 ip_csum; | |
296 | u8 l4_csum; | |
297 | u8 ipv6; | |
f93f160b | 298 | u8 qnq; |
2e588f84 | 299 | u8 pkt_type; |
e38b1706 | 300 | u8 ip_frag; |
c9c47142 | 301 | u8 tunneled; |
2e588f84 SP |
302 | }; |
303 | ||
6b7c5b94 | 304 | struct be_rx_obj { |
3abcdeda | 305 | struct be_adapter *adapter; |
6b7c5b94 SP |
306 | struct be_queue_info q; |
307 | struct be_queue_info cq; | |
2e588f84 | 308 | struct be_rx_compl_info rxcp; |
6b7c5b94 | 309 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; |
3abcdeda SP |
310 | struct be_rx_stats stats; |
311 | u8 rss_id; | |
312 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | |
10ef9ab4 | 313 | } ____cacheline_aligned_in_smp; |
6b7c5b94 | 314 | |
609ff3bb | 315 | struct be_drv_stats { |
9ae081c6 | 316 | u32 be_on_die_temperature; |
ac124ff9 | 317 | u32 eth_red_drops; |
d3de1540 | 318 | u32 dma_map_errors; |
ac124ff9 SP |
319 | u32 rx_drops_no_pbuf; |
320 | u32 rx_drops_no_txpb; | |
321 | u32 rx_drops_no_erx_descr; | |
322 | u32 rx_drops_no_tpre_descr; | |
323 | u32 rx_drops_too_many_frags; | |
ac124ff9 SP |
324 | u32 forwarded_packets; |
325 | u32 rx_drops_mtu; | |
326 | u32 rx_crc_errors; | |
327 | u32 rx_alignment_symbol_errors; | |
328 | u32 rx_pause_frames; | |
329 | u32 rx_priority_pause_frames; | |
330 | u32 rx_control_frames; | |
331 | u32 rx_in_range_errors; | |
332 | u32 rx_out_range_errors; | |
333 | u32 rx_frame_too_long; | |
18fb06a1 | 334 | u32 rx_address_filtered; |
ac124ff9 SP |
335 | u32 rx_dropped_too_small; |
336 | u32 rx_dropped_too_short; | |
337 | u32 rx_dropped_header_too_small; | |
338 | u32 rx_dropped_tcp_length; | |
339 | u32 rx_dropped_runt; | |
340 | u32 rx_ip_checksum_errs; | |
341 | u32 rx_tcp_checksum_errs; | |
342 | u32 rx_udp_checksum_errs; | |
343 | u32 tx_pauseframes; | |
344 | u32 tx_priority_pauseframes; | |
345 | u32 tx_controlframes; | |
346 | u32 rxpp_fifo_overflow_drop; | |
347 | u32 rx_input_fifo_overflow_drop; | |
348 | u32 pmem_fifo_overflow_drop; | |
349 | u32 jabber_events; | |
461ae379 AK |
350 | u32 rx_roce_bytes_lsd; |
351 | u32 rx_roce_bytes_msd; | |
352 | u32 rx_roce_frames; | |
353 | u32 roce_drops_payload_len; | |
354 | u32 roce_drops_crc; | |
609ff3bb AK |
355 | }; |
356 | ||
c502224e SK |
357 | /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ |
358 | #define BE_RESET_VLAN_TAG_ID 0xFFFF | |
359 | ||
64600ea5 | 360 | struct be_vf_cfg { |
11ac75ed SP |
361 | unsigned char mac_addr[ETH_ALEN]; |
362 | int if_handle; | |
363 | int pmac_id; | |
364 | u16 vlan_tag; | |
365 | u32 tx_rate; | |
bdce2ad7 | 366 | u32 plink_tracking; |
435452aa | 367 | u32 privileges; |
64600ea5 AK |
368 | }; |
369 | ||
39f1d94d SP |
370 | enum vf_state { |
371 | ENABLED = 0, | |
372 | ASSIGNED = 1 | |
373 | }; | |
374 | ||
83b06116 VV |
375 | #define BE_FLAGS_LINK_STATUS_INIT BIT(1) |
376 | #define BE_FLAGS_SRIOV_ENABLED BIT(2) | |
377 | #define BE_FLAGS_WORKER_SCHEDULED BIT(3) | |
83b06116 VV |
378 | #define BE_FLAGS_NAPI_ENABLED BIT(6) |
379 | #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) | |
380 | #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) | |
381 | #define BE_FLAGS_SETUP_DONE BIT(9) | |
21252377 | 382 | #define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10) |
eb7dd46c | 383 | #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) |
b236916a | 384 | |
c9c47142 SP |
385 | #define BE_UC_PMAC_COUNT 30 |
386 | #define BE_VF_UC_PMAC_COUNT 2 | |
f0613380 | 387 | |
5c510811 SK |
388 | /* Ethtool set_dump flags */ |
389 | #define LANCER_INITIATE_FW_DUMP 0x1 | |
f0613380 | 390 | #define LANCER_DELETE_FW_DUMP 0x2 |
5c510811 | 391 | |
42f11cf2 | 392 | struct phy_info { |
21252377 VV |
393 | /* From SFF-8472 spec */ |
394 | #define SFP_VENDOR_NAME_LEN 17 | |
42f11cf2 AK |
395 | u8 transceiver; |
396 | u8 autoneg; | |
397 | u8 fc_autoneg; | |
398 | u8 port_type; | |
399 | u16 phy_type; | |
400 | u16 interface_type; | |
401 | u32 misc_params; | |
402 | u16 auto_speeds_supported; | |
403 | u16 fixed_speeds_supported; | |
404 | int link_speed; | |
42f11cf2 AK |
405 | u32 advertising; |
406 | u32 supported; | |
6809cee0 | 407 | u8 cable_type; |
21252377 VV |
408 | u8 vendor_name[SFP_VENDOR_NAME_LEN]; |
409 | u8 vendor_pn[SFP_VENDOR_NAME_LEN]; | |
42f11cf2 AK |
410 | }; |
411 | ||
92bf14ab SP |
412 | struct be_resources { |
413 | u16 max_vfs; /* Total VFs "really" supported by FW/HW */ | |
414 | u16 max_mcast_mac; | |
415 | u16 max_tx_qs; | |
416 | u16 max_rss_qs; | |
417 | u16 max_rx_qs; | |
f2858738 | 418 | u16 max_cq_count; |
92bf14ab SP |
419 | u16 max_uc_mac; /* Max UC MACs programmable */ |
420 | u16 max_vlans; /* Number of vlans supported */ | |
f2858738 VV |
421 | u16 max_iface_count; |
422 | u16 max_mcc_count; | |
92bf14ab SP |
423 | u16 max_evt_qs; |
424 | u32 if_cap_flags; | |
10cccf60 | 425 | u32 vf_if_cap_flags; /* VF if capability flags */ |
92bf14ab SP |
426 | }; |
427 | ||
e2557877 VD |
428 | struct rss_info { |
429 | u64 rss_flags; | |
430 | u8 rsstable[RSS_INDIR_TABLE_LEN]; | |
431 | u8 rss_queue[RSS_INDIR_TABLE_LEN]; | |
432 | u8 rss_hkey[RSS_HASH_KEY_LEN]; | |
433 | }; | |
434 | ||
804abcdb SB |
435 | /* Macros to read/write the 'features' word of be_wrb_params structure. |
436 | */ | |
437 | #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT | |
438 | #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) | |
439 | ||
440 | #define BE_WRB_F_GET(word, name) \ | |
441 | (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) | |
442 | ||
443 | #define BE_WRB_F_SET(word, name, val) \ | |
444 | ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) | |
445 | ||
446 | /* Feature/offload bits */ | |
447 | enum { | |
448 | BE_WRB_F_CRC_BIT, /* Ethernet CRC */ | |
449 | BE_WRB_F_IPCS_BIT, /* IP csum */ | |
450 | BE_WRB_F_TCPCS_BIT, /* TCP csum */ | |
451 | BE_WRB_F_UDPCS_BIT, /* UDP csum */ | |
452 | BE_WRB_F_LSO_BIT, /* LSO */ | |
453 | BE_WRB_F_LSO6_BIT, /* LSO6 */ | |
454 | BE_WRB_F_VLAN_BIT, /* VLAN */ | |
455 | BE_WRB_F_VLAN_SKIP_HW_BIT /* Skip VLAN tag (workaround) */ | |
456 | }; | |
457 | ||
458 | /* The structure below provides a HW-agnostic abstraction of WRB params | |
459 | * retrieved from a TX skb. This is in turn passed to chip specific routines | |
460 | * during transmit, to set the corresponding params in the WRB. | |
461 | */ | |
462 | struct be_wrb_params { | |
463 | u32 features; /* Feature bits */ | |
464 | u16 vlan_tag; /* VLAN tag */ | |
465 | u16 lso_mss; /* MSS for LSO */ | |
466 | }; | |
467 | ||
6b7c5b94 SP |
468 | struct be_adapter { |
469 | struct pci_dev *pdev; | |
470 | struct net_device *netdev; | |
471 | ||
c5b3ad4c | 472 | u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ |
8788fdc2 | 473 | u8 __iomem *db; /* Door Bell */ |
25848c90 | 474 | u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */ |
8788fdc2 | 475 | |
2984961c | 476 | struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ |
8788fdc2 SP |
477 | struct be_dma_mem mbox_mem; |
478 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
479 | * is stored for freeing purpose */ | |
480 | struct be_dma_mem mbox_mem_alloced; | |
481 | ||
482 | struct be_mcc_obj mcc_obj; | |
483 | spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ | |
484 | spinlock_t mcc_cq_lock; | |
6b7c5b94 | 485 | |
92bf14ab SP |
486 | u16 cfg_num_qs; /* configured via set-channels */ |
487 | u16 num_evt_qs; | |
488 | u16 num_msix_vec; | |
489 | struct be_eq_obj eq_obj[MAX_EVT_QS]; | |
10ef9ab4 | 490 | struct msix_entry msix_entries[MAX_MSIX_VECTORS]; |
6b7c5b94 SP |
491 | bool isr_registered; |
492 | ||
493 | /* TX Rings */ | |
92bf14ab | 494 | u16 num_tx_qs; |
3c8def97 | 495 | struct be_tx_obj tx_obj[MAX_TX_QS]; |
6b7c5b94 SP |
496 | |
497 | /* Rx rings */ | |
92bf14ab | 498 | u16 num_rx_qs; |
71bb8bd0 VV |
499 | u16 num_rss_qs; |
500 | u16 need_def_rxq; | |
10ef9ab4 | 501 | struct be_rx_obj rx_obj[MAX_RX_QS]; |
6b7c5b94 SP |
502 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ |
503 | ||
609ff3bb | 504 | struct be_drv_stats drv_stats; |
2632bafd | 505 | struct be_aic_obj aic_obj[MAX_EVT_QS]; |
cc4ce020 SK |
506 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
507 | u16 recommended_prio; /* Recommended Priority */ | |
5b8821b7 | 508 | struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ |
6b7c5b94 | 509 | |
3abcdeda | 510 | struct be_dma_mem stats_cmd; |
6b7c5b94 SP |
511 | /* Work queue used to perform periodic tasks like getting statistics */ |
512 | struct delayed_work work; | |
609ff3bb | 513 | u16 work_counter; |
6b7c5b94 | 514 | |
eb7dd46c | 515 | struct delayed_work be_err_detection_work; |
b236916a | 516 | u32 flags; |
f25b119c | 517 | u32 cmd_privileges; |
6b7c5b94 | 518 | /* Ethtool knobs and info */ |
6b7c5b94 | 519 | char fw_ver[FW_VER_LEN]; |
eeb65ced | 520 | char fw_on_flash[FW_VER_LEN]; |
f66b7cfd SP |
521 | |
522 | /* IFACE filtering fields */ | |
30128031 | 523 | int if_handle; /* Used to configure filtering */ |
f66b7cfd | 524 | u32 if_flags; /* Interface filtering flags */ |
fbc13f01 | 525 | u32 *pmac_id; /* MAC addr handle used by BE card */ |
f66b7cfd SP |
526 | u32 uc_macs; /* Count of secondary UC MAC programmed */ |
527 | unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; | |
528 | u16 vlans_added; | |
529 | ||
1a642469 | 530 | u32 beacon_state; /* for set_phys_id */ |
6b7c5b94 | 531 | |
f67ef7ba | 532 | bool eeh_error; |
6589ade0 | 533 | bool fw_timeout; |
f67ef7ba PR |
534 | bool hw_error; |
535 | ||
6b7c5b94 | 536 | u32 port_num; |
21252377 | 537 | char port_name; |
f93f160b | 538 | u8 mc_type; |
3486be29 | 539 | u32 function_mode; |
3abcdeda | 540 | u32 function_caps; |
9e90c961 AK |
541 | u32 rx_fc; /* Rx flow control */ |
542 | u32 tx_fc; /* Tx flow control */ | |
b2aebe6d | 543 | bool stats_cmd_sent; |
045508a8 | 544 | struct { |
045508a8 PP |
545 | u32 size; |
546 | u32 total_size; | |
547 | u64 io_addr; | |
548 | } roce_db; | |
549 | u32 num_msix_roce_vec; | |
550 | struct ocrdma_dev *ocrdma_dev; | |
551 | struct list_head entry; | |
552 | ||
dd131e76 | 553 | u32 flash_status; |
5eeff635 | 554 | struct completion et_cmd_compl; |
ba343c77 | 555 | |
bec84e6b | 556 | struct be_resources pool_res; /* resources available for the port */ |
92bf14ab SP |
557 | struct be_resources res; /* resources available for the func */ |
558 | u16 num_vfs; /* Number of VFs provisioned by PF */ | |
39f1d94d | 559 | u8 virtfn; |
11ac75ed SP |
560 | struct be_vf_cfg *vf_cfg; |
561 | bool be3_native; | |
fe6d2a38 | 562 | u32 sli_family; |
9e1453c5 | 563 | u8 hba_port_num; |
3968fa1e | 564 | u16 pvid; |
c9c47142 | 565 | __be16 vxlan_port; |
630f4b70 | 566 | int vxlan_port_count; |
42f11cf2 | 567 | struct phy_info phy; |
4762f6ce | 568 | u8 wol_cap; |
76a9e08e | 569 | bool wol_en; |
0ad3157e | 570 | u16 asic_rev; |
bc0c3405 | 571 | u16 qnq_vid; |
941a77d5 | 572 | u32 msg_enable; |
7aeb2156 | 573 | int be_get_temp_freq; |
d5c18473 | 574 | u8 pf_number; |
e2557877 | 575 | struct rss_info rss_info; |
6b7c5b94 SP |
576 | }; |
577 | ||
39f1d94d | 578 | #define be_physfn(adapter) (!adapter->virtfn) |
2c7a9dc1 | 579 | #define be_virtfn(adapter) (adapter->virtfn) |
f174c7ec VV |
580 | #define sriov_enabled(adapter) (adapter->flags & \ |
581 | BE_FLAGS_SRIOV_ENABLED) | |
bec84e6b | 582 | |
11ac75ed SP |
583 | #define for_all_vfs(adapter, vf_cfg, i) \ |
584 | for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ | |
585 | i++, vf_cfg++) | |
ba343c77 | 586 | |
5b8821b7 SP |
587 | #define ON 1 |
588 | #define OFF 0 | |
ca34fe38 | 589 | |
92bf14ab SP |
590 | #define be_max_vlans(adapter) (adapter->res.max_vlans) |
591 | #define be_max_uc(adapter) (adapter->res.max_uc_mac) | |
592 | #define be_max_mc(adapter) (adapter->res.max_mcast_mac) | |
bec84e6b | 593 | #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) |
92bf14ab SP |
594 | #define be_max_rss(adapter) (adapter->res.max_rss_qs) |
595 | #define be_max_txqs(adapter) (adapter->res.max_tx_qs) | |
596 | #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) | |
597 | #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) | |
598 | #define be_max_eqs(adapter) (adapter->res.max_evt_qs) | |
599 | #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) | |
600 | ||
601 | static inline u16 be_max_qs(struct be_adapter *adapter) | |
602 | { | |
603 | /* If no RSS, need atleast the one def RXQ */ | |
604 | u16 num = max_t(u16, be_max_rss(adapter), 1); | |
605 | ||
606 | num = min(num, be_max_eqs(adapter)); | |
607 | return min_t(u16, num, num_online_cpus()); | |
608 | } | |
609 | ||
f93f160b VV |
610 | /* Is BE in pvid_tagging mode */ |
611 | #define be_pvid_tagging_enabled(adapter) (adapter->pvid) | |
612 | ||
613 | /* Is BE in QNQ multi-channel mode */ | |
66064dbc | 614 | #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) |
f93f160b | 615 | |
ca34fe38 SP |
616 | #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ |
617 | adapter->pdev->device == OC_DEVICE_ID4) | |
fe6d2a38 | 618 | |
76b73530 PR |
619 | #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ |
620 | adapter->pdev->device == OC_DEVICE_ID6) | |
d3bd3a5e | 621 | |
ca34fe38 SP |
622 | #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ |
623 | adapter->pdev->device == OC_DEVICE_ID2) | |
624 | ||
625 | #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ | |
626 | adapter->pdev->device == OC_DEVICE_ID1) | |
627 | ||
628 | #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) | |
d3bd3a5e | 629 | |
dbf0f2a7 SP |
630 | #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ |
631 | (adapter->function_mode & RDMA_ENABLED)) | |
045508a8 | 632 | |
0fc0b732 | 633 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 | 634 | |
ac6a0c4a | 635 | #define msix_enabled(adapter) (adapter->num_msix_vec > 0) |
10ef9ab4 SP |
636 | #define num_irqs(adapter) (msix_enabled(adapter) ? \ |
637 | adapter->num_msix_vec : 1) | |
638 | #define tx_stats(txo) (&(txo)->stats) | |
639 | #define rx_stats(rxo) (&(rxo)->stats) | |
6b7c5b94 | 640 | |
10ef9ab4 SP |
641 | /* The default RXQ is the last RXQ */ |
642 | #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) | |
6b7c5b94 | 643 | |
3abcdeda SP |
644 | #define for_all_rx_queues(adapter, rxo, i) \ |
645 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ | |
646 | i++, rxo++) | |
647 | ||
3abcdeda | 648 | #define for_all_rss_queues(adapter, rxo, i) \ |
71bb8bd0 | 649 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \ |
3abcdeda SP |
650 | i++, rxo++) |
651 | ||
3c8def97 SP |
652 | #define for_all_tx_queues(adapter, txo, i) \ |
653 | for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ | |
654 | i++, txo++) | |
655 | ||
10ef9ab4 SP |
656 | #define for_all_evt_queues(adapter, eqo, i) \ |
657 | for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ | |
658 | i++, eqo++) | |
659 | ||
6384a4d0 SP |
660 | #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ |
661 | for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ | |
662 | i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) | |
663 | ||
a4906ea0 SP |
664 | #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ |
665 | for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ | |
666 | i += adapter->num_evt_qs, txo += adapter->num_evt_qs) | |
667 | ||
10ef9ab4 SP |
668 | #define is_mcc_eqo(eqo) (eqo->idx == 0) |
669 | #define mcc_eqo(adapter) (&adapter->eq_obj[0]) | |
670 | ||
6b7c5b94 SP |
671 | #define PAGE_SHIFT_4K 12 |
672 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
673 | ||
674 | /* Returns number of pages spanned by the data starting at the given addr */ | |
675 | #define PAGES_4K_SPANNED(_address, size) \ | |
676 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
677 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
678 | ||
6b7c5b94 SP |
679 | /* Returns bit offset within a DWORD of a bitfield */ |
680 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
681 | (((size_t)&(((_struct *)0)->field))%32) | |
682 | ||
683 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
684 | static inline u32 amap_mask(u32 bitsize) | |
685 | { | |
686 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
687 | } | |
688 | ||
689 | static inline void | |
690 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
691 | { | |
692 | u32 *dw = (u32 *) ptr + dw_offset; | |
693 | *dw &= ~(mask << offset); | |
694 | *dw |= (mask & value) << offset; | |
695 | } | |
696 | ||
697 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
698 | amap_set(ptr, \ | |
699 | offsetof(_struct, field)/32, \ | |
700 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
701 | AMAP_BIT_OFFSET(_struct, field), \ | |
702 | val) | |
703 | ||
704 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
705 | { | |
706 | u32 *dw = (u32 *) ptr; | |
707 | return mask & (*(dw + dw_offset) >> offset); | |
708 | } | |
709 | ||
710 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
711 | amap_get(ptr, \ | |
712 | offsetof(_struct, field)/32, \ | |
713 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
714 | AMAP_BIT_OFFSET(_struct, field)) | |
715 | ||
c3c18bc1 SP |
716 | #define GET_RX_COMPL_V0_BITS(field, ptr) \ |
717 | AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) | |
718 | ||
719 | #define GET_RX_COMPL_V1_BITS(field, ptr) \ | |
720 | AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) | |
721 | ||
722 | #define GET_TX_COMPL_BITS(field, ptr) \ | |
723 | AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) | |
724 | ||
725 | #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ | |
726 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) | |
727 | ||
6b7c5b94 SP |
728 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) |
729 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
730 | static inline void swap_dws(void *wrb, int len) | |
731 | { | |
732 | #ifdef __BIG_ENDIAN | |
733 | u32 *dw = wrb; | |
734 | BUG_ON(len % 4); | |
735 | do { | |
736 | *dw = cpu_to_le32(*dw); | |
737 | dw++; | |
738 | len -= 4; | |
739 | } while (len); | |
740 | #endif /* __BIG_ENDIAN */ | |
741 | } | |
742 | ||
0532d4e3 KA |
743 | #define be_cmd_status(status) (status > 0 ? -EIO : status) |
744 | ||
6b7c5b94 SP |
745 | static inline u8 is_tcp_pkt(struct sk_buff *skb) |
746 | { | |
747 | u8 val = 0; | |
748 | ||
749 | if (ip_hdr(skb)->version == 4) | |
750 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
751 | else if (ip_hdr(skb)->version == 6) | |
752 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
753 | ||
754 | return val; | |
755 | } | |
756 | ||
757 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
758 | { | |
759 | u8 val = 0; | |
760 | ||
761 | if (ip_hdr(skb)->version == 4) | |
762 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
763 | else if (ip_hdr(skb)->version == 6) | |
764 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
765 | ||
766 | return val; | |
767 | } | |
768 | ||
93040ae5 SK |
769 | static inline bool is_ipv4_pkt(struct sk_buff *skb) |
770 | { | |
e8efcec5 | 771 | return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; |
93040ae5 SK |
772 | } |
773 | ||
4b972914 AK |
774 | static inline bool be_multi_rxq(const struct be_adapter *adapter) |
775 | { | |
776 | return adapter->num_rx_qs > 1; | |
777 | } | |
778 | ||
6589ade0 SP |
779 | static inline bool be_error(struct be_adapter *adapter) |
780 | { | |
f67ef7ba PR |
781 | return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; |
782 | } | |
783 | ||
d23e946c | 784 | static inline bool be_hw_error(struct be_adapter *adapter) |
f67ef7ba PR |
785 | { |
786 | return adapter->eeh_error || adapter->hw_error; | |
787 | } | |
788 | ||
789 | static inline void be_clear_all_error(struct be_adapter *adapter) | |
790 | { | |
791 | adapter->eeh_error = false; | |
792 | adapter->hw_error = false; | |
793 | adapter->fw_timeout = false; | |
6589ade0 SP |
794 | } |
795 | ||
31886e87 JP |
796 | void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
797 | u16 num_popped); | |
798 | void be_link_status_update(struct be_adapter *adapter, u8 link_status); | |
799 | void be_parse_stats(struct be_adapter *adapter); | |
800 | int be_load_fw(struct be_adapter *adapter, u8 *func); | |
801 | bool be_is_wol_supported(struct be_adapter *adapter); | |
802 | bool be_pause_supported(struct be_adapter *adapter); | |
803 | u32 be_get_fw_log_level(struct be_adapter *adapter); | |
68d7bdcb SP |
804 | int be_update_queues(struct be_adapter *adapter); |
805 | int be_poll(struct napi_struct *napi, int budget); | |
941a77d5 | 806 | |
045508a8 PP |
807 | /* |
808 | * internal function to initialize-cleanup roce device. | |
809 | */ | |
31886e87 JP |
810 | void be_roce_dev_add(struct be_adapter *); |
811 | void be_roce_dev_remove(struct be_adapter *); | |
045508a8 PP |
812 | |
813 | /* | |
814 | * internal function to open-close roce device during ifup-ifdown. | |
815 | */ | |
31886e87 JP |
816 | void be_roce_dev_open(struct be_adapter *); |
817 | void be_roce_dev_close(struct be_adapter *); | |
d114f99a | 818 | void be_roce_dev_shutdown(struct be_adapter *); |
045508a8 | 819 | |
6b7c5b94 | 820 | #endif /* BE_H */ |