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ip_tunnel: Call ip_tunnel_core_init() from inet_init()
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
d19261b8 2 * Copyright (C) 2005 - 2015 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
21252377
VV		 22static char *be_port_misconfig_evt_desc[] = {
23 "A valid SFP module detected",
24 "Optics faulted/ incorrectly installed/ not installed.",
25 "Optics of two types installed.",
26 "Incompatible optics.",
27 "Unknown port SFP status"
28};
29
30static char *be_port_misconfig_remedy_desc[] = {
31 "",
32 "Reseat optics. If issue not resolved, replace",
33 "Remove one optic or install matching pair of optics",
34 "Replace with compatible optics for card to function",
35 ""
36};
37
f25b119c
PR		 38static struct be_cmd_priv_map cmd_priv_map[] = {
39 {
40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
41 CMD_SUBSYSTEM_ETH,
42 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
43 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
44 },
45 {
46 OPCODE_COMMON_GET_FLOW_CONTROL,
47 CMD_SUBSYSTEM_COMMON,
48 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_SET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_ETH_GET_PPORT_STATS,
59 CMD_SUBSYSTEM_ETH,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_COMMON_GET_PHY_DETAILS,
65 CMD_SUBSYSTEM_COMMON,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 }
69};
70
a2cc4e0b 71static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 72{
73 int i;
74 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
75 u32 cmd_privileges = adapter->cmd_privileges;
76
77 for (i = 0; i < num_entries; i++)
78 if (opcode == cmd_priv_map[i].opcode &&
79 subsystem == cmd_priv_map[i].subsystem)
80 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
81 return false;
82
83 return true;
84}
85
3de09455
SK		 86static inline void *embedded_payload(struct be_mcc_wrb *wrb)
87{
88 return wrb->payload.embedded_payload;
89}
609ff3bb 90
efaa408e 91static int be_mcc_notify(struct be_adapter *adapter)
5fb379ee 92{
8788fdc2 93 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 94 u32 val = 0;
95
954f6825 96 if (be_check_error(adapter, BE_ERROR_ANY))
efaa408e 97 return -EIO;
7acc2087 98
5fb379ee
SP		 99 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
100 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 101
102 wmb();
8788fdc2 103 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
efaa408e
SR		 104
105 return 0;
5fb379ee
SP		 106}
107
108/* To check if valid bit is set, check the entire word as we don't know
109 * the endianness of the data (old entry is host endian while a new entry is
110 * little endian) */
efd2e40a 111static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 112{
9e9ff4b7
SP		 113 u32 flags;
114
5fb379ee 115 if (compl->flags != 0) {
9e9ff4b7
SP		 116 flags = le32_to_cpu(compl->flags);
117 if (flags & CQE_FLAGS_VALID_MASK) {
118 compl->flags = flags;
119 return true;
120 }
5fb379ee 121 }
9e9ff4b7 122 return false;
5fb379ee
SP		 123}
124
125/* Need to reset the entire word that houses the valid bit */
efd2e40a 126static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 127{
128 compl->flags = 0;
129}
130
652bf646
PR		 131static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
132{
133 unsigned long addr;
134
135 addr = tag1;
136 addr = ((addr << 16) << 16) | tag0;
137 return (void *)addr;
138}
139
4c60005f
KA		 140static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
141{
142 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
143 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
144 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
77be8c1c 145 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
4c60005f
KA		 146 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
147 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
148 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
149 return true;
150 else
151 return false;
152}
153
559b633f
SP		 154/* Place holder for all the async MCC cmds wherein the caller is not in a busy
155 * loop (has not issued be_mcc_notify_wait())
156 */
157static void be_async_cmd_process(struct be_adapter *adapter,
158 struct be_mcc_compl *compl,
159 struct be_cmd_resp_hdr *resp_hdr)
160{
161 enum mcc_base_status base_status = base_status(compl->status);
162 u8 opcode = 0, subsystem = 0;
163
164 if (resp_hdr) {
165 opcode = resp_hdr->opcode;
166 subsystem = resp_hdr->subsystem;
167 }
168
169 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
170 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
171 complete(&adapter->et_cmd_compl);
172 return;
173 }
174
9c855975
SR		 175 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
176 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
177 complete(&adapter->et_cmd_compl);
178 return;
179 }
180
559b633f
SP		 181 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
182 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
183 subsystem == CMD_SUBSYSTEM_COMMON) {
184 adapter->flash_status = compl->status;
185 complete(&adapter->et_cmd_compl);
186 return;
187 }
188
189 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
190 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
191 subsystem == CMD_SUBSYSTEM_ETH &&
192 base_status == MCC_STATUS_SUCCESS) {
193 be_parse_stats(adapter);
194 adapter->stats_cmd_sent = false;
195 return;
196 }
197
198 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
199 subsystem == CMD_SUBSYSTEM_COMMON) {
200 if (base_status == MCC_STATUS_SUCCESS) {
201 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
202 (void *)resp_hdr;
29e9122b 203 adapter->hwmon_info.be_on_die_temp =
559b633f
SP		 204 resp->on_die_temperature;
205 } else {
206 adapter->be_get_temp_freq = 0;
29e9122b
VD		 207 adapter->hwmon_info.be_on_die_temp =
208 BE_INVALID_DIE_TEMP;
559b633f
SP		 209 }
210 return;
211 }
212}
213
8788fdc2 214static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 215 struct be_mcc_compl *compl)
5fb379ee 216{
4c60005f
KA		 217 enum mcc_base_status base_status;
218 enum mcc_addl_status addl_status;
652bf646
PR		 219 struct be_cmd_resp_hdr *resp_hdr;
220 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 221
222 /* Just swap the status to host endian; mcc tag is opaquely copied
223 * from mcc_wrb */
224 be_dws_le_to_cpu(compl, 4);
225
4c60005f
KA		 226 base_status = base_status(compl->status);
227 addl_status = addl_status(compl->status);
96c9b2e4 228
652bf646 229 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 230 if (resp_hdr) {
231 opcode = resp_hdr->opcode;
232 subsystem = resp_hdr->subsystem;
233 }
234
559b633f 235 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 236
559b633f
SP		 237 if (base_status != MCC_STATUS_SUCCESS &&
238 !be_skip_err_log(opcode, base_status, addl_status)) {
4c60005f 239 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 240 dev_warn(&adapter->pdev->dev,
522609f2 241 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 242 opcode, subsystem);
2b3f291b 243 } else {
97f1d8cd
VV		 244 dev_err(&adapter->pdev->dev,
245 "opcode %d-%d failed:status %d-%d\n",
4c60005f 246 opcode, subsystem, base_status, addl_status);
2b3f291b 247 }
5fb379ee 248 }
4c60005f 249 return compl->status;
5fb379ee
SP		 250}
251
a8f447bd 252/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 253static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 254 struct be_mcc_compl *compl)
a8f447bd 255{
3acf19d9
SP		 256 struct be_async_event_link_state *evt =
257 (struct be_async_event_link_state *)compl;
258
b236916a 259 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 260 adapter->phy.link_speed = -1;
b236916a 261
bdce2ad7
SR		 262 /* On BEx the FW does not send a separate link status
263 * notification for physical and logical link.
264 * On other chips just process the logical link
265 * status notification
266 */
267 if (!BEx_chip(adapter) &&
2e177a5c
PR		 268 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
269 return;
270
b236916a
AK		 271 /* For the initial link status do not rely on the ASYNC event as
272 * it may not be received in some cases.
273 */
274 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 275 be_link_status_update(adapter,
276 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 277}
278
21252377
VV		 279static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
280 struct be_mcc_compl *compl)
281{
282 struct be_async_event_misconfig_port *evt =
283 (struct be_async_event_misconfig_port *)compl;
284 u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
285 struct device *dev = &adapter->pdev->dev;
286 u8 port_misconfig_evt;
287
288 port_misconfig_evt =
289 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
290
291 /* Log an error message that would allow a user to determine
292 * whether the SFPs have an issue
293 */
294 dev_info(dev, "Port %c: %s %s", adapter->port_name,
295 be_port_misconfig_evt_desc[port_misconfig_evt],
296 be_port_misconfig_remedy_desc[port_misconfig_evt]);
297
298 if (port_misconfig_evt == INCOMPATIBLE_SFP)
299 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
300}
301
cc4ce020
SK		 302/* Grp5 CoS Priority evt */
303static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 304 struct be_mcc_compl *compl)
cc4ce020 305{
3acf19d9
SP		 306 struct be_async_event_grp5_cos_priority *evt =
307 (struct be_async_event_grp5_cos_priority *)compl;
308
cc4ce020
SK		 309 if (evt->valid) {
310 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 311 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 312 adapter->recommended_prio =
313 evt->reco_default_priority << VLAN_PRIO_SHIFT;
314 }
315}
316
323ff71e 317/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 318static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 319 struct be_mcc_compl *compl)
cc4ce020 320{
3acf19d9
SP		 321 struct be_async_event_grp5_qos_link_speed *evt =
322 (struct be_async_event_grp5_qos_link_speed *)compl;
323
323ff71e
SP		 324 if (adapter->phy.link_speed >= 0 &&
325 evt->physical_port == adapter->port_num)
326 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 327}
328
3968fa1e
AK		 329/*Grp5 PVID evt*/
330static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 331 struct be_mcc_compl *compl)
3968fa1e 332{
3acf19d9
SP		 333 struct be_async_event_grp5_pvid_state *evt =
334 (struct be_async_event_grp5_pvid_state *)compl;
335
bdac85b5 336 if (evt->enabled) {
939cf306 337 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 338 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
339 } else {
3968fa1e 340 adapter->pvid = 0;
bdac85b5 341 }
3968fa1e
AK		 342}
343
760c295e
VD		 344#define MGMT_ENABLE_MASK 0x4
345static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
346 struct be_mcc_compl *compl)
347{
348 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
349 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
350
351 if (evt_dw1 & MGMT_ENABLE_MASK) {
352 adapter->flags |= BE_FLAGS_OS2BMC;
353 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
354 } else {
355 adapter->flags &= ~BE_FLAGS_OS2BMC;
356 }
357}
358
cc4ce020 359static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 360 struct be_mcc_compl *compl)
cc4ce020 361{
3acf19d9
SP		 362 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
363 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 364
365 switch (event_type) {
366 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 367 be_async_grp5_cos_priority_process(adapter, compl);
368 break;
cc4ce020 369 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 370 be_async_grp5_qos_speed_process(adapter, compl);
371 break;
3968fa1e 372 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 373 be_async_grp5_pvid_state_process(adapter, compl);
374 break;
760c295e
VD		 375 /* Async event to disable/enable os2bmc and/or mac-learning */
376 case ASYNC_EVENT_FW_CONTROL:
377 be_async_grp5_fw_control_process(adapter, compl);
378 break;
cc4ce020 379 default:
cc4ce020
SK		 380 break;
381 }
382}
383
bc0c3405 384static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 385 struct be_mcc_compl *cmp)
bc0c3405
AK		 386{
387 u8 event_type = 0;
504fbf1e 388 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 389
3acf19d9
SP		 390 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
391 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 392
393 switch (event_type) {
394 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
395 if (evt->valid)
396 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
397 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
398 break;
399 default:
05ccaa2b
VV		 400 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
401 event_type);
bc0c3405
AK		 402 break;
403 }
404}
405
21252377
VV		 406static void be_async_sliport_evt_process(struct be_adapter *adapter,
407 struct be_mcc_compl *cmp)
408{
409 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
410 ASYNC_EVENT_TYPE_MASK;
411
412 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
413 be_async_port_misconfig_event_process(adapter, cmp);
414}
415
3acf19d9 416static inline bool is_link_state_evt(u32 flags)
a8f447bd 417{
3acf19d9
SP		 418 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
419 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 420}
5fb379ee 421
3acf19d9 422static inline bool is_grp5_evt(u32 flags)
cc4ce020 423{
3acf19d9
SP		 424 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
425 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 426}
427
3acf19d9 428static inline bool is_dbg_evt(u32 flags)
bc0c3405 429{
3acf19d9
SP		 430 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
431 ASYNC_EVENT_CODE_QNQ;
432}
433
21252377
VV		 434static inline bool is_sliport_evt(u32 flags)
435{
436 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
437 ASYNC_EVENT_CODE_SLIPORT;
438}
439
3acf19d9
SP		 440static void be_mcc_event_process(struct be_adapter *adapter,
441 struct be_mcc_compl *compl)
442{
443 if (is_link_state_evt(compl->flags))
444 be_async_link_state_process(adapter, compl);
445 else if (is_grp5_evt(compl->flags))
446 be_async_grp5_evt_process(adapter, compl);
447 else if (is_dbg_evt(compl->flags))
448 be_async_dbg_evt_process(adapter, compl);
21252377
VV		 449 else if (is_sliport_evt(compl->flags))
450 be_async_sliport_evt_process(adapter, compl);
bc0c3405
AK		 451}
452
efd2e40a 453static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 454{
8788fdc2 455 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 456 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 457
458 if (be_mcc_compl_is_new(compl)) {
459 queue_tail_inc(mcc_cq);
460 return compl;
461 }
462 return NULL;
463}
464
7a1e9b20
SP		 465void be_async_mcc_enable(struct be_adapter *adapter)
466{
467 spin_lock_bh(&adapter->mcc_cq_lock);
468
469 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
470 adapter->mcc_obj.rearm_cq = true;
471
472 spin_unlock_bh(&adapter->mcc_cq_lock);
473}
474
475void be_async_mcc_disable(struct be_adapter *adapter)
476{
a323d9bf
SP		 477 spin_lock_bh(&adapter->mcc_cq_lock);
478
7a1e9b20 479 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 480 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
481
482 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 483}
484
10ef9ab4 485int be_process_mcc(struct be_adapter *adapter)
5fb379ee 486{
efd2e40a 487 struct be_mcc_compl *compl;
10ef9ab4 488 int num = 0, status = 0;
7a1e9b20 489 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 490
072a9c48 491 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 492
8788fdc2 493 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 494 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 495 be_mcc_event_process(adapter, compl);
b31c50a7 496 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 497 status = be_mcc_compl_process(adapter, compl);
498 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 499 }
500 be_mcc_compl_use(compl);
501 num++;
502 }
b31c50a7 503
10ef9ab4
SP		 504 if (num)
505 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
506
072a9c48 507 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 508 return status;
5fb379ee
SP		 509}
510
6ac7b687 511/* Wait till no more pending mcc requests are present */
b31c50a7 512static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 513{
b31c50a7 514#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 515 int i, status = 0;
f31e50a8
SP		 516 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
517
6ac7b687 518 for (i = 0; i < mcc_timeout; i++) {
954f6825 519 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 520 return -EIO;
521
072a9c48 522 local_bh_disable();
10ef9ab4 523 status = be_process_mcc(adapter);
072a9c48 524 local_bh_enable();
b31c50a7 525
f31e50a8 526 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 527 break;
528 udelay(100);
529 }
b31c50a7 530 if (i == mcc_timeout) {
6589ade0 531 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 532 be_set_error(adapter, BE_ERROR_FW);
652bf646 533 return -EIO;
b31c50a7 534 }
f31e50a8 535 return status;
6ac7b687
SP		 536}
537
538/* Notify MCC requests and wait for completion */
b31c50a7 539static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 540{
652bf646
PR		 541 int status;
542 struct be_mcc_wrb *wrb;
543 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
544 u16 index = mcc_obj->q.head;
545 struct be_cmd_resp_hdr *resp;
546
547 index_dec(&index, mcc_obj->q.len);
548 wrb = queue_index_node(&mcc_obj->q, index);
549
550 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
551
efaa408e
SR		 552 status = be_mcc_notify(adapter);
553 if (status)
554 goto out;
652bf646
PR		 555
556 status = be_mcc_wait_compl(adapter);
557 if (status == -EIO)
558 goto out;
559
4c60005f
KA		 560 status = (resp->base_status |
561 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
562 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 563out:
564 return status;
6ac7b687
SP		 565}
566
5f0b849e 567static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 568{
f25b03a7 569 int msecs = 0;
6b7c5b94
SP		 570 u32 ready;
571
572 do {
954f6825 573 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 574 return -EIO;
575
cf588477 576 ready = ioread32(db);
434b3648 577 if (ready == 0xffffffff)
cf588477 578 return -1;
cf588477
SP		 579
580 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 581 if (ready)
582 break;
583
f25b03a7 584 if (msecs > 4000) {
6589ade0 585 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 586 be_set_error(adapter, BE_ERROR_FW);
f67ef7ba 587 be_detect_error(adapter);
6b7c5b94
SP		 588 return -1;
589 }
590
1dbf53a2 591 msleep(1);
f25b03a7 592 msecs++;
6b7c5b94
SP		 593 } while (true);
594
595 return 0;
596}
597
598/*
599 * Insert the mailbox address into the doorbell in two steps
5fb379ee 600 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 601 */
b31c50a7 602static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 603{
604 int status;
6b7c5b94 605 u32 val = 0;
8788fdc2
SP		 606 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
607 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 608 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 609 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 610
cf588477
SP		 611 /* wait for ready to be set */
612 status = be_mbox_db_ready_wait(adapter, db);
613 if (status != 0)
614 return status;
615
6b7c5b94
SP		 616 val |= MPU_MAILBOX_DB_HI_MASK;
617 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
618 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
619 iowrite32(val, db);
620
621 /* wait for ready to be set */
5f0b849e 622 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 623 if (status != 0)
624 return status;
625
626 val = 0;
6b7c5b94
SP		 627 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
628 val |= (u32)(mbox_mem->dma >> 4) << 2;
629 iowrite32(val, db);
630
5f0b849e 631 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 632 if (status != 0)
633 return status;
634
5fb379ee 635 /* A cq entry has been made now */
efd2e40a
SP		 636 if (be_mcc_compl_is_new(compl)) {
637 status = be_mcc_compl_process(adapter, &mbox->compl);
638 be_mcc_compl_use(compl);
5fb379ee
SP		 639 if (status)
640 return status;
641 } else {
5f0b849e 642 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 643 return -1;
644 }
5fb379ee 645 return 0;
6b7c5b94
SP		 646}
647
c5b3ad4c 648static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 649{
fe6d2a38
SP		 650 u32 sem;
651
c5b3ad4c
SP		 652 if (BEx_chip(adapter))
653 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 654 else
c5b3ad4c
SP		 655 pci_read_config_dword(adapter->pdev,
656 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
657
658 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 659}
660
87f20c26 661static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 662{
663#define SLIPORT_READY_TIMEOUT 30
664 u32 sliport_status;
e673244a 665 int i;
bf99e50d
PR		 666
667 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
668 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
669 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
9fa465c0 670 return 0;
67297ad8 671
9fa465c0
SP		 672 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
673 !(sliport_status & SLIPORT_STATUS_RN_MASK))
674 return -EIO;
67297ad8 675
9fa465c0 676 msleep(1000);
bf99e50d 677 }
67297ad8 678
9fa465c0 679 return sliport_status ? : -1;
bf99e50d
PR		 680}
681
682int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 683{
43a04fdc
SP		 684 u16 stage;
685 int status, timeout = 0;
6ed35eea 686 struct device *dev = &adapter->pdev->dev;
6b7c5b94 687
bf99e50d
PR		 688 if (lancer_chip(adapter)) {
689 status = lancer_wait_ready(adapter);
e673244a
KA		 690 if (status) {
691 stage = status;
692 goto err;
693 }
694 return 0;
bf99e50d
PR		 695 }
696
43a04fdc 697 do {
ca3de6b2
SP		 698 /* There's no means to poll POST state on BE2/3 VFs */
699 if (BEx_chip(adapter) && be_virtfn(adapter))
700 return 0;
701
c5b3ad4c 702 stage = be_POST_stage_get(adapter);
66d29cbc 703 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 704 return 0;
66d29cbc 705
a2cc4e0b 706 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 707 if (msleep_interruptible(2000)) {
708 dev_err(dev, "Waiting for POST aborted\n");
709 return -EINTR;
43a04fdc 710 }
66d29cbc 711 timeout += 2;
3ab81b5f 712 } while (timeout < 60);
6b7c5b94 713
e673244a
KA		 714err:
715 dev_err(dev, "POST timeout; stage=%#x\n", stage);
9fa465c0 716 return -ETIMEDOUT;
6b7c5b94
SP		 717}
718
6b7c5b94
SP		 719static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
720{
721 return &wrb->payload.sgl[0];
722}
723
a2cc4e0b 724static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 725{
726 wrb->tag0 = addr & 0xFFFFFFFF;
727 wrb->tag1 = upper_32_bits(addr);
728}
6b7c5b94
SP		 729
730/* Don't touch the hdr after it's prepared */
106df1e3
SK		 731/* mem will be NULL for embedded commands */
732static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 733 u8 subsystem, u8 opcode, int cmd_len,
734 struct be_mcc_wrb *wrb,
735 struct be_dma_mem *mem)
6b7c5b94 736{
106df1e3
SK		 737 struct be_sge *sge;
738
6b7c5b94
SP		 739 req_hdr->opcode = opcode;
740 req_hdr->subsystem = subsystem;
741 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 742 req_hdr->version = 0;
bea50988 743 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 744 wrb->payload_length = cmd_len;
745 if (mem) {
746 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
747 MCC_WRB_SGE_CNT_SHIFT;
748 sge = nonembedded_sgl(wrb);
749 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
750 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
751 sge->len = cpu_to_le32(mem->size);
752 } else
753 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
754 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 755}
756
757static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 758 struct be_dma_mem *mem)
6b7c5b94
SP		 759{
760 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
761 u64 dma = (u64)mem->dma;
762
763 for (i = 0; i < buf_pages; i++) {
764 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
765 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
766 dma += PAGE_SIZE_4K;
767 }
768}
769
b31c50a7 770static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 771{
b31c50a7
SP		 772 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
773 struct be_mcc_wrb *wrb
774 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
775 memset(wrb, 0, sizeof(*wrb));
776 return wrb;
6b7c5b94
SP		 777}
778
b31c50a7 779static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 780{
b31c50a7
SP		 781 struct be_queue_info *mccq = &adapter->mcc_obj.q;
782 struct be_mcc_wrb *wrb;
783
aa790db9
PR		 784 if (!mccq->created)
785 return NULL;
786
4d277125 787 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 788 return NULL;
713d0394 789
b31c50a7
SP		 790 wrb = queue_head_node(mccq);
791 queue_head_inc(mccq);
792 atomic_inc(&mccq->used);
793 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 794 return wrb;
795}
796
bea50988
SP		 797static bool use_mcc(struct be_adapter *adapter)
798{
799 return adapter->mcc_obj.q.created;
800}
801
802/* Must be used only in process context */
803static int be_cmd_lock(struct be_adapter *adapter)
804{
805 if (use_mcc(adapter)) {
806 spin_lock_bh(&adapter->mcc_lock);
807 return 0;
808 } else {
809 return mutex_lock_interruptible(&adapter->mbox_lock);
810 }
811}
812
813/* Must be used only in process context */
814static void be_cmd_unlock(struct be_adapter *adapter)
815{
816 if (use_mcc(adapter))
817 spin_unlock_bh(&adapter->mcc_lock);
818 else
819 return mutex_unlock(&adapter->mbox_lock);
820}
821
822static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
823 struct be_mcc_wrb *wrb)
824{
825 struct be_mcc_wrb *dest_wrb;
826
827 if (use_mcc(adapter)) {
828 dest_wrb = wrb_from_mccq(adapter);
829 if (!dest_wrb)
830 return NULL;
831 } else {
832 dest_wrb = wrb_from_mbox(adapter);
833 }
834
835 memcpy(dest_wrb, wrb, sizeof(*wrb));
836 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
837 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
838
839 return dest_wrb;
840}
841
842/* Must be used only in process context */
843static int be_cmd_notify_wait(struct be_adapter *adapter,
844 struct be_mcc_wrb *wrb)
845{
846 struct be_mcc_wrb *dest_wrb;
847 int status;
848
849 status = be_cmd_lock(adapter);
850 if (status)
851 return status;
852
853 dest_wrb = be_cmd_copy(adapter, wrb);
854 if (!dest_wrb)
855 return -EBUSY;
856
857 if (use_mcc(adapter))
858 status = be_mcc_notify_wait(adapter);
859 else
860 status = be_mbox_notify_wait(adapter);
861
862 if (!status)
863 memcpy(wrb, dest_wrb, sizeof(*wrb));
864
865 be_cmd_unlock(adapter);
866 return status;
867}
868
2243e2e9
SP		 869/* Tell fw we're about to start firing cmds by writing a
870 * special pattern across the wrb hdr; uses mbox
871 */
872int be_cmd_fw_init(struct be_adapter *adapter)
873{
874 u8 *wrb;
875 int status;
876
bf99e50d
PR		 877 if (lancer_chip(adapter))
878 return 0;
879
2984961c
IV		 880 if (mutex_lock_interruptible(&adapter->mbox_lock))
881 return -1;
2243e2e9
SP		 882
883 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 884 *wrb++ = 0xFF;
885 *wrb++ = 0x12;
886 *wrb++ = 0x34;
887 *wrb++ = 0xFF;
888 *wrb++ = 0xFF;
889 *wrb++ = 0x56;
890 *wrb++ = 0x78;
891 *wrb = 0xFF;
2243e2e9
SP		 892
893 status = be_mbox_notify_wait(adapter);
894
2984961c 895 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 896 return status;
897}
898
899/* Tell fw we're done with firing cmds by writing a
900 * special pattern across the wrb hdr; uses mbox
901 */
902int be_cmd_fw_clean(struct be_adapter *adapter)
903{
904 u8 *wrb;
905 int status;
906
bf99e50d
PR		 907 if (lancer_chip(adapter))
908 return 0;
909
2984961c
IV		 910 if (mutex_lock_interruptible(&adapter->mbox_lock))
911 return -1;
2243e2e9
SP		 912
913 wrb = (u8 *)wrb_from_mbox(adapter);
914 *wrb++ = 0xFF;
915 *wrb++ = 0xAA;
916 *wrb++ = 0xBB;
917 *wrb++ = 0xFF;
918 *wrb++ = 0xFF;
919 *wrb++ = 0xCC;
920 *wrb++ = 0xDD;
921 *wrb = 0xFF;
922
923 status = be_mbox_notify_wait(adapter);
924
2984961c 925 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 926 return status;
927}
bf99e50d 928
f2f781a7 929int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 930{
b31c50a7
SP		 931 struct be_mcc_wrb *wrb;
932 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 933 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
934 int status, ver = 0;
6b7c5b94 935
2984961c
IV		 936 if (mutex_lock_interruptible(&adapter->mbox_lock))
937 return -1;
b31c50a7
SP		 938
939 wrb = wrb_from_mbox(adapter);
940 req = embedded_payload(wrb);
6b7c5b94 941
106df1e3 942 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 943 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
944 NULL);
6b7c5b94 945
f2f781a7
SP		 946 /* Support for EQ_CREATEv2 available only SH-R onwards */
947 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
948 ver = 2;
949
950 req->hdr.version = ver;
6b7c5b94
SP		 951 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
952
6b7c5b94
SP		 953 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
954 /* 4byte eqe*/
955 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
956 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 957 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 958 be_dws_cpu_to_le(req->context, sizeof(req->context));
959
960 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
961
b31c50a7 962 status = be_mbox_notify_wait(adapter);
6b7c5b94 963 if (!status) {
b31c50a7 964 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 965
f2f781a7
SP		 966 eqo->q.id = le16_to_cpu(resp->eq_id);
967 eqo->msix_idx =
968 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
969 eqo->q.created = true;
6b7c5b94 970 }
b31c50a7 971
2984961c 972 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 973 return status;
974}
975
f9449ab7 976/* Use MCC */
8788fdc2 977int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 978 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 979{
b31c50a7
SP		 980 struct be_mcc_wrb *wrb;
981 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 982 int status;
983
f9449ab7 984 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 985
f9449ab7
SP		 986 wrb = wrb_from_mccq(adapter);
987 if (!wrb) {
988 status = -EBUSY;
989 goto err;
990 }
b31c50a7 991 req = embedded_payload(wrb);
6b7c5b94 992
106df1e3 993 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 994 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
995 NULL);
5ee4979b 996 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 997 if (permanent) {
998 req->permanent = 1;
999 } else {
504fbf1e 1000 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 1001 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 1002 req->permanent = 0;
1003 }
1004
f9449ab7 1005 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 1006 if (!status) {
1007 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 1008
6b7c5b94 1009 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 1010 }
6b7c5b94 1011
f9449ab7
SP		 1012err:
1013 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1014 return status;
1015}
1016
b31c50a7 1017/* Uses synchronous MCCQ */
8788fdc2 1018int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 1019 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 1020{
b31c50a7
SP		 1021 struct be_mcc_wrb *wrb;
1022 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 1023 int status;
1024
b31c50a7
SP		 1025 spin_lock_bh(&adapter->mcc_lock);
1026
1027 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1028 if (!wrb) {
1029 status = -EBUSY;
1030 goto err;
1031 }
b31c50a7 1032 req = embedded_payload(wrb);
6b7c5b94 1033
106df1e3 1034 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1035 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1036 NULL);
6b7c5b94 1037
f8617e08 1038 req->hdr.domain = domain;
6b7c5b94
SP		 1039 req->if_id = cpu_to_le32(if_id);
1040 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1041
b31c50a7 1042 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1043 if (!status) {
1044 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1045
6b7c5b94
SP		 1046 *pmac_id = le32_to_cpu(resp->pmac_id);
1047 }
1048
713d0394 1049err:
b31c50a7 1050 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 1051
1052 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1053 status = -EPERM;
1054
6b7c5b94
SP		 1055 return status;
1056}
1057
b31c50a7 1058/* Uses synchronous MCCQ */
30128031 1059int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1060{
b31c50a7
SP		 1061 struct be_mcc_wrb *wrb;
1062 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1063 int status;
1064
30128031
SP		 1065 if (pmac_id == -1)
1066 return 0;
1067
b31c50a7
SP		 1068 spin_lock_bh(&adapter->mcc_lock);
1069
1070 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1071 if (!wrb) {
1072 status = -EBUSY;
1073 goto err;
1074 }
b31c50a7 1075 req = embedded_payload(wrb);
6b7c5b94 1076
106df1e3 1077 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
cd3307aa
KA		 1078 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1079 wrb, NULL);
6b7c5b94 1080
f8617e08 1081 req->hdr.domain = dom;
6b7c5b94
SP		 1082 req->if_id = cpu_to_le32(if_id);
1083 req->pmac_id = cpu_to_le32(pmac_id);
1084
b31c50a7
SP		 1085 status = be_mcc_notify_wait(adapter);
1086
713d0394 1087err:
b31c50a7 1088 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1089 return status;
1090}
1091
b31c50a7 1092/* Uses Mbox */
10ef9ab4 1093int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1094 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1095{
b31c50a7
SP		 1096 struct be_mcc_wrb *wrb;
1097 struct be_cmd_req_cq_create *req;
6b7c5b94 1098 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1099 void *ctxt;
6b7c5b94
SP		 1100 int status;
1101
2984961c
IV		 1102 if (mutex_lock_interruptible(&adapter->mbox_lock))
1103 return -1;
b31c50a7
SP		 1104
1105 wrb = wrb_from_mbox(adapter);
1106 req = embedded_payload(wrb);
1107 ctxt = &req->context;
6b7c5b94 1108
106df1e3 1109 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1110 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1111 NULL);
6b7c5b94
SP		 1112
1113 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1114
1115 if (BEx_chip(adapter)) {
fe6d2a38 1116 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1117 coalesce_wm);
fe6d2a38 1118 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1119 ctxt, no_delay);
fe6d2a38 1120 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1121 __ilog2_u32(cq->len / 256));
fe6d2a38 1122 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1123 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1124 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1125 } else {
1126 req->hdr.version = 2;
1127 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1128
1129 /* coalesce-wm field in this cmd is not relevant to Lancer.
1130 * Lancer uses COMMON_MODIFY_CQ to set this field
1131 */
1132 if (!lancer_chip(adapter))
1133 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1134 ctxt, coalesce_wm);
bbdc42f8 1135 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1136 no_delay);
bbdc42f8 1137 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1138 __ilog2_u32(cq->len / 256));
bbdc42f8 1139 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1140 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1141 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1142 }
6b7c5b94 1143
6b7c5b94
SP		 1144 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1145
1146 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1147
b31c50a7 1148 status = be_mbox_notify_wait(adapter);
6b7c5b94 1149 if (!status) {
b31c50a7 1150 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1151
6b7c5b94
SP		 1152 cq->id = le16_to_cpu(resp->cq_id);
1153 cq->created = true;
1154 }
b31c50a7 1155
2984961c 1156 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1157
1158 return status;
1159}
1160
1161static u32 be_encoded_q_len(int q_len)
1162{
1163 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1164
5fb379ee
SP		 1165 if (len_encoded == 16)
1166 len_encoded = 0;
1167 return len_encoded;
1168}
1169
4188e7df 1170static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1171 struct be_queue_info *mccq,
1172 struct be_queue_info *cq)
5fb379ee 1173{
b31c50a7 1174 struct be_mcc_wrb *wrb;
34b1ef04 1175 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1176 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1177 void *ctxt;
5fb379ee
SP		 1178 int status;
1179
2984961c
IV		 1180 if (mutex_lock_interruptible(&adapter->mbox_lock))
1181 return -1;
b31c50a7
SP		 1182
1183 wrb = wrb_from_mbox(adapter);
1184 req = embedded_payload(wrb);
1185 ctxt = &req->context;
5fb379ee 1186
106df1e3 1187 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1188 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1189 NULL);
5fb379ee 1190
d4a2ac3e 1191 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1192 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1193 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1194 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1195 be_encoded_q_len(mccq->len));
fe6d2a38 1196 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1197 } else {
1198 req->hdr.version = 1;
1199 req->cq_id = cpu_to_le16(cq->id);
1200
1201 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1202 be_encoded_q_len(mccq->len));
1203 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1204 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1205 ctxt, cq->id);
1206 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1207 ctxt, 1);
fe6d2a38 1208 }
5fb379ee 1209
21252377
VV		 1210 /* Subscribe to Link State, Sliport Event and Group 5 Events
1211 * (bits 1, 5 and 17 set)
1212 */
1213 req->async_event_bitmap[0] =
1214 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1215 BIT(ASYNC_EVENT_CODE_GRP_5) |
1216 BIT(ASYNC_EVENT_CODE_QNQ) |
1217 BIT(ASYNC_EVENT_CODE_SLIPORT));
1218
5fb379ee
SP		 1219 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1220
1221 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1222
b31c50a7 1223 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1224 if (!status) {
1225 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1226
5fb379ee
SP		 1227 mccq->id = le16_to_cpu(resp->id);
1228 mccq->created = true;
1229 }
2984961c 1230 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1231
1232 return status;
1233}
1234
4188e7df 1235static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1236 struct be_queue_info *mccq,
1237 struct be_queue_info *cq)
34b1ef04
SK		 1238{
1239 struct be_mcc_wrb *wrb;
1240 struct be_cmd_req_mcc_create *req;
1241 struct be_dma_mem *q_mem = &mccq->dma_mem;
1242 void *ctxt;
1243 int status;
1244
1245 if (mutex_lock_interruptible(&adapter->mbox_lock))
1246 return -1;
1247
1248 wrb = wrb_from_mbox(adapter);
1249 req = embedded_payload(wrb);
1250 ctxt = &req->context;
1251
106df1e3 1252 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1253 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1254 NULL);
34b1ef04
SK		 1255
1256 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1257
1258 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1259 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1260 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1261 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1262
1263 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1264
1265 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1266
1267 status = be_mbox_notify_wait(adapter);
1268 if (!status) {
1269 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1270
34b1ef04
SK		 1271 mccq->id = le16_to_cpu(resp->id);
1272 mccq->created = true;
1273 }
1274
1275 mutex_unlock(&adapter->mbox_lock);
1276 return status;
1277}
1278
1279int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1280 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1281{
1282 int status;
1283
1284 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1285 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1286 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1287 "or newer to avoid conflicting priorities between NIC "
1288 "and FCoE traffic");
1289 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1290 }
1291 return status;
1292}
1293
94d73aaa 1294int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1295{
7707133c 1296 struct be_mcc_wrb wrb = {0};
b31c50a7 1297 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1298 struct be_queue_info *txq = &txo->q;
1299 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1300 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1301 int status, ver = 0;
6b7c5b94 1302
7707133c 1303 req = embedded_payload(&wrb);
106df1e3 1304 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1305 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1306
8b7756ca
PR		 1307 if (lancer_chip(adapter)) {
1308 req->hdr.version = 1;
94d73aaa
VV		 1309 } else if (BEx_chip(adapter)) {
1310 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1311 req->hdr.version = 2;
1312 } else { /* For SH */
1313 req->hdr.version = 2;
8b7756ca
PR		 1314 }
1315
81b02655
VV		 1316 if (req->hdr.version > 0)
1317 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1318 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1319 req->ulp_num = BE_ULP1_NUM;
1320 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1321 req->cq_id = cpu_to_le16(cq->id);
1322 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1323 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1324 ver = req->hdr.version;
1325
7707133c 1326 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1327 if (!status) {
7707133c 1328 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1329
6b7c5b94 1330 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1331 if (ver == 2)
1332 txo->db_offset = le32_to_cpu(resp->db_offset);
1333 else
1334 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1335 txq->created = true;
1336 }
b31c50a7 1337
6b7c5b94
SP		 1338 return status;
1339}
1340
482c9e79 1341/* Uses MCC */
8788fdc2 1342int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1343 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1344 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1345{
b31c50a7
SP		 1346 struct be_mcc_wrb *wrb;
1347 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1348 struct be_dma_mem *q_mem = &rxq->dma_mem;
1349 int status;
1350
482c9e79 1351 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1352
482c9e79
SP		 1353 wrb = wrb_from_mccq(adapter);
1354 if (!wrb) {
1355 status = -EBUSY;
1356 goto err;
1357 }
b31c50a7 1358 req = embedded_payload(wrb);
6b7c5b94 1359
106df1e3 1360 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1361 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1362
1363 req->cq_id = cpu_to_le16(cq_id);
1364 req->frag_size = fls(frag_size) - 1;
1365 req->num_pages = 2;
1366 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1367 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1368 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1369 req->rss_queue = cpu_to_le32(rss);
1370
482c9e79 1371 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1372 if (!status) {
1373 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1374
6b7c5b94
SP		 1375 rxq->id = le16_to_cpu(resp->id);
1376 rxq->created = true;
3abcdeda 1377 *rss_id = resp->rss_id;
6b7c5b94 1378 }
b31c50a7 1379
482c9e79
SP		 1380err:
1381 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1382 return status;
1383}
1384
b31c50a7
SP		 1385/* Generic destroyer function for all types of queues
1386 * Uses Mbox
1387 */
8788fdc2 1388int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1389 int queue_type)
6b7c5b94 1390{
b31c50a7
SP		 1391 struct be_mcc_wrb *wrb;
1392 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1393 u8 subsys = 0, opcode = 0;
1394 int status;
1395
2984961c
IV		 1396 if (mutex_lock_interruptible(&adapter->mbox_lock))
1397 return -1;
6b7c5b94 1398
b31c50a7
SP		 1399 wrb = wrb_from_mbox(adapter);
1400 req = embedded_payload(wrb);
1401
6b7c5b94
SP		 1402 switch (queue_type) {
1403 case QTYPE_EQ:
1404 subsys = CMD_SUBSYSTEM_COMMON;
1405 opcode = OPCODE_COMMON_EQ_DESTROY;
1406 break;
1407 case QTYPE_CQ:
1408 subsys = CMD_SUBSYSTEM_COMMON;
1409 opcode = OPCODE_COMMON_CQ_DESTROY;
1410 break;
1411 case QTYPE_TXQ:
1412 subsys = CMD_SUBSYSTEM_ETH;
1413 opcode = OPCODE_ETH_TX_DESTROY;
1414 break;
1415 case QTYPE_RXQ:
1416 subsys = CMD_SUBSYSTEM_ETH;
1417 opcode = OPCODE_ETH_RX_DESTROY;
1418 break;
5fb379ee
SP		 1419 case QTYPE_MCCQ:
1420 subsys = CMD_SUBSYSTEM_COMMON;
1421 opcode = OPCODE_COMMON_MCC_DESTROY;
1422 break;
6b7c5b94 1423 default:
5f0b849e 1424 BUG();
6b7c5b94 1425 }
d744b44e 1426
106df1e3 1427 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1428 NULL);
6b7c5b94
SP		 1429 req->id = cpu_to_le16(q->id);
1430
b31c50a7 1431 status = be_mbox_notify_wait(adapter);
aa790db9 1432 q->created = false;
5f0b849e 1433
2984961c 1434 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1435 return status;
1436}
6b7c5b94 1437
482c9e79
SP		 1438/* Uses MCC */
1439int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1440{
1441 struct be_mcc_wrb *wrb;
1442 struct be_cmd_req_q_destroy *req;
1443 int status;
1444
1445 spin_lock_bh(&adapter->mcc_lock);
1446
1447 wrb = wrb_from_mccq(adapter);
1448 if (!wrb) {
1449 status = -EBUSY;
1450 goto err;
1451 }
1452 req = embedded_payload(wrb);
1453
106df1e3 1454 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1455 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1456 req->id = cpu_to_le16(q->id);
1457
1458 status = be_mcc_notify_wait(adapter);
aa790db9 1459 q->created = false;
482c9e79
SP		 1460
1461err:
1462 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1463 return status;
1464}
1465
b31c50a7 1466/* Create an rx filtering policy configuration on an i/f
bea50988 1467 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1468 */
73d540f2 1469int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1470 u32 *if_handle, u32 domain)
6b7c5b94 1471{
bea50988 1472 struct be_mcc_wrb wrb = {0};
b31c50a7 1473 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1474 int status;
1475
bea50988 1476 req = embedded_payload(&wrb);
106df1e3 1477 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1478 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1479 sizeof(*req), &wrb, NULL);
ba343c77 1480 req->hdr.domain = domain;
73d540f2
SP		 1481 req->capability_flags = cpu_to_le32(cap_flags);
1482 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1483 req->pmac_invalid = true;
6b7c5b94 1484
bea50988 1485 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1486 if (!status) {
bea50988 1487 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1488
6b7c5b94 1489 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1490
1491 /* Hack to retrieve VF's pmac-id on BE3 */
18c57c74 1492 if (BE3_chip(adapter) && be_virtfn(adapter))
b5bb9776 1493 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1494 }
6b7c5b94
SP		 1495 return status;
1496}
1497
f9449ab7 1498/* Uses MCCQ */
30128031 1499int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1500{
b31c50a7
SP		 1501 struct be_mcc_wrb *wrb;
1502 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1503 int status;
1504
30128031 1505 if (interface_id == -1)
f9449ab7 1506 return 0;
b31c50a7 1507
f9449ab7
SP		 1508 spin_lock_bh(&adapter->mcc_lock);
1509
1510 wrb = wrb_from_mccq(adapter);
1511 if (!wrb) {
1512 status = -EBUSY;
1513 goto err;
1514 }
b31c50a7 1515 req = embedded_payload(wrb);
6b7c5b94 1516
106df1e3 1517 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1518 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1519 sizeof(*req), wrb, NULL);
658681f7 1520 req->hdr.domain = domain;
6b7c5b94 1521 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1522
f9449ab7
SP		 1523 status = be_mcc_notify_wait(adapter);
1524err:
1525 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1526 return status;
1527}
1528
1529/* Get stats is a non embedded command: the request is not embedded inside
1530 * WRB but is a separate dma memory block
b31c50a7 1531 * Uses asynchronous MCC
6b7c5b94 1532 */
8788fdc2 1533int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1534{
b31c50a7 1535 struct be_mcc_wrb *wrb;
89a88ab8 1536 struct be_cmd_req_hdr *hdr;
713d0394 1537 int status = 0;
6b7c5b94 1538
b31c50a7 1539 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1540
b31c50a7 1541 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1542 if (!wrb) {
1543 status = -EBUSY;
1544 goto err;
1545 }
89a88ab8 1546 hdr = nonemb_cmd->va;
6b7c5b94 1547
106df1e3 1548 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1549 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1550 nonemb_cmd);
89a88ab8 1551
ca34fe38 1552 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1553 if (BE2_chip(adapter))
1554 hdr->version = 0;
1555 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1556 hdr->version = 1;
61000861
AK		 1557 else
1558 hdr->version = 2;
89a88ab8 1559
efaa408e
SR		 1560 status = be_mcc_notify(adapter);
1561 if (status)
1562 goto err;
1563
b2aebe6d 1564 adapter->stats_cmd_sent = true;
6b7c5b94 1565
713d0394 1566err:
b31c50a7 1567 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1568 return status;
6b7c5b94
SP		 1569}
1570
005d5696
SX		 1571/* Lancer Stats */
1572int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1573 struct be_dma_mem *nonemb_cmd)
005d5696 1574{
005d5696
SX		 1575 struct be_mcc_wrb *wrb;
1576 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1577 int status = 0;
1578
f25b119c
PR		 1579 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1580 CMD_SUBSYSTEM_ETH))
1581 return -EPERM;
1582
005d5696
SX		 1583 spin_lock_bh(&adapter->mcc_lock);
1584
1585 wrb = wrb_from_mccq(adapter);
1586 if (!wrb) {
1587 status = -EBUSY;
1588 goto err;
1589 }
1590 req = nonemb_cmd->va;
005d5696 1591
106df1e3 1592 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1593 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1594 wrb, nonemb_cmd);
005d5696 1595
d51ebd33 1596 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1597 req->cmd_params.params.reset_stats = 0;
1598
efaa408e
SR		 1599 status = be_mcc_notify(adapter);
1600 if (status)
1601 goto err;
1602
005d5696
SX		 1603 adapter->stats_cmd_sent = true;
1604
1605err:
1606 spin_unlock_bh(&adapter->mcc_lock);
1607 return status;
1608}
1609
323ff71e
SP		 1610static int be_mac_to_link_speed(int mac_speed)
1611{
1612 switch (mac_speed) {
1613 case PHY_LINK_SPEED_ZERO:
1614 return 0;
1615 case PHY_LINK_SPEED_10MBPS:
1616 return 10;
1617 case PHY_LINK_SPEED_100MBPS:
1618 return 100;
1619 case PHY_LINK_SPEED_1GBPS:
1620 return 1000;
1621 case PHY_LINK_SPEED_10GBPS:
1622 return 10000;
b971f847
VV		 1623 case PHY_LINK_SPEED_20GBPS:
1624 return 20000;
1625 case PHY_LINK_SPEED_25GBPS:
1626 return 25000;
1627 case PHY_LINK_SPEED_40GBPS:
1628 return 40000;
323ff71e
SP		 1629 }
1630 return 0;
1631}
1632
1633/* Uses synchronous mcc
1634 * Returns link_speed in Mbps
1635 */
1636int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1637 u8 *link_status, u32 dom)
6b7c5b94 1638{
b31c50a7
SP		 1639 struct be_mcc_wrb *wrb;
1640 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1641 int status;
1642
b31c50a7
SP		 1643 spin_lock_bh(&adapter->mcc_lock);
1644
b236916a
AK		 1645 if (link_status)
1646 *link_status = LINK_DOWN;
1647
b31c50a7 1648 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1649 if (!wrb) {
1650 status = -EBUSY;
1651 goto err;
1652 }
b31c50a7 1653 req = embedded_payload(wrb);
a8f447bd 1654
57cd80d4 1655 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1656 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1657 sizeof(*req), wrb, NULL);
57cd80d4 1658
ca34fe38
SP		 1659 /* version 1 of the cmd is not supported only by BE2 */
1660 if (!BE2_chip(adapter))
daad6167
PR		 1661 req->hdr.version = 1;
1662
57cd80d4 1663 req->hdr.domain = dom;
6b7c5b94 1664
b31c50a7 1665 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1666 if (!status) {
1667 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1668
323ff71e
SP		 1669 if (link_speed) {
1670 *link_speed = resp->link_speed ?
1671 le16_to_cpu(resp->link_speed) * 10 :
1672 be_mac_to_link_speed(resp->mac_speed);
1673
1674 if (!resp->logical_link_status)
1675 *link_speed = 0;
0388f251 1676 }
b236916a
AK		 1677 if (link_status)
1678 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1679 }
1680
713d0394 1681err:
b31c50a7 1682 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1683 return status;
1684}
1685
609ff3bb
AK		 1686/* Uses synchronous mcc */
1687int be_cmd_get_die_temperature(struct be_adapter *adapter)
1688{
1689 struct be_mcc_wrb *wrb;
1690 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1691 int status = 0;
609ff3bb
AK		 1692
1693 spin_lock_bh(&adapter->mcc_lock);
1694
1695 wrb = wrb_from_mccq(adapter);
1696 if (!wrb) {
1697 status = -EBUSY;
1698 goto err;
1699 }
1700 req = embedded_payload(wrb);
1701
106df1e3 1702 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1703 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1704 sizeof(*req), wrb, NULL);
609ff3bb 1705
efaa408e 1706 status = be_mcc_notify(adapter);
609ff3bb
AK		 1707err:
1708 spin_unlock_bh(&adapter->mcc_lock);
1709 return status;
1710}
1711
311fddc7
SK		 1712/* Uses synchronous mcc */
1713int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1714{
1715 struct be_mcc_wrb *wrb;
1716 struct be_cmd_req_get_fat *req;
1717 int status;
1718
1719 spin_lock_bh(&adapter->mcc_lock);
1720
1721 wrb = wrb_from_mccq(adapter);
1722 if (!wrb) {
1723 status = -EBUSY;
1724 goto err;
1725 }
1726 req = embedded_payload(wrb);
1727
106df1e3 1728 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1729 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1730 NULL);
311fddc7
SK		 1731 req->fat_operation = cpu_to_le32(QUERY_FAT);
1732 status = be_mcc_notify_wait(adapter);
1733 if (!status) {
1734 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
03d28ffe 1735
311fddc7 1736 if (log_size && resp->log_size)
fe2a70ee
SK		 1737 *log_size = le32_to_cpu(resp->log_size) -
1738 sizeof(u32);
311fddc7
SK		 1739 }
1740err:
1741 spin_unlock_bh(&adapter->mcc_lock);
1742 return status;
1743}
1744
c5f156de 1745int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1746{
1747 struct be_dma_mem get_fat_cmd;
1748 struct be_mcc_wrb *wrb;
1749 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1750 u32 offset = 0, total_size, buf_size,
1751 log_offset = sizeof(u32), payload_len;
c5f156de 1752 int status = 0;
311fddc7
SK		 1753
1754 if (buf_len == 0)
c5f156de 1755 return -EIO;
311fddc7
SK		 1756
1757 total_size = buf_len;
1758
fe2a70ee 1759 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
e51000db
SB		 1760 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1761 get_fat_cmd.size,
1762 &get_fat_cmd.dma, GFP_ATOMIC);
fe2a70ee 1763 if (!get_fat_cmd.va) {
fe2a70ee 1764 dev_err(&adapter->pdev->dev,
cd3307aa 1765 "Memory allocation failure while reading FAT data\n");
c5f156de 1766 return -ENOMEM;
fe2a70ee
SK		 1767 }
1768
311fddc7
SK		 1769 spin_lock_bh(&adapter->mcc_lock);
1770
311fddc7
SK		 1771 while (total_size) {
1772 buf_size = min(total_size, (u32)60*1024);
1773 total_size -= buf_size;
1774
fe2a70ee
SK		 1775 wrb = wrb_from_mccq(adapter);
1776 if (!wrb) {
1777 status = -EBUSY;
311fddc7
SK		 1778 goto err;
1779 }
1780 req = get_fat_cmd.va;
311fddc7 1781
fe2a70ee 1782 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1783 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1784 OPCODE_COMMON_MANAGE_FAT, payload_len,
1785 wrb, &get_fat_cmd);
311fddc7
SK		 1786
1787 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1788 req->read_log_offset = cpu_to_le32(log_offset);
1789 req->read_log_length = cpu_to_le32(buf_size);
1790 req->data_buffer_size = cpu_to_le32(buf_size);
1791
1792 status = be_mcc_notify_wait(adapter);
1793 if (!status) {
1794 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1795
311fddc7 1796 memcpy(buf + offset,
a2cc4e0b
SP		 1797 resp->data_buffer,
1798 le32_to_cpu(resp->read_log_length));
fe2a70ee 1799 } else {
311fddc7 1800 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1801 goto err;
1802 }
311fddc7
SK		 1803 offset += buf_size;
1804 log_offset += buf_size;
1805 }
1806err:
e51000db
SB		 1807 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1808 get_fat_cmd.va, get_fat_cmd.dma);
311fddc7 1809 spin_unlock_bh(&adapter->mcc_lock);
c5f156de 1810 return status;
311fddc7
SK		 1811}
1812
04b71175 1813/* Uses synchronous mcc */
e97e3cda 1814int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1815{
b31c50a7
SP		 1816 struct be_mcc_wrb *wrb;
1817 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1818 int status;
1819
04b71175 1820 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1821
04b71175
SP		 1822 wrb = wrb_from_mccq(adapter);
1823 if (!wrb) {
1824 status = -EBUSY;
1825 goto err;
1826 }
6b7c5b94 1827
04b71175 1828 req = embedded_payload(wrb);
6b7c5b94 1829
106df1e3 1830 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1831 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1832 NULL);
04b71175 1833 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1834 if (!status) {
1835 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1836
242eb470
VV		 1837 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1838 sizeof(adapter->fw_ver));
1839 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1840 sizeof(adapter->fw_on_flash));
6b7c5b94 1841 }
04b71175
SP		 1842err:
1843 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1844 return status;
1845}
1846
b31c50a7
SP		 1847/* set the EQ delay interval of an EQ to specified value
1848 * Uses async mcc
1849 */
b502ae8d
KA		 1850static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1851 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1852{
b31c50a7
SP		 1853 struct be_mcc_wrb *wrb;
1854 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1855 int status = 0, i;
6b7c5b94 1856
b31c50a7
SP		 1857 spin_lock_bh(&adapter->mcc_lock);
1858
1859 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1860 if (!wrb) {
1861 status = -EBUSY;
1862 goto err;
1863 }
b31c50a7 1864 req = embedded_payload(wrb);
6b7c5b94 1865
106df1e3 1866 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1867 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1868 NULL);
6b7c5b94 1869
2632bafd
SP		 1870 req->num_eq = cpu_to_le32(num);
1871 for (i = 0; i < num; i++) {
1872 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1873 req->set_eqd[i].phase = 0;
1874 req->set_eqd[i].delay_multiplier =
1875 cpu_to_le32(set_eqd[i].delay_multiplier);
1876 }
6b7c5b94 1877
efaa408e 1878 status = be_mcc_notify(adapter);
713d0394 1879err:
b31c50a7 1880 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1881 return status;
6b7c5b94
SP		 1882}
1883
93676703
KA		 1884int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1885 int num)
1886{
1887 int num_eqs, i = 0;
1888
c8ba4ad0
SR		 1889 while (num) {
1890 num_eqs = min(num, 8);
1891 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1892 i += num_eqs;
1893 num -= num_eqs;
93676703
KA		 1894 }
1895
1896 return 0;
1897}
1898
b31c50a7 1899/* Uses sycnhronous mcc */
8788fdc2 1900int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 1901 u32 num, u32 domain)
6b7c5b94 1902{
b31c50a7
SP		 1903 struct be_mcc_wrb *wrb;
1904 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1905 int status;
1906
b31c50a7
SP		 1907 spin_lock_bh(&adapter->mcc_lock);
1908
1909 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1910 if (!wrb) {
1911 status = -EBUSY;
1912 goto err;
1913 }
b31c50a7 1914 req = embedded_payload(wrb);
6b7c5b94 1915
106df1e3 1916 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1917 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1918 wrb, NULL);
435452aa 1919 req->hdr.domain = domain;
6b7c5b94
SP		 1920
1921 req->interface_id = if_id;
012bd387 1922 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1923 req->num_vlan = num;
4d567d97
KA		 1924 memcpy(req->normal_vlan, vtag_array,
1925 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1926
b31c50a7 1927 status = be_mcc_notify_wait(adapter);
713d0394 1928err:
b31c50a7 1929 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1930 return status;
1931}
1932
ac34b743 1933static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1934{
6ac7b687 1935 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1936 struct be_dma_mem *mem = &adapter->rx_filter;
1937 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1938 int status;
6b7c5b94 1939
8788fdc2 1940 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1941
b31c50a7 1942 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1943 if (!wrb) {
1944 status = -EBUSY;
1945 goto err;
1946 }
5b8821b7 1947 memset(req, 0, sizeof(*req));
106df1e3 1948 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1949 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1950 wrb, mem);
6b7c5b94 1951
5b8821b7 1952 req->if_id = cpu_to_le32(adapter->if_handle);
ac34b743
SP		 1953 req->if_flags_mask = cpu_to_le32(flags);
1954 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1955
1956 if (flags & BE_IF_FLAGS_MULTICAST) {
22bedad3 1957 struct netdev_hw_addr *ha;
5b8821b7 1958 int i = 0;
24307eef 1959
1610c79f
PR		 1960 /* Reset mcast promisc mode if already set by setting mask
1961 * and not setting flags field
1962 */
abb93951
PR		 1963 req->if_flags_mask |=
1964 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 1965 be_if_cap_flags(adapter));
016f97b1 1966 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1967 netdev_for_each_mc_addr(ha, adapter->netdev)
1968 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1969 }
1970
8af65c2f 1971 status = be_mcc_notify(adapter);
713d0394 1972err:
8788fdc2 1973 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1974 return status;
6b7c5b94
SP		 1975}
1976
ac34b743
SP		 1977int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1978{
1979 struct device *dev = &adapter->pdev->dev;
1980
1981 if ((flags & be_if_cap_flags(adapter)) != flags) {
1982 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1983 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1984 be_if_cap_flags(adapter));
1985 }
1986 flags &= be_if_cap_flags(adapter);
1987
1988 return __be_cmd_rx_filter(adapter, flags, value);
1989}
1990
b31c50a7 1991/* Uses synchrounous mcc */
8788fdc2 1992int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1993{
b31c50a7
SP		 1994 struct be_mcc_wrb *wrb;
1995 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1996 int status;
1997
f25b119c
PR		 1998 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1999 CMD_SUBSYSTEM_COMMON))
2000 return -EPERM;
2001
b31c50a7 2002 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2003
b31c50a7 2004 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2005 if (!wrb) {
2006 status = -EBUSY;
2007 goto err;
2008 }
b31c50a7 2009 req = embedded_payload(wrb);
6b7c5b94 2010
106df1e3 2011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2012 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2013 wrb, NULL);
6b7c5b94 2014
b29812c1 2015 req->hdr.version = 1;
6b7c5b94
SP		 2016 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2017 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2018
b31c50a7 2019 status = be_mcc_notify_wait(adapter);
6b7c5b94 2020
713d0394 2021err:
b31c50a7 2022 spin_unlock_bh(&adapter->mcc_lock);
b29812c1
SR		 2023
2024 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2025 return -EOPNOTSUPP;
2026
6b7c5b94
SP		 2027 return status;
2028}
2029
b31c50a7 2030/* Uses sycn mcc */
8788fdc2 2031int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 2032{
b31c50a7
SP		 2033 struct be_mcc_wrb *wrb;
2034 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 2035 int status;
2036
f25b119c
PR		 2037 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2038 CMD_SUBSYSTEM_COMMON))
2039 return -EPERM;
2040
b31c50a7 2041 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2042
b31c50a7 2043 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2044 if (!wrb) {
2045 status = -EBUSY;
2046 goto err;
2047 }
b31c50a7 2048 req = embedded_payload(wrb);
6b7c5b94 2049
106df1e3 2050 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2051 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2052 wrb, NULL);
6b7c5b94 2053
b31c50a7 2054 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2055 if (!status) {
2056 struct be_cmd_resp_get_flow_control *resp =
2057 embedded_payload(wrb);
03d28ffe 2058
6b7c5b94
SP		 2059 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2060 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2061 }
2062
713d0394 2063err:
b31c50a7 2064 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 2065 return status;
2066}
2067
b31c50a7 2068/* Uses mbox */
e97e3cda 2069int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2070{
b31c50a7
SP		 2071 struct be_mcc_wrb *wrb;
2072 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2073 int status;
2074
2984961c
IV		 2075 if (mutex_lock_interruptible(&adapter->mbox_lock))
2076 return -1;
6b7c5b94 2077
b31c50a7
SP		 2078 wrb = wrb_from_mbox(adapter);
2079 req = embedded_payload(wrb);
6b7c5b94 2080
106df1e3 2081 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2082 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2083 sizeof(*req), wrb, NULL);
6b7c5b94 2084
b31c50a7 2085 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2086 if (!status) {
2087 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2088
e97e3cda
KA		 2089 adapter->port_num = le32_to_cpu(resp->phys_port);
2090 adapter->function_mode = le32_to_cpu(resp->function_mode);
2091 adapter->function_caps = le32_to_cpu(resp->function_caps);
2092 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2093 dev_info(&adapter->pdev->dev,
2094 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2095 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2096 }
2097
2984961c 2098 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2099 return status;
2100}
14074eab 2101
b31c50a7 2102/* Uses mbox */
14074eab 2103int be_cmd_reset_function(struct be_adapter *adapter)
2104{
b31c50a7
SP		 2105 struct be_mcc_wrb *wrb;
2106 struct be_cmd_req_hdr *req;
14074eab 2107 int status;
2108
bf99e50d 2109 if (lancer_chip(adapter)) {
9fa465c0
SP		 2110 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2111 adapter->db + SLIPORT_CONTROL_OFFSET);
bf99e50d 2112 status = lancer_wait_ready(adapter);
9fa465c0 2113 if (status)
bf99e50d
PR		 2114 dev_err(&adapter->pdev->dev,
2115 "Adapter in non recoverable error\n");
bf99e50d
PR		 2116 return status;
2117 }
2118
2984961c
IV		 2119 if (mutex_lock_interruptible(&adapter->mbox_lock))
2120 return -1;
14074eab 2121
b31c50a7
SP		 2122 wrb = wrb_from_mbox(adapter);
2123 req = embedded_payload(wrb);
14074eab 2124
106df1e3 2125 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2126 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2127 NULL);
14074eab 2128
b31c50a7 2129 status = be_mbox_notify_wait(adapter);
14074eab 2130
2984961c 2131 mutex_unlock(&adapter->mbox_lock);
14074eab 2132 return status;
2133}
84517482 2134
594ad54a 2135int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2136 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2137{
2138 struct be_mcc_wrb *wrb;
2139 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2140 int status;
2141
da1388d6
VV		 2142 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2143 return 0;
2144
b51aa367 2145 spin_lock_bh(&adapter->mcc_lock);
3abcdeda 2146
b51aa367
KA		 2147 wrb = wrb_from_mccq(adapter);
2148 if (!wrb) {
2149 status = -EBUSY;
2150 goto err;
2151 }
3abcdeda
SP		 2152 req = embedded_payload(wrb);
2153
106df1e3 2154 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2155 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2156
2157 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2158 req->enable_rss = cpu_to_le16(rss_hash_opts);
2159 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2160
b51aa367 2161 if (!BEx_chip(adapter))
d3bd3a5e 2162 req->hdr.version = 1;
d3bd3a5e 2163
3abcdeda 2164 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2165 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2166 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2167
b51aa367
KA		 2168 status = be_mcc_notify_wait(adapter);
2169err:
2170 spin_unlock_bh(&adapter->mcc_lock);
3abcdeda
SP		 2171 return status;
2172}
2173
fad9ab2c
SB		 2174/* Uses sync mcc */
2175int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2176 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2177{
2178 struct be_mcc_wrb *wrb;
2179 struct be_cmd_req_enable_disable_beacon *req;
2180 int status;
2181
2182 spin_lock_bh(&adapter->mcc_lock);
2183
2184 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2185 if (!wrb) {
2186 status = -EBUSY;
2187 goto err;
2188 }
fad9ab2c
SB		 2189 req = embedded_payload(wrb);
2190
106df1e3 2191 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2192 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2193 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2194
2195 req->port_num = port_num;
2196 req->beacon_state = state;
2197 req->beacon_duration = bcn;
2198 req->status_duration = sts;
2199
2200 status = be_mcc_notify_wait(adapter);
2201
713d0394 2202err:
fad9ab2c
SB		 2203 spin_unlock_bh(&adapter->mcc_lock);
2204 return status;
2205}
2206
2207/* Uses sync mcc */
2208int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2209{
2210 struct be_mcc_wrb *wrb;
2211 struct be_cmd_req_get_beacon_state *req;
2212 int status;
2213
2214 spin_lock_bh(&adapter->mcc_lock);
2215
2216 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2217 if (!wrb) {
2218 status = -EBUSY;
2219 goto err;
2220 }
fad9ab2c
SB		 2221 req = embedded_payload(wrb);
2222
106df1e3 2223 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2224 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2225 wrb, NULL);
fad9ab2c
SB		 2226
2227 req->port_num = port_num;
2228
2229 status = be_mcc_notify_wait(adapter);
2230 if (!status) {
2231 struct be_cmd_resp_get_beacon_state *resp =
2232 embedded_payload(wrb);
03d28ffe 2233
fad9ab2c
SB		 2234 *state = resp->beacon_state;
2235 }
2236
713d0394 2237err:
fad9ab2c
SB		 2238 spin_unlock_bh(&adapter->mcc_lock);
2239 return status;
2240}
2241
e36edd9d
ML		 2242/* Uses sync mcc */
2243int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2244 u8 page_num, u8 *data)
2245{
2246 struct be_dma_mem cmd;
2247 struct be_mcc_wrb *wrb;
2248 struct be_cmd_req_port_type *req;
2249 int status;
2250
2251 if (page_num > TR_PAGE_A2)
2252 return -EINVAL;
2253
2254 cmd.size = sizeof(struct be_cmd_resp_port_type);
e51000db
SB		 2255 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2256 GFP_ATOMIC);
e36edd9d
ML		 2257 if (!cmd.va) {
2258 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2259 return -ENOMEM;
2260 }
e36edd9d
ML		 2261
2262 spin_lock_bh(&adapter->mcc_lock);
2263
2264 wrb = wrb_from_mccq(adapter);
2265 if (!wrb) {
2266 status = -EBUSY;
2267 goto err;
2268 }
2269 req = cmd.va;
2270
2271 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2272 OPCODE_COMMON_READ_TRANSRECV_DATA,
2273 cmd.size, wrb, &cmd);
2274
2275 req->port = cpu_to_le32(adapter->hba_port_num);
2276 req->page_num = cpu_to_le32(page_num);
2277 status = be_mcc_notify_wait(adapter);
2278 if (!status) {
2279 struct be_cmd_resp_port_type *resp = cmd.va;
2280
2281 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2282 }
2283err:
2284 spin_unlock_bh(&adapter->mcc_lock);
e51000db 2285 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
e36edd9d
ML		 2286 return status;
2287}
2288
485bf569 2289int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 2290 u32 data_size, u32 data_offset,
2291 const char *obj_name, u32 *data_written,
2292 u8 *change_status, u8 *addn_status)
485bf569
SN		 2293{
2294 struct be_mcc_wrb *wrb;
2295 struct lancer_cmd_req_write_object *req;
2296 struct lancer_cmd_resp_write_object *resp;
2297 void *ctxt = NULL;
2298 int status;
2299
2300 spin_lock_bh(&adapter->mcc_lock);
2301 adapter->flash_status = 0;
2302
2303 wrb = wrb_from_mccq(adapter);
2304 if (!wrb) {
2305 status = -EBUSY;
2306 goto err_unlock;
2307 }
2308
2309 req = embedded_payload(wrb);
2310
106df1e3 2311 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2312 OPCODE_COMMON_WRITE_OBJECT,
2313 sizeof(struct lancer_cmd_req_write_object), wrb,
2314 NULL);
485bf569
SN		 2315
2316 ctxt = &req->context;
2317 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2318 write_length, ctxt, data_size);
485bf569
SN		 2319
2320 if (data_size == 0)
2321 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2322 eof, ctxt, 1);
485bf569
SN		 2323 else
2324 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2325 eof, ctxt, 0);
485bf569
SN		 2326
2327 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2328 req->write_offset = cpu_to_le32(data_offset);
242eb470 2329 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2330 req->descriptor_count = cpu_to_le32(1);
2331 req->buf_len = cpu_to_le32(data_size);
2332 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2333 sizeof(struct lancer_cmd_req_write_object))
2334 & 0xFFFFFFFF);
485bf569
SN		 2335 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2336 sizeof(struct lancer_cmd_req_write_object)));
2337
efaa408e
SR		 2338 status = be_mcc_notify(adapter);
2339 if (status)
2340 goto err_unlock;
2341
485bf569
SN		 2342 spin_unlock_bh(&adapter->mcc_lock);
2343
5eeff635 2344 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2345 msecs_to_jiffies(60000)))
fd45160c 2346 status = -ETIMEDOUT;
485bf569
SN		 2347 else
2348 status = adapter->flash_status;
2349
2350 resp = embedded_payload(wrb);
f67ef7ba 2351 if (!status) {
485bf569 2352 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2353 *change_status = resp->change_status;
2354 } else {
485bf569 2355 *addn_status = resp->additional_status;
f67ef7ba 2356 }
485bf569
SN		 2357
2358 return status;
2359
2360err_unlock:
2361 spin_unlock_bh(&adapter->mcc_lock);
2362 return status;
2363}
2364
6809cee0
RN		 2365int be_cmd_query_cable_type(struct be_adapter *adapter)
2366{
2367 u8 page_data[PAGE_DATA_LEN];
2368 int status;
2369
2370 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2371 page_data);
2372 if (!status) {
2373 switch (adapter->phy.interface_type) {
2374 case PHY_TYPE_QSFP:
2375 adapter->phy.cable_type =
2376 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2377 break;
2378 case PHY_TYPE_SFP_PLUS_10GB:
2379 adapter->phy.cable_type =
2380 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2381 break;
2382 default:
2383 adapter->phy.cable_type = 0;
2384 break;
2385 }
2386 }
2387 return status;
2388}
2389
21252377
VV		 2390int be_cmd_query_sfp_info(struct be_adapter *adapter)
2391{
2392 u8 page_data[PAGE_DATA_LEN];
2393 int status;
2394
2395 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2396 page_data);
2397 if (!status) {
2398 strlcpy(adapter->phy.vendor_name, page_data +
2399 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2400 strlcpy(adapter->phy.vendor_pn,
2401 page_data + SFP_VENDOR_PN_OFFSET,
2402 SFP_VENDOR_NAME_LEN - 1);
2403 }
2404
2405 return status;
2406}
2407
f0613380
KA		 2408int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2409{
2410 struct lancer_cmd_req_delete_object *req;
2411 struct be_mcc_wrb *wrb;
2412 int status;
2413
2414 spin_lock_bh(&adapter->mcc_lock);
2415
2416 wrb = wrb_from_mccq(adapter);
2417 if (!wrb) {
2418 status = -EBUSY;
2419 goto err;
2420 }
2421
2422 req = embedded_payload(wrb);
2423
2424 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2425 OPCODE_COMMON_DELETE_OBJECT,
2426 sizeof(*req), wrb, NULL);
2427
242eb470 2428 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2429
2430 status = be_mcc_notify_wait(adapter);
2431err:
2432 spin_unlock_bh(&adapter->mcc_lock);
2433 return status;
2434}
2435
de49bd5a 2436int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2437 u32 data_size, u32 data_offset, const char *obj_name,
2438 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2439{
2440 struct be_mcc_wrb *wrb;
2441 struct lancer_cmd_req_read_object *req;
2442 struct lancer_cmd_resp_read_object *resp;
2443 int status;
2444
2445 spin_lock_bh(&adapter->mcc_lock);
2446
2447 wrb = wrb_from_mccq(adapter);
2448 if (!wrb) {
2449 status = -EBUSY;
2450 goto err_unlock;
2451 }
2452
2453 req = embedded_payload(wrb);
2454
2455 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2456 OPCODE_COMMON_READ_OBJECT,
2457 sizeof(struct lancer_cmd_req_read_object), wrb,
2458 NULL);
de49bd5a
PR		 2459
2460 req->desired_read_len = cpu_to_le32(data_size);
2461 req->read_offset = cpu_to_le32(data_offset);
2462 strcpy(req->object_name, obj_name);
2463 req->descriptor_count = cpu_to_le32(1);
2464 req->buf_len = cpu_to_le32(data_size);
2465 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2466 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2467
2468 status = be_mcc_notify_wait(adapter);
2469
2470 resp = embedded_payload(wrb);
2471 if (!status) {
2472 *data_read = le32_to_cpu(resp->actual_read_len);
2473 *eof = le32_to_cpu(resp->eof);
2474 } else {
2475 *addn_status = resp->additional_status;
2476 }
2477
2478err_unlock:
2479 spin_unlock_bh(&adapter->mcc_lock);
2480 return status;
2481}
2482
84517482 2483int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
70a7b525
VV		 2484 u32 flash_type, u32 flash_opcode, u32 img_offset,
2485 u32 buf_size)
84517482 2486{
b31c50a7 2487 struct be_mcc_wrb *wrb;
3f0d4560 2488 struct be_cmd_write_flashrom *req;
84517482
AK		 2489 int status;
2490
b31c50a7 2491 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2492 adapter->flash_status = 0;
b31c50a7
SP		 2493
2494 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2495 if (!wrb) {
2496 status = -EBUSY;
2892d9c2 2497 goto err_unlock;
713d0394
SP		 2498 }
2499 req = cmd->va;
84517482 2500
106df1e3 2501 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2502 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2503 cmd);
84517482
AK		 2504
2505 req->params.op_type = cpu_to_le32(flash_type);
70a7b525
VV		 2506 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2507 req->params.offset = cpu_to_le32(img_offset);
2508
84517482
AK		 2509 req->params.op_code = cpu_to_le32(flash_opcode);
2510 req->params.data_buf_size = cpu_to_le32(buf_size);
2511
efaa408e
SR		 2512 status = be_mcc_notify(adapter);
2513 if (status)
2514 goto err_unlock;
2515
dd131e76
SB		 2516 spin_unlock_bh(&adapter->mcc_lock);
2517
5eeff635
SR		 2518 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2519 msecs_to_jiffies(40000)))
fd45160c 2520 status = -ETIMEDOUT;
dd131e76
SB		 2521 else
2522 status = adapter->flash_status;
84517482 2523
2892d9c2
DC		 2524 return status;
2525
2526err_unlock:
2527 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2528 return status;
2529}
fa9a6fed 2530
3f0d4560 2531int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
70a7b525 2532 u16 img_optype, u32 img_offset, u32 crc_offset)
fa9a6fed 2533{
be716446 2534 struct be_cmd_read_flash_crc *req;
70a7b525 2535 struct be_mcc_wrb *wrb;
fa9a6fed
SB		 2536 int status;
2537
2538 spin_lock_bh(&adapter->mcc_lock);
2539
2540 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2541 if (!wrb) {
2542 status = -EBUSY;
2543 goto err;
2544 }
fa9a6fed
SB		 2545 req = embedded_payload(wrb);
2546
106df1e3 2547 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2548 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2549 wrb, NULL);
fa9a6fed 2550
70a7b525
VV		 2551 req->params.op_type = cpu_to_le32(img_optype);
2552 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2553 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2554 else
2555 req->params.offset = cpu_to_le32(crc_offset);
2556
fa9a6fed 2557 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710 2558 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2559
2560 status = be_mcc_notify_wait(adapter);
2561 if (!status)
be716446 2562 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2563
713d0394 2564err:
fa9a6fed
SB		 2565 spin_unlock_bh(&adapter->mcc_lock);
2566 return status;
2567}
71d8d1b5 2568
c196b02c 2569int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 2570 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 2571{
2572 struct be_mcc_wrb *wrb;
2573 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2574 int status;
2575
2576 spin_lock_bh(&adapter->mcc_lock);
2577
2578 wrb = wrb_from_mccq(adapter);
2579 if (!wrb) {
2580 status = -EBUSY;
2581 goto err;
2582 }
2583 req = nonemb_cmd->va;
71d8d1b5 2584
106df1e3 2585 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 2586 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2587 wrb, nonemb_cmd);
71d8d1b5
AK		 2588 memcpy(req->magic_mac, mac, ETH_ALEN);
2589
71d8d1b5
AK		 2590 status = be_mcc_notify_wait(adapter);
2591
2592err:
2593 spin_unlock_bh(&adapter->mcc_lock);
2594 return status;
2595}
ff33a6e2 2596
fced9999
SB		 2597int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2598 u8 loopback_type, u8 enable)
2599{
2600 struct be_mcc_wrb *wrb;
2601 struct be_cmd_req_set_lmode *req;
2602 int status;
2603
2604 spin_lock_bh(&adapter->mcc_lock);
2605
2606 wrb = wrb_from_mccq(adapter);
2607 if (!wrb) {
2608 status = -EBUSY;
9c855975 2609 goto err_unlock;
fced9999
SB		 2610 }
2611
2612 req = embedded_payload(wrb);
2613
106df1e3 2614 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2615 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2616 wrb, NULL);
fced9999
SB		 2617
2618 req->src_port = port_num;
2619 req->dest_port = port_num;
2620 req->loopback_type = loopback_type;
2621 req->loopback_state = enable;
2622
9c855975
SR		 2623 status = be_mcc_notify(adapter);
2624 if (status)
2625 goto err_unlock;
2626
2627 spin_unlock_bh(&adapter->mcc_lock);
2628
2629 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2630 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
2631 status = -ETIMEDOUT;
2632
2633 return status;
2634
2635err_unlock:
fced9999
SB		 2636 spin_unlock_bh(&adapter->mcc_lock);
2637 return status;
2638}
2639
ff33a6e2 2640int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 2641 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2642 u64 pattern)
ff33a6e2
S		 2643{
2644 struct be_mcc_wrb *wrb;
2645 struct be_cmd_req_loopback_test *req;
5eeff635 2646 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 2647 int status;
2648
2649 spin_lock_bh(&adapter->mcc_lock);
2650
2651 wrb = wrb_from_mccq(adapter);
2652 if (!wrb) {
2653 status = -EBUSY;
2654 goto err;
2655 }
2656
2657 req = embedded_payload(wrb);
2658
106df1e3 2659 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2660 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2661 NULL);
ff33a6e2 2662
5eeff635 2663 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 2664 req->pattern = cpu_to_le64(pattern);
2665 req->src_port = cpu_to_le32(port_num);
2666 req->dest_port = cpu_to_le32(port_num);
2667 req->pkt_size = cpu_to_le32(pkt_size);
2668 req->num_pkts = cpu_to_le32(num_pkts);
2669 req->loopback_type = cpu_to_le32(loopback_type);
2670
efaa408e
SR		 2671 status = be_mcc_notify(adapter);
2672 if (status)
2673 goto err;
5eeff635
SR		 2674
2675 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 2676
5eeff635
SR		 2677 wait_for_completion(&adapter->et_cmd_compl);
2678 resp = embedded_payload(wrb);
2679 status = le32_to_cpu(resp->status);
2680
2681 return status;
ff33a6e2
S		 2682err:
2683 spin_unlock_bh(&adapter->mcc_lock);
2684 return status;
2685}
2686
2687int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 2688 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 2689{
2690 struct be_mcc_wrb *wrb;
2691 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2692 int status;
2693 int i, j = 0;
2694
2695 spin_lock_bh(&adapter->mcc_lock);
2696
2697 wrb = wrb_from_mccq(adapter);
2698 if (!wrb) {
2699 status = -EBUSY;
2700 goto err;
2701 }
2702 req = cmd->va;
106df1e3 2703 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2704 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2705 cmd);
ff33a6e2
S		 2706
2707 req->pattern = cpu_to_le64(pattern);
2708 req->byte_count = cpu_to_le32(byte_cnt);
2709 for (i = 0; i < byte_cnt; i++) {
2710 req->snd_buff[i] = (u8)(pattern >> (j*8));
2711 j++;
2712 if (j > 7)
2713 j = 0;
2714 }
2715
2716 status = be_mcc_notify_wait(adapter);
2717
2718 if (!status) {
2719 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 2720
ff33a6e2
S		 2721 resp = cmd->va;
2722 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
cd3307aa 2723 resp->snd_err) {
ff33a6e2
S		 2724 status = -1;
2725 }
2726 }
2727
2728err:
2729 spin_unlock_bh(&adapter->mcc_lock);
2730 return status;
2731}
368c0ca2 2732
c196b02c 2733int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 2734 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 2735{
2736 struct be_mcc_wrb *wrb;
2737 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 2738 int status;
2739
2740 spin_lock_bh(&adapter->mcc_lock);
2741
2742 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2743 if (!wrb) {
2744 status = -EBUSY;
2745 goto err;
2746 }
368c0ca2 2747 req = nonemb_cmd->va;
368c0ca2 2748
106df1e3 2749 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2750 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2751 nonemb_cmd);
368c0ca2
SB		 2752
2753 status = be_mcc_notify_wait(adapter);
2754
e45ff01d 2755err:
368c0ca2
SB		 2756 spin_unlock_bh(&adapter->mcc_lock);
2757 return status;
2758}
ee3cb629 2759
42f11cf2 2760int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2761{
2762 struct be_mcc_wrb *wrb;
2763 struct be_cmd_req_get_phy_info *req;
306f1348 2764 struct be_dma_mem cmd;
ee3cb629
AK		 2765 int status;
2766
f25b119c
PR		 2767 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2768 CMD_SUBSYSTEM_COMMON))
2769 return -EPERM;
2770
ee3cb629
AK		 2771 spin_lock_bh(&adapter->mcc_lock);
2772
2773 wrb = wrb_from_mccq(adapter);
2774 if (!wrb) {
2775 status = -EBUSY;
2776 goto err;
2777 }
306f1348 2778 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
e51000db
SB		 2779 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2780 GFP_ATOMIC);
306f1348
SP		 2781 if (!cmd.va) {
2782 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2783 status = -ENOMEM;
2784 goto err;
2785 }
ee3cb629 2786
306f1348 2787 req = cmd.va;
ee3cb629 2788
106df1e3 2789 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2790 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2791 wrb, &cmd);
ee3cb629
AK		 2792
2793 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2794 if (!status) {
2795 struct be_phy_info *resp_phy_info =
2796 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 2797
42f11cf2
AK		 2798 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2799 adapter->phy.interface_type =
306f1348 2800 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2801 adapter->phy.auto_speeds_supported =
2802 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2803 adapter->phy.fixed_speeds_supported =
2804 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2805 adapter->phy.misc_params =
2806 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 2807
2808 if (BE2_chip(adapter)) {
2809 adapter->phy.fixed_speeds_supported =
2810 BE_SUPPORTED_SPEED_10GBPS |
2811 BE_SUPPORTED_SPEED_1GBPS;
2812 }
306f1348 2813 }
e51000db 2814 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
ee3cb629
AK		 2815err:
2816 spin_unlock_bh(&adapter->mcc_lock);
2817 return status;
2818}
e1d18735 2819
bc0ee163 2820static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
e1d18735
AK		 2821{
2822 struct be_mcc_wrb *wrb;
2823 struct be_cmd_req_set_qos *req;
2824 int status;
2825
2826 spin_lock_bh(&adapter->mcc_lock);
2827
2828 wrb = wrb_from_mccq(adapter);
2829 if (!wrb) {
2830 status = -EBUSY;
2831 goto err;
2832 }
2833
2834 req = embedded_payload(wrb);
2835
106df1e3 2836 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 2837 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2838
2839 req->hdr.domain = domain;
6bff57a7
AK		 2840 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2841 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2842
2843 status = be_mcc_notify_wait(adapter);
2844
2845err:
2846 spin_unlock_bh(&adapter->mcc_lock);
2847 return status;
2848}
9e1453c5
AK		 2849
2850int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2851{
2852 struct be_mcc_wrb *wrb;
2853 struct be_cmd_req_cntl_attribs *req;
2854 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2855 int status;
2856 int payload_len = max(sizeof(*req), sizeof(*resp));
2857 struct mgmt_controller_attrib *attribs;
2858 struct be_dma_mem attribs_cmd;
2859
d98ef50f
SR		 2860 if (mutex_lock_interruptible(&adapter->mbox_lock))
2861 return -1;
2862
9e1453c5
AK		 2863 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2864 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
e51000db
SB		 2865 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
2866 attribs_cmd.size,
2867 &attribs_cmd.dma, GFP_ATOMIC);
9e1453c5 2868 if (!attribs_cmd.va) {
a2cc4e0b 2869 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 2870 status = -ENOMEM;
2871 goto err;
9e1453c5
AK		 2872 }
2873
9e1453c5
AK		 2874 wrb = wrb_from_mbox(adapter);
2875 if (!wrb) {
2876 status = -EBUSY;
2877 goto err;
2878 }
2879 req = attribs_cmd.va;
9e1453c5 2880
106df1e3 2881 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2882 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2883 wrb, &attribs_cmd);
9e1453c5
AK		 2884
2885 status = be_mbox_notify_wait(adapter);
2886 if (!status) {
43d620c8 2887 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2888 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2889 }
2890
2891err:
2892 mutex_unlock(&adapter->mbox_lock);
d98ef50f 2893 if (attribs_cmd.va)
e51000db
SB		 2894 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
2895 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 2896 return status;
2897}
2e588f84
SP		 2898
2899/* Uses mbox */
2dc1deb6 2900int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2901{
2902 struct be_mcc_wrb *wrb;
2903 struct be_cmd_req_set_func_cap *req;
2904 int status;
2905
2906 if (mutex_lock_interruptible(&adapter->mbox_lock))
2907 return -1;
2908
2909 wrb = wrb_from_mbox(adapter);
2910 if (!wrb) {
2911 status = -EBUSY;
2912 goto err;
2913 }
2914
2915 req = embedded_payload(wrb);
2916
106df1e3 2917 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2918 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2919 sizeof(*req), wrb, NULL);
2e588f84
SP		 2920
2921 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2922 CAPABILITY_BE3_NATIVE_ERX_API);
2923 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2924
2925 status = be_mbox_notify_wait(adapter);
2926 if (!status) {
2927 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 2928
2e588f84
SP		 2929 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2930 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 2931 if (!adapter->be3_native)
2932 dev_warn(&adapter->pdev->dev,
2933 "adapter not in advanced mode\n");
2e588f84
SP		 2934 }
2935err:
2936 mutex_unlock(&adapter->mbox_lock);
2937 return status;
2938}
590c391d 2939
f25b119c
PR		 2940/* Get privilege(s) for a function */
2941int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2942 u32 domain)
2943{
2944 struct be_mcc_wrb *wrb;
2945 struct be_cmd_req_get_fn_privileges *req;
2946 int status;
2947
2948 spin_lock_bh(&adapter->mcc_lock);
2949
2950 wrb = wrb_from_mccq(adapter);
2951 if (!wrb) {
2952 status = -EBUSY;
2953 goto err;
2954 }
2955
2956 req = embedded_payload(wrb);
2957
2958 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2959 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2960 wrb, NULL);
2961
2962 req->hdr.domain = domain;
2963
2964 status = be_mcc_notify_wait(adapter);
2965 if (!status) {
2966 struct be_cmd_resp_get_fn_privileges *resp =
2967 embedded_payload(wrb);
03d28ffe 2968
f25b119c 2969 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 2970
2971 /* In UMC mode FW does not return right privileges.
2972 * Override with correct privilege equivalent to PF.
2973 */
2974 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2975 be_physfn(adapter))
2976 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 2977 }
2978
2979err:
2980 spin_unlock_bh(&adapter->mcc_lock);
2981 return status;
2982}
2983
04a06028
SP		 2984/* Set privilege(s) for a function */
2985int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2986 u32 domain)
2987{
2988 struct be_mcc_wrb *wrb;
2989 struct be_cmd_req_set_fn_privileges *req;
2990 int status;
2991
2992 spin_lock_bh(&adapter->mcc_lock);
2993
2994 wrb = wrb_from_mccq(adapter);
2995 if (!wrb) {
2996 status = -EBUSY;
2997 goto err;
2998 }
2999
3000 req = embedded_payload(wrb);
3001 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3002 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3003 wrb, NULL);
3004 req->hdr.domain = domain;
3005 if (lancer_chip(adapter))
3006 req->privileges_lancer = cpu_to_le32(privileges);
3007 else
3008 req->privileges = cpu_to_le32(privileges);
3009
3010 status = be_mcc_notify_wait(adapter);
3011err:
3012 spin_unlock_bh(&adapter->mcc_lock);
3013 return status;
3014}
3015
5a712c13
SP		 3016/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3017 * pmac_id_valid: false => pmac_id or MAC address is requested.
3018 * If pmac_id is returned, pmac_id_valid is returned as true
3019 */
1578e777 3020int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 3021 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3022 u8 domain)
590c391d
PR		 3023{
3024 struct be_mcc_wrb *wrb;
3025 struct be_cmd_req_get_mac_list *req;
3026 int status;
3027 int mac_count;
e5e1ee89
PR		 3028 struct be_dma_mem get_mac_list_cmd;
3029 int i;
3030
3031 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3032 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
e51000db
SB		 3033 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3034 get_mac_list_cmd.size,
3035 &get_mac_list_cmd.dma,
3036 GFP_ATOMIC);
e5e1ee89
PR		 3037
3038 if (!get_mac_list_cmd.va) {
3039 dev_err(&adapter->pdev->dev,
a2cc4e0b 3040 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 3041 return -ENOMEM;
3042 }
590c391d
PR		 3043
3044 spin_lock_bh(&adapter->mcc_lock);
3045
3046 wrb = wrb_from_mccq(adapter);
3047 if (!wrb) {
3048 status = -EBUSY;
e5e1ee89 3049 goto out;
590c391d 3050 }
e5e1ee89
PR		 3051
3052 req = get_mac_list_cmd.va;
590c391d
PR		 3053
3054 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 3055 OPCODE_COMMON_GET_MAC_LIST,
3056 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 3057 req->hdr.domain = domain;
e5e1ee89 3058 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 3059 if (*pmac_id_valid) {
3060 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 3061 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 3062 req->perm_override = 0;
3063 } else {
3064 req->perm_override = 1;
3065 }
590c391d
PR		 3066
3067 status = be_mcc_notify_wait(adapter);
3068 if (!status) {
3069 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 3070 get_mac_list_cmd.va;
5a712c13
SP		 3071
3072 if (*pmac_id_valid) {
3073 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3074 ETH_ALEN);
3075 goto out;
3076 }
3077
e5e1ee89
PR		 3078 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3079 /* Mac list returned could contain one or more active mac_ids
dbedd44e 3080 * or one or more true or pseudo permanent mac addresses.
1578e777
PR		 3081 * If an active mac_id is present, return first active mac_id
3082 * found.
e5e1ee89 3083 */
590c391d 3084 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3085 struct get_list_macaddr *mac_entry;
3086 u16 mac_addr_size;
3087 u32 mac_id;
3088
3089 mac_entry = &resp->macaddr_list[i];
3090 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3091 /* mac_id is a 32 bit value and mac_addr size
3092 * is 6 bytes
3093 */
3094 if (mac_addr_size == sizeof(u32)) {
5a712c13 3095 *pmac_id_valid = true;
e5e1ee89
PR		 3096 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3097 *pmac_id = le32_to_cpu(mac_id);
3098 goto out;
590c391d 3099 }
590c391d 3100 }
1578e777 3101 /* If no active mac_id found, return first mac addr */
5a712c13 3102 *pmac_id_valid = false;
e5e1ee89 3103 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3104 ETH_ALEN);
590c391d
PR		 3105 }
3106
e5e1ee89 3107out:
590c391d 3108 spin_unlock_bh(&adapter->mcc_lock);
e51000db
SB		 3109 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3110 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3111 return status;
3112}
3113
a2cc4e0b
SP		 3114int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3115 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3116{
b188f090
SR		 3117 if (!active)
3118 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3119 if_handle, domain);
3175d8c2 3120 if (BEx_chip(adapter))
5a712c13 3121 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3122 if_handle, curr_pmac_id);
3175d8c2
SP		 3123 else
3124 /* Fetch the MAC address using pmac_id */
3125 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3126 &curr_pmac_id,
3127 if_handle, domain);
5a712c13
SP		 3128}
3129
95046b92
SP		 3130int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3131{
3132 int status;
3133 bool pmac_valid = false;
3134
c7bf7169 3135 eth_zero_addr(mac);
95046b92 3136
3175d8c2
SP		 3137 if (BEx_chip(adapter)) {
3138 if (be_physfn(adapter))
3139 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3140 0);
3141 else
3142 status = be_cmd_mac_addr_query(adapter, mac, false,
3143 adapter->if_handle, 0);
3144 } else {
95046b92 3145 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3146 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3147 }
3148
95046b92
SP		 3149 return status;
3150}
3151
590c391d
PR		 3152/* Uses synchronous MCCQ */
3153int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3154 u8 mac_count, u32 domain)
3155{
3156 struct be_mcc_wrb *wrb;
3157 struct be_cmd_req_set_mac_list *req;
3158 int status;
3159 struct be_dma_mem cmd;
3160
3161 memset(&cmd, 0, sizeof(struct be_dma_mem));
3162 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
e51000db
SB		 3163 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3164 GFP_KERNEL);
d0320f75 3165 if (!cmd.va)
590c391d 3166 return -ENOMEM;
590c391d
PR		 3167
3168 spin_lock_bh(&adapter->mcc_lock);
3169
3170 wrb = wrb_from_mccq(adapter);
3171 if (!wrb) {
3172 status = -EBUSY;
3173 goto err;
3174 }
3175
3176 req = cmd.va;
3177 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3178 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3179 wrb, &cmd);
590c391d
PR		 3180
3181 req->hdr.domain = domain;
3182 req->mac_count = mac_count;
3183 if (mac_count)
3184 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3185
3186 status = be_mcc_notify_wait(adapter);
3187
3188err:
a2cc4e0b 3189 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
590c391d
PR		 3190 spin_unlock_bh(&adapter->mcc_lock);
3191 return status;
3192}
4762f6ce 3193
3175d8c2
SP		 3194/* Wrapper to delete any active MACs and provision the new mac.
3195 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3196 * current list are active.
3197 */
3198int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3199{
3200 bool active_mac = false;
3201 u8 old_mac[ETH_ALEN];
3202 u32 pmac_id;
3203 int status;
3204
3205 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3206 &pmac_id, if_id, dom);
3207
3175d8c2
SP		 3208 if (!status && active_mac)
3209 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3210
3211 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3212}
3213
f1f3ee1b 3214int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
e7bcbd7b 3215 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
f1f3ee1b
AK		 3216{
3217 struct be_mcc_wrb *wrb;
3218 struct be_cmd_req_set_hsw_config *req;
3219 void *ctxt;
3220 int status;
3221
3222 spin_lock_bh(&adapter->mcc_lock);
3223
3224 wrb = wrb_from_mccq(adapter);
3225 if (!wrb) {
3226 status = -EBUSY;
3227 goto err;
3228 }
3229
3230 req = embedded_payload(wrb);
3231 ctxt = &req->context;
3232
3233 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3234 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3235 NULL);
f1f3ee1b
AK		 3236
3237 req->hdr.domain = domain;
3238 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3239 if (pvid) {
3240 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3241 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3242 }
a77dcb8c
AK		 3243 if (!BEx_chip(adapter) && hsw_mode) {
3244 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3245 ctxt, adapter->hba_port_num);
3246 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3247 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3248 ctxt, hsw_mode);
3249 }
f1f3ee1b 3250
e7bcbd7b
KA		 3251 /* Enable/disable both mac and vlan spoof checking */
3252 if (!BEx_chip(adapter) && spoofchk) {
3253 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3254 ctxt, spoofchk);
3255 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3256 ctxt, spoofchk);
3257 }
3258
f1f3ee1b
AK		 3259 be_dws_cpu_to_le(req->context, sizeof(req->context));
3260 status = be_mcc_notify_wait(adapter);
3261
3262err:
3263 spin_unlock_bh(&adapter->mcc_lock);
3264 return status;
3265}
3266
3267/* Get Hyper switch config */
3268int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
e7bcbd7b 3269 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
f1f3ee1b
AK		 3270{
3271 struct be_mcc_wrb *wrb;
3272 struct be_cmd_req_get_hsw_config *req;
3273 void *ctxt;
3274 int status;
3275 u16 vid;
3276
3277 spin_lock_bh(&adapter->mcc_lock);
3278
3279 wrb = wrb_from_mccq(adapter);
3280 if (!wrb) {
3281 status = -EBUSY;
3282 goto err;
3283 }
3284
3285 req = embedded_payload(wrb);
3286 ctxt = &req->context;
3287
3288 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3289 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3290 NULL);
f1f3ee1b
AK		 3291
3292 req->hdr.domain = domain;
a77dcb8c
AK		 3293 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3294 ctxt, intf_id);
f1f3ee1b 3295 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3296
2c07c1d7 3297 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3298 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3299 ctxt, adapter->hba_port_num);
3300 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3301 }
f1f3ee1b
AK		 3302 be_dws_cpu_to_le(req->context, sizeof(req->context));
3303
3304 status = be_mcc_notify_wait(adapter);
3305 if (!status) {
3306 struct be_cmd_resp_get_hsw_config *resp =
3307 embedded_payload(wrb);
03d28ffe 3308
a2cc4e0b 3309 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3310 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3311 pvid, &resp->context);
a77dcb8c
AK		 3312 if (pvid)
3313 *pvid = le16_to_cpu(vid);
3314 if (mode)
3315 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3316 port_fwd_type, &resp->context);
e7bcbd7b
KA		 3317 if (spoofchk)
3318 *spoofchk =
3319 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3320 spoofchk, &resp->context);
f1f3ee1b
AK		 3321 }
3322
3323err:
3324 spin_unlock_bh(&adapter->mcc_lock);
3325 return status;
3326}
3327
f7062ee5
SP		 3328static bool be_is_wol_excluded(struct be_adapter *adapter)
3329{
3330 struct pci_dev *pdev = adapter->pdev;
3331
18c57c74 3332 if (be_virtfn(adapter))
f7062ee5
SP		 3333 return true;
3334
3335 switch (pdev->subsystem_device) {
3336 case OC_SUBSYS_DEVICE_ID1:
3337 case OC_SUBSYS_DEVICE_ID2:
3338 case OC_SUBSYS_DEVICE_ID3:
3339 case OC_SUBSYS_DEVICE_ID4:
3340 return true;
3341 default:
3342 return false;
3343 }
3344}
3345
4762f6ce
AK		 3346int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3347{
3348 struct be_mcc_wrb *wrb;
3349 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3350 int status = 0;
4762f6ce
AK		 3351 struct be_dma_mem cmd;
3352
f25b119c
PR		 3353 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3354 CMD_SUBSYSTEM_ETH))
3355 return -EPERM;
3356
76a9e08e
SR		 3357 if (be_is_wol_excluded(adapter))
3358 return status;
3359
d98ef50f
SR		 3360 if (mutex_lock_interruptible(&adapter->mbox_lock))
3361 return -1;
3362
4762f6ce
AK		 3363 memset(&cmd, 0, sizeof(struct be_dma_mem));
3364 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
e51000db
SB		 3365 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3366 GFP_ATOMIC);
4762f6ce 3367 if (!cmd.va) {
a2cc4e0b 3368 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3369 status = -ENOMEM;
3370 goto err;
4762f6ce
AK		 3371 }
3372
4762f6ce
AK		 3373 wrb = wrb_from_mbox(adapter);
3374 if (!wrb) {
3375 status = -EBUSY;
3376 goto err;
3377 }
3378
3379 req = cmd.va;
3380
3381 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3382 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 3383 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 3384
3385 req->hdr.version = 1;
3386 req->query_options = BE_GET_WOL_CAP;
3387
3388 status = be_mbox_notify_wait(adapter);
3389 if (!status) {
3390 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 3391
504fbf1e 3392 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 3393
4762f6ce 3394 adapter->wol_cap = resp->wol_settings;
76a9e08e
SR		 3395 if (adapter->wol_cap & BE_WOL_CAP)
3396 adapter->wol_en = true;
4762f6ce
AK		 3397 }
3398err:
3399 mutex_unlock(&adapter->mbox_lock);
d98ef50f 3400 if (cmd.va)
e51000db
SB		 3401 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3402 cmd.dma);
4762f6ce 3403 return status;
941a77d5
SK		 3404
3405}
baaa08d1
VV		 3406
3407int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3408{
3409 struct be_dma_mem extfat_cmd;
3410 struct be_fat_conf_params *cfgs;
3411 int status;
3412 int i, j;
3413
3414 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3415 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
e51000db
SB		 3416 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3417 extfat_cmd.size, &extfat_cmd.dma,
3418 GFP_ATOMIC);
baaa08d1
VV		 3419 if (!extfat_cmd.va)
3420 return -ENOMEM;
3421
3422 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3423 if (status)
3424 goto err;
3425
3426 cfgs = (struct be_fat_conf_params *)
3427 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3428 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3429 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 3430
baaa08d1
VV		 3431 for (j = 0; j < num_modes; j++) {
3432 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3433 cfgs->module[i].trace_lvl[j].dbg_lvl =
3434 cpu_to_le32(level);
3435 }
3436 }
3437
3438 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3439err:
e51000db
SB		 3440 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
3441 extfat_cmd.dma);
baaa08d1
VV		 3442 return status;
3443}
3444
3445int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3446{
3447 struct be_dma_mem extfat_cmd;
3448 struct be_fat_conf_params *cfgs;
3449 int status, j;
3450 int level = 0;
3451
3452 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3453 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
e51000db
SB		 3454 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3455 extfat_cmd.size, &extfat_cmd.dma,
3456 GFP_ATOMIC);
baaa08d1
VV		 3457
3458 if (!extfat_cmd.va) {
3459 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3460 __func__);
3461 goto err;
3462 }
3463
3464 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3465 if (!status) {
3466 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3467 sizeof(struct be_cmd_resp_hdr));
03d28ffe 3468
baaa08d1
VV		 3469 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3470 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3471 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3472 }
3473 }
e51000db
SB		 3474 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
3475 extfat_cmd.dma);
baaa08d1
VV		 3476err:
3477 return level;
3478}
3479
941a77d5
SK		 3480int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3481 struct be_dma_mem *cmd)
3482{
3483 struct be_mcc_wrb *wrb;
3484 struct be_cmd_req_get_ext_fat_caps *req;
3485 int status;
3486
3487 if (mutex_lock_interruptible(&adapter->mbox_lock))
3488 return -1;
3489
3490 wrb = wrb_from_mbox(adapter);
3491 if (!wrb) {
3492 status = -EBUSY;
3493 goto err;
3494 }
3495
3496 req = cmd->va;
3497 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3498 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3499 cmd->size, wrb, cmd);
3500 req->parameter_type = cpu_to_le32(1);
3501
3502 status = be_mbox_notify_wait(adapter);
3503err:
3504 mutex_unlock(&adapter->mbox_lock);
3505 return status;
3506}
3507
3508int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3509 struct be_dma_mem *cmd,
3510 struct be_fat_conf_params *configs)
3511{
3512 struct be_mcc_wrb *wrb;
3513 struct be_cmd_req_set_ext_fat_caps *req;
3514 int status;
3515
3516 spin_lock_bh(&adapter->mcc_lock);
3517
3518 wrb = wrb_from_mccq(adapter);
3519 if (!wrb) {
3520 status = -EBUSY;
3521 goto err;
3522 }
3523
3524 req = cmd->va;
3525 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3526 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3527 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3528 cmd->size, wrb, cmd);
3529
3530 status = be_mcc_notify_wait(adapter);
3531err:
3532 spin_unlock_bh(&adapter->mcc_lock);
3533 return status;
4762f6ce 3534}
6a4ab669 3535
21252377 3536int be_cmd_query_port_name(struct be_adapter *adapter)
b4e32a71 3537{
b4e32a71 3538 struct be_cmd_req_get_port_name *req;
21252377 3539 struct be_mcc_wrb *wrb;
b4e32a71
PR		 3540 int status;
3541
21252377
VV		 3542 if (mutex_lock_interruptible(&adapter->mbox_lock))
3543 return -1;
b4e32a71 3544
21252377 3545 wrb = wrb_from_mbox(adapter);
b4e32a71
PR		 3546 req = embedded_payload(wrb);
3547
3548 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3549 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3550 NULL);
21252377
VV		 3551 if (!BEx_chip(adapter))
3552 req->hdr.version = 1;
b4e32a71 3553
21252377 3554 status = be_mbox_notify_wait(adapter);
b4e32a71
PR		 3555 if (!status) {
3556 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 3557
21252377 3558 adapter->port_name = resp->port_name[adapter->hba_port_num];
b4e32a71 3559 } else {
21252377 3560 adapter->port_name = adapter->hba_port_num + '0';
b4e32a71 3561 }
21252377
VV		 3562
3563 mutex_unlock(&adapter->mbox_lock);
b4e32a71
PR		 3564 return status;
3565}
3566
10cccf60
VV		 3567/* Descriptor type */
3568enum {
3569 FUNC_DESC = 1,
3570 VFT_DESC = 2
3571};
3572
3573static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3574 int desc_type)
abb93951 3575{
150d58c7 3576 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 3577 struct be_nic_res_desc *nic;
abb93951
PR		 3578 int i;
3579
3580 for (i = 0; i < desc_count; i++) {
150d58c7 3581 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 3582 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3583 nic = (struct be_nic_res_desc *)hdr;
3584 if (desc_type == FUNC_DESC ||
3585 (desc_type == VFT_DESC &&
3586 nic->flags & (1 << VFT_SHIFT)))
3587 return nic;
3588 }
abb93951 3589
150d58c7
VV		 3590 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3591 hdr = (void *)hdr + hdr->desc_len;
abb93951 3592 }
150d58c7
VV		 3593 return NULL;
3594}
3595
10cccf60
VV		 3596static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3597{
3598 return be_get_nic_desc(buf, desc_count, VFT_DESC);
3599}
3600
3601static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3602{
3603 return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3604}
3605
150d58c7
VV		 3606static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3607 u32 desc_count)
3608{
3609 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3610 struct be_pcie_res_desc *pcie;
3611 int i;
3612
3613 for (i = 0; i < desc_count; i++) {
3614 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3615 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3616 pcie = (struct be_pcie_res_desc *)hdr;
3617 if (pcie->pf_num == devfn)
3618 return pcie;
3619 }
abb93951 3620
150d58c7
VV		 3621 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3622 hdr = (void *)hdr + hdr->desc_len;
3623 }
950e2958 3624 return NULL;
abb93951
PR		 3625}
3626
f93f160b
VV		 3627static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3628{
3629 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3630 int i;
3631
3632 for (i = 0; i < desc_count; i++) {
3633 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3634 return (struct be_port_res_desc *)hdr;
3635
3636 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3637 hdr = (void *)hdr + hdr->desc_len;
3638 }
3639 return NULL;
3640}
3641
92bf14ab
SP		 3642static void be_copy_nic_desc(struct be_resources *res,
3643 struct be_nic_res_desc *desc)
3644{
3645 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3646 res->max_vlans = le16_to_cpu(desc->vlan_count);
3647 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3648 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3649 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3650 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3651 res->max_evt_qs = le16_to_cpu(desc->eq_count);
f2858738
VV		 3652 res->max_cq_count = le16_to_cpu(desc->cq_count);
3653 res->max_iface_count = le16_to_cpu(desc->iface_count);
3654 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
92bf14ab
SP		 3655 /* Clear flags that driver is not interested in */
3656 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3657 BE_IF_CAP_FLAGS_WANT;
92bf14ab
SP		 3658}
3659
abb93951 3660/* Uses Mbox */
92bf14ab 3661int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 3662{
3663 struct be_mcc_wrb *wrb;
3664 struct be_cmd_req_get_func_config *req;
3665 int status;
3666 struct be_dma_mem cmd;
3667
d98ef50f
SR		 3668 if (mutex_lock_interruptible(&adapter->mbox_lock))
3669 return -1;
3670
abb93951
PR		 3671 memset(&cmd, 0, sizeof(struct be_dma_mem));
3672 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
e51000db
SB		 3673 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3674 GFP_ATOMIC);
abb93951
PR		 3675 if (!cmd.va) {
3676 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 3677 status = -ENOMEM;
3678 goto err;
abb93951 3679 }
abb93951
PR		 3680
3681 wrb = wrb_from_mbox(adapter);
3682 if (!wrb) {
3683 status = -EBUSY;
3684 goto err;
3685 }
3686
3687 req = cmd.va;
3688
3689 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3690 OPCODE_COMMON_GET_FUNC_CONFIG,
3691 cmd.size, wrb, &cmd);
3692
28710c55
KA		 3693 if (skyhawk_chip(adapter))
3694 req->hdr.version = 1;
3695
abb93951
PR		 3696 status = be_mbox_notify_wait(adapter);
3697 if (!status) {
3698 struct be_cmd_resp_get_func_config *resp = cmd.va;
3699 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 3700 struct be_nic_res_desc *desc;
abb93951 3701
10cccf60 3702 desc = be_get_func_nic_desc(resp->func_param, desc_count);
abb93951
PR		 3703 if (!desc) {
3704 status = -EINVAL;
3705 goto err;
3706 }
3707
d5c18473 3708 adapter->pf_number = desc->pf_num;
92bf14ab 3709 be_copy_nic_desc(res, desc);
abb93951
PR		 3710 }
3711err:
3712 mutex_unlock(&adapter->mbox_lock);
d98ef50f 3713 if (cmd.va)
e51000db
SB		 3714 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3715 cmd.dma);
abb93951
PR		 3716 return status;
3717}
3718
ba48c0c9 3719/* Will use MBOX only if MCCQ has not been created */
92bf14ab 3720int be_cmd_get_profile_config(struct be_adapter *adapter,
f2858738 3721 struct be_resources *res, u8 query, u8 domain)
a05f99db 3722{
150d58c7 3723 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 3724 struct be_cmd_req_get_profile_config *req;
10cccf60 3725 struct be_nic_res_desc *vf_res;
150d58c7 3726 struct be_pcie_res_desc *pcie;
f93f160b 3727 struct be_port_res_desc *port;
150d58c7 3728 struct be_nic_res_desc *nic;
ba48c0c9 3729 struct be_mcc_wrb wrb = {0};
a05f99db 3730 struct be_dma_mem cmd;
f2858738 3731 u16 desc_count;
a05f99db
VV		 3732 int status;
3733
3734 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7 3735 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
e51000db
SB		 3736 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3737 GFP_ATOMIC);
150d58c7 3738 if (!cmd.va)
a05f99db 3739 return -ENOMEM;
a05f99db 3740
ba48c0c9
VV		 3741 req = cmd.va;
3742 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3743 OPCODE_COMMON_GET_PROFILE_CONFIG,
3744 cmd.size, &wrb, &cmd);
3745
3746 req->hdr.domain = domain;
3747 if (!lancer_chip(adapter))
3748 req->hdr.version = 1;
3749 req->type = ACTIVE_PROFILE_TYPE;
3750
f2858738
VV		 3751 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
3752 * descriptors with all bits set to "1" for the fields which can be
3753 * modified using SET_PROFILE_CONFIG cmd.
3754 */
3755 if (query == RESOURCE_MODIFIABLE)
3756 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
3757
ba48c0c9 3758 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 3759 if (status)
3760 goto err;
abb93951 3761
150d58c7 3762 resp = cmd.va;
f2858738 3763 desc_count = le16_to_cpu(resp->desc_count);
abb93951 3764
a2cc4e0b
SP		 3765 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3766 desc_count);
150d58c7 3767 if (pcie)
92bf14ab 3768 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 3769
f93f160b
VV		 3770 port = be_get_port_desc(resp->func_param, desc_count);
3771 if (port)
3772 adapter->mc_type = port->mc_type;
3773
10cccf60 3774 nic = be_get_func_nic_desc(resp->func_param, desc_count);
92bf14ab
SP		 3775 if (nic)
3776 be_copy_nic_desc(res, nic);
3777
10cccf60
VV		 3778 vf_res = be_get_vft_desc(resp->func_param, desc_count);
3779 if (vf_res)
3780 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 3781err:
a05f99db 3782 if (cmd.va)
e51000db
SB		 3783 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3784 cmd.dma);
abb93951
PR		 3785 return status;
3786}
3787
bec84e6b
VV		 3788/* Will use MBOX only if MCCQ has not been created */
3789static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3790 int size, int count, u8 version, u8 domain)
d5c18473 3791{
d5c18473 3792 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 3793 struct be_mcc_wrb wrb = {0};
3794 struct be_dma_mem cmd;
d5c18473
PR		 3795 int status;
3796
bec84e6b
VV		 3797 memset(&cmd, 0, sizeof(struct be_dma_mem));
3798 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
e51000db
SB		 3799 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3800 GFP_ATOMIC);
bec84e6b
VV		 3801 if (!cmd.va)
3802 return -ENOMEM;
d5c18473 3803
bec84e6b 3804 req = cmd.va;
d5c18473 3805 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 3806 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3807 &wrb, &cmd);
a401801c 3808 req->hdr.version = version;
d5c18473 3809 req->hdr.domain = domain;
bec84e6b 3810 req->desc_count = cpu_to_le32(count);
a401801c
SP		 3811 memcpy(req->desc, desc, size);
3812
bec84e6b
VV		 3813 status = be_cmd_notify_wait(adapter, &wrb);
3814
3815 if (cmd.va)
e51000db
SB		 3816 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3817 cmd.dma);
d5c18473
PR		 3818 return status;
3819}
3820
a401801c 3821/* Mark all fields invalid */
bec84e6b 3822static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 3823{
3824 memset(nic, 0, sizeof(*nic));
3825 nic->unicast_mac_count = 0xFFFF;
3826 nic->mcc_count = 0xFFFF;
3827 nic->vlan_count = 0xFFFF;
3828 nic->mcast_mac_count = 0xFFFF;
3829 nic->txq_count = 0xFFFF;
3830 nic->rq_count = 0xFFFF;
3831 nic->rssq_count = 0xFFFF;
3832 nic->lro_count = 0xFFFF;
3833 nic->cq_count = 0xFFFF;
3834 nic->toe_conn_count = 0xFFFF;
3835 nic->eq_count = 0xFFFF;
0f77ba73 3836 nic->iface_count = 0xFFFF;
a401801c 3837 nic->link_param = 0xFF;
0f77ba73 3838 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 3839 nic->acpi_params = 0xFF;
3840 nic->wol_param = 0x0F;
0f77ba73
RN		 3841 nic->tunnel_iface_count = 0xFFFF;
3842 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 3843 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 3844 nic->bw_max = 0xFFFFFFFF;
3845}
3846
bec84e6b
VV		 3847/* Mark all fields invalid */
3848static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3849{
3850 memset(pcie, 0, sizeof(*pcie));
3851 pcie->sriov_state = 0xFF;
3852 pcie->pf_state = 0xFF;
3853 pcie->pf_type = 0xFF;
3854 pcie->num_vfs = 0xFFFF;
3855}
3856
0f77ba73
RN		 3857int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3858 u8 domain)
a401801c 3859{
0f77ba73
RN		 3860 struct be_nic_res_desc nic_desc;
3861 u32 bw_percent;
3862 u16 version = 0;
3863
3864 if (BE3_chip(adapter))
3865 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 3866
0f77ba73
RN		 3867 be_reset_nic_desc(&nic_desc);
3868 nic_desc.pf_num = adapter->pf_number;
3869 nic_desc.vf_num = domain;
58bdeaa6 3870 nic_desc.bw_min = 0;
0f77ba73 3871 if (lancer_chip(adapter)) {
a401801c
SP		 3872 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3873 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3874 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3875 (1 << NOSV_SHIFT);
0f77ba73 3876 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 3877 } else {
0f77ba73
RN		 3878 version = 1;
3879 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3880 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3881 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3882 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3883 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 3884 }
0f77ba73
RN		 3885
3886 return be_cmd_set_profile_config(adapter, &nic_desc,
3887 nic_desc.hdr.desc_len,
bec84e6b
VV		 3888 1, version, domain);
3889}
3890
f2858738
VV		 3891static void be_fill_vf_res_template(struct be_adapter *adapter,
3892 struct be_resources pool_res,
3893 u16 num_vfs, u16 num_vf_qs,
3894 struct be_nic_res_desc *nic_vft)
3895{
3896 u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
3897 struct be_resources res_mod = {0};
3898
3899 /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
3900 * which are modifiable using SET_PROFILE_CONFIG cmd.
3901 */
3902 be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
3903
3904 /* If RSS IFACE capability flags are modifiable for a VF, set the
3905 * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
3906 * more than 1 RSSQ is available for a VF.
3907 * Otherwise, provision only 1 queue pair for VF.
3908 */
3909 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3910 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
3911 if (num_vf_qs > 1) {
3912 vf_if_cap_flags |= BE_IF_FLAGS_RSS;
3913 if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
3914 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
3915 } else {
3916 vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
3917 BE_IF_FLAGS_DEFQ_RSS);
3918 }
3919
3920 nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
3921 } else {
3922 num_vf_qs = 1;
3923 }
3924
3925 nic_vft->rq_count = cpu_to_le16(num_vf_qs);
3926 nic_vft->txq_count = cpu_to_le16(num_vf_qs);
3927 nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
3928 nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
3929 (num_vfs + 1));
3930
3931 /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
3932 * among the PF and it's VFs, if the fields are changeable
3933 */
3934 if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
3935 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
3936 (num_vfs + 1));
3937
3938 if (res_mod.max_vlans == FIELD_MODIFIABLE)
3939 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
3940 (num_vfs + 1));
3941
3942 if (res_mod.max_iface_count == FIELD_MODIFIABLE)
3943 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
3944 (num_vfs + 1));
3945
3946 if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
3947 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
3948 (num_vfs + 1));
3949}
3950
bec84e6b 3951int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738
VV		 3952 struct be_resources pool_res, u16 num_vfs,
3953 u16 num_vf_qs)
bec84e6b
VV		 3954{
3955 struct {
3956 struct be_pcie_res_desc pcie;
3957 struct be_nic_res_desc nic_vft;
3958 } __packed desc;
bec84e6b 3959
bec84e6b
VV		 3960 /* PF PCIE descriptor */
3961 be_reset_pcie_desc(&desc.pcie);
3962 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3963 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 3964 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 3965 desc.pcie.pf_num = adapter->pdev->devfn;
3966 desc.pcie.sriov_state = num_vfs ? 1 : 0;
3967 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3968
3969 /* VF NIC Template descriptor */
3970 be_reset_nic_desc(&desc.nic_vft);
3971 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3972 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 3973 desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 3974 desc.nic_vft.pf_num = adapter->pdev->devfn;
3975 desc.nic_vft.vf_num = 0;
3976
f2858738
VV		 3977 be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
3978 &desc.nic_vft);
bec84e6b
VV		 3979
3980 return be_cmd_set_profile_config(adapter, &desc,
3981 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 3982}
3983
3984int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3985{
3986 struct be_mcc_wrb *wrb;
3987 struct be_cmd_req_manage_iface_filters *req;
3988 int status;
3989
3990 if (iface == 0xFFFFFFFF)
3991 return -1;
3992
3993 spin_lock_bh(&adapter->mcc_lock);
3994
3995 wrb = wrb_from_mccq(adapter);
3996 if (!wrb) {
3997 status = -EBUSY;
3998 goto err;
3999 }
4000 req = embedded_payload(wrb);
4001
4002 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4003 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4004 wrb, NULL);
4005 req->op = op;
4006 req->target_iface_id = cpu_to_le32(iface);
4007
4008 status = be_mcc_notify_wait(adapter);
4009err:
4010 spin_unlock_bh(&adapter->mcc_lock);
4011 return status;
4012}
4013
4014int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4015{
4016 struct be_port_res_desc port_desc;
4017
4018 memset(&port_desc, 0, sizeof(port_desc));
4019 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4020 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4021 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4022 port_desc.link_num = adapter->hba_port_num;
4023 if (port) {
4024 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4025 (1 << RCVID_SHIFT);
4026 port_desc.nv_port = swab16(port);
4027 } else {
4028 port_desc.nv_flags = NV_TYPE_DISABLED;
4029 port_desc.nv_port = 0;
4030 }
4031
4032 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 4033 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 4034}
4035
4c876616
SP		 4036int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4037 int vf_num)
4038{
4039 struct be_mcc_wrb *wrb;
4040 struct be_cmd_req_get_iface_list *req;
4041 struct be_cmd_resp_get_iface_list *resp;
4042 int status;
4043
4044 spin_lock_bh(&adapter->mcc_lock);
4045
4046 wrb = wrb_from_mccq(adapter);
4047 if (!wrb) {
4048 status = -EBUSY;
4049 goto err;
4050 }
4051 req = embedded_payload(wrb);
4052
4053 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4054 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4055 wrb, NULL);
4056 req->hdr.domain = vf_num + 1;
4057
4058 status = be_mcc_notify_wait(adapter);
4059 if (!status) {
4060 resp = (struct be_cmd_resp_get_iface_list *)req;
4061 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4062 }
4063
4064err:
4065 spin_unlock_bh(&adapter->mcc_lock);
4066 return status;
4067}
4068
5c510811
SK		 4069static int lancer_wait_idle(struct be_adapter *adapter)
4070{
4071#define SLIPORT_IDLE_TIMEOUT 30
4072 u32 reg_val;
4073 int status = 0, i;
4074
4075 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4076 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4077 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4078 break;
4079
4080 ssleep(1);
4081 }
4082
4083 if (i == SLIPORT_IDLE_TIMEOUT)
4084 status = -1;
4085
4086 return status;
4087}
4088
4089int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4090{
4091 int status = 0;
4092
4093 status = lancer_wait_idle(adapter);
4094 if (status)
4095 return status;
4096
4097 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4098
4099 return status;
4100}
4101
4102/* Routine to check whether dump image is present or not */
4103bool dump_present(struct be_adapter *adapter)
4104{
4105 u32 sliport_status = 0;
4106
4107 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4108 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4109}
4110
4111int lancer_initiate_dump(struct be_adapter *adapter)
4112{
f0613380 4113 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 4114 int status;
4115
f0613380
KA		 4116 if (dump_present(adapter)) {
4117 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4118 return -EEXIST;
4119 }
4120
5c510811
SK		 4121 /* give firmware reset and diagnostic dump */
4122 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4123 PHYSDEV_CONTROL_DD_MASK);
4124 if (status < 0) {
f0613380 4125 dev_err(dev, "FW reset failed\n");
5c510811
SK		 4126 return status;
4127 }
4128
4129 status = lancer_wait_idle(adapter);
4130 if (status)
4131 return status;
4132
4133 if (!dump_present(adapter)) {
f0613380
KA		 4134 dev_err(dev, "FW dump not generated\n");
4135 return -EIO;
5c510811
SK		 4136 }
4137
4138 return 0;
4139}
4140
f0613380
KA		 4141int lancer_delete_dump(struct be_adapter *adapter)
4142{
4143 int status;
4144
4145 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4146 return be_cmd_status(status);
4147}
4148
dcf7ebba
PR		 4149/* Uses sync mcc */
4150int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4151{
4152 struct be_mcc_wrb *wrb;
4153 struct be_cmd_enable_disable_vf *req;
4154 int status;
4155
0599863d 4156 if (BEx_chip(adapter))
dcf7ebba
PR		 4157 return 0;
4158
4159 spin_lock_bh(&adapter->mcc_lock);
4160
4161 wrb = wrb_from_mccq(adapter);
4162 if (!wrb) {
4163 status = -EBUSY;
4164 goto err;
4165 }
4166
4167 req = embedded_payload(wrb);
4168
4169 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4170 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4171 wrb, NULL);
4172
4173 req->hdr.domain = domain;
4174 req->enable = 1;
4175 status = be_mcc_notify_wait(adapter);
4176err:
4177 spin_unlock_bh(&adapter->mcc_lock);
4178 return status;
4179}
4180
68c45a2d
SK		 4181int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4182{
4183 struct be_mcc_wrb *wrb;
4184 struct be_cmd_req_intr_set *req;
4185 int status;
4186
4187 if (mutex_lock_interruptible(&adapter->mbox_lock))
4188 return -1;
4189
4190 wrb = wrb_from_mbox(adapter);
4191
4192 req = embedded_payload(wrb);
4193
4194 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4195 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4196 wrb, NULL);
4197
4198 req->intr_enabled = intr_enable;
4199
4200 status = be_mbox_notify_wait(adapter);
4201
4202 mutex_unlock(&adapter->mbox_lock);
4203 return status;
4204}
4205
542963b7
VV		 4206/* Uses MBOX */
4207int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4208{
4209 struct be_cmd_req_get_active_profile *req;
4210 struct be_mcc_wrb *wrb;
4211 int status;
4212
4213 if (mutex_lock_interruptible(&adapter->mbox_lock))
4214 return -1;
4215
4216 wrb = wrb_from_mbox(adapter);
4217 if (!wrb) {
4218 status = -EBUSY;
4219 goto err;
4220 }
4221
4222 req = embedded_payload(wrb);
4223
4224 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4225 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4226 wrb, NULL);
4227
4228 status = be_mbox_notify_wait(adapter);
4229 if (!status) {
4230 struct be_cmd_resp_get_active_profile *resp =
4231 embedded_payload(wrb);
03d28ffe 4232
542963b7
VV		 4233 *profile_id = le16_to_cpu(resp->active_profile_id);
4234 }
4235
4236err:
4237 mutex_unlock(&adapter->mbox_lock);
4238 return status;
4239}
4240
bdce2ad7
SR		 4241int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4242 int link_state, u8 domain)
4243{
4244 struct be_mcc_wrb *wrb;
4245 struct be_cmd_req_set_ll_link *req;
4246 int status;
4247
4248 if (BEx_chip(adapter) || lancer_chip(adapter))
18fd6025 4249 return -EOPNOTSUPP;
bdce2ad7
SR		 4250
4251 spin_lock_bh(&adapter->mcc_lock);
4252
4253 wrb = wrb_from_mccq(adapter);
4254 if (!wrb) {
4255 status = -EBUSY;
4256 goto err;
4257 }
4258
4259 req = embedded_payload(wrb);
4260
4261 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4262 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4263 sizeof(*req), wrb, NULL);
4264
4265 req->hdr.version = 1;
4266 req->hdr.domain = domain;
4267
4268 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4269 req->link_config |= 1;
4270
4271 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4272 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4273
4274 status = be_mcc_notify_wait(adapter);
4275err:
4276 spin_unlock_bh(&adapter->mcc_lock);
4277 return status;
4278}
4279
6a4ab669 4280int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 4281 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 4282{
4283 struct be_adapter *adapter = netdev_priv(netdev_handle);
4284 struct be_mcc_wrb *wrb;
504fbf1e 4285 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 4286 struct be_cmd_req_hdr *req;
4287 struct be_cmd_resp_hdr *resp;
4288 int status;
4289
4290 spin_lock_bh(&adapter->mcc_lock);
4291
4292 wrb = wrb_from_mccq(adapter);
4293 if (!wrb) {
4294 status = -EBUSY;
4295 goto err;
4296 }
4297 req = embedded_payload(wrb);
4298 resp = embedded_payload(wrb);
4299
4300 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4301 hdr->opcode, wrb_payload_size, wrb, NULL);
4302 memcpy(req, wrb_payload, wrb_payload_size);
4303 be_dws_cpu_to_le(req, wrb_payload_size);
4304
4305 status = be_mcc_notify_wait(adapter);
4306 if (cmd_status)
4307 *cmd_status = (status & 0xffff);
4308 if (ext_status)
4309 *ext_status = 0;
4310 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4311 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4312err:
4313 spin_unlock_bh(&adapter->mcc_lock);
4314 return status;
4315}
4316EXPORT_SYMBOL(be_roce_mcc_cmd);
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