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Merge remote-tracking branches 'asoc/topic/adsp', 'asoc/topic/ak4613', 'asoc/topic...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
7dfbe7d7 2 * Copyright (C) 2005 - 2016 Broadcom
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
51d1f98a
AK		 22char *be_misconfig_evt_port_state[] = {
23 "Physical Link is functional",
24 "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
25 "Optics of two types installed – Remove one optic or install matching pair of optics.",
26 "Incompatible optics – Replace with compatible optics for card to function.",
27 "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
28 "Uncertified optics – Replace with Avago-certified optics to enable link operation."
21252377
VV		 29};
30
51d1f98a
AK		 31static char *be_port_misconfig_evt_severity[] = {
32 "KERN_WARN",
33 "KERN_INFO",
34 "KERN_ERR",
35 "KERN_WARN"
36};
37
38static char *phy_state_oper_desc[] = {
39 "Link is non-operational",
40 "Link is operational",
21252377
VV		 41 ""
42};
43
f25b119c
PR		 44static struct be_cmd_priv_map cmd_priv_map[] = {
45 {
46 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
47 CMD_SUBSYSTEM_ETH,
48 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_GET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_COMMON_SET_FLOW_CONTROL,
59 CMD_SUBSYSTEM_COMMON,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_ETH_GET_PPORT_STATS,
65 CMD_SUBSYSTEM_ETH,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 },
69 {
70 OPCODE_COMMON_GET_PHY_DETAILS,
71 CMD_SUBSYSTEM_COMMON,
72 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
73 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
2e365b1b
SK		 74 },
75 {
76 OPCODE_LOWLEVEL_HOST_DDR_DMA,
77 CMD_SUBSYSTEM_LOWLEVEL,
78 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
79 },
80 {
81 OPCODE_LOWLEVEL_LOOPBACK_TEST,
82 CMD_SUBSYSTEM_LOWLEVEL,
83 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
84 },
85 {
86 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
87 CMD_SUBSYSTEM_LOWLEVEL,
88 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
89 },
884476be
SK		 90 {
91 OPCODE_COMMON_SET_HSW_CONFIG,
92 CMD_SUBSYSTEM_COMMON,
d14584d9
VD		 93 BE_PRIV_DEVCFG | BE_PRIV_VHADM |
94 BE_PRIV_DEVSEC
884476be 95 },
62259ac4
SK		 96 {
97 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
98 CMD_SUBSYSTEM_COMMON,
99 BE_PRIV_DEVCFG
100 }
f25b119c
PR		 101};
102
a2cc4e0b 103static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 104{
105 int i;
106 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
107 u32 cmd_privileges = adapter->cmd_privileges;
108
109 for (i = 0; i < num_entries; i++)
110 if (opcode == cmd_priv_map[i].opcode &&
111 subsystem == cmd_priv_map[i].subsystem)
112 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
113 return false;
114
115 return true;
116}
117
3de09455
SK		 118static inline void *embedded_payload(struct be_mcc_wrb *wrb)
119{
120 return wrb->payload.embedded_payload;
121}
609ff3bb 122
efaa408e 123static int be_mcc_notify(struct be_adapter *adapter)
5fb379ee 124{
8788fdc2 125 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 126 u32 val = 0;
127
954f6825 128 if (be_check_error(adapter, BE_ERROR_ANY))
efaa408e 129 return -EIO;
7acc2087 130
5fb379ee
SP		 131 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
132 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 133
134 wmb();
8788fdc2 135 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
efaa408e
SR		 136
137 return 0;
5fb379ee
SP		 138}
139
140/* To check if valid bit is set, check the entire word as we don't know
141 * the endianness of the data (old entry is host endian while a new entry is
142 * little endian) */
efd2e40a 143static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 144{
9e9ff4b7
SP		 145 u32 flags;
146
5fb379ee 147 if (compl->flags != 0) {
9e9ff4b7
SP		 148 flags = le32_to_cpu(compl->flags);
149 if (flags & CQE_FLAGS_VALID_MASK) {
150 compl->flags = flags;
151 return true;
152 }
5fb379ee 153 }
9e9ff4b7 154 return false;
5fb379ee
SP		 155}
156
157/* Need to reset the entire word that houses the valid bit */
efd2e40a 158static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 159{
160 compl->flags = 0;
161}
162
652bf646
PR		 163static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
164{
165 unsigned long addr;
166
167 addr = tag1;
168 addr = ((addr << 16) << 16) | tag0;
169 return (void *)addr;
170}
171
4c60005f
KA		 172static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
173{
174 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
175 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
176 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
77be8c1c 177 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
4c60005f
KA		 178 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
179 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
180 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
181 return true;
182 else
183 return false;
184}
185
559b633f
SP		 186/* Place holder for all the async MCC cmds wherein the caller is not in a busy
187 * loop (has not issued be_mcc_notify_wait())
188 */
189static void be_async_cmd_process(struct be_adapter *adapter,
190 struct be_mcc_compl *compl,
191 struct be_cmd_resp_hdr *resp_hdr)
192{
193 enum mcc_base_status base_status = base_status(compl->status);
194 u8 opcode = 0, subsystem = 0;
195
196 if (resp_hdr) {
197 opcode = resp_hdr->opcode;
198 subsystem = resp_hdr->subsystem;
199 }
200
201 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
202 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
203 complete(&adapter->et_cmd_compl);
204 return;
205 }
206
9c855975
SR		 207 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
208 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
209 complete(&adapter->et_cmd_compl);
210 return;
211 }
212
559b633f
SP		 213 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
214 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
215 subsystem == CMD_SUBSYSTEM_COMMON) {
216 adapter->flash_status = compl->status;
217 complete(&adapter->et_cmd_compl);
218 return;
219 }
220
221 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
222 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
223 subsystem == CMD_SUBSYSTEM_ETH &&
224 base_status == MCC_STATUS_SUCCESS) {
225 be_parse_stats(adapter);
226 adapter->stats_cmd_sent = false;
227 return;
228 }
229
230 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
231 subsystem == CMD_SUBSYSTEM_COMMON) {
232 if (base_status == MCC_STATUS_SUCCESS) {
233 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
234 (void *)resp_hdr;
29e9122b 235 adapter->hwmon_info.be_on_die_temp =
559b633f
SP		 236 resp->on_die_temperature;
237 } else {
238 adapter->be_get_temp_freq = 0;
29e9122b
VD		 239 adapter->hwmon_info.be_on_die_temp =
240 BE_INVALID_DIE_TEMP;
559b633f
SP		 241 }
242 return;
243 }
244}
245
8788fdc2 246static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 247 struct be_mcc_compl *compl)
5fb379ee 248{
4c60005f
KA		 249 enum mcc_base_status base_status;
250 enum mcc_addl_status addl_status;
652bf646
PR		 251 struct be_cmd_resp_hdr *resp_hdr;
252 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 253
254 /* Just swap the status to host endian; mcc tag is opaquely copied
255 * from mcc_wrb */
256 be_dws_le_to_cpu(compl, 4);
257
4c60005f
KA		 258 base_status = base_status(compl->status);
259 addl_status = addl_status(compl->status);
96c9b2e4 260
652bf646 261 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 262 if (resp_hdr) {
263 opcode = resp_hdr->opcode;
264 subsystem = resp_hdr->subsystem;
265 }
266
559b633f 267 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 268
559b633f
SP		 269 if (base_status != MCC_STATUS_SUCCESS &&
270 !be_skip_err_log(opcode, base_status, addl_status)) {
fa5c867d
SR		 271 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
272 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
97f1d8cd 273 dev_warn(&adapter->pdev->dev,
522609f2 274 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 275 opcode, subsystem);
2b3f291b 276 } else {
97f1d8cd
VV		 277 dev_err(&adapter->pdev->dev,
278 "opcode %d-%d failed:status %d-%d\n",
4c60005f 279 opcode, subsystem, base_status, addl_status);
2b3f291b 280 }
5fb379ee 281 }
4c60005f 282 return compl->status;
5fb379ee
SP		 283}
284
a8f447bd 285/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 286static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 287 struct be_mcc_compl *compl)
a8f447bd 288{
3acf19d9
SP		 289 struct be_async_event_link_state *evt =
290 (struct be_async_event_link_state *)compl;
291
b236916a 292 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 293 adapter->phy.link_speed = -1;
b236916a 294
bdce2ad7
SR		 295 /* On BEx the FW does not send a separate link status
296 * notification for physical and logical link.
297 * On other chips just process the logical link
298 * status notification
299 */
300 if (!BEx_chip(adapter) &&
2e177a5c
PR		 301 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
302 return;
303
b236916a
AK		 304 /* For the initial link status do not rely on the ASYNC event as
305 * it may not be received in some cases.
306 */
307 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 308 be_link_status_update(adapter,
309 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 310}
311
21252377
VV		 312static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
313 struct be_mcc_compl *compl)
314{
315 struct be_async_event_misconfig_port *evt =
316 (struct be_async_event_misconfig_port *)compl;
51d1f98a
AK		 317 u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
318 u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
319 u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
21252377 320 struct device *dev = &adapter->pdev->dev;
51d1f98a
AK		 321 u8 msg_severity = DEFAULT_MSG_SEVERITY;
322 u8 phy_state_info;
323 u8 new_phy_state;
324
325 new_phy_state =
326 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
327
328 if (new_phy_state == adapter->phy_state)
329 return;
330
331 adapter->phy_state = new_phy_state;
21252377 332
51d1f98a
AK		 333 /* for older fw that doesn't populate link effect data */
334 if (!sfp_misconfig_evt_word2)
335 goto log_message;
21252377 336
51d1f98a
AK		 337 phy_state_info =
338 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
339
340 if (phy_state_info & PHY_STATE_INFO_VALID) {
341 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
342
343 if (be_phy_unqualified(new_phy_state))
344 phy_oper_state = (phy_state_info & PHY_STATE_OPER);
345 }
346
347log_message:
21252377
VV		 348 /* Log an error message that would allow a user to determine
349 * whether the SFPs have an issue
350 */
51d1f98a
AK		 351 if (be_phy_state_unknown(new_phy_state))
352 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
353 "Port %c: Unrecognized Optics state: 0x%x. %s",
354 adapter->port_name,
355 new_phy_state,
356 phy_state_oper_desc[phy_oper_state]);
357 else
358 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
359 "Port %c: %s %s",
360 adapter->port_name,
361 be_misconfig_evt_port_state[new_phy_state],
362 phy_state_oper_desc[phy_oper_state]);
363
364 /* Log Vendor name and part no. if a misconfigured SFP is detected */
365 if (be_phy_misconfigured(new_phy_state))
366 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
21252377
VV		 367}
368
cc4ce020
SK		 369/* Grp5 CoS Priority evt */
370static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 371 struct be_mcc_compl *compl)
cc4ce020 372{
3acf19d9
SP		 373 struct be_async_event_grp5_cos_priority *evt =
374 (struct be_async_event_grp5_cos_priority *)compl;
375
cc4ce020
SK		 376 if (evt->valid) {
377 adapter->vlan_prio_bmap = evt->available_priority_bmap;
fdf81bfb 378 adapter->recommended_prio_bits =
cc4ce020
SK		 379 evt->reco_default_priority << VLAN_PRIO_SHIFT;
380 }
381}
382
323ff71e 383/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 384static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 385 struct be_mcc_compl *compl)
cc4ce020 386{
3acf19d9
SP		 387 struct be_async_event_grp5_qos_link_speed *evt =
388 (struct be_async_event_grp5_qos_link_speed *)compl;
389
323ff71e
SP		 390 if (adapter->phy.link_speed >= 0 &&
391 evt->physical_port == adapter->port_num)
392 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 393}
394
3968fa1e
AK		 395/*Grp5 PVID evt*/
396static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 397 struct be_mcc_compl *compl)
3968fa1e 398{
3acf19d9
SP		 399 struct be_async_event_grp5_pvid_state *evt =
400 (struct be_async_event_grp5_pvid_state *)compl;
401
bdac85b5 402 if (evt->enabled) {
939cf306 403 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 404 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
405 } else {
3968fa1e 406 adapter->pvid = 0;
bdac85b5 407 }
3968fa1e
AK		 408}
409
760c295e
VD		 410#define MGMT_ENABLE_MASK 0x4
411static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
412 struct be_mcc_compl *compl)
413{
414 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
415 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
416
417 if (evt_dw1 & MGMT_ENABLE_MASK) {
418 adapter->flags |= BE_FLAGS_OS2BMC;
419 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
420 } else {
421 adapter->flags &= ~BE_FLAGS_OS2BMC;
422 }
423}
424
cc4ce020 425static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 426 struct be_mcc_compl *compl)
cc4ce020 427{
3acf19d9
SP		 428 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
429 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 430
431 switch (event_type) {
432 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 433 be_async_grp5_cos_priority_process(adapter, compl);
434 break;
cc4ce020 435 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 436 be_async_grp5_qos_speed_process(adapter, compl);
437 break;
3968fa1e 438 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 439 be_async_grp5_pvid_state_process(adapter, compl);
440 break;
760c295e
VD		 441 /* Async event to disable/enable os2bmc and/or mac-learning */
442 case ASYNC_EVENT_FW_CONTROL:
443 be_async_grp5_fw_control_process(adapter, compl);
444 break;
cc4ce020 445 default:
cc4ce020
SK		 446 break;
447 }
448}
449
bc0c3405 450static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 451 struct be_mcc_compl *cmp)
bc0c3405
AK		 452{
453 u8 event_type = 0;
504fbf1e 454 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 455
3acf19d9
SP		 456 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
457 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 458
459 switch (event_type) {
460 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
461 if (evt->valid)
462 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
463 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
464 break;
465 default:
05ccaa2b
VV		 466 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
467 event_type);
bc0c3405
AK		 468 break;
469 }
470}
471
21252377
VV		 472static void be_async_sliport_evt_process(struct be_adapter *adapter,
473 struct be_mcc_compl *cmp)
474{
475 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
476 ASYNC_EVENT_TYPE_MASK;
477
478 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
479 be_async_port_misconfig_event_process(adapter, cmp);
480}
481
3acf19d9 482static inline bool is_link_state_evt(u32 flags)
a8f447bd 483{
3acf19d9
SP		 484 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
485 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 486}
5fb379ee 487
3acf19d9 488static inline bool is_grp5_evt(u32 flags)
cc4ce020 489{
3acf19d9
SP		 490 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
491 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 492}
493
3acf19d9 494static inline bool is_dbg_evt(u32 flags)
bc0c3405 495{
3acf19d9
SP		 496 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
497 ASYNC_EVENT_CODE_QNQ;
498}
499
21252377
VV		 500static inline bool is_sliport_evt(u32 flags)
501{
502 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
503 ASYNC_EVENT_CODE_SLIPORT;
504}
505
3acf19d9
SP		 506static void be_mcc_event_process(struct be_adapter *adapter,
507 struct be_mcc_compl *compl)
508{
509 if (is_link_state_evt(compl->flags))
510 be_async_link_state_process(adapter, compl);
511 else if (is_grp5_evt(compl->flags))
512 be_async_grp5_evt_process(adapter, compl);
513 else if (is_dbg_evt(compl->flags))
514 be_async_dbg_evt_process(adapter, compl);
21252377
VV		 515 else if (is_sliport_evt(compl->flags))
516 be_async_sliport_evt_process(adapter, compl);
bc0c3405
AK		 517}
518
efd2e40a 519static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 520{
8788fdc2 521 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 522 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 523
524 if (be_mcc_compl_is_new(compl)) {
525 queue_tail_inc(mcc_cq);
526 return compl;
527 }
528 return NULL;
529}
530
7a1e9b20
SP		 531void be_async_mcc_enable(struct be_adapter *adapter)
532{
533 spin_lock_bh(&adapter->mcc_cq_lock);
534
535 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
536 adapter->mcc_obj.rearm_cq = true;
537
538 spin_unlock_bh(&adapter->mcc_cq_lock);
539}
540
541void be_async_mcc_disable(struct be_adapter *adapter)
542{
a323d9bf
SP		 543 spin_lock_bh(&adapter->mcc_cq_lock);
544
7a1e9b20 545 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 546 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
547
548 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 549}
550
10ef9ab4 551int be_process_mcc(struct be_adapter *adapter)
5fb379ee 552{
efd2e40a 553 struct be_mcc_compl *compl;
10ef9ab4 554 int num = 0, status = 0;
7a1e9b20 555 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 556
072a9c48 557 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 558
8788fdc2 559 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 560 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 561 be_mcc_event_process(adapter, compl);
b31c50a7 562 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 563 status = be_mcc_compl_process(adapter, compl);
564 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 565 }
566 be_mcc_compl_use(compl);
567 num++;
568 }
b31c50a7 569
10ef9ab4
SP		 570 if (num)
571 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
572
072a9c48 573 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 574 return status;
5fb379ee
SP		 575}
576
6ac7b687 577/* Wait till no more pending mcc requests are present */
b31c50a7 578static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 579{
b7172414 580#define mcc_timeout 12000 /* 12s timeout */
10ef9ab4 581 int i, status = 0;
f31e50a8
SP		 582 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
583
6ac7b687 584 for (i = 0; i < mcc_timeout; i++) {
954f6825 585 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 586 return -EIO;
587
072a9c48 588 local_bh_disable();
10ef9ab4 589 status = be_process_mcc(adapter);
072a9c48 590 local_bh_enable();
b31c50a7 591
f31e50a8 592 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687 593 break;
b7172414 594 usleep_range(500, 1000);
6ac7b687 595 }
b31c50a7 596 if (i == mcc_timeout) {
6589ade0 597 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 598 be_set_error(adapter, BE_ERROR_FW);
652bf646 599 return -EIO;
b31c50a7 600 }
f31e50a8 601 return status;
6ac7b687
SP		 602}
603
604/* Notify MCC requests and wait for completion */
b31c50a7 605static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 606{
652bf646
PR		 607 int status;
608 struct be_mcc_wrb *wrb;
609 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
b0fd2eb2 610 u32 index = mcc_obj->q.head;
652bf646
PR		 611 struct be_cmd_resp_hdr *resp;
612
613 index_dec(&index, mcc_obj->q.len);
614 wrb = queue_index_node(&mcc_obj->q, index);
615
616 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
617
efaa408e
SR		 618 status = be_mcc_notify(adapter);
619 if (status)
620 goto out;
652bf646
PR		 621
622 status = be_mcc_wait_compl(adapter);
623 if (status == -EIO)
624 goto out;
625
4c60005f
KA		 626 status = (resp->base_status |
627 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
628 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 629out:
630 return status;
6ac7b687
SP		 631}
632
5f0b849e 633static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 634{
f25b03a7 635 int msecs = 0;
6b7c5b94
SP		 636 u32 ready;
637
638 do {
954f6825 639 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 640 return -EIO;
641
cf588477 642 ready = ioread32(db);
434b3648 643 if (ready == 0xffffffff)
cf588477 644 return -1;
cf588477
SP		 645
646 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 647 if (ready)
648 break;
649
f25b03a7 650 if (msecs > 4000) {
6589ade0 651 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 652 be_set_error(adapter, BE_ERROR_FW);
f67ef7ba 653 be_detect_error(adapter);
6b7c5b94
SP		 654 return -1;
655 }
656
1dbf53a2 657 msleep(1);
f25b03a7 658 msecs++;
6b7c5b94
SP		 659 } while (true);
660
661 return 0;
662}
663
664/*
665 * Insert the mailbox address into the doorbell in two steps
5fb379ee 666 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 667 */
b31c50a7 668static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 669{
670 int status;
6b7c5b94 671 u32 val = 0;
8788fdc2
SP		 672 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
673 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 674 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 675 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 676
cf588477
SP		 677 /* wait for ready to be set */
678 status = be_mbox_db_ready_wait(adapter, db);
679 if (status != 0)
680 return status;
681
6b7c5b94
SP		 682 val |= MPU_MAILBOX_DB_HI_MASK;
683 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
684 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
685 iowrite32(val, db);
686
687 /* wait for ready to be set */
5f0b849e 688 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 689 if (status != 0)
690 return status;
691
692 val = 0;
6b7c5b94
SP		 693 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
694 val |= (u32)(mbox_mem->dma >> 4) << 2;
695 iowrite32(val, db);
696
5f0b849e 697 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 698 if (status != 0)
699 return status;
700
5fb379ee 701 /* A cq entry has been made now */
efd2e40a
SP		 702 if (be_mcc_compl_is_new(compl)) {
703 status = be_mcc_compl_process(adapter, &mbox->compl);
704 be_mcc_compl_use(compl);
5fb379ee
SP		 705 if (status)
706 return status;
707 } else {
5f0b849e 708 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 709 return -1;
710 }
5fb379ee 711 return 0;
6b7c5b94
SP		 712}
713
710f3e59 714u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 715{
fe6d2a38
SP		 716 u32 sem;
717
c5b3ad4c
SP		 718 if (BEx_chip(adapter))
719 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 720 else
c5b3ad4c
SP		 721 pci_read_config_dword(adapter->pdev,
722 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
723
724 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 725}
726
87f20c26 727static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 728{
729#define SLIPORT_READY_TIMEOUT 30
730 u32 sliport_status;
e673244a 731 int i;
bf99e50d
PR		 732
733 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
734 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
735 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
9fa465c0 736 return 0;
67297ad8 737
9fa465c0
SP		 738 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
739 !(sliport_status & SLIPORT_STATUS_RN_MASK))
740 return -EIO;
67297ad8 741
9fa465c0 742 msleep(1000);
bf99e50d 743 }
67297ad8 744
9fa465c0 745 return sliport_status ? : -1;
bf99e50d
PR		 746}
747
748int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 749{
43a04fdc
SP		 750 u16 stage;
751 int status, timeout = 0;
6ed35eea 752 struct device *dev = &adapter->pdev->dev;
6b7c5b94 753
bf99e50d
PR		 754 if (lancer_chip(adapter)) {
755 status = lancer_wait_ready(adapter);
e673244a
KA		 756 if (status) {
757 stage = status;
758 goto err;
759 }
760 return 0;
bf99e50d
PR		 761 }
762
43a04fdc 763 do {
ca3de6b2
SP		 764 /* There's no means to poll POST state on BE2/3 VFs */
765 if (BEx_chip(adapter) && be_virtfn(adapter))
766 return 0;
767
c5b3ad4c 768 stage = be_POST_stage_get(adapter);
66d29cbc 769 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 770 return 0;
66d29cbc 771
a2cc4e0b 772 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 773 if (msleep_interruptible(2000)) {
774 dev_err(dev, "Waiting for POST aborted\n");
775 return -EINTR;
43a04fdc 776 }
66d29cbc 777 timeout += 2;
3ab81b5f 778 } while (timeout < 60);
6b7c5b94 779
e673244a
KA		 780err:
781 dev_err(dev, "POST timeout; stage=%#x\n", stage);
9fa465c0 782 return -ETIMEDOUT;
6b7c5b94
SP		 783}
784
6b7c5b94
SP		 785static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
786{
787 return &wrb->payload.sgl[0];
788}
789
a2cc4e0b 790static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 791{
792 wrb->tag0 = addr & 0xFFFFFFFF;
793 wrb->tag1 = upper_32_bits(addr);
794}
6b7c5b94
SP		 795
796/* Don't touch the hdr after it's prepared */
106df1e3
SK		 797/* mem will be NULL for embedded commands */
798static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 799 u8 subsystem, u8 opcode, int cmd_len,
800 struct be_mcc_wrb *wrb,
801 struct be_dma_mem *mem)
6b7c5b94 802{
106df1e3
SK		 803 struct be_sge *sge;
804
6b7c5b94
SP		 805 req_hdr->opcode = opcode;
806 req_hdr->subsystem = subsystem;
807 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 808 req_hdr->version = 0;
bea50988 809 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 810 wrb->payload_length = cmd_len;
811 if (mem) {
812 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
813 MCC_WRB_SGE_CNT_SHIFT;
814 sge = nonembedded_sgl(wrb);
815 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
816 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
817 sge->len = cpu_to_le32(mem->size);
818 } else
819 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
820 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 821}
822
823static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 824 struct be_dma_mem *mem)
6b7c5b94
SP		 825{
826 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
827 u64 dma = (u64)mem->dma;
828
829 for (i = 0; i < buf_pages; i++) {
830 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
831 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
832 dma += PAGE_SIZE_4K;
833 }
834}
835
b31c50a7 836static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 837{
b31c50a7
SP		 838 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
839 struct be_mcc_wrb *wrb
840 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
841 memset(wrb, 0, sizeof(*wrb));
842 return wrb;
6b7c5b94
SP		 843}
844
b31c50a7 845static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 846{
b31c50a7
SP		 847 struct be_queue_info *mccq = &adapter->mcc_obj.q;
848 struct be_mcc_wrb *wrb;
849
aa790db9
PR		 850 if (!mccq->created)
851 return NULL;
852
4d277125 853 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 854 return NULL;
713d0394 855
b31c50a7
SP		 856 wrb = queue_head_node(mccq);
857 queue_head_inc(mccq);
858 atomic_inc(&mccq->used);
859 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 860 return wrb;
861}
862
bea50988
SP		 863static bool use_mcc(struct be_adapter *adapter)
864{
865 return adapter->mcc_obj.q.created;
866}
867
868/* Must be used only in process context */
869static int be_cmd_lock(struct be_adapter *adapter)
870{
871 if (use_mcc(adapter)) {
b7172414 872 mutex_lock(&adapter->mcc_lock);
bea50988
SP		 873 return 0;
874 } else {
875 return mutex_lock_interruptible(&adapter->mbox_lock);
876 }
877}
878
879/* Must be used only in process context */
880static void be_cmd_unlock(struct be_adapter *adapter)
881{
882 if (use_mcc(adapter))
b7172414 883 return mutex_unlock(&adapter->mcc_lock);
bea50988
SP		 884 else
885 return mutex_unlock(&adapter->mbox_lock);
886}
887
888static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
889 struct be_mcc_wrb *wrb)
890{
891 struct be_mcc_wrb *dest_wrb;
892
893 if (use_mcc(adapter)) {
894 dest_wrb = wrb_from_mccq(adapter);
895 if (!dest_wrb)
896 return NULL;
897 } else {
898 dest_wrb = wrb_from_mbox(adapter);
899 }
900
901 memcpy(dest_wrb, wrb, sizeof(*wrb));
902 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
903 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
904
905 return dest_wrb;
906}
907
908/* Must be used only in process context */
909static int be_cmd_notify_wait(struct be_adapter *adapter,
910 struct be_mcc_wrb *wrb)
911{
912 struct be_mcc_wrb *dest_wrb;
913 int status;
914
915 status = be_cmd_lock(adapter);
916 if (status)
917 return status;
918
919 dest_wrb = be_cmd_copy(adapter, wrb);
0c884567
SR		 920 if (!dest_wrb) {
921 status = -EBUSY;
922 goto unlock;
923 }
bea50988
SP		 924
925 if (use_mcc(adapter))
926 status = be_mcc_notify_wait(adapter);
927 else
928 status = be_mbox_notify_wait(adapter);
929
930 if (!status)
931 memcpy(wrb, dest_wrb, sizeof(*wrb));
932
0c884567 933unlock:
bea50988
SP		 934 be_cmd_unlock(adapter);
935 return status;
936}
937
2243e2e9
SP		 938/* Tell fw we're about to start firing cmds by writing a
939 * special pattern across the wrb hdr; uses mbox
940 */
941int be_cmd_fw_init(struct be_adapter *adapter)
942{
943 u8 *wrb;
944 int status;
945
bf99e50d
PR		 946 if (lancer_chip(adapter))
947 return 0;
948
2984961c
IV		 949 if (mutex_lock_interruptible(&adapter->mbox_lock))
950 return -1;
2243e2e9
SP		 951
952 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 953 *wrb++ = 0xFF;
954 *wrb++ = 0x12;
955 *wrb++ = 0x34;
956 *wrb++ = 0xFF;
957 *wrb++ = 0xFF;
958 *wrb++ = 0x56;
959 *wrb++ = 0x78;
960 *wrb = 0xFF;
2243e2e9
SP		 961
962 status = be_mbox_notify_wait(adapter);
963
2984961c 964 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 965 return status;
966}
967
968/* Tell fw we're done with firing cmds by writing a
969 * special pattern across the wrb hdr; uses mbox
970 */
971int be_cmd_fw_clean(struct be_adapter *adapter)
972{
973 u8 *wrb;
974 int status;
975
bf99e50d
PR		 976 if (lancer_chip(adapter))
977 return 0;
978
2984961c
IV		 979 if (mutex_lock_interruptible(&adapter->mbox_lock))
980 return -1;
2243e2e9
SP		 981
982 wrb = (u8 *)wrb_from_mbox(adapter);
983 *wrb++ = 0xFF;
984 *wrb++ = 0xAA;
985 *wrb++ = 0xBB;
986 *wrb++ = 0xFF;
987 *wrb++ = 0xFF;
988 *wrb++ = 0xCC;
989 *wrb++ = 0xDD;
990 *wrb = 0xFF;
991
992 status = be_mbox_notify_wait(adapter);
993
2984961c 994 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 995 return status;
996}
bf99e50d 997
f2f781a7 998int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 999{
b31c50a7
SP		 1000 struct be_mcc_wrb *wrb;
1001 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 1002 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
1003 int status, ver = 0;
6b7c5b94 1004
2984961c
IV		 1005 if (mutex_lock_interruptible(&adapter->mbox_lock))
1006 return -1;
b31c50a7
SP		 1007
1008 wrb = wrb_from_mbox(adapter);
1009 req = embedded_payload(wrb);
6b7c5b94 1010
106df1e3 1011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1012 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1013 NULL);
6b7c5b94 1014
f2f781a7
SP		 1015 /* Support for EQ_CREATEv2 available only SH-R onwards */
1016 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1017 ver = 2;
1018
1019 req->hdr.version = ver;
6b7c5b94
SP		 1020 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1021
6b7c5b94
SP		 1022 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1023 /* 4byte eqe*/
1024 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1025 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 1026 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 1027 be_dws_cpu_to_le(req->context, sizeof(req->context));
1028
1029 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1030
b31c50a7 1031 status = be_mbox_notify_wait(adapter);
6b7c5b94 1032 if (!status) {
b31c50a7 1033 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 1034
f2f781a7
SP		 1035 eqo->q.id = le16_to_cpu(resp->eq_id);
1036 eqo->msix_idx =
1037 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1038 eqo->q.created = true;
6b7c5b94 1039 }
b31c50a7 1040
2984961c 1041 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1042 return status;
1043}
1044
f9449ab7 1045/* Use MCC */
8788fdc2 1046int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 1047 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 1048{
b31c50a7
SP		 1049 struct be_mcc_wrb *wrb;
1050 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 1051 int status;
1052
b7172414 1053 mutex_lock(&adapter->mcc_lock);
b31c50a7 1054
f9449ab7
SP		 1055 wrb = wrb_from_mccq(adapter);
1056 if (!wrb) {
1057 status = -EBUSY;
1058 goto err;
1059 }
b31c50a7 1060 req = embedded_payload(wrb);
6b7c5b94 1061
106df1e3 1062 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1063 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1064 NULL);
5ee4979b 1065 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 1066 if (permanent) {
1067 req->permanent = 1;
1068 } else {
504fbf1e 1069 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 1070 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 1071 req->permanent = 0;
1072 }
1073
f9449ab7 1074 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 1075 if (!status) {
1076 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 1077
6b7c5b94 1078 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 1079 }
6b7c5b94 1080
f9449ab7 1081err:
b7172414 1082 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1083 return status;
1084}
1085
b31c50a7 1086/* Uses synchronous MCCQ */
8788fdc2 1087int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 1088 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 1089{
b31c50a7
SP		 1090 struct be_mcc_wrb *wrb;
1091 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 1092 int status;
1093
b7172414 1094 mutex_lock(&adapter->mcc_lock);
b31c50a7
SP		 1095
1096 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1097 if (!wrb) {
1098 status = -EBUSY;
1099 goto err;
1100 }
b31c50a7 1101 req = embedded_payload(wrb);
6b7c5b94 1102
106df1e3 1103 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1104 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1105 NULL);
6b7c5b94 1106
f8617e08 1107 req->hdr.domain = domain;
6b7c5b94
SP		 1108 req->if_id = cpu_to_le32(if_id);
1109 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1110
b31c50a7 1111 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1112 if (!status) {
1113 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1114
6b7c5b94
SP		 1115 *pmac_id = le32_to_cpu(resp->pmac_id);
1116 }
1117
713d0394 1118err:
b7172414 1119 mutex_unlock(&adapter->mcc_lock);
e3a7ae2c 1120
fe68d8bf 1121 if (base_status(status) == MCC_STATUS_UNAUTHORIZED_REQUEST)
e3a7ae2c
SK		 1122 status = -EPERM;
1123
6b7c5b94
SP		 1124 return status;
1125}
1126
b31c50a7 1127/* Uses synchronous MCCQ */
30128031 1128int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1129{
b31c50a7
SP		 1130 struct be_mcc_wrb *wrb;
1131 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1132 int status;
1133
30128031
SP		 1134 if (pmac_id == -1)
1135 return 0;
1136
b7172414 1137 mutex_lock(&adapter->mcc_lock);
b31c50a7
SP		 1138
1139 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1140 if (!wrb) {
1141 status = -EBUSY;
1142 goto err;
1143 }
b31c50a7 1144 req = embedded_payload(wrb);
6b7c5b94 1145
106df1e3 1146 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
cd3307aa
KA		 1147 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1148 wrb, NULL);
6b7c5b94 1149
f8617e08 1150 req->hdr.domain = dom;
6b7c5b94
SP		 1151 req->if_id = cpu_to_le32(if_id);
1152 req->pmac_id = cpu_to_le32(pmac_id);
1153
b31c50a7
SP		 1154 status = be_mcc_notify_wait(adapter);
1155
713d0394 1156err:
b7172414 1157 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1158 return status;
1159}
1160
b31c50a7 1161/* Uses Mbox */
10ef9ab4 1162int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1163 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1164{
b31c50a7
SP		 1165 struct be_mcc_wrb *wrb;
1166 struct be_cmd_req_cq_create *req;
6b7c5b94 1167 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1168 void *ctxt;
6b7c5b94
SP		 1169 int status;
1170
2984961c
IV		 1171 if (mutex_lock_interruptible(&adapter->mbox_lock))
1172 return -1;
b31c50a7
SP		 1173
1174 wrb = wrb_from_mbox(adapter);
1175 req = embedded_payload(wrb);
1176 ctxt = &req->context;
6b7c5b94 1177
106df1e3 1178 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1179 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1180 NULL);
6b7c5b94
SP		 1181
1182 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1183
1184 if (BEx_chip(adapter)) {
fe6d2a38 1185 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1186 coalesce_wm);
fe6d2a38 1187 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1188 ctxt, no_delay);
fe6d2a38 1189 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1190 __ilog2_u32(cq->len / 256));
fe6d2a38 1191 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1192 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1193 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1194 } else {
1195 req->hdr.version = 2;
1196 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1197
1198 /* coalesce-wm field in this cmd is not relevant to Lancer.
1199 * Lancer uses COMMON_MODIFY_CQ to set this field
1200 */
1201 if (!lancer_chip(adapter))
1202 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1203 ctxt, coalesce_wm);
bbdc42f8 1204 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1205 no_delay);
bbdc42f8 1206 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1207 __ilog2_u32(cq->len / 256));
bbdc42f8 1208 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1209 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1210 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1211 }
6b7c5b94 1212
6b7c5b94
SP		 1213 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1214
1215 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1216
b31c50a7 1217 status = be_mbox_notify_wait(adapter);
6b7c5b94 1218 if (!status) {
b31c50a7 1219 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1220
6b7c5b94
SP		 1221 cq->id = le16_to_cpu(resp->cq_id);
1222 cq->created = true;
1223 }
b31c50a7 1224
2984961c 1225 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1226
1227 return status;
1228}
1229
1230static u32 be_encoded_q_len(int q_len)
1231{
1232 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1233
5fb379ee
SP		 1234 if (len_encoded == 16)
1235 len_encoded = 0;
1236 return len_encoded;
1237}
1238
4188e7df 1239static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1240 struct be_queue_info *mccq,
1241 struct be_queue_info *cq)
5fb379ee 1242{
b31c50a7 1243 struct be_mcc_wrb *wrb;
34b1ef04 1244 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1245 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1246 void *ctxt;
5fb379ee
SP		 1247 int status;
1248
2984961c
IV		 1249 if (mutex_lock_interruptible(&adapter->mbox_lock))
1250 return -1;
b31c50a7
SP		 1251
1252 wrb = wrb_from_mbox(adapter);
1253 req = embedded_payload(wrb);
1254 ctxt = &req->context;
5fb379ee 1255
106df1e3 1256 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1257 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1258 NULL);
5fb379ee 1259
d4a2ac3e 1260 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1261 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1262 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1263 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1264 be_encoded_q_len(mccq->len));
fe6d2a38 1265 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1266 } else {
1267 req->hdr.version = 1;
1268 req->cq_id = cpu_to_le16(cq->id);
1269
1270 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1271 be_encoded_q_len(mccq->len));
1272 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1273 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1274 ctxt, cq->id);
1275 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1276 ctxt, 1);
fe6d2a38 1277 }
5fb379ee 1278
21252377
VV		 1279 /* Subscribe to Link State, Sliport Event and Group 5 Events
1280 * (bits 1, 5 and 17 set)
1281 */
1282 req->async_event_bitmap[0] =
1283 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1284 BIT(ASYNC_EVENT_CODE_GRP_5) |
1285 BIT(ASYNC_EVENT_CODE_QNQ) |
1286 BIT(ASYNC_EVENT_CODE_SLIPORT));
1287
5fb379ee
SP		 1288 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1289
1290 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1291
b31c50a7 1292 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1293 if (!status) {
1294 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1295
5fb379ee
SP		 1296 mccq->id = le16_to_cpu(resp->id);
1297 mccq->created = true;
1298 }
2984961c 1299 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1300
1301 return status;
1302}
1303
4188e7df 1304static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1305 struct be_queue_info *mccq,
1306 struct be_queue_info *cq)
34b1ef04
SK		 1307{
1308 struct be_mcc_wrb *wrb;
1309 struct be_cmd_req_mcc_create *req;
1310 struct be_dma_mem *q_mem = &mccq->dma_mem;
1311 void *ctxt;
1312 int status;
1313
1314 if (mutex_lock_interruptible(&adapter->mbox_lock))
1315 return -1;
1316
1317 wrb = wrb_from_mbox(adapter);
1318 req = embedded_payload(wrb);
1319 ctxt = &req->context;
1320
106df1e3 1321 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1322 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1323 NULL);
34b1ef04
SK		 1324
1325 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1326
1327 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1328 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1329 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1330 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1331
1332 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1333
1334 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1335
1336 status = be_mbox_notify_wait(adapter);
1337 if (!status) {
1338 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1339
34b1ef04
SK		 1340 mccq->id = le16_to_cpu(resp->id);
1341 mccq->created = true;
1342 }
1343
1344 mutex_unlock(&adapter->mbox_lock);
1345 return status;
1346}
1347
1348int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1349 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1350{
1351 int status;
1352
1353 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1354 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1355 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1356 "or newer to avoid conflicting priorities between NIC "
1357 "and FCoE traffic");
1358 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1359 }
1360 return status;
1361}
1362
94d73aaa 1363int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1364{
7707133c 1365 struct be_mcc_wrb wrb = {0};
b31c50a7 1366 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1367 struct be_queue_info *txq = &txo->q;
1368 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1369 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1370 int status, ver = 0;
6b7c5b94 1371
7707133c 1372 req = embedded_payload(&wrb);
106df1e3 1373 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1374 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1375
8b7756ca
PR		 1376 if (lancer_chip(adapter)) {
1377 req->hdr.version = 1;
94d73aaa
VV		 1378 } else if (BEx_chip(adapter)) {
1379 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1380 req->hdr.version = 2;
1381 } else { /* For SH */
1382 req->hdr.version = 2;
8b7756ca
PR		 1383 }
1384
81b02655
VV		 1385 if (req->hdr.version > 0)
1386 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1387 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1388 req->ulp_num = BE_ULP1_NUM;
1389 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1390 req->cq_id = cpu_to_le16(cq->id);
1391 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1392 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1393 ver = req->hdr.version;
1394
7707133c 1395 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1396 if (!status) {
7707133c 1397 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1398
6b7c5b94 1399 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1400 if (ver == 2)
1401 txo->db_offset = le32_to_cpu(resp->db_offset);
1402 else
1403 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1404 txq->created = true;
1405 }
b31c50a7 1406
6b7c5b94
SP		 1407 return status;
1408}
1409
482c9e79 1410/* Uses MCC */
8788fdc2 1411int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1412 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1413 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1414{
b31c50a7
SP		 1415 struct be_mcc_wrb *wrb;
1416 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1417 struct be_dma_mem *q_mem = &rxq->dma_mem;
1418 int status;
1419
b7172414 1420 mutex_lock(&adapter->mcc_lock);
b31c50a7 1421
482c9e79
SP		 1422 wrb = wrb_from_mccq(adapter);
1423 if (!wrb) {
1424 status = -EBUSY;
1425 goto err;
1426 }
b31c50a7 1427 req = embedded_payload(wrb);
6b7c5b94 1428
106df1e3 1429 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1430 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1431
1432 req->cq_id = cpu_to_le16(cq_id);
1433 req->frag_size = fls(frag_size) - 1;
1434 req->num_pages = 2;
1435 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1436 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1437 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1438 req->rss_queue = cpu_to_le32(rss);
1439
482c9e79 1440 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1441 if (!status) {
1442 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1443
6b7c5b94
SP		 1444 rxq->id = le16_to_cpu(resp->id);
1445 rxq->created = true;
3abcdeda 1446 *rss_id = resp->rss_id;
6b7c5b94 1447 }
b31c50a7 1448
482c9e79 1449err:
b7172414 1450 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1451 return status;
1452}
1453
b31c50a7
SP		 1454/* Generic destroyer function for all types of queues
1455 * Uses Mbox
1456 */
8788fdc2 1457int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1458 int queue_type)
6b7c5b94 1459{
b31c50a7
SP		 1460 struct be_mcc_wrb *wrb;
1461 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1462 u8 subsys = 0, opcode = 0;
1463 int status;
1464
2984961c
IV		 1465 if (mutex_lock_interruptible(&adapter->mbox_lock))
1466 return -1;
6b7c5b94 1467
b31c50a7
SP		 1468 wrb = wrb_from_mbox(adapter);
1469 req = embedded_payload(wrb);
1470
6b7c5b94
SP		 1471 switch (queue_type) {
1472 case QTYPE_EQ:
1473 subsys = CMD_SUBSYSTEM_COMMON;
1474 opcode = OPCODE_COMMON_EQ_DESTROY;
1475 break;
1476 case QTYPE_CQ:
1477 subsys = CMD_SUBSYSTEM_COMMON;
1478 opcode = OPCODE_COMMON_CQ_DESTROY;
1479 break;
1480 case QTYPE_TXQ:
1481 subsys = CMD_SUBSYSTEM_ETH;
1482 opcode = OPCODE_ETH_TX_DESTROY;
1483 break;
1484 case QTYPE_RXQ:
1485 subsys = CMD_SUBSYSTEM_ETH;
1486 opcode = OPCODE_ETH_RX_DESTROY;
1487 break;
5fb379ee
SP		 1488 case QTYPE_MCCQ:
1489 subsys = CMD_SUBSYSTEM_COMMON;
1490 opcode = OPCODE_COMMON_MCC_DESTROY;
1491 break;
6b7c5b94 1492 default:
5f0b849e 1493 BUG();
6b7c5b94 1494 }
d744b44e 1495
106df1e3 1496 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1497 NULL);
6b7c5b94
SP		 1498 req->id = cpu_to_le16(q->id);
1499
b31c50a7 1500 status = be_mbox_notify_wait(adapter);
aa790db9 1501 q->created = false;
5f0b849e 1502
2984961c 1503 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1504 return status;
1505}
6b7c5b94 1506
482c9e79
SP		 1507/* Uses MCC */
1508int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1509{
1510 struct be_mcc_wrb *wrb;
1511 struct be_cmd_req_q_destroy *req;
1512 int status;
1513
b7172414 1514 mutex_lock(&adapter->mcc_lock);
482c9e79
SP		 1515
1516 wrb = wrb_from_mccq(adapter);
1517 if (!wrb) {
1518 status = -EBUSY;
1519 goto err;
1520 }
1521 req = embedded_payload(wrb);
1522
106df1e3 1523 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1524 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1525 req->id = cpu_to_le16(q->id);
1526
1527 status = be_mcc_notify_wait(adapter);
aa790db9 1528 q->created = false;
482c9e79
SP		 1529
1530err:
b7172414 1531 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1532 return status;
1533}
1534
b31c50a7 1535/* Create an rx filtering policy configuration on an i/f
bea50988 1536 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1537 */
73d540f2 1538int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1539 u32 *if_handle, u32 domain)
6b7c5b94 1540{
bea50988 1541 struct be_mcc_wrb wrb = {0};
b31c50a7 1542 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1543 int status;
1544
bea50988 1545 req = embedded_payload(&wrb);
106df1e3 1546 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1547 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1548 sizeof(*req), &wrb, NULL);
ba343c77 1549 req->hdr.domain = domain;
73d540f2
SP		 1550 req->capability_flags = cpu_to_le32(cap_flags);
1551 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1552 req->pmac_invalid = true;
6b7c5b94 1553
bea50988 1554 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1555 if (!status) {
bea50988 1556 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1557
6b7c5b94 1558 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1559
1560 /* Hack to retrieve VF's pmac-id on BE3 */
18c57c74 1561 if (BE3_chip(adapter) && be_virtfn(adapter))
b5bb9776 1562 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1563 }
6b7c5b94
SP		 1564 return status;
1565}
1566
62219066 1567/* Uses MCCQ if available else MBOX */
30128031 1568int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1569{
62219066 1570 struct be_mcc_wrb wrb = {0};
b31c50a7 1571 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1572 int status;
1573
30128031 1574 if (interface_id == -1)
f9449ab7 1575 return 0;
b31c50a7 1576
62219066 1577 req = embedded_payload(&wrb);
6b7c5b94 1578
106df1e3 1579 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 1580 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
62219066 1581 sizeof(*req), &wrb, NULL);
658681f7 1582 req->hdr.domain = domain;
6b7c5b94 1583 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1584
62219066 1585 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94
SP		 1586 return status;
1587}
1588
1589/* Get stats is a non embedded command: the request is not embedded inside
1590 * WRB but is a separate dma memory block
b31c50a7 1591 * Uses asynchronous MCC
6b7c5b94 1592 */
8788fdc2 1593int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1594{
b31c50a7 1595 struct be_mcc_wrb *wrb;
89a88ab8 1596 struct be_cmd_req_hdr *hdr;
713d0394 1597 int status = 0;
6b7c5b94 1598
b7172414 1599 mutex_lock(&adapter->mcc_lock);
6b7c5b94 1600
b31c50a7 1601 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1602 if (!wrb) {
1603 status = -EBUSY;
1604 goto err;
1605 }
89a88ab8 1606 hdr = nonemb_cmd->va;
6b7c5b94 1607
106df1e3 1608 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1609 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1610 nonemb_cmd);
89a88ab8 1611
ca34fe38 1612 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1613 if (BE2_chip(adapter))
1614 hdr->version = 0;
1615 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1616 hdr->version = 1;
61000861
AK		 1617 else
1618 hdr->version = 2;
89a88ab8 1619
efaa408e
SR		 1620 status = be_mcc_notify(adapter);
1621 if (status)
1622 goto err;
1623
b2aebe6d 1624 adapter->stats_cmd_sent = true;
6b7c5b94 1625
713d0394 1626err:
b7172414 1627 mutex_unlock(&adapter->mcc_lock);
713d0394 1628 return status;
6b7c5b94
SP		 1629}
1630
005d5696
SX		 1631/* Lancer Stats */
1632int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1633 struct be_dma_mem *nonemb_cmd)
005d5696 1634{
005d5696
SX		 1635 struct be_mcc_wrb *wrb;
1636 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1637 int status = 0;
1638
f25b119c
PR		 1639 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1640 CMD_SUBSYSTEM_ETH))
1641 return -EPERM;
1642
b7172414 1643 mutex_lock(&adapter->mcc_lock);
005d5696
SX		 1644
1645 wrb = wrb_from_mccq(adapter);
1646 if (!wrb) {
1647 status = -EBUSY;
1648 goto err;
1649 }
1650 req = nonemb_cmd->va;
005d5696 1651
106df1e3 1652 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1653 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1654 wrb, nonemb_cmd);
005d5696 1655
d51ebd33 1656 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1657 req->cmd_params.params.reset_stats = 0;
1658
efaa408e
SR		 1659 status = be_mcc_notify(adapter);
1660 if (status)
1661 goto err;
1662
005d5696
SX		 1663 adapter->stats_cmd_sent = true;
1664
1665err:
b7172414 1666 mutex_unlock(&adapter->mcc_lock);
005d5696
SX		 1667 return status;
1668}
1669
323ff71e
SP		 1670static int be_mac_to_link_speed(int mac_speed)
1671{
1672 switch (mac_speed) {
1673 case PHY_LINK_SPEED_ZERO:
1674 return 0;
1675 case PHY_LINK_SPEED_10MBPS:
1676 return 10;
1677 case PHY_LINK_SPEED_100MBPS:
1678 return 100;
1679 case PHY_LINK_SPEED_1GBPS:
1680 return 1000;
1681 case PHY_LINK_SPEED_10GBPS:
1682 return 10000;
b971f847
VV		 1683 case PHY_LINK_SPEED_20GBPS:
1684 return 20000;
1685 case PHY_LINK_SPEED_25GBPS:
1686 return 25000;
1687 case PHY_LINK_SPEED_40GBPS:
1688 return 40000;
323ff71e
SP		 1689 }
1690 return 0;
1691}
1692
1693/* Uses synchronous mcc
1694 * Returns link_speed in Mbps
1695 */
1696int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1697 u8 *link_status, u32 dom)
6b7c5b94 1698{
b31c50a7
SP		 1699 struct be_mcc_wrb *wrb;
1700 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1701 int status;
1702
b7172414 1703 mutex_lock(&adapter->mcc_lock);
b31c50a7 1704
b236916a
AK		 1705 if (link_status)
1706 *link_status = LINK_DOWN;
1707
b31c50a7 1708 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1709 if (!wrb) {
1710 status = -EBUSY;
1711 goto err;
1712 }
b31c50a7 1713 req = embedded_payload(wrb);
a8f447bd 1714
57cd80d4 1715 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1716 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1717 sizeof(*req), wrb, NULL);
57cd80d4 1718
ca34fe38
SP		 1719 /* version 1 of the cmd is not supported only by BE2 */
1720 if (!BE2_chip(adapter))
daad6167
PR		 1721 req->hdr.version = 1;
1722
57cd80d4 1723 req->hdr.domain = dom;
6b7c5b94 1724
b31c50a7 1725 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1726 if (!status) {
1727 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1728
323ff71e
SP		 1729 if (link_speed) {
1730 *link_speed = resp->link_speed ?
1731 le16_to_cpu(resp->link_speed) * 10 :
1732 be_mac_to_link_speed(resp->mac_speed);
1733
1734 if (!resp->logical_link_status)
1735 *link_speed = 0;
0388f251 1736 }
b236916a
AK		 1737 if (link_status)
1738 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1739 }
1740
713d0394 1741err:
b7172414 1742 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1743 return status;
1744}
1745
609ff3bb
AK		 1746/* Uses synchronous mcc */
1747int be_cmd_get_die_temperature(struct be_adapter *adapter)
1748{
1749 struct be_mcc_wrb *wrb;
1750 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1751 int status = 0;
609ff3bb 1752
b7172414 1753 mutex_lock(&adapter->mcc_lock);
609ff3bb
AK		 1754
1755 wrb = wrb_from_mccq(adapter);
1756 if (!wrb) {
1757 status = -EBUSY;
1758 goto err;
1759 }
1760 req = embedded_payload(wrb);
1761
106df1e3 1762 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1763 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1764 sizeof(*req), wrb, NULL);
609ff3bb 1765
efaa408e 1766 status = be_mcc_notify(adapter);
609ff3bb 1767err:
b7172414 1768 mutex_unlock(&adapter->mcc_lock);
609ff3bb
AK		 1769 return status;
1770}
1771
311fddc7 1772/* Uses synchronous mcc */
fd7ff6f0 1773int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
311fddc7 1774{
fd7ff6f0 1775 struct be_mcc_wrb wrb = {0};
311fddc7
SK		 1776 struct be_cmd_req_get_fat *req;
1777 int status;
1778
fd7ff6f0 1779 req = embedded_payload(&wrb);
311fddc7 1780
106df1e3 1781 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
fd7ff6f0
VD		 1782 OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1783 &wrb, NULL);
311fddc7 1784 req->fat_operation = cpu_to_le32(QUERY_FAT);
fd7ff6f0 1785 status = be_cmd_notify_wait(adapter, &wrb);
311fddc7 1786 if (!status) {
fd7ff6f0 1787 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
03d28ffe 1788
fd7ff6f0
VD		 1789 if (dump_size && resp->log_size)
1790 *dump_size = le32_to_cpu(resp->log_size) -
fe2a70ee 1791 sizeof(u32);
311fddc7 1792 }
311fddc7
SK		 1793 return status;
1794}
1795
fd7ff6f0 1796int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1797{
1798 struct be_dma_mem get_fat_cmd;
1799 struct be_mcc_wrb *wrb;
1800 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1801 u32 offset = 0, total_size, buf_size,
1802 log_offset = sizeof(u32), payload_len;
fd7ff6f0 1803 int status;
311fddc7
SK		 1804
1805 if (buf_len == 0)
fd7ff6f0 1806 return 0;
311fddc7
SK		 1807
1808 total_size = buf_len;
1809
fe2a70ee 1810 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
e51000db
SB		 1811 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1812 get_fat_cmd.size,
1813 &get_fat_cmd.dma, GFP_ATOMIC);
fd7ff6f0 1814 if (!get_fat_cmd.va)
c5f156de 1815 return -ENOMEM;
fe2a70ee 1816
b7172414 1817 mutex_lock(&adapter->mcc_lock);
311fddc7 1818
311fddc7
SK		 1819 while (total_size) {
1820 buf_size = min(total_size, (u32)60*1024);
1821 total_size -= buf_size;
1822
fe2a70ee
SK		 1823 wrb = wrb_from_mccq(adapter);
1824 if (!wrb) {
1825 status = -EBUSY;
311fddc7
SK		 1826 goto err;
1827 }
1828 req = get_fat_cmd.va;
311fddc7 1829
fe2a70ee 1830 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1831 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1832 OPCODE_COMMON_MANAGE_FAT, payload_len,
1833 wrb, &get_fat_cmd);
311fddc7
SK		 1834
1835 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1836 req->read_log_offset = cpu_to_le32(log_offset);
1837 req->read_log_length = cpu_to_le32(buf_size);
1838 req->data_buffer_size = cpu_to_le32(buf_size);
1839
1840 status = be_mcc_notify_wait(adapter);
1841 if (!status) {
1842 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1843
311fddc7 1844 memcpy(buf + offset,
a2cc4e0b
SP		 1845 resp->data_buffer,
1846 le32_to_cpu(resp->read_log_length));
fe2a70ee 1847 } else {
311fddc7 1848 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1849 goto err;
1850 }
311fddc7
SK		 1851 offset += buf_size;
1852 log_offset += buf_size;
1853 }
1854err:
e51000db
SB		 1855 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1856 get_fat_cmd.va, get_fat_cmd.dma);
b7172414 1857 mutex_unlock(&adapter->mcc_lock);
c5f156de 1858 return status;
311fddc7
SK		 1859}
1860
04b71175 1861/* Uses synchronous mcc */
e97e3cda 1862int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1863{
b31c50a7
SP		 1864 struct be_mcc_wrb *wrb;
1865 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1866 int status;
1867
b7172414 1868 mutex_lock(&adapter->mcc_lock);
b31c50a7 1869
04b71175
SP		 1870 wrb = wrb_from_mccq(adapter);
1871 if (!wrb) {
1872 status = -EBUSY;
1873 goto err;
1874 }
6b7c5b94 1875
04b71175 1876 req = embedded_payload(wrb);
6b7c5b94 1877
106df1e3 1878 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1879 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1880 NULL);
04b71175 1881 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1882 if (!status) {
1883 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1884
242eb470
VV		 1885 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1886 sizeof(adapter->fw_ver));
1887 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1888 sizeof(adapter->fw_on_flash));
6b7c5b94 1889 }
04b71175 1890err:
b7172414 1891 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1892 return status;
1893}
1894
b31c50a7
SP		 1895/* set the EQ delay interval of an EQ to specified value
1896 * Uses async mcc
1897 */
b502ae8d
KA		 1898static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1899 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1900{
b31c50a7
SP		 1901 struct be_mcc_wrb *wrb;
1902 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1903 int status = 0, i;
6b7c5b94 1904
b7172414 1905 mutex_lock(&adapter->mcc_lock);
b31c50a7
SP		 1906
1907 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1908 if (!wrb) {
1909 status = -EBUSY;
1910 goto err;
1911 }
b31c50a7 1912 req = embedded_payload(wrb);
6b7c5b94 1913
106df1e3 1914 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1915 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1916 NULL);
6b7c5b94 1917
2632bafd
SP		 1918 req->num_eq = cpu_to_le32(num);
1919 for (i = 0; i < num; i++) {
1920 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1921 req->set_eqd[i].phase = 0;
1922 req->set_eqd[i].delay_multiplier =
1923 cpu_to_le32(set_eqd[i].delay_multiplier);
1924 }
6b7c5b94 1925
efaa408e 1926 status = be_mcc_notify(adapter);
713d0394 1927err:
b7172414 1928 mutex_unlock(&adapter->mcc_lock);
713d0394 1929 return status;
6b7c5b94
SP		 1930}
1931
93676703
KA		 1932int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1933 int num)
1934{
1935 int num_eqs, i = 0;
1936
c8ba4ad0
SR		 1937 while (num) {
1938 num_eqs = min(num, 8);
1939 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1940 i += num_eqs;
1941 num -= num_eqs;
93676703
KA		 1942 }
1943
1944 return 0;
1945}
1946
b31c50a7 1947/* Uses sycnhronous mcc */
8788fdc2 1948int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 1949 u32 num, u32 domain)
6b7c5b94 1950{
b31c50a7
SP		 1951 struct be_mcc_wrb *wrb;
1952 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1953 int status;
1954
b7172414 1955 mutex_lock(&adapter->mcc_lock);
b31c50a7
SP		 1956
1957 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1958 if (!wrb) {
1959 status = -EBUSY;
1960 goto err;
1961 }
b31c50a7 1962 req = embedded_payload(wrb);
6b7c5b94 1963
106df1e3 1964 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1965 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1966 wrb, NULL);
435452aa 1967 req->hdr.domain = domain;
6b7c5b94
SP		 1968
1969 req->interface_id = if_id;
012bd387 1970 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1971 req->num_vlan = num;
4d567d97
KA		 1972 memcpy(req->normal_vlan, vtag_array,
1973 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1974
b31c50a7 1975 status = be_mcc_notify_wait(adapter);
713d0394 1976err:
b7172414 1977 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1978 return status;
1979}
1980
ac34b743 1981static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1982{
6ac7b687 1983 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1984 struct be_dma_mem *mem = &adapter->rx_filter;
1985 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1986 int status;
6b7c5b94 1987
b7172414 1988 mutex_lock(&adapter->mcc_lock);
6ac7b687 1989
b31c50a7 1990 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1991 if (!wrb) {
1992 status = -EBUSY;
1993 goto err;
1994 }
5b8821b7 1995 memset(req, 0, sizeof(*req));
106df1e3 1996 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1997 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1998 wrb, mem);
6b7c5b94 1999
5b8821b7 2000 req->if_id = cpu_to_le32(adapter->if_handle);
ac34b743
SP		 2001 req->if_flags_mask = cpu_to_le32(flags);
2002 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
2003
2004 if (flags & BE_IF_FLAGS_MULTICAST) {
b7172414 2005 int i;
24307eef 2006
1610c79f
PR		 2007 /* Reset mcast promisc mode if already set by setting mask
2008 * and not setting flags field
2009 */
abb93951
PR		 2010 req->if_flags_mask |=
2011 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 2012 be_if_cap_flags(adapter));
b7172414
SP		 2013 req->mcast_num = cpu_to_le32(adapter->mc_count);
2014 for (i = 0; i < adapter->mc_count; i++)
2015 ether_addr_copy(req->mcast_mac[i].byte,
2016 adapter->mc_list[i].mac);
6b7c5b94
SP		 2017 }
2018
b6588879 2019 status = be_mcc_notify_wait(adapter);
713d0394 2020err:
b7172414 2021 mutex_unlock(&adapter->mcc_lock);
e7b909a6 2022 return status;
6b7c5b94
SP		 2023}
2024
ac34b743
SP		 2025int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2026{
2027 struct device *dev = &adapter->pdev->dev;
2028
2029 if ((flags & be_if_cap_flags(adapter)) != flags) {
2030 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2031 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2032 be_if_cap_flags(adapter));
2033 }
2034 flags &= be_if_cap_flags(adapter);
196e3735
KA		 2035 if (!flags)
2036 return -ENOTSUPP;
ac34b743
SP		 2037
2038 return __be_cmd_rx_filter(adapter, flags, value);
2039}
2040
b31c50a7 2041/* Uses synchrounous mcc */
8788fdc2 2042int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 2043{
b31c50a7
SP		 2044 struct be_mcc_wrb *wrb;
2045 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 2046 int status;
2047
f25b119c
PR		 2048 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2049 CMD_SUBSYSTEM_COMMON))
2050 return -EPERM;
2051
b7172414 2052 mutex_lock(&adapter->mcc_lock);
6b7c5b94 2053
b31c50a7 2054 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2055 if (!wrb) {
2056 status = -EBUSY;
2057 goto err;
2058 }
b31c50a7 2059 req = embedded_payload(wrb);
6b7c5b94 2060
106df1e3 2061 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2062 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2063 wrb, NULL);
6b7c5b94 2064
b29812c1 2065 req->hdr.version = 1;
6b7c5b94
SP		 2066 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2067 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2068
b31c50a7 2069 status = be_mcc_notify_wait(adapter);
6b7c5b94 2070
713d0394 2071err:
b7172414 2072 mutex_unlock(&adapter->mcc_lock);
b29812c1
SR		 2073
2074 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2075 return -EOPNOTSUPP;
2076
6b7c5b94
SP		 2077 return status;
2078}
2079
b31c50a7 2080/* Uses sycn mcc */
8788fdc2 2081int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 2082{
b31c50a7
SP		 2083 struct be_mcc_wrb *wrb;
2084 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 2085 int status;
2086
f25b119c
PR		 2087 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2088 CMD_SUBSYSTEM_COMMON))
2089 return -EPERM;
2090
b7172414 2091 mutex_lock(&adapter->mcc_lock);
6b7c5b94 2092
b31c50a7 2093 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2094 if (!wrb) {
2095 status = -EBUSY;
2096 goto err;
2097 }
b31c50a7 2098 req = embedded_payload(wrb);
6b7c5b94 2099
106df1e3 2100 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2101 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2102 wrb, NULL);
6b7c5b94 2103
b31c50a7 2104 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2105 if (!status) {
2106 struct be_cmd_resp_get_flow_control *resp =
2107 embedded_payload(wrb);
03d28ffe 2108
6b7c5b94
SP		 2109 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2110 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2111 }
2112
713d0394 2113err:
b7172414 2114 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 2115 return status;
2116}
2117
b31c50a7 2118/* Uses mbox */
e97e3cda 2119int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2120{
b31c50a7
SP		 2121 struct be_mcc_wrb *wrb;
2122 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2123 int status;
2124
2984961c
IV		 2125 if (mutex_lock_interruptible(&adapter->mbox_lock))
2126 return -1;
6b7c5b94 2127
b31c50a7
SP		 2128 wrb = wrb_from_mbox(adapter);
2129 req = embedded_payload(wrb);
6b7c5b94 2130
106df1e3 2131 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2132 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2133 sizeof(*req), wrb, NULL);
6b7c5b94 2134
b31c50a7 2135 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2136 if (!status) {
2137 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2138
e97e3cda
KA		 2139 adapter->port_num = le32_to_cpu(resp->phys_port);
2140 adapter->function_mode = le32_to_cpu(resp->function_mode);
2141 adapter->function_caps = le32_to_cpu(resp->function_caps);
2142 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2143 dev_info(&adapter->pdev->dev,
2144 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2145 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2146 }
2147
2984961c 2148 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2149 return status;
2150}
14074eab 2151
b31c50a7 2152/* Uses mbox */
14074eab 2153int be_cmd_reset_function(struct be_adapter *adapter)
2154{
b31c50a7
SP		 2155 struct be_mcc_wrb *wrb;
2156 struct be_cmd_req_hdr *req;
14074eab 2157 int status;
2158
bf99e50d 2159 if (lancer_chip(adapter)) {
9fa465c0
SP		 2160 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2161 adapter->db + SLIPORT_CONTROL_OFFSET);
bf99e50d 2162 status = lancer_wait_ready(adapter);
9fa465c0 2163 if (status)
bf99e50d
PR		 2164 dev_err(&adapter->pdev->dev,
2165 "Adapter in non recoverable error\n");
bf99e50d
PR		 2166 return status;
2167 }
2168
2984961c
IV		 2169 if (mutex_lock_interruptible(&adapter->mbox_lock))
2170 return -1;
14074eab 2171
b31c50a7
SP		 2172 wrb = wrb_from_mbox(adapter);
2173 req = embedded_payload(wrb);
14074eab 2174
106df1e3 2175 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2176 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2177 NULL);
14074eab 2178
b31c50a7 2179 status = be_mbox_notify_wait(adapter);
14074eab 2180
2984961c 2181 mutex_unlock(&adapter->mbox_lock);
14074eab 2182 return status;
2183}
84517482 2184
594ad54a 2185int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2186 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2187{
2188 struct be_mcc_wrb *wrb;
2189 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2190 int status;
2191
da1388d6
VV		 2192 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2193 return 0;
2194
b7172414 2195 mutex_lock(&adapter->mcc_lock);
3abcdeda 2196
b51aa367
KA		 2197 wrb = wrb_from_mccq(adapter);
2198 if (!wrb) {
2199 status = -EBUSY;
2200 goto err;
2201 }
3abcdeda
SP		 2202 req = embedded_payload(wrb);
2203
106df1e3 2204 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2205 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2206
2207 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2208 req->enable_rss = cpu_to_le16(rss_hash_opts);
2209 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2210
b51aa367 2211 if (!BEx_chip(adapter))
d3bd3a5e 2212 req->hdr.version = 1;
d3bd3a5e 2213
3abcdeda 2214 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2215 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2216 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2217
b51aa367
KA		 2218 status = be_mcc_notify_wait(adapter);
2219err:
b7172414 2220 mutex_unlock(&adapter->mcc_lock);
3abcdeda
SP		 2221 return status;
2222}
2223
fad9ab2c
SB		 2224/* Uses sync mcc */
2225int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2226 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2227{
2228 struct be_mcc_wrb *wrb;
2229 struct be_cmd_req_enable_disable_beacon *req;
2230 int status;
2231
b7172414 2232 mutex_lock(&adapter->mcc_lock);
fad9ab2c
SB		 2233
2234 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2235 if (!wrb) {
2236 status = -EBUSY;
2237 goto err;
2238 }
fad9ab2c
SB		 2239 req = embedded_payload(wrb);
2240
106df1e3 2241 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2242 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2243 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2244
2245 req->port_num = port_num;
2246 req->beacon_state = state;
2247 req->beacon_duration = bcn;
2248 req->status_duration = sts;
2249
2250 status = be_mcc_notify_wait(adapter);
2251
713d0394 2252err:
b7172414 2253 mutex_unlock(&adapter->mcc_lock);
fad9ab2c
SB		 2254 return status;
2255}
2256
2257/* Uses sync mcc */
2258int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2259{
2260 struct be_mcc_wrb *wrb;
2261 struct be_cmd_req_get_beacon_state *req;
2262 int status;
2263
b7172414 2264 mutex_lock(&adapter->mcc_lock);
fad9ab2c
SB		 2265
2266 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2267 if (!wrb) {
2268 status = -EBUSY;
2269 goto err;
2270 }
fad9ab2c
SB		 2271 req = embedded_payload(wrb);
2272
106df1e3 2273 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2274 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2275 wrb, NULL);
fad9ab2c
SB		 2276
2277 req->port_num = port_num;
2278
2279 status = be_mcc_notify_wait(adapter);
2280 if (!status) {
2281 struct be_cmd_resp_get_beacon_state *resp =
2282 embedded_payload(wrb);
03d28ffe 2283
fad9ab2c
SB		 2284 *state = resp->beacon_state;
2285 }
2286
713d0394 2287err:
b7172414 2288 mutex_unlock(&adapter->mcc_lock);
fad9ab2c
SB		 2289 return status;
2290}
2291
e36edd9d
ML		 2292/* Uses sync mcc */
2293int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2294 u8 page_num, u8 *data)
2295{
2296 struct be_dma_mem cmd;
2297 struct be_mcc_wrb *wrb;
2298 struct be_cmd_req_port_type *req;
2299 int status;
2300
2301 if (page_num > TR_PAGE_A2)
2302 return -EINVAL;
2303
2304 cmd.size = sizeof(struct be_cmd_resp_port_type);
e51000db
SB		 2305 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2306 GFP_ATOMIC);
e36edd9d
ML		 2307 if (!cmd.va) {
2308 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2309 return -ENOMEM;
2310 }
e36edd9d 2311
b7172414 2312 mutex_lock(&adapter->mcc_lock);
e36edd9d
ML		 2313
2314 wrb = wrb_from_mccq(adapter);
2315 if (!wrb) {
2316 status = -EBUSY;
2317 goto err;
2318 }
2319 req = cmd.va;
2320
2321 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2322 OPCODE_COMMON_READ_TRANSRECV_DATA,
2323 cmd.size, wrb, &cmd);
2324
2325 req->port = cpu_to_le32(adapter->hba_port_num);
2326 req->page_num = cpu_to_le32(page_num);
2327 status = be_mcc_notify_wait(adapter);
2328 if (!status) {
2329 struct be_cmd_resp_port_type *resp = cmd.va;
2330
2331 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2332 }
2333err:
b7172414 2334 mutex_unlock(&adapter->mcc_lock);
e51000db 2335 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
e36edd9d
ML		 2336 return status;
2337}
2338
a23113b5
SR		 2339static int lancer_cmd_write_object(struct be_adapter *adapter,
2340 struct be_dma_mem *cmd, u32 data_size,
2341 u32 data_offset, const char *obj_name,
2342 u32 *data_written, u8 *change_status,
2343 u8 *addn_status)
485bf569
SN		 2344{
2345 struct be_mcc_wrb *wrb;
2346 struct lancer_cmd_req_write_object *req;
2347 struct lancer_cmd_resp_write_object *resp;
2348 void *ctxt = NULL;
2349 int status;
2350
b7172414 2351 mutex_lock(&adapter->mcc_lock);
485bf569
SN		 2352 adapter->flash_status = 0;
2353
2354 wrb = wrb_from_mccq(adapter);
2355 if (!wrb) {
2356 status = -EBUSY;
2357 goto err_unlock;
2358 }
2359
2360 req = embedded_payload(wrb);
2361
106df1e3 2362 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2363 OPCODE_COMMON_WRITE_OBJECT,
2364 sizeof(struct lancer_cmd_req_write_object), wrb,
2365 NULL);
485bf569
SN		 2366
2367 ctxt = &req->context;
2368 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2369 write_length, ctxt, data_size);
485bf569
SN		 2370
2371 if (data_size == 0)
2372 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2373 eof, ctxt, 1);
485bf569
SN		 2374 else
2375 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2376 eof, ctxt, 0);
485bf569
SN		 2377
2378 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2379 req->write_offset = cpu_to_le32(data_offset);
242eb470 2380 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2381 req->descriptor_count = cpu_to_le32(1);
2382 req->buf_len = cpu_to_le32(data_size);
2383 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2384 sizeof(struct lancer_cmd_req_write_object))
2385 & 0xFFFFFFFF);
485bf569
SN		 2386 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2387 sizeof(struct lancer_cmd_req_write_object)));
2388
efaa408e
SR		 2389 status = be_mcc_notify(adapter);
2390 if (status)
2391 goto err_unlock;
2392
b7172414 2393 mutex_unlock(&adapter->mcc_lock);
485bf569 2394
5eeff635 2395 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2396 msecs_to_jiffies(60000)))
fd45160c 2397 status = -ETIMEDOUT;
485bf569
SN		 2398 else
2399 status = adapter->flash_status;
2400
2401 resp = embedded_payload(wrb);
f67ef7ba 2402 if (!status) {
485bf569 2403 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2404 *change_status = resp->change_status;
2405 } else {
485bf569 2406 *addn_status = resp->additional_status;
f67ef7ba 2407 }
485bf569
SN		 2408
2409 return status;
2410
2411err_unlock:
b7172414 2412 mutex_unlock(&adapter->mcc_lock);
485bf569
SN		 2413 return status;
2414}
2415
6809cee0
RN		 2416int be_cmd_query_cable_type(struct be_adapter *adapter)
2417{
2418 u8 page_data[PAGE_DATA_LEN];
2419 int status;
2420
2421 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2422 page_data);
2423 if (!status) {
2424 switch (adapter->phy.interface_type) {
2425 case PHY_TYPE_QSFP:
2426 adapter->phy.cable_type =
2427 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2428 break;
2429 case PHY_TYPE_SFP_PLUS_10GB:
2430 adapter->phy.cable_type =
2431 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2432 break;
2433 default:
2434 adapter->phy.cable_type = 0;
2435 break;
2436 }
2437 }
2438 return status;
2439}
2440
21252377
VV		 2441int be_cmd_query_sfp_info(struct be_adapter *adapter)
2442{
2443 u8 page_data[PAGE_DATA_LEN];
2444 int status;
2445
2446 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2447 page_data);
2448 if (!status) {
2449 strlcpy(adapter->phy.vendor_name, page_data +
2450 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2451 strlcpy(adapter->phy.vendor_pn,
2452 page_data + SFP_VENDOR_PN_OFFSET,
2453 SFP_VENDOR_NAME_LEN - 1);
2454 }
2455
2456 return status;
2457}
2458
a23113b5
SR		 2459static int lancer_cmd_delete_object(struct be_adapter *adapter,
2460 const char *obj_name)
f0613380
KA		 2461{
2462 struct lancer_cmd_req_delete_object *req;
2463 struct be_mcc_wrb *wrb;
2464 int status;
2465
b7172414 2466 mutex_lock(&adapter->mcc_lock);
f0613380
KA		 2467
2468 wrb = wrb_from_mccq(adapter);
2469 if (!wrb) {
2470 status = -EBUSY;
2471 goto err;
2472 }
2473
2474 req = embedded_payload(wrb);
2475
2476 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2477 OPCODE_COMMON_DELETE_OBJECT,
2478 sizeof(*req), wrb, NULL);
2479
242eb470 2480 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2481
2482 status = be_mcc_notify_wait(adapter);
2483err:
b7172414 2484 mutex_unlock(&adapter->mcc_lock);
f0613380
KA		 2485 return status;
2486}
2487
de49bd5a 2488int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2489 u32 data_size, u32 data_offset, const char *obj_name,
2490 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2491{
2492 struct be_mcc_wrb *wrb;
2493 struct lancer_cmd_req_read_object *req;
2494 struct lancer_cmd_resp_read_object *resp;
2495 int status;
2496
b7172414 2497 mutex_lock(&adapter->mcc_lock);
de49bd5a
PR		 2498
2499 wrb = wrb_from_mccq(adapter);
2500 if (!wrb) {
2501 status = -EBUSY;
2502 goto err_unlock;
2503 }
2504
2505 req = embedded_payload(wrb);
2506
2507 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2508 OPCODE_COMMON_READ_OBJECT,
2509 sizeof(struct lancer_cmd_req_read_object), wrb,
2510 NULL);
de49bd5a
PR		 2511
2512 req->desired_read_len = cpu_to_le32(data_size);
2513 req->read_offset = cpu_to_le32(data_offset);
2514 strcpy(req->object_name, obj_name);
2515 req->descriptor_count = cpu_to_le32(1);
2516 req->buf_len = cpu_to_le32(data_size);
2517 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2518 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2519
2520 status = be_mcc_notify_wait(adapter);
2521
2522 resp = embedded_payload(wrb);
2523 if (!status) {
2524 *data_read = le32_to_cpu(resp->actual_read_len);
2525 *eof = le32_to_cpu(resp->eof);
2526 } else {
2527 *addn_status = resp->additional_status;
2528 }
2529
2530err_unlock:
b7172414 2531 mutex_unlock(&adapter->mcc_lock);
de49bd5a
PR		 2532 return status;
2533}
2534
a23113b5
SR		 2535static int be_cmd_write_flashrom(struct be_adapter *adapter,
2536 struct be_dma_mem *cmd, u32 flash_type,
2537 u32 flash_opcode, u32 img_offset, u32 buf_size)
84517482 2538{
b31c50a7 2539 struct be_mcc_wrb *wrb;
3f0d4560 2540 struct be_cmd_write_flashrom *req;
84517482
AK		 2541 int status;
2542
b7172414 2543 mutex_lock(&adapter->mcc_lock);
dd131e76 2544 adapter->flash_status = 0;
b31c50a7
SP		 2545
2546 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2547 if (!wrb) {
2548 status = -EBUSY;
2892d9c2 2549 goto err_unlock;
713d0394
SP		 2550 }
2551 req = cmd->va;
84517482 2552
106df1e3 2553 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2554 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2555 cmd);
84517482
AK		 2556
2557 req->params.op_type = cpu_to_le32(flash_type);
70a7b525
VV		 2558 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2559 req->params.offset = cpu_to_le32(img_offset);
2560
84517482
AK		 2561 req->params.op_code = cpu_to_le32(flash_opcode);
2562 req->params.data_buf_size = cpu_to_le32(buf_size);
2563
efaa408e
SR		 2564 status = be_mcc_notify(adapter);
2565 if (status)
2566 goto err_unlock;
2567
b7172414 2568 mutex_unlock(&adapter->mcc_lock);
dd131e76 2569
5eeff635
SR		 2570 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2571 msecs_to_jiffies(40000)))
fd45160c 2572 status = -ETIMEDOUT;
dd131e76
SB		 2573 else
2574 status = adapter->flash_status;
84517482 2575
2892d9c2
DC		 2576 return status;
2577
2578err_unlock:
b7172414 2579 mutex_unlock(&adapter->mcc_lock);
84517482
AK		 2580 return status;
2581}
fa9a6fed 2582
a23113b5
SR		 2583static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2584 u16 img_optype, u32 img_offset, u32 crc_offset)
fa9a6fed 2585{
be716446 2586 struct be_cmd_read_flash_crc *req;
70a7b525 2587 struct be_mcc_wrb *wrb;
fa9a6fed
SB		 2588 int status;
2589
b7172414 2590 mutex_lock(&adapter->mcc_lock);
fa9a6fed
SB		 2591
2592 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2593 if (!wrb) {
2594 status = -EBUSY;
2595 goto err;
2596 }
fa9a6fed
SB		 2597 req = embedded_payload(wrb);
2598
106df1e3 2599 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2600 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2601 wrb, NULL);
fa9a6fed 2602
70a7b525
VV		 2603 req->params.op_type = cpu_to_le32(img_optype);
2604 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2605 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2606 else
2607 req->params.offset = cpu_to_le32(crc_offset);
2608
fa9a6fed 2609 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710 2610 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2611
2612 status = be_mcc_notify_wait(adapter);
2613 if (!status)
be716446 2614 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2615
713d0394 2616err:
b7172414 2617 mutex_unlock(&adapter->mcc_lock);
fa9a6fed
SB		 2618 return status;
2619}
71d8d1b5 2620
a23113b5
SR		 2621static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2622
2623static bool phy_flashing_required(struct be_adapter *adapter)
2624{
2625 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2626 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2627}
2628
2629static bool is_comp_in_ufi(struct be_adapter *adapter,
2630 struct flash_section_info *fsec, int type)
2631{
2632 int i = 0, img_type = 0;
2633 struct flash_section_info_g2 *fsec_g2 = NULL;
2634
2635 if (BE2_chip(adapter))
2636 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2637
2638 for (i = 0; i < MAX_FLASH_COMP; i++) {
2639 if (fsec_g2)
2640 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2641 else
2642 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2643
2644 if (img_type == type)
2645 return true;
2646 }
2647 return false;
2648}
2649
2650static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2651 int header_size,
2652 const struct firmware *fw)
2653{
2654 struct flash_section_info *fsec = NULL;
2655 const u8 *p = fw->data;
2656
2657 p += header_size;
2658 while (p < (fw->data + fw->size)) {
2659 fsec = (struct flash_section_info *)p;
2660 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2661 return fsec;
2662 p += 32;
2663 }
2664 return NULL;
2665}
2666
2667static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2668 u32 img_offset, u32 img_size, int hdr_size,
2669 u16 img_optype, bool *crc_match)
2670{
2671 u32 crc_offset;
2672 int status;
2673 u8 crc[4];
2674
2675 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2676 img_size - 4);
2677 if (status)
2678 return status;
2679
2680 crc_offset = hdr_size + img_offset + img_size - 4;
2681
2682 /* Skip flashing, if crc of flashed region matches */
2683 if (!memcmp(crc, p + crc_offset, 4))
2684 *crc_match = true;
2685 else
2686 *crc_match = false;
2687
2688 return status;
2689}
2690
2691static int be_flash(struct be_adapter *adapter, const u8 *img,
2692 struct be_dma_mem *flash_cmd, int optype, int img_size,
2693 u32 img_offset)
2694{
2695 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2696 struct be_cmd_write_flashrom *req = flash_cmd->va;
2697 int status;
2698
2699 while (total_bytes) {
2700 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2701
2702 total_bytes -= num_bytes;
2703
2704 if (!total_bytes) {
2705 if (optype == OPTYPE_PHY_FW)
2706 flash_op = FLASHROM_OPER_PHY_FLASH;
2707 else
2708 flash_op = FLASHROM_OPER_FLASH;
2709 } else {
2710 if (optype == OPTYPE_PHY_FW)
2711 flash_op = FLASHROM_OPER_PHY_SAVE;
2712 else
2713 flash_op = FLASHROM_OPER_SAVE;
2714 }
2715
2716 memcpy(req->data_buf, img, num_bytes);
2717 img += num_bytes;
2718 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2719 flash_op, img_offset +
2720 bytes_sent, num_bytes);
2721 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2722 optype == OPTYPE_PHY_FW)
2723 break;
2724 else if (status)
2725 return status;
2726
2727 bytes_sent += num_bytes;
2728 }
2729 return 0;
2730}
2731
f5ef017e
SB		 2732#define NCSI_UPDATE_LOG "NCSI section update is not supported in FW ver %s\n"
2733static bool be_fw_ncsi_supported(char *ver)
2734{
2735 int v1[4] = {3, 102, 148, 0}; /* Min ver that supports NCSI FW */
2736 int v2[4];
2737 int i;
2738
2739 if (sscanf(ver, "%d.%d.%d.%d", &v2[0], &v2[1], &v2[2], &v2[3]) != 4)
2740 return false;
2741
2742 for (i = 0; i < 4; i++) {
2743 if (v1[i] < v2[i])
2744 return true;
2745 else if (v1[i] > v2[i])
2746 return false;
2747 }
2748
2749 return true;
2750}
2751
a23113b5
SR		 2752/* For BE2, BE3 and BE3-R */
2753static int be_flash_BEx(struct be_adapter *adapter,
2754 const struct firmware *fw,
2755 struct be_dma_mem *flash_cmd, int num_of_images)
2756{
2757 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2758 struct device *dev = &adapter->pdev->dev;
2759 struct flash_section_info *fsec = NULL;
2760 int status, i, filehdr_size, num_comp;
2761 const struct flash_comp *pflashcomp;
2762 bool crc_match;
2763 const u8 *p;
2764
2765 struct flash_comp gen3_flash_types[] = {
2766 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2767 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2768 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2769 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2770 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2771 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2772 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2773 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2774 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2775 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2776 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2777 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2778 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2779 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2780 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2781 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2782 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2783 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2784 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2785 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2786 };
2787
2788 struct flash_comp gen2_flash_types[] = {
2789 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2790 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2791 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2792 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2793 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2794 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2795 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2796 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2797 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2798 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2799 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2800 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2801 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2802 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2803 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2804 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2805 };
2806
2807 if (BE3_chip(adapter)) {
2808 pflashcomp = gen3_flash_types;
2809 filehdr_size = sizeof(struct flash_file_hdr_g3);
2810 num_comp = ARRAY_SIZE(gen3_flash_types);
2811 } else {
2812 pflashcomp = gen2_flash_types;
2813 filehdr_size = sizeof(struct flash_file_hdr_g2);
2814 num_comp = ARRAY_SIZE(gen2_flash_types);
2815 img_hdrs_size = 0;
2816 }
2817
2818 /* Get flash section info*/
2819 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2820 if (!fsec) {
2821 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2822 return -1;
2823 }
2824 for (i = 0; i < num_comp; i++) {
2825 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2826 continue;
2827
2828 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
f5ef017e
SB		 2829 !be_fw_ncsi_supported(adapter->fw_ver)) {
2830 dev_info(dev, NCSI_UPDATE_LOG, adapter->fw_ver);
a23113b5 2831 continue;
f5ef017e 2832 }
a23113b5
SR		 2833
2834 if (pflashcomp[i].optype == OPTYPE_PHY_FW &&
2835 !phy_flashing_required(adapter))
2836 continue;
2837
2838 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2839 status = be_check_flash_crc(adapter, fw->data,
2840 pflashcomp[i].offset,
2841 pflashcomp[i].size,
2842 filehdr_size +
2843 img_hdrs_size,
2844 OPTYPE_REDBOOT, &crc_match);
2845 if (status) {
2846 dev_err(dev,
2847 "Could not get CRC for 0x%x region\n",
2848 pflashcomp[i].optype);
2849 continue;
2850 }
2851
2852 if (crc_match)
2853 continue;
2854 }
2855
2856 p = fw->data + filehdr_size + pflashcomp[i].offset +
2857 img_hdrs_size;
2858 if (p + pflashcomp[i].size > fw->data + fw->size)
2859 return -1;
2860
2861 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2862 pflashcomp[i].size, 0);
2863 if (status) {
2864 dev_err(dev, "Flashing section type 0x%x failed\n",
2865 pflashcomp[i].img_type);
2866 return status;
2867 }
2868 }
2869 return 0;
2870}
2871
2872static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2873{
2874 u32 img_type = le32_to_cpu(fsec_entry.type);
2875 u16 img_optype = le16_to_cpu(fsec_entry.optype);
2876
2877 if (img_optype != 0xFFFF)
2878 return img_optype;
2879
2880 switch (img_type) {
2881 case IMAGE_FIRMWARE_ISCSI:
2882 img_optype = OPTYPE_ISCSI_ACTIVE;
2883 break;
2884 case IMAGE_BOOT_CODE:
2885 img_optype = OPTYPE_REDBOOT;
2886 break;
2887 case IMAGE_OPTION_ROM_ISCSI:
2888 img_optype = OPTYPE_BIOS;
2889 break;
2890 case IMAGE_OPTION_ROM_PXE:
2891 img_optype = OPTYPE_PXE_BIOS;
2892 break;
2893 case IMAGE_OPTION_ROM_FCOE:
2894 img_optype = OPTYPE_FCOE_BIOS;
2895 break;
2896 case IMAGE_FIRMWARE_BACKUP_ISCSI:
2897 img_optype = OPTYPE_ISCSI_BACKUP;
2898 break;
2899 case IMAGE_NCSI:
2900 img_optype = OPTYPE_NCSI_FW;
2901 break;
2902 case IMAGE_FLASHISM_JUMPVECTOR:
2903 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2904 break;
2905 case IMAGE_FIRMWARE_PHY:
2906 img_optype = OPTYPE_SH_PHY_FW;
2907 break;
2908 case IMAGE_REDBOOT_DIR:
2909 img_optype = OPTYPE_REDBOOT_DIR;
2910 break;
2911 case IMAGE_REDBOOT_CONFIG:
2912 img_optype = OPTYPE_REDBOOT_CONFIG;
2913 break;
2914 case IMAGE_UFI_DIR:
2915 img_optype = OPTYPE_UFI_DIR;
2916 break;
2917 default:
2918 break;
2919 }
2920
2921 return img_optype;
2922}
2923
2924static int be_flash_skyhawk(struct be_adapter *adapter,
2925 const struct firmware *fw,
2926 struct be_dma_mem *flash_cmd, int num_of_images)
2927{
2928 int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2929 bool crc_match, old_fw_img, flash_offset_support = true;
2930 struct device *dev = &adapter->pdev->dev;
2931 struct flash_section_info *fsec = NULL;
2932 u32 img_offset, img_size, img_type;
2933 u16 img_optype, flash_optype;
2934 int status, i, filehdr_size;
2935 const u8 *p;
2936
2937 filehdr_size = sizeof(struct flash_file_hdr_g3);
2938 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2939 if (!fsec) {
2940 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2941 return -EINVAL;
2942 }
2943
2944retry_flash:
2945 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2946 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2947 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2948 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2949 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2950 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2951
2952 if (img_optype == 0xFFFF)
2953 continue;
2954
2955 if (flash_offset_support)
2956 flash_optype = OPTYPE_OFFSET_SPECIFIED;
2957 else
2958 flash_optype = img_optype;
2959
2960 /* Don't bother verifying CRC if an old FW image is being
2961 * flashed
2962 */
2963 if (old_fw_img)
2964 goto flash;
2965
2966 status = be_check_flash_crc(adapter, fw->data, img_offset,
2967 img_size, filehdr_size +
2968 img_hdrs_size, flash_optype,
2969 &crc_match);
2970 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2971 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2972 /* The current FW image on the card does not support
2973 * OFFSET based flashing. Retry using older mechanism
2974 * of OPTYPE based flashing
2975 */
2976 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2977 flash_offset_support = false;
2978 goto retry_flash;
2979 }
2980
2981 /* The current FW image on the card does not recognize
2982 * the new FLASH op_type. The FW download is partially
2983 * complete. Reboot the server now to enable FW image
2984 * to recognize the new FLASH op_type. To complete the
2985 * remaining process, download the same FW again after
2986 * the reboot.
2987 */
2988 dev_err(dev, "Flash incomplete. Reset the server\n");
2989 dev_err(dev, "Download FW image again after reset\n");
2990 return -EAGAIN;
2991 } else if (status) {
2992 dev_err(dev, "Could not get CRC for 0x%x region\n",
2993 img_optype);
2994 return -EFAULT;
2995 }
2996
2997 if (crc_match)
2998 continue;
2999
3000flash:
3001 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
3002 if (p + img_size > fw->data + fw->size)
3003 return -1;
3004
3005 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
3006 img_offset);
3007
3008 /* The current FW image on the card does not support OFFSET
3009 * based flashing. Retry using older mechanism of OPTYPE based
3010 * flashing
3011 */
3012 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
3013 flash_optype == OPTYPE_OFFSET_SPECIFIED) {
3014 flash_offset_support = false;
3015 goto retry_flash;
3016 }
3017
3018 /* For old FW images ignore ILLEGAL_FIELD error or errors on
3019 * UFI_DIR region
3020 */
3021 if (old_fw_img &&
3022 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
3023 (img_optype == OPTYPE_UFI_DIR &&
3024 base_status(status) == MCC_STATUS_FAILED))) {
3025 continue;
3026 } else if (status) {
3027 dev_err(dev, "Flashing section type 0x%x failed\n",
3028 img_type);
6b525782
SR		 3029
3030 switch (addl_status(status)) {
3031 case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3032 dev_err(dev,
3033 "Digital signature missing in FW\n");
3034 return -EINVAL;
3035 case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3036 dev_err(dev,
3037 "Invalid digital signature in FW\n");
3038 return -EINVAL;
3039 default:
3040 return -EFAULT;
3041 }
a23113b5
SR		 3042 }
3043 }
3044 return 0;
3045}
3046
3047int lancer_fw_download(struct be_adapter *adapter,
3048 const struct firmware *fw)
3049{
3050 struct device *dev = &adapter->pdev->dev;
3051 struct be_dma_mem flash_cmd;
3052 const u8 *data_ptr = NULL;
3053 u8 *dest_image_ptr = NULL;
3054 size_t image_size = 0;
3055 u32 chunk_size = 0;
3056 u32 data_written = 0;
3057 u32 offset = 0;
3058 int status = 0;
3059 u8 add_status = 0;
3060 u8 change_status;
3061
3062 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3063 dev_err(dev, "FW image size should be multiple of 4\n");
3064 return -EINVAL;
3065 }
3066
3067 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3068 + LANCER_FW_DOWNLOAD_CHUNK;
3069 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3070 &flash_cmd.dma, GFP_KERNEL);
3071 if (!flash_cmd.va)
3072 return -ENOMEM;
3073
3074 dest_image_ptr = flash_cmd.va +
3075 sizeof(struct lancer_cmd_req_write_object);
3076 image_size = fw->size;
3077 data_ptr = fw->data;
3078
3079 while (image_size) {
3080 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3081
3082 /* Copy the image chunk content. */
3083 memcpy(dest_image_ptr, data_ptr, chunk_size);
3084
3085 status = lancer_cmd_write_object(adapter, &flash_cmd,
3086 chunk_size, offset,
3087 LANCER_FW_DOWNLOAD_LOCATION,
3088 &data_written, &change_status,
3089 &add_status);
3090 if (status)
3091 break;
3092
3093 offset += data_written;
3094 data_ptr += data_written;
3095 image_size -= data_written;
3096 }
3097
3098 if (!status) {
3099 /* Commit the FW written */
3100 status = lancer_cmd_write_object(adapter, &flash_cmd,
3101 0, offset,
3102 LANCER_FW_DOWNLOAD_LOCATION,
3103 &data_written, &change_status,
3104 &add_status);
3105 }
3106
3107 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3108 if (status) {
3109 dev_err(dev, "Firmware load error\n");
3110 return be_cmd_status(status);
3111 }
3112
3113 dev_info(dev, "Firmware flashed successfully\n");
3114
3115 if (change_status == LANCER_FW_RESET_NEEDED) {
3116 dev_info(dev, "Resetting adapter to activate new FW\n");
3117 status = lancer_physdev_ctrl(adapter,
3118 PHYSDEV_CONTROL_FW_RESET_MASK);
3119 if (status) {
3120 dev_err(dev, "Adapter busy, could not reset FW\n");
3121 dev_err(dev, "Reboot server to activate new FW\n");
3122 }
3123 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3124 dev_info(dev, "Reboot server to activate new FW\n");
3125 }
3126
3127 return 0;
3128}
3129
3130/* Check if the flash image file is compatible with the adapter that
3131 * is being flashed.
3132 */
3133static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3134 struct flash_file_hdr_g3 *fhdr)
3135{
3136 if (!fhdr) {
3137 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3138 return false;
3139 }
3140
3141 /* First letter of the build version is used to identify
3142 * which chip this image file is meant for.
3143 */
3144 switch (fhdr->build[0]) {
3145 case BLD_STR_UFI_TYPE_SH:
3146 if (!skyhawk_chip(adapter))
3147 return false;
3148 break;
3149 case BLD_STR_UFI_TYPE_BE3:
3150 if (!BE3_chip(adapter))
3151 return false;
3152 break;
3153 case BLD_STR_UFI_TYPE_BE2:
3154 if (!BE2_chip(adapter))
3155 return false;
3156 break;
3157 default:
3158 return false;
3159 }
3160
3161 /* In BE3 FW images the "asic_type_rev" field doesn't track the
3162 * asic_rev of the chips it is compatible with.
3163 * When asic_type_rev is 0 the image is compatible only with
3164 * pre-BE3-R chips (asic_rev < 0x10)
3165 */
3166 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3167 return adapter->asic_rev < 0x10;
3168 else
3169 return (fhdr->asic_type_rev >= adapter->asic_rev);
3170}
3171
3172int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3173{
3174 struct device *dev = &adapter->pdev->dev;
3175 struct flash_file_hdr_g3 *fhdr3;
3176 struct image_hdr *img_hdr_ptr;
3177 int status = 0, i, num_imgs;
3178 struct be_dma_mem flash_cmd;
3179
3180 fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3181 if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3182 dev_err(dev, "Flash image is not compatible with adapter\n");
3183 return -EINVAL;
3184 }
3185
3186 flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3187 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3188 GFP_KERNEL);
3189 if (!flash_cmd.va)
3190 return -ENOMEM;
3191
3192 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3193 for (i = 0; i < num_imgs; i++) {
3194 img_hdr_ptr = (struct image_hdr *)(fw->data +
3195 (sizeof(struct flash_file_hdr_g3) +
3196 i * sizeof(struct image_hdr)));
3197 if (!BE2_chip(adapter) &&
3198 le32_to_cpu(img_hdr_ptr->imageid) != 1)
3199 continue;
3200
3201 if (skyhawk_chip(adapter))
3202 status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3203 num_imgs);
3204 else
3205 status = be_flash_BEx(adapter, fw, &flash_cmd,
3206 num_imgs);
3207 }
3208
3209 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3210 if (!status)
3211 dev_info(dev, "Firmware flashed successfully\n");
3212
3213 return status;
3214}
3215
c196b02c 3216int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 3217 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 3218{
3219 struct be_mcc_wrb *wrb;
3220 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 3221 int status;
3222
b7172414 3223 mutex_lock(&adapter->mcc_lock);
71d8d1b5
AK		 3224
3225 wrb = wrb_from_mccq(adapter);
3226 if (!wrb) {
3227 status = -EBUSY;
3228 goto err;
3229 }
3230 req = nonemb_cmd->va;
71d8d1b5 3231
106df1e3 3232 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 3233 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3234 wrb, nonemb_cmd);
71d8d1b5
AK		 3235 memcpy(req->magic_mac, mac, ETH_ALEN);
3236
71d8d1b5
AK		 3237 status = be_mcc_notify_wait(adapter);
3238
3239err:
b7172414 3240 mutex_unlock(&adapter->mcc_lock);
71d8d1b5
AK		 3241 return status;
3242}
ff33a6e2 3243
fced9999
SB		 3244int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3245 u8 loopback_type, u8 enable)
3246{
3247 struct be_mcc_wrb *wrb;
3248 struct be_cmd_req_set_lmode *req;
3249 int status;
3250
2e365b1b
SK		 3251 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3252 CMD_SUBSYSTEM_LOWLEVEL))
3253 return -EPERM;
3254
b7172414 3255 mutex_lock(&adapter->mcc_lock);
fced9999
SB		 3256
3257 wrb = wrb_from_mccq(adapter);
3258 if (!wrb) {
3259 status = -EBUSY;
9c855975 3260 goto err_unlock;
fced9999
SB		 3261 }
3262
3263 req = embedded_payload(wrb);
3264
106df1e3 3265 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3266 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3267 wrb, NULL);
fced9999
SB		 3268
3269 req->src_port = port_num;
3270 req->dest_port = port_num;
3271 req->loopback_type = loopback_type;
3272 req->loopback_state = enable;
3273
9c855975
SR		 3274 status = be_mcc_notify(adapter);
3275 if (status)
3276 goto err_unlock;
3277
b7172414 3278 mutex_unlock(&adapter->mcc_lock);
9c855975
SR		 3279
3280 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3281 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3282 status = -ETIMEDOUT;
3283
3284 return status;
3285
3286err_unlock:
b7172414 3287 mutex_unlock(&adapter->mcc_lock);
fced9999
SB		 3288 return status;
3289}
3290
ff33a6e2 3291int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 3292 u32 loopback_type, u32 pkt_size, u32 num_pkts,
3293 u64 pattern)
ff33a6e2
S		 3294{
3295 struct be_mcc_wrb *wrb;
3296 struct be_cmd_req_loopback_test *req;
5eeff635 3297 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 3298 int status;
3299
2e365b1b
SK		 3300 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3301 CMD_SUBSYSTEM_LOWLEVEL))
3302 return -EPERM;
3303
b7172414 3304 mutex_lock(&adapter->mcc_lock);
ff33a6e2
S		 3305
3306 wrb = wrb_from_mccq(adapter);
3307 if (!wrb) {
3308 status = -EBUSY;
3309 goto err;
3310 }
3311
3312 req = embedded_payload(wrb);
3313
106df1e3 3314 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3315 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3316 NULL);
ff33a6e2 3317
5eeff635 3318 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 3319 req->pattern = cpu_to_le64(pattern);
3320 req->src_port = cpu_to_le32(port_num);
3321 req->dest_port = cpu_to_le32(port_num);
3322 req->pkt_size = cpu_to_le32(pkt_size);
3323 req->num_pkts = cpu_to_le32(num_pkts);
3324 req->loopback_type = cpu_to_le32(loopback_type);
3325
efaa408e
SR		 3326 status = be_mcc_notify(adapter);
3327 if (status)
3328 goto err;
5eeff635 3329
b7172414 3330 mutex_unlock(&adapter->mcc_lock);
ff33a6e2 3331
5eeff635
SR		 3332 wait_for_completion(&adapter->et_cmd_compl);
3333 resp = embedded_payload(wrb);
3334 status = le32_to_cpu(resp->status);
3335
3336 return status;
ff33a6e2 3337err:
b7172414 3338 mutex_unlock(&adapter->mcc_lock);
ff33a6e2
S		 3339 return status;
3340}
3341
3342int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 3343 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 3344{
3345 struct be_mcc_wrb *wrb;
3346 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 3347 int status;
3348 int i, j = 0;
3349
2e365b1b
SK		 3350 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3351 CMD_SUBSYSTEM_LOWLEVEL))
3352 return -EPERM;
3353
b7172414 3354 mutex_lock(&adapter->mcc_lock);
ff33a6e2
S		 3355
3356 wrb = wrb_from_mccq(adapter);
3357 if (!wrb) {
3358 status = -EBUSY;
3359 goto err;
3360 }
3361 req = cmd->va;
106df1e3 3362 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3363 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3364 cmd);
ff33a6e2
S		 3365
3366 req->pattern = cpu_to_le64(pattern);
3367 req->byte_count = cpu_to_le32(byte_cnt);
3368 for (i = 0; i < byte_cnt; i++) {
3369 req->snd_buff[i] = (u8)(pattern >> (j*8));
3370 j++;
3371 if (j > 7)
3372 j = 0;
3373 }
3374
3375 status = be_mcc_notify_wait(adapter);
3376
3377 if (!status) {
3378 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 3379
ff33a6e2
S		 3380 resp = cmd->va;
3381 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
cd3307aa 3382 resp->snd_err) {
ff33a6e2
S		 3383 status = -1;
3384 }
3385 }
3386
3387err:
b7172414 3388 mutex_unlock(&adapter->mcc_lock);
ff33a6e2
S		 3389 return status;
3390}
368c0ca2 3391
c196b02c 3392int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 3393 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 3394{
3395 struct be_mcc_wrb *wrb;
3396 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 3397 int status;
3398
b7172414 3399 mutex_lock(&adapter->mcc_lock);
368c0ca2
SB		 3400
3401 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 3402 if (!wrb) {
3403 status = -EBUSY;
3404 goto err;
3405 }
368c0ca2 3406 req = nonemb_cmd->va;
368c0ca2 3407
106df1e3 3408 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3409 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3410 nonemb_cmd);
368c0ca2
SB		 3411
3412 status = be_mcc_notify_wait(adapter);
3413
e45ff01d 3414err:
b7172414 3415 mutex_unlock(&adapter->mcc_lock);
368c0ca2
SB		 3416 return status;
3417}
ee3cb629 3418
42f11cf2 3419int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 3420{
3421 struct be_mcc_wrb *wrb;
3422 struct be_cmd_req_get_phy_info *req;
306f1348 3423 struct be_dma_mem cmd;
ee3cb629
AK		 3424 int status;
3425
f25b119c
PR		 3426 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3427 CMD_SUBSYSTEM_COMMON))
3428 return -EPERM;
3429
b7172414 3430 mutex_lock(&adapter->mcc_lock);
ee3cb629
AK		 3431
3432 wrb = wrb_from_mccq(adapter);
3433 if (!wrb) {
3434 status = -EBUSY;
3435 goto err;
3436 }
306f1348 3437 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
e51000db
SB		 3438 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3439 GFP_ATOMIC);
306f1348
SP		 3440 if (!cmd.va) {
3441 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3442 status = -ENOMEM;
3443 goto err;
3444 }
ee3cb629 3445
306f1348 3446 req = cmd.va;
ee3cb629 3447
106df1e3 3448 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3449 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3450 wrb, &cmd);
ee3cb629
AK		 3451
3452 status = be_mcc_notify_wait(adapter);
306f1348
SP		 3453 if (!status) {
3454 struct be_phy_info *resp_phy_info =
3455 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 3456
42f11cf2
AK		 3457 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3458 adapter->phy.interface_type =
306f1348 3459 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 3460 adapter->phy.auto_speeds_supported =
3461 le16_to_cpu(resp_phy_info->auto_speeds_supported);
3462 adapter->phy.fixed_speeds_supported =
3463 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3464 adapter->phy.misc_params =
3465 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 3466
3467 if (BE2_chip(adapter)) {
3468 adapter->phy.fixed_speeds_supported =
3469 BE_SUPPORTED_SPEED_10GBPS |
3470 BE_SUPPORTED_SPEED_1GBPS;
3471 }
306f1348 3472 }
e51000db 3473 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
ee3cb629 3474err:
b7172414 3475 mutex_unlock(&adapter->mcc_lock);
ee3cb629
AK		 3476 return status;
3477}
e1d18735 3478
bc0ee163 3479static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
e1d18735
AK		 3480{
3481 struct be_mcc_wrb *wrb;
3482 struct be_cmd_req_set_qos *req;
3483 int status;
3484
b7172414 3485 mutex_lock(&adapter->mcc_lock);
e1d18735
AK		 3486
3487 wrb = wrb_from_mccq(adapter);
3488 if (!wrb) {
3489 status = -EBUSY;
3490 goto err;
3491 }
3492
3493 req = embedded_payload(wrb);
3494
106df1e3 3495 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 3496 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 3497
3498 req->hdr.domain = domain;
6bff57a7
AK		 3499 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3500 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 3501
3502 status = be_mcc_notify_wait(adapter);
3503
3504err:
b7172414 3505 mutex_unlock(&adapter->mcc_lock);
e1d18735
AK		 3506 return status;
3507}
9e1453c5
AK		 3508
3509int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3510{
3511 struct be_mcc_wrb *wrb;
3512 struct be_cmd_req_cntl_attribs *req;
3513 struct be_cmd_resp_cntl_attribs *resp;
a155a5db 3514 int status, i;
9e1453c5
AK		 3515 int payload_len = max(sizeof(*req), sizeof(*resp));
3516 struct mgmt_controller_attrib *attribs;
3517 struct be_dma_mem attribs_cmd;
a155a5db 3518 u32 *serial_num;
9e1453c5 3519
d98ef50f
SR		 3520 if (mutex_lock_interruptible(&adapter->mbox_lock))
3521 return -1;
3522
9e1453c5
AK		 3523 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3524 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
e51000db
SB		 3525 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3526 attribs_cmd.size,
3527 &attribs_cmd.dma, GFP_ATOMIC);
9e1453c5 3528 if (!attribs_cmd.va) {
a2cc4e0b 3529 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3530 status = -ENOMEM;
3531 goto err;
9e1453c5
AK		 3532 }
3533
9e1453c5
AK		 3534 wrb = wrb_from_mbox(adapter);
3535 if (!wrb) {
3536 status = -EBUSY;
3537 goto err;
3538 }
3539 req = attribs_cmd.va;
9e1453c5 3540
106df1e3 3541 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3542 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3543 wrb, &attribs_cmd);
9e1453c5
AK		 3544
3545 status = be_mbox_notify_wait(adapter);
3546 if (!status) {
43d620c8 3547 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5 3548 adapter->hba_port_num = attribs->hba_attribs.phy_port;
a155a5db
SB		 3549 serial_num = attribs->hba_attribs.controller_serial_number;
3550 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3551 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3552 (BIT_MASK(16) - 1);
6ee080bb
SB		 3553 /* For BEx, since GET_FUNC_CONFIG command is not
3554 * supported, we read funcnum here as a workaround.
3555 */
3556 if (BEx_chip(adapter))
3557 adapter->pf_num = attribs->hba_attribs.pci_funcnum;
9e1453c5
AK		 3558 }
3559
3560err:
3561 mutex_unlock(&adapter->mbox_lock);
d98ef50f 3562 if (attribs_cmd.va)
e51000db
SB		 3563 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3564 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 3565 return status;
3566}
2e588f84
SP		 3567
3568/* Uses mbox */
2dc1deb6 3569int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 3570{
3571 struct be_mcc_wrb *wrb;
3572 struct be_cmd_req_set_func_cap *req;
3573 int status;
3574
3575 if (mutex_lock_interruptible(&adapter->mbox_lock))
3576 return -1;
3577
3578 wrb = wrb_from_mbox(adapter);
3579 if (!wrb) {
3580 status = -EBUSY;
3581 goto err;
3582 }
3583
3584 req = embedded_payload(wrb);
3585
106df1e3 3586 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3587 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3588 sizeof(*req), wrb, NULL);
2e588f84
SP		 3589
3590 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3591 CAPABILITY_BE3_NATIVE_ERX_API);
3592 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3593
3594 status = be_mbox_notify_wait(adapter);
3595 if (!status) {
3596 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 3597
2e588f84
SP		 3598 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3599 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 3600 if (!adapter->be3_native)
3601 dev_warn(&adapter->pdev->dev,
3602 "adapter not in advanced mode\n");
2e588f84
SP		 3603 }
3604err:
3605 mutex_unlock(&adapter->mbox_lock);
3606 return status;
3607}
590c391d 3608
f25b119c
PR		 3609/* Get privilege(s) for a function */
3610int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3611 u32 domain)
3612{
3613 struct be_mcc_wrb *wrb;
3614 struct be_cmd_req_get_fn_privileges *req;
3615 int status;
3616
b7172414 3617 mutex_lock(&adapter->mcc_lock);
f25b119c
PR		 3618
3619 wrb = wrb_from_mccq(adapter);
3620 if (!wrb) {
3621 status = -EBUSY;
3622 goto err;
3623 }
3624
3625 req = embedded_payload(wrb);
3626
3627 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3628 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3629 wrb, NULL);
3630
3631 req->hdr.domain = domain;
3632
3633 status = be_mcc_notify_wait(adapter);
3634 if (!status) {
3635 struct be_cmd_resp_get_fn_privileges *resp =
3636 embedded_payload(wrb);
03d28ffe 3637
f25b119c 3638 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 3639
3640 /* In UMC mode FW does not return right privileges.
3641 * Override with correct privilege equivalent to PF.
3642 */
3643 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3644 be_physfn(adapter))
3645 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 3646 }
3647
3648err:
b7172414 3649 mutex_unlock(&adapter->mcc_lock);
f25b119c
PR		 3650 return status;
3651}
3652
04a06028
SP		 3653/* Set privilege(s) for a function */
3654int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3655 u32 domain)
3656{
3657 struct be_mcc_wrb *wrb;
3658 struct be_cmd_req_set_fn_privileges *req;
3659 int status;
3660
b7172414 3661 mutex_lock(&adapter->mcc_lock);
04a06028
SP		 3662
3663 wrb = wrb_from_mccq(adapter);
3664 if (!wrb) {
3665 status = -EBUSY;
3666 goto err;
3667 }
3668
3669 req = embedded_payload(wrb);
3670 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3671 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3672 wrb, NULL);
3673 req->hdr.domain = domain;
3674 if (lancer_chip(adapter))
3675 req->privileges_lancer = cpu_to_le32(privileges);
3676 else
3677 req->privileges = cpu_to_le32(privileges);
3678
3679 status = be_mcc_notify_wait(adapter);
3680err:
b7172414 3681 mutex_unlock(&adapter->mcc_lock);
04a06028
SP		 3682 return status;
3683}
3684
5a712c13
SP		 3685/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3686 * pmac_id_valid: false => pmac_id or MAC address is requested.
3687 * If pmac_id is returned, pmac_id_valid is returned as true
3688 */
1578e777 3689int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 3690 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3691 u8 domain)
590c391d
PR		 3692{
3693 struct be_mcc_wrb *wrb;
3694 struct be_cmd_req_get_mac_list *req;
3695 int status;
3696 int mac_count;
e5e1ee89
PR		 3697 struct be_dma_mem get_mac_list_cmd;
3698 int i;
3699
3700 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3701 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
e51000db
SB		 3702 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3703 get_mac_list_cmd.size,
3704 &get_mac_list_cmd.dma,
3705 GFP_ATOMIC);
e5e1ee89
PR		 3706
3707 if (!get_mac_list_cmd.va) {
3708 dev_err(&adapter->pdev->dev,
a2cc4e0b 3709 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 3710 return -ENOMEM;
3711 }
590c391d 3712
b7172414 3713 mutex_lock(&adapter->mcc_lock);
590c391d
PR		 3714
3715 wrb = wrb_from_mccq(adapter);
3716 if (!wrb) {
3717 status = -EBUSY;
e5e1ee89 3718 goto out;
590c391d 3719 }
e5e1ee89
PR		 3720
3721 req = get_mac_list_cmd.va;
590c391d
PR		 3722
3723 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 3724 OPCODE_COMMON_GET_MAC_LIST,
3725 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 3726 req->hdr.domain = domain;
e5e1ee89 3727 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 3728 if (*pmac_id_valid) {
3729 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 3730 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 3731 req->perm_override = 0;
3732 } else {
3733 req->perm_override = 1;
3734 }
590c391d
PR		 3735
3736 status = be_mcc_notify_wait(adapter);
3737 if (!status) {
3738 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 3739 get_mac_list_cmd.va;
5a712c13
SP		 3740
3741 if (*pmac_id_valid) {
3742 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3743 ETH_ALEN);
3744 goto out;
3745 }
3746
e5e1ee89
PR		 3747 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3748 /* Mac list returned could contain one or more active mac_ids
dbedd44e 3749 * or one or more true or pseudo permanent mac addresses.
1578e777
PR		 3750 * If an active mac_id is present, return first active mac_id
3751 * found.
e5e1ee89 3752 */
590c391d 3753 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3754 struct get_list_macaddr *mac_entry;
3755 u16 mac_addr_size;
3756 u32 mac_id;
3757
3758 mac_entry = &resp->macaddr_list[i];
3759 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3760 /* mac_id is a 32 bit value and mac_addr size
3761 * is 6 bytes
3762 */
3763 if (mac_addr_size == sizeof(u32)) {
5a712c13 3764 *pmac_id_valid = true;
e5e1ee89
PR		 3765 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3766 *pmac_id = le32_to_cpu(mac_id);
3767 goto out;
590c391d 3768 }
590c391d 3769 }
1578e777 3770 /* If no active mac_id found, return first mac addr */
5a712c13 3771 *pmac_id_valid = false;
e5e1ee89 3772 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3773 ETH_ALEN);
590c391d
PR		 3774 }
3775
e5e1ee89 3776out:
b7172414 3777 mutex_unlock(&adapter->mcc_lock);
e51000db
SB		 3778 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3779 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3780 return status;
3781}
3782
a2cc4e0b
SP		 3783int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3784 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3785{
b188f090
SR		 3786 if (!active)
3787 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3788 if_handle, domain);
3175d8c2 3789 if (BEx_chip(adapter))
5a712c13 3790 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3791 if_handle, curr_pmac_id);
3175d8c2
SP		 3792 else
3793 /* Fetch the MAC address using pmac_id */
3794 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3795 &curr_pmac_id,
3796 if_handle, domain);
5a712c13
SP		 3797}
3798
95046b92
SP		 3799int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3800{
3801 int status;
3802 bool pmac_valid = false;
3803
c7bf7169 3804 eth_zero_addr(mac);
95046b92 3805
3175d8c2
SP		 3806 if (BEx_chip(adapter)) {
3807 if (be_physfn(adapter))
3808 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3809 0);
3810 else
3811 status = be_cmd_mac_addr_query(adapter, mac, false,
3812 adapter->if_handle, 0);
3813 } else {
95046b92 3814 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3815 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3816 }
3817
95046b92
SP		 3818 return status;
3819}
3820
590c391d
PR		 3821/* Uses synchronous MCCQ */
3822int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3823 u8 mac_count, u32 domain)
3824{
3825 struct be_mcc_wrb *wrb;
3826 struct be_cmd_req_set_mac_list *req;
3827 int status;
3828 struct be_dma_mem cmd;
3829
3830 memset(&cmd, 0, sizeof(struct be_dma_mem));
3831 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
e51000db
SB		 3832 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3833 GFP_KERNEL);
d0320f75 3834 if (!cmd.va)
590c391d 3835 return -ENOMEM;
590c391d 3836
b7172414 3837 mutex_lock(&adapter->mcc_lock);
590c391d
PR		 3838
3839 wrb = wrb_from_mccq(adapter);
3840 if (!wrb) {
3841 status = -EBUSY;
3842 goto err;
3843 }
3844
3845 req = cmd.va;
3846 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3847 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3848 wrb, &cmd);
590c391d
PR		 3849
3850 req->hdr.domain = domain;
3851 req->mac_count = mac_count;
3852 if (mac_count)
3853 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3854
3855 status = be_mcc_notify_wait(adapter);
3856
3857err:
a2cc4e0b 3858 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
b7172414 3859 mutex_unlock(&adapter->mcc_lock);
590c391d
PR		 3860 return status;
3861}
4762f6ce 3862
3175d8c2
SP		 3863/* Wrapper to delete any active MACs and provision the new mac.
3864 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3865 * current list are active.
3866 */
3867int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3868{
3869 bool active_mac = false;
3870 u8 old_mac[ETH_ALEN];
3871 u32 pmac_id;
3872 int status;
3873
3874 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3875 &pmac_id, if_id, dom);
3876
3175d8c2
SP		 3877 if (!status && active_mac)
3878 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3879
3880 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3881}
3882
f1f3ee1b 3883int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
e7bcbd7b 3884 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
f1f3ee1b
AK		 3885{
3886 struct be_mcc_wrb *wrb;
3887 struct be_cmd_req_set_hsw_config *req;
3888 void *ctxt;
3889 int status;
3890
884476be
SK		 3891 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3892 CMD_SUBSYSTEM_COMMON))
3893 return -EPERM;
3894
b7172414 3895 mutex_lock(&adapter->mcc_lock);
f1f3ee1b
AK		 3896
3897 wrb = wrb_from_mccq(adapter);
3898 if (!wrb) {
3899 status = -EBUSY;
3900 goto err;
3901 }
3902
3903 req = embedded_payload(wrb);
3904 ctxt = &req->context;
3905
3906 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3907 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3908 NULL);
f1f3ee1b
AK		 3909
3910 req->hdr.domain = domain;
3911 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3912 if (pvid) {
3913 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3914 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3915 }
884476be 3916 if (hsw_mode) {
a77dcb8c
AK		 3917 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3918 ctxt, adapter->hba_port_num);
3919 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3920 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3921 ctxt, hsw_mode);
3922 }
f1f3ee1b 3923
e7bcbd7b
KA		 3924 /* Enable/disable both mac and vlan spoof checking */
3925 if (!BEx_chip(adapter) && spoofchk) {
3926 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3927 ctxt, spoofchk);
3928 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3929 ctxt, spoofchk);
3930 }
3931
f1f3ee1b
AK		 3932 be_dws_cpu_to_le(req->context, sizeof(req->context));
3933 status = be_mcc_notify_wait(adapter);
3934
3935err:
b7172414 3936 mutex_unlock(&adapter->mcc_lock);
f1f3ee1b
AK		 3937 return status;
3938}
3939
3940/* Get Hyper switch config */
3941int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
e7bcbd7b 3942 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
f1f3ee1b
AK		 3943{
3944 struct be_mcc_wrb *wrb;
3945 struct be_cmd_req_get_hsw_config *req;
3946 void *ctxt;
3947 int status;
3948 u16 vid;
3949
b7172414 3950 mutex_lock(&adapter->mcc_lock);
f1f3ee1b
AK		 3951
3952 wrb = wrb_from_mccq(adapter);
3953 if (!wrb) {
3954 status = -EBUSY;
3955 goto err;
3956 }
3957
3958 req = embedded_payload(wrb);
3959 ctxt = &req->context;
3960
3961 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3962 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3963 NULL);
f1f3ee1b
AK		 3964
3965 req->hdr.domain = domain;
a77dcb8c
AK		 3966 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3967 ctxt, intf_id);
f1f3ee1b 3968 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3969
2c07c1d7 3970 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3971 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3972 ctxt, adapter->hba_port_num);
3973 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3974 }
f1f3ee1b
AK		 3975 be_dws_cpu_to_le(req->context, sizeof(req->context));
3976
3977 status = be_mcc_notify_wait(adapter);
3978 if (!status) {
3979 struct be_cmd_resp_get_hsw_config *resp =
3980 embedded_payload(wrb);
03d28ffe 3981
a2cc4e0b 3982 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3983 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3984 pvid, &resp->context);
a77dcb8c
AK		 3985 if (pvid)
3986 *pvid = le16_to_cpu(vid);
3987 if (mode)
3988 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3989 port_fwd_type, &resp->context);
e7bcbd7b
KA		 3990 if (spoofchk)
3991 *spoofchk =
3992 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3993 spoofchk, &resp->context);
f1f3ee1b
AK		 3994 }
3995
3996err:
b7172414 3997 mutex_unlock(&adapter->mcc_lock);
f1f3ee1b
AK		 3998 return status;
3999}
4000
f7062ee5
SP		 4001static bool be_is_wol_excluded(struct be_adapter *adapter)
4002{
4003 struct pci_dev *pdev = adapter->pdev;
4004
18c57c74 4005 if (be_virtfn(adapter))
f7062ee5
SP		 4006 return true;
4007
4008 switch (pdev->subsystem_device) {
4009 case OC_SUBSYS_DEVICE_ID1:
4010 case OC_SUBSYS_DEVICE_ID2:
4011 case OC_SUBSYS_DEVICE_ID3:
4012 case OC_SUBSYS_DEVICE_ID4:
4013 return true;
4014 default:
4015 return false;
4016 }
4017}
4018
4762f6ce
AK		 4019int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
4020{
4021 struct be_mcc_wrb *wrb;
4022 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 4023 int status = 0;
4762f6ce
AK		 4024 struct be_dma_mem cmd;
4025
f25b119c
PR		 4026 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4027 CMD_SUBSYSTEM_ETH))
4028 return -EPERM;
4029
76a9e08e
SR		 4030 if (be_is_wol_excluded(adapter))
4031 return status;
4032
d98ef50f
SR		 4033 if (mutex_lock_interruptible(&adapter->mbox_lock))
4034 return -1;
4035
4762f6ce
AK		 4036 memset(&cmd, 0, sizeof(struct be_dma_mem));
4037 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
e51000db
SB		 4038 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4039 GFP_ATOMIC);
4762f6ce 4040 if (!cmd.va) {
a2cc4e0b 4041 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 4042 status = -ENOMEM;
4043 goto err;
4762f6ce
AK		 4044 }
4045
4762f6ce
AK		 4046 wrb = wrb_from_mbox(adapter);
4047 if (!wrb) {
4048 status = -EBUSY;
4049 goto err;
4050 }
4051
4052 req = cmd.va;
4053
4054 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4055 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 4056 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 4057
4058 req->hdr.version = 1;
4059 req->query_options = BE_GET_WOL_CAP;
4060
4061 status = be_mbox_notify_wait(adapter);
4062 if (!status) {
4063 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 4064
504fbf1e 4065 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 4066
4762f6ce 4067 adapter->wol_cap = resp->wol_settings;
45f13df7
SB		 4068
4069 /* Non-zero macaddr indicates WOL is enabled */
4070 if (adapter->wol_cap & BE_WOL_CAP &&
4071 !is_zero_ether_addr(resp->magic_mac))
76a9e08e 4072 adapter->wol_en = true;
4762f6ce
AK		 4073 }
4074err:
4075 mutex_unlock(&adapter->mbox_lock);
d98ef50f 4076 if (cmd.va)
e51000db
SB		 4077 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4078 cmd.dma);
4762f6ce 4079 return status;
941a77d5
SK		 4080
4081}
baaa08d1
VV		 4082
4083int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4084{
4085 struct be_dma_mem extfat_cmd;
4086 struct be_fat_conf_params *cfgs;
4087 int status;
4088 int i, j;
4089
4090 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4091 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
e51000db
SB		 4092 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4093 extfat_cmd.size, &extfat_cmd.dma,
4094 GFP_ATOMIC);
baaa08d1
VV		 4095 if (!extfat_cmd.va)
4096 return -ENOMEM;
4097
4098 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4099 if (status)
4100 goto err;
4101
4102 cfgs = (struct be_fat_conf_params *)
4103 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4104 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4105 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 4106
baaa08d1
VV		 4107 for (j = 0; j < num_modes; j++) {
4108 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4109 cfgs->module[i].trace_lvl[j].dbg_lvl =
4110 cpu_to_le32(level);
4111 }
4112 }
4113
4114 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4115err:
e51000db
SB		 4116 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4117 extfat_cmd.dma);
baaa08d1
VV		 4118 return status;
4119}
4120
4121int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4122{
4123 struct be_dma_mem extfat_cmd;
4124 struct be_fat_conf_params *cfgs;
4125 int status, j;
4126 int level = 0;
4127
4128 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4129 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
e51000db
SB		 4130 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4131 extfat_cmd.size, &extfat_cmd.dma,
4132 GFP_ATOMIC);
baaa08d1
VV		 4133
4134 if (!extfat_cmd.va) {
4135 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4136 __func__);
4137 goto err;
4138 }
4139
4140 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4141 if (!status) {
4142 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4143 sizeof(struct be_cmd_resp_hdr));
03d28ffe 4144
baaa08d1
VV		 4145 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4146 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4147 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4148 }
4149 }
e51000db
SB		 4150 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4151 extfat_cmd.dma);
baaa08d1
VV		 4152err:
4153 return level;
4154}
4155
941a77d5
SK		 4156int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4157 struct be_dma_mem *cmd)
4158{
4159 struct be_mcc_wrb *wrb;
4160 struct be_cmd_req_get_ext_fat_caps *req;
4161 int status;
4162
62259ac4
SK		 4163 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4164 CMD_SUBSYSTEM_COMMON))
4165 return -EPERM;
4166
941a77d5
SK		 4167 if (mutex_lock_interruptible(&adapter->mbox_lock))
4168 return -1;
4169
4170 wrb = wrb_from_mbox(adapter);
4171 if (!wrb) {
4172 status = -EBUSY;
4173 goto err;
4174 }
4175
4176 req = cmd->va;
4177 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
62259ac4 4178 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
941a77d5
SK		 4179 cmd->size, wrb, cmd);
4180 req->parameter_type = cpu_to_le32(1);
4181
4182 status = be_mbox_notify_wait(adapter);
4183err:
4184 mutex_unlock(&adapter->mbox_lock);
4185 return status;
4186}
4187
4188int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4189 struct be_dma_mem *cmd,
4190 struct be_fat_conf_params *configs)
4191{
4192 struct be_mcc_wrb *wrb;
4193 struct be_cmd_req_set_ext_fat_caps *req;
4194 int status;
4195
b7172414 4196 mutex_lock(&adapter->mcc_lock);
941a77d5
SK		 4197
4198 wrb = wrb_from_mccq(adapter);
4199 if (!wrb) {
4200 status = -EBUSY;
4201 goto err;
4202 }
4203
4204 req = cmd->va;
4205 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4206 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
62259ac4 4207 OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES,
941a77d5
SK		 4208 cmd->size, wrb, cmd);
4209
4210 status = be_mcc_notify_wait(adapter);
4211err:
b7172414 4212 mutex_unlock(&adapter->mcc_lock);
941a77d5 4213 return status;
4762f6ce 4214}
6a4ab669 4215
21252377 4216int be_cmd_query_port_name(struct be_adapter *adapter)
b4e32a71 4217{
b4e32a71 4218 struct be_cmd_req_get_port_name *req;
21252377 4219 struct be_mcc_wrb *wrb;
b4e32a71
PR		 4220 int status;
4221
21252377
VV		 4222 if (mutex_lock_interruptible(&adapter->mbox_lock))
4223 return -1;
b4e32a71 4224
21252377 4225 wrb = wrb_from_mbox(adapter);
b4e32a71
PR		 4226 req = embedded_payload(wrb);
4227
4228 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4229 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4230 NULL);
21252377
VV		 4231 if (!BEx_chip(adapter))
4232 req->hdr.version = 1;
b4e32a71 4233
21252377 4234 status = be_mbox_notify_wait(adapter);
b4e32a71
PR		 4235 if (!status) {
4236 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 4237
21252377 4238 adapter->port_name = resp->port_name[adapter->hba_port_num];
b4e32a71 4239 } else {
21252377 4240 adapter->port_name = adapter->hba_port_num + '0';
b4e32a71 4241 }
21252377
VV		 4242
4243 mutex_unlock(&adapter->mbox_lock);
b4e32a71
PR		 4244 return status;
4245}
4246
980df249
SR		 4247/* When more than 1 NIC descriptor is present in the descriptor list,
4248 * the caller must specify the pf_num to obtain the NIC descriptor
4249 * corresponding to its pci function.
4250 * get_vft must be true when the caller wants the VF-template desc of the
4251 * PF-pool.
4252 * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4253 * that only it's NIC descriptor is present in the descriptor list.
4254 */
10cccf60 4255static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
980df249 4256 bool get_vft, u8 pf_num)
abb93951 4257{
150d58c7 4258 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 4259 struct be_nic_res_desc *nic;
abb93951
PR		 4260 int i;
4261
4262 for (i = 0; i < desc_count; i++) {
150d58c7 4263 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 4264 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4265 nic = (struct be_nic_res_desc *)hdr;
980df249
SR		 4266
4267 if ((pf_num == PF_NUM_IGNORE ||
4268 nic->pf_num == pf_num) &&
4269 (!get_vft || nic->flags & BIT(VFT_SHIFT)))
10cccf60
VV		 4270 return nic;
4271 }
150d58c7
VV		 4272 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4273 hdr = (void *)hdr + hdr->desc_len;
abb93951 4274 }
150d58c7
VV		 4275 return NULL;
4276}
4277
980df249
SR		 4278static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4279 u8 pf_num)
10cccf60 4280{
980df249 4281 return be_get_nic_desc(buf, desc_count, true, pf_num);
10cccf60
VV		 4282}
4283
980df249
SR		 4284static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4285 u8 pf_num)
10cccf60 4286{
980df249 4287 return be_get_nic_desc(buf, desc_count, false, pf_num);
10cccf60
VV		 4288}
4289
980df249
SR		 4290static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4291 u8 pf_num)
150d58c7
VV		 4292{
4293 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4294 struct be_pcie_res_desc *pcie;
4295 int i;
4296
4297 for (i = 0; i < desc_count; i++) {
980df249
SR		 4298 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4299 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4300 pcie = (struct be_pcie_res_desc *)hdr;
4301 if (pcie->pf_num == pf_num)
150d58c7
VV		 4302 return pcie;
4303 }
abb93951 4304
150d58c7
VV		 4305 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4306 hdr = (void *)hdr + hdr->desc_len;
4307 }
950e2958 4308 return NULL;
abb93951
PR		 4309}
4310
f93f160b
VV		 4311static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4312{
4313 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4314 int i;
4315
4316 for (i = 0; i < desc_count; i++) {
4317 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4318 return (struct be_port_res_desc *)hdr;
4319
4320 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4321 hdr = (void *)hdr + hdr->desc_len;
4322 }
4323 return NULL;
4324}
4325
92bf14ab
SP		 4326static void be_copy_nic_desc(struct be_resources *res,
4327 struct be_nic_res_desc *desc)
4328{
4329 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4330 res->max_vlans = le16_to_cpu(desc->vlan_count);
4331 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4332 res->max_tx_qs = le16_to_cpu(desc->txq_count);
4333 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4334 res->max_rx_qs = le16_to_cpu(desc->rq_count);
4335 res->max_evt_qs = le16_to_cpu(desc->eq_count);
f2858738
VV		 4336 res->max_cq_count = le16_to_cpu(desc->cq_count);
4337 res->max_iface_count = le16_to_cpu(desc->iface_count);
4338 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
92bf14ab
SP		 4339 /* Clear flags that driver is not interested in */
4340 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4341 BE_IF_CAP_FLAGS_WANT;
92bf14ab
SP		 4342}
4343
abb93951 4344/* Uses Mbox */
92bf14ab 4345int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 4346{
4347 struct be_mcc_wrb *wrb;
4348 struct be_cmd_req_get_func_config *req;
4349 int status;
4350 struct be_dma_mem cmd;
4351
d98ef50f
SR		 4352 if (mutex_lock_interruptible(&adapter->mbox_lock))
4353 return -1;
4354
abb93951
PR		 4355 memset(&cmd, 0, sizeof(struct be_dma_mem));
4356 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
e51000db
SB		 4357 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4358 GFP_ATOMIC);
abb93951
PR		 4359 if (!cmd.va) {
4360 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 4361 status = -ENOMEM;
4362 goto err;
abb93951 4363 }
abb93951
PR		 4364
4365 wrb = wrb_from_mbox(adapter);
4366 if (!wrb) {
4367 status = -EBUSY;
4368 goto err;
4369 }
4370
4371 req = cmd.va;
4372
4373 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4374 OPCODE_COMMON_GET_FUNC_CONFIG,
4375 cmd.size, wrb, &cmd);
4376
28710c55
KA		 4377 if (skyhawk_chip(adapter))
4378 req->hdr.version = 1;
4379
abb93951
PR		 4380 status = be_mbox_notify_wait(adapter);
4381 if (!status) {
4382 struct be_cmd_resp_get_func_config *resp = cmd.va;
4383 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 4384 struct be_nic_res_desc *desc;
abb93951 4385
980df249
SR		 4386 /* GET_FUNC_CONFIG returns resource descriptors of the
4387 * current function only. So, pf_num should be set to
4388 * PF_NUM_IGNORE.
4389 */
4390 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4391 PF_NUM_IGNORE);
abb93951
PR		 4392 if (!desc) {
4393 status = -EINVAL;
4394 goto err;
4395 }
980df249
SR		 4396
4397 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4398 adapter->pf_num = desc->pf_num;
4399 adapter->vf_num = desc->vf_num;
4400
4401 if (res)
4402 be_copy_nic_desc(res, desc);
abb93951
PR		 4403 }
4404err:
4405 mutex_unlock(&adapter->mbox_lock);
d98ef50f 4406 if (cmd.va)
e51000db
SB		 4407 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4408 cmd.dma);
abb93951
PR		 4409 return status;
4410}
4411
de2b1e03 4412/* This routine returns a list of all the NIC PF_nums in the adapter */
d766e7e6 4413static u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
de2b1e03
SK		 4414{
4415 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4416 struct be_pcie_res_desc *pcie = NULL;
4417 int i;
4418 u16 nic_pf_count = 0;
4419
4420 for (i = 0; i < desc_count; i++) {
4421 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4422 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4423 pcie = (struct be_pcie_res_desc *)hdr;
4424 if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4425 pcie->pf_type == MISSION_RDMA)) {
4426 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4427 }
4428 }
4429
4430 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4431 hdr = (void *)hdr + hdr->desc_len;
4432 }
4433 return nic_pf_count;
4434}
4435
980df249 4436/* Will use MBOX only if MCCQ has not been created */
92bf14ab 4437int be_cmd_get_profile_config(struct be_adapter *adapter,
de2b1e03
SK		 4438 struct be_resources *res,
4439 struct be_port_resources *port_res,
4440 u8 profile_type, u8 query, u8 domain)
a05f99db 4441{
150d58c7 4442 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 4443 struct be_cmd_req_get_profile_config *req;
10cccf60 4444 struct be_nic_res_desc *vf_res;
150d58c7 4445 struct be_pcie_res_desc *pcie;
f93f160b 4446 struct be_port_res_desc *port;
150d58c7 4447 struct be_nic_res_desc *nic;
ba48c0c9 4448 struct be_mcc_wrb wrb = {0};
a05f99db 4449 struct be_dma_mem cmd;
f2858738 4450 u16 desc_count;
a05f99db
VV		 4451 int status;
4452
4453 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7 4454 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
e51000db
SB		 4455 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4456 GFP_ATOMIC);
150d58c7 4457 if (!cmd.va)
a05f99db 4458 return -ENOMEM;
a05f99db 4459
ba48c0c9
VV		 4460 req = cmd.va;
4461 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4462 OPCODE_COMMON_GET_PROFILE_CONFIG,
4463 cmd.size, &wrb, &cmd);
4464
ba48c0c9
VV		 4465 if (!lancer_chip(adapter))
4466 req->hdr.version = 1;
de2b1e03 4467 req->type = profile_type;
72ef3a88 4468 req->hdr.domain = domain;
ba48c0c9 4469
f2858738
VV		 4470 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4471 * descriptors with all bits set to "1" for the fields which can be
4472 * modified using SET_PROFILE_CONFIG cmd.
4473 */
4474 if (query == RESOURCE_MODIFIABLE)
4475 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4476
ba48c0c9 4477 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 4478 if (status)
4479 goto err;
abb93951 4480
150d58c7 4481 resp = cmd.va;
f2858738 4482 desc_count = le16_to_cpu(resp->desc_count);
abb93951 4483
de2b1e03
SK		 4484 if (port_res) {
4485 u16 nic_pf_cnt = 0, i;
4486 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4487
4488 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4489 desc_count,
4490 nic_pf_num_list);
4491
4492 for (i = 0; i < nic_pf_cnt; i++) {
4493 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4494 nic_pf_num_list[i]);
4495 if (nic->link_param == adapter->port_num) {
4496 port_res->nic_pfs++;
4497 pcie = be_get_pcie_desc(resp->func_param,
4498 desc_count,
4499 nic_pf_num_list[i]);
4500 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4501 }
4502 }
4503 return status;
4504 }
4505
980df249
SR		 4506 pcie = be_get_pcie_desc(resp->func_param, desc_count,
4507 adapter->pf_num);
150d58c7 4508 if (pcie)
92bf14ab 4509 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 4510
f93f160b
VV		 4511 port = be_get_port_desc(resp->func_param, desc_count);
4512 if (port)
4513 adapter->mc_type = port->mc_type;
4514
980df249
SR		 4515 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4516 adapter->pf_num);
92bf14ab
SP		 4517 if (nic)
4518 be_copy_nic_desc(res, nic);
4519
980df249
SR		 4520 vf_res = be_get_vft_desc(resp->func_param, desc_count,
4521 adapter->pf_num);
10cccf60
VV		 4522 if (vf_res)
4523 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 4524err:
a05f99db 4525 if (cmd.va)
e51000db
SB		 4526 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4527 cmd.dma);
abb93951
PR		 4528 return status;
4529}
4530
bec84e6b
VV		 4531/* Will use MBOX only if MCCQ has not been created */
4532static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4533 int size, int count, u8 version, u8 domain)
d5c18473 4534{
d5c18473 4535 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 4536 struct be_mcc_wrb wrb = {0};
4537 struct be_dma_mem cmd;
d5c18473
PR		 4538 int status;
4539
bec84e6b
VV		 4540 memset(&cmd, 0, sizeof(struct be_dma_mem));
4541 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
e51000db
SB		 4542 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4543 GFP_ATOMIC);
bec84e6b
VV		 4544 if (!cmd.va)
4545 return -ENOMEM;
d5c18473 4546
bec84e6b 4547 req = cmd.va;
d5c18473 4548 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 4549 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4550 &wrb, &cmd);
a401801c 4551 req->hdr.version = version;
d5c18473 4552 req->hdr.domain = domain;
bec84e6b 4553 req->desc_count = cpu_to_le32(count);
a401801c
SP		 4554 memcpy(req->desc, desc, size);
4555
bec84e6b
VV		 4556 status = be_cmd_notify_wait(adapter, &wrb);
4557
4558 if (cmd.va)
e51000db
SB		 4559 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4560 cmd.dma);
d5c18473
PR		 4561 return status;
4562}
4563
a401801c 4564/* Mark all fields invalid */
d766e7e6 4565static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 4566{
4567 memset(nic, 0, sizeof(*nic));
4568 nic->unicast_mac_count = 0xFFFF;
4569 nic->mcc_count = 0xFFFF;
4570 nic->vlan_count = 0xFFFF;
4571 nic->mcast_mac_count = 0xFFFF;
4572 nic->txq_count = 0xFFFF;
4573 nic->rq_count = 0xFFFF;
4574 nic->rssq_count = 0xFFFF;
4575 nic->lro_count = 0xFFFF;
4576 nic->cq_count = 0xFFFF;
4577 nic->toe_conn_count = 0xFFFF;
4578 nic->eq_count = 0xFFFF;
0f77ba73 4579 nic->iface_count = 0xFFFF;
a401801c 4580 nic->link_param = 0xFF;
0f77ba73 4581 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 4582 nic->acpi_params = 0xFF;
4583 nic->wol_param = 0x0F;
0f77ba73
RN		 4584 nic->tunnel_iface_count = 0xFFFF;
4585 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 4586 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 4587 nic->bw_max = 0xFFFFFFFF;
4588}
4589
bec84e6b
VV		 4590/* Mark all fields invalid */
4591static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4592{
4593 memset(pcie, 0, sizeof(*pcie));
4594 pcie->sriov_state = 0xFF;
4595 pcie->pf_state = 0xFF;
4596 pcie->pf_type = 0xFF;
4597 pcie->num_vfs = 0xFFFF;
4598}
4599
0f77ba73
RN		 4600int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4601 u8 domain)
a401801c 4602{
0f77ba73
RN		 4603 struct be_nic_res_desc nic_desc;
4604 u32 bw_percent;
4605 u16 version = 0;
4606
4607 if (BE3_chip(adapter))
4608 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 4609
0f77ba73 4610 be_reset_nic_desc(&nic_desc);
980df249 4611 nic_desc.pf_num = adapter->pf_num;
0f77ba73 4612 nic_desc.vf_num = domain;
58bdeaa6 4613 nic_desc.bw_min = 0;
0f77ba73 4614 if (lancer_chip(adapter)) {
a401801c
SP		 4615 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4616 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4617 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4618 (1 << NOSV_SHIFT);
0f77ba73 4619 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 4620 } else {
0f77ba73
RN		 4621 version = 1;
4622 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4623 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4624 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4625 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4626 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 4627 }
0f77ba73
RN		 4628
4629 return be_cmd_set_profile_config(adapter, &nic_desc,
4630 nic_desc.hdr.desc_len,
bec84e6b
VV		 4631 1, version, domain);
4632}
4633
4634int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738 4635 struct be_resources pool_res, u16 num_vfs,
b9263cbf 4636 struct be_resources *vft_res)
bec84e6b
VV		 4637{
4638 struct {
4639 struct be_pcie_res_desc pcie;
4640 struct be_nic_res_desc nic_vft;
4641 } __packed desc;
bec84e6b 4642
bec84e6b
VV		 4643 /* PF PCIE descriptor */
4644 be_reset_pcie_desc(&desc.pcie);
4645 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4646 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 4647 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 4648 desc.pcie.pf_num = adapter->pdev->devfn;
4649 desc.pcie.sriov_state = num_vfs ? 1 : 0;
4650 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4651
4652 /* VF NIC Template descriptor */
4653 be_reset_nic_desc(&desc.nic_vft);
4654 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4655 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
b9263cbf
SR		 4656 desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4657 BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 4658 desc.nic_vft.pf_num = adapter->pdev->devfn;
4659 desc.nic_vft.vf_num = 0;
b9263cbf
SR		 4660 desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4661 desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4662 desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4663 desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4664 desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4665
4666 if (vft_res->max_uc_mac)
4667 desc.nic_vft.unicast_mac_count =
4668 cpu_to_le16(vft_res->max_uc_mac);
4669 if (vft_res->max_vlans)
4670 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4671 if (vft_res->max_iface_count)
4672 desc.nic_vft.iface_count =
4673 cpu_to_le16(vft_res->max_iface_count);
4674 if (vft_res->max_mcc_count)
4675 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
bec84e6b
VV		 4676
4677 return be_cmd_set_profile_config(adapter, &desc,
4678 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 4679}
4680
4681int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4682{
4683 struct be_mcc_wrb *wrb;
4684 struct be_cmd_req_manage_iface_filters *req;
4685 int status;
4686
4687 if (iface == 0xFFFFFFFF)
4688 return -1;
4689
b7172414 4690 mutex_lock(&adapter->mcc_lock);
a401801c
SP		 4691
4692 wrb = wrb_from_mccq(adapter);
4693 if (!wrb) {
4694 status = -EBUSY;
4695 goto err;
4696 }
4697 req = embedded_payload(wrb);
4698
4699 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4700 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4701 wrb, NULL);
4702 req->op = op;
4703 req->target_iface_id = cpu_to_le32(iface);
4704
4705 status = be_mcc_notify_wait(adapter);
4706err:
b7172414 4707 mutex_unlock(&adapter->mcc_lock);
a401801c
SP		 4708 return status;
4709}
4710
4711int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4712{
4713 struct be_port_res_desc port_desc;
4714
4715 memset(&port_desc, 0, sizeof(port_desc));
4716 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4717 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4718 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4719 port_desc.link_num = adapter->hba_port_num;
4720 if (port) {
4721 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4722 (1 << RCVID_SHIFT);
4723 port_desc.nv_port = swab16(port);
4724 } else {
4725 port_desc.nv_flags = NV_TYPE_DISABLED;
4726 port_desc.nv_port = 0;
4727 }
4728
4729 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 4730 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 4731}
4732
4c876616
SP		 4733int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4734 int vf_num)
4735{
4736 struct be_mcc_wrb *wrb;
4737 struct be_cmd_req_get_iface_list *req;
4738 struct be_cmd_resp_get_iface_list *resp;
4739 int status;
4740
b7172414 4741 mutex_lock(&adapter->mcc_lock);
4c876616
SP		 4742
4743 wrb = wrb_from_mccq(adapter);
4744 if (!wrb) {
4745 status = -EBUSY;
4746 goto err;
4747 }
4748 req = embedded_payload(wrb);
4749
4750 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4751 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4752 wrb, NULL);
4753 req->hdr.domain = vf_num + 1;
4754
4755 status = be_mcc_notify_wait(adapter);
4756 if (!status) {
4757 resp = (struct be_cmd_resp_get_iface_list *)req;
4758 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4759 }
4760
4761err:
b7172414 4762 mutex_unlock(&adapter->mcc_lock);
4c876616
SP		 4763 return status;
4764}
4765
5c510811
SK		 4766static int lancer_wait_idle(struct be_adapter *adapter)
4767{
4768#define SLIPORT_IDLE_TIMEOUT 30
4769 u32 reg_val;
4770 int status = 0, i;
4771
4772 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4773 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4774 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4775 break;
4776
4777 ssleep(1);
4778 }
4779
4780 if (i == SLIPORT_IDLE_TIMEOUT)
4781 status = -1;
4782
4783 return status;
4784}
4785
4786int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4787{
4788 int status = 0;
4789
4790 status = lancer_wait_idle(adapter);
4791 if (status)
4792 return status;
4793
4794 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4795
4796 return status;
4797}
4798
4799/* Routine to check whether dump image is present or not */
4800bool dump_present(struct be_adapter *adapter)
4801{
4802 u32 sliport_status = 0;
4803
4804 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4805 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4806}
4807
4808int lancer_initiate_dump(struct be_adapter *adapter)
4809{
f0613380 4810 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 4811 int status;
4812
f0613380
KA		 4813 if (dump_present(adapter)) {
4814 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4815 return -EEXIST;
4816 }
4817
5c510811
SK		 4818 /* give firmware reset and diagnostic dump */
4819 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4820 PHYSDEV_CONTROL_DD_MASK);
4821 if (status < 0) {
f0613380 4822 dev_err(dev, "FW reset failed\n");
5c510811
SK		 4823 return status;
4824 }
4825
4826 status = lancer_wait_idle(adapter);
4827 if (status)
4828 return status;
4829
4830 if (!dump_present(adapter)) {
f0613380
KA		 4831 dev_err(dev, "FW dump not generated\n");
4832 return -EIO;
5c510811
SK		 4833 }
4834
4835 return 0;
4836}
4837
f0613380
KA		 4838int lancer_delete_dump(struct be_adapter *adapter)
4839{
4840 int status;
4841
4842 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4843 return be_cmd_status(status);
4844}
4845
dcf7ebba
PR		 4846/* Uses sync mcc */
4847int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4848{
4849 struct be_mcc_wrb *wrb;
4850 struct be_cmd_enable_disable_vf *req;
4851 int status;
4852
0599863d 4853 if (BEx_chip(adapter))
dcf7ebba
PR		 4854 return 0;
4855
b7172414 4856 mutex_lock(&adapter->mcc_lock);
dcf7ebba
PR		 4857
4858 wrb = wrb_from_mccq(adapter);
4859 if (!wrb) {
4860 status = -EBUSY;
4861 goto err;
4862 }
4863
4864 req = embedded_payload(wrb);
4865
4866 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4867 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4868 wrb, NULL);
4869
4870 req->hdr.domain = domain;
4871 req->enable = 1;
4872 status = be_mcc_notify_wait(adapter);
4873err:
b7172414 4874 mutex_unlock(&adapter->mcc_lock);
dcf7ebba
PR		 4875 return status;
4876}
4877
68c45a2d
SK		 4878int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4879{
4880 struct be_mcc_wrb *wrb;
4881 struct be_cmd_req_intr_set *req;
4882 int status;
4883
4884 if (mutex_lock_interruptible(&adapter->mbox_lock))
4885 return -1;
4886
4887 wrb = wrb_from_mbox(adapter);
4888
4889 req = embedded_payload(wrb);
4890
4891 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4892 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4893 wrb, NULL);
4894
4895 req->intr_enabled = intr_enable;
4896
4897 status = be_mbox_notify_wait(adapter);
4898
4899 mutex_unlock(&adapter->mbox_lock);
4900 return status;
4901}
4902
542963b7
VV		 4903/* Uses MBOX */
4904int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4905{
4906 struct be_cmd_req_get_active_profile *req;
4907 struct be_mcc_wrb *wrb;
4908 int status;
4909
4910 if (mutex_lock_interruptible(&adapter->mbox_lock))
4911 return -1;
4912
4913 wrb = wrb_from_mbox(adapter);
4914 if (!wrb) {
4915 status = -EBUSY;
4916 goto err;
4917 }
4918
4919 req = embedded_payload(wrb);
4920
4921 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4922 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4923 wrb, NULL);
4924
4925 status = be_mbox_notify_wait(adapter);
4926 if (!status) {
4927 struct be_cmd_resp_get_active_profile *resp =
4928 embedded_payload(wrb);
03d28ffe 4929
542963b7
VV		 4930 *profile_id = le16_to_cpu(resp->active_profile_id);
4931 }
4932
4933err:
4934 mutex_unlock(&adapter->mbox_lock);
4935 return status;
4936}
4937
d766e7e6
BX		 4938static int
4939__be_cmd_set_logical_link_config(struct be_adapter *adapter,
4940 int link_state, int version, u8 domain)
bdce2ad7 4941{
bdce2ad7 4942 struct be_cmd_req_set_ll_link *req;
0b98ca2a
SR		 4943 struct be_mcc_wrb *wrb;
4944 u32 link_config = 0;
bdce2ad7
SR		 4945 int status;
4946
b7172414 4947 mutex_lock(&adapter->mcc_lock);
bdce2ad7
SR		 4948
4949 wrb = wrb_from_mccq(adapter);
4950 if (!wrb) {
4951 status = -EBUSY;
4952 goto err;
4953 }
4954
4955 req = embedded_payload(wrb);
4956
4957 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4958 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4959 sizeof(*req), wrb, NULL);
4960
d9d426af 4961 req->hdr.version = version;
bdce2ad7
SR		 4962 req->hdr.domain = domain;
4963
d9d426af
SR		 4964 if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4965 link_state == IFLA_VF_LINK_STATE_AUTO)
0b98ca2a 4966 link_config |= PLINK_ENABLE;
bdce2ad7
SR		 4967
4968 if (link_state == IFLA_VF_LINK_STATE_AUTO)
0b98ca2a
SR		 4969 link_config |= PLINK_TRACK;
4970
4971 req->link_config = cpu_to_le32(link_config);
bdce2ad7
SR		 4972
4973 status = be_mcc_notify_wait(adapter);
4974err:
b7172414 4975 mutex_unlock(&adapter->mcc_lock);
bdce2ad7
SR		 4976 return status;
4977}
4978
d9d426af
SR		 4979int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4980 int link_state, u8 domain)
4981{
4982 int status;
4983
dc6e8511 4984 if (BE2_chip(adapter))
d9d426af
SR		 4985 return -EOPNOTSUPP;
4986
4987 status = __be_cmd_set_logical_link_config(adapter, link_state,
4988 2, domain);
4989
4990 /* Version 2 of the command will not be recognized by older FW.
4991 * On such a failure issue version 1 of the command.
4992 */
4993 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4994 status = __be_cmd_set_logical_link_config(adapter, link_state,
4995 1, domain);
4996 return status;
4997}
710f3e59
SB		 4998
4999int be_cmd_set_features(struct be_adapter *adapter)
5000{
5001 struct be_cmd_resp_set_features *resp;
5002 struct be_cmd_req_set_features *req;
5003 struct be_mcc_wrb *wrb;
5004 int status;
5005
5006 if (mutex_lock_interruptible(&adapter->mcc_lock))
5007 return -1;
5008
5009 wrb = wrb_from_mccq(adapter);
5010 if (!wrb) {
5011 status = -EBUSY;
5012 goto err;
5013 }
5014
5015 req = embedded_payload(wrb);
5016
5017 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
5018 OPCODE_COMMON_SET_FEATURES,
5019 sizeof(*req), wrb, NULL);
5020
5021 req->features = cpu_to_le32(BE_FEATURE_UE_RECOVERY);
5022 req->parameter_len = cpu_to_le32(sizeof(struct be_req_ue_recovery));
5023 req->parameter.req.uer = cpu_to_le32(BE_UE_RECOVERY_UER_MASK);
5024
5025 status = be_mcc_notify_wait(adapter);
5026 if (status)
5027 goto err;
5028
5029 resp = embedded_payload(wrb);
5030
5031 adapter->error_recovery.ue_to_poll_time =
5032 le16_to_cpu(resp->parameter.resp.ue2rp);
5033 adapter->error_recovery.ue_to_reset_time =
5034 le16_to_cpu(resp->parameter.resp.ue2sr);
5035 adapter->error_recovery.recovery_supported = true;
5036err:
5037 /* Checking "MCC_STATUS_INVALID_LENGTH" for SKH as FW
5038 * returns this error in older firmware versions
5039 */
5040 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
5041 base_status(status) == MCC_STATUS_INVALID_LENGTH)
5042 dev_info(&adapter->pdev->dev,
5043 "Adapter does not support HW error recovery\n");
5044
5045 mutex_unlock(&adapter->mcc_lock);
5046 return status;
5047}
5048
6a4ab669 5049int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 5050 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 5051{
5052 struct be_adapter *adapter = netdev_priv(netdev_handle);
5053 struct be_mcc_wrb *wrb;
504fbf1e 5054 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 5055 struct be_cmd_req_hdr *req;
5056 struct be_cmd_resp_hdr *resp;
5057 int status;
5058
b7172414 5059 mutex_lock(&adapter->mcc_lock);
6a4ab669
PP		 5060
5061 wrb = wrb_from_mccq(adapter);
5062 if (!wrb) {
5063 status = -EBUSY;
5064 goto err;
5065 }
5066 req = embedded_payload(wrb);
5067 resp = embedded_payload(wrb);
5068
5069 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
5070 hdr->opcode, wrb_payload_size, wrb, NULL);
5071 memcpy(req, wrb_payload, wrb_payload_size);
5072 be_dws_cpu_to_le(req, wrb_payload_size);
5073
5074 status = be_mcc_notify_wait(adapter);
5075 if (cmd_status)
5076 *cmd_status = (status & 0xffff);
5077 if (ext_status)
5078 *ext_status = 0;
5079 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
5080 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
5081err:
b7172414 5082 mutex_unlock(&adapter->mcc_lock);
6a4ab669
PP		 5083 return status;
5084}
5085EXPORT_SYMBOL(be_roce_mcc_cmd);
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