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be2net: remove multiple assignments on a single line
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
40263820 2 * Copyright (C) 2005 - 2014 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
f25b119c
PR		 22static struct be_cmd_priv_map cmd_priv_map[] = {
23 {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
25 CMD_SUBSYSTEM_ETH,
26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
28 },
29 {
30 OPCODE_COMMON_GET_FLOW_CONTROL,
31 CMD_SUBSYSTEM_COMMON,
32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
34 },
35 {
36 OPCODE_COMMON_SET_FLOW_CONTROL,
37 CMD_SUBSYSTEM_COMMON,
38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
40 },
41 {
42 OPCODE_ETH_GET_PPORT_STATS,
43 CMD_SUBSYSTEM_ETH,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
46 },
47 {
48 OPCODE_COMMON_GET_PHY_DETAILS,
49 CMD_SUBSYSTEM_COMMON,
50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 }
53};
54
a2cc4e0b 55static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 56{
57 int i;
58 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
59 u32 cmd_privileges = adapter->cmd_privileges;
60
61 for (i = 0; i < num_entries; i++)
62 if (opcode == cmd_priv_map[i].opcode &&
63 subsystem == cmd_priv_map[i].subsystem)
64 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
65 return false;
66
67 return true;
68}
69
3de09455
SK		 70static inline void *embedded_payload(struct be_mcc_wrb *wrb)
71{
72 return wrb->payload.embedded_payload;
73}
609ff3bb 74
8788fdc2 75static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 76{
8788fdc2 77 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 78 u32 val = 0;
79
6589ade0 80 if (be_error(adapter))
7acc2087 81 return;
7acc2087 82
5fb379ee
SP		 83 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
84 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 85
86 wmb();
8788fdc2 87 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 88}
89
90/* To check if valid bit is set, check the entire word as we don't know
91 * the endianness of the data (old entry is host endian while a new entry is
92 * little endian) */
efd2e40a 93static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 94{
9e9ff4b7
SP		 95 u32 flags;
96
5fb379ee 97 if (compl->flags != 0) {
9e9ff4b7
SP		 98 flags = le32_to_cpu(compl->flags);
99 if (flags & CQE_FLAGS_VALID_MASK) {
100 compl->flags = flags;
101 return true;
102 }
5fb379ee 103 }
9e9ff4b7 104 return false;
5fb379ee
SP		 105}
106
107/* Need to reset the entire word that houses the valid bit */
efd2e40a 108static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 109{
110 compl->flags = 0;
111}
112
652bf646
PR		 113static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
114{
115 unsigned long addr;
116
117 addr = tag1;
118 addr = ((addr << 16) << 16) | tag0;
119 return (void *)addr;
120}
121
4c60005f
KA		 122static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
123{
124 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
125 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
126 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
127 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
128 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
129 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
130 return true;
131 else
132 return false;
133}
134
559b633f
SP		 135/* Place holder for all the async MCC cmds wherein the caller is not in a busy
136 * loop (has not issued be_mcc_notify_wait())
137 */
138static void be_async_cmd_process(struct be_adapter *adapter,
139 struct be_mcc_compl *compl,
140 struct be_cmd_resp_hdr *resp_hdr)
141{
142 enum mcc_base_status base_status = base_status(compl->status);
143 u8 opcode = 0, subsystem = 0;
144
145 if (resp_hdr) {
146 opcode = resp_hdr->opcode;
147 subsystem = resp_hdr->subsystem;
148 }
149
150 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
151 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
152 complete(&adapter->et_cmd_compl);
153 return;
154 }
155
156 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
157 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
158 subsystem == CMD_SUBSYSTEM_COMMON) {
159 adapter->flash_status = compl->status;
160 complete(&adapter->et_cmd_compl);
161 return;
162 }
163
164 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
165 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
166 subsystem == CMD_SUBSYSTEM_ETH &&
167 base_status == MCC_STATUS_SUCCESS) {
168 be_parse_stats(adapter);
169 adapter->stats_cmd_sent = false;
170 return;
171 }
172
173 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
174 subsystem == CMD_SUBSYSTEM_COMMON) {
175 if (base_status == MCC_STATUS_SUCCESS) {
176 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
177 (void *)resp_hdr;
178 adapter->drv_stats.be_on_die_temperature =
179 resp->on_die_temperature;
180 } else {
181 adapter->be_get_temp_freq = 0;
182 }
183 return;
184 }
185}
186
8788fdc2 187static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 188 struct be_mcc_compl *compl)
5fb379ee 189{
4c60005f
KA		 190 enum mcc_base_status base_status;
191 enum mcc_addl_status addl_status;
652bf646
PR		 192 struct be_cmd_resp_hdr *resp_hdr;
193 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 194
195 /* Just swap the status to host endian; mcc tag is opaquely copied
196 * from mcc_wrb */
197 be_dws_le_to_cpu(compl, 4);
198
4c60005f
KA		 199 base_status = base_status(compl->status);
200 addl_status = addl_status(compl->status);
96c9b2e4 201
652bf646 202 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 203 if (resp_hdr) {
204 opcode = resp_hdr->opcode;
205 subsystem = resp_hdr->subsystem;
206 }
207
559b633f 208 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 209
559b633f
SP		 210 if (base_status != MCC_STATUS_SUCCESS &&
211 !be_skip_err_log(opcode, base_status, addl_status)) {
4c60005f 212 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 213 dev_warn(&adapter->pdev->dev,
522609f2 214 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 215 opcode, subsystem);
2b3f291b 216 } else {
97f1d8cd
VV		 217 dev_err(&adapter->pdev->dev,
218 "opcode %d-%d failed:status %d-%d\n",
4c60005f 219 opcode, subsystem, base_status, addl_status);
2b3f291b 220 }
5fb379ee 221 }
4c60005f 222 return compl->status;
5fb379ee
SP		 223}
224
a8f447bd 225/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 226static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 227 struct be_mcc_compl *compl)
a8f447bd 228{
3acf19d9
SP		 229 struct be_async_event_link_state *evt =
230 (struct be_async_event_link_state *)compl;
231
b236916a 232 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 233 adapter->phy.link_speed = -1;
b236916a 234
bdce2ad7
SR		 235 /* On BEx the FW does not send a separate link status
236 * notification for physical and logical link.
237 * On other chips just process the logical link
238 * status notification
239 */
240 if (!BEx_chip(adapter) &&
2e177a5c
PR		 241 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
242 return;
243
b236916a
AK		 244 /* For the initial link status do not rely on the ASYNC event as
245 * it may not be received in some cases.
246 */
247 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 248 be_link_status_update(adapter,
249 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 250}
251
cc4ce020
SK		 252/* Grp5 CoS Priority evt */
253static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 254 struct be_mcc_compl *compl)
cc4ce020 255{
3acf19d9
SP		 256 struct be_async_event_grp5_cos_priority *evt =
257 (struct be_async_event_grp5_cos_priority *)compl;
258
cc4ce020
SK		 259 if (evt->valid) {
260 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 261 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 262 adapter->recommended_prio =
263 evt->reco_default_priority << VLAN_PRIO_SHIFT;
264 }
265}
266
323ff71e 267/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 268static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 269 struct be_mcc_compl *compl)
cc4ce020 270{
3acf19d9
SP		 271 struct be_async_event_grp5_qos_link_speed *evt =
272 (struct be_async_event_grp5_qos_link_speed *)compl;
273
323ff71e
SP		 274 if (adapter->phy.link_speed >= 0 &&
275 evt->physical_port == adapter->port_num)
276 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 277}
278
3968fa1e
AK		 279/*Grp5 PVID evt*/
280static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 281 struct be_mcc_compl *compl)
3968fa1e 282{
3acf19d9
SP		 283 struct be_async_event_grp5_pvid_state *evt =
284 (struct be_async_event_grp5_pvid_state *)compl;
285
bdac85b5 286 if (evt->enabled) {
939cf306 287 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 288 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
289 } else {
3968fa1e 290 adapter->pvid = 0;
bdac85b5 291 }
3968fa1e
AK		 292}
293
cc4ce020 294static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 295 struct be_mcc_compl *compl)
cc4ce020 296{
3acf19d9
SP		 297 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
298 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 299
300 switch (event_type) {
301 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 302 be_async_grp5_cos_priority_process(adapter, compl);
303 break;
cc4ce020 304 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 305 be_async_grp5_qos_speed_process(adapter, compl);
306 break;
3968fa1e 307 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 308 be_async_grp5_pvid_state_process(adapter, compl);
309 break;
cc4ce020 310 default:
cc4ce020
SK		 311 break;
312 }
313}
314
bc0c3405 315static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 316 struct be_mcc_compl *cmp)
bc0c3405
AK		 317{
318 u8 event_type = 0;
504fbf1e 319 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 320
3acf19d9
SP		 321 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
322 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 323
324 switch (event_type) {
325 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
326 if (evt->valid)
327 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
328 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
329 break;
330 default:
05ccaa2b
VV		 331 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
332 event_type);
bc0c3405
AK		 333 break;
334 }
335}
336
3acf19d9 337static inline bool is_link_state_evt(u32 flags)
a8f447bd 338{
3acf19d9
SP		 339 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
340 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 341}
5fb379ee 342
3acf19d9 343static inline bool is_grp5_evt(u32 flags)
cc4ce020 344{
3acf19d9
SP		 345 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
346 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 347}
348
3acf19d9 349static inline bool is_dbg_evt(u32 flags)
bc0c3405 350{
3acf19d9
SP		 351 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
352 ASYNC_EVENT_CODE_QNQ;
353}
354
355static void be_mcc_event_process(struct be_adapter *adapter,
356 struct be_mcc_compl *compl)
357{
358 if (is_link_state_evt(compl->flags))
359 be_async_link_state_process(adapter, compl);
360 else if (is_grp5_evt(compl->flags))
361 be_async_grp5_evt_process(adapter, compl);
362 else if (is_dbg_evt(compl->flags))
363 be_async_dbg_evt_process(adapter, compl);
bc0c3405
AK		 364}
365
efd2e40a 366static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 367{
8788fdc2 368 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 369 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 370
371 if (be_mcc_compl_is_new(compl)) {
372 queue_tail_inc(mcc_cq);
373 return compl;
374 }
375 return NULL;
376}
377
7a1e9b20
SP		 378void be_async_mcc_enable(struct be_adapter *adapter)
379{
380 spin_lock_bh(&adapter->mcc_cq_lock);
381
382 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
383 adapter->mcc_obj.rearm_cq = true;
384
385 spin_unlock_bh(&adapter->mcc_cq_lock);
386}
387
388void be_async_mcc_disable(struct be_adapter *adapter)
389{
a323d9bf
SP		 390 spin_lock_bh(&adapter->mcc_cq_lock);
391
7a1e9b20 392 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 393 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
394
395 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 396}
397
10ef9ab4 398int be_process_mcc(struct be_adapter *adapter)
5fb379ee 399{
efd2e40a 400 struct be_mcc_compl *compl;
10ef9ab4 401 int num = 0, status = 0;
7a1e9b20 402 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 403
072a9c48 404 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 405
8788fdc2 406 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 407 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 408 be_mcc_event_process(adapter, compl);
b31c50a7 409 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 410 status = be_mcc_compl_process(adapter, compl);
411 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 412 }
413 be_mcc_compl_use(compl);
414 num++;
415 }
b31c50a7 416
10ef9ab4
SP		 417 if (num)
418 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
419
072a9c48 420 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 421 return status;
5fb379ee
SP		 422}
423
6ac7b687 424/* Wait till no more pending mcc requests are present */
b31c50a7 425static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 426{
b31c50a7 427#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 428 int i, status = 0;
f31e50a8
SP		 429 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
430
6ac7b687 431 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 432 if (be_error(adapter))
433 return -EIO;
434
072a9c48 435 local_bh_disable();
10ef9ab4 436 status = be_process_mcc(adapter);
072a9c48 437 local_bh_enable();
b31c50a7 438
f31e50a8 439 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 440 break;
441 udelay(100);
442 }
b31c50a7 443 if (i == mcc_timeout) {
6589ade0
SP		 444 dev_err(&adapter->pdev->dev, "FW not responding\n");
445 adapter->fw_timeout = true;
652bf646 446 return -EIO;
b31c50a7 447 }
f31e50a8 448 return status;
6ac7b687
SP		 449}
450
451/* Notify MCC requests and wait for completion */
b31c50a7 452static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 453{
652bf646
PR		 454 int status;
455 struct be_mcc_wrb *wrb;
456 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
457 u16 index = mcc_obj->q.head;
458 struct be_cmd_resp_hdr *resp;
459
460 index_dec(&index, mcc_obj->q.len);
461 wrb = queue_index_node(&mcc_obj->q, index);
462
463 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
464
8788fdc2 465 be_mcc_notify(adapter);
652bf646
PR		 466
467 status = be_mcc_wait_compl(adapter);
468 if (status == -EIO)
469 goto out;
470
4c60005f
KA		 471 status = (resp->base_status |
472 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
473 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 474out:
475 return status;
6ac7b687
SP		 476}
477
5f0b849e 478static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 479{
f25b03a7 480 int msecs = 0;
6b7c5b94
SP		 481 u32 ready;
482
483 do {
6589ade0
SP		 484 if (be_error(adapter))
485 return -EIO;
486
cf588477 487 ready = ioread32(db);
434b3648 488 if (ready == 0xffffffff)
cf588477 489 return -1;
cf588477
SP		 490
491 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 492 if (ready)
493 break;
494
f25b03a7 495 if (msecs > 4000) {
6589ade0
SP		 496 dev_err(&adapter->pdev->dev, "FW not responding\n");
497 adapter->fw_timeout = true;
f67ef7ba 498 be_detect_error(adapter);
6b7c5b94
SP		 499 return -1;
500 }
501
1dbf53a2 502 msleep(1);
f25b03a7 503 msecs++;
6b7c5b94
SP		 504 } while (true);
505
506 return 0;
507}
508
509/*
510 * Insert the mailbox address into the doorbell in two steps
5fb379ee 511 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 512 */
b31c50a7 513static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 514{
515 int status;
6b7c5b94 516 u32 val = 0;
8788fdc2
SP		 517 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
518 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 519 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 520 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 521
cf588477
SP		 522 /* wait for ready to be set */
523 status = be_mbox_db_ready_wait(adapter, db);
524 if (status != 0)
525 return status;
526
6b7c5b94
SP		 527 val |= MPU_MAILBOX_DB_HI_MASK;
528 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
529 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
530 iowrite32(val, db);
531
532 /* wait for ready to be set */
5f0b849e 533 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 534 if (status != 0)
535 return status;
536
537 val = 0;
6b7c5b94
SP		 538 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
539 val |= (u32)(mbox_mem->dma >> 4) << 2;
540 iowrite32(val, db);
541
5f0b849e 542 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 543 if (status != 0)
544 return status;
545
5fb379ee 546 /* A cq entry has been made now */
efd2e40a
SP		 547 if (be_mcc_compl_is_new(compl)) {
548 status = be_mcc_compl_process(adapter, &mbox->compl);
549 be_mcc_compl_use(compl);
5fb379ee
SP		 550 if (status)
551 return status;
552 } else {
5f0b849e 553 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 554 return -1;
555 }
5fb379ee 556 return 0;
6b7c5b94
SP		 557}
558
c5b3ad4c 559static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 560{
fe6d2a38
SP		 561 u32 sem;
562
c5b3ad4c
SP		 563 if (BEx_chip(adapter))
564 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 565 else
c5b3ad4c
SP		 566 pci_read_config_dword(adapter->pdev,
567 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
568
569 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 570}
571
87f20c26 572static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 573{
574#define SLIPORT_READY_TIMEOUT 30
575 u32 sliport_status;
576 int status = 0, i;
577
578 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
579 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
580 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
581 break;
582
583 msleep(1000);
584 }
585
586 if (i == SLIPORT_READY_TIMEOUT)
587 status = -1;
588
589 return status;
590}
591
67297ad8
PR		 592static bool lancer_provisioning_error(struct be_adapter *adapter)
593{
594 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
03d28ffe 595
67297ad8
PR		 596 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
597 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
a2cc4e0b
SP		 598 sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET);
599 sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET);
67297ad8
PR		 600
601 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
602 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
603 return true;
604 }
605 return false;
606}
607
bf99e50d
PR		 608int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
609{
610 int status;
611 u32 sliport_status, err, reset_needed;
67297ad8
PR		 612 bool resource_error;
613
614 resource_error = lancer_provisioning_error(adapter);
615 if (resource_error)
01e5b2c4 616 return -EAGAIN;
67297ad8 617
bf99e50d
PR		 618 status = lancer_wait_ready(adapter);
619 if (!status) {
620 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
621 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
622 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
623 if (err && reset_needed) {
624 iowrite32(SLI_PORT_CONTROL_IP_MASK,
625 adapter->db + SLIPORT_CONTROL_OFFSET);
626
627 /* check adapter has corrected the error */
628 status = lancer_wait_ready(adapter);
629 sliport_status = ioread32(adapter->db +
630 SLIPORT_STATUS_OFFSET);
631 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
632 SLIPORT_STATUS_RN_MASK);
633 if (status || sliport_status)
634 status = -1;
635 } else if (err || reset_needed) {
636 status = -1;
637 }
638 }
67297ad8
PR		 639 /* Stop error recovery if error is not recoverable.
640 * No resource error is temporary errors and will go away
641 * when PF provisions resources.
642 */
643 resource_error = lancer_provisioning_error(adapter);
01e5b2c4
SK		 644 if (resource_error)
645 status = -EAGAIN;
67297ad8 646
bf99e50d
PR		 647 return status;
648}
649
650int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 651{
43a04fdc
SP		 652 u16 stage;
653 int status, timeout = 0;
6ed35eea 654 struct device *dev = &adapter->pdev->dev;
6b7c5b94 655
bf99e50d
PR		 656 if (lancer_chip(adapter)) {
657 status = lancer_wait_ready(adapter);
658 return status;
659 }
660
43a04fdc 661 do {
c5b3ad4c 662 stage = be_POST_stage_get(adapter);
66d29cbc 663 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 664 return 0;
66d29cbc 665
a2cc4e0b 666 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 667 if (msleep_interruptible(2000)) {
668 dev_err(dev, "Waiting for POST aborted\n");
669 return -EINTR;
43a04fdc 670 }
66d29cbc 671 timeout += 2;
3ab81b5f 672 } while (timeout < 60);
6b7c5b94 673
6ed35eea 674 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
43a04fdc 675 return -1;
6b7c5b94
SP		 676}
677
6b7c5b94
SP		 678static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
679{
680 return &wrb->payload.sgl[0];
681}
682
a2cc4e0b 683static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 684{
685 wrb->tag0 = addr & 0xFFFFFFFF;
686 wrb->tag1 = upper_32_bits(addr);
687}
6b7c5b94
SP		 688
689/* Don't touch the hdr after it's prepared */
106df1e3
SK		 690/* mem will be NULL for embedded commands */
691static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 692 u8 subsystem, u8 opcode, int cmd_len,
693 struct be_mcc_wrb *wrb,
694 struct be_dma_mem *mem)
6b7c5b94 695{
106df1e3
SK		 696 struct be_sge *sge;
697
6b7c5b94
SP		 698 req_hdr->opcode = opcode;
699 req_hdr->subsystem = subsystem;
700 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 701 req_hdr->version = 0;
bea50988 702 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 703 wrb->payload_length = cmd_len;
704 if (mem) {
705 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
706 MCC_WRB_SGE_CNT_SHIFT;
707 sge = nonembedded_sgl(wrb);
708 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
709 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
710 sge->len = cpu_to_le32(mem->size);
711 } else
712 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
713 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 714}
715
716static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 717 struct be_dma_mem *mem)
6b7c5b94
SP		 718{
719 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
720 u64 dma = (u64)mem->dma;
721
722 for (i = 0; i < buf_pages; i++) {
723 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
724 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
725 dma += PAGE_SIZE_4K;
726 }
727}
728
b31c50a7 729static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 730{
b31c50a7
SP		 731 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
732 struct be_mcc_wrb *wrb
733 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
734 memset(wrb, 0, sizeof(*wrb));
735 return wrb;
6b7c5b94
SP		 736}
737
b31c50a7 738static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 739{
b31c50a7
SP		 740 struct be_queue_info *mccq = &adapter->mcc_obj.q;
741 struct be_mcc_wrb *wrb;
742
aa790db9
PR		 743 if (!mccq->created)
744 return NULL;
745
4d277125 746 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 747 return NULL;
713d0394 748
b31c50a7
SP		 749 wrb = queue_head_node(mccq);
750 queue_head_inc(mccq);
751 atomic_inc(&mccq->used);
752 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 753 return wrb;
754}
755
bea50988
SP		 756static bool use_mcc(struct be_adapter *adapter)
757{
758 return adapter->mcc_obj.q.created;
759}
760
761/* Must be used only in process context */
762static int be_cmd_lock(struct be_adapter *adapter)
763{
764 if (use_mcc(adapter)) {
765 spin_lock_bh(&adapter->mcc_lock);
766 return 0;
767 } else {
768 return mutex_lock_interruptible(&adapter->mbox_lock);
769 }
770}
771
772/* Must be used only in process context */
773static void be_cmd_unlock(struct be_adapter *adapter)
774{
775 if (use_mcc(adapter))
776 spin_unlock_bh(&adapter->mcc_lock);
777 else
778 return mutex_unlock(&adapter->mbox_lock);
779}
780
781static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
782 struct be_mcc_wrb *wrb)
783{
784 struct be_mcc_wrb *dest_wrb;
785
786 if (use_mcc(adapter)) {
787 dest_wrb = wrb_from_mccq(adapter);
788 if (!dest_wrb)
789 return NULL;
790 } else {
791 dest_wrb = wrb_from_mbox(adapter);
792 }
793
794 memcpy(dest_wrb, wrb, sizeof(*wrb));
795 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
796 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
797
798 return dest_wrb;
799}
800
801/* Must be used only in process context */
802static int be_cmd_notify_wait(struct be_adapter *adapter,
803 struct be_mcc_wrb *wrb)
804{
805 struct be_mcc_wrb *dest_wrb;
806 int status;
807
808 status = be_cmd_lock(adapter);
809 if (status)
810 return status;
811
812 dest_wrb = be_cmd_copy(adapter, wrb);
813 if (!dest_wrb)
814 return -EBUSY;
815
816 if (use_mcc(adapter))
817 status = be_mcc_notify_wait(adapter);
818 else
819 status = be_mbox_notify_wait(adapter);
820
821 if (!status)
822 memcpy(wrb, dest_wrb, sizeof(*wrb));
823
824 be_cmd_unlock(adapter);
825 return status;
826}
827
2243e2e9
SP		 828/* Tell fw we're about to start firing cmds by writing a
829 * special pattern across the wrb hdr; uses mbox
830 */
831int be_cmd_fw_init(struct be_adapter *adapter)
832{
833 u8 *wrb;
834 int status;
835
bf99e50d
PR		 836 if (lancer_chip(adapter))
837 return 0;
838
2984961c
IV		 839 if (mutex_lock_interruptible(&adapter->mbox_lock))
840 return -1;
2243e2e9
SP		 841
842 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 843 *wrb++ = 0xFF;
844 *wrb++ = 0x12;
845 *wrb++ = 0x34;
846 *wrb++ = 0xFF;
847 *wrb++ = 0xFF;
848 *wrb++ = 0x56;
849 *wrb++ = 0x78;
850 *wrb = 0xFF;
2243e2e9
SP		 851
852 status = be_mbox_notify_wait(adapter);
853
2984961c 854 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 855 return status;
856}
857
858/* Tell fw we're done with firing cmds by writing a
859 * special pattern across the wrb hdr; uses mbox
860 */
861int be_cmd_fw_clean(struct be_adapter *adapter)
862{
863 u8 *wrb;
864 int status;
865
bf99e50d
PR		 866 if (lancer_chip(adapter))
867 return 0;
868
2984961c
IV		 869 if (mutex_lock_interruptible(&adapter->mbox_lock))
870 return -1;
2243e2e9
SP		 871
872 wrb = (u8 *)wrb_from_mbox(adapter);
873 *wrb++ = 0xFF;
874 *wrb++ = 0xAA;
875 *wrb++ = 0xBB;
876 *wrb++ = 0xFF;
877 *wrb++ = 0xFF;
878 *wrb++ = 0xCC;
879 *wrb++ = 0xDD;
880 *wrb = 0xFF;
881
882 status = be_mbox_notify_wait(adapter);
883
2984961c 884 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 885 return status;
886}
bf99e50d 887
f2f781a7 888int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 889{
b31c50a7
SP		 890 struct be_mcc_wrb *wrb;
891 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 892 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
893 int status, ver = 0;
6b7c5b94 894
2984961c
IV		 895 if (mutex_lock_interruptible(&adapter->mbox_lock))
896 return -1;
b31c50a7
SP		 897
898 wrb = wrb_from_mbox(adapter);
899 req = embedded_payload(wrb);
6b7c5b94 900
106df1e3 901 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 902 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
903 NULL);
6b7c5b94 904
f2f781a7
SP		 905 /* Support for EQ_CREATEv2 available only SH-R onwards */
906 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
907 ver = 2;
908
909 req->hdr.version = ver;
6b7c5b94
SP		 910 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
911
6b7c5b94
SP		 912 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
913 /* 4byte eqe*/
914 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
915 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 916 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 917 be_dws_cpu_to_le(req->context, sizeof(req->context));
918
919 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
920
b31c50a7 921 status = be_mbox_notify_wait(adapter);
6b7c5b94 922 if (!status) {
b31c50a7 923 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 924
f2f781a7
SP		 925 eqo->q.id = le16_to_cpu(resp->eq_id);
926 eqo->msix_idx =
927 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
928 eqo->q.created = true;
6b7c5b94 929 }
b31c50a7 930
2984961c 931 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 932 return status;
933}
934
f9449ab7 935/* Use MCC */
8788fdc2 936int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 937 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 938{
b31c50a7
SP		 939 struct be_mcc_wrb *wrb;
940 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 941 int status;
942
f9449ab7 943 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 944
f9449ab7
SP		 945 wrb = wrb_from_mccq(adapter);
946 if (!wrb) {
947 status = -EBUSY;
948 goto err;
949 }
b31c50a7 950 req = embedded_payload(wrb);
6b7c5b94 951
106df1e3 952 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 953 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
954 NULL);
5ee4979b 955 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 956 if (permanent) {
957 req->permanent = 1;
958 } else {
504fbf1e 959 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 960 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 961 req->permanent = 0;
962 }
963
f9449ab7 964 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 965 if (!status) {
966 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 967
6b7c5b94 968 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 969 }
6b7c5b94 970
f9449ab7
SP		 971err:
972 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 973 return status;
974}
975
b31c50a7 976/* Uses synchronous MCCQ */
8788fdc2 977int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 978 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 979{
b31c50a7
SP		 980 struct be_mcc_wrb *wrb;
981 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 982 int status;
983
b31c50a7
SP		 984 spin_lock_bh(&adapter->mcc_lock);
985
986 wrb = wrb_from_mccq(adapter);
713d0394
SP		 987 if (!wrb) {
988 status = -EBUSY;
989 goto err;
990 }
b31c50a7 991 req = embedded_payload(wrb);
6b7c5b94 992
106df1e3 993 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 994 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
995 NULL);
6b7c5b94 996
f8617e08 997 req->hdr.domain = domain;
6b7c5b94
SP		 998 req->if_id = cpu_to_le32(if_id);
999 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1000
b31c50a7 1001 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1002 if (!status) {
1003 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1004
6b7c5b94
SP		 1005 *pmac_id = le32_to_cpu(resp->pmac_id);
1006 }
1007
713d0394 1008err:
b31c50a7 1009 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 1010
1011 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1012 status = -EPERM;
1013
6b7c5b94
SP		 1014 return status;
1015}
1016
b31c50a7 1017/* Uses synchronous MCCQ */
30128031 1018int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1019{
b31c50a7
SP		 1020 struct be_mcc_wrb *wrb;
1021 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1022 int status;
1023
30128031
SP		 1024 if (pmac_id == -1)
1025 return 0;
1026
b31c50a7
SP		 1027 spin_lock_bh(&adapter->mcc_lock);
1028
1029 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1030 if (!wrb) {
1031 status = -EBUSY;
1032 goto err;
1033 }
b31c50a7 1034 req = embedded_payload(wrb);
6b7c5b94 1035
106df1e3
SK		 1036 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1037 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
6b7c5b94 1038
f8617e08 1039 req->hdr.domain = dom;
6b7c5b94
SP		 1040 req->if_id = cpu_to_le32(if_id);
1041 req->pmac_id = cpu_to_le32(pmac_id);
1042
b31c50a7
SP		 1043 status = be_mcc_notify_wait(adapter);
1044
713d0394 1045err:
b31c50a7 1046 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1047 return status;
1048}
1049
b31c50a7 1050/* Uses Mbox */
10ef9ab4 1051int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1052 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1053{
b31c50a7
SP		 1054 struct be_mcc_wrb *wrb;
1055 struct be_cmd_req_cq_create *req;
6b7c5b94 1056 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1057 void *ctxt;
6b7c5b94
SP		 1058 int status;
1059
2984961c
IV		 1060 if (mutex_lock_interruptible(&adapter->mbox_lock))
1061 return -1;
b31c50a7
SP		 1062
1063 wrb = wrb_from_mbox(adapter);
1064 req = embedded_payload(wrb);
1065 ctxt = &req->context;
6b7c5b94 1066
106df1e3 1067 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1068 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1069 NULL);
6b7c5b94
SP		 1070
1071 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1072
1073 if (BEx_chip(adapter)) {
fe6d2a38 1074 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1075 coalesce_wm);
fe6d2a38 1076 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1077 ctxt, no_delay);
fe6d2a38 1078 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1079 __ilog2_u32(cq->len / 256));
fe6d2a38 1080 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1081 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1082 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1083 } else {
1084 req->hdr.version = 2;
1085 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1086
1087 /* coalesce-wm field in this cmd is not relevant to Lancer.
1088 * Lancer uses COMMON_MODIFY_CQ to set this field
1089 */
1090 if (!lancer_chip(adapter))
1091 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1092 ctxt, coalesce_wm);
bbdc42f8 1093 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1094 no_delay);
bbdc42f8 1095 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1096 __ilog2_u32(cq->len / 256));
bbdc42f8 1097 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1098 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1099 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1100 }
6b7c5b94 1101
6b7c5b94
SP		 1102 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1103
1104 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1105
b31c50a7 1106 status = be_mbox_notify_wait(adapter);
6b7c5b94 1107 if (!status) {
b31c50a7 1108 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1109
6b7c5b94
SP		 1110 cq->id = le16_to_cpu(resp->cq_id);
1111 cq->created = true;
1112 }
b31c50a7 1113
2984961c 1114 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1115
1116 return status;
1117}
1118
1119static u32 be_encoded_q_len(int q_len)
1120{
1121 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1122
5fb379ee
SP		 1123 if (len_encoded == 16)
1124 len_encoded = 0;
1125 return len_encoded;
1126}
1127
4188e7df 1128static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1129 struct be_queue_info *mccq,
1130 struct be_queue_info *cq)
5fb379ee 1131{
b31c50a7 1132 struct be_mcc_wrb *wrb;
34b1ef04 1133 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1134 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1135 void *ctxt;
5fb379ee
SP		 1136 int status;
1137
2984961c
IV		 1138 if (mutex_lock_interruptible(&adapter->mbox_lock))
1139 return -1;
b31c50a7
SP		 1140
1141 wrb = wrb_from_mbox(adapter);
1142 req = embedded_payload(wrb);
1143 ctxt = &req->context;
5fb379ee 1144
106df1e3 1145 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1146 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1147 NULL);
5fb379ee 1148
d4a2ac3e 1149 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1150 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1151 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1152 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1153 be_encoded_q_len(mccq->len));
fe6d2a38 1154 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1155 } else {
1156 req->hdr.version = 1;
1157 req->cq_id = cpu_to_le16(cq->id);
1158
1159 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1160 be_encoded_q_len(mccq->len));
1161 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1162 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1163 ctxt, cq->id);
1164 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1165 ctxt, 1);
fe6d2a38 1166 }
5fb379ee 1167
cc4ce020 1168 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 1169 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
bc0c3405 1170 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
5fb379ee
SP		 1171 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1172
1173 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1174
b31c50a7 1175 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1176 if (!status) {
1177 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1178
5fb379ee
SP		 1179 mccq->id = le16_to_cpu(resp->id);
1180 mccq->created = true;
1181 }
2984961c 1182 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1183
1184 return status;
1185}
1186
4188e7df 1187static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1188 struct be_queue_info *mccq,
1189 struct be_queue_info *cq)
34b1ef04
SK		 1190{
1191 struct be_mcc_wrb *wrb;
1192 struct be_cmd_req_mcc_create *req;
1193 struct be_dma_mem *q_mem = &mccq->dma_mem;
1194 void *ctxt;
1195 int status;
1196
1197 if (mutex_lock_interruptible(&adapter->mbox_lock))
1198 return -1;
1199
1200 wrb = wrb_from_mbox(adapter);
1201 req = embedded_payload(wrb);
1202 ctxt = &req->context;
1203
106df1e3 1204 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1205 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1206 NULL);
34b1ef04
SK		 1207
1208 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1209
1210 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1211 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1212 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1213 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1214
1215 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1216
1217 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1218
1219 status = be_mbox_notify_wait(adapter);
1220 if (!status) {
1221 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1222
34b1ef04
SK		 1223 mccq->id = le16_to_cpu(resp->id);
1224 mccq->created = true;
1225 }
1226
1227 mutex_unlock(&adapter->mbox_lock);
1228 return status;
1229}
1230
1231int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1232 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1233{
1234 int status;
1235
1236 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1237 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1238 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1239 "or newer to avoid conflicting priorities between NIC "
1240 "and FCoE traffic");
1241 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1242 }
1243 return status;
1244}
1245
94d73aaa 1246int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1247{
7707133c 1248 struct be_mcc_wrb wrb = {0};
b31c50a7 1249 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1250 struct be_queue_info *txq = &txo->q;
1251 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1252 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1253 int status, ver = 0;
6b7c5b94 1254
7707133c 1255 req = embedded_payload(&wrb);
106df1e3 1256 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1257 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1258
8b7756ca
PR		 1259 if (lancer_chip(adapter)) {
1260 req->hdr.version = 1;
94d73aaa
VV		 1261 } else if (BEx_chip(adapter)) {
1262 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1263 req->hdr.version = 2;
1264 } else { /* For SH */
1265 req->hdr.version = 2;
8b7756ca
PR		 1266 }
1267
81b02655
VV		 1268 if (req->hdr.version > 0)
1269 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1270 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1271 req->ulp_num = BE_ULP1_NUM;
1272 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1273 req->cq_id = cpu_to_le16(cq->id);
1274 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1275 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1276 ver = req->hdr.version;
1277
7707133c 1278 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1279 if (!status) {
7707133c 1280 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1281
6b7c5b94 1282 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1283 if (ver == 2)
1284 txo->db_offset = le32_to_cpu(resp->db_offset);
1285 else
1286 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1287 txq->created = true;
1288 }
b31c50a7 1289
6b7c5b94
SP		 1290 return status;
1291}
1292
482c9e79 1293/* Uses MCC */
8788fdc2 1294int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1295 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1296 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1297{
b31c50a7
SP		 1298 struct be_mcc_wrb *wrb;
1299 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1300 struct be_dma_mem *q_mem = &rxq->dma_mem;
1301 int status;
1302
482c9e79 1303 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1304
482c9e79
SP		 1305 wrb = wrb_from_mccq(adapter);
1306 if (!wrb) {
1307 status = -EBUSY;
1308 goto err;
1309 }
b31c50a7 1310 req = embedded_payload(wrb);
6b7c5b94 1311
106df1e3 1312 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1313 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1314
1315 req->cq_id = cpu_to_le16(cq_id);
1316 req->frag_size = fls(frag_size) - 1;
1317 req->num_pages = 2;
1318 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1319 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1320 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1321 req->rss_queue = cpu_to_le32(rss);
1322
482c9e79 1323 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1324 if (!status) {
1325 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1326
6b7c5b94
SP		 1327 rxq->id = le16_to_cpu(resp->id);
1328 rxq->created = true;
3abcdeda 1329 *rss_id = resp->rss_id;
6b7c5b94 1330 }
b31c50a7 1331
482c9e79
SP		 1332err:
1333 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1334 return status;
1335}
1336
b31c50a7
SP		 1337/* Generic destroyer function for all types of queues
1338 * Uses Mbox
1339 */
8788fdc2 1340int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1341 int queue_type)
6b7c5b94 1342{
b31c50a7
SP		 1343 struct be_mcc_wrb *wrb;
1344 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1345 u8 subsys = 0, opcode = 0;
1346 int status;
1347
2984961c
IV		 1348 if (mutex_lock_interruptible(&adapter->mbox_lock))
1349 return -1;
6b7c5b94 1350
b31c50a7
SP		 1351 wrb = wrb_from_mbox(adapter);
1352 req = embedded_payload(wrb);
1353
6b7c5b94
SP		 1354 switch (queue_type) {
1355 case QTYPE_EQ:
1356 subsys = CMD_SUBSYSTEM_COMMON;
1357 opcode = OPCODE_COMMON_EQ_DESTROY;
1358 break;
1359 case QTYPE_CQ:
1360 subsys = CMD_SUBSYSTEM_COMMON;
1361 opcode = OPCODE_COMMON_CQ_DESTROY;
1362 break;
1363 case QTYPE_TXQ:
1364 subsys = CMD_SUBSYSTEM_ETH;
1365 opcode = OPCODE_ETH_TX_DESTROY;
1366 break;
1367 case QTYPE_RXQ:
1368 subsys = CMD_SUBSYSTEM_ETH;
1369 opcode = OPCODE_ETH_RX_DESTROY;
1370 break;
5fb379ee
SP		 1371 case QTYPE_MCCQ:
1372 subsys = CMD_SUBSYSTEM_COMMON;
1373 opcode = OPCODE_COMMON_MCC_DESTROY;
1374 break;
6b7c5b94 1375 default:
5f0b849e 1376 BUG();
6b7c5b94 1377 }
d744b44e 1378
106df1e3 1379 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1380 NULL);
6b7c5b94
SP		 1381 req->id = cpu_to_le16(q->id);
1382
b31c50a7 1383 status = be_mbox_notify_wait(adapter);
aa790db9 1384 q->created = false;
5f0b849e 1385
2984961c 1386 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1387 return status;
1388}
6b7c5b94 1389
482c9e79
SP		 1390/* Uses MCC */
1391int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1392{
1393 struct be_mcc_wrb *wrb;
1394 struct be_cmd_req_q_destroy *req;
1395 int status;
1396
1397 spin_lock_bh(&adapter->mcc_lock);
1398
1399 wrb = wrb_from_mccq(adapter);
1400 if (!wrb) {
1401 status = -EBUSY;
1402 goto err;
1403 }
1404 req = embedded_payload(wrb);
1405
106df1e3 1406 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1407 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1408 req->id = cpu_to_le16(q->id);
1409
1410 status = be_mcc_notify_wait(adapter);
aa790db9 1411 q->created = false;
482c9e79
SP		 1412
1413err:
1414 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1415 return status;
1416}
1417
b31c50a7 1418/* Create an rx filtering policy configuration on an i/f
bea50988 1419 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1420 */
73d540f2 1421int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1422 u32 *if_handle, u32 domain)
6b7c5b94 1423{
bea50988 1424 struct be_mcc_wrb wrb = {0};
b31c50a7 1425 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1426 int status;
1427
bea50988 1428 req = embedded_payload(&wrb);
106df1e3 1429 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1430 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1431 sizeof(*req), &wrb, NULL);
ba343c77 1432 req->hdr.domain = domain;
73d540f2
SP		 1433 req->capability_flags = cpu_to_le32(cap_flags);
1434 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1435 req->pmac_invalid = true;
6b7c5b94 1436
bea50988 1437 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1438 if (!status) {
bea50988 1439 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1440
6b7c5b94 1441 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1442
1443 /* Hack to retrieve VF's pmac-id on BE3 */
1444 if (BE3_chip(adapter) && !be_physfn(adapter))
1445 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1446 }
6b7c5b94
SP		 1447 return status;
1448}
1449
f9449ab7 1450/* Uses MCCQ */
30128031 1451int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1452{
b31c50a7
SP		 1453 struct be_mcc_wrb *wrb;
1454 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1455 int status;
1456
30128031 1457 if (interface_id == -1)
f9449ab7 1458 return 0;
b31c50a7 1459
f9449ab7
SP		 1460 spin_lock_bh(&adapter->mcc_lock);
1461
1462 wrb = wrb_from_mccq(adapter);
1463 if (!wrb) {
1464 status = -EBUSY;
1465 goto err;
1466 }
b31c50a7 1467 req = embedded_payload(wrb);
6b7c5b94 1468
106df1e3 1469 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1470 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1471 sizeof(*req), wrb, NULL);
658681f7 1472 req->hdr.domain = domain;
6b7c5b94 1473 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1474
f9449ab7
SP		 1475 status = be_mcc_notify_wait(adapter);
1476err:
1477 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1478 return status;
1479}
1480
1481/* Get stats is a non embedded command: the request is not embedded inside
1482 * WRB but is a separate dma memory block
b31c50a7 1483 * Uses asynchronous MCC
6b7c5b94 1484 */
8788fdc2 1485int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1486{
b31c50a7 1487 struct be_mcc_wrb *wrb;
89a88ab8 1488 struct be_cmd_req_hdr *hdr;
713d0394 1489 int status = 0;
6b7c5b94 1490
b31c50a7 1491 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1492
b31c50a7 1493 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1494 if (!wrb) {
1495 status = -EBUSY;
1496 goto err;
1497 }
89a88ab8 1498 hdr = nonemb_cmd->va;
6b7c5b94 1499
106df1e3 1500 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1501 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1502 nonemb_cmd);
89a88ab8 1503
ca34fe38 1504 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1505 if (BE2_chip(adapter))
1506 hdr->version = 0;
1507 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1508 hdr->version = 1;
61000861
AK		 1509 else
1510 hdr->version = 2;
89a88ab8 1511
b31c50a7 1512 be_mcc_notify(adapter);
b2aebe6d 1513 adapter->stats_cmd_sent = true;
6b7c5b94 1514
713d0394 1515err:
b31c50a7 1516 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1517 return status;
6b7c5b94
SP		 1518}
1519
005d5696
SX		 1520/* Lancer Stats */
1521int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1522 struct be_dma_mem *nonemb_cmd)
005d5696 1523{
005d5696
SX		 1524 struct be_mcc_wrb *wrb;
1525 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1526 int status = 0;
1527
f25b119c
PR		 1528 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1529 CMD_SUBSYSTEM_ETH))
1530 return -EPERM;
1531
005d5696
SX		 1532 spin_lock_bh(&adapter->mcc_lock);
1533
1534 wrb = wrb_from_mccq(adapter);
1535 if (!wrb) {
1536 status = -EBUSY;
1537 goto err;
1538 }
1539 req = nonemb_cmd->va;
005d5696 1540
106df1e3 1541 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1542 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1543 wrb, nonemb_cmd);
005d5696 1544
d51ebd33 1545 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1546 req->cmd_params.params.reset_stats = 0;
1547
005d5696
SX		 1548 be_mcc_notify(adapter);
1549 adapter->stats_cmd_sent = true;
1550
1551err:
1552 spin_unlock_bh(&adapter->mcc_lock);
1553 return status;
1554}
1555
323ff71e
SP		 1556static int be_mac_to_link_speed(int mac_speed)
1557{
1558 switch (mac_speed) {
1559 case PHY_LINK_SPEED_ZERO:
1560 return 0;
1561 case PHY_LINK_SPEED_10MBPS:
1562 return 10;
1563 case PHY_LINK_SPEED_100MBPS:
1564 return 100;
1565 case PHY_LINK_SPEED_1GBPS:
1566 return 1000;
1567 case PHY_LINK_SPEED_10GBPS:
1568 return 10000;
b971f847
VV		 1569 case PHY_LINK_SPEED_20GBPS:
1570 return 20000;
1571 case PHY_LINK_SPEED_25GBPS:
1572 return 25000;
1573 case PHY_LINK_SPEED_40GBPS:
1574 return 40000;
323ff71e
SP		 1575 }
1576 return 0;
1577}
1578
1579/* Uses synchronous mcc
1580 * Returns link_speed in Mbps
1581 */
1582int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1583 u8 *link_status, u32 dom)
6b7c5b94 1584{
b31c50a7
SP		 1585 struct be_mcc_wrb *wrb;
1586 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1587 int status;
1588
b31c50a7
SP		 1589 spin_lock_bh(&adapter->mcc_lock);
1590
b236916a
AK		 1591 if (link_status)
1592 *link_status = LINK_DOWN;
1593
b31c50a7 1594 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1595 if (!wrb) {
1596 status = -EBUSY;
1597 goto err;
1598 }
b31c50a7 1599 req = embedded_payload(wrb);
a8f447bd 1600
57cd80d4 1601 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1602 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1603 sizeof(*req), wrb, NULL);
57cd80d4 1604
ca34fe38
SP		 1605 /* version 1 of the cmd is not supported only by BE2 */
1606 if (!BE2_chip(adapter))
daad6167
PR		 1607 req->hdr.version = 1;
1608
57cd80d4 1609 req->hdr.domain = dom;
6b7c5b94 1610
b31c50a7 1611 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1612 if (!status) {
1613 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1614
323ff71e
SP		 1615 if (link_speed) {
1616 *link_speed = resp->link_speed ?
1617 le16_to_cpu(resp->link_speed) * 10 :
1618 be_mac_to_link_speed(resp->mac_speed);
1619
1620 if (!resp->logical_link_status)
1621 *link_speed = 0;
0388f251 1622 }
b236916a
AK		 1623 if (link_status)
1624 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1625 }
1626
713d0394 1627err:
b31c50a7 1628 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1629 return status;
1630}
1631
609ff3bb
AK		 1632/* Uses synchronous mcc */
1633int be_cmd_get_die_temperature(struct be_adapter *adapter)
1634{
1635 struct be_mcc_wrb *wrb;
1636 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1637 int status = 0;
609ff3bb
AK		 1638
1639 spin_lock_bh(&adapter->mcc_lock);
1640
1641 wrb = wrb_from_mccq(adapter);
1642 if (!wrb) {
1643 status = -EBUSY;
1644 goto err;
1645 }
1646 req = embedded_payload(wrb);
1647
106df1e3 1648 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1649 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1650 sizeof(*req), wrb, NULL);
609ff3bb 1651
3de09455 1652 be_mcc_notify(adapter);
609ff3bb
AK		 1653
1654err:
1655 spin_unlock_bh(&adapter->mcc_lock);
1656 return status;
1657}
1658
311fddc7
SK		 1659/* Uses synchronous mcc */
1660int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1661{
1662 struct be_mcc_wrb *wrb;
1663 struct be_cmd_req_get_fat *req;
1664 int status;
1665
1666 spin_lock_bh(&adapter->mcc_lock);
1667
1668 wrb = wrb_from_mccq(adapter);
1669 if (!wrb) {
1670 status = -EBUSY;
1671 goto err;
1672 }
1673 req = embedded_payload(wrb);
1674
106df1e3 1675 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1676 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1677 NULL);
311fddc7
SK		 1678 req->fat_operation = cpu_to_le32(QUERY_FAT);
1679 status = be_mcc_notify_wait(adapter);
1680 if (!status) {
1681 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
03d28ffe 1682
311fddc7 1683 if (log_size && resp->log_size)
fe2a70ee
SK		 1684 *log_size = le32_to_cpu(resp->log_size) -
1685 sizeof(u32);
311fddc7
SK		 1686 }
1687err:
1688 spin_unlock_bh(&adapter->mcc_lock);
1689 return status;
1690}
1691
c5f156de 1692int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1693{
1694 struct be_dma_mem get_fat_cmd;
1695 struct be_mcc_wrb *wrb;
1696 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1697 u32 offset = 0, total_size, buf_size,
1698 log_offset = sizeof(u32), payload_len;
c5f156de 1699 int status = 0;
311fddc7
SK		 1700
1701 if (buf_len == 0)
c5f156de 1702 return -EIO;
311fddc7
SK		 1703
1704 total_size = buf_len;
1705
fe2a70ee
SK		 1706 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1707 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 1708 get_fat_cmd.size,
1709 &get_fat_cmd.dma);
fe2a70ee 1710 if (!get_fat_cmd.va) {
fe2a70ee
SK		 1711 dev_err(&adapter->pdev->dev,
1712 "Memory allocation failure while retrieving FAT data\n");
c5f156de 1713 return -ENOMEM;
fe2a70ee
SK		 1714 }
1715
311fddc7
SK		 1716 spin_lock_bh(&adapter->mcc_lock);
1717
311fddc7
SK		 1718 while (total_size) {
1719 buf_size = min(total_size, (u32)60*1024);
1720 total_size -= buf_size;
1721
fe2a70ee
SK		 1722 wrb = wrb_from_mccq(adapter);
1723 if (!wrb) {
1724 status = -EBUSY;
311fddc7
SK		 1725 goto err;
1726 }
1727 req = get_fat_cmd.va;
311fddc7 1728
fe2a70ee 1729 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1730 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1731 OPCODE_COMMON_MANAGE_FAT, payload_len,
1732 wrb, &get_fat_cmd);
311fddc7
SK		 1733
1734 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1735 req->read_log_offset = cpu_to_le32(log_offset);
1736 req->read_log_length = cpu_to_le32(buf_size);
1737 req->data_buffer_size = cpu_to_le32(buf_size);
1738
1739 status = be_mcc_notify_wait(adapter);
1740 if (!status) {
1741 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1742
311fddc7 1743 memcpy(buf + offset,
a2cc4e0b
SP		 1744 resp->data_buffer,
1745 le32_to_cpu(resp->read_log_length));
fe2a70ee 1746 } else {
311fddc7 1747 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1748 goto err;
1749 }
311fddc7
SK		 1750 offset += buf_size;
1751 log_offset += buf_size;
1752 }
1753err:
fe2a70ee 1754 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
a2cc4e0b 1755 get_fat_cmd.va, get_fat_cmd.dma);
311fddc7 1756 spin_unlock_bh(&adapter->mcc_lock);
c5f156de 1757 return status;
311fddc7
SK		 1758}
1759
04b71175 1760/* Uses synchronous mcc */
e97e3cda 1761int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1762{
b31c50a7
SP		 1763 struct be_mcc_wrb *wrb;
1764 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1765 int status;
1766
04b71175 1767 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1768
04b71175
SP		 1769 wrb = wrb_from_mccq(adapter);
1770 if (!wrb) {
1771 status = -EBUSY;
1772 goto err;
1773 }
6b7c5b94 1774
04b71175 1775 req = embedded_payload(wrb);
6b7c5b94 1776
106df1e3 1777 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1778 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1779 NULL);
04b71175 1780 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1781 if (!status) {
1782 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1783
242eb470
VV		 1784 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1785 sizeof(adapter->fw_ver));
1786 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1787 sizeof(adapter->fw_on_flash));
6b7c5b94 1788 }
04b71175
SP		 1789err:
1790 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1791 return status;
1792}
1793
b31c50a7
SP		 1794/* set the EQ delay interval of an EQ to specified value
1795 * Uses async mcc
1796 */
b502ae8d
KA		 1797static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1798 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1799{
b31c50a7
SP		 1800 struct be_mcc_wrb *wrb;
1801 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1802 int status = 0, i;
6b7c5b94 1803
b31c50a7
SP		 1804 spin_lock_bh(&adapter->mcc_lock);
1805
1806 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1807 if (!wrb) {
1808 status = -EBUSY;
1809 goto err;
1810 }
b31c50a7 1811 req = embedded_payload(wrb);
6b7c5b94 1812
106df1e3 1813 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1814 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1815 NULL);
6b7c5b94 1816
2632bafd
SP		 1817 req->num_eq = cpu_to_le32(num);
1818 for (i = 0; i < num; i++) {
1819 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1820 req->set_eqd[i].phase = 0;
1821 req->set_eqd[i].delay_multiplier =
1822 cpu_to_le32(set_eqd[i].delay_multiplier);
1823 }
6b7c5b94 1824
b31c50a7 1825 be_mcc_notify(adapter);
713d0394 1826err:
b31c50a7 1827 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1828 return status;
6b7c5b94
SP		 1829}
1830
93676703
KA		 1831int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1832 int num)
1833{
1834 int num_eqs, i = 0;
1835
1836 if (lancer_chip(adapter) && num > 8) {
1837 while (num) {
1838 num_eqs = min(num, 8);
1839 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1840 i += num_eqs;
1841 num -= num_eqs;
1842 }
1843 } else {
1844 __be_cmd_modify_eqd(adapter, set_eqd, num);
1845 }
1846
1847 return 0;
1848}
1849
b31c50a7 1850/* Uses sycnhronous mcc */
8788fdc2 1851int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
4d567d97 1852 u32 num)
6b7c5b94 1853{
b31c50a7
SP		 1854 struct be_mcc_wrb *wrb;
1855 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1856 int status;
1857
b31c50a7
SP		 1858 spin_lock_bh(&adapter->mcc_lock);
1859
1860 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1861 if (!wrb) {
1862 status = -EBUSY;
1863 goto err;
1864 }
b31c50a7 1865 req = embedded_payload(wrb);
6b7c5b94 1866
106df1e3 1867 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1868 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1869 wrb, NULL);
6b7c5b94
SP		 1870
1871 req->interface_id = if_id;
012bd387 1872 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1873 req->num_vlan = num;
4d567d97
KA		 1874 memcpy(req->normal_vlan, vtag_array,
1875 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1876
b31c50a7 1877 status = be_mcc_notify_wait(adapter);
713d0394 1878err:
b31c50a7 1879 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1880 return status;
1881}
1882
5b8821b7 1883int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1884{
6ac7b687 1885 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1886 struct be_dma_mem *mem = &adapter->rx_filter;
1887 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1888 int status;
6b7c5b94 1889
8788fdc2 1890 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1891
b31c50a7 1892 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1893 if (!wrb) {
1894 status = -EBUSY;
1895 goto err;
1896 }
5b8821b7 1897 memset(req, 0, sizeof(*req));
106df1e3 1898 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1899 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1900 wrb, mem);
6b7c5b94 1901
5b8821b7
SP		 1902 req->if_id = cpu_to_le32(adapter->if_handle);
1903 if (flags & IFF_PROMISC) {
1904 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
a2cc4e0b
SP		 1905 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1906 BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7 1907 if (value == ON)
a2cc4e0b
SP		 1908 req->if_flags =
1909 cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1910 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1911 BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7 1912 } else if (flags & IFF_ALLMULTI) {
5f820b6c
KA		 1913 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1914 req->if_flags = cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
d9d604f8
AK		 1915 } else if (flags & BE_FLAGS_VLAN_PROMISC) {
1916 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1917
1918 if (value == ON)
1919 req->if_flags =
1920 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
5b8821b7 1921 } else {
22bedad3 1922 struct netdev_hw_addr *ha;
5b8821b7 1923 int i = 0;
24307eef 1924
5f820b6c
KA		 1925 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1926 req->if_flags = cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1610c79f
PR		 1927
1928 /* Reset mcast promisc mode if already set by setting mask
1929 * and not setting flags field
1930 */
abb93951
PR		 1931 req->if_flags_mask |=
1932 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 1933 be_if_cap_flags(adapter));
016f97b1 1934 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1935 netdev_for_each_mc_addr(ha, adapter->netdev)
1936 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1937 }
1938
012bd387 1939 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) !=
a2cc4e0b 1940 req->if_flags_mask) {
012bd387
AK		 1941 dev_warn(&adapter->pdev->dev,
1942 "Cannot set rx filter flags 0x%x\n",
1943 req->if_flags_mask);
1944 dev_warn(&adapter->pdev->dev,
1945 "Interface is capable of 0x%x flags only\n",
1946 be_if_cap_flags(adapter));
1947 }
1948 req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter));
1949
0d1d5875 1950 status = be_mcc_notify_wait(adapter);
012bd387 1951
713d0394 1952err:
8788fdc2 1953 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1954 return status;
6b7c5b94
SP		 1955}
1956
b31c50a7 1957/* Uses synchrounous mcc */
8788fdc2 1958int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1959{
b31c50a7
SP		 1960 struct be_mcc_wrb *wrb;
1961 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1962 int status;
1963
f25b119c
PR		 1964 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1965 CMD_SUBSYSTEM_COMMON))
1966 return -EPERM;
1967
b31c50a7 1968 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1969
b31c50a7 1970 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1971 if (!wrb) {
1972 status = -EBUSY;
1973 goto err;
1974 }
b31c50a7 1975 req = embedded_payload(wrb);
6b7c5b94 1976
106df1e3 1977 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1978 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
1979 wrb, NULL);
6b7c5b94 1980
b29812c1 1981 req->hdr.version = 1;
6b7c5b94
SP		 1982 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1983 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1984
b31c50a7 1985 status = be_mcc_notify_wait(adapter);
6b7c5b94 1986
713d0394 1987err:
b31c50a7 1988 spin_unlock_bh(&adapter->mcc_lock);
b29812c1
SR		 1989
1990 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
1991 return -EOPNOTSUPP;
1992
6b7c5b94
SP		 1993 return status;
1994}
1995
b31c50a7 1996/* Uses sycn mcc */
8788fdc2 1997int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1998{
b31c50a7
SP		 1999 struct be_mcc_wrb *wrb;
2000 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 2001 int status;
2002
f25b119c
PR		 2003 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2004 CMD_SUBSYSTEM_COMMON))
2005 return -EPERM;
2006
b31c50a7 2007 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2008
b31c50a7 2009 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2010 if (!wrb) {
2011 status = -EBUSY;
2012 goto err;
2013 }
b31c50a7 2014 req = embedded_payload(wrb);
6b7c5b94 2015
106df1e3 2016 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2017 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2018 wrb, NULL);
6b7c5b94 2019
b31c50a7 2020 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2021 if (!status) {
2022 struct be_cmd_resp_get_flow_control *resp =
2023 embedded_payload(wrb);
03d28ffe 2024
6b7c5b94
SP		 2025 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2026 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2027 }
2028
713d0394 2029err:
b31c50a7 2030 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 2031 return status;
2032}
2033
b31c50a7 2034/* Uses mbox */
e97e3cda 2035int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2036{
b31c50a7
SP		 2037 struct be_mcc_wrb *wrb;
2038 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2039 int status;
2040
2984961c
IV		 2041 if (mutex_lock_interruptible(&adapter->mbox_lock))
2042 return -1;
6b7c5b94 2043
b31c50a7
SP		 2044 wrb = wrb_from_mbox(adapter);
2045 req = embedded_payload(wrb);
6b7c5b94 2046
106df1e3 2047 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2048 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2049 sizeof(*req), wrb, NULL);
6b7c5b94 2050
b31c50a7 2051 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2052 if (!status) {
2053 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2054
e97e3cda
KA		 2055 adapter->port_num = le32_to_cpu(resp->phys_port);
2056 adapter->function_mode = le32_to_cpu(resp->function_mode);
2057 adapter->function_caps = le32_to_cpu(resp->function_caps);
2058 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2059 dev_info(&adapter->pdev->dev,
2060 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2061 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2062 }
2063
2984961c 2064 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2065 return status;
2066}
14074eab 2067
b31c50a7 2068/* Uses mbox */
14074eab 2069int be_cmd_reset_function(struct be_adapter *adapter)
2070{
b31c50a7
SP		 2071 struct be_mcc_wrb *wrb;
2072 struct be_cmd_req_hdr *req;
14074eab 2073 int status;
2074
bf99e50d
PR		 2075 if (lancer_chip(adapter)) {
2076 status = lancer_wait_ready(adapter);
2077 if (!status) {
2078 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2079 adapter->db + SLIPORT_CONTROL_OFFSET);
2080 status = lancer_test_and_set_rdy_state(adapter);
2081 }
2082 if (status) {
2083 dev_err(&adapter->pdev->dev,
2084 "Adapter in non recoverable error\n");
2085 }
2086 return status;
2087 }
2088
2984961c
IV		 2089 if (mutex_lock_interruptible(&adapter->mbox_lock))
2090 return -1;
14074eab 2091
b31c50a7
SP		 2092 wrb = wrb_from_mbox(adapter);
2093 req = embedded_payload(wrb);
14074eab 2094
106df1e3 2095 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2096 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2097 NULL);
14074eab 2098
b31c50a7 2099 status = be_mbox_notify_wait(adapter);
14074eab 2100
2984961c 2101 mutex_unlock(&adapter->mbox_lock);
14074eab 2102 return status;
2103}
84517482 2104
594ad54a 2105int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2106 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2107{
2108 struct be_mcc_wrb *wrb;
2109 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2110 int status;
2111
da1388d6
VV		 2112 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2113 return 0;
2114
b51aa367 2115 spin_lock_bh(&adapter->mcc_lock);
3abcdeda 2116
b51aa367
KA		 2117 wrb = wrb_from_mccq(adapter);
2118 if (!wrb) {
2119 status = -EBUSY;
2120 goto err;
2121 }
3abcdeda
SP		 2122 req = embedded_payload(wrb);
2123
106df1e3 2124 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2125 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2126
2127 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2128 req->enable_rss = cpu_to_le16(rss_hash_opts);
2129 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2130
b51aa367 2131 if (!BEx_chip(adapter))
d3bd3a5e 2132 req->hdr.version = 1;
d3bd3a5e 2133
3abcdeda 2134 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2135 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2136 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2137
b51aa367
KA		 2138 status = be_mcc_notify_wait(adapter);
2139err:
2140 spin_unlock_bh(&adapter->mcc_lock);
3abcdeda
SP		 2141 return status;
2142}
2143
fad9ab2c
SB		 2144/* Uses sync mcc */
2145int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2146 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2147{
2148 struct be_mcc_wrb *wrb;
2149 struct be_cmd_req_enable_disable_beacon *req;
2150 int status;
2151
2152 spin_lock_bh(&adapter->mcc_lock);
2153
2154 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2155 if (!wrb) {
2156 status = -EBUSY;
2157 goto err;
2158 }
fad9ab2c
SB		 2159 req = embedded_payload(wrb);
2160
106df1e3 2161 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2162 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2163 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2164
2165 req->port_num = port_num;
2166 req->beacon_state = state;
2167 req->beacon_duration = bcn;
2168 req->status_duration = sts;
2169
2170 status = be_mcc_notify_wait(adapter);
2171
713d0394 2172err:
fad9ab2c
SB		 2173 spin_unlock_bh(&adapter->mcc_lock);
2174 return status;
2175}
2176
2177/* Uses sync mcc */
2178int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2179{
2180 struct be_mcc_wrb *wrb;
2181 struct be_cmd_req_get_beacon_state *req;
2182 int status;
2183
2184 spin_lock_bh(&adapter->mcc_lock);
2185
2186 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2187 if (!wrb) {
2188 status = -EBUSY;
2189 goto err;
2190 }
fad9ab2c
SB		 2191 req = embedded_payload(wrb);
2192
106df1e3 2193 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2194 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2195 wrb, NULL);
fad9ab2c
SB		 2196
2197 req->port_num = port_num;
2198
2199 status = be_mcc_notify_wait(adapter);
2200 if (!status) {
2201 struct be_cmd_resp_get_beacon_state *resp =
2202 embedded_payload(wrb);
03d28ffe 2203
fad9ab2c
SB		 2204 *state = resp->beacon_state;
2205 }
2206
713d0394 2207err:
fad9ab2c
SB		 2208 spin_unlock_bh(&adapter->mcc_lock);
2209 return status;
2210}
2211
e36edd9d
ML		 2212/* Uses sync mcc */
2213int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2214 u8 page_num, u8 *data)
2215{
2216 struct be_dma_mem cmd;
2217 struct be_mcc_wrb *wrb;
2218 struct be_cmd_req_port_type *req;
2219 int status;
2220
2221 if (page_num > TR_PAGE_A2)
2222 return -EINVAL;
2223
2224 cmd.size = sizeof(struct be_cmd_resp_port_type);
2225 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2226 if (!cmd.va) {
2227 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2228 return -ENOMEM;
2229 }
2230 memset(cmd.va, 0, cmd.size);
2231
2232 spin_lock_bh(&adapter->mcc_lock);
2233
2234 wrb = wrb_from_mccq(adapter);
2235 if (!wrb) {
2236 status = -EBUSY;
2237 goto err;
2238 }
2239 req = cmd.va;
2240
2241 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2242 OPCODE_COMMON_READ_TRANSRECV_DATA,
2243 cmd.size, wrb, &cmd);
2244
2245 req->port = cpu_to_le32(adapter->hba_port_num);
2246 req->page_num = cpu_to_le32(page_num);
2247 status = be_mcc_notify_wait(adapter);
2248 if (!status) {
2249 struct be_cmd_resp_port_type *resp = cmd.va;
2250
2251 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2252 }
2253err:
2254 spin_unlock_bh(&adapter->mcc_lock);
2255 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2256 return status;
2257}
2258
485bf569 2259int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 2260 u32 data_size, u32 data_offset,
2261 const char *obj_name, u32 *data_written,
2262 u8 *change_status, u8 *addn_status)
485bf569
SN		 2263{
2264 struct be_mcc_wrb *wrb;
2265 struct lancer_cmd_req_write_object *req;
2266 struct lancer_cmd_resp_write_object *resp;
2267 void *ctxt = NULL;
2268 int status;
2269
2270 spin_lock_bh(&adapter->mcc_lock);
2271 adapter->flash_status = 0;
2272
2273 wrb = wrb_from_mccq(adapter);
2274 if (!wrb) {
2275 status = -EBUSY;
2276 goto err_unlock;
2277 }
2278
2279 req = embedded_payload(wrb);
2280
106df1e3 2281 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2282 OPCODE_COMMON_WRITE_OBJECT,
2283 sizeof(struct lancer_cmd_req_write_object), wrb,
2284 NULL);
485bf569
SN		 2285
2286 ctxt = &req->context;
2287 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2288 write_length, ctxt, data_size);
485bf569
SN		 2289
2290 if (data_size == 0)
2291 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2292 eof, ctxt, 1);
485bf569
SN		 2293 else
2294 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2295 eof, ctxt, 0);
485bf569
SN		 2296
2297 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2298 req->write_offset = cpu_to_le32(data_offset);
242eb470 2299 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2300 req->descriptor_count = cpu_to_le32(1);
2301 req->buf_len = cpu_to_le32(data_size);
2302 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2303 sizeof(struct lancer_cmd_req_write_object))
2304 & 0xFFFFFFFF);
485bf569
SN		 2305 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2306 sizeof(struct lancer_cmd_req_write_object)));
2307
2308 be_mcc_notify(adapter);
2309 spin_unlock_bh(&adapter->mcc_lock);
2310
5eeff635 2311 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2312 msecs_to_jiffies(60000)))
fd45160c 2313 status = -ETIMEDOUT;
485bf569
SN		 2314 else
2315 status = adapter->flash_status;
2316
2317 resp = embedded_payload(wrb);
f67ef7ba 2318 if (!status) {
485bf569 2319 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2320 *change_status = resp->change_status;
2321 } else {
485bf569 2322 *addn_status = resp->additional_status;
f67ef7ba 2323 }
485bf569
SN		 2324
2325 return status;
2326
2327err_unlock:
2328 spin_unlock_bh(&adapter->mcc_lock);
2329 return status;
2330}
2331
6809cee0
RN		 2332int be_cmd_query_cable_type(struct be_adapter *adapter)
2333{
2334 u8 page_data[PAGE_DATA_LEN];
2335 int status;
2336
2337 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2338 page_data);
2339 if (!status) {
2340 switch (adapter->phy.interface_type) {
2341 case PHY_TYPE_QSFP:
2342 adapter->phy.cable_type =
2343 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2344 break;
2345 case PHY_TYPE_SFP_PLUS_10GB:
2346 adapter->phy.cable_type =
2347 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2348 break;
2349 default:
2350 adapter->phy.cable_type = 0;
2351 break;
2352 }
2353 }
2354 return status;
2355}
2356
f0613380
KA		 2357int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2358{
2359 struct lancer_cmd_req_delete_object *req;
2360 struct be_mcc_wrb *wrb;
2361 int status;
2362
2363 spin_lock_bh(&adapter->mcc_lock);
2364
2365 wrb = wrb_from_mccq(adapter);
2366 if (!wrb) {
2367 status = -EBUSY;
2368 goto err;
2369 }
2370
2371 req = embedded_payload(wrb);
2372
2373 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2374 OPCODE_COMMON_DELETE_OBJECT,
2375 sizeof(*req), wrb, NULL);
2376
242eb470 2377 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2378
2379 status = be_mcc_notify_wait(adapter);
2380err:
2381 spin_unlock_bh(&adapter->mcc_lock);
2382 return status;
2383}
2384
de49bd5a 2385int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2386 u32 data_size, u32 data_offset, const char *obj_name,
2387 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2388{
2389 struct be_mcc_wrb *wrb;
2390 struct lancer_cmd_req_read_object *req;
2391 struct lancer_cmd_resp_read_object *resp;
2392 int status;
2393
2394 spin_lock_bh(&adapter->mcc_lock);
2395
2396 wrb = wrb_from_mccq(adapter);
2397 if (!wrb) {
2398 status = -EBUSY;
2399 goto err_unlock;
2400 }
2401
2402 req = embedded_payload(wrb);
2403
2404 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2405 OPCODE_COMMON_READ_OBJECT,
2406 sizeof(struct lancer_cmd_req_read_object), wrb,
2407 NULL);
de49bd5a
PR		 2408
2409 req->desired_read_len = cpu_to_le32(data_size);
2410 req->read_offset = cpu_to_le32(data_offset);
2411 strcpy(req->object_name, obj_name);
2412 req->descriptor_count = cpu_to_le32(1);
2413 req->buf_len = cpu_to_le32(data_size);
2414 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2415 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2416
2417 status = be_mcc_notify_wait(adapter);
2418
2419 resp = embedded_payload(wrb);
2420 if (!status) {
2421 *data_read = le32_to_cpu(resp->actual_read_len);
2422 *eof = le32_to_cpu(resp->eof);
2423 } else {
2424 *addn_status = resp->additional_status;
2425 }
2426
2427err_unlock:
2428 spin_unlock_bh(&adapter->mcc_lock);
2429 return status;
2430}
2431
84517482 2432int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b 2433 u32 flash_type, u32 flash_opcode, u32 buf_size)
84517482 2434{
b31c50a7 2435 struct be_mcc_wrb *wrb;
3f0d4560 2436 struct be_cmd_write_flashrom *req;
84517482
AK		 2437 int status;
2438
b31c50a7 2439 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2440 adapter->flash_status = 0;
b31c50a7
SP		 2441
2442 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2443 if (!wrb) {
2444 status = -EBUSY;
2892d9c2 2445 goto err_unlock;
713d0394
SP		 2446 }
2447 req = cmd->va;
84517482 2448
106df1e3 2449 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2450 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2451 cmd);
84517482
AK		 2452
2453 req->params.op_type = cpu_to_le32(flash_type);
2454 req->params.op_code = cpu_to_le32(flash_opcode);
2455 req->params.data_buf_size = cpu_to_le32(buf_size);
2456
dd131e76
SB		 2457 be_mcc_notify(adapter);
2458 spin_unlock_bh(&adapter->mcc_lock);
2459
5eeff635
SR		 2460 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2461 msecs_to_jiffies(40000)))
fd45160c 2462 status = -ETIMEDOUT;
dd131e76
SB		 2463 else
2464 status = adapter->flash_status;
84517482 2465
2892d9c2
DC		 2466 return status;
2467
2468err_unlock:
2469 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2470 return status;
2471}
fa9a6fed 2472
3f0d4560 2473int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
96c9b2e4 2474 u16 optype, int offset)
fa9a6fed
SB		 2475{
2476 struct be_mcc_wrb *wrb;
be716446 2477 struct be_cmd_read_flash_crc *req;
fa9a6fed
SB		 2478 int status;
2479
2480 spin_lock_bh(&adapter->mcc_lock);
2481
2482 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2483 if (!wrb) {
2484 status = -EBUSY;
2485 goto err;
2486 }
fa9a6fed
SB		 2487 req = embedded_payload(wrb);
2488
106df1e3 2489 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2490 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2491 wrb, NULL);
fa9a6fed 2492
96c9b2e4 2493 req->params.op_type = cpu_to_le32(optype);
fa9a6fed 2494 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710
AK		 2495 req->params.offset = cpu_to_le32(offset);
2496 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2497
2498 status = be_mcc_notify_wait(adapter);
2499 if (!status)
be716446 2500 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2501
713d0394 2502err:
fa9a6fed
SB		 2503 spin_unlock_bh(&adapter->mcc_lock);
2504 return status;
2505}
71d8d1b5 2506
c196b02c 2507int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 2508 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 2509{
2510 struct be_mcc_wrb *wrb;
2511 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2512 int status;
2513
2514 spin_lock_bh(&adapter->mcc_lock);
2515
2516 wrb = wrb_from_mccq(adapter);
2517 if (!wrb) {
2518 status = -EBUSY;
2519 goto err;
2520 }
2521 req = nonemb_cmd->va;
71d8d1b5 2522
106df1e3 2523 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 2524 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2525 wrb, nonemb_cmd);
71d8d1b5
AK		 2526 memcpy(req->magic_mac, mac, ETH_ALEN);
2527
71d8d1b5
AK		 2528 status = be_mcc_notify_wait(adapter);
2529
2530err:
2531 spin_unlock_bh(&adapter->mcc_lock);
2532 return status;
2533}
ff33a6e2 2534
fced9999
SB		 2535int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2536 u8 loopback_type, u8 enable)
2537{
2538 struct be_mcc_wrb *wrb;
2539 struct be_cmd_req_set_lmode *req;
2540 int status;
2541
2542 spin_lock_bh(&adapter->mcc_lock);
2543
2544 wrb = wrb_from_mccq(adapter);
2545 if (!wrb) {
2546 status = -EBUSY;
2547 goto err;
2548 }
2549
2550 req = embedded_payload(wrb);
2551
106df1e3 2552 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2553 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2554 wrb, NULL);
fced9999
SB		 2555
2556 req->src_port = port_num;
2557 req->dest_port = port_num;
2558 req->loopback_type = loopback_type;
2559 req->loopback_state = enable;
2560
2561 status = be_mcc_notify_wait(adapter);
2562err:
2563 spin_unlock_bh(&adapter->mcc_lock);
2564 return status;
2565}
2566
ff33a6e2 2567int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 2568 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2569 u64 pattern)
ff33a6e2
S		 2570{
2571 struct be_mcc_wrb *wrb;
2572 struct be_cmd_req_loopback_test *req;
5eeff635 2573 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 2574 int status;
2575
2576 spin_lock_bh(&adapter->mcc_lock);
2577
2578 wrb = wrb_from_mccq(adapter);
2579 if (!wrb) {
2580 status = -EBUSY;
2581 goto err;
2582 }
2583
2584 req = embedded_payload(wrb);
2585
106df1e3 2586 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2587 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2588 NULL);
ff33a6e2 2589
5eeff635 2590 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 2591 req->pattern = cpu_to_le64(pattern);
2592 req->src_port = cpu_to_le32(port_num);
2593 req->dest_port = cpu_to_le32(port_num);
2594 req->pkt_size = cpu_to_le32(pkt_size);
2595 req->num_pkts = cpu_to_le32(num_pkts);
2596 req->loopback_type = cpu_to_le32(loopback_type);
2597
5eeff635
SR		 2598 be_mcc_notify(adapter);
2599
2600 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 2601
5eeff635
SR		 2602 wait_for_completion(&adapter->et_cmd_compl);
2603 resp = embedded_payload(wrb);
2604 status = le32_to_cpu(resp->status);
2605
2606 return status;
ff33a6e2
S		 2607err:
2608 spin_unlock_bh(&adapter->mcc_lock);
2609 return status;
2610}
2611
2612int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 2613 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 2614{
2615 struct be_mcc_wrb *wrb;
2616 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2617 int status;
2618 int i, j = 0;
2619
2620 spin_lock_bh(&adapter->mcc_lock);
2621
2622 wrb = wrb_from_mccq(adapter);
2623 if (!wrb) {
2624 status = -EBUSY;
2625 goto err;
2626 }
2627 req = cmd->va;
106df1e3 2628 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2629 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2630 cmd);
ff33a6e2
S		 2631
2632 req->pattern = cpu_to_le64(pattern);
2633 req->byte_count = cpu_to_le32(byte_cnt);
2634 for (i = 0; i < byte_cnt; i++) {
2635 req->snd_buff[i] = (u8)(pattern >> (j*8));
2636 j++;
2637 if (j > 7)
2638 j = 0;
2639 }
2640
2641 status = be_mcc_notify_wait(adapter);
2642
2643 if (!status) {
2644 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 2645
ff33a6e2
S		 2646 resp = cmd->va;
2647 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2648 resp->snd_err) {
2649 status = -1;
2650 }
2651 }
2652
2653err:
2654 spin_unlock_bh(&adapter->mcc_lock);
2655 return status;
2656}
368c0ca2 2657
c196b02c 2658int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 2659 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 2660{
2661 struct be_mcc_wrb *wrb;
2662 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 2663 int status;
2664
2665 spin_lock_bh(&adapter->mcc_lock);
2666
2667 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2668 if (!wrb) {
2669 status = -EBUSY;
2670 goto err;
2671 }
368c0ca2 2672 req = nonemb_cmd->va;
368c0ca2 2673
106df1e3 2674 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2675 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2676 nonemb_cmd);
368c0ca2
SB		 2677
2678 status = be_mcc_notify_wait(adapter);
2679
e45ff01d 2680err:
368c0ca2
SB		 2681 spin_unlock_bh(&adapter->mcc_lock);
2682 return status;
2683}
ee3cb629 2684
42f11cf2 2685int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2686{
2687 struct be_mcc_wrb *wrb;
2688 struct be_cmd_req_get_phy_info *req;
306f1348 2689 struct be_dma_mem cmd;
ee3cb629
AK		 2690 int status;
2691
f25b119c
PR		 2692 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2693 CMD_SUBSYSTEM_COMMON))
2694 return -EPERM;
2695
ee3cb629
AK		 2696 spin_lock_bh(&adapter->mcc_lock);
2697
2698 wrb = wrb_from_mccq(adapter);
2699 if (!wrb) {
2700 status = -EBUSY;
2701 goto err;
2702 }
306f1348 2703 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
a2cc4e0b 2704 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
306f1348
SP		 2705 if (!cmd.va) {
2706 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2707 status = -ENOMEM;
2708 goto err;
2709 }
ee3cb629 2710
306f1348 2711 req = cmd.va;
ee3cb629 2712
106df1e3 2713 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2714 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2715 wrb, &cmd);
ee3cb629
AK		 2716
2717 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2718 if (!status) {
2719 struct be_phy_info *resp_phy_info =
2720 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 2721
42f11cf2
AK		 2722 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2723 adapter->phy.interface_type =
306f1348 2724 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2725 adapter->phy.auto_speeds_supported =
2726 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2727 adapter->phy.fixed_speeds_supported =
2728 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2729 adapter->phy.misc_params =
2730 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 2731
2732 if (BE2_chip(adapter)) {
2733 adapter->phy.fixed_speeds_supported =
2734 BE_SUPPORTED_SPEED_10GBPS |
2735 BE_SUPPORTED_SPEED_1GBPS;
2736 }
306f1348 2737 }
a2cc4e0b 2738 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
ee3cb629
AK		 2739err:
2740 spin_unlock_bh(&adapter->mcc_lock);
2741 return status;
2742}
e1d18735
AK		 2743
2744int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2745{
2746 struct be_mcc_wrb *wrb;
2747 struct be_cmd_req_set_qos *req;
2748 int status;
2749
2750 spin_lock_bh(&adapter->mcc_lock);
2751
2752 wrb = wrb_from_mccq(adapter);
2753 if (!wrb) {
2754 status = -EBUSY;
2755 goto err;
2756 }
2757
2758 req = embedded_payload(wrb);
2759
106df1e3 2760 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 2761 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2762
2763 req->hdr.domain = domain;
6bff57a7
AK		 2764 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2765 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2766
2767 status = be_mcc_notify_wait(adapter);
2768
2769err:
2770 spin_unlock_bh(&adapter->mcc_lock);
2771 return status;
2772}
9e1453c5
AK		 2773
2774int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2775{
2776 struct be_mcc_wrb *wrb;
2777 struct be_cmd_req_cntl_attribs *req;
2778 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2779 int status;
2780 int payload_len = max(sizeof(*req), sizeof(*resp));
2781 struct mgmt_controller_attrib *attribs;
2782 struct be_dma_mem attribs_cmd;
2783
d98ef50f
SR		 2784 if (mutex_lock_interruptible(&adapter->mbox_lock))
2785 return -1;
2786
9e1453c5
AK		 2787 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2788 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2789 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
a2cc4e0b 2790 &attribs_cmd.dma);
9e1453c5 2791 if (!attribs_cmd.va) {
a2cc4e0b 2792 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 2793 status = -ENOMEM;
2794 goto err;
9e1453c5
AK		 2795 }
2796
9e1453c5
AK		 2797 wrb = wrb_from_mbox(adapter);
2798 if (!wrb) {
2799 status = -EBUSY;
2800 goto err;
2801 }
2802 req = attribs_cmd.va;
9e1453c5 2803
106df1e3 2804 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2805 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2806 wrb, &attribs_cmd);
9e1453c5
AK		 2807
2808 status = be_mbox_notify_wait(adapter);
2809 if (!status) {
43d620c8 2810 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2811 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2812 }
2813
2814err:
2815 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 2816 if (attribs_cmd.va)
2817 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2818 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 2819 return status;
2820}
2e588f84
SP		 2821
2822/* Uses mbox */
2dc1deb6 2823int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2824{
2825 struct be_mcc_wrb *wrb;
2826 struct be_cmd_req_set_func_cap *req;
2827 int status;
2828
2829 if (mutex_lock_interruptible(&adapter->mbox_lock))
2830 return -1;
2831
2832 wrb = wrb_from_mbox(adapter);
2833 if (!wrb) {
2834 status = -EBUSY;
2835 goto err;
2836 }
2837
2838 req = embedded_payload(wrb);
2839
106df1e3 2840 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2841 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2842 sizeof(*req), wrb, NULL);
2e588f84
SP		 2843
2844 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2845 CAPABILITY_BE3_NATIVE_ERX_API);
2846 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2847
2848 status = be_mbox_notify_wait(adapter);
2849 if (!status) {
2850 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 2851
2e588f84
SP		 2852 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2853 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 2854 if (!adapter->be3_native)
2855 dev_warn(&adapter->pdev->dev,
2856 "adapter not in advanced mode\n");
2e588f84
SP		 2857 }
2858err:
2859 mutex_unlock(&adapter->mbox_lock);
2860 return status;
2861}
590c391d 2862
f25b119c
PR		 2863/* Get privilege(s) for a function */
2864int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2865 u32 domain)
2866{
2867 struct be_mcc_wrb *wrb;
2868 struct be_cmd_req_get_fn_privileges *req;
2869 int status;
2870
2871 spin_lock_bh(&adapter->mcc_lock);
2872
2873 wrb = wrb_from_mccq(adapter);
2874 if (!wrb) {
2875 status = -EBUSY;
2876 goto err;
2877 }
2878
2879 req = embedded_payload(wrb);
2880
2881 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2882 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2883 wrb, NULL);
2884
2885 req->hdr.domain = domain;
2886
2887 status = be_mcc_notify_wait(adapter);
2888 if (!status) {
2889 struct be_cmd_resp_get_fn_privileges *resp =
2890 embedded_payload(wrb);
03d28ffe 2891
f25b119c 2892 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 2893
2894 /* In UMC mode FW does not return right privileges.
2895 * Override with correct privilege equivalent to PF.
2896 */
2897 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2898 be_physfn(adapter))
2899 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 2900 }
2901
2902err:
2903 spin_unlock_bh(&adapter->mcc_lock);
2904 return status;
2905}
2906
04a06028
SP		 2907/* Set privilege(s) for a function */
2908int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2909 u32 domain)
2910{
2911 struct be_mcc_wrb *wrb;
2912 struct be_cmd_req_set_fn_privileges *req;
2913 int status;
2914
2915 spin_lock_bh(&adapter->mcc_lock);
2916
2917 wrb = wrb_from_mccq(adapter);
2918 if (!wrb) {
2919 status = -EBUSY;
2920 goto err;
2921 }
2922
2923 req = embedded_payload(wrb);
2924 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2925 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2926 wrb, NULL);
2927 req->hdr.domain = domain;
2928 if (lancer_chip(adapter))
2929 req->privileges_lancer = cpu_to_le32(privileges);
2930 else
2931 req->privileges = cpu_to_le32(privileges);
2932
2933 status = be_mcc_notify_wait(adapter);
2934err:
2935 spin_unlock_bh(&adapter->mcc_lock);
2936 return status;
2937}
2938
5a712c13
SP		 2939/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2940 * pmac_id_valid: false => pmac_id or MAC address is requested.
2941 * If pmac_id is returned, pmac_id_valid is returned as true
2942 */
1578e777 2943int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 2944 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2945 u8 domain)
590c391d
PR		 2946{
2947 struct be_mcc_wrb *wrb;
2948 struct be_cmd_req_get_mac_list *req;
2949 int status;
2950 int mac_count;
e5e1ee89
PR		 2951 struct be_dma_mem get_mac_list_cmd;
2952 int i;
2953
2954 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2955 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2956 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 2957 get_mac_list_cmd.size,
2958 &get_mac_list_cmd.dma);
e5e1ee89
PR		 2959
2960 if (!get_mac_list_cmd.va) {
2961 dev_err(&adapter->pdev->dev,
a2cc4e0b 2962 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 2963 return -ENOMEM;
2964 }
590c391d
PR		 2965
2966 spin_lock_bh(&adapter->mcc_lock);
2967
2968 wrb = wrb_from_mccq(adapter);
2969 if (!wrb) {
2970 status = -EBUSY;
e5e1ee89 2971 goto out;
590c391d 2972 }
e5e1ee89
PR		 2973
2974 req = get_mac_list_cmd.va;
590c391d
PR		 2975
2976 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 2977 OPCODE_COMMON_GET_MAC_LIST,
2978 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 2979 req->hdr.domain = domain;
e5e1ee89 2980 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 2981 if (*pmac_id_valid) {
2982 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 2983 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 2984 req->perm_override = 0;
2985 } else {
2986 req->perm_override = 1;
2987 }
590c391d
PR		 2988
2989 status = be_mcc_notify_wait(adapter);
2990 if (!status) {
2991 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 2992 get_mac_list_cmd.va;
5a712c13
SP		 2993
2994 if (*pmac_id_valid) {
2995 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2996 ETH_ALEN);
2997 goto out;
2998 }
2999
e5e1ee89
PR		 3000 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3001 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 3002 * or one or more true or pseudo permanant mac addresses.
3003 * If an active mac_id is present, return first active mac_id
3004 * found.
e5e1ee89 3005 */
590c391d 3006 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3007 struct get_list_macaddr *mac_entry;
3008 u16 mac_addr_size;
3009 u32 mac_id;
3010
3011 mac_entry = &resp->macaddr_list[i];
3012 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3013 /* mac_id is a 32 bit value and mac_addr size
3014 * is 6 bytes
3015 */
3016 if (mac_addr_size == sizeof(u32)) {
5a712c13 3017 *pmac_id_valid = true;
e5e1ee89
PR		 3018 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3019 *pmac_id = le32_to_cpu(mac_id);
3020 goto out;
590c391d 3021 }
590c391d 3022 }
1578e777 3023 /* If no active mac_id found, return first mac addr */
5a712c13 3024 *pmac_id_valid = false;
e5e1ee89 3025 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3026 ETH_ALEN);
590c391d
PR		 3027 }
3028
e5e1ee89 3029out:
590c391d 3030 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89 3031 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
a2cc4e0b 3032 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3033 return status;
3034}
3035
a2cc4e0b
SP		 3036int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3037 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3038{
b188f090
SR		 3039 if (!active)
3040 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3041 if_handle, domain);
3175d8c2 3042 if (BEx_chip(adapter))
5a712c13 3043 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3044 if_handle, curr_pmac_id);
3175d8c2
SP		 3045 else
3046 /* Fetch the MAC address using pmac_id */
3047 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3048 &curr_pmac_id,
3049 if_handle, domain);
5a712c13
SP		 3050}
3051
95046b92
SP		 3052int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3053{
3054 int status;
3055 bool pmac_valid = false;
3056
3057 memset(mac, 0, ETH_ALEN);
3058
3175d8c2
SP		 3059 if (BEx_chip(adapter)) {
3060 if (be_physfn(adapter))
3061 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3062 0);
3063 else
3064 status = be_cmd_mac_addr_query(adapter, mac, false,
3065 adapter->if_handle, 0);
3066 } else {
95046b92 3067 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3068 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3069 }
3070
95046b92
SP		 3071 return status;
3072}
3073
590c391d
PR		 3074/* Uses synchronous MCCQ */
3075int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3076 u8 mac_count, u32 domain)
3077{
3078 struct be_mcc_wrb *wrb;
3079 struct be_cmd_req_set_mac_list *req;
3080 int status;
3081 struct be_dma_mem cmd;
3082
3083 memset(&cmd, 0, sizeof(struct be_dma_mem));
3084 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3085 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
a2cc4e0b 3086 &cmd.dma, GFP_KERNEL);
d0320f75 3087 if (!cmd.va)
590c391d 3088 return -ENOMEM;
590c391d
PR		 3089
3090 spin_lock_bh(&adapter->mcc_lock);
3091
3092 wrb = wrb_from_mccq(adapter);
3093 if (!wrb) {
3094 status = -EBUSY;
3095 goto err;
3096 }
3097
3098 req = cmd.va;
3099 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3100 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3101 wrb, &cmd);
590c391d
PR		 3102
3103 req->hdr.domain = domain;
3104 req->mac_count = mac_count;
3105 if (mac_count)
3106 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3107
3108 status = be_mcc_notify_wait(adapter);
3109
3110err:
a2cc4e0b 3111 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
590c391d
PR		 3112 spin_unlock_bh(&adapter->mcc_lock);
3113 return status;
3114}
4762f6ce 3115
3175d8c2
SP		 3116/* Wrapper to delete any active MACs and provision the new mac.
3117 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3118 * current list are active.
3119 */
3120int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3121{
3122 bool active_mac = false;
3123 u8 old_mac[ETH_ALEN];
3124 u32 pmac_id;
3125 int status;
3126
3127 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3128 &pmac_id, if_id, dom);
3129
3175d8c2
SP		 3130 if (!status && active_mac)
3131 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3132
3133 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3134}
3135
f1f3ee1b 3136int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
a77dcb8c 3137 u32 domain, u16 intf_id, u16 hsw_mode)
f1f3ee1b
AK		 3138{
3139 struct be_mcc_wrb *wrb;
3140 struct be_cmd_req_set_hsw_config *req;
3141 void *ctxt;
3142 int status;
3143
3144 spin_lock_bh(&adapter->mcc_lock);
3145
3146 wrb = wrb_from_mccq(adapter);
3147 if (!wrb) {
3148 status = -EBUSY;
3149 goto err;
3150 }
3151
3152 req = embedded_payload(wrb);
3153 ctxt = &req->context;
3154
3155 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3156 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3157 NULL);
f1f3ee1b
AK		 3158
3159 req->hdr.domain = domain;
3160 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3161 if (pvid) {
3162 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3163 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3164 }
a77dcb8c
AK		 3165 if (!BEx_chip(adapter) && hsw_mode) {
3166 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3167 ctxt, adapter->hba_port_num);
3168 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3169 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3170 ctxt, hsw_mode);
3171 }
f1f3ee1b
AK		 3172
3173 be_dws_cpu_to_le(req->context, sizeof(req->context));
3174 status = be_mcc_notify_wait(adapter);
3175
3176err:
3177 spin_unlock_bh(&adapter->mcc_lock);
3178 return status;
3179}
3180
3181/* Get Hyper switch config */
3182int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
a77dcb8c 3183 u32 domain, u16 intf_id, u8 *mode)
f1f3ee1b
AK		 3184{
3185 struct be_mcc_wrb *wrb;
3186 struct be_cmd_req_get_hsw_config *req;
3187 void *ctxt;
3188 int status;
3189 u16 vid;
3190
3191 spin_lock_bh(&adapter->mcc_lock);
3192
3193 wrb = wrb_from_mccq(adapter);
3194 if (!wrb) {
3195 status = -EBUSY;
3196 goto err;
3197 }
3198
3199 req = embedded_payload(wrb);
3200 ctxt = &req->context;
3201
3202 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3203 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3204 NULL);
f1f3ee1b
AK		 3205
3206 req->hdr.domain = domain;
a77dcb8c
AK		 3207 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3208 ctxt, intf_id);
f1f3ee1b 3209 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3210
2c07c1d7 3211 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3212 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3213 ctxt, adapter->hba_port_num);
3214 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3215 }
f1f3ee1b
AK		 3216 be_dws_cpu_to_le(req->context, sizeof(req->context));
3217
3218 status = be_mcc_notify_wait(adapter);
3219 if (!status) {
3220 struct be_cmd_resp_get_hsw_config *resp =
3221 embedded_payload(wrb);
03d28ffe 3222
a2cc4e0b 3223 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3224 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3225 pvid, &resp->context);
a77dcb8c
AK		 3226 if (pvid)
3227 *pvid = le16_to_cpu(vid);
3228 if (mode)
3229 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3230 port_fwd_type, &resp->context);
f1f3ee1b
AK		 3231 }
3232
3233err:
3234 spin_unlock_bh(&adapter->mcc_lock);
3235 return status;
3236}
3237
4762f6ce
AK		 3238int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3239{
3240 struct be_mcc_wrb *wrb;
3241 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3242 int status = 0;
4762f6ce
AK		 3243 struct be_dma_mem cmd;
3244
f25b119c
PR		 3245 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3246 CMD_SUBSYSTEM_ETH))
3247 return -EPERM;
3248
76a9e08e
SR		 3249 if (be_is_wol_excluded(adapter))
3250 return status;
3251
d98ef50f
SR		 3252 if (mutex_lock_interruptible(&adapter->mbox_lock))
3253 return -1;
3254
4762f6ce
AK		 3255 memset(&cmd, 0, sizeof(struct be_dma_mem));
3256 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
a2cc4e0b 3257 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
4762f6ce 3258 if (!cmd.va) {
a2cc4e0b 3259 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3260 status = -ENOMEM;
3261 goto err;
4762f6ce
AK		 3262 }
3263
4762f6ce
AK		 3264 wrb = wrb_from_mbox(adapter);
3265 if (!wrb) {
3266 status = -EBUSY;
3267 goto err;
3268 }
3269
3270 req = cmd.va;
3271
3272 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3273 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 3274 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 3275
3276 req->hdr.version = 1;
3277 req->query_options = BE_GET_WOL_CAP;
3278
3279 status = be_mbox_notify_wait(adapter);
3280 if (!status) {
3281 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 3282
504fbf1e 3283 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 3284
4762f6ce 3285 adapter->wol_cap = resp->wol_settings;
76a9e08e
SR		 3286 if (adapter->wol_cap & BE_WOL_CAP)
3287 adapter->wol_en = true;
4762f6ce
AK		 3288 }
3289err:
3290 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3291 if (cmd.va)
3292 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
4762f6ce 3293 return status;
941a77d5
SK		 3294
3295}
baaa08d1
VV		 3296
3297int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3298{
3299 struct be_dma_mem extfat_cmd;
3300 struct be_fat_conf_params *cfgs;
3301 int status;
3302 int i, j;
3303
3304 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3305 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3306 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3307 &extfat_cmd.dma);
3308 if (!extfat_cmd.va)
3309 return -ENOMEM;
3310
3311 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3312 if (status)
3313 goto err;
3314
3315 cfgs = (struct be_fat_conf_params *)
3316 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3317 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3318 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 3319
baaa08d1
VV		 3320 for (j = 0; j < num_modes; j++) {
3321 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3322 cfgs->module[i].trace_lvl[j].dbg_lvl =
3323 cpu_to_le32(level);
3324 }
3325 }
3326
3327 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3328err:
3329 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3330 extfat_cmd.dma);
3331 return status;
3332}
3333
3334int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3335{
3336 struct be_dma_mem extfat_cmd;
3337 struct be_fat_conf_params *cfgs;
3338 int status, j;
3339 int level = 0;
3340
3341 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3342 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3343 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3344 &extfat_cmd.dma);
3345
3346 if (!extfat_cmd.va) {
3347 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3348 __func__);
3349 goto err;
3350 }
3351
3352 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3353 if (!status) {
3354 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3355 sizeof(struct be_cmd_resp_hdr));
03d28ffe 3356
baaa08d1
VV		 3357 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3358 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3359 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3360 }
3361 }
3362 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3363 extfat_cmd.dma);
3364err:
3365 return level;
3366}
3367
941a77d5
SK		 3368int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3369 struct be_dma_mem *cmd)
3370{
3371 struct be_mcc_wrb *wrb;
3372 struct be_cmd_req_get_ext_fat_caps *req;
3373 int status;
3374
3375 if (mutex_lock_interruptible(&adapter->mbox_lock))
3376 return -1;
3377
3378 wrb = wrb_from_mbox(adapter);
3379 if (!wrb) {
3380 status = -EBUSY;
3381 goto err;
3382 }
3383
3384 req = cmd->va;
3385 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3386 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3387 cmd->size, wrb, cmd);
3388 req->parameter_type = cpu_to_le32(1);
3389
3390 status = be_mbox_notify_wait(adapter);
3391err:
3392 mutex_unlock(&adapter->mbox_lock);
3393 return status;
3394}
3395
3396int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3397 struct be_dma_mem *cmd,
3398 struct be_fat_conf_params *configs)
3399{
3400 struct be_mcc_wrb *wrb;
3401 struct be_cmd_req_set_ext_fat_caps *req;
3402 int status;
3403
3404 spin_lock_bh(&adapter->mcc_lock);
3405
3406 wrb = wrb_from_mccq(adapter);
3407 if (!wrb) {
3408 status = -EBUSY;
3409 goto err;
3410 }
3411
3412 req = cmd->va;
3413 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3414 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3415 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3416 cmd->size, wrb, cmd);
3417
3418 status = be_mcc_notify_wait(adapter);
3419err:
3420 spin_unlock_bh(&adapter->mcc_lock);
3421 return status;
4762f6ce 3422}
6a4ab669 3423
b4e32a71
PR		 3424int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3425{
3426 struct be_mcc_wrb *wrb;
3427 struct be_cmd_req_get_port_name *req;
3428 int status;
3429
3430 if (!lancer_chip(adapter)) {
3431 *port_name = adapter->hba_port_num + '0';
3432 return 0;
3433 }
3434
3435 spin_lock_bh(&adapter->mcc_lock);
3436
3437 wrb = wrb_from_mccq(adapter);
3438 if (!wrb) {
3439 status = -EBUSY;
3440 goto err;
3441 }
3442
3443 req = embedded_payload(wrb);
3444
3445 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3446 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3447 NULL);
3448 req->hdr.version = 1;
3449
3450 status = be_mcc_notify_wait(adapter);
3451 if (!status) {
3452 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 3453
b4e32a71
PR		 3454 *port_name = resp->port_name[adapter->hba_port_num];
3455 } else {
3456 *port_name = adapter->hba_port_num + '0';
3457 }
3458err:
3459 spin_unlock_bh(&adapter->mcc_lock);
3460 return status;
3461}
3462
10cccf60
VV		 3463/* Descriptor type */
3464enum {
3465 FUNC_DESC = 1,
3466 VFT_DESC = 2
3467};
3468
3469static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3470 int desc_type)
abb93951 3471{
150d58c7 3472 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 3473 struct be_nic_res_desc *nic;
abb93951
PR		 3474 int i;
3475
3476 for (i = 0; i < desc_count; i++) {
150d58c7 3477 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 3478 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3479 nic = (struct be_nic_res_desc *)hdr;
3480 if (desc_type == FUNC_DESC ||
3481 (desc_type == VFT_DESC &&
3482 nic->flags & (1 << VFT_SHIFT)))
3483 return nic;
3484 }
abb93951 3485
150d58c7
VV		 3486 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3487 hdr = (void *)hdr + hdr->desc_len;
abb93951 3488 }
150d58c7
VV		 3489 return NULL;
3490}
3491
10cccf60
VV		 3492static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3493{
3494 return be_get_nic_desc(buf, desc_count, VFT_DESC);
3495}
3496
3497static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3498{
3499 return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3500}
3501
150d58c7
VV		 3502static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3503 u32 desc_count)
3504{
3505 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3506 struct be_pcie_res_desc *pcie;
3507 int i;
3508
3509 for (i = 0; i < desc_count; i++) {
3510 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3511 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3512 pcie = (struct be_pcie_res_desc *)hdr;
3513 if (pcie->pf_num == devfn)
3514 return pcie;
3515 }
abb93951 3516
150d58c7
VV		 3517 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3518 hdr = (void *)hdr + hdr->desc_len;
3519 }
950e2958 3520 return NULL;
abb93951
PR		 3521}
3522
f93f160b
VV		 3523static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3524{
3525 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3526 int i;
3527
3528 for (i = 0; i < desc_count; i++) {
3529 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3530 return (struct be_port_res_desc *)hdr;
3531
3532 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3533 hdr = (void *)hdr + hdr->desc_len;
3534 }
3535 return NULL;
3536}
3537
92bf14ab
SP		 3538static void be_copy_nic_desc(struct be_resources *res,
3539 struct be_nic_res_desc *desc)
3540{
3541 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3542 res->max_vlans = le16_to_cpu(desc->vlan_count);
3543 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3544 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3545 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3546 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3547 res->max_evt_qs = le16_to_cpu(desc->eq_count);
3548 /* Clear flags that driver is not interested in */
3549 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3550 BE_IF_CAP_FLAGS_WANT;
3551 /* Need 1 RXQ as the default RXQ */
3552 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3553 res->max_rss_qs -= 1;
3554}
3555
abb93951 3556/* Uses Mbox */
92bf14ab 3557int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 3558{
3559 struct be_mcc_wrb *wrb;
3560 struct be_cmd_req_get_func_config *req;
3561 int status;
3562 struct be_dma_mem cmd;
3563
d98ef50f
SR		 3564 if (mutex_lock_interruptible(&adapter->mbox_lock))
3565 return -1;
3566
abb93951
PR		 3567 memset(&cmd, 0, sizeof(struct be_dma_mem));
3568 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
a2cc4e0b 3569 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
abb93951
PR		 3570 if (!cmd.va) {
3571 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 3572 status = -ENOMEM;
3573 goto err;
abb93951 3574 }
abb93951
PR		 3575
3576 wrb = wrb_from_mbox(adapter);
3577 if (!wrb) {
3578 status = -EBUSY;
3579 goto err;
3580 }
3581
3582 req = cmd.va;
3583
3584 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3585 OPCODE_COMMON_GET_FUNC_CONFIG,
3586 cmd.size, wrb, &cmd);
3587
28710c55
KA		 3588 if (skyhawk_chip(adapter))
3589 req->hdr.version = 1;
3590
abb93951
PR		 3591 status = be_mbox_notify_wait(adapter);
3592 if (!status) {
3593 struct be_cmd_resp_get_func_config *resp = cmd.va;
3594 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 3595 struct be_nic_res_desc *desc;
abb93951 3596
10cccf60 3597 desc = be_get_func_nic_desc(resp->func_param, desc_count);
abb93951
PR		 3598 if (!desc) {
3599 status = -EINVAL;
3600 goto err;
3601 }
3602
d5c18473 3603 adapter->pf_number = desc->pf_num;
92bf14ab 3604 be_copy_nic_desc(res, desc);
abb93951
PR		 3605 }
3606err:
3607 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3608 if (cmd.va)
3609 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3610 return status;
3611}
3612
ba48c0c9 3613/* Will use MBOX only if MCCQ has not been created */
92bf14ab
SP		 3614int be_cmd_get_profile_config(struct be_adapter *adapter,
3615 struct be_resources *res, u8 domain)
a05f99db 3616{
150d58c7 3617 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 3618 struct be_cmd_req_get_profile_config *req;
10cccf60 3619 struct be_nic_res_desc *vf_res;
150d58c7 3620 struct be_pcie_res_desc *pcie;
f93f160b 3621 struct be_port_res_desc *port;
150d58c7 3622 struct be_nic_res_desc *nic;
ba48c0c9 3623 struct be_mcc_wrb wrb = {0};
a05f99db 3624 struct be_dma_mem cmd;
150d58c7 3625 u32 desc_count;
a05f99db
VV		 3626 int status;
3627
3628 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7
VV		 3629 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3630 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3631 if (!cmd.va)
a05f99db 3632 return -ENOMEM;
a05f99db 3633
ba48c0c9
VV		 3634 req = cmd.va;
3635 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3636 OPCODE_COMMON_GET_PROFILE_CONFIG,
3637 cmd.size, &wrb, &cmd);
3638
3639 req->hdr.domain = domain;
3640 if (!lancer_chip(adapter))
3641 req->hdr.version = 1;
3642 req->type = ACTIVE_PROFILE_TYPE;
3643
3644 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 3645 if (status)
3646 goto err;
abb93951 3647
150d58c7
VV		 3648 resp = cmd.va;
3649 desc_count = le32_to_cpu(resp->desc_count);
abb93951 3650
a2cc4e0b
SP		 3651 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3652 desc_count);
150d58c7 3653 if (pcie)
92bf14ab 3654 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 3655
f93f160b
VV		 3656 port = be_get_port_desc(resp->func_param, desc_count);
3657 if (port)
3658 adapter->mc_type = port->mc_type;
3659
10cccf60 3660 nic = be_get_func_nic_desc(resp->func_param, desc_count);
92bf14ab
SP		 3661 if (nic)
3662 be_copy_nic_desc(res, nic);
3663
10cccf60
VV		 3664 vf_res = be_get_vft_desc(resp->func_param, desc_count);
3665 if (vf_res)
3666 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 3667err:
a05f99db 3668 if (cmd.va)
150d58c7 3669 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3670 return status;
3671}
3672
bec84e6b
VV		 3673/* Will use MBOX only if MCCQ has not been created */
3674static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3675 int size, int count, u8 version, u8 domain)
d5c18473 3676{
d5c18473 3677 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 3678 struct be_mcc_wrb wrb = {0};
3679 struct be_dma_mem cmd;
d5c18473
PR		 3680 int status;
3681
bec84e6b
VV		 3682 memset(&cmd, 0, sizeof(struct be_dma_mem));
3683 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
3684 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3685 if (!cmd.va)
3686 return -ENOMEM;
d5c18473 3687
bec84e6b 3688 req = cmd.va;
d5c18473 3689 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 3690 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3691 &wrb, &cmd);
a401801c 3692 req->hdr.version = version;
d5c18473 3693 req->hdr.domain = domain;
bec84e6b 3694 req->desc_count = cpu_to_le32(count);
a401801c
SP		 3695 memcpy(req->desc, desc, size);
3696
bec84e6b
VV		 3697 status = be_cmd_notify_wait(adapter, &wrb);
3698
3699 if (cmd.va)
3700 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
d5c18473
PR		 3701 return status;
3702}
3703
a401801c 3704/* Mark all fields invalid */
bec84e6b 3705static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 3706{
3707 memset(nic, 0, sizeof(*nic));
3708 nic->unicast_mac_count = 0xFFFF;
3709 nic->mcc_count = 0xFFFF;
3710 nic->vlan_count = 0xFFFF;
3711 nic->mcast_mac_count = 0xFFFF;
3712 nic->txq_count = 0xFFFF;
3713 nic->rq_count = 0xFFFF;
3714 nic->rssq_count = 0xFFFF;
3715 nic->lro_count = 0xFFFF;
3716 nic->cq_count = 0xFFFF;
3717 nic->toe_conn_count = 0xFFFF;
3718 nic->eq_count = 0xFFFF;
0f77ba73 3719 nic->iface_count = 0xFFFF;
a401801c 3720 nic->link_param = 0xFF;
0f77ba73 3721 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 3722 nic->acpi_params = 0xFF;
3723 nic->wol_param = 0x0F;
0f77ba73
RN		 3724 nic->tunnel_iface_count = 0xFFFF;
3725 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 3726 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 3727 nic->bw_max = 0xFFFFFFFF;
3728}
3729
bec84e6b
VV		 3730/* Mark all fields invalid */
3731static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3732{
3733 memset(pcie, 0, sizeof(*pcie));
3734 pcie->sriov_state = 0xFF;
3735 pcie->pf_state = 0xFF;
3736 pcie->pf_type = 0xFF;
3737 pcie->num_vfs = 0xFFFF;
3738}
3739
0f77ba73
RN		 3740int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3741 u8 domain)
a401801c 3742{
0f77ba73
RN		 3743 struct be_nic_res_desc nic_desc;
3744 u32 bw_percent;
3745 u16 version = 0;
3746
3747 if (BE3_chip(adapter))
3748 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 3749
0f77ba73
RN		 3750 be_reset_nic_desc(&nic_desc);
3751 nic_desc.pf_num = adapter->pf_number;
3752 nic_desc.vf_num = domain;
3753 if (lancer_chip(adapter)) {
a401801c
SP		 3754 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3755 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3756 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3757 (1 << NOSV_SHIFT);
0f77ba73 3758 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 3759 } else {
0f77ba73
RN		 3760 version = 1;
3761 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3762 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3763 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3764 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3765 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 3766 }
0f77ba73
RN		 3767
3768 return be_cmd_set_profile_config(adapter, &nic_desc,
3769 nic_desc.hdr.desc_len,
bec84e6b
VV		 3770 1, version, domain);
3771}
3772
3773int be_cmd_set_sriov_config(struct be_adapter *adapter,
3774 struct be_resources res, u16 num_vfs)
3775{
3776 struct {
3777 struct be_pcie_res_desc pcie;
3778 struct be_nic_res_desc nic_vft;
3779 } __packed desc;
3780 u16 vf_q_count;
3781
3782 if (BEx_chip(adapter) || lancer_chip(adapter))
3783 return 0;
3784
3785 /* PF PCIE descriptor */
3786 be_reset_pcie_desc(&desc.pcie);
3787 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3788 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3789 desc.pcie.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3790 desc.pcie.pf_num = adapter->pdev->devfn;
3791 desc.pcie.sriov_state = num_vfs ? 1 : 0;
3792 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3793
3794 /* VF NIC Template descriptor */
3795 be_reset_nic_desc(&desc.nic_vft);
3796 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3797 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3798 desc.nic_vft.flags = (1 << VFT_SHIFT) | (1 << IMM_SHIFT) |
3799 (1 << NOSV_SHIFT);
3800 desc.nic_vft.pf_num = adapter->pdev->devfn;
3801 desc.nic_vft.vf_num = 0;
3802
3803 if (num_vfs && res.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3804 /* If number of VFs requested is 8 less than max supported,
3805 * assign 8 queue pairs to the PF and divide the remaining
3806 * resources evenly among the VFs
3807 */
3808 if (num_vfs < (be_max_vfs(adapter) - 8))
3809 vf_q_count = (res.max_rss_qs - 8) / num_vfs;
3810 else
3811 vf_q_count = res.max_rss_qs / num_vfs;
3812
3813 desc.nic_vft.rq_count = cpu_to_le16(vf_q_count);
3814 desc.nic_vft.txq_count = cpu_to_le16(vf_q_count);
3815 desc.nic_vft.rssq_count = cpu_to_le16(vf_q_count - 1);
3816 desc.nic_vft.cq_count = cpu_to_le16(3 * vf_q_count);
3817 } else {
3818 desc.nic_vft.txq_count = cpu_to_le16(1);
3819 desc.nic_vft.rq_count = cpu_to_le16(1);
3820 desc.nic_vft.rssq_count = cpu_to_le16(0);
3821 /* One CQ for each TX, RX and MCCQ */
3822 desc.nic_vft.cq_count = cpu_to_le16(3);
3823 }
3824
3825 return be_cmd_set_profile_config(adapter, &desc,
3826 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 3827}
3828
3829int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3830{
3831 struct be_mcc_wrb *wrb;
3832 struct be_cmd_req_manage_iface_filters *req;
3833 int status;
3834
3835 if (iface == 0xFFFFFFFF)
3836 return -1;
3837
3838 spin_lock_bh(&adapter->mcc_lock);
3839
3840 wrb = wrb_from_mccq(adapter);
3841 if (!wrb) {
3842 status = -EBUSY;
3843 goto err;
3844 }
3845 req = embedded_payload(wrb);
3846
3847 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3848 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3849 wrb, NULL);
3850 req->op = op;
3851 req->target_iface_id = cpu_to_le32(iface);
3852
3853 status = be_mcc_notify_wait(adapter);
3854err:
3855 spin_unlock_bh(&adapter->mcc_lock);
3856 return status;
3857}
3858
3859int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3860{
3861 struct be_port_res_desc port_desc;
3862
3863 memset(&port_desc, 0, sizeof(port_desc));
3864 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3865 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3866 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3867 port_desc.link_num = adapter->hba_port_num;
3868 if (port) {
3869 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3870 (1 << RCVID_SHIFT);
3871 port_desc.nv_port = swab16(port);
3872 } else {
3873 port_desc.nv_flags = NV_TYPE_DISABLED;
3874 port_desc.nv_port = 0;
3875 }
3876
3877 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 3878 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 3879}
3880
4c876616
SP		 3881int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3882 int vf_num)
3883{
3884 struct be_mcc_wrb *wrb;
3885 struct be_cmd_req_get_iface_list *req;
3886 struct be_cmd_resp_get_iface_list *resp;
3887 int status;
3888
3889 spin_lock_bh(&adapter->mcc_lock);
3890
3891 wrb = wrb_from_mccq(adapter);
3892 if (!wrb) {
3893 status = -EBUSY;
3894 goto err;
3895 }
3896 req = embedded_payload(wrb);
3897
3898 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3899 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3900 wrb, NULL);
3901 req->hdr.domain = vf_num + 1;
3902
3903 status = be_mcc_notify_wait(adapter);
3904 if (!status) {
3905 resp = (struct be_cmd_resp_get_iface_list *)req;
3906 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3907 }
3908
3909err:
3910 spin_unlock_bh(&adapter->mcc_lock);
3911 return status;
3912}
3913
5c510811
SK		 3914static int lancer_wait_idle(struct be_adapter *adapter)
3915{
3916#define SLIPORT_IDLE_TIMEOUT 30
3917 u32 reg_val;
3918 int status = 0, i;
3919
3920 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3921 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3922 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3923 break;
3924
3925 ssleep(1);
3926 }
3927
3928 if (i == SLIPORT_IDLE_TIMEOUT)
3929 status = -1;
3930
3931 return status;
3932}
3933
3934int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3935{
3936 int status = 0;
3937
3938 status = lancer_wait_idle(adapter);
3939 if (status)
3940 return status;
3941
3942 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3943
3944 return status;
3945}
3946
3947/* Routine to check whether dump image is present or not */
3948bool dump_present(struct be_adapter *adapter)
3949{
3950 u32 sliport_status = 0;
3951
3952 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3953 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3954}
3955
3956int lancer_initiate_dump(struct be_adapter *adapter)
3957{
f0613380 3958 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 3959 int status;
3960
f0613380
KA		 3961 if (dump_present(adapter)) {
3962 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
3963 return -EEXIST;
3964 }
3965
5c510811
SK		 3966 /* give firmware reset and diagnostic dump */
3967 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3968 PHYSDEV_CONTROL_DD_MASK);
3969 if (status < 0) {
f0613380 3970 dev_err(dev, "FW reset failed\n");
5c510811
SK		 3971 return status;
3972 }
3973
3974 status = lancer_wait_idle(adapter);
3975 if (status)
3976 return status;
3977
3978 if (!dump_present(adapter)) {
f0613380
KA		 3979 dev_err(dev, "FW dump not generated\n");
3980 return -EIO;
5c510811
SK		 3981 }
3982
3983 return 0;
3984}
3985
f0613380
KA		 3986int lancer_delete_dump(struct be_adapter *adapter)
3987{
3988 int status;
3989
3990 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
3991 return be_cmd_status(status);
3992}
3993
dcf7ebba
PR		 3994/* Uses sync mcc */
3995int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3996{
3997 struct be_mcc_wrb *wrb;
3998 struct be_cmd_enable_disable_vf *req;
3999 int status;
4000
0599863d 4001 if (BEx_chip(adapter))
dcf7ebba
PR		 4002 return 0;
4003
4004 spin_lock_bh(&adapter->mcc_lock);
4005
4006 wrb = wrb_from_mccq(adapter);
4007 if (!wrb) {
4008 status = -EBUSY;
4009 goto err;
4010 }
4011
4012 req = embedded_payload(wrb);
4013
4014 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4015 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4016 wrb, NULL);
4017
4018 req->hdr.domain = domain;
4019 req->enable = 1;
4020 status = be_mcc_notify_wait(adapter);
4021err:
4022 spin_unlock_bh(&adapter->mcc_lock);
4023 return status;
4024}
4025
68c45a2d
SK		 4026int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4027{
4028 struct be_mcc_wrb *wrb;
4029 struct be_cmd_req_intr_set *req;
4030 int status;
4031
4032 if (mutex_lock_interruptible(&adapter->mbox_lock))
4033 return -1;
4034
4035 wrb = wrb_from_mbox(adapter);
4036
4037 req = embedded_payload(wrb);
4038
4039 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4040 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4041 wrb, NULL);
4042
4043 req->intr_enabled = intr_enable;
4044
4045 status = be_mbox_notify_wait(adapter);
4046
4047 mutex_unlock(&adapter->mbox_lock);
4048 return status;
4049}
4050
542963b7
VV		 4051/* Uses MBOX */
4052int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4053{
4054 struct be_cmd_req_get_active_profile *req;
4055 struct be_mcc_wrb *wrb;
4056 int status;
4057
4058 if (mutex_lock_interruptible(&adapter->mbox_lock))
4059 return -1;
4060
4061 wrb = wrb_from_mbox(adapter);
4062 if (!wrb) {
4063 status = -EBUSY;
4064 goto err;
4065 }
4066
4067 req = embedded_payload(wrb);
4068
4069 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4070 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4071 wrb, NULL);
4072
4073 status = be_mbox_notify_wait(adapter);
4074 if (!status) {
4075 struct be_cmd_resp_get_active_profile *resp =
4076 embedded_payload(wrb);
03d28ffe 4077
542963b7
VV		 4078 *profile_id = le16_to_cpu(resp->active_profile_id);
4079 }
4080
4081err:
4082 mutex_unlock(&adapter->mbox_lock);
4083 return status;
4084}
4085
bdce2ad7
SR		 4086int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4087 int link_state, u8 domain)
4088{
4089 struct be_mcc_wrb *wrb;
4090 struct be_cmd_req_set_ll_link *req;
4091 int status;
4092
4093 if (BEx_chip(adapter) || lancer_chip(adapter))
4094 return 0;
4095
4096 spin_lock_bh(&adapter->mcc_lock);
4097
4098 wrb = wrb_from_mccq(adapter);
4099 if (!wrb) {
4100 status = -EBUSY;
4101 goto err;
4102 }
4103
4104 req = embedded_payload(wrb);
4105
4106 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4107 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4108 sizeof(*req), wrb, NULL);
4109
4110 req->hdr.version = 1;
4111 req->hdr.domain = domain;
4112
4113 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4114 req->link_config |= 1;
4115
4116 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4117 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4118
4119 status = be_mcc_notify_wait(adapter);
4120err:
4121 spin_unlock_bh(&adapter->mcc_lock);
4122 return status;
4123}
4124
6a4ab669 4125int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 4126 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 4127{
4128 struct be_adapter *adapter = netdev_priv(netdev_handle);
4129 struct be_mcc_wrb *wrb;
504fbf1e 4130 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 4131 struct be_cmd_req_hdr *req;
4132 struct be_cmd_resp_hdr *resp;
4133 int status;
4134
4135 spin_lock_bh(&adapter->mcc_lock);
4136
4137 wrb = wrb_from_mccq(adapter);
4138 if (!wrb) {
4139 status = -EBUSY;
4140 goto err;
4141 }
4142 req = embedded_payload(wrb);
4143 resp = embedded_payload(wrb);
4144
4145 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4146 hdr->opcode, wrb_payload_size, wrb, NULL);
4147 memcpy(req, wrb_payload, wrb_payload_size);
4148 be_dws_cpu_to_le(req, wrb_payload_size);
4149
4150 status = be_mcc_notify_wait(adapter);
4151 if (cmd_status)
4152 *cmd_status = (status & 0xffff);
4153 if (ext_status)
4154 *ext_status = 0;
4155 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4156 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4157err:
4158 spin_unlock_bh(&adapter->mcc_lock);
4159 return status;
4160}
4161EXPORT_SYMBOL(be_roce_mcc_cmd);
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