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be2net: Avoid unnecessary firmware updates of multicast list
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
7dfbe7d7 2 * Copyright (C) 2005 - 2016 Broadcom
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
51d1f98a
AK		 22char *be_misconfig_evt_port_state[] = {
23 "Physical Link is functional",
24 "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
25 "Optics of two types installed – Remove one optic or install matching pair of optics.",
26 "Incompatible optics – Replace with compatible optics for card to function.",
27 "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
28 "Uncertified optics – Replace with Avago-certified optics to enable link operation."
21252377
VV		 29};
30
51d1f98a
AK		 31static char *be_port_misconfig_evt_severity[] = {
32 "KERN_WARN",
33 "KERN_INFO",
34 "KERN_ERR",
35 "KERN_WARN"
36};
37
38static char *phy_state_oper_desc[] = {
39 "Link is non-operational",
40 "Link is operational",
21252377
VV		 41 ""
42};
43
f25b119c
PR		 44static struct be_cmd_priv_map cmd_priv_map[] = {
45 {
46 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
47 CMD_SUBSYSTEM_ETH,
48 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_GET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_COMMON_SET_FLOW_CONTROL,
59 CMD_SUBSYSTEM_COMMON,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_ETH_GET_PPORT_STATS,
65 CMD_SUBSYSTEM_ETH,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 },
69 {
70 OPCODE_COMMON_GET_PHY_DETAILS,
71 CMD_SUBSYSTEM_COMMON,
72 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
73 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
2e365b1b
SK		 74 },
75 {
76 OPCODE_LOWLEVEL_HOST_DDR_DMA,
77 CMD_SUBSYSTEM_LOWLEVEL,
78 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
79 },
80 {
81 OPCODE_LOWLEVEL_LOOPBACK_TEST,
82 CMD_SUBSYSTEM_LOWLEVEL,
83 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
84 },
85 {
86 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
87 CMD_SUBSYSTEM_LOWLEVEL,
88 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
89 },
884476be
SK		 90 {
91 OPCODE_COMMON_SET_HSW_CONFIG,
92 CMD_SUBSYSTEM_COMMON,
93 BE_PRIV_DEVCFG | BE_PRIV_VHADM
94 },
f25b119c
PR		 95};
96
a2cc4e0b 97static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 98{
99 int i;
100 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
101 u32 cmd_privileges = adapter->cmd_privileges;
102
103 for (i = 0; i < num_entries; i++)
104 if (opcode == cmd_priv_map[i].opcode &&
105 subsystem == cmd_priv_map[i].subsystem)
106 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
107 return false;
108
109 return true;
110}
111
3de09455
SK		 112static inline void *embedded_payload(struct be_mcc_wrb *wrb)
113{
114 return wrb->payload.embedded_payload;
115}
609ff3bb 116
efaa408e 117static int be_mcc_notify(struct be_adapter *adapter)
5fb379ee 118{
8788fdc2 119 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 120 u32 val = 0;
121
954f6825 122 if (be_check_error(adapter, BE_ERROR_ANY))
efaa408e 123 return -EIO;
7acc2087 124
5fb379ee
SP		 125 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
126 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 127
128 wmb();
8788fdc2 129 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
efaa408e
SR		 130
131 return 0;
5fb379ee
SP		 132}
133
134/* To check if valid bit is set, check the entire word as we don't know
135 * the endianness of the data (old entry is host endian while a new entry is
136 * little endian) */
efd2e40a 137static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 138{
9e9ff4b7
SP		 139 u32 flags;
140
5fb379ee 141 if (compl->flags != 0) {
9e9ff4b7
SP		 142 flags = le32_to_cpu(compl->flags);
143 if (flags & CQE_FLAGS_VALID_MASK) {
144 compl->flags = flags;
145 return true;
146 }
5fb379ee 147 }
9e9ff4b7 148 return false;
5fb379ee
SP		 149}
150
151/* Need to reset the entire word that houses the valid bit */
efd2e40a 152static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 153{
154 compl->flags = 0;
155}
156
652bf646
PR		 157static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
158{
159 unsigned long addr;
160
161 addr = tag1;
162 addr = ((addr << 16) << 16) | tag0;
163 return (void *)addr;
164}
165
4c60005f
KA		 166static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
167{
168 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
169 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
170 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
77be8c1c 171 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
4c60005f
KA		 172 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
173 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
174 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
175 return true;
176 else
177 return false;
178}
179
559b633f
SP		 180/* Place holder for all the async MCC cmds wherein the caller is not in a busy
181 * loop (has not issued be_mcc_notify_wait())
182 */
183static void be_async_cmd_process(struct be_adapter *adapter,
184 struct be_mcc_compl *compl,
185 struct be_cmd_resp_hdr *resp_hdr)
186{
187 enum mcc_base_status base_status = base_status(compl->status);
188 u8 opcode = 0, subsystem = 0;
189
190 if (resp_hdr) {
191 opcode = resp_hdr->opcode;
192 subsystem = resp_hdr->subsystem;
193 }
194
195 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
196 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
197 complete(&adapter->et_cmd_compl);
198 return;
199 }
200
9c855975
SR		 201 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
202 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
203 complete(&adapter->et_cmd_compl);
204 return;
205 }
206
559b633f
SP		 207 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
208 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
209 subsystem == CMD_SUBSYSTEM_COMMON) {
210 adapter->flash_status = compl->status;
211 complete(&adapter->et_cmd_compl);
212 return;
213 }
214
215 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
216 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
217 subsystem == CMD_SUBSYSTEM_ETH &&
218 base_status == MCC_STATUS_SUCCESS) {
219 be_parse_stats(adapter);
220 adapter->stats_cmd_sent = false;
221 return;
222 }
223
224 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
225 subsystem == CMD_SUBSYSTEM_COMMON) {
226 if (base_status == MCC_STATUS_SUCCESS) {
227 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
228 (void *)resp_hdr;
29e9122b 229 adapter->hwmon_info.be_on_die_temp =
559b633f
SP		 230 resp->on_die_temperature;
231 } else {
232 adapter->be_get_temp_freq = 0;
29e9122b
VD		 233 adapter->hwmon_info.be_on_die_temp =
234 BE_INVALID_DIE_TEMP;
559b633f
SP		 235 }
236 return;
237 }
238}
239
8788fdc2 240static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 241 struct be_mcc_compl *compl)
5fb379ee 242{
4c60005f
KA		 243 enum mcc_base_status base_status;
244 enum mcc_addl_status addl_status;
652bf646
PR		 245 struct be_cmd_resp_hdr *resp_hdr;
246 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 247
248 /* Just swap the status to host endian; mcc tag is opaquely copied
249 * from mcc_wrb */
250 be_dws_le_to_cpu(compl, 4);
251
4c60005f
KA		 252 base_status = base_status(compl->status);
253 addl_status = addl_status(compl->status);
96c9b2e4 254
652bf646 255 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 256 if (resp_hdr) {
257 opcode = resp_hdr->opcode;
258 subsystem = resp_hdr->subsystem;
259 }
260
559b633f 261 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 262
559b633f
SP		 263 if (base_status != MCC_STATUS_SUCCESS &&
264 !be_skip_err_log(opcode, base_status, addl_status)) {
fa5c867d
SR		 265 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
266 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
97f1d8cd 267 dev_warn(&adapter->pdev->dev,
522609f2 268 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 269 opcode, subsystem);
2b3f291b 270 } else {
97f1d8cd
VV		 271 dev_err(&adapter->pdev->dev,
272 "opcode %d-%d failed:status %d-%d\n",
4c60005f 273 opcode, subsystem, base_status, addl_status);
2b3f291b 274 }
5fb379ee 275 }
4c60005f 276 return compl->status;
5fb379ee
SP		 277}
278
a8f447bd 279/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 280static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 281 struct be_mcc_compl *compl)
a8f447bd 282{
3acf19d9
SP		 283 struct be_async_event_link_state *evt =
284 (struct be_async_event_link_state *)compl;
285
b236916a 286 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 287 adapter->phy.link_speed = -1;
b236916a 288
bdce2ad7
SR		 289 /* On BEx the FW does not send a separate link status
290 * notification for physical and logical link.
291 * On other chips just process the logical link
292 * status notification
293 */
294 if (!BEx_chip(adapter) &&
2e177a5c
PR		 295 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
296 return;
297
b236916a
AK		 298 /* For the initial link status do not rely on the ASYNC event as
299 * it may not be received in some cases.
300 */
301 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 302 be_link_status_update(adapter,
303 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 304}
305
21252377
VV		 306static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
307 struct be_mcc_compl *compl)
308{
309 struct be_async_event_misconfig_port *evt =
310 (struct be_async_event_misconfig_port *)compl;
51d1f98a
AK		 311 u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
312 u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
313 u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
21252377 314 struct device *dev = &adapter->pdev->dev;
51d1f98a
AK		 315 u8 msg_severity = DEFAULT_MSG_SEVERITY;
316 u8 phy_state_info;
317 u8 new_phy_state;
318
319 new_phy_state =
320 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
321
322 if (new_phy_state == adapter->phy_state)
323 return;
324
325 adapter->phy_state = new_phy_state;
21252377 326
51d1f98a
AK		 327 /* for older fw that doesn't populate link effect data */
328 if (!sfp_misconfig_evt_word2)
329 goto log_message;
21252377 330
51d1f98a
AK		 331 phy_state_info =
332 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
333
334 if (phy_state_info & PHY_STATE_INFO_VALID) {
335 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
336
337 if (be_phy_unqualified(new_phy_state))
338 phy_oper_state = (phy_state_info & PHY_STATE_OPER);
339 }
340
341log_message:
21252377
VV		 342 /* Log an error message that would allow a user to determine
343 * whether the SFPs have an issue
344 */
51d1f98a
AK		 345 if (be_phy_state_unknown(new_phy_state))
346 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
347 "Port %c: Unrecognized Optics state: 0x%x. %s",
348 adapter->port_name,
349 new_phy_state,
350 phy_state_oper_desc[phy_oper_state]);
351 else
352 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
353 "Port %c: %s %s",
354 adapter->port_name,
355 be_misconfig_evt_port_state[new_phy_state],
356 phy_state_oper_desc[phy_oper_state]);
357
358 /* Log Vendor name and part no. if a misconfigured SFP is detected */
359 if (be_phy_misconfigured(new_phy_state))
360 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
21252377
VV		 361}
362
cc4ce020
SK		 363/* Grp5 CoS Priority evt */
364static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 365 struct be_mcc_compl *compl)
cc4ce020 366{
3acf19d9
SP		 367 struct be_async_event_grp5_cos_priority *evt =
368 (struct be_async_event_grp5_cos_priority *)compl;
369
cc4ce020
SK		 370 if (evt->valid) {
371 adapter->vlan_prio_bmap = evt->available_priority_bmap;
fdf81bfb 372 adapter->recommended_prio_bits =
cc4ce020
SK		 373 evt->reco_default_priority << VLAN_PRIO_SHIFT;
374 }
375}
376
323ff71e 377/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 378static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 379 struct be_mcc_compl *compl)
cc4ce020 380{
3acf19d9
SP		 381 struct be_async_event_grp5_qos_link_speed *evt =
382 (struct be_async_event_grp5_qos_link_speed *)compl;
383
323ff71e
SP		 384 if (adapter->phy.link_speed >= 0 &&
385 evt->physical_port == adapter->port_num)
386 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 387}
388
3968fa1e
AK		 389/*Grp5 PVID evt*/
390static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 391 struct be_mcc_compl *compl)
3968fa1e 392{
3acf19d9
SP		 393 struct be_async_event_grp5_pvid_state *evt =
394 (struct be_async_event_grp5_pvid_state *)compl;
395
bdac85b5 396 if (evt->enabled) {
939cf306 397 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 398 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
399 } else {
3968fa1e 400 adapter->pvid = 0;
bdac85b5 401 }
3968fa1e
AK		 402}
403
760c295e
VD		 404#define MGMT_ENABLE_MASK 0x4
405static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
406 struct be_mcc_compl *compl)
407{
408 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
409 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
410
411 if (evt_dw1 & MGMT_ENABLE_MASK) {
412 adapter->flags |= BE_FLAGS_OS2BMC;
413 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
414 } else {
415 adapter->flags &= ~BE_FLAGS_OS2BMC;
416 }
417}
418
cc4ce020 419static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 420 struct be_mcc_compl *compl)
cc4ce020 421{
3acf19d9
SP		 422 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
423 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 424
425 switch (event_type) {
426 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 427 be_async_grp5_cos_priority_process(adapter, compl);
428 break;
cc4ce020 429 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 430 be_async_grp5_qos_speed_process(adapter, compl);
431 break;
3968fa1e 432 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 433 be_async_grp5_pvid_state_process(adapter, compl);
434 break;
760c295e
VD		 435 /* Async event to disable/enable os2bmc and/or mac-learning */
436 case ASYNC_EVENT_FW_CONTROL:
437 be_async_grp5_fw_control_process(adapter, compl);
438 break;
cc4ce020 439 default:
cc4ce020
SK		 440 break;
441 }
442}
443
bc0c3405 444static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 445 struct be_mcc_compl *cmp)
bc0c3405
AK		 446{
447 u8 event_type = 0;
504fbf1e 448 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 449
3acf19d9
SP		 450 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
451 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 452
453 switch (event_type) {
454 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
455 if (evt->valid)
456 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
457 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
458 break;
459 default:
05ccaa2b
VV		 460 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
461 event_type);
bc0c3405
AK		 462 break;
463 }
464}
465
21252377
VV		 466static void be_async_sliport_evt_process(struct be_adapter *adapter,
467 struct be_mcc_compl *cmp)
468{
469 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
470 ASYNC_EVENT_TYPE_MASK;
471
472 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
473 be_async_port_misconfig_event_process(adapter, cmp);
474}
475
3acf19d9 476static inline bool is_link_state_evt(u32 flags)
a8f447bd 477{
3acf19d9
SP		 478 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
479 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 480}
5fb379ee 481
3acf19d9 482static inline bool is_grp5_evt(u32 flags)
cc4ce020 483{
3acf19d9
SP		 484 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
485 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 486}
487
3acf19d9 488static inline bool is_dbg_evt(u32 flags)
bc0c3405 489{
3acf19d9
SP		 490 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
491 ASYNC_EVENT_CODE_QNQ;
492}
493
21252377
VV		 494static inline bool is_sliport_evt(u32 flags)
495{
496 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
497 ASYNC_EVENT_CODE_SLIPORT;
498}
499
3acf19d9
SP		 500static void be_mcc_event_process(struct be_adapter *adapter,
501 struct be_mcc_compl *compl)
502{
503 if (is_link_state_evt(compl->flags))
504 be_async_link_state_process(adapter, compl);
505 else if (is_grp5_evt(compl->flags))
506 be_async_grp5_evt_process(adapter, compl);
507 else if (is_dbg_evt(compl->flags))
508 be_async_dbg_evt_process(adapter, compl);
21252377
VV		 509 else if (is_sliport_evt(compl->flags))
510 be_async_sliport_evt_process(adapter, compl);
bc0c3405
AK		 511}
512
efd2e40a 513static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 514{
8788fdc2 515 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 516 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 517
518 if (be_mcc_compl_is_new(compl)) {
519 queue_tail_inc(mcc_cq);
520 return compl;
521 }
522 return NULL;
523}
524
7a1e9b20
SP		 525void be_async_mcc_enable(struct be_adapter *adapter)
526{
527 spin_lock_bh(&adapter->mcc_cq_lock);
528
529 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
530 adapter->mcc_obj.rearm_cq = true;
531
532 spin_unlock_bh(&adapter->mcc_cq_lock);
533}
534
535void be_async_mcc_disable(struct be_adapter *adapter)
536{
a323d9bf
SP		 537 spin_lock_bh(&adapter->mcc_cq_lock);
538
7a1e9b20 539 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 540 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
541
542 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 543}
544
10ef9ab4 545int be_process_mcc(struct be_adapter *adapter)
5fb379ee 546{
efd2e40a 547 struct be_mcc_compl *compl;
10ef9ab4 548 int num = 0, status = 0;
7a1e9b20 549 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 550
072a9c48 551 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 552
8788fdc2 553 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 554 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 555 be_mcc_event_process(adapter, compl);
b31c50a7 556 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 557 status = be_mcc_compl_process(adapter, compl);
558 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 559 }
560 be_mcc_compl_use(compl);
561 num++;
562 }
b31c50a7 563
10ef9ab4
SP		 564 if (num)
565 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
566
072a9c48 567 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 568 return status;
5fb379ee
SP		 569}
570
6ac7b687 571/* Wait till no more pending mcc requests are present */
b31c50a7 572static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 573{
b31c50a7 574#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 575 int i, status = 0;
f31e50a8
SP		 576 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
577
6ac7b687 578 for (i = 0; i < mcc_timeout; i++) {
954f6825 579 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 580 return -EIO;
581
072a9c48 582 local_bh_disable();
10ef9ab4 583 status = be_process_mcc(adapter);
072a9c48 584 local_bh_enable();
b31c50a7 585
f31e50a8 586 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 587 break;
588 udelay(100);
589 }
b31c50a7 590 if (i == mcc_timeout) {
6589ade0 591 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 592 be_set_error(adapter, BE_ERROR_FW);
652bf646 593 return -EIO;
b31c50a7 594 }
f31e50a8 595 return status;
6ac7b687
SP		 596}
597
598/* Notify MCC requests and wait for completion */
b31c50a7 599static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 600{
652bf646
PR		 601 int status;
602 struct be_mcc_wrb *wrb;
603 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
b0fd2eb2 604 u32 index = mcc_obj->q.head;
652bf646
PR		 605 struct be_cmd_resp_hdr *resp;
606
607 index_dec(&index, mcc_obj->q.len);
608 wrb = queue_index_node(&mcc_obj->q, index);
609
610 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
611
efaa408e
SR		 612 status = be_mcc_notify(adapter);
613 if (status)
614 goto out;
652bf646
PR		 615
616 status = be_mcc_wait_compl(adapter);
617 if (status == -EIO)
618 goto out;
619
4c60005f
KA		 620 status = (resp->base_status |
621 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
622 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 623out:
624 return status;
6ac7b687
SP		 625}
626
5f0b849e 627static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 628{
f25b03a7 629 int msecs = 0;
6b7c5b94
SP		 630 u32 ready;
631
632 do {
954f6825 633 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 634 return -EIO;
635
cf588477 636 ready = ioread32(db);
434b3648 637 if (ready == 0xffffffff)
cf588477 638 return -1;
cf588477
SP		 639
640 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 641 if (ready)
642 break;
643
f25b03a7 644 if (msecs > 4000) {
6589ade0 645 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 646 be_set_error(adapter, BE_ERROR_FW);
f67ef7ba 647 be_detect_error(adapter);
6b7c5b94
SP		 648 return -1;
649 }
650
1dbf53a2 651 msleep(1);
f25b03a7 652 msecs++;
6b7c5b94
SP		 653 } while (true);
654
655 return 0;
656}
657
658/*
659 * Insert the mailbox address into the doorbell in two steps
5fb379ee 660 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 661 */
b31c50a7 662static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 663{
664 int status;
6b7c5b94 665 u32 val = 0;
8788fdc2
SP		 666 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
667 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 668 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 669 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 670
cf588477
SP		 671 /* wait for ready to be set */
672 status = be_mbox_db_ready_wait(adapter, db);
673 if (status != 0)
674 return status;
675
6b7c5b94
SP		 676 val |= MPU_MAILBOX_DB_HI_MASK;
677 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
678 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
679 iowrite32(val, db);
680
681 /* wait for ready to be set */
5f0b849e 682 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 683 if (status != 0)
684 return status;
685
686 val = 0;
6b7c5b94
SP		 687 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
688 val |= (u32)(mbox_mem->dma >> 4) << 2;
689 iowrite32(val, db);
690
5f0b849e 691 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 692 if (status != 0)
693 return status;
694
5fb379ee 695 /* A cq entry has been made now */
efd2e40a
SP		 696 if (be_mcc_compl_is_new(compl)) {
697 status = be_mcc_compl_process(adapter, &mbox->compl);
698 be_mcc_compl_use(compl);
5fb379ee
SP		 699 if (status)
700 return status;
701 } else {
5f0b849e 702 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 703 return -1;
704 }
5fb379ee 705 return 0;
6b7c5b94
SP		 706}
707
c5b3ad4c 708static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 709{
fe6d2a38
SP		 710 u32 sem;
711
c5b3ad4c
SP		 712 if (BEx_chip(adapter))
713 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 714 else
c5b3ad4c
SP		 715 pci_read_config_dword(adapter->pdev,
716 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
717
718 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 719}
720
87f20c26 721static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 722{
723#define SLIPORT_READY_TIMEOUT 30
724 u32 sliport_status;
e673244a 725 int i;
bf99e50d
PR		 726
727 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
728 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
729 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
9fa465c0 730 return 0;
67297ad8 731
9fa465c0
SP		 732 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
733 !(sliport_status & SLIPORT_STATUS_RN_MASK))
734 return -EIO;
67297ad8 735
9fa465c0 736 msleep(1000);
bf99e50d 737 }
67297ad8 738
9fa465c0 739 return sliport_status ? : -1;
bf99e50d
PR		 740}
741
742int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 743{
43a04fdc
SP		 744 u16 stage;
745 int status, timeout = 0;
6ed35eea 746 struct device *dev = &adapter->pdev->dev;
6b7c5b94 747
bf99e50d
PR		 748 if (lancer_chip(adapter)) {
749 status = lancer_wait_ready(adapter);
e673244a
KA		 750 if (status) {
751 stage = status;
752 goto err;
753 }
754 return 0;
bf99e50d
PR		 755 }
756
43a04fdc 757 do {
ca3de6b2
SP		 758 /* There's no means to poll POST state on BE2/3 VFs */
759 if (BEx_chip(adapter) && be_virtfn(adapter))
760 return 0;
761
c5b3ad4c 762 stage = be_POST_stage_get(adapter);
66d29cbc 763 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 764 return 0;
66d29cbc 765
a2cc4e0b 766 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 767 if (msleep_interruptible(2000)) {
768 dev_err(dev, "Waiting for POST aborted\n");
769 return -EINTR;
43a04fdc 770 }
66d29cbc 771 timeout += 2;
3ab81b5f 772 } while (timeout < 60);
6b7c5b94 773
e673244a
KA		 774err:
775 dev_err(dev, "POST timeout; stage=%#x\n", stage);
9fa465c0 776 return -ETIMEDOUT;
6b7c5b94
SP		 777}
778
6b7c5b94
SP		 779static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
780{
781 return &wrb->payload.sgl[0];
782}
783
a2cc4e0b 784static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 785{
786 wrb->tag0 = addr & 0xFFFFFFFF;
787 wrb->tag1 = upper_32_bits(addr);
788}
6b7c5b94
SP		 789
790/* Don't touch the hdr after it's prepared */
106df1e3
SK		 791/* mem will be NULL for embedded commands */
792static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 793 u8 subsystem, u8 opcode, int cmd_len,
794 struct be_mcc_wrb *wrb,
795 struct be_dma_mem *mem)
6b7c5b94 796{
106df1e3
SK		 797 struct be_sge *sge;
798
6b7c5b94
SP		 799 req_hdr->opcode = opcode;
800 req_hdr->subsystem = subsystem;
801 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 802 req_hdr->version = 0;
bea50988 803 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 804 wrb->payload_length = cmd_len;
805 if (mem) {
806 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
807 MCC_WRB_SGE_CNT_SHIFT;
808 sge = nonembedded_sgl(wrb);
809 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
810 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
811 sge->len = cpu_to_le32(mem->size);
812 } else
813 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
814 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 815}
816
817static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 818 struct be_dma_mem *mem)
6b7c5b94
SP		 819{
820 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
821 u64 dma = (u64)mem->dma;
822
823 for (i = 0; i < buf_pages; i++) {
824 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
825 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
826 dma += PAGE_SIZE_4K;
827 }
828}
829
b31c50a7 830static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 831{
b31c50a7
SP		 832 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
833 struct be_mcc_wrb *wrb
834 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
835 memset(wrb, 0, sizeof(*wrb));
836 return wrb;
6b7c5b94
SP		 837}
838
b31c50a7 839static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 840{
b31c50a7
SP		 841 struct be_queue_info *mccq = &adapter->mcc_obj.q;
842 struct be_mcc_wrb *wrb;
843
aa790db9
PR		 844 if (!mccq->created)
845 return NULL;
846
4d277125 847 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 848 return NULL;
713d0394 849
b31c50a7
SP		 850 wrb = queue_head_node(mccq);
851 queue_head_inc(mccq);
852 atomic_inc(&mccq->used);
853 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 854 return wrb;
855}
856
bea50988
SP		 857static bool use_mcc(struct be_adapter *adapter)
858{
859 return adapter->mcc_obj.q.created;
860}
861
862/* Must be used only in process context */
863static int be_cmd_lock(struct be_adapter *adapter)
864{
865 if (use_mcc(adapter)) {
866 spin_lock_bh(&adapter->mcc_lock);
867 return 0;
868 } else {
869 return mutex_lock_interruptible(&adapter->mbox_lock);
870 }
871}
872
873/* Must be used only in process context */
874static void be_cmd_unlock(struct be_adapter *adapter)
875{
876 if (use_mcc(adapter))
877 spin_unlock_bh(&adapter->mcc_lock);
878 else
879 return mutex_unlock(&adapter->mbox_lock);
880}
881
882static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
883 struct be_mcc_wrb *wrb)
884{
885 struct be_mcc_wrb *dest_wrb;
886
887 if (use_mcc(adapter)) {
888 dest_wrb = wrb_from_mccq(adapter);
889 if (!dest_wrb)
890 return NULL;
891 } else {
892 dest_wrb = wrb_from_mbox(adapter);
893 }
894
895 memcpy(dest_wrb, wrb, sizeof(*wrb));
896 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
897 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
898
899 return dest_wrb;
900}
901
902/* Must be used only in process context */
903static int be_cmd_notify_wait(struct be_adapter *adapter,
904 struct be_mcc_wrb *wrb)
905{
906 struct be_mcc_wrb *dest_wrb;
907 int status;
908
909 status = be_cmd_lock(adapter);
910 if (status)
911 return status;
912
913 dest_wrb = be_cmd_copy(adapter, wrb);
0c884567
SR		 914 if (!dest_wrb) {
915 status = -EBUSY;
916 goto unlock;
917 }
bea50988
SP		 918
919 if (use_mcc(adapter))
920 status = be_mcc_notify_wait(adapter);
921 else
922 status = be_mbox_notify_wait(adapter);
923
924 if (!status)
925 memcpy(wrb, dest_wrb, sizeof(*wrb));
926
0c884567 927unlock:
bea50988
SP		 928 be_cmd_unlock(adapter);
929 return status;
930}
931
2243e2e9
SP		 932/* Tell fw we're about to start firing cmds by writing a
933 * special pattern across the wrb hdr; uses mbox
934 */
935int be_cmd_fw_init(struct be_adapter *adapter)
936{
937 u8 *wrb;
938 int status;
939
bf99e50d
PR		 940 if (lancer_chip(adapter))
941 return 0;
942
2984961c
IV		 943 if (mutex_lock_interruptible(&adapter->mbox_lock))
944 return -1;
2243e2e9
SP		 945
946 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 947 *wrb++ = 0xFF;
948 *wrb++ = 0x12;
949 *wrb++ = 0x34;
950 *wrb++ = 0xFF;
951 *wrb++ = 0xFF;
952 *wrb++ = 0x56;
953 *wrb++ = 0x78;
954 *wrb = 0xFF;
2243e2e9
SP		 955
956 status = be_mbox_notify_wait(adapter);
957
2984961c 958 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 959 return status;
960}
961
962/* Tell fw we're done with firing cmds by writing a
963 * special pattern across the wrb hdr; uses mbox
964 */
965int be_cmd_fw_clean(struct be_adapter *adapter)
966{
967 u8 *wrb;
968 int status;
969
bf99e50d
PR		 970 if (lancer_chip(adapter))
971 return 0;
972
2984961c
IV		 973 if (mutex_lock_interruptible(&adapter->mbox_lock))
974 return -1;
2243e2e9
SP		 975
976 wrb = (u8 *)wrb_from_mbox(adapter);
977 *wrb++ = 0xFF;
978 *wrb++ = 0xAA;
979 *wrb++ = 0xBB;
980 *wrb++ = 0xFF;
981 *wrb++ = 0xFF;
982 *wrb++ = 0xCC;
983 *wrb++ = 0xDD;
984 *wrb = 0xFF;
985
986 status = be_mbox_notify_wait(adapter);
987
2984961c 988 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 989 return status;
990}
bf99e50d 991
f2f781a7 992int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 993{
b31c50a7
SP		 994 struct be_mcc_wrb *wrb;
995 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 996 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
997 int status, ver = 0;
6b7c5b94 998
2984961c
IV		 999 if (mutex_lock_interruptible(&adapter->mbox_lock))
1000 return -1;
b31c50a7
SP		 1001
1002 wrb = wrb_from_mbox(adapter);
1003 req = embedded_payload(wrb);
6b7c5b94 1004
106df1e3 1005 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1006 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1007 NULL);
6b7c5b94 1008
f2f781a7
SP		 1009 /* Support for EQ_CREATEv2 available only SH-R onwards */
1010 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1011 ver = 2;
1012
1013 req->hdr.version = ver;
6b7c5b94
SP		 1014 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1015
6b7c5b94
SP		 1016 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1017 /* 4byte eqe*/
1018 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1019 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 1020 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 1021 be_dws_cpu_to_le(req->context, sizeof(req->context));
1022
1023 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1024
b31c50a7 1025 status = be_mbox_notify_wait(adapter);
6b7c5b94 1026 if (!status) {
b31c50a7 1027 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 1028
f2f781a7
SP		 1029 eqo->q.id = le16_to_cpu(resp->eq_id);
1030 eqo->msix_idx =
1031 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1032 eqo->q.created = true;
6b7c5b94 1033 }
b31c50a7 1034
2984961c 1035 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1036 return status;
1037}
1038
f9449ab7 1039/* Use MCC */
8788fdc2 1040int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 1041 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 1042{
b31c50a7
SP		 1043 struct be_mcc_wrb *wrb;
1044 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 1045 int status;
1046
f9449ab7 1047 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1048
f9449ab7
SP		 1049 wrb = wrb_from_mccq(adapter);
1050 if (!wrb) {
1051 status = -EBUSY;
1052 goto err;
1053 }
b31c50a7 1054 req = embedded_payload(wrb);
6b7c5b94 1055
106df1e3 1056 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1057 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1058 NULL);
5ee4979b 1059 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 1060 if (permanent) {
1061 req->permanent = 1;
1062 } else {
504fbf1e 1063 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 1064 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 1065 req->permanent = 0;
1066 }
1067
f9449ab7 1068 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 1069 if (!status) {
1070 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 1071
6b7c5b94 1072 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 1073 }
6b7c5b94 1074
f9449ab7
SP		 1075err:
1076 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1077 return status;
1078}
1079
b31c50a7 1080/* Uses synchronous MCCQ */
8788fdc2 1081int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 1082 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 1083{
b31c50a7
SP		 1084 struct be_mcc_wrb *wrb;
1085 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 1086 int status;
1087
b31c50a7
SP		 1088 spin_lock_bh(&adapter->mcc_lock);
1089
1090 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1091 if (!wrb) {
1092 status = -EBUSY;
1093 goto err;
1094 }
b31c50a7 1095 req = embedded_payload(wrb);
6b7c5b94 1096
106df1e3 1097 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1098 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1099 NULL);
6b7c5b94 1100
f8617e08 1101 req->hdr.domain = domain;
6b7c5b94
SP		 1102 req->if_id = cpu_to_le32(if_id);
1103 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1104
b31c50a7 1105 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1106 if (!status) {
1107 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1108
6b7c5b94
SP		 1109 *pmac_id = le32_to_cpu(resp->pmac_id);
1110 }
1111
713d0394 1112err:
b31c50a7 1113 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 1114
1115 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1116 status = -EPERM;
1117
6b7c5b94
SP		 1118 return status;
1119}
1120
b31c50a7 1121/* Uses synchronous MCCQ */
30128031 1122int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1123{
b31c50a7
SP		 1124 struct be_mcc_wrb *wrb;
1125 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1126 int status;
1127
30128031
SP		 1128 if (pmac_id == -1)
1129 return 0;
1130
b31c50a7
SP		 1131 spin_lock_bh(&adapter->mcc_lock);
1132
1133 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1134 if (!wrb) {
1135 status = -EBUSY;
1136 goto err;
1137 }
b31c50a7 1138 req = embedded_payload(wrb);
6b7c5b94 1139
106df1e3 1140 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
cd3307aa
KA		 1141 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1142 wrb, NULL);
6b7c5b94 1143
f8617e08 1144 req->hdr.domain = dom;
6b7c5b94
SP		 1145 req->if_id = cpu_to_le32(if_id);
1146 req->pmac_id = cpu_to_le32(pmac_id);
1147
b31c50a7
SP		 1148 status = be_mcc_notify_wait(adapter);
1149
713d0394 1150err:
b31c50a7 1151 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1152 return status;
1153}
1154
b31c50a7 1155/* Uses Mbox */
10ef9ab4 1156int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1157 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1158{
b31c50a7
SP		 1159 struct be_mcc_wrb *wrb;
1160 struct be_cmd_req_cq_create *req;
6b7c5b94 1161 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1162 void *ctxt;
6b7c5b94
SP		 1163 int status;
1164
2984961c
IV		 1165 if (mutex_lock_interruptible(&adapter->mbox_lock))
1166 return -1;
b31c50a7
SP		 1167
1168 wrb = wrb_from_mbox(adapter);
1169 req = embedded_payload(wrb);
1170 ctxt = &req->context;
6b7c5b94 1171
106df1e3 1172 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1173 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1174 NULL);
6b7c5b94
SP		 1175
1176 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1177
1178 if (BEx_chip(adapter)) {
fe6d2a38 1179 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1180 coalesce_wm);
fe6d2a38 1181 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1182 ctxt, no_delay);
fe6d2a38 1183 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1184 __ilog2_u32(cq->len / 256));
fe6d2a38 1185 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1186 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1187 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1188 } else {
1189 req->hdr.version = 2;
1190 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1191
1192 /* coalesce-wm field in this cmd is not relevant to Lancer.
1193 * Lancer uses COMMON_MODIFY_CQ to set this field
1194 */
1195 if (!lancer_chip(adapter))
1196 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1197 ctxt, coalesce_wm);
bbdc42f8 1198 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1199 no_delay);
bbdc42f8 1200 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1201 __ilog2_u32(cq->len / 256));
bbdc42f8 1202 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1203 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1204 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1205 }
6b7c5b94 1206
6b7c5b94
SP		 1207 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1208
1209 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1210
b31c50a7 1211 status = be_mbox_notify_wait(adapter);
6b7c5b94 1212 if (!status) {
b31c50a7 1213 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1214
6b7c5b94
SP		 1215 cq->id = le16_to_cpu(resp->cq_id);
1216 cq->created = true;
1217 }
b31c50a7 1218
2984961c 1219 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1220
1221 return status;
1222}
1223
1224static u32 be_encoded_q_len(int q_len)
1225{
1226 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1227
5fb379ee
SP		 1228 if (len_encoded == 16)
1229 len_encoded = 0;
1230 return len_encoded;
1231}
1232
4188e7df 1233static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1234 struct be_queue_info *mccq,
1235 struct be_queue_info *cq)
5fb379ee 1236{
b31c50a7 1237 struct be_mcc_wrb *wrb;
34b1ef04 1238 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1239 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1240 void *ctxt;
5fb379ee
SP		 1241 int status;
1242
2984961c
IV		 1243 if (mutex_lock_interruptible(&adapter->mbox_lock))
1244 return -1;
b31c50a7
SP		 1245
1246 wrb = wrb_from_mbox(adapter);
1247 req = embedded_payload(wrb);
1248 ctxt = &req->context;
5fb379ee 1249
106df1e3 1250 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1251 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1252 NULL);
5fb379ee 1253
d4a2ac3e 1254 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1255 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1256 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1257 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1258 be_encoded_q_len(mccq->len));
fe6d2a38 1259 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1260 } else {
1261 req->hdr.version = 1;
1262 req->cq_id = cpu_to_le16(cq->id);
1263
1264 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1265 be_encoded_q_len(mccq->len));
1266 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1267 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1268 ctxt, cq->id);
1269 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1270 ctxt, 1);
fe6d2a38 1271 }
5fb379ee 1272
21252377
VV		 1273 /* Subscribe to Link State, Sliport Event and Group 5 Events
1274 * (bits 1, 5 and 17 set)
1275 */
1276 req->async_event_bitmap[0] =
1277 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1278 BIT(ASYNC_EVENT_CODE_GRP_5) |
1279 BIT(ASYNC_EVENT_CODE_QNQ) |
1280 BIT(ASYNC_EVENT_CODE_SLIPORT));
1281
5fb379ee
SP		 1282 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1283
1284 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1285
b31c50a7 1286 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1287 if (!status) {
1288 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1289
5fb379ee
SP		 1290 mccq->id = le16_to_cpu(resp->id);
1291 mccq->created = true;
1292 }
2984961c 1293 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1294
1295 return status;
1296}
1297
4188e7df 1298static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1299 struct be_queue_info *mccq,
1300 struct be_queue_info *cq)
34b1ef04
SK		 1301{
1302 struct be_mcc_wrb *wrb;
1303 struct be_cmd_req_mcc_create *req;
1304 struct be_dma_mem *q_mem = &mccq->dma_mem;
1305 void *ctxt;
1306 int status;
1307
1308 if (mutex_lock_interruptible(&adapter->mbox_lock))
1309 return -1;
1310
1311 wrb = wrb_from_mbox(adapter);
1312 req = embedded_payload(wrb);
1313 ctxt = &req->context;
1314
106df1e3 1315 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1316 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1317 NULL);
34b1ef04
SK		 1318
1319 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1320
1321 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1322 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1323 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1324 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1325
1326 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1327
1328 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1329
1330 status = be_mbox_notify_wait(adapter);
1331 if (!status) {
1332 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1333
34b1ef04
SK		 1334 mccq->id = le16_to_cpu(resp->id);
1335 mccq->created = true;
1336 }
1337
1338 mutex_unlock(&adapter->mbox_lock);
1339 return status;
1340}
1341
1342int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1343 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1344{
1345 int status;
1346
1347 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1348 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1349 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1350 "or newer to avoid conflicting priorities between NIC "
1351 "and FCoE traffic");
1352 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1353 }
1354 return status;
1355}
1356
94d73aaa 1357int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1358{
7707133c 1359 struct be_mcc_wrb wrb = {0};
b31c50a7 1360 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1361 struct be_queue_info *txq = &txo->q;
1362 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1363 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1364 int status, ver = 0;
6b7c5b94 1365
7707133c 1366 req = embedded_payload(&wrb);
106df1e3 1367 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1368 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1369
8b7756ca
PR		 1370 if (lancer_chip(adapter)) {
1371 req->hdr.version = 1;
94d73aaa
VV		 1372 } else if (BEx_chip(adapter)) {
1373 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1374 req->hdr.version = 2;
1375 } else { /* For SH */
1376 req->hdr.version = 2;
8b7756ca
PR		 1377 }
1378
81b02655
VV		 1379 if (req->hdr.version > 0)
1380 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1381 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1382 req->ulp_num = BE_ULP1_NUM;
1383 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1384 req->cq_id = cpu_to_le16(cq->id);
1385 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1386 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1387 ver = req->hdr.version;
1388
7707133c 1389 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1390 if (!status) {
7707133c 1391 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1392
6b7c5b94 1393 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1394 if (ver == 2)
1395 txo->db_offset = le32_to_cpu(resp->db_offset);
1396 else
1397 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1398 txq->created = true;
1399 }
b31c50a7 1400
6b7c5b94
SP		 1401 return status;
1402}
1403
482c9e79 1404/* Uses MCC */
8788fdc2 1405int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1406 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1407 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1408{
b31c50a7
SP		 1409 struct be_mcc_wrb *wrb;
1410 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1411 struct be_dma_mem *q_mem = &rxq->dma_mem;
1412 int status;
1413
482c9e79 1414 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1415
482c9e79
SP		 1416 wrb = wrb_from_mccq(adapter);
1417 if (!wrb) {
1418 status = -EBUSY;
1419 goto err;
1420 }
b31c50a7 1421 req = embedded_payload(wrb);
6b7c5b94 1422
106df1e3 1423 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1424 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1425
1426 req->cq_id = cpu_to_le16(cq_id);
1427 req->frag_size = fls(frag_size) - 1;
1428 req->num_pages = 2;
1429 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1430 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1431 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1432 req->rss_queue = cpu_to_le32(rss);
1433
482c9e79 1434 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1435 if (!status) {
1436 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1437
6b7c5b94
SP		 1438 rxq->id = le16_to_cpu(resp->id);
1439 rxq->created = true;
3abcdeda 1440 *rss_id = resp->rss_id;
6b7c5b94 1441 }
b31c50a7 1442
482c9e79
SP		 1443err:
1444 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1445 return status;
1446}
1447
b31c50a7
SP		 1448/* Generic destroyer function for all types of queues
1449 * Uses Mbox
1450 */
8788fdc2 1451int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1452 int queue_type)
6b7c5b94 1453{
b31c50a7
SP		 1454 struct be_mcc_wrb *wrb;
1455 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1456 u8 subsys = 0, opcode = 0;
1457 int status;
1458
2984961c
IV		 1459 if (mutex_lock_interruptible(&adapter->mbox_lock))
1460 return -1;
6b7c5b94 1461
b31c50a7
SP		 1462 wrb = wrb_from_mbox(adapter);
1463 req = embedded_payload(wrb);
1464
6b7c5b94
SP		 1465 switch (queue_type) {
1466 case QTYPE_EQ:
1467 subsys = CMD_SUBSYSTEM_COMMON;
1468 opcode = OPCODE_COMMON_EQ_DESTROY;
1469 break;
1470 case QTYPE_CQ:
1471 subsys = CMD_SUBSYSTEM_COMMON;
1472 opcode = OPCODE_COMMON_CQ_DESTROY;
1473 break;
1474 case QTYPE_TXQ:
1475 subsys = CMD_SUBSYSTEM_ETH;
1476 opcode = OPCODE_ETH_TX_DESTROY;
1477 break;
1478 case QTYPE_RXQ:
1479 subsys = CMD_SUBSYSTEM_ETH;
1480 opcode = OPCODE_ETH_RX_DESTROY;
1481 break;
5fb379ee
SP		 1482 case QTYPE_MCCQ:
1483 subsys = CMD_SUBSYSTEM_COMMON;
1484 opcode = OPCODE_COMMON_MCC_DESTROY;
1485 break;
6b7c5b94 1486 default:
5f0b849e 1487 BUG();
6b7c5b94 1488 }
d744b44e 1489
106df1e3 1490 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1491 NULL);
6b7c5b94
SP		 1492 req->id = cpu_to_le16(q->id);
1493
b31c50a7 1494 status = be_mbox_notify_wait(adapter);
aa790db9 1495 q->created = false;
5f0b849e 1496
2984961c 1497 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1498 return status;
1499}
6b7c5b94 1500
482c9e79
SP		 1501/* Uses MCC */
1502int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1503{
1504 struct be_mcc_wrb *wrb;
1505 struct be_cmd_req_q_destroy *req;
1506 int status;
1507
1508 spin_lock_bh(&adapter->mcc_lock);
1509
1510 wrb = wrb_from_mccq(adapter);
1511 if (!wrb) {
1512 status = -EBUSY;
1513 goto err;
1514 }
1515 req = embedded_payload(wrb);
1516
106df1e3 1517 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1518 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1519 req->id = cpu_to_le16(q->id);
1520
1521 status = be_mcc_notify_wait(adapter);
aa790db9 1522 q->created = false;
482c9e79
SP		 1523
1524err:
1525 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1526 return status;
1527}
1528
b31c50a7 1529/* Create an rx filtering policy configuration on an i/f
bea50988 1530 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1531 */
73d540f2 1532int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1533 u32 *if_handle, u32 domain)
6b7c5b94 1534{
bea50988 1535 struct be_mcc_wrb wrb = {0};
b31c50a7 1536 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1537 int status;
1538
bea50988 1539 req = embedded_payload(&wrb);
106df1e3 1540 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1541 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1542 sizeof(*req), &wrb, NULL);
ba343c77 1543 req->hdr.domain = domain;
73d540f2
SP		 1544 req->capability_flags = cpu_to_le32(cap_flags);
1545 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1546 req->pmac_invalid = true;
6b7c5b94 1547
bea50988 1548 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1549 if (!status) {
bea50988 1550 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1551
6b7c5b94 1552 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1553
1554 /* Hack to retrieve VF's pmac-id on BE3 */
18c57c74 1555 if (BE3_chip(adapter) && be_virtfn(adapter))
b5bb9776 1556 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1557 }
6b7c5b94
SP		 1558 return status;
1559}
1560
62219066 1561/* Uses MCCQ if available else MBOX */
30128031 1562int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1563{
62219066 1564 struct be_mcc_wrb wrb = {0};
b31c50a7 1565 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1566 int status;
1567
30128031 1568 if (interface_id == -1)
f9449ab7 1569 return 0;
b31c50a7 1570
62219066 1571 req = embedded_payload(&wrb);
6b7c5b94 1572
106df1e3 1573 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 1574 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
62219066 1575 sizeof(*req), &wrb, NULL);
658681f7 1576 req->hdr.domain = domain;
6b7c5b94 1577 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1578
62219066 1579 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94
SP		 1580 return status;
1581}
1582
1583/* Get stats is a non embedded command: the request is not embedded inside
1584 * WRB but is a separate dma memory block
b31c50a7 1585 * Uses asynchronous MCC
6b7c5b94 1586 */
8788fdc2 1587int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1588{
b31c50a7 1589 struct be_mcc_wrb *wrb;
89a88ab8 1590 struct be_cmd_req_hdr *hdr;
713d0394 1591 int status = 0;
6b7c5b94 1592
b31c50a7 1593 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1594
b31c50a7 1595 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1596 if (!wrb) {
1597 status = -EBUSY;
1598 goto err;
1599 }
89a88ab8 1600 hdr = nonemb_cmd->va;
6b7c5b94 1601
106df1e3 1602 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1603 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1604 nonemb_cmd);
89a88ab8 1605
ca34fe38 1606 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1607 if (BE2_chip(adapter))
1608 hdr->version = 0;
1609 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1610 hdr->version = 1;
61000861
AK		 1611 else
1612 hdr->version = 2;
89a88ab8 1613
efaa408e
SR		 1614 status = be_mcc_notify(adapter);
1615 if (status)
1616 goto err;
1617
b2aebe6d 1618 adapter->stats_cmd_sent = true;
6b7c5b94 1619
713d0394 1620err:
b31c50a7 1621 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1622 return status;
6b7c5b94
SP		 1623}
1624
005d5696
SX		 1625/* Lancer Stats */
1626int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1627 struct be_dma_mem *nonemb_cmd)
005d5696 1628{
005d5696
SX		 1629 struct be_mcc_wrb *wrb;
1630 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1631 int status = 0;
1632
f25b119c
PR		 1633 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1634 CMD_SUBSYSTEM_ETH))
1635 return -EPERM;
1636
005d5696
SX		 1637 spin_lock_bh(&adapter->mcc_lock);
1638
1639 wrb = wrb_from_mccq(adapter);
1640 if (!wrb) {
1641 status = -EBUSY;
1642 goto err;
1643 }
1644 req = nonemb_cmd->va;
005d5696 1645
106df1e3 1646 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1647 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1648 wrb, nonemb_cmd);
005d5696 1649
d51ebd33 1650 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1651 req->cmd_params.params.reset_stats = 0;
1652
efaa408e
SR		 1653 status = be_mcc_notify(adapter);
1654 if (status)
1655 goto err;
1656
005d5696
SX		 1657 adapter->stats_cmd_sent = true;
1658
1659err:
1660 spin_unlock_bh(&adapter->mcc_lock);
1661 return status;
1662}
1663
323ff71e
SP		 1664static int be_mac_to_link_speed(int mac_speed)
1665{
1666 switch (mac_speed) {
1667 case PHY_LINK_SPEED_ZERO:
1668 return 0;
1669 case PHY_LINK_SPEED_10MBPS:
1670 return 10;
1671 case PHY_LINK_SPEED_100MBPS:
1672 return 100;
1673 case PHY_LINK_SPEED_1GBPS:
1674 return 1000;
1675 case PHY_LINK_SPEED_10GBPS:
1676 return 10000;
b971f847
VV		 1677 case PHY_LINK_SPEED_20GBPS:
1678 return 20000;
1679 case PHY_LINK_SPEED_25GBPS:
1680 return 25000;
1681 case PHY_LINK_SPEED_40GBPS:
1682 return 40000;
323ff71e
SP		 1683 }
1684 return 0;
1685}
1686
1687/* Uses synchronous mcc
1688 * Returns link_speed in Mbps
1689 */
1690int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1691 u8 *link_status, u32 dom)
6b7c5b94 1692{
b31c50a7
SP		 1693 struct be_mcc_wrb *wrb;
1694 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1695 int status;
1696
b31c50a7
SP		 1697 spin_lock_bh(&adapter->mcc_lock);
1698
b236916a
AK		 1699 if (link_status)
1700 *link_status = LINK_DOWN;
1701
b31c50a7 1702 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1703 if (!wrb) {
1704 status = -EBUSY;
1705 goto err;
1706 }
b31c50a7 1707 req = embedded_payload(wrb);
a8f447bd 1708
57cd80d4 1709 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1710 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1711 sizeof(*req), wrb, NULL);
57cd80d4 1712
ca34fe38
SP		 1713 /* version 1 of the cmd is not supported only by BE2 */
1714 if (!BE2_chip(adapter))
daad6167
PR		 1715 req->hdr.version = 1;
1716
57cd80d4 1717 req->hdr.domain = dom;
6b7c5b94 1718
b31c50a7 1719 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1720 if (!status) {
1721 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1722
323ff71e
SP		 1723 if (link_speed) {
1724 *link_speed = resp->link_speed ?
1725 le16_to_cpu(resp->link_speed) * 10 :
1726 be_mac_to_link_speed(resp->mac_speed);
1727
1728 if (!resp->logical_link_status)
1729 *link_speed = 0;
0388f251 1730 }
b236916a
AK		 1731 if (link_status)
1732 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1733 }
1734
713d0394 1735err:
b31c50a7 1736 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1737 return status;
1738}
1739
609ff3bb
AK		 1740/* Uses synchronous mcc */
1741int be_cmd_get_die_temperature(struct be_adapter *adapter)
1742{
1743 struct be_mcc_wrb *wrb;
1744 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1745 int status = 0;
609ff3bb
AK		 1746
1747 spin_lock_bh(&adapter->mcc_lock);
1748
1749 wrb = wrb_from_mccq(adapter);
1750 if (!wrb) {
1751 status = -EBUSY;
1752 goto err;
1753 }
1754 req = embedded_payload(wrb);
1755
106df1e3 1756 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1757 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1758 sizeof(*req), wrb, NULL);
609ff3bb 1759
efaa408e 1760 status = be_mcc_notify(adapter);
609ff3bb
AK		 1761err:
1762 spin_unlock_bh(&adapter->mcc_lock);
1763 return status;
1764}
1765
311fddc7 1766/* Uses synchronous mcc */
fd7ff6f0 1767int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
311fddc7 1768{
fd7ff6f0 1769 struct be_mcc_wrb wrb = {0};
311fddc7
SK		 1770 struct be_cmd_req_get_fat *req;
1771 int status;
1772
fd7ff6f0 1773 req = embedded_payload(&wrb);
311fddc7 1774
106df1e3 1775 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
fd7ff6f0
VD		 1776 OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1777 &wrb, NULL);
311fddc7 1778 req->fat_operation = cpu_to_le32(QUERY_FAT);
fd7ff6f0 1779 status = be_cmd_notify_wait(adapter, &wrb);
311fddc7 1780 if (!status) {
fd7ff6f0 1781 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
03d28ffe 1782
fd7ff6f0
VD		 1783 if (dump_size && resp->log_size)
1784 *dump_size = le32_to_cpu(resp->log_size) -
fe2a70ee 1785 sizeof(u32);
311fddc7 1786 }
311fddc7
SK		 1787 return status;
1788}
1789
fd7ff6f0 1790int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1791{
1792 struct be_dma_mem get_fat_cmd;
1793 struct be_mcc_wrb *wrb;
1794 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1795 u32 offset = 0, total_size, buf_size,
1796 log_offset = sizeof(u32), payload_len;
fd7ff6f0 1797 int status;
311fddc7
SK		 1798
1799 if (buf_len == 0)
fd7ff6f0 1800 return 0;
311fddc7
SK		 1801
1802 total_size = buf_len;
1803
fe2a70ee 1804 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
e51000db
SB		 1805 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1806 get_fat_cmd.size,
1807 &get_fat_cmd.dma, GFP_ATOMIC);
fd7ff6f0 1808 if (!get_fat_cmd.va)
c5f156de 1809 return -ENOMEM;
fe2a70ee 1810
311fddc7
SK		 1811 spin_lock_bh(&adapter->mcc_lock);
1812
311fddc7
SK		 1813 while (total_size) {
1814 buf_size = min(total_size, (u32)60*1024);
1815 total_size -= buf_size;
1816
fe2a70ee
SK		 1817 wrb = wrb_from_mccq(adapter);
1818 if (!wrb) {
1819 status = -EBUSY;
311fddc7
SK		 1820 goto err;
1821 }
1822 req = get_fat_cmd.va;
311fddc7 1823
fe2a70ee 1824 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1825 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1826 OPCODE_COMMON_MANAGE_FAT, payload_len,
1827 wrb, &get_fat_cmd);
311fddc7
SK		 1828
1829 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1830 req->read_log_offset = cpu_to_le32(log_offset);
1831 req->read_log_length = cpu_to_le32(buf_size);
1832 req->data_buffer_size = cpu_to_le32(buf_size);
1833
1834 status = be_mcc_notify_wait(adapter);
1835 if (!status) {
1836 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1837
311fddc7 1838 memcpy(buf + offset,
a2cc4e0b
SP		 1839 resp->data_buffer,
1840 le32_to_cpu(resp->read_log_length));
fe2a70ee 1841 } else {
311fddc7 1842 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1843 goto err;
1844 }
311fddc7
SK		 1845 offset += buf_size;
1846 log_offset += buf_size;
1847 }
1848err:
e51000db
SB		 1849 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1850 get_fat_cmd.va, get_fat_cmd.dma);
311fddc7 1851 spin_unlock_bh(&adapter->mcc_lock);
c5f156de 1852 return status;
311fddc7
SK		 1853}
1854
04b71175 1855/* Uses synchronous mcc */
e97e3cda 1856int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1857{
b31c50a7
SP		 1858 struct be_mcc_wrb *wrb;
1859 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1860 int status;
1861
04b71175 1862 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1863
04b71175
SP		 1864 wrb = wrb_from_mccq(adapter);
1865 if (!wrb) {
1866 status = -EBUSY;
1867 goto err;
1868 }
6b7c5b94 1869
04b71175 1870 req = embedded_payload(wrb);
6b7c5b94 1871
106df1e3 1872 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1873 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1874 NULL);
04b71175 1875 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1876 if (!status) {
1877 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1878
242eb470
VV		 1879 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1880 sizeof(adapter->fw_ver));
1881 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1882 sizeof(adapter->fw_on_flash));
6b7c5b94 1883 }
04b71175
SP		 1884err:
1885 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1886 return status;
1887}
1888
b31c50a7
SP		 1889/* set the EQ delay interval of an EQ to specified value
1890 * Uses async mcc
1891 */
b502ae8d
KA		 1892static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1893 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1894{
b31c50a7
SP		 1895 struct be_mcc_wrb *wrb;
1896 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1897 int status = 0, i;
6b7c5b94 1898
b31c50a7
SP		 1899 spin_lock_bh(&adapter->mcc_lock);
1900
1901 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1902 if (!wrb) {
1903 status = -EBUSY;
1904 goto err;
1905 }
b31c50a7 1906 req = embedded_payload(wrb);
6b7c5b94 1907
106df1e3 1908 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1909 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1910 NULL);
6b7c5b94 1911
2632bafd
SP		 1912 req->num_eq = cpu_to_le32(num);
1913 for (i = 0; i < num; i++) {
1914 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1915 req->set_eqd[i].phase = 0;
1916 req->set_eqd[i].delay_multiplier =
1917 cpu_to_le32(set_eqd[i].delay_multiplier);
1918 }
6b7c5b94 1919
efaa408e 1920 status = be_mcc_notify(adapter);
713d0394 1921err:
b31c50a7 1922 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1923 return status;
6b7c5b94
SP		 1924}
1925
93676703
KA		 1926int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1927 int num)
1928{
1929 int num_eqs, i = 0;
1930
c8ba4ad0
SR		 1931 while (num) {
1932 num_eqs = min(num, 8);
1933 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1934 i += num_eqs;
1935 num -= num_eqs;
93676703
KA		 1936 }
1937
1938 return 0;
1939}
1940
b31c50a7 1941/* Uses sycnhronous mcc */
8788fdc2 1942int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 1943 u32 num, u32 domain)
6b7c5b94 1944{
b31c50a7
SP		 1945 struct be_mcc_wrb *wrb;
1946 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1947 int status;
1948
b31c50a7
SP		 1949 spin_lock_bh(&adapter->mcc_lock);
1950
1951 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1952 if (!wrb) {
1953 status = -EBUSY;
1954 goto err;
1955 }
b31c50a7 1956 req = embedded_payload(wrb);
6b7c5b94 1957
106df1e3 1958 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1959 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1960 wrb, NULL);
435452aa 1961 req->hdr.domain = domain;
6b7c5b94
SP		 1962
1963 req->interface_id = if_id;
012bd387 1964 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1965 req->num_vlan = num;
4d567d97
KA		 1966 memcpy(req->normal_vlan, vtag_array,
1967 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1968
b31c50a7 1969 status = be_mcc_notify_wait(adapter);
713d0394 1970err:
b31c50a7 1971 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1972 return status;
1973}
1974
ac34b743 1975static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1976{
6ac7b687 1977 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1978 struct be_dma_mem *mem = &adapter->rx_filter;
1979 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1980 int status;
6b7c5b94 1981
8788fdc2 1982 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1983
b31c50a7 1984 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1985 if (!wrb) {
1986 status = -EBUSY;
1987 goto err;
1988 }
5b8821b7 1989 memset(req, 0, sizeof(*req));
106df1e3 1990 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1991 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1992 wrb, mem);
6b7c5b94 1993
5b8821b7 1994 req->if_id = cpu_to_le32(adapter->if_handle);
ac34b743
SP		 1995 req->if_flags_mask = cpu_to_le32(flags);
1996 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1997
1998 if (flags & BE_IF_FLAGS_MULTICAST) {
22bedad3 1999 struct netdev_hw_addr *ha;
5b8821b7 2000 int i = 0;
24307eef 2001
1610c79f
PR		 2002 /* Reset mcast promisc mode if already set by setting mask
2003 * and not setting flags field
2004 */
abb93951
PR		 2005 req->if_flags_mask |=
2006 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 2007 be_if_cap_flags(adapter));
016f97b1 2008 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 2009 netdev_for_each_mc_addr(ha, adapter->netdev)
2010 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 2011 }
2012
b6588879 2013 status = be_mcc_notify_wait(adapter);
713d0394 2014err:
8788fdc2 2015 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 2016 return status;
6b7c5b94
SP		 2017}
2018
ac34b743
SP		 2019int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2020{
2021 struct device *dev = &adapter->pdev->dev;
2022
2023 if ((flags & be_if_cap_flags(adapter)) != flags) {
2024 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2025 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2026 be_if_cap_flags(adapter));
2027 }
2028 flags &= be_if_cap_flags(adapter);
196e3735
KA		 2029 if (!flags)
2030 return -ENOTSUPP;
ac34b743
SP		 2031
2032 return __be_cmd_rx_filter(adapter, flags, value);
2033}
2034
b31c50a7 2035/* Uses synchrounous mcc */
8788fdc2 2036int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 2037{
b31c50a7
SP		 2038 struct be_mcc_wrb *wrb;
2039 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 2040 int status;
2041
f25b119c
PR		 2042 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2043 CMD_SUBSYSTEM_COMMON))
2044 return -EPERM;
2045
b31c50a7 2046 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2047
b31c50a7 2048 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2049 if (!wrb) {
2050 status = -EBUSY;
2051 goto err;
2052 }
b31c50a7 2053 req = embedded_payload(wrb);
6b7c5b94 2054
106df1e3 2055 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2056 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2057 wrb, NULL);
6b7c5b94 2058
b29812c1 2059 req->hdr.version = 1;
6b7c5b94
SP		 2060 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2061 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2062
b31c50a7 2063 status = be_mcc_notify_wait(adapter);
6b7c5b94 2064
713d0394 2065err:
b31c50a7 2066 spin_unlock_bh(&adapter->mcc_lock);
b29812c1
SR		 2067
2068 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2069 return -EOPNOTSUPP;
2070
6b7c5b94
SP		 2071 return status;
2072}
2073
b31c50a7 2074/* Uses sycn mcc */
8788fdc2 2075int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 2076{
b31c50a7
SP		 2077 struct be_mcc_wrb *wrb;
2078 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 2079 int status;
2080
f25b119c
PR		 2081 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2082 CMD_SUBSYSTEM_COMMON))
2083 return -EPERM;
2084
b31c50a7 2085 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2086
b31c50a7 2087 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2088 if (!wrb) {
2089 status = -EBUSY;
2090 goto err;
2091 }
b31c50a7 2092 req = embedded_payload(wrb);
6b7c5b94 2093
106df1e3 2094 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2095 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2096 wrb, NULL);
6b7c5b94 2097
b31c50a7 2098 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2099 if (!status) {
2100 struct be_cmd_resp_get_flow_control *resp =
2101 embedded_payload(wrb);
03d28ffe 2102
6b7c5b94
SP		 2103 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2104 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2105 }
2106
713d0394 2107err:
b31c50a7 2108 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 2109 return status;
2110}
2111
b31c50a7 2112/* Uses mbox */
e97e3cda 2113int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2114{
b31c50a7
SP		 2115 struct be_mcc_wrb *wrb;
2116 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2117 int status;
2118
2984961c
IV		 2119 if (mutex_lock_interruptible(&adapter->mbox_lock))
2120 return -1;
6b7c5b94 2121
b31c50a7
SP		 2122 wrb = wrb_from_mbox(adapter);
2123 req = embedded_payload(wrb);
6b7c5b94 2124
106df1e3 2125 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2126 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2127 sizeof(*req), wrb, NULL);
6b7c5b94 2128
b31c50a7 2129 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2130 if (!status) {
2131 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2132
e97e3cda
KA		 2133 adapter->port_num = le32_to_cpu(resp->phys_port);
2134 adapter->function_mode = le32_to_cpu(resp->function_mode);
2135 adapter->function_caps = le32_to_cpu(resp->function_caps);
2136 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2137 dev_info(&adapter->pdev->dev,
2138 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2139 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2140 }
2141
2984961c 2142 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2143 return status;
2144}
14074eab 2145
b31c50a7 2146/* Uses mbox */
14074eab 2147int be_cmd_reset_function(struct be_adapter *adapter)
2148{
b31c50a7
SP		 2149 struct be_mcc_wrb *wrb;
2150 struct be_cmd_req_hdr *req;
14074eab 2151 int status;
2152
bf99e50d 2153 if (lancer_chip(adapter)) {
9fa465c0
SP		 2154 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2155 adapter->db + SLIPORT_CONTROL_OFFSET);
bf99e50d 2156 status = lancer_wait_ready(adapter);
9fa465c0 2157 if (status)
bf99e50d
PR		 2158 dev_err(&adapter->pdev->dev,
2159 "Adapter in non recoverable error\n");
bf99e50d
PR		 2160 return status;
2161 }
2162
2984961c
IV		 2163 if (mutex_lock_interruptible(&adapter->mbox_lock))
2164 return -1;
14074eab 2165
b31c50a7
SP		 2166 wrb = wrb_from_mbox(adapter);
2167 req = embedded_payload(wrb);
14074eab 2168
106df1e3 2169 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2170 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2171 NULL);
14074eab 2172
b31c50a7 2173 status = be_mbox_notify_wait(adapter);
14074eab 2174
2984961c 2175 mutex_unlock(&adapter->mbox_lock);
14074eab 2176 return status;
2177}
84517482 2178
594ad54a 2179int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2180 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2181{
2182 struct be_mcc_wrb *wrb;
2183 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2184 int status;
2185
da1388d6
VV		 2186 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2187 return 0;
2188
b51aa367 2189 spin_lock_bh(&adapter->mcc_lock);
3abcdeda 2190
b51aa367
KA		 2191 wrb = wrb_from_mccq(adapter);
2192 if (!wrb) {
2193 status = -EBUSY;
2194 goto err;
2195 }
3abcdeda
SP		 2196 req = embedded_payload(wrb);
2197
106df1e3 2198 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2199 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2200
2201 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2202 req->enable_rss = cpu_to_le16(rss_hash_opts);
2203 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2204
b51aa367 2205 if (!BEx_chip(adapter))
d3bd3a5e 2206 req->hdr.version = 1;
d3bd3a5e 2207
3abcdeda 2208 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2209 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2210 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2211
b51aa367
KA		 2212 status = be_mcc_notify_wait(adapter);
2213err:
2214 spin_unlock_bh(&adapter->mcc_lock);
3abcdeda
SP		 2215 return status;
2216}
2217
fad9ab2c
SB		 2218/* Uses sync mcc */
2219int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2220 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2221{
2222 struct be_mcc_wrb *wrb;
2223 struct be_cmd_req_enable_disable_beacon *req;
2224 int status;
2225
2226 spin_lock_bh(&adapter->mcc_lock);
2227
2228 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2229 if (!wrb) {
2230 status = -EBUSY;
2231 goto err;
2232 }
fad9ab2c
SB		 2233 req = embedded_payload(wrb);
2234
106df1e3 2235 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2236 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2237 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2238
2239 req->port_num = port_num;
2240 req->beacon_state = state;
2241 req->beacon_duration = bcn;
2242 req->status_duration = sts;
2243
2244 status = be_mcc_notify_wait(adapter);
2245
713d0394 2246err:
fad9ab2c
SB		 2247 spin_unlock_bh(&adapter->mcc_lock);
2248 return status;
2249}
2250
2251/* Uses sync mcc */
2252int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2253{
2254 struct be_mcc_wrb *wrb;
2255 struct be_cmd_req_get_beacon_state *req;
2256 int status;
2257
2258 spin_lock_bh(&adapter->mcc_lock);
2259
2260 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2261 if (!wrb) {
2262 status = -EBUSY;
2263 goto err;
2264 }
fad9ab2c
SB		 2265 req = embedded_payload(wrb);
2266
106df1e3 2267 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2268 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2269 wrb, NULL);
fad9ab2c
SB		 2270
2271 req->port_num = port_num;
2272
2273 status = be_mcc_notify_wait(adapter);
2274 if (!status) {
2275 struct be_cmd_resp_get_beacon_state *resp =
2276 embedded_payload(wrb);
03d28ffe 2277
fad9ab2c
SB		 2278 *state = resp->beacon_state;
2279 }
2280
713d0394 2281err:
fad9ab2c
SB		 2282 spin_unlock_bh(&adapter->mcc_lock);
2283 return status;
2284}
2285
e36edd9d
ML		 2286/* Uses sync mcc */
2287int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2288 u8 page_num, u8 *data)
2289{
2290 struct be_dma_mem cmd;
2291 struct be_mcc_wrb *wrb;
2292 struct be_cmd_req_port_type *req;
2293 int status;
2294
2295 if (page_num > TR_PAGE_A2)
2296 return -EINVAL;
2297
2298 cmd.size = sizeof(struct be_cmd_resp_port_type);
e51000db
SB		 2299 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2300 GFP_ATOMIC);
e36edd9d
ML		 2301 if (!cmd.va) {
2302 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2303 return -ENOMEM;
2304 }
e36edd9d
ML		 2305
2306 spin_lock_bh(&adapter->mcc_lock);
2307
2308 wrb = wrb_from_mccq(adapter);
2309 if (!wrb) {
2310 status = -EBUSY;
2311 goto err;
2312 }
2313 req = cmd.va;
2314
2315 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2316 OPCODE_COMMON_READ_TRANSRECV_DATA,
2317 cmd.size, wrb, &cmd);
2318
2319 req->port = cpu_to_le32(adapter->hba_port_num);
2320 req->page_num = cpu_to_le32(page_num);
2321 status = be_mcc_notify_wait(adapter);
2322 if (!status) {
2323 struct be_cmd_resp_port_type *resp = cmd.va;
2324
2325 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2326 }
2327err:
2328 spin_unlock_bh(&adapter->mcc_lock);
e51000db 2329 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
e36edd9d
ML		 2330 return status;
2331}
2332
a23113b5
SR		 2333static int lancer_cmd_write_object(struct be_adapter *adapter,
2334 struct be_dma_mem *cmd, u32 data_size,
2335 u32 data_offset, const char *obj_name,
2336 u32 *data_written, u8 *change_status,
2337 u8 *addn_status)
485bf569
SN		 2338{
2339 struct be_mcc_wrb *wrb;
2340 struct lancer_cmd_req_write_object *req;
2341 struct lancer_cmd_resp_write_object *resp;
2342 void *ctxt = NULL;
2343 int status;
2344
2345 spin_lock_bh(&adapter->mcc_lock);
2346 adapter->flash_status = 0;
2347
2348 wrb = wrb_from_mccq(adapter);
2349 if (!wrb) {
2350 status = -EBUSY;
2351 goto err_unlock;
2352 }
2353
2354 req = embedded_payload(wrb);
2355
106df1e3 2356 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2357 OPCODE_COMMON_WRITE_OBJECT,
2358 sizeof(struct lancer_cmd_req_write_object), wrb,
2359 NULL);
485bf569
SN		 2360
2361 ctxt = &req->context;
2362 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2363 write_length, ctxt, data_size);
485bf569
SN		 2364
2365 if (data_size == 0)
2366 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2367 eof, ctxt, 1);
485bf569
SN		 2368 else
2369 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2370 eof, ctxt, 0);
485bf569
SN		 2371
2372 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2373 req->write_offset = cpu_to_le32(data_offset);
242eb470 2374 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2375 req->descriptor_count = cpu_to_le32(1);
2376 req->buf_len = cpu_to_le32(data_size);
2377 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2378 sizeof(struct lancer_cmd_req_write_object))
2379 & 0xFFFFFFFF);
485bf569
SN		 2380 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2381 sizeof(struct lancer_cmd_req_write_object)));
2382
efaa408e
SR		 2383 status = be_mcc_notify(adapter);
2384 if (status)
2385 goto err_unlock;
2386
485bf569
SN		 2387 spin_unlock_bh(&adapter->mcc_lock);
2388
5eeff635 2389 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2390 msecs_to_jiffies(60000)))
fd45160c 2391 status = -ETIMEDOUT;
485bf569
SN		 2392 else
2393 status = adapter->flash_status;
2394
2395 resp = embedded_payload(wrb);
f67ef7ba 2396 if (!status) {
485bf569 2397 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2398 *change_status = resp->change_status;
2399 } else {
485bf569 2400 *addn_status = resp->additional_status;
f67ef7ba 2401 }
485bf569
SN		 2402
2403 return status;
2404
2405err_unlock:
2406 spin_unlock_bh(&adapter->mcc_lock);
2407 return status;
2408}
2409
6809cee0
RN		 2410int be_cmd_query_cable_type(struct be_adapter *adapter)
2411{
2412 u8 page_data[PAGE_DATA_LEN];
2413 int status;
2414
2415 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2416 page_data);
2417 if (!status) {
2418 switch (adapter->phy.interface_type) {
2419 case PHY_TYPE_QSFP:
2420 adapter->phy.cable_type =
2421 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2422 break;
2423 case PHY_TYPE_SFP_PLUS_10GB:
2424 adapter->phy.cable_type =
2425 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2426 break;
2427 default:
2428 adapter->phy.cable_type = 0;
2429 break;
2430 }
2431 }
2432 return status;
2433}
2434
21252377
VV		 2435int be_cmd_query_sfp_info(struct be_adapter *adapter)
2436{
2437 u8 page_data[PAGE_DATA_LEN];
2438 int status;
2439
2440 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2441 page_data);
2442 if (!status) {
2443 strlcpy(adapter->phy.vendor_name, page_data +
2444 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2445 strlcpy(adapter->phy.vendor_pn,
2446 page_data + SFP_VENDOR_PN_OFFSET,
2447 SFP_VENDOR_NAME_LEN - 1);
2448 }
2449
2450 return status;
2451}
2452
a23113b5
SR		 2453static int lancer_cmd_delete_object(struct be_adapter *adapter,
2454 const char *obj_name)
f0613380
KA		 2455{
2456 struct lancer_cmd_req_delete_object *req;
2457 struct be_mcc_wrb *wrb;
2458 int status;
2459
2460 spin_lock_bh(&adapter->mcc_lock);
2461
2462 wrb = wrb_from_mccq(adapter);
2463 if (!wrb) {
2464 status = -EBUSY;
2465 goto err;
2466 }
2467
2468 req = embedded_payload(wrb);
2469
2470 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2471 OPCODE_COMMON_DELETE_OBJECT,
2472 sizeof(*req), wrb, NULL);
2473
242eb470 2474 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2475
2476 status = be_mcc_notify_wait(adapter);
2477err:
2478 spin_unlock_bh(&adapter->mcc_lock);
2479 return status;
2480}
2481
de49bd5a 2482int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2483 u32 data_size, u32 data_offset, const char *obj_name,
2484 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2485{
2486 struct be_mcc_wrb *wrb;
2487 struct lancer_cmd_req_read_object *req;
2488 struct lancer_cmd_resp_read_object *resp;
2489 int status;
2490
2491 spin_lock_bh(&adapter->mcc_lock);
2492
2493 wrb = wrb_from_mccq(adapter);
2494 if (!wrb) {
2495 status = -EBUSY;
2496 goto err_unlock;
2497 }
2498
2499 req = embedded_payload(wrb);
2500
2501 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2502 OPCODE_COMMON_READ_OBJECT,
2503 sizeof(struct lancer_cmd_req_read_object), wrb,
2504 NULL);
de49bd5a
PR		 2505
2506 req->desired_read_len = cpu_to_le32(data_size);
2507 req->read_offset = cpu_to_le32(data_offset);
2508 strcpy(req->object_name, obj_name);
2509 req->descriptor_count = cpu_to_le32(1);
2510 req->buf_len = cpu_to_le32(data_size);
2511 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2512 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2513
2514 status = be_mcc_notify_wait(adapter);
2515
2516 resp = embedded_payload(wrb);
2517 if (!status) {
2518 *data_read = le32_to_cpu(resp->actual_read_len);
2519 *eof = le32_to_cpu(resp->eof);
2520 } else {
2521 *addn_status = resp->additional_status;
2522 }
2523
2524err_unlock:
2525 spin_unlock_bh(&adapter->mcc_lock);
2526 return status;
2527}
2528
a23113b5
SR		 2529static int be_cmd_write_flashrom(struct be_adapter *adapter,
2530 struct be_dma_mem *cmd, u32 flash_type,
2531 u32 flash_opcode, u32 img_offset, u32 buf_size)
84517482 2532{
b31c50a7 2533 struct be_mcc_wrb *wrb;
3f0d4560 2534 struct be_cmd_write_flashrom *req;
84517482
AK		 2535 int status;
2536
b31c50a7 2537 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2538 adapter->flash_status = 0;
b31c50a7
SP		 2539
2540 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2541 if (!wrb) {
2542 status = -EBUSY;
2892d9c2 2543 goto err_unlock;
713d0394
SP		 2544 }
2545 req = cmd->va;
84517482 2546
106df1e3 2547 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2548 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2549 cmd);
84517482
AK		 2550
2551 req->params.op_type = cpu_to_le32(flash_type);
70a7b525
VV		 2552 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2553 req->params.offset = cpu_to_le32(img_offset);
2554
84517482
AK		 2555 req->params.op_code = cpu_to_le32(flash_opcode);
2556 req->params.data_buf_size = cpu_to_le32(buf_size);
2557
efaa408e
SR		 2558 status = be_mcc_notify(adapter);
2559 if (status)
2560 goto err_unlock;
2561
dd131e76
SB		 2562 spin_unlock_bh(&adapter->mcc_lock);
2563
5eeff635
SR		 2564 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2565 msecs_to_jiffies(40000)))
fd45160c 2566 status = -ETIMEDOUT;
dd131e76
SB		 2567 else
2568 status = adapter->flash_status;
84517482 2569
2892d9c2
DC		 2570 return status;
2571
2572err_unlock:
2573 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2574 return status;
2575}
fa9a6fed 2576
a23113b5
SR		 2577static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2578 u16 img_optype, u32 img_offset, u32 crc_offset)
fa9a6fed 2579{
be716446 2580 struct be_cmd_read_flash_crc *req;
70a7b525 2581 struct be_mcc_wrb *wrb;
fa9a6fed
SB		 2582 int status;
2583
2584 spin_lock_bh(&adapter->mcc_lock);
2585
2586 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2587 if (!wrb) {
2588 status = -EBUSY;
2589 goto err;
2590 }
fa9a6fed
SB		 2591 req = embedded_payload(wrb);
2592
106df1e3 2593 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2594 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2595 wrb, NULL);
fa9a6fed 2596
70a7b525
VV		 2597 req->params.op_type = cpu_to_le32(img_optype);
2598 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2599 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2600 else
2601 req->params.offset = cpu_to_le32(crc_offset);
2602
fa9a6fed 2603 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710 2604 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2605
2606 status = be_mcc_notify_wait(adapter);
2607 if (!status)
be716446 2608 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2609
713d0394 2610err:
fa9a6fed
SB		 2611 spin_unlock_bh(&adapter->mcc_lock);
2612 return status;
2613}
71d8d1b5 2614
a23113b5
SR		 2615static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2616
2617static bool phy_flashing_required(struct be_adapter *adapter)
2618{
2619 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2620 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2621}
2622
2623static bool is_comp_in_ufi(struct be_adapter *adapter,
2624 struct flash_section_info *fsec, int type)
2625{
2626 int i = 0, img_type = 0;
2627 struct flash_section_info_g2 *fsec_g2 = NULL;
2628
2629 if (BE2_chip(adapter))
2630 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2631
2632 for (i = 0; i < MAX_FLASH_COMP; i++) {
2633 if (fsec_g2)
2634 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2635 else
2636 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2637
2638 if (img_type == type)
2639 return true;
2640 }
2641 return false;
2642}
2643
2644static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2645 int header_size,
2646 const struct firmware *fw)
2647{
2648 struct flash_section_info *fsec = NULL;
2649 const u8 *p = fw->data;
2650
2651 p += header_size;
2652 while (p < (fw->data + fw->size)) {
2653 fsec = (struct flash_section_info *)p;
2654 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2655 return fsec;
2656 p += 32;
2657 }
2658 return NULL;
2659}
2660
2661static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2662 u32 img_offset, u32 img_size, int hdr_size,
2663 u16 img_optype, bool *crc_match)
2664{
2665 u32 crc_offset;
2666 int status;
2667 u8 crc[4];
2668
2669 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2670 img_size - 4);
2671 if (status)
2672 return status;
2673
2674 crc_offset = hdr_size + img_offset + img_size - 4;
2675
2676 /* Skip flashing, if crc of flashed region matches */
2677 if (!memcmp(crc, p + crc_offset, 4))
2678 *crc_match = true;
2679 else
2680 *crc_match = false;
2681
2682 return status;
2683}
2684
2685static int be_flash(struct be_adapter *adapter, const u8 *img,
2686 struct be_dma_mem *flash_cmd, int optype, int img_size,
2687 u32 img_offset)
2688{
2689 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2690 struct be_cmd_write_flashrom *req = flash_cmd->va;
2691 int status;
2692
2693 while (total_bytes) {
2694 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2695
2696 total_bytes -= num_bytes;
2697
2698 if (!total_bytes) {
2699 if (optype == OPTYPE_PHY_FW)
2700 flash_op = FLASHROM_OPER_PHY_FLASH;
2701 else
2702 flash_op = FLASHROM_OPER_FLASH;
2703 } else {
2704 if (optype == OPTYPE_PHY_FW)
2705 flash_op = FLASHROM_OPER_PHY_SAVE;
2706 else
2707 flash_op = FLASHROM_OPER_SAVE;
2708 }
2709
2710 memcpy(req->data_buf, img, num_bytes);
2711 img += num_bytes;
2712 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2713 flash_op, img_offset +
2714 bytes_sent, num_bytes);
2715 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2716 optype == OPTYPE_PHY_FW)
2717 break;
2718 else if (status)
2719 return status;
2720
2721 bytes_sent += num_bytes;
2722 }
2723 return 0;
2724}
2725
2726/* For BE2, BE3 and BE3-R */
2727static int be_flash_BEx(struct be_adapter *adapter,
2728 const struct firmware *fw,
2729 struct be_dma_mem *flash_cmd, int num_of_images)
2730{
2731 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2732 struct device *dev = &adapter->pdev->dev;
2733 struct flash_section_info *fsec = NULL;
2734 int status, i, filehdr_size, num_comp;
2735 const struct flash_comp *pflashcomp;
2736 bool crc_match;
2737 const u8 *p;
2738
2739 struct flash_comp gen3_flash_types[] = {
2740 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2741 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2742 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2743 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2744 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2745 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2746 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2747 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2748 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2749 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2750 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2751 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2752 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2753 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2754 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2755 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2756 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2757 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2758 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2759 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2760 };
2761
2762 struct flash_comp gen2_flash_types[] = {
2763 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2764 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2765 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2766 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2767 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2768 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2769 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2770 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2771 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2772 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2773 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2774 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2775 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2776 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2777 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2778 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2779 };
2780
2781 if (BE3_chip(adapter)) {
2782 pflashcomp = gen3_flash_types;
2783 filehdr_size = sizeof(struct flash_file_hdr_g3);
2784 num_comp = ARRAY_SIZE(gen3_flash_types);
2785 } else {
2786 pflashcomp = gen2_flash_types;
2787 filehdr_size = sizeof(struct flash_file_hdr_g2);
2788 num_comp = ARRAY_SIZE(gen2_flash_types);
2789 img_hdrs_size = 0;
2790 }
2791
2792 /* Get flash section info*/
2793 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2794 if (!fsec) {
2795 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2796 return -1;
2797 }
2798 for (i = 0; i < num_comp; i++) {
2799 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2800 continue;
2801
2802 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2803 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2804 continue;
2805
2806 if (pflashcomp[i].optype == OPTYPE_PHY_FW &&
2807 !phy_flashing_required(adapter))
2808 continue;
2809
2810 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2811 status = be_check_flash_crc(adapter, fw->data,
2812 pflashcomp[i].offset,
2813 pflashcomp[i].size,
2814 filehdr_size +
2815 img_hdrs_size,
2816 OPTYPE_REDBOOT, &crc_match);
2817 if (status) {
2818 dev_err(dev,
2819 "Could not get CRC for 0x%x region\n",
2820 pflashcomp[i].optype);
2821 continue;
2822 }
2823
2824 if (crc_match)
2825 continue;
2826 }
2827
2828 p = fw->data + filehdr_size + pflashcomp[i].offset +
2829 img_hdrs_size;
2830 if (p + pflashcomp[i].size > fw->data + fw->size)
2831 return -1;
2832
2833 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2834 pflashcomp[i].size, 0);
2835 if (status) {
2836 dev_err(dev, "Flashing section type 0x%x failed\n",
2837 pflashcomp[i].img_type);
2838 return status;
2839 }
2840 }
2841 return 0;
2842}
2843
2844static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2845{
2846 u32 img_type = le32_to_cpu(fsec_entry.type);
2847 u16 img_optype = le16_to_cpu(fsec_entry.optype);
2848
2849 if (img_optype != 0xFFFF)
2850 return img_optype;
2851
2852 switch (img_type) {
2853 case IMAGE_FIRMWARE_ISCSI:
2854 img_optype = OPTYPE_ISCSI_ACTIVE;
2855 break;
2856 case IMAGE_BOOT_CODE:
2857 img_optype = OPTYPE_REDBOOT;
2858 break;
2859 case IMAGE_OPTION_ROM_ISCSI:
2860 img_optype = OPTYPE_BIOS;
2861 break;
2862 case IMAGE_OPTION_ROM_PXE:
2863 img_optype = OPTYPE_PXE_BIOS;
2864 break;
2865 case IMAGE_OPTION_ROM_FCOE:
2866 img_optype = OPTYPE_FCOE_BIOS;
2867 break;
2868 case IMAGE_FIRMWARE_BACKUP_ISCSI:
2869 img_optype = OPTYPE_ISCSI_BACKUP;
2870 break;
2871 case IMAGE_NCSI:
2872 img_optype = OPTYPE_NCSI_FW;
2873 break;
2874 case IMAGE_FLASHISM_JUMPVECTOR:
2875 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2876 break;
2877 case IMAGE_FIRMWARE_PHY:
2878 img_optype = OPTYPE_SH_PHY_FW;
2879 break;
2880 case IMAGE_REDBOOT_DIR:
2881 img_optype = OPTYPE_REDBOOT_DIR;
2882 break;
2883 case IMAGE_REDBOOT_CONFIG:
2884 img_optype = OPTYPE_REDBOOT_CONFIG;
2885 break;
2886 case IMAGE_UFI_DIR:
2887 img_optype = OPTYPE_UFI_DIR;
2888 break;
2889 default:
2890 break;
2891 }
2892
2893 return img_optype;
2894}
2895
2896static int be_flash_skyhawk(struct be_adapter *adapter,
2897 const struct firmware *fw,
2898 struct be_dma_mem *flash_cmd, int num_of_images)
2899{
2900 int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2901 bool crc_match, old_fw_img, flash_offset_support = true;
2902 struct device *dev = &adapter->pdev->dev;
2903 struct flash_section_info *fsec = NULL;
2904 u32 img_offset, img_size, img_type;
2905 u16 img_optype, flash_optype;
2906 int status, i, filehdr_size;
2907 const u8 *p;
2908
2909 filehdr_size = sizeof(struct flash_file_hdr_g3);
2910 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2911 if (!fsec) {
2912 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2913 return -EINVAL;
2914 }
2915
2916retry_flash:
2917 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2918 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2919 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2920 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2921 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2922 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2923
2924 if (img_optype == 0xFFFF)
2925 continue;
2926
2927 if (flash_offset_support)
2928 flash_optype = OPTYPE_OFFSET_SPECIFIED;
2929 else
2930 flash_optype = img_optype;
2931
2932 /* Don't bother verifying CRC if an old FW image is being
2933 * flashed
2934 */
2935 if (old_fw_img)
2936 goto flash;
2937
2938 status = be_check_flash_crc(adapter, fw->data, img_offset,
2939 img_size, filehdr_size +
2940 img_hdrs_size, flash_optype,
2941 &crc_match);
2942 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2943 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2944 /* The current FW image on the card does not support
2945 * OFFSET based flashing. Retry using older mechanism
2946 * of OPTYPE based flashing
2947 */
2948 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2949 flash_offset_support = false;
2950 goto retry_flash;
2951 }
2952
2953 /* The current FW image on the card does not recognize
2954 * the new FLASH op_type. The FW download is partially
2955 * complete. Reboot the server now to enable FW image
2956 * to recognize the new FLASH op_type. To complete the
2957 * remaining process, download the same FW again after
2958 * the reboot.
2959 */
2960 dev_err(dev, "Flash incomplete. Reset the server\n");
2961 dev_err(dev, "Download FW image again after reset\n");
2962 return -EAGAIN;
2963 } else if (status) {
2964 dev_err(dev, "Could not get CRC for 0x%x region\n",
2965 img_optype);
2966 return -EFAULT;
2967 }
2968
2969 if (crc_match)
2970 continue;
2971
2972flash:
2973 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2974 if (p + img_size > fw->data + fw->size)
2975 return -1;
2976
2977 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
2978 img_offset);
2979
2980 /* The current FW image on the card does not support OFFSET
2981 * based flashing. Retry using older mechanism of OPTYPE based
2982 * flashing
2983 */
2984 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
2985 flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2986 flash_offset_support = false;
2987 goto retry_flash;
2988 }
2989
2990 /* For old FW images ignore ILLEGAL_FIELD error or errors on
2991 * UFI_DIR region
2992 */
2993 if (old_fw_img &&
2994 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
2995 (img_optype == OPTYPE_UFI_DIR &&
2996 base_status(status) == MCC_STATUS_FAILED))) {
2997 continue;
2998 } else if (status) {
2999 dev_err(dev, "Flashing section type 0x%x failed\n",
3000 img_type);
6b525782
SR		 3001
3002 switch (addl_status(status)) {
3003 case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3004 dev_err(dev,
3005 "Digital signature missing in FW\n");
3006 return -EINVAL;
3007 case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3008 dev_err(dev,
3009 "Invalid digital signature in FW\n");
3010 return -EINVAL;
3011 default:
3012 return -EFAULT;
3013 }
a23113b5
SR		 3014 }
3015 }
3016 return 0;
3017}
3018
3019int lancer_fw_download(struct be_adapter *adapter,
3020 const struct firmware *fw)
3021{
3022 struct device *dev = &adapter->pdev->dev;
3023 struct be_dma_mem flash_cmd;
3024 const u8 *data_ptr = NULL;
3025 u8 *dest_image_ptr = NULL;
3026 size_t image_size = 0;
3027 u32 chunk_size = 0;
3028 u32 data_written = 0;
3029 u32 offset = 0;
3030 int status = 0;
3031 u8 add_status = 0;
3032 u8 change_status;
3033
3034 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3035 dev_err(dev, "FW image size should be multiple of 4\n");
3036 return -EINVAL;
3037 }
3038
3039 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3040 + LANCER_FW_DOWNLOAD_CHUNK;
3041 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3042 &flash_cmd.dma, GFP_KERNEL);
3043 if (!flash_cmd.va)
3044 return -ENOMEM;
3045
3046 dest_image_ptr = flash_cmd.va +
3047 sizeof(struct lancer_cmd_req_write_object);
3048 image_size = fw->size;
3049 data_ptr = fw->data;
3050
3051 while (image_size) {
3052 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3053
3054 /* Copy the image chunk content. */
3055 memcpy(dest_image_ptr, data_ptr, chunk_size);
3056
3057 status = lancer_cmd_write_object(adapter, &flash_cmd,
3058 chunk_size, offset,
3059 LANCER_FW_DOWNLOAD_LOCATION,
3060 &data_written, &change_status,
3061 &add_status);
3062 if (status)
3063 break;
3064
3065 offset += data_written;
3066 data_ptr += data_written;
3067 image_size -= data_written;
3068 }
3069
3070 if (!status) {
3071 /* Commit the FW written */
3072 status = lancer_cmd_write_object(adapter, &flash_cmd,
3073 0, offset,
3074 LANCER_FW_DOWNLOAD_LOCATION,
3075 &data_written, &change_status,
3076 &add_status);
3077 }
3078
3079 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3080 if (status) {
3081 dev_err(dev, "Firmware load error\n");
3082 return be_cmd_status(status);
3083 }
3084
3085 dev_info(dev, "Firmware flashed successfully\n");
3086
3087 if (change_status == LANCER_FW_RESET_NEEDED) {
3088 dev_info(dev, "Resetting adapter to activate new FW\n");
3089 status = lancer_physdev_ctrl(adapter,
3090 PHYSDEV_CONTROL_FW_RESET_MASK);
3091 if (status) {
3092 dev_err(dev, "Adapter busy, could not reset FW\n");
3093 dev_err(dev, "Reboot server to activate new FW\n");
3094 }
3095 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3096 dev_info(dev, "Reboot server to activate new FW\n");
3097 }
3098
3099 return 0;
3100}
3101
3102/* Check if the flash image file is compatible with the adapter that
3103 * is being flashed.
3104 */
3105static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3106 struct flash_file_hdr_g3 *fhdr)
3107{
3108 if (!fhdr) {
3109 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3110 return false;
3111 }
3112
3113 /* First letter of the build version is used to identify
3114 * which chip this image file is meant for.
3115 */
3116 switch (fhdr->build[0]) {
3117 case BLD_STR_UFI_TYPE_SH:
3118 if (!skyhawk_chip(adapter))
3119 return false;
3120 break;
3121 case BLD_STR_UFI_TYPE_BE3:
3122 if (!BE3_chip(adapter))
3123 return false;
3124 break;
3125 case BLD_STR_UFI_TYPE_BE2:
3126 if (!BE2_chip(adapter))
3127 return false;
3128 break;
3129 default:
3130 return false;
3131 }
3132
3133 /* In BE3 FW images the "asic_type_rev" field doesn't track the
3134 * asic_rev of the chips it is compatible with.
3135 * When asic_type_rev is 0 the image is compatible only with
3136 * pre-BE3-R chips (asic_rev < 0x10)
3137 */
3138 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3139 return adapter->asic_rev < 0x10;
3140 else
3141 return (fhdr->asic_type_rev >= adapter->asic_rev);
3142}
3143
3144int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3145{
3146 struct device *dev = &adapter->pdev->dev;
3147 struct flash_file_hdr_g3 *fhdr3;
3148 struct image_hdr *img_hdr_ptr;
3149 int status = 0, i, num_imgs;
3150 struct be_dma_mem flash_cmd;
3151
3152 fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3153 if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3154 dev_err(dev, "Flash image is not compatible with adapter\n");
3155 return -EINVAL;
3156 }
3157
3158 flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3159 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3160 GFP_KERNEL);
3161 if (!flash_cmd.va)
3162 return -ENOMEM;
3163
3164 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3165 for (i = 0; i < num_imgs; i++) {
3166 img_hdr_ptr = (struct image_hdr *)(fw->data +
3167 (sizeof(struct flash_file_hdr_g3) +
3168 i * sizeof(struct image_hdr)));
3169 if (!BE2_chip(adapter) &&
3170 le32_to_cpu(img_hdr_ptr->imageid) != 1)
3171 continue;
3172
3173 if (skyhawk_chip(adapter))
3174 status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3175 num_imgs);
3176 else
3177 status = be_flash_BEx(adapter, fw, &flash_cmd,
3178 num_imgs);
3179 }
3180
3181 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3182 if (!status)
3183 dev_info(dev, "Firmware flashed successfully\n");
3184
3185 return status;
3186}
3187
c196b02c 3188int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 3189 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 3190{
3191 struct be_mcc_wrb *wrb;
3192 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 3193 int status;
3194
3195 spin_lock_bh(&adapter->mcc_lock);
3196
3197 wrb = wrb_from_mccq(adapter);
3198 if (!wrb) {
3199 status = -EBUSY;
3200 goto err;
3201 }
3202 req = nonemb_cmd->va;
71d8d1b5 3203
106df1e3 3204 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 3205 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3206 wrb, nonemb_cmd);
71d8d1b5
AK		 3207 memcpy(req->magic_mac, mac, ETH_ALEN);
3208
71d8d1b5
AK		 3209 status = be_mcc_notify_wait(adapter);
3210
3211err:
3212 spin_unlock_bh(&adapter->mcc_lock);
3213 return status;
3214}
ff33a6e2 3215
fced9999
SB		 3216int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3217 u8 loopback_type, u8 enable)
3218{
3219 struct be_mcc_wrb *wrb;
3220 struct be_cmd_req_set_lmode *req;
3221 int status;
3222
2e365b1b
SK		 3223 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3224 CMD_SUBSYSTEM_LOWLEVEL))
3225 return -EPERM;
3226
fced9999
SB		 3227 spin_lock_bh(&adapter->mcc_lock);
3228
3229 wrb = wrb_from_mccq(adapter);
3230 if (!wrb) {
3231 status = -EBUSY;
9c855975 3232 goto err_unlock;
fced9999
SB		 3233 }
3234
3235 req = embedded_payload(wrb);
3236
106df1e3 3237 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3238 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3239 wrb, NULL);
fced9999
SB		 3240
3241 req->src_port = port_num;
3242 req->dest_port = port_num;
3243 req->loopback_type = loopback_type;
3244 req->loopback_state = enable;
3245
9c855975
SR		 3246 status = be_mcc_notify(adapter);
3247 if (status)
3248 goto err_unlock;
3249
3250 spin_unlock_bh(&adapter->mcc_lock);
3251
3252 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3253 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3254 status = -ETIMEDOUT;
3255
3256 return status;
3257
3258err_unlock:
fced9999
SB		 3259 spin_unlock_bh(&adapter->mcc_lock);
3260 return status;
3261}
3262
ff33a6e2 3263int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 3264 u32 loopback_type, u32 pkt_size, u32 num_pkts,
3265 u64 pattern)
ff33a6e2
S		 3266{
3267 struct be_mcc_wrb *wrb;
3268 struct be_cmd_req_loopback_test *req;
5eeff635 3269 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 3270 int status;
3271
2e365b1b
SK		 3272 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3273 CMD_SUBSYSTEM_LOWLEVEL))
3274 return -EPERM;
3275
ff33a6e2
S		 3276 spin_lock_bh(&adapter->mcc_lock);
3277
3278 wrb = wrb_from_mccq(adapter);
3279 if (!wrb) {
3280 status = -EBUSY;
3281 goto err;
3282 }
3283
3284 req = embedded_payload(wrb);
3285
106df1e3 3286 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3287 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3288 NULL);
ff33a6e2 3289
5eeff635 3290 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 3291 req->pattern = cpu_to_le64(pattern);
3292 req->src_port = cpu_to_le32(port_num);
3293 req->dest_port = cpu_to_le32(port_num);
3294 req->pkt_size = cpu_to_le32(pkt_size);
3295 req->num_pkts = cpu_to_le32(num_pkts);
3296 req->loopback_type = cpu_to_le32(loopback_type);
3297
efaa408e
SR		 3298 status = be_mcc_notify(adapter);
3299 if (status)
3300 goto err;
5eeff635
SR		 3301
3302 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 3303
5eeff635
SR		 3304 wait_for_completion(&adapter->et_cmd_compl);
3305 resp = embedded_payload(wrb);
3306 status = le32_to_cpu(resp->status);
3307
3308 return status;
ff33a6e2
S		 3309err:
3310 spin_unlock_bh(&adapter->mcc_lock);
3311 return status;
3312}
3313
3314int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 3315 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 3316{
3317 struct be_mcc_wrb *wrb;
3318 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 3319 int status;
3320 int i, j = 0;
3321
2e365b1b
SK		 3322 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3323 CMD_SUBSYSTEM_LOWLEVEL))
3324 return -EPERM;
3325
ff33a6e2
S		 3326 spin_lock_bh(&adapter->mcc_lock);
3327
3328 wrb = wrb_from_mccq(adapter);
3329 if (!wrb) {
3330 status = -EBUSY;
3331 goto err;
3332 }
3333 req = cmd->va;
106df1e3 3334 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3335 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3336 cmd);
ff33a6e2
S		 3337
3338 req->pattern = cpu_to_le64(pattern);
3339 req->byte_count = cpu_to_le32(byte_cnt);
3340 for (i = 0; i < byte_cnt; i++) {
3341 req->snd_buff[i] = (u8)(pattern >> (j*8));
3342 j++;
3343 if (j > 7)
3344 j = 0;
3345 }
3346
3347 status = be_mcc_notify_wait(adapter);
3348
3349 if (!status) {
3350 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 3351
ff33a6e2
S		 3352 resp = cmd->va;
3353 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
cd3307aa 3354 resp->snd_err) {
ff33a6e2
S		 3355 status = -1;
3356 }
3357 }
3358
3359err:
3360 spin_unlock_bh(&adapter->mcc_lock);
3361 return status;
3362}
368c0ca2 3363
c196b02c 3364int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 3365 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 3366{
3367 struct be_mcc_wrb *wrb;
3368 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 3369 int status;
3370
3371 spin_lock_bh(&adapter->mcc_lock);
3372
3373 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 3374 if (!wrb) {
3375 status = -EBUSY;
3376 goto err;
3377 }
368c0ca2 3378 req = nonemb_cmd->va;
368c0ca2 3379
106df1e3 3380 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3381 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3382 nonemb_cmd);
368c0ca2
SB		 3383
3384 status = be_mcc_notify_wait(adapter);
3385
e45ff01d 3386err:
368c0ca2
SB		 3387 spin_unlock_bh(&adapter->mcc_lock);
3388 return status;
3389}
ee3cb629 3390
42f11cf2 3391int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 3392{
3393 struct be_mcc_wrb *wrb;
3394 struct be_cmd_req_get_phy_info *req;
306f1348 3395 struct be_dma_mem cmd;
ee3cb629
AK		 3396 int status;
3397
f25b119c
PR		 3398 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3399 CMD_SUBSYSTEM_COMMON))
3400 return -EPERM;
3401
ee3cb629
AK		 3402 spin_lock_bh(&adapter->mcc_lock);
3403
3404 wrb = wrb_from_mccq(adapter);
3405 if (!wrb) {
3406 status = -EBUSY;
3407 goto err;
3408 }
306f1348 3409 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
e51000db
SB		 3410 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3411 GFP_ATOMIC);
306f1348
SP		 3412 if (!cmd.va) {
3413 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3414 status = -ENOMEM;
3415 goto err;
3416 }
ee3cb629 3417
306f1348 3418 req = cmd.va;
ee3cb629 3419
106df1e3 3420 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3421 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3422 wrb, &cmd);
ee3cb629
AK		 3423
3424 status = be_mcc_notify_wait(adapter);
306f1348
SP		 3425 if (!status) {
3426 struct be_phy_info *resp_phy_info =
3427 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 3428
42f11cf2
AK		 3429 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3430 adapter->phy.interface_type =
306f1348 3431 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 3432 adapter->phy.auto_speeds_supported =
3433 le16_to_cpu(resp_phy_info->auto_speeds_supported);
3434 adapter->phy.fixed_speeds_supported =
3435 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3436 adapter->phy.misc_params =
3437 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 3438
3439 if (BE2_chip(adapter)) {
3440 adapter->phy.fixed_speeds_supported =
3441 BE_SUPPORTED_SPEED_10GBPS |
3442 BE_SUPPORTED_SPEED_1GBPS;
3443 }
306f1348 3444 }
e51000db 3445 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
ee3cb629
AK		 3446err:
3447 spin_unlock_bh(&adapter->mcc_lock);
3448 return status;
3449}
e1d18735 3450
bc0ee163 3451static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
e1d18735
AK		 3452{
3453 struct be_mcc_wrb *wrb;
3454 struct be_cmd_req_set_qos *req;
3455 int status;
3456
3457 spin_lock_bh(&adapter->mcc_lock);
3458
3459 wrb = wrb_from_mccq(adapter);
3460 if (!wrb) {
3461 status = -EBUSY;
3462 goto err;
3463 }
3464
3465 req = embedded_payload(wrb);
3466
106df1e3 3467 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 3468 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 3469
3470 req->hdr.domain = domain;
6bff57a7
AK		 3471 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3472 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 3473
3474 status = be_mcc_notify_wait(adapter);
3475
3476err:
3477 spin_unlock_bh(&adapter->mcc_lock);
3478 return status;
3479}
9e1453c5
AK		 3480
3481int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3482{
3483 struct be_mcc_wrb *wrb;
3484 struct be_cmd_req_cntl_attribs *req;
3485 struct be_cmd_resp_cntl_attribs *resp;
a155a5db 3486 int status, i;
9e1453c5
AK		 3487 int payload_len = max(sizeof(*req), sizeof(*resp));
3488 struct mgmt_controller_attrib *attribs;
3489 struct be_dma_mem attribs_cmd;
a155a5db 3490 u32 *serial_num;
9e1453c5 3491
d98ef50f
SR		 3492 if (mutex_lock_interruptible(&adapter->mbox_lock))
3493 return -1;
3494
9e1453c5
AK		 3495 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3496 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
e51000db
SB		 3497 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3498 attribs_cmd.size,
3499 &attribs_cmd.dma, GFP_ATOMIC);
9e1453c5 3500 if (!attribs_cmd.va) {
a2cc4e0b 3501 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3502 status = -ENOMEM;
3503 goto err;
9e1453c5
AK		 3504 }
3505
9e1453c5
AK		 3506 wrb = wrb_from_mbox(adapter);
3507 if (!wrb) {
3508 status = -EBUSY;
3509 goto err;
3510 }
3511 req = attribs_cmd.va;
9e1453c5 3512
106df1e3 3513 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3514 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3515 wrb, &attribs_cmd);
9e1453c5
AK		 3516
3517 status = be_mbox_notify_wait(adapter);
3518 if (!status) {
43d620c8 3519 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5 3520 adapter->hba_port_num = attribs->hba_attribs.phy_port;
a155a5db
SB		 3521 serial_num = attribs->hba_attribs.controller_serial_number;
3522 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3523 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3524 (BIT_MASK(16) - 1);
9e1453c5
AK		 3525 }
3526
3527err:
3528 mutex_unlock(&adapter->mbox_lock);
d98ef50f 3529 if (attribs_cmd.va)
e51000db
SB		 3530 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3531 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 3532 return status;
3533}
2e588f84
SP		 3534
3535/* Uses mbox */
2dc1deb6 3536int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 3537{
3538 struct be_mcc_wrb *wrb;
3539 struct be_cmd_req_set_func_cap *req;
3540 int status;
3541
3542 if (mutex_lock_interruptible(&adapter->mbox_lock))
3543 return -1;
3544
3545 wrb = wrb_from_mbox(adapter);
3546 if (!wrb) {
3547 status = -EBUSY;
3548 goto err;
3549 }
3550
3551 req = embedded_payload(wrb);
3552
106df1e3 3553 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3554 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3555 sizeof(*req), wrb, NULL);
2e588f84
SP		 3556
3557 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3558 CAPABILITY_BE3_NATIVE_ERX_API);
3559 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3560
3561 status = be_mbox_notify_wait(adapter);
3562 if (!status) {
3563 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 3564
2e588f84
SP		 3565 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3566 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 3567 if (!adapter->be3_native)
3568 dev_warn(&adapter->pdev->dev,
3569 "adapter not in advanced mode\n");
2e588f84
SP		 3570 }
3571err:
3572 mutex_unlock(&adapter->mbox_lock);
3573 return status;
3574}
590c391d 3575
f25b119c
PR		 3576/* Get privilege(s) for a function */
3577int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3578 u32 domain)
3579{
3580 struct be_mcc_wrb *wrb;
3581 struct be_cmd_req_get_fn_privileges *req;
3582 int status;
3583
3584 spin_lock_bh(&adapter->mcc_lock);
3585
3586 wrb = wrb_from_mccq(adapter);
3587 if (!wrb) {
3588 status = -EBUSY;
3589 goto err;
3590 }
3591
3592 req = embedded_payload(wrb);
3593
3594 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3595 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3596 wrb, NULL);
3597
3598 req->hdr.domain = domain;
3599
3600 status = be_mcc_notify_wait(adapter);
3601 if (!status) {
3602 struct be_cmd_resp_get_fn_privileges *resp =
3603 embedded_payload(wrb);
03d28ffe 3604
f25b119c 3605 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 3606
3607 /* In UMC mode FW does not return right privileges.
3608 * Override with correct privilege equivalent to PF.
3609 */
3610 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3611 be_physfn(adapter))
3612 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 3613 }
3614
3615err:
3616 spin_unlock_bh(&adapter->mcc_lock);
3617 return status;
3618}
3619
04a06028
SP		 3620/* Set privilege(s) for a function */
3621int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3622 u32 domain)
3623{
3624 struct be_mcc_wrb *wrb;
3625 struct be_cmd_req_set_fn_privileges *req;
3626 int status;
3627
3628 spin_lock_bh(&adapter->mcc_lock);
3629
3630 wrb = wrb_from_mccq(adapter);
3631 if (!wrb) {
3632 status = -EBUSY;
3633 goto err;
3634 }
3635
3636 req = embedded_payload(wrb);
3637 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3638 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3639 wrb, NULL);
3640 req->hdr.domain = domain;
3641 if (lancer_chip(adapter))
3642 req->privileges_lancer = cpu_to_le32(privileges);
3643 else
3644 req->privileges = cpu_to_le32(privileges);
3645
3646 status = be_mcc_notify_wait(adapter);
3647err:
3648 spin_unlock_bh(&adapter->mcc_lock);
3649 return status;
3650}
3651
5a712c13
SP		 3652/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3653 * pmac_id_valid: false => pmac_id or MAC address is requested.
3654 * If pmac_id is returned, pmac_id_valid is returned as true
3655 */
1578e777 3656int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 3657 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3658 u8 domain)
590c391d
PR		 3659{
3660 struct be_mcc_wrb *wrb;
3661 struct be_cmd_req_get_mac_list *req;
3662 int status;
3663 int mac_count;
e5e1ee89
PR		 3664 struct be_dma_mem get_mac_list_cmd;
3665 int i;
3666
3667 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3668 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
e51000db
SB		 3669 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3670 get_mac_list_cmd.size,
3671 &get_mac_list_cmd.dma,
3672 GFP_ATOMIC);
e5e1ee89
PR		 3673
3674 if (!get_mac_list_cmd.va) {
3675 dev_err(&adapter->pdev->dev,
a2cc4e0b 3676 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 3677 return -ENOMEM;
3678 }
590c391d
PR		 3679
3680 spin_lock_bh(&adapter->mcc_lock);
3681
3682 wrb = wrb_from_mccq(adapter);
3683 if (!wrb) {
3684 status = -EBUSY;
e5e1ee89 3685 goto out;
590c391d 3686 }
e5e1ee89
PR		 3687
3688 req = get_mac_list_cmd.va;
590c391d
PR		 3689
3690 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 3691 OPCODE_COMMON_GET_MAC_LIST,
3692 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 3693 req->hdr.domain = domain;
e5e1ee89 3694 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 3695 if (*pmac_id_valid) {
3696 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 3697 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 3698 req->perm_override = 0;
3699 } else {
3700 req->perm_override = 1;
3701 }
590c391d
PR		 3702
3703 status = be_mcc_notify_wait(adapter);
3704 if (!status) {
3705 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 3706 get_mac_list_cmd.va;
5a712c13
SP		 3707
3708 if (*pmac_id_valid) {
3709 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3710 ETH_ALEN);
3711 goto out;
3712 }
3713
e5e1ee89
PR		 3714 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3715 /* Mac list returned could contain one or more active mac_ids
dbedd44e 3716 * or one or more true or pseudo permanent mac addresses.
1578e777
PR		 3717 * If an active mac_id is present, return first active mac_id
3718 * found.
e5e1ee89 3719 */
590c391d 3720 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3721 struct get_list_macaddr *mac_entry;
3722 u16 mac_addr_size;
3723 u32 mac_id;
3724
3725 mac_entry = &resp->macaddr_list[i];
3726 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3727 /* mac_id is a 32 bit value and mac_addr size
3728 * is 6 bytes
3729 */
3730 if (mac_addr_size == sizeof(u32)) {
5a712c13 3731 *pmac_id_valid = true;
e5e1ee89
PR		 3732 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3733 *pmac_id = le32_to_cpu(mac_id);
3734 goto out;
590c391d 3735 }
590c391d 3736 }
1578e777 3737 /* If no active mac_id found, return first mac addr */
5a712c13 3738 *pmac_id_valid = false;
e5e1ee89 3739 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3740 ETH_ALEN);
590c391d
PR		 3741 }
3742
e5e1ee89 3743out:
590c391d 3744 spin_unlock_bh(&adapter->mcc_lock);
e51000db
SB		 3745 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3746 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3747 return status;
3748}
3749
a2cc4e0b
SP		 3750int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3751 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3752{
b188f090
SR		 3753 if (!active)
3754 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3755 if_handle, domain);
3175d8c2 3756 if (BEx_chip(adapter))
5a712c13 3757 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3758 if_handle, curr_pmac_id);
3175d8c2
SP		 3759 else
3760 /* Fetch the MAC address using pmac_id */
3761 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3762 &curr_pmac_id,
3763 if_handle, domain);
5a712c13
SP		 3764}
3765
95046b92
SP		 3766int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3767{
3768 int status;
3769 bool pmac_valid = false;
3770
c7bf7169 3771 eth_zero_addr(mac);
95046b92 3772
3175d8c2
SP		 3773 if (BEx_chip(adapter)) {
3774 if (be_physfn(adapter))
3775 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3776 0);
3777 else
3778 status = be_cmd_mac_addr_query(adapter, mac, false,
3779 adapter->if_handle, 0);
3780 } else {
95046b92 3781 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3782 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3783 }
3784
95046b92
SP		 3785 return status;
3786}
3787
590c391d
PR		 3788/* Uses synchronous MCCQ */
3789int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3790 u8 mac_count, u32 domain)
3791{
3792 struct be_mcc_wrb *wrb;
3793 struct be_cmd_req_set_mac_list *req;
3794 int status;
3795 struct be_dma_mem cmd;
3796
3797 memset(&cmd, 0, sizeof(struct be_dma_mem));
3798 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
e51000db
SB		 3799 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3800 GFP_KERNEL);
d0320f75 3801 if (!cmd.va)
590c391d 3802 return -ENOMEM;
590c391d
PR		 3803
3804 spin_lock_bh(&adapter->mcc_lock);
3805
3806 wrb = wrb_from_mccq(adapter);
3807 if (!wrb) {
3808 status = -EBUSY;
3809 goto err;
3810 }
3811
3812 req = cmd.va;
3813 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3814 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3815 wrb, &cmd);
590c391d
PR		 3816
3817 req->hdr.domain = domain;
3818 req->mac_count = mac_count;
3819 if (mac_count)
3820 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3821
3822 status = be_mcc_notify_wait(adapter);
3823
3824err:
a2cc4e0b 3825 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
590c391d
PR		 3826 spin_unlock_bh(&adapter->mcc_lock);
3827 return status;
3828}
4762f6ce 3829
3175d8c2
SP		 3830/* Wrapper to delete any active MACs and provision the new mac.
3831 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3832 * current list are active.
3833 */
3834int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3835{
3836 bool active_mac = false;
3837 u8 old_mac[ETH_ALEN];
3838 u32 pmac_id;
3839 int status;
3840
3841 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3842 &pmac_id, if_id, dom);
3843
3175d8c2
SP		 3844 if (!status && active_mac)
3845 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3846
3847 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3848}
3849
f1f3ee1b 3850int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
e7bcbd7b 3851 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
f1f3ee1b
AK		 3852{
3853 struct be_mcc_wrb *wrb;
3854 struct be_cmd_req_set_hsw_config *req;
3855 void *ctxt;
3856 int status;
3857
884476be
SK		 3858 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3859 CMD_SUBSYSTEM_COMMON))
3860 return -EPERM;
3861
f1f3ee1b
AK		 3862 spin_lock_bh(&adapter->mcc_lock);
3863
3864 wrb = wrb_from_mccq(adapter);
3865 if (!wrb) {
3866 status = -EBUSY;
3867 goto err;
3868 }
3869
3870 req = embedded_payload(wrb);
3871 ctxt = &req->context;
3872
3873 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3874 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3875 NULL);
f1f3ee1b
AK		 3876
3877 req->hdr.domain = domain;
3878 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3879 if (pvid) {
3880 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3881 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3882 }
884476be 3883 if (hsw_mode) {
a77dcb8c
AK		 3884 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3885 ctxt, adapter->hba_port_num);
3886 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3887 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3888 ctxt, hsw_mode);
3889 }
f1f3ee1b 3890
e7bcbd7b
KA		 3891 /* Enable/disable both mac and vlan spoof checking */
3892 if (!BEx_chip(adapter) && spoofchk) {
3893 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3894 ctxt, spoofchk);
3895 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3896 ctxt, spoofchk);
3897 }
3898
f1f3ee1b
AK		 3899 be_dws_cpu_to_le(req->context, sizeof(req->context));
3900 status = be_mcc_notify_wait(adapter);
3901
3902err:
3903 spin_unlock_bh(&adapter->mcc_lock);
3904 return status;
3905}
3906
3907/* Get Hyper switch config */
3908int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
e7bcbd7b 3909 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
f1f3ee1b
AK		 3910{
3911 struct be_mcc_wrb *wrb;
3912 struct be_cmd_req_get_hsw_config *req;
3913 void *ctxt;
3914 int status;
3915 u16 vid;
3916
3917 spin_lock_bh(&adapter->mcc_lock);
3918
3919 wrb = wrb_from_mccq(adapter);
3920 if (!wrb) {
3921 status = -EBUSY;
3922 goto err;
3923 }
3924
3925 req = embedded_payload(wrb);
3926 ctxt = &req->context;
3927
3928 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3929 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3930 NULL);
f1f3ee1b
AK		 3931
3932 req->hdr.domain = domain;
a77dcb8c
AK		 3933 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3934 ctxt, intf_id);
f1f3ee1b 3935 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3936
2c07c1d7 3937 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3938 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3939 ctxt, adapter->hba_port_num);
3940 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3941 }
f1f3ee1b
AK		 3942 be_dws_cpu_to_le(req->context, sizeof(req->context));
3943
3944 status = be_mcc_notify_wait(adapter);
3945 if (!status) {
3946 struct be_cmd_resp_get_hsw_config *resp =
3947 embedded_payload(wrb);
03d28ffe 3948
a2cc4e0b 3949 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3950 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3951 pvid, &resp->context);
a77dcb8c
AK		 3952 if (pvid)
3953 *pvid = le16_to_cpu(vid);
3954 if (mode)
3955 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3956 port_fwd_type, &resp->context);
e7bcbd7b
KA		 3957 if (spoofchk)
3958 *spoofchk =
3959 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3960 spoofchk, &resp->context);
f1f3ee1b
AK		 3961 }
3962
3963err:
3964 spin_unlock_bh(&adapter->mcc_lock);
3965 return status;
3966}
3967
f7062ee5
SP		 3968static bool be_is_wol_excluded(struct be_adapter *adapter)
3969{
3970 struct pci_dev *pdev = adapter->pdev;
3971
18c57c74 3972 if (be_virtfn(adapter))
f7062ee5
SP		 3973 return true;
3974
3975 switch (pdev->subsystem_device) {
3976 case OC_SUBSYS_DEVICE_ID1:
3977 case OC_SUBSYS_DEVICE_ID2:
3978 case OC_SUBSYS_DEVICE_ID3:
3979 case OC_SUBSYS_DEVICE_ID4:
3980 return true;
3981 default:
3982 return false;
3983 }
3984}
3985
4762f6ce
AK		 3986int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3987{
3988 struct be_mcc_wrb *wrb;
3989 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3990 int status = 0;
4762f6ce
AK		 3991 struct be_dma_mem cmd;
3992
f25b119c
PR		 3993 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3994 CMD_SUBSYSTEM_ETH))
3995 return -EPERM;
3996
76a9e08e
SR		 3997 if (be_is_wol_excluded(adapter))
3998 return status;
3999
d98ef50f
SR		 4000 if (mutex_lock_interruptible(&adapter->mbox_lock))
4001 return -1;
4002
4762f6ce
AK		 4003 memset(&cmd, 0, sizeof(struct be_dma_mem));
4004 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
e51000db
SB		 4005 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4006 GFP_ATOMIC);
4762f6ce 4007 if (!cmd.va) {
a2cc4e0b 4008 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 4009 status = -ENOMEM;
4010 goto err;
4762f6ce
AK		 4011 }
4012
4762f6ce
AK		 4013 wrb = wrb_from_mbox(adapter);
4014 if (!wrb) {
4015 status = -EBUSY;
4016 goto err;
4017 }
4018
4019 req = cmd.va;
4020
4021 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4022 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 4023 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 4024
4025 req->hdr.version = 1;
4026 req->query_options = BE_GET_WOL_CAP;
4027
4028 status = be_mbox_notify_wait(adapter);
4029 if (!status) {
4030 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 4031
504fbf1e 4032 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 4033
4762f6ce 4034 adapter->wol_cap = resp->wol_settings;
45f13df7
SB		 4035
4036 /* Non-zero macaddr indicates WOL is enabled */
4037 if (adapter->wol_cap & BE_WOL_CAP &&
4038 !is_zero_ether_addr(resp->magic_mac))
76a9e08e 4039 adapter->wol_en = true;
4762f6ce
AK		 4040 }
4041err:
4042 mutex_unlock(&adapter->mbox_lock);
d98ef50f 4043 if (cmd.va)
e51000db
SB		 4044 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4045 cmd.dma);
4762f6ce 4046 return status;
941a77d5
SK		 4047
4048}
baaa08d1
VV		 4049
4050int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4051{
4052 struct be_dma_mem extfat_cmd;
4053 struct be_fat_conf_params *cfgs;
4054 int status;
4055 int i, j;
4056
4057 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4058 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
e51000db
SB		 4059 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4060 extfat_cmd.size, &extfat_cmd.dma,
4061 GFP_ATOMIC);
baaa08d1
VV		 4062 if (!extfat_cmd.va)
4063 return -ENOMEM;
4064
4065 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4066 if (status)
4067 goto err;
4068
4069 cfgs = (struct be_fat_conf_params *)
4070 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4071 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4072 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 4073
baaa08d1
VV		 4074 for (j = 0; j < num_modes; j++) {
4075 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4076 cfgs->module[i].trace_lvl[j].dbg_lvl =
4077 cpu_to_le32(level);
4078 }
4079 }
4080
4081 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4082err:
e51000db
SB		 4083 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4084 extfat_cmd.dma);
baaa08d1
VV		 4085 return status;
4086}
4087
4088int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4089{
4090 struct be_dma_mem extfat_cmd;
4091 struct be_fat_conf_params *cfgs;
4092 int status, j;
4093 int level = 0;
4094
4095 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4096 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
e51000db
SB		 4097 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4098 extfat_cmd.size, &extfat_cmd.dma,
4099 GFP_ATOMIC);
baaa08d1
VV		 4100
4101 if (!extfat_cmd.va) {
4102 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4103 __func__);
4104 goto err;
4105 }
4106
4107 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4108 if (!status) {
4109 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4110 sizeof(struct be_cmd_resp_hdr));
03d28ffe 4111
baaa08d1
VV		 4112 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4113 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4114 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4115 }
4116 }
e51000db
SB		 4117 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4118 extfat_cmd.dma);
baaa08d1
VV		 4119err:
4120 return level;
4121}
4122
941a77d5
SK		 4123int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4124 struct be_dma_mem *cmd)
4125{
4126 struct be_mcc_wrb *wrb;
4127 struct be_cmd_req_get_ext_fat_caps *req;
4128 int status;
4129
4130 if (mutex_lock_interruptible(&adapter->mbox_lock))
4131 return -1;
4132
4133 wrb = wrb_from_mbox(adapter);
4134 if (!wrb) {
4135 status = -EBUSY;
4136 goto err;
4137 }
4138
4139 req = cmd->va;
4140 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4141 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
4142 cmd->size, wrb, cmd);
4143 req->parameter_type = cpu_to_le32(1);
4144
4145 status = be_mbox_notify_wait(adapter);
4146err:
4147 mutex_unlock(&adapter->mbox_lock);
4148 return status;
4149}
4150
4151int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4152 struct be_dma_mem *cmd,
4153 struct be_fat_conf_params *configs)
4154{
4155 struct be_mcc_wrb *wrb;
4156 struct be_cmd_req_set_ext_fat_caps *req;
4157 int status;
4158
4159 spin_lock_bh(&adapter->mcc_lock);
4160
4161 wrb = wrb_from_mccq(adapter);
4162 if (!wrb) {
4163 status = -EBUSY;
4164 goto err;
4165 }
4166
4167 req = cmd->va;
4168 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4169 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4170 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
4171 cmd->size, wrb, cmd);
4172
4173 status = be_mcc_notify_wait(adapter);
4174err:
4175 spin_unlock_bh(&adapter->mcc_lock);
4176 return status;
4762f6ce 4177}
6a4ab669 4178
21252377 4179int be_cmd_query_port_name(struct be_adapter *adapter)
b4e32a71 4180{
b4e32a71 4181 struct be_cmd_req_get_port_name *req;
21252377 4182 struct be_mcc_wrb *wrb;
b4e32a71
PR		 4183 int status;
4184
21252377
VV		 4185 if (mutex_lock_interruptible(&adapter->mbox_lock))
4186 return -1;
b4e32a71 4187
21252377 4188 wrb = wrb_from_mbox(adapter);
b4e32a71
PR		 4189 req = embedded_payload(wrb);
4190
4191 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4192 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4193 NULL);
21252377
VV		 4194 if (!BEx_chip(adapter))
4195 req->hdr.version = 1;
b4e32a71 4196
21252377 4197 status = be_mbox_notify_wait(adapter);
b4e32a71
PR		 4198 if (!status) {
4199 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 4200
21252377 4201 adapter->port_name = resp->port_name[adapter->hba_port_num];
b4e32a71 4202 } else {
21252377 4203 adapter->port_name = adapter->hba_port_num + '0';
b4e32a71 4204 }
21252377
VV		 4205
4206 mutex_unlock(&adapter->mbox_lock);
b4e32a71
PR		 4207 return status;
4208}
4209
980df249
SR		 4210/* When more than 1 NIC descriptor is present in the descriptor list,
4211 * the caller must specify the pf_num to obtain the NIC descriptor
4212 * corresponding to its pci function.
4213 * get_vft must be true when the caller wants the VF-template desc of the
4214 * PF-pool.
4215 * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4216 * that only it's NIC descriptor is present in the descriptor list.
4217 */
10cccf60 4218static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
980df249 4219 bool get_vft, u8 pf_num)
abb93951 4220{
150d58c7 4221 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 4222 struct be_nic_res_desc *nic;
abb93951
PR		 4223 int i;
4224
4225 for (i = 0; i < desc_count; i++) {
150d58c7 4226 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 4227 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4228 nic = (struct be_nic_res_desc *)hdr;
980df249
SR		 4229
4230 if ((pf_num == PF_NUM_IGNORE ||
4231 nic->pf_num == pf_num) &&
4232 (!get_vft || nic->flags & BIT(VFT_SHIFT)))
10cccf60
VV		 4233 return nic;
4234 }
150d58c7
VV		 4235 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4236 hdr = (void *)hdr + hdr->desc_len;
abb93951 4237 }
150d58c7
VV		 4238 return NULL;
4239}
4240
980df249
SR		 4241static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4242 u8 pf_num)
10cccf60 4243{
980df249 4244 return be_get_nic_desc(buf, desc_count, true, pf_num);
10cccf60
VV		 4245}
4246
980df249
SR		 4247static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4248 u8 pf_num)
10cccf60 4249{
980df249 4250 return be_get_nic_desc(buf, desc_count, false, pf_num);
10cccf60
VV		 4251}
4252
980df249
SR		 4253static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4254 u8 pf_num)
150d58c7
VV		 4255{
4256 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4257 struct be_pcie_res_desc *pcie;
4258 int i;
4259
4260 for (i = 0; i < desc_count; i++) {
980df249
SR		 4261 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4262 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4263 pcie = (struct be_pcie_res_desc *)hdr;
4264 if (pcie->pf_num == pf_num)
150d58c7
VV		 4265 return pcie;
4266 }
abb93951 4267
150d58c7
VV		 4268 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4269 hdr = (void *)hdr + hdr->desc_len;
4270 }
950e2958 4271 return NULL;
abb93951
PR		 4272}
4273
f93f160b
VV		 4274static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4275{
4276 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4277 int i;
4278
4279 for (i = 0; i < desc_count; i++) {
4280 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4281 return (struct be_port_res_desc *)hdr;
4282
4283 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4284 hdr = (void *)hdr + hdr->desc_len;
4285 }
4286 return NULL;
4287}
4288
92bf14ab
SP		 4289static void be_copy_nic_desc(struct be_resources *res,
4290 struct be_nic_res_desc *desc)
4291{
4292 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4293 res->max_vlans = le16_to_cpu(desc->vlan_count);
4294 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4295 res->max_tx_qs = le16_to_cpu(desc->txq_count);
4296 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4297 res->max_rx_qs = le16_to_cpu(desc->rq_count);
4298 res->max_evt_qs = le16_to_cpu(desc->eq_count);
f2858738
VV		 4299 res->max_cq_count = le16_to_cpu(desc->cq_count);
4300 res->max_iface_count = le16_to_cpu(desc->iface_count);
4301 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
92bf14ab
SP		 4302 /* Clear flags that driver is not interested in */
4303 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4304 BE_IF_CAP_FLAGS_WANT;
92bf14ab
SP		 4305}
4306
abb93951 4307/* Uses Mbox */
92bf14ab 4308int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 4309{
4310 struct be_mcc_wrb *wrb;
4311 struct be_cmd_req_get_func_config *req;
4312 int status;
4313 struct be_dma_mem cmd;
4314
d98ef50f
SR		 4315 if (mutex_lock_interruptible(&adapter->mbox_lock))
4316 return -1;
4317
abb93951
PR		 4318 memset(&cmd, 0, sizeof(struct be_dma_mem));
4319 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
e51000db
SB		 4320 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4321 GFP_ATOMIC);
abb93951
PR		 4322 if (!cmd.va) {
4323 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 4324 status = -ENOMEM;
4325 goto err;
abb93951 4326 }
abb93951
PR		 4327
4328 wrb = wrb_from_mbox(adapter);
4329 if (!wrb) {
4330 status = -EBUSY;
4331 goto err;
4332 }
4333
4334 req = cmd.va;
4335
4336 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4337 OPCODE_COMMON_GET_FUNC_CONFIG,
4338 cmd.size, wrb, &cmd);
4339
28710c55
KA		 4340 if (skyhawk_chip(adapter))
4341 req->hdr.version = 1;
4342
abb93951
PR		 4343 status = be_mbox_notify_wait(adapter);
4344 if (!status) {
4345 struct be_cmd_resp_get_func_config *resp = cmd.va;
4346 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 4347 struct be_nic_res_desc *desc;
abb93951 4348
980df249
SR		 4349 /* GET_FUNC_CONFIG returns resource descriptors of the
4350 * current function only. So, pf_num should be set to
4351 * PF_NUM_IGNORE.
4352 */
4353 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4354 PF_NUM_IGNORE);
abb93951
PR		 4355 if (!desc) {
4356 status = -EINVAL;
4357 goto err;
4358 }
980df249
SR		 4359
4360 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4361 adapter->pf_num = desc->pf_num;
4362 adapter->vf_num = desc->vf_num;
4363
4364 if (res)
4365 be_copy_nic_desc(res, desc);
abb93951
PR		 4366 }
4367err:
4368 mutex_unlock(&adapter->mbox_lock);
d98ef50f 4369 if (cmd.va)
e51000db
SB		 4370 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4371 cmd.dma);
abb93951
PR		 4372 return status;
4373}
4374
de2b1e03
SK		 4375/* This routine returns a list of all the NIC PF_nums in the adapter */
4376u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
4377{
4378 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4379 struct be_pcie_res_desc *pcie = NULL;
4380 int i;
4381 u16 nic_pf_count = 0;
4382
4383 for (i = 0; i < desc_count; i++) {
4384 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4385 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4386 pcie = (struct be_pcie_res_desc *)hdr;
4387 if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4388 pcie->pf_type == MISSION_RDMA)) {
4389 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4390 }
4391 }
4392
4393 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4394 hdr = (void *)hdr + hdr->desc_len;
4395 }
4396 return nic_pf_count;
4397}
4398
980df249 4399/* Will use MBOX only if MCCQ has not been created */
92bf14ab 4400int be_cmd_get_profile_config(struct be_adapter *adapter,
de2b1e03
SK		 4401 struct be_resources *res,
4402 struct be_port_resources *port_res,
4403 u8 profile_type, u8 query, u8 domain)
a05f99db 4404{
150d58c7 4405 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 4406 struct be_cmd_req_get_profile_config *req;
10cccf60 4407 struct be_nic_res_desc *vf_res;
150d58c7 4408 struct be_pcie_res_desc *pcie;
f93f160b 4409 struct be_port_res_desc *port;
150d58c7 4410 struct be_nic_res_desc *nic;
ba48c0c9 4411 struct be_mcc_wrb wrb = {0};
a05f99db 4412 struct be_dma_mem cmd;
f2858738 4413 u16 desc_count;
a05f99db
VV		 4414 int status;
4415
4416 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7 4417 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
e51000db
SB		 4418 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4419 GFP_ATOMIC);
150d58c7 4420 if (!cmd.va)
a05f99db 4421 return -ENOMEM;
a05f99db 4422
ba48c0c9
VV		 4423 req = cmd.va;
4424 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4425 OPCODE_COMMON_GET_PROFILE_CONFIG,
4426 cmd.size, &wrb, &cmd);
4427
ba48c0c9
VV		 4428 if (!lancer_chip(adapter))
4429 req->hdr.version = 1;
de2b1e03 4430 req->type = profile_type;
72ef3a88 4431 req->hdr.domain = domain;
ba48c0c9 4432
f2858738
VV		 4433 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4434 * descriptors with all bits set to "1" for the fields which can be
4435 * modified using SET_PROFILE_CONFIG cmd.
4436 */
4437 if (query == RESOURCE_MODIFIABLE)
4438 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4439
ba48c0c9 4440 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 4441 if (status)
4442 goto err;
abb93951 4443
150d58c7 4444 resp = cmd.va;
f2858738 4445 desc_count = le16_to_cpu(resp->desc_count);
abb93951 4446
de2b1e03
SK		 4447 if (port_res) {
4448 u16 nic_pf_cnt = 0, i;
4449 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4450
4451 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4452 desc_count,
4453 nic_pf_num_list);
4454
4455 for (i = 0; i < nic_pf_cnt; i++) {
4456 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4457 nic_pf_num_list[i]);
4458 if (nic->link_param == adapter->port_num) {
4459 port_res->nic_pfs++;
4460 pcie = be_get_pcie_desc(resp->func_param,
4461 desc_count,
4462 nic_pf_num_list[i]);
4463 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4464 }
4465 }
4466 return status;
4467 }
4468
980df249
SR		 4469 pcie = be_get_pcie_desc(resp->func_param, desc_count,
4470 adapter->pf_num);
150d58c7 4471 if (pcie)
92bf14ab 4472 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 4473
f93f160b
VV		 4474 port = be_get_port_desc(resp->func_param, desc_count);
4475 if (port)
4476 adapter->mc_type = port->mc_type;
4477
980df249
SR		 4478 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4479 adapter->pf_num);
92bf14ab
SP		 4480 if (nic)
4481 be_copy_nic_desc(res, nic);
4482
980df249
SR		 4483 vf_res = be_get_vft_desc(resp->func_param, desc_count,
4484 adapter->pf_num);
10cccf60
VV		 4485 if (vf_res)
4486 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 4487err:
a05f99db 4488 if (cmd.va)
e51000db
SB		 4489 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4490 cmd.dma);
abb93951
PR		 4491 return status;
4492}
4493
bec84e6b
VV		 4494/* Will use MBOX only if MCCQ has not been created */
4495static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4496 int size, int count, u8 version, u8 domain)
d5c18473 4497{
d5c18473 4498 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 4499 struct be_mcc_wrb wrb = {0};
4500 struct be_dma_mem cmd;
d5c18473
PR		 4501 int status;
4502
bec84e6b
VV		 4503 memset(&cmd, 0, sizeof(struct be_dma_mem));
4504 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
e51000db
SB		 4505 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4506 GFP_ATOMIC);
bec84e6b
VV		 4507 if (!cmd.va)
4508 return -ENOMEM;
d5c18473 4509
bec84e6b 4510 req = cmd.va;
d5c18473 4511 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 4512 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4513 &wrb, &cmd);
a401801c 4514 req->hdr.version = version;
d5c18473 4515 req->hdr.domain = domain;
bec84e6b 4516 req->desc_count = cpu_to_le32(count);
a401801c
SP		 4517 memcpy(req->desc, desc, size);
4518
bec84e6b
VV		 4519 status = be_cmd_notify_wait(adapter, &wrb);
4520
4521 if (cmd.va)
e51000db
SB		 4522 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4523 cmd.dma);
d5c18473
PR		 4524 return status;
4525}
4526
a401801c 4527/* Mark all fields invalid */
b9263cbf 4528void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 4529{
4530 memset(nic, 0, sizeof(*nic));
4531 nic->unicast_mac_count = 0xFFFF;
4532 nic->mcc_count = 0xFFFF;
4533 nic->vlan_count = 0xFFFF;
4534 nic->mcast_mac_count = 0xFFFF;
4535 nic->txq_count = 0xFFFF;
4536 nic->rq_count = 0xFFFF;
4537 nic->rssq_count = 0xFFFF;
4538 nic->lro_count = 0xFFFF;
4539 nic->cq_count = 0xFFFF;
4540 nic->toe_conn_count = 0xFFFF;
4541 nic->eq_count = 0xFFFF;
0f77ba73 4542 nic->iface_count = 0xFFFF;
a401801c 4543 nic->link_param = 0xFF;
0f77ba73 4544 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 4545 nic->acpi_params = 0xFF;
4546 nic->wol_param = 0x0F;
0f77ba73
RN		 4547 nic->tunnel_iface_count = 0xFFFF;
4548 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 4549 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 4550 nic->bw_max = 0xFFFFFFFF;
4551}
4552
bec84e6b
VV		 4553/* Mark all fields invalid */
4554static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4555{
4556 memset(pcie, 0, sizeof(*pcie));
4557 pcie->sriov_state = 0xFF;
4558 pcie->pf_state = 0xFF;
4559 pcie->pf_type = 0xFF;
4560 pcie->num_vfs = 0xFFFF;
4561}
4562
0f77ba73
RN		 4563int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4564 u8 domain)
a401801c 4565{
0f77ba73
RN		 4566 struct be_nic_res_desc nic_desc;
4567 u32 bw_percent;
4568 u16 version = 0;
4569
4570 if (BE3_chip(adapter))
4571 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 4572
0f77ba73 4573 be_reset_nic_desc(&nic_desc);
980df249 4574 nic_desc.pf_num = adapter->pf_num;
0f77ba73 4575 nic_desc.vf_num = domain;
58bdeaa6 4576 nic_desc.bw_min = 0;
0f77ba73 4577 if (lancer_chip(adapter)) {
a401801c
SP		 4578 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4579 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4580 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4581 (1 << NOSV_SHIFT);
0f77ba73 4582 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 4583 } else {
0f77ba73
RN		 4584 version = 1;
4585 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4586 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4587 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4588 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4589 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 4590 }
0f77ba73
RN		 4591
4592 return be_cmd_set_profile_config(adapter, &nic_desc,
4593 nic_desc.hdr.desc_len,
bec84e6b
VV		 4594 1, version, domain);
4595}
4596
4597int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738 4598 struct be_resources pool_res, u16 num_vfs,
b9263cbf 4599 struct be_resources *vft_res)
bec84e6b
VV		 4600{
4601 struct {
4602 struct be_pcie_res_desc pcie;
4603 struct be_nic_res_desc nic_vft;
4604 } __packed desc;
bec84e6b 4605
bec84e6b
VV		 4606 /* PF PCIE descriptor */
4607 be_reset_pcie_desc(&desc.pcie);
4608 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4609 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 4610 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 4611 desc.pcie.pf_num = adapter->pdev->devfn;
4612 desc.pcie.sriov_state = num_vfs ? 1 : 0;
4613 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4614
4615 /* VF NIC Template descriptor */
4616 be_reset_nic_desc(&desc.nic_vft);
4617 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4618 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
b9263cbf
SR		 4619 desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4620 BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 4621 desc.nic_vft.pf_num = adapter->pdev->devfn;
4622 desc.nic_vft.vf_num = 0;
b9263cbf
SR		 4623 desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4624 desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4625 desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4626 desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4627 desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4628
4629 if (vft_res->max_uc_mac)
4630 desc.nic_vft.unicast_mac_count =
4631 cpu_to_le16(vft_res->max_uc_mac);
4632 if (vft_res->max_vlans)
4633 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4634 if (vft_res->max_iface_count)
4635 desc.nic_vft.iface_count =
4636 cpu_to_le16(vft_res->max_iface_count);
4637 if (vft_res->max_mcc_count)
4638 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
bec84e6b
VV		 4639
4640 return be_cmd_set_profile_config(adapter, &desc,
4641 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 4642}
4643
4644int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4645{
4646 struct be_mcc_wrb *wrb;
4647 struct be_cmd_req_manage_iface_filters *req;
4648 int status;
4649
4650 if (iface == 0xFFFFFFFF)
4651 return -1;
4652
4653 spin_lock_bh(&adapter->mcc_lock);
4654
4655 wrb = wrb_from_mccq(adapter);
4656 if (!wrb) {
4657 status = -EBUSY;
4658 goto err;
4659 }
4660 req = embedded_payload(wrb);
4661
4662 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4663 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4664 wrb, NULL);
4665 req->op = op;
4666 req->target_iface_id = cpu_to_le32(iface);
4667
4668 status = be_mcc_notify_wait(adapter);
4669err:
4670 spin_unlock_bh(&adapter->mcc_lock);
4671 return status;
4672}
4673
4674int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4675{
4676 struct be_port_res_desc port_desc;
4677
4678 memset(&port_desc, 0, sizeof(port_desc));
4679 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4680 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4681 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4682 port_desc.link_num = adapter->hba_port_num;
4683 if (port) {
4684 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4685 (1 << RCVID_SHIFT);
4686 port_desc.nv_port = swab16(port);
4687 } else {
4688 port_desc.nv_flags = NV_TYPE_DISABLED;
4689 port_desc.nv_port = 0;
4690 }
4691
4692 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 4693 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 4694}
4695
4c876616
SP		 4696int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4697 int vf_num)
4698{
4699 struct be_mcc_wrb *wrb;
4700 struct be_cmd_req_get_iface_list *req;
4701 struct be_cmd_resp_get_iface_list *resp;
4702 int status;
4703
4704 spin_lock_bh(&adapter->mcc_lock);
4705
4706 wrb = wrb_from_mccq(adapter);
4707 if (!wrb) {
4708 status = -EBUSY;
4709 goto err;
4710 }
4711 req = embedded_payload(wrb);
4712
4713 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4714 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4715 wrb, NULL);
4716 req->hdr.domain = vf_num + 1;
4717
4718 status = be_mcc_notify_wait(adapter);
4719 if (!status) {
4720 resp = (struct be_cmd_resp_get_iface_list *)req;
4721 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4722 }
4723
4724err:
4725 spin_unlock_bh(&adapter->mcc_lock);
4726 return status;
4727}
4728
5c510811
SK		 4729static int lancer_wait_idle(struct be_adapter *adapter)
4730{
4731#define SLIPORT_IDLE_TIMEOUT 30
4732 u32 reg_val;
4733 int status = 0, i;
4734
4735 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4736 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4737 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4738 break;
4739
4740 ssleep(1);
4741 }
4742
4743 if (i == SLIPORT_IDLE_TIMEOUT)
4744 status = -1;
4745
4746 return status;
4747}
4748
4749int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4750{
4751 int status = 0;
4752
4753 status = lancer_wait_idle(adapter);
4754 if (status)
4755 return status;
4756
4757 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4758
4759 return status;
4760}
4761
4762/* Routine to check whether dump image is present or not */
4763bool dump_present(struct be_adapter *adapter)
4764{
4765 u32 sliport_status = 0;
4766
4767 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4768 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4769}
4770
4771int lancer_initiate_dump(struct be_adapter *adapter)
4772{
f0613380 4773 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 4774 int status;
4775
f0613380
KA		 4776 if (dump_present(adapter)) {
4777 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4778 return -EEXIST;
4779 }
4780
5c510811
SK		 4781 /* give firmware reset and diagnostic dump */
4782 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4783 PHYSDEV_CONTROL_DD_MASK);
4784 if (status < 0) {
f0613380 4785 dev_err(dev, "FW reset failed\n");
5c510811
SK		 4786 return status;
4787 }
4788
4789 status = lancer_wait_idle(adapter);
4790 if (status)
4791 return status;
4792
4793 if (!dump_present(adapter)) {
f0613380
KA		 4794 dev_err(dev, "FW dump not generated\n");
4795 return -EIO;
5c510811
SK		 4796 }
4797
4798 return 0;
4799}
4800
f0613380
KA		 4801int lancer_delete_dump(struct be_adapter *adapter)
4802{
4803 int status;
4804
4805 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4806 return be_cmd_status(status);
4807}
4808
dcf7ebba
PR		 4809/* Uses sync mcc */
4810int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4811{
4812 struct be_mcc_wrb *wrb;
4813 struct be_cmd_enable_disable_vf *req;
4814 int status;
4815
0599863d 4816 if (BEx_chip(adapter))
dcf7ebba
PR		 4817 return 0;
4818
4819 spin_lock_bh(&adapter->mcc_lock);
4820
4821 wrb = wrb_from_mccq(adapter);
4822 if (!wrb) {
4823 status = -EBUSY;
4824 goto err;
4825 }
4826
4827 req = embedded_payload(wrb);
4828
4829 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4830 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4831 wrb, NULL);
4832
4833 req->hdr.domain = domain;
4834 req->enable = 1;
4835 status = be_mcc_notify_wait(adapter);
4836err:
4837 spin_unlock_bh(&adapter->mcc_lock);
4838 return status;
4839}
4840
68c45a2d
SK		 4841int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4842{
4843 struct be_mcc_wrb *wrb;
4844 struct be_cmd_req_intr_set *req;
4845 int status;
4846
4847 if (mutex_lock_interruptible(&adapter->mbox_lock))
4848 return -1;
4849
4850 wrb = wrb_from_mbox(adapter);
4851
4852 req = embedded_payload(wrb);
4853
4854 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4855 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4856 wrb, NULL);
4857
4858 req->intr_enabled = intr_enable;
4859
4860 status = be_mbox_notify_wait(adapter);
4861
4862 mutex_unlock(&adapter->mbox_lock);
4863 return status;
4864}
4865
542963b7
VV		 4866/* Uses MBOX */
4867int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4868{
4869 struct be_cmd_req_get_active_profile *req;
4870 struct be_mcc_wrb *wrb;
4871 int status;
4872
4873 if (mutex_lock_interruptible(&adapter->mbox_lock))
4874 return -1;
4875
4876 wrb = wrb_from_mbox(adapter);
4877 if (!wrb) {
4878 status = -EBUSY;
4879 goto err;
4880 }
4881
4882 req = embedded_payload(wrb);
4883
4884 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4885 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4886 wrb, NULL);
4887
4888 status = be_mbox_notify_wait(adapter);
4889 if (!status) {
4890 struct be_cmd_resp_get_active_profile *resp =
4891 embedded_payload(wrb);
03d28ffe 4892
542963b7
VV		 4893 *profile_id = le16_to_cpu(resp->active_profile_id);
4894 }
4895
4896err:
4897 mutex_unlock(&adapter->mbox_lock);
4898 return status;
4899}
4900
d9d426af
SR		 4901int __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4902 int link_state, int version, u8 domain)
bdce2ad7
SR		 4903{
4904 struct be_mcc_wrb *wrb;
4905 struct be_cmd_req_set_ll_link *req;
4906 int status;
4907
bdce2ad7
SR		 4908 spin_lock_bh(&adapter->mcc_lock);
4909
4910 wrb = wrb_from_mccq(adapter);
4911 if (!wrb) {
4912 status = -EBUSY;
4913 goto err;
4914 }
4915
4916 req = embedded_payload(wrb);
4917
4918 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4919 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4920 sizeof(*req), wrb, NULL);
4921
d9d426af 4922 req->hdr.version = version;
bdce2ad7
SR		 4923 req->hdr.domain = domain;
4924
d9d426af
SR		 4925 if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4926 link_state == IFLA_VF_LINK_STATE_AUTO)
4927 req->link_config |= PLINK_ENABLE;
bdce2ad7
SR		 4928
4929 if (link_state == IFLA_VF_LINK_STATE_AUTO)
d9d426af 4930 req->link_config |= PLINK_TRACK;
bdce2ad7
SR		 4931
4932 status = be_mcc_notify_wait(adapter);
4933err:
4934 spin_unlock_bh(&adapter->mcc_lock);
4935 return status;
4936}
4937
d9d426af
SR		 4938int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4939 int link_state, u8 domain)
4940{
4941 int status;
4942
4943 if (BEx_chip(adapter))
4944 return -EOPNOTSUPP;
4945
4946 status = __be_cmd_set_logical_link_config(adapter, link_state,
4947 2, domain);
4948
4949 /* Version 2 of the command will not be recognized by older FW.
4950 * On such a failure issue version 1 of the command.
4951 */
4952 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4953 status = __be_cmd_set_logical_link_config(adapter, link_state,
4954 1, domain);
4955 return status;
4956}
6a4ab669 4957int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 4958 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 4959{
4960 struct be_adapter *adapter = netdev_priv(netdev_handle);
4961 struct be_mcc_wrb *wrb;
504fbf1e 4962 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 4963 struct be_cmd_req_hdr *req;
4964 struct be_cmd_resp_hdr *resp;
4965 int status;
4966
4967 spin_lock_bh(&adapter->mcc_lock);
4968
4969 wrb = wrb_from_mccq(adapter);
4970 if (!wrb) {
4971 status = -EBUSY;
4972 goto err;
4973 }
4974 req = embedded_payload(wrb);
4975 resp = embedded_payload(wrb);
4976
4977 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4978 hdr->opcode, wrb_payload_size, wrb, NULL);
4979 memcpy(req, wrb_payload, wrb_payload_size);
4980 be_dws_cpu_to_le(req, wrb_payload_size);
4981
4982 status = be_mcc_notify_wait(adapter);
4983 if (cmd_status)
4984 *cmd_status = (status & 0xffff);
4985 if (ext_status)
4986 *ext_status = 0;
4987 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4988 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4989err:
4990 spin_unlock_bh(&adapter->mcc_lock);
4991 return status;
4992}
4993EXPORT_SYMBOL(be_roce_mcc_cmd);
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