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be2net: move FW flash cmd code to be_cmds.c
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
d19261b8 2 * Copyright (C) 2005 - 2015 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
21252377
VV		 22static char *be_port_misconfig_evt_desc[] = {
23 "A valid SFP module detected",
24 "Optics faulted/ incorrectly installed/ not installed.",
25 "Optics of two types installed.",
26 "Incompatible optics.",
27 "Unknown port SFP status"
28};
29
30static char *be_port_misconfig_remedy_desc[] = {
31 "",
32 "Reseat optics. If issue not resolved, replace",
33 "Remove one optic or install matching pair of optics",
34 "Replace with compatible optics for card to function",
35 ""
36};
37
f25b119c
PR		 38static struct be_cmd_priv_map cmd_priv_map[] = {
39 {
40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
41 CMD_SUBSYSTEM_ETH,
42 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
43 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
44 },
45 {
46 OPCODE_COMMON_GET_FLOW_CONTROL,
47 CMD_SUBSYSTEM_COMMON,
48 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_SET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_ETH_GET_PPORT_STATS,
59 CMD_SUBSYSTEM_ETH,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_COMMON_GET_PHY_DETAILS,
65 CMD_SUBSYSTEM_COMMON,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 }
69};
70
a2cc4e0b 71static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 72{
73 int i;
74 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
75 u32 cmd_privileges = adapter->cmd_privileges;
76
77 for (i = 0; i < num_entries; i++)
78 if (opcode == cmd_priv_map[i].opcode &&
79 subsystem == cmd_priv_map[i].subsystem)
80 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
81 return false;
82
83 return true;
84}
85
3de09455
SK		 86static inline void *embedded_payload(struct be_mcc_wrb *wrb)
87{
88 return wrb->payload.embedded_payload;
89}
609ff3bb 90
efaa408e 91static int be_mcc_notify(struct be_adapter *adapter)
5fb379ee 92{
8788fdc2 93 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 94 u32 val = 0;
95
954f6825 96 if (be_check_error(adapter, BE_ERROR_ANY))
efaa408e 97 return -EIO;
7acc2087 98
5fb379ee
SP		 99 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
100 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 101
102 wmb();
8788fdc2 103 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
efaa408e
SR		 104
105 return 0;
5fb379ee
SP		 106}
107
108/* To check if valid bit is set, check the entire word as we don't know
109 * the endianness of the data (old entry is host endian while a new entry is
110 * little endian) */
efd2e40a 111static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 112{
9e9ff4b7
SP		 113 u32 flags;
114
5fb379ee 115 if (compl->flags != 0) {
9e9ff4b7
SP		 116 flags = le32_to_cpu(compl->flags);
117 if (flags & CQE_FLAGS_VALID_MASK) {
118 compl->flags = flags;
119 return true;
120 }
5fb379ee 121 }
9e9ff4b7 122 return false;
5fb379ee
SP		 123}
124
125/* Need to reset the entire word that houses the valid bit */
efd2e40a 126static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 127{
128 compl->flags = 0;
129}
130
652bf646
PR		 131static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
132{
133 unsigned long addr;
134
135 addr = tag1;
136 addr = ((addr << 16) << 16) | tag0;
137 return (void *)addr;
138}
139
4c60005f
KA		 140static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
141{
142 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
143 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
144 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
77be8c1c 145 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
4c60005f
KA		 146 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
147 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
148 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
149 return true;
150 else
151 return false;
152}
153
559b633f
SP		 154/* Place holder for all the async MCC cmds wherein the caller is not in a busy
155 * loop (has not issued be_mcc_notify_wait())
156 */
157static void be_async_cmd_process(struct be_adapter *adapter,
158 struct be_mcc_compl *compl,
159 struct be_cmd_resp_hdr *resp_hdr)
160{
161 enum mcc_base_status base_status = base_status(compl->status);
162 u8 opcode = 0, subsystem = 0;
163
164 if (resp_hdr) {
165 opcode = resp_hdr->opcode;
166 subsystem = resp_hdr->subsystem;
167 }
168
169 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
170 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
171 complete(&adapter->et_cmd_compl);
172 return;
173 }
174
9c855975
SR		 175 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
176 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
177 complete(&adapter->et_cmd_compl);
178 return;
179 }
180
559b633f
SP		 181 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
182 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
183 subsystem == CMD_SUBSYSTEM_COMMON) {
184 adapter->flash_status = compl->status;
185 complete(&adapter->et_cmd_compl);
186 return;
187 }
188
189 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
190 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
191 subsystem == CMD_SUBSYSTEM_ETH &&
192 base_status == MCC_STATUS_SUCCESS) {
193 be_parse_stats(adapter);
194 adapter->stats_cmd_sent = false;
195 return;
196 }
197
198 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
199 subsystem == CMD_SUBSYSTEM_COMMON) {
200 if (base_status == MCC_STATUS_SUCCESS) {
201 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
202 (void *)resp_hdr;
29e9122b 203 adapter->hwmon_info.be_on_die_temp =
559b633f
SP		 204 resp->on_die_temperature;
205 } else {
206 adapter->be_get_temp_freq = 0;
29e9122b
VD		 207 adapter->hwmon_info.be_on_die_temp =
208 BE_INVALID_DIE_TEMP;
559b633f
SP		 209 }
210 return;
211 }
212}
213
8788fdc2 214static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 215 struct be_mcc_compl *compl)
5fb379ee 216{
4c60005f
KA		 217 enum mcc_base_status base_status;
218 enum mcc_addl_status addl_status;
652bf646
PR		 219 struct be_cmd_resp_hdr *resp_hdr;
220 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 221
222 /* Just swap the status to host endian; mcc tag is opaquely copied
223 * from mcc_wrb */
224 be_dws_le_to_cpu(compl, 4);
225
4c60005f
KA		 226 base_status = base_status(compl->status);
227 addl_status = addl_status(compl->status);
96c9b2e4 228
652bf646 229 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 230 if (resp_hdr) {
231 opcode = resp_hdr->opcode;
232 subsystem = resp_hdr->subsystem;
233 }
234
559b633f 235 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 236
559b633f
SP		 237 if (base_status != MCC_STATUS_SUCCESS &&
238 !be_skip_err_log(opcode, base_status, addl_status)) {
4c60005f 239 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 240 dev_warn(&adapter->pdev->dev,
522609f2 241 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 242 opcode, subsystem);
2b3f291b 243 } else {
97f1d8cd
VV		 244 dev_err(&adapter->pdev->dev,
245 "opcode %d-%d failed:status %d-%d\n",
4c60005f 246 opcode, subsystem, base_status, addl_status);
2b3f291b 247 }
5fb379ee 248 }
4c60005f 249 return compl->status;
5fb379ee
SP		 250}
251
a8f447bd 252/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 253static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 254 struct be_mcc_compl *compl)
a8f447bd 255{
3acf19d9
SP		 256 struct be_async_event_link_state *evt =
257 (struct be_async_event_link_state *)compl;
258
b236916a 259 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 260 adapter->phy.link_speed = -1;
b236916a 261
bdce2ad7
SR		 262 /* On BEx the FW does not send a separate link status
263 * notification for physical and logical link.
264 * On other chips just process the logical link
265 * status notification
266 */
267 if (!BEx_chip(adapter) &&
2e177a5c
PR		 268 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
269 return;
270
b236916a
AK		 271 /* For the initial link status do not rely on the ASYNC event as
272 * it may not be received in some cases.
273 */
274 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 275 be_link_status_update(adapter,
276 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 277}
278
21252377
VV		 279static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
280 struct be_mcc_compl *compl)
281{
282 struct be_async_event_misconfig_port *evt =
283 (struct be_async_event_misconfig_port *)compl;
284 u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
285 struct device *dev = &adapter->pdev->dev;
286 u8 port_misconfig_evt;
287
288 port_misconfig_evt =
289 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
290
291 /* Log an error message that would allow a user to determine
292 * whether the SFPs have an issue
293 */
294 dev_info(dev, "Port %c: %s %s", adapter->port_name,
295 be_port_misconfig_evt_desc[port_misconfig_evt],
296 be_port_misconfig_remedy_desc[port_misconfig_evt]);
297
298 if (port_misconfig_evt == INCOMPATIBLE_SFP)
299 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
300}
301
cc4ce020
SK		 302/* Grp5 CoS Priority evt */
303static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 304 struct be_mcc_compl *compl)
cc4ce020 305{
3acf19d9
SP		 306 struct be_async_event_grp5_cos_priority *evt =
307 (struct be_async_event_grp5_cos_priority *)compl;
308
cc4ce020
SK		 309 if (evt->valid) {
310 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 311 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 312 adapter->recommended_prio =
313 evt->reco_default_priority << VLAN_PRIO_SHIFT;
314 }
315}
316
323ff71e 317/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 318static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 319 struct be_mcc_compl *compl)
cc4ce020 320{
3acf19d9
SP		 321 struct be_async_event_grp5_qos_link_speed *evt =
322 (struct be_async_event_grp5_qos_link_speed *)compl;
323
323ff71e
SP		 324 if (adapter->phy.link_speed >= 0 &&
325 evt->physical_port == adapter->port_num)
326 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 327}
328
3968fa1e
AK		 329/*Grp5 PVID evt*/
330static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 331 struct be_mcc_compl *compl)
3968fa1e 332{
3acf19d9
SP		 333 struct be_async_event_grp5_pvid_state *evt =
334 (struct be_async_event_grp5_pvid_state *)compl;
335
bdac85b5 336 if (evt->enabled) {
939cf306 337 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 338 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
339 } else {
3968fa1e 340 adapter->pvid = 0;
bdac85b5 341 }
3968fa1e
AK		 342}
343
760c295e
VD		 344#define MGMT_ENABLE_MASK 0x4
345static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
346 struct be_mcc_compl *compl)
347{
348 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
349 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
350
351 if (evt_dw1 & MGMT_ENABLE_MASK) {
352 adapter->flags |= BE_FLAGS_OS2BMC;
353 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
354 } else {
355 adapter->flags &= ~BE_FLAGS_OS2BMC;
356 }
357}
358
cc4ce020 359static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 360 struct be_mcc_compl *compl)
cc4ce020 361{
3acf19d9
SP		 362 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
363 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 364
365 switch (event_type) {
366 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 367 be_async_grp5_cos_priority_process(adapter, compl);
368 break;
cc4ce020 369 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 370 be_async_grp5_qos_speed_process(adapter, compl);
371 break;
3968fa1e 372 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 373 be_async_grp5_pvid_state_process(adapter, compl);
374 break;
760c295e
VD		 375 /* Async event to disable/enable os2bmc and/or mac-learning */
376 case ASYNC_EVENT_FW_CONTROL:
377 be_async_grp5_fw_control_process(adapter, compl);
378 break;
cc4ce020 379 default:
cc4ce020
SK		 380 break;
381 }
382}
383
bc0c3405 384static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 385 struct be_mcc_compl *cmp)
bc0c3405
AK		 386{
387 u8 event_type = 0;
504fbf1e 388 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 389
3acf19d9
SP		 390 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
391 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 392
393 switch (event_type) {
394 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
395 if (evt->valid)
396 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
397 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
398 break;
399 default:
05ccaa2b
VV		 400 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
401 event_type);
bc0c3405
AK		 402 break;
403 }
404}
405
21252377
VV		 406static void be_async_sliport_evt_process(struct be_adapter *adapter,
407 struct be_mcc_compl *cmp)
408{
409 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
410 ASYNC_EVENT_TYPE_MASK;
411
412 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
413 be_async_port_misconfig_event_process(adapter, cmp);
414}
415
3acf19d9 416static inline bool is_link_state_evt(u32 flags)
a8f447bd 417{
3acf19d9
SP		 418 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
419 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 420}
5fb379ee 421
3acf19d9 422static inline bool is_grp5_evt(u32 flags)
cc4ce020 423{
3acf19d9
SP		 424 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
425 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 426}
427
3acf19d9 428static inline bool is_dbg_evt(u32 flags)
bc0c3405 429{
3acf19d9
SP		 430 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
431 ASYNC_EVENT_CODE_QNQ;
432}
433
21252377
VV		 434static inline bool is_sliport_evt(u32 flags)
435{
436 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
437 ASYNC_EVENT_CODE_SLIPORT;
438}
439
3acf19d9
SP		 440static void be_mcc_event_process(struct be_adapter *adapter,
441 struct be_mcc_compl *compl)
442{
443 if (is_link_state_evt(compl->flags))
444 be_async_link_state_process(adapter, compl);
445 else if (is_grp5_evt(compl->flags))
446 be_async_grp5_evt_process(adapter, compl);
447 else if (is_dbg_evt(compl->flags))
448 be_async_dbg_evt_process(adapter, compl);
21252377
VV		 449 else if (is_sliport_evt(compl->flags))
450 be_async_sliport_evt_process(adapter, compl);
bc0c3405
AK		 451}
452
efd2e40a 453static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 454{
8788fdc2 455 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 456 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 457
458 if (be_mcc_compl_is_new(compl)) {
459 queue_tail_inc(mcc_cq);
460 return compl;
461 }
462 return NULL;
463}
464
7a1e9b20
SP		 465void be_async_mcc_enable(struct be_adapter *adapter)
466{
467 spin_lock_bh(&adapter->mcc_cq_lock);
468
469 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
470 adapter->mcc_obj.rearm_cq = true;
471
472 spin_unlock_bh(&adapter->mcc_cq_lock);
473}
474
475void be_async_mcc_disable(struct be_adapter *adapter)
476{
a323d9bf
SP		 477 spin_lock_bh(&adapter->mcc_cq_lock);
478
7a1e9b20 479 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 480 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
481
482 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 483}
484
10ef9ab4 485int be_process_mcc(struct be_adapter *adapter)
5fb379ee 486{
efd2e40a 487 struct be_mcc_compl *compl;
10ef9ab4 488 int num = 0, status = 0;
7a1e9b20 489 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 490
072a9c48 491 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 492
8788fdc2 493 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 494 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 495 be_mcc_event_process(adapter, compl);
b31c50a7 496 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 497 status = be_mcc_compl_process(adapter, compl);
498 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 499 }
500 be_mcc_compl_use(compl);
501 num++;
502 }
b31c50a7 503
10ef9ab4
SP		 504 if (num)
505 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
506
072a9c48 507 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 508 return status;
5fb379ee
SP		 509}
510
6ac7b687 511/* Wait till no more pending mcc requests are present */
b31c50a7 512static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 513{
b31c50a7 514#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 515 int i, status = 0;
f31e50a8
SP		 516 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
517
6ac7b687 518 for (i = 0; i < mcc_timeout; i++) {
954f6825 519 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 520 return -EIO;
521
072a9c48 522 local_bh_disable();
10ef9ab4 523 status = be_process_mcc(adapter);
072a9c48 524 local_bh_enable();
b31c50a7 525
f31e50a8 526 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 527 break;
528 udelay(100);
529 }
b31c50a7 530 if (i == mcc_timeout) {
6589ade0 531 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 532 be_set_error(adapter, BE_ERROR_FW);
652bf646 533 return -EIO;
b31c50a7 534 }
f31e50a8 535 return status;
6ac7b687
SP		 536}
537
538/* Notify MCC requests and wait for completion */
b31c50a7 539static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 540{
652bf646
PR		 541 int status;
542 struct be_mcc_wrb *wrb;
543 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
544 u16 index = mcc_obj->q.head;
545 struct be_cmd_resp_hdr *resp;
546
547 index_dec(&index, mcc_obj->q.len);
548 wrb = queue_index_node(&mcc_obj->q, index);
549
550 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
551
efaa408e
SR		 552 status = be_mcc_notify(adapter);
553 if (status)
554 goto out;
652bf646
PR		 555
556 status = be_mcc_wait_compl(adapter);
557 if (status == -EIO)
558 goto out;
559
4c60005f
KA		 560 status = (resp->base_status |
561 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
562 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 563out:
564 return status;
6ac7b687
SP		 565}
566
5f0b849e 567static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 568{
f25b03a7 569 int msecs = 0;
6b7c5b94
SP		 570 u32 ready;
571
572 do {
954f6825 573 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 574 return -EIO;
575
cf588477 576 ready = ioread32(db);
434b3648 577 if (ready == 0xffffffff)
cf588477 578 return -1;
cf588477
SP		 579
580 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 581 if (ready)
582 break;
583
f25b03a7 584 if (msecs > 4000) {
6589ade0 585 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 586 be_set_error(adapter, BE_ERROR_FW);
f67ef7ba 587 be_detect_error(adapter);
6b7c5b94
SP		 588 return -1;
589 }
590
1dbf53a2 591 msleep(1);
f25b03a7 592 msecs++;
6b7c5b94
SP		 593 } while (true);
594
595 return 0;
596}
597
598/*
599 * Insert the mailbox address into the doorbell in two steps
5fb379ee 600 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 601 */
b31c50a7 602static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 603{
604 int status;
6b7c5b94 605 u32 val = 0;
8788fdc2
SP		 606 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
607 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 608 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 609 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 610
cf588477
SP		 611 /* wait for ready to be set */
612 status = be_mbox_db_ready_wait(adapter, db);
613 if (status != 0)
614 return status;
615
6b7c5b94
SP		 616 val |= MPU_MAILBOX_DB_HI_MASK;
617 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
618 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
619 iowrite32(val, db);
620
621 /* wait for ready to be set */
5f0b849e 622 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 623 if (status != 0)
624 return status;
625
626 val = 0;
6b7c5b94
SP		 627 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
628 val |= (u32)(mbox_mem->dma >> 4) << 2;
629 iowrite32(val, db);
630
5f0b849e 631 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 632 if (status != 0)
633 return status;
634
5fb379ee 635 /* A cq entry has been made now */
efd2e40a
SP		 636 if (be_mcc_compl_is_new(compl)) {
637 status = be_mcc_compl_process(adapter, &mbox->compl);
638 be_mcc_compl_use(compl);
5fb379ee
SP		 639 if (status)
640 return status;
641 } else {
5f0b849e 642 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 643 return -1;
644 }
5fb379ee 645 return 0;
6b7c5b94
SP		 646}
647
c5b3ad4c 648static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 649{
fe6d2a38
SP		 650 u32 sem;
651
c5b3ad4c
SP		 652 if (BEx_chip(adapter))
653 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 654 else
c5b3ad4c
SP		 655 pci_read_config_dword(adapter->pdev,
656 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
657
658 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 659}
660
87f20c26 661static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 662{
663#define SLIPORT_READY_TIMEOUT 30
664 u32 sliport_status;
e673244a 665 int i;
bf99e50d
PR		 666
667 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
668 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
669 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
9fa465c0 670 return 0;
67297ad8 671
9fa465c0
SP		 672 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
673 !(sliport_status & SLIPORT_STATUS_RN_MASK))
674 return -EIO;
67297ad8 675
9fa465c0 676 msleep(1000);
bf99e50d 677 }
67297ad8 678
9fa465c0 679 return sliport_status ? : -1;
bf99e50d
PR		 680}
681
682int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 683{
43a04fdc
SP		 684 u16 stage;
685 int status, timeout = 0;
6ed35eea 686 struct device *dev = &adapter->pdev->dev;
6b7c5b94 687
bf99e50d
PR		 688 if (lancer_chip(adapter)) {
689 status = lancer_wait_ready(adapter);
e673244a
KA		 690 if (status) {
691 stage = status;
692 goto err;
693 }
694 return 0;
bf99e50d
PR		 695 }
696
43a04fdc 697 do {
ca3de6b2
SP		 698 /* There's no means to poll POST state on BE2/3 VFs */
699 if (BEx_chip(adapter) && be_virtfn(adapter))
700 return 0;
701
c5b3ad4c 702 stage = be_POST_stage_get(adapter);
66d29cbc 703 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 704 return 0;
66d29cbc 705
a2cc4e0b 706 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 707 if (msleep_interruptible(2000)) {
708 dev_err(dev, "Waiting for POST aborted\n");
709 return -EINTR;
43a04fdc 710 }
66d29cbc 711 timeout += 2;
3ab81b5f 712 } while (timeout < 60);
6b7c5b94 713
e673244a
KA		 714err:
715 dev_err(dev, "POST timeout; stage=%#x\n", stage);
9fa465c0 716 return -ETIMEDOUT;
6b7c5b94
SP		 717}
718
6b7c5b94
SP		 719static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
720{
721 return &wrb->payload.sgl[0];
722}
723
a2cc4e0b 724static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 725{
726 wrb->tag0 = addr & 0xFFFFFFFF;
727 wrb->tag1 = upper_32_bits(addr);
728}
6b7c5b94
SP		 729
730/* Don't touch the hdr after it's prepared */
106df1e3
SK		 731/* mem will be NULL for embedded commands */
732static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 733 u8 subsystem, u8 opcode, int cmd_len,
734 struct be_mcc_wrb *wrb,
735 struct be_dma_mem *mem)
6b7c5b94 736{
106df1e3
SK		 737 struct be_sge *sge;
738
6b7c5b94
SP		 739 req_hdr->opcode = opcode;
740 req_hdr->subsystem = subsystem;
741 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 742 req_hdr->version = 0;
bea50988 743 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 744 wrb->payload_length = cmd_len;
745 if (mem) {
746 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
747 MCC_WRB_SGE_CNT_SHIFT;
748 sge = nonembedded_sgl(wrb);
749 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
750 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
751 sge->len = cpu_to_le32(mem->size);
752 } else
753 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
754 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 755}
756
757static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 758 struct be_dma_mem *mem)
6b7c5b94
SP		 759{
760 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
761 u64 dma = (u64)mem->dma;
762
763 for (i = 0; i < buf_pages; i++) {
764 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
765 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
766 dma += PAGE_SIZE_4K;
767 }
768}
769
b31c50a7 770static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 771{
b31c50a7
SP		 772 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
773 struct be_mcc_wrb *wrb
774 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
775 memset(wrb, 0, sizeof(*wrb));
776 return wrb;
6b7c5b94
SP		 777}
778
b31c50a7 779static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 780{
b31c50a7
SP		 781 struct be_queue_info *mccq = &adapter->mcc_obj.q;
782 struct be_mcc_wrb *wrb;
783
aa790db9
PR		 784 if (!mccq->created)
785 return NULL;
786
4d277125 787 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 788 return NULL;
713d0394 789
b31c50a7
SP		 790 wrb = queue_head_node(mccq);
791 queue_head_inc(mccq);
792 atomic_inc(&mccq->used);
793 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 794 return wrb;
795}
796
bea50988
SP		 797static bool use_mcc(struct be_adapter *adapter)
798{
799 return adapter->mcc_obj.q.created;
800}
801
802/* Must be used only in process context */
803static int be_cmd_lock(struct be_adapter *adapter)
804{
805 if (use_mcc(adapter)) {
806 spin_lock_bh(&adapter->mcc_lock);
807 return 0;
808 } else {
809 return mutex_lock_interruptible(&adapter->mbox_lock);
810 }
811}
812
813/* Must be used only in process context */
814static void be_cmd_unlock(struct be_adapter *adapter)
815{
816 if (use_mcc(adapter))
817 spin_unlock_bh(&adapter->mcc_lock);
818 else
819 return mutex_unlock(&adapter->mbox_lock);
820}
821
822static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
823 struct be_mcc_wrb *wrb)
824{
825 struct be_mcc_wrb *dest_wrb;
826
827 if (use_mcc(adapter)) {
828 dest_wrb = wrb_from_mccq(adapter);
829 if (!dest_wrb)
830 return NULL;
831 } else {
832 dest_wrb = wrb_from_mbox(adapter);
833 }
834
835 memcpy(dest_wrb, wrb, sizeof(*wrb));
836 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
837 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
838
839 return dest_wrb;
840}
841
842/* Must be used only in process context */
843static int be_cmd_notify_wait(struct be_adapter *adapter,
844 struct be_mcc_wrb *wrb)
845{
846 struct be_mcc_wrb *dest_wrb;
847 int status;
848
849 status = be_cmd_lock(adapter);
850 if (status)
851 return status;
852
853 dest_wrb = be_cmd_copy(adapter, wrb);
0c884567
SR		 854 if (!dest_wrb) {
855 status = -EBUSY;
856 goto unlock;
857 }
bea50988
SP		 858
859 if (use_mcc(adapter))
860 status = be_mcc_notify_wait(adapter);
861 else
862 status = be_mbox_notify_wait(adapter);
863
864 if (!status)
865 memcpy(wrb, dest_wrb, sizeof(*wrb));
866
0c884567 867unlock:
bea50988
SP		 868 be_cmd_unlock(adapter);
869 return status;
870}
871
2243e2e9
SP		 872/* Tell fw we're about to start firing cmds by writing a
873 * special pattern across the wrb hdr; uses mbox
874 */
875int be_cmd_fw_init(struct be_adapter *adapter)
876{
877 u8 *wrb;
878 int status;
879
bf99e50d
PR		 880 if (lancer_chip(adapter))
881 return 0;
882
2984961c
IV		 883 if (mutex_lock_interruptible(&adapter->mbox_lock))
884 return -1;
2243e2e9
SP		 885
886 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 887 *wrb++ = 0xFF;
888 *wrb++ = 0x12;
889 *wrb++ = 0x34;
890 *wrb++ = 0xFF;
891 *wrb++ = 0xFF;
892 *wrb++ = 0x56;
893 *wrb++ = 0x78;
894 *wrb = 0xFF;
2243e2e9
SP		 895
896 status = be_mbox_notify_wait(adapter);
897
2984961c 898 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 899 return status;
900}
901
902/* Tell fw we're done with firing cmds by writing a
903 * special pattern across the wrb hdr; uses mbox
904 */
905int be_cmd_fw_clean(struct be_adapter *adapter)
906{
907 u8 *wrb;
908 int status;
909
bf99e50d
PR		 910 if (lancer_chip(adapter))
911 return 0;
912
2984961c
IV		 913 if (mutex_lock_interruptible(&adapter->mbox_lock))
914 return -1;
2243e2e9
SP		 915
916 wrb = (u8 *)wrb_from_mbox(adapter);
917 *wrb++ = 0xFF;
918 *wrb++ = 0xAA;
919 *wrb++ = 0xBB;
920 *wrb++ = 0xFF;
921 *wrb++ = 0xFF;
922 *wrb++ = 0xCC;
923 *wrb++ = 0xDD;
924 *wrb = 0xFF;
925
926 status = be_mbox_notify_wait(adapter);
927
2984961c 928 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 929 return status;
930}
bf99e50d 931
f2f781a7 932int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 933{
b31c50a7
SP		 934 struct be_mcc_wrb *wrb;
935 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 936 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
937 int status, ver = 0;
6b7c5b94 938
2984961c
IV		 939 if (mutex_lock_interruptible(&adapter->mbox_lock))
940 return -1;
b31c50a7
SP		 941
942 wrb = wrb_from_mbox(adapter);
943 req = embedded_payload(wrb);
6b7c5b94 944
106df1e3 945 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 946 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
947 NULL);
6b7c5b94 948
f2f781a7
SP		 949 /* Support for EQ_CREATEv2 available only SH-R onwards */
950 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
951 ver = 2;
952
953 req->hdr.version = ver;
6b7c5b94
SP		 954 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
955
6b7c5b94
SP		 956 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
957 /* 4byte eqe*/
958 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
959 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 960 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 961 be_dws_cpu_to_le(req->context, sizeof(req->context));
962
963 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
964
b31c50a7 965 status = be_mbox_notify_wait(adapter);
6b7c5b94 966 if (!status) {
b31c50a7 967 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 968
f2f781a7
SP		 969 eqo->q.id = le16_to_cpu(resp->eq_id);
970 eqo->msix_idx =
971 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
972 eqo->q.created = true;
6b7c5b94 973 }
b31c50a7 974
2984961c 975 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 976 return status;
977}
978
f9449ab7 979/* Use MCC */
8788fdc2 980int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 981 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 982{
b31c50a7
SP		 983 struct be_mcc_wrb *wrb;
984 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 985 int status;
986
f9449ab7 987 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 988
f9449ab7
SP		 989 wrb = wrb_from_mccq(adapter);
990 if (!wrb) {
991 status = -EBUSY;
992 goto err;
993 }
b31c50a7 994 req = embedded_payload(wrb);
6b7c5b94 995
106df1e3 996 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 997 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
998 NULL);
5ee4979b 999 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 1000 if (permanent) {
1001 req->permanent = 1;
1002 } else {
504fbf1e 1003 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 1004 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 1005 req->permanent = 0;
1006 }
1007
f9449ab7 1008 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 1009 if (!status) {
1010 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 1011
6b7c5b94 1012 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 1013 }
6b7c5b94 1014
f9449ab7
SP		 1015err:
1016 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1017 return status;
1018}
1019
b31c50a7 1020/* Uses synchronous MCCQ */
8788fdc2 1021int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 1022 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 1023{
b31c50a7
SP		 1024 struct be_mcc_wrb *wrb;
1025 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 1026 int status;
1027
b31c50a7
SP		 1028 spin_lock_bh(&adapter->mcc_lock);
1029
1030 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1031 if (!wrb) {
1032 status = -EBUSY;
1033 goto err;
1034 }
b31c50a7 1035 req = embedded_payload(wrb);
6b7c5b94 1036
106df1e3 1037 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1038 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1039 NULL);
6b7c5b94 1040
f8617e08 1041 req->hdr.domain = domain;
6b7c5b94
SP		 1042 req->if_id = cpu_to_le32(if_id);
1043 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1044
b31c50a7 1045 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1046 if (!status) {
1047 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1048
6b7c5b94
SP		 1049 *pmac_id = le32_to_cpu(resp->pmac_id);
1050 }
1051
713d0394 1052err:
b31c50a7 1053 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 1054
1055 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1056 status = -EPERM;
1057
6b7c5b94
SP		 1058 return status;
1059}
1060
b31c50a7 1061/* Uses synchronous MCCQ */
30128031 1062int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1063{
b31c50a7
SP		 1064 struct be_mcc_wrb *wrb;
1065 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1066 int status;
1067
30128031
SP		 1068 if (pmac_id == -1)
1069 return 0;
1070
b31c50a7
SP		 1071 spin_lock_bh(&adapter->mcc_lock);
1072
1073 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1074 if (!wrb) {
1075 status = -EBUSY;
1076 goto err;
1077 }
b31c50a7 1078 req = embedded_payload(wrb);
6b7c5b94 1079
106df1e3 1080 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
cd3307aa
KA		 1081 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1082 wrb, NULL);
6b7c5b94 1083
f8617e08 1084 req->hdr.domain = dom;
6b7c5b94
SP		 1085 req->if_id = cpu_to_le32(if_id);
1086 req->pmac_id = cpu_to_le32(pmac_id);
1087
b31c50a7
SP		 1088 status = be_mcc_notify_wait(adapter);
1089
713d0394 1090err:
b31c50a7 1091 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1092 return status;
1093}
1094
b31c50a7 1095/* Uses Mbox */
10ef9ab4 1096int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1097 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1098{
b31c50a7
SP		 1099 struct be_mcc_wrb *wrb;
1100 struct be_cmd_req_cq_create *req;
6b7c5b94 1101 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1102 void *ctxt;
6b7c5b94
SP		 1103 int status;
1104
2984961c
IV		 1105 if (mutex_lock_interruptible(&adapter->mbox_lock))
1106 return -1;
b31c50a7
SP		 1107
1108 wrb = wrb_from_mbox(adapter);
1109 req = embedded_payload(wrb);
1110 ctxt = &req->context;
6b7c5b94 1111
106df1e3 1112 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1113 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1114 NULL);
6b7c5b94
SP		 1115
1116 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1117
1118 if (BEx_chip(adapter)) {
fe6d2a38 1119 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1120 coalesce_wm);
fe6d2a38 1121 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1122 ctxt, no_delay);
fe6d2a38 1123 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1124 __ilog2_u32(cq->len / 256));
fe6d2a38 1125 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1126 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1127 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1128 } else {
1129 req->hdr.version = 2;
1130 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1131
1132 /* coalesce-wm field in this cmd is not relevant to Lancer.
1133 * Lancer uses COMMON_MODIFY_CQ to set this field
1134 */
1135 if (!lancer_chip(adapter))
1136 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1137 ctxt, coalesce_wm);
bbdc42f8 1138 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1139 no_delay);
bbdc42f8 1140 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1141 __ilog2_u32(cq->len / 256));
bbdc42f8 1142 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1143 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1144 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1145 }
6b7c5b94 1146
6b7c5b94
SP		 1147 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1148
1149 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1150
b31c50a7 1151 status = be_mbox_notify_wait(adapter);
6b7c5b94 1152 if (!status) {
b31c50a7 1153 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1154
6b7c5b94
SP		 1155 cq->id = le16_to_cpu(resp->cq_id);
1156 cq->created = true;
1157 }
b31c50a7 1158
2984961c 1159 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1160
1161 return status;
1162}
1163
1164static u32 be_encoded_q_len(int q_len)
1165{
1166 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1167
5fb379ee
SP		 1168 if (len_encoded == 16)
1169 len_encoded = 0;
1170 return len_encoded;
1171}
1172
4188e7df 1173static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1174 struct be_queue_info *mccq,
1175 struct be_queue_info *cq)
5fb379ee 1176{
b31c50a7 1177 struct be_mcc_wrb *wrb;
34b1ef04 1178 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1179 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1180 void *ctxt;
5fb379ee
SP		 1181 int status;
1182
2984961c
IV		 1183 if (mutex_lock_interruptible(&adapter->mbox_lock))
1184 return -1;
b31c50a7
SP		 1185
1186 wrb = wrb_from_mbox(adapter);
1187 req = embedded_payload(wrb);
1188 ctxt = &req->context;
5fb379ee 1189
106df1e3 1190 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1191 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1192 NULL);
5fb379ee 1193
d4a2ac3e 1194 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1195 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1196 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1197 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1198 be_encoded_q_len(mccq->len));
fe6d2a38 1199 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1200 } else {
1201 req->hdr.version = 1;
1202 req->cq_id = cpu_to_le16(cq->id);
1203
1204 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1205 be_encoded_q_len(mccq->len));
1206 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1207 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1208 ctxt, cq->id);
1209 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1210 ctxt, 1);
fe6d2a38 1211 }
5fb379ee 1212
21252377
VV		 1213 /* Subscribe to Link State, Sliport Event and Group 5 Events
1214 * (bits 1, 5 and 17 set)
1215 */
1216 req->async_event_bitmap[0] =
1217 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1218 BIT(ASYNC_EVENT_CODE_GRP_5) |
1219 BIT(ASYNC_EVENT_CODE_QNQ) |
1220 BIT(ASYNC_EVENT_CODE_SLIPORT));
1221
5fb379ee
SP		 1222 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1223
1224 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1225
b31c50a7 1226 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1227 if (!status) {
1228 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1229
5fb379ee
SP		 1230 mccq->id = le16_to_cpu(resp->id);
1231 mccq->created = true;
1232 }
2984961c 1233 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1234
1235 return status;
1236}
1237
4188e7df 1238static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1239 struct be_queue_info *mccq,
1240 struct be_queue_info *cq)
34b1ef04
SK		 1241{
1242 struct be_mcc_wrb *wrb;
1243 struct be_cmd_req_mcc_create *req;
1244 struct be_dma_mem *q_mem = &mccq->dma_mem;
1245 void *ctxt;
1246 int status;
1247
1248 if (mutex_lock_interruptible(&adapter->mbox_lock))
1249 return -1;
1250
1251 wrb = wrb_from_mbox(adapter);
1252 req = embedded_payload(wrb);
1253 ctxt = &req->context;
1254
106df1e3 1255 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1256 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1257 NULL);
34b1ef04
SK		 1258
1259 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1260
1261 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1262 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1263 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1264 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1265
1266 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1267
1268 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1269
1270 status = be_mbox_notify_wait(adapter);
1271 if (!status) {
1272 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1273
34b1ef04
SK		 1274 mccq->id = le16_to_cpu(resp->id);
1275 mccq->created = true;
1276 }
1277
1278 mutex_unlock(&adapter->mbox_lock);
1279 return status;
1280}
1281
1282int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1283 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1284{
1285 int status;
1286
1287 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1288 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1289 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1290 "or newer to avoid conflicting priorities between NIC "
1291 "and FCoE traffic");
1292 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1293 }
1294 return status;
1295}
1296
94d73aaa 1297int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1298{
7707133c 1299 struct be_mcc_wrb wrb = {0};
b31c50a7 1300 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1301 struct be_queue_info *txq = &txo->q;
1302 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1303 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1304 int status, ver = 0;
6b7c5b94 1305
7707133c 1306 req = embedded_payload(&wrb);
106df1e3 1307 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1308 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1309
8b7756ca
PR		 1310 if (lancer_chip(adapter)) {
1311 req->hdr.version = 1;
94d73aaa
VV		 1312 } else if (BEx_chip(adapter)) {
1313 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1314 req->hdr.version = 2;
1315 } else { /* For SH */
1316 req->hdr.version = 2;
8b7756ca
PR		 1317 }
1318
81b02655
VV		 1319 if (req->hdr.version > 0)
1320 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1321 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1322 req->ulp_num = BE_ULP1_NUM;
1323 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1324 req->cq_id = cpu_to_le16(cq->id);
1325 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1326 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1327 ver = req->hdr.version;
1328
7707133c 1329 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1330 if (!status) {
7707133c 1331 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1332
6b7c5b94 1333 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1334 if (ver == 2)
1335 txo->db_offset = le32_to_cpu(resp->db_offset);
1336 else
1337 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1338 txq->created = true;
1339 }
b31c50a7 1340
6b7c5b94
SP		 1341 return status;
1342}
1343
482c9e79 1344/* Uses MCC */
8788fdc2 1345int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1346 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1347 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1348{
b31c50a7
SP		 1349 struct be_mcc_wrb *wrb;
1350 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1351 struct be_dma_mem *q_mem = &rxq->dma_mem;
1352 int status;
1353
482c9e79 1354 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1355
482c9e79
SP		 1356 wrb = wrb_from_mccq(adapter);
1357 if (!wrb) {
1358 status = -EBUSY;
1359 goto err;
1360 }
b31c50a7 1361 req = embedded_payload(wrb);
6b7c5b94 1362
106df1e3 1363 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1364 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1365
1366 req->cq_id = cpu_to_le16(cq_id);
1367 req->frag_size = fls(frag_size) - 1;
1368 req->num_pages = 2;
1369 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1370 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1371 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1372 req->rss_queue = cpu_to_le32(rss);
1373
482c9e79 1374 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1375 if (!status) {
1376 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1377
6b7c5b94
SP		 1378 rxq->id = le16_to_cpu(resp->id);
1379 rxq->created = true;
3abcdeda 1380 *rss_id = resp->rss_id;
6b7c5b94 1381 }
b31c50a7 1382
482c9e79
SP		 1383err:
1384 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1385 return status;
1386}
1387
b31c50a7
SP		 1388/* Generic destroyer function for all types of queues
1389 * Uses Mbox
1390 */
8788fdc2 1391int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1392 int queue_type)
6b7c5b94 1393{
b31c50a7
SP		 1394 struct be_mcc_wrb *wrb;
1395 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1396 u8 subsys = 0, opcode = 0;
1397 int status;
1398
2984961c
IV		 1399 if (mutex_lock_interruptible(&adapter->mbox_lock))
1400 return -1;
6b7c5b94 1401
b31c50a7
SP		 1402 wrb = wrb_from_mbox(adapter);
1403 req = embedded_payload(wrb);
1404
6b7c5b94
SP		 1405 switch (queue_type) {
1406 case QTYPE_EQ:
1407 subsys = CMD_SUBSYSTEM_COMMON;
1408 opcode = OPCODE_COMMON_EQ_DESTROY;
1409 break;
1410 case QTYPE_CQ:
1411 subsys = CMD_SUBSYSTEM_COMMON;
1412 opcode = OPCODE_COMMON_CQ_DESTROY;
1413 break;
1414 case QTYPE_TXQ:
1415 subsys = CMD_SUBSYSTEM_ETH;
1416 opcode = OPCODE_ETH_TX_DESTROY;
1417 break;
1418 case QTYPE_RXQ:
1419 subsys = CMD_SUBSYSTEM_ETH;
1420 opcode = OPCODE_ETH_RX_DESTROY;
1421 break;
5fb379ee
SP		 1422 case QTYPE_MCCQ:
1423 subsys = CMD_SUBSYSTEM_COMMON;
1424 opcode = OPCODE_COMMON_MCC_DESTROY;
1425 break;
6b7c5b94 1426 default:
5f0b849e 1427 BUG();
6b7c5b94 1428 }
d744b44e 1429
106df1e3 1430 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1431 NULL);
6b7c5b94
SP		 1432 req->id = cpu_to_le16(q->id);
1433
b31c50a7 1434 status = be_mbox_notify_wait(adapter);
aa790db9 1435 q->created = false;
5f0b849e 1436
2984961c 1437 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1438 return status;
1439}
6b7c5b94 1440
482c9e79
SP		 1441/* Uses MCC */
1442int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1443{
1444 struct be_mcc_wrb *wrb;
1445 struct be_cmd_req_q_destroy *req;
1446 int status;
1447
1448 spin_lock_bh(&adapter->mcc_lock);
1449
1450 wrb = wrb_from_mccq(adapter);
1451 if (!wrb) {
1452 status = -EBUSY;
1453 goto err;
1454 }
1455 req = embedded_payload(wrb);
1456
106df1e3 1457 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1458 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1459 req->id = cpu_to_le16(q->id);
1460
1461 status = be_mcc_notify_wait(adapter);
aa790db9 1462 q->created = false;
482c9e79
SP		 1463
1464err:
1465 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1466 return status;
1467}
1468
b31c50a7 1469/* Create an rx filtering policy configuration on an i/f
bea50988 1470 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1471 */
73d540f2 1472int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1473 u32 *if_handle, u32 domain)
6b7c5b94 1474{
bea50988 1475 struct be_mcc_wrb wrb = {0};
b31c50a7 1476 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1477 int status;
1478
bea50988 1479 req = embedded_payload(&wrb);
106df1e3 1480 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1481 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1482 sizeof(*req), &wrb, NULL);
ba343c77 1483 req->hdr.domain = domain;
73d540f2
SP		 1484 req->capability_flags = cpu_to_le32(cap_flags);
1485 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1486 req->pmac_invalid = true;
6b7c5b94 1487
bea50988 1488 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1489 if (!status) {
bea50988 1490 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1491
6b7c5b94 1492 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1493
1494 /* Hack to retrieve VF's pmac-id on BE3 */
18c57c74 1495 if (BE3_chip(adapter) && be_virtfn(adapter))
b5bb9776 1496 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1497 }
6b7c5b94
SP		 1498 return status;
1499}
1500
f9449ab7 1501/* Uses MCCQ */
30128031 1502int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1503{
b31c50a7
SP		 1504 struct be_mcc_wrb *wrb;
1505 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1506 int status;
1507
30128031 1508 if (interface_id == -1)
f9449ab7 1509 return 0;
b31c50a7 1510
f9449ab7
SP		 1511 spin_lock_bh(&adapter->mcc_lock);
1512
1513 wrb = wrb_from_mccq(adapter);
1514 if (!wrb) {
1515 status = -EBUSY;
1516 goto err;
1517 }
b31c50a7 1518 req = embedded_payload(wrb);
6b7c5b94 1519
106df1e3 1520 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1521 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1522 sizeof(*req), wrb, NULL);
658681f7 1523 req->hdr.domain = domain;
6b7c5b94 1524 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1525
f9449ab7
SP		 1526 status = be_mcc_notify_wait(adapter);
1527err:
1528 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1529 return status;
1530}
1531
1532/* Get stats is a non embedded command: the request is not embedded inside
1533 * WRB but is a separate dma memory block
b31c50a7 1534 * Uses asynchronous MCC
6b7c5b94 1535 */
8788fdc2 1536int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1537{
b31c50a7 1538 struct be_mcc_wrb *wrb;
89a88ab8 1539 struct be_cmd_req_hdr *hdr;
713d0394 1540 int status = 0;
6b7c5b94 1541
b31c50a7 1542 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1543
b31c50a7 1544 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1545 if (!wrb) {
1546 status = -EBUSY;
1547 goto err;
1548 }
89a88ab8 1549 hdr = nonemb_cmd->va;
6b7c5b94 1550
106df1e3 1551 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1552 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1553 nonemb_cmd);
89a88ab8 1554
ca34fe38 1555 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1556 if (BE2_chip(adapter))
1557 hdr->version = 0;
1558 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1559 hdr->version = 1;
61000861
AK		 1560 else
1561 hdr->version = 2;
89a88ab8 1562
efaa408e
SR		 1563 status = be_mcc_notify(adapter);
1564 if (status)
1565 goto err;
1566
b2aebe6d 1567 adapter->stats_cmd_sent = true;
6b7c5b94 1568
713d0394 1569err:
b31c50a7 1570 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1571 return status;
6b7c5b94
SP		 1572}
1573
005d5696
SX		 1574/* Lancer Stats */
1575int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1576 struct be_dma_mem *nonemb_cmd)
005d5696 1577{
005d5696
SX		 1578 struct be_mcc_wrb *wrb;
1579 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1580 int status = 0;
1581
f25b119c
PR		 1582 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1583 CMD_SUBSYSTEM_ETH))
1584 return -EPERM;
1585
005d5696
SX		 1586 spin_lock_bh(&adapter->mcc_lock);
1587
1588 wrb = wrb_from_mccq(adapter);
1589 if (!wrb) {
1590 status = -EBUSY;
1591 goto err;
1592 }
1593 req = nonemb_cmd->va;
005d5696 1594
106df1e3 1595 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1596 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1597 wrb, nonemb_cmd);
005d5696 1598
d51ebd33 1599 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1600 req->cmd_params.params.reset_stats = 0;
1601
efaa408e
SR		 1602 status = be_mcc_notify(adapter);
1603 if (status)
1604 goto err;
1605
005d5696
SX		 1606 adapter->stats_cmd_sent = true;
1607
1608err:
1609 spin_unlock_bh(&adapter->mcc_lock);
1610 return status;
1611}
1612
323ff71e
SP		 1613static int be_mac_to_link_speed(int mac_speed)
1614{
1615 switch (mac_speed) {
1616 case PHY_LINK_SPEED_ZERO:
1617 return 0;
1618 case PHY_LINK_SPEED_10MBPS:
1619 return 10;
1620 case PHY_LINK_SPEED_100MBPS:
1621 return 100;
1622 case PHY_LINK_SPEED_1GBPS:
1623 return 1000;
1624 case PHY_LINK_SPEED_10GBPS:
1625 return 10000;
b971f847
VV		 1626 case PHY_LINK_SPEED_20GBPS:
1627 return 20000;
1628 case PHY_LINK_SPEED_25GBPS:
1629 return 25000;
1630 case PHY_LINK_SPEED_40GBPS:
1631 return 40000;
323ff71e
SP		 1632 }
1633 return 0;
1634}
1635
1636/* Uses synchronous mcc
1637 * Returns link_speed in Mbps
1638 */
1639int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1640 u8 *link_status, u32 dom)
6b7c5b94 1641{
b31c50a7
SP		 1642 struct be_mcc_wrb *wrb;
1643 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1644 int status;
1645
b31c50a7
SP		 1646 spin_lock_bh(&adapter->mcc_lock);
1647
b236916a
AK		 1648 if (link_status)
1649 *link_status = LINK_DOWN;
1650
b31c50a7 1651 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1652 if (!wrb) {
1653 status = -EBUSY;
1654 goto err;
1655 }
b31c50a7 1656 req = embedded_payload(wrb);
a8f447bd 1657
57cd80d4 1658 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1659 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1660 sizeof(*req), wrb, NULL);
57cd80d4 1661
ca34fe38
SP		 1662 /* version 1 of the cmd is not supported only by BE2 */
1663 if (!BE2_chip(adapter))
daad6167
PR		 1664 req->hdr.version = 1;
1665
57cd80d4 1666 req->hdr.domain = dom;
6b7c5b94 1667
b31c50a7 1668 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1669 if (!status) {
1670 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1671
323ff71e
SP		 1672 if (link_speed) {
1673 *link_speed = resp->link_speed ?
1674 le16_to_cpu(resp->link_speed) * 10 :
1675 be_mac_to_link_speed(resp->mac_speed);
1676
1677 if (!resp->logical_link_status)
1678 *link_speed = 0;
0388f251 1679 }
b236916a
AK		 1680 if (link_status)
1681 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1682 }
1683
713d0394 1684err:
b31c50a7 1685 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1686 return status;
1687}
1688
609ff3bb
AK		 1689/* Uses synchronous mcc */
1690int be_cmd_get_die_temperature(struct be_adapter *adapter)
1691{
1692 struct be_mcc_wrb *wrb;
1693 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1694 int status = 0;
609ff3bb
AK		 1695
1696 spin_lock_bh(&adapter->mcc_lock);
1697
1698 wrb = wrb_from_mccq(adapter);
1699 if (!wrb) {
1700 status = -EBUSY;
1701 goto err;
1702 }
1703 req = embedded_payload(wrb);
1704
106df1e3 1705 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1706 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1707 sizeof(*req), wrb, NULL);
609ff3bb 1708
efaa408e 1709 status = be_mcc_notify(adapter);
609ff3bb
AK		 1710err:
1711 spin_unlock_bh(&adapter->mcc_lock);
1712 return status;
1713}
1714
311fddc7
SK		 1715/* Uses synchronous mcc */
1716int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1717{
1718 struct be_mcc_wrb *wrb;
1719 struct be_cmd_req_get_fat *req;
1720 int status;
1721
1722 spin_lock_bh(&adapter->mcc_lock);
1723
1724 wrb = wrb_from_mccq(adapter);
1725 if (!wrb) {
1726 status = -EBUSY;
1727 goto err;
1728 }
1729 req = embedded_payload(wrb);
1730
106df1e3 1731 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1732 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1733 NULL);
311fddc7
SK		 1734 req->fat_operation = cpu_to_le32(QUERY_FAT);
1735 status = be_mcc_notify_wait(adapter);
1736 if (!status) {
1737 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
03d28ffe 1738
311fddc7 1739 if (log_size && resp->log_size)
fe2a70ee
SK		 1740 *log_size = le32_to_cpu(resp->log_size) -
1741 sizeof(u32);
311fddc7
SK		 1742 }
1743err:
1744 spin_unlock_bh(&adapter->mcc_lock);
1745 return status;
1746}
1747
c5f156de 1748int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1749{
1750 struct be_dma_mem get_fat_cmd;
1751 struct be_mcc_wrb *wrb;
1752 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1753 u32 offset = 0, total_size, buf_size,
1754 log_offset = sizeof(u32), payload_len;
c5f156de 1755 int status = 0;
311fddc7
SK		 1756
1757 if (buf_len == 0)
c5f156de 1758 return -EIO;
311fddc7
SK		 1759
1760 total_size = buf_len;
1761
fe2a70ee 1762 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
e51000db
SB		 1763 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1764 get_fat_cmd.size,
1765 &get_fat_cmd.dma, GFP_ATOMIC);
fe2a70ee 1766 if (!get_fat_cmd.va) {
fe2a70ee 1767 dev_err(&adapter->pdev->dev,
cd3307aa 1768 "Memory allocation failure while reading FAT data\n");
c5f156de 1769 return -ENOMEM;
fe2a70ee
SK		 1770 }
1771
311fddc7
SK		 1772 spin_lock_bh(&adapter->mcc_lock);
1773
311fddc7
SK		 1774 while (total_size) {
1775 buf_size = min(total_size, (u32)60*1024);
1776 total_size -= buf_size;
1777
fe2a70ee
SK		 1778 wrb = wrb_from_mccq(adapter);
1779 if (!wrb) {
1780 status = -EBUSY;
311fddc7
SK		 1781 goto err;
1782 }
1783 req = get_fat_cmd.va;
311fddc7 1784
fe2a70ee 1785 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1786 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1787 OPCODE_COMMON_MANAGE_FAT, payload_len,
1788 wrb, &get_fat_cmd);
311fddc7
SK		 1789
1790 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1791 req->read_log_offset = cpu_to_le32(log_offset);
1792 req->read_log_length = cpu_to_le32(buf_size);
1793 req->data_buffer_size = cpu_to_le32(buf_size);
1794
1795 status = be_mcc_notify_wait(adapter);
1796 if (!status) {
1797 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1798
311fddc7 1799 memcpy(buf + offset,
a2cc4e0b
SP		 1800 resp->data_buffer,
1801 le32_to_cpu(resp->read_log_length));
fe2a70ee 1802 } else {
311fddc7 1803 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1804 goto err;
1805 }
311fddc7
SK		 1806 offset += buf_size;
1807 log_offset += buf_size;
1808 }
1809err:
e51000db
SB		 1810 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1811 get_fat_cmd.va, get_fat_cmd.dma);
311fddc7 1812 spin_unlock_bh(&adapter->mcc_lock);
c5f156de 1813 return status;
311fddc7
SK		 1814}
1815
04b71175 1816/* Uses synchronous mcc */
e97e3cda 1817int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1818{
b31c50a7
SP		 1819 struct be_mcc_wrb *wrb;
1820 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1821 int status;
1822
04b71175 1823 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1824
04b71175
SP		 1825 wrb = wrb_from_mccq(adapter);
1826 if (!wrb) {
1827 status = -EBUSY;
1828 goto err;
1829 }
6b7c5b94 1830
04b71175 1831 req = embedded_payload(wrb);
6b7c5b94 1832
106df1e3 1833 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1834 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1835 NULL);
04b71175 1836 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1837 if (!status) {
1838 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1839
242eb470
VV		 1840 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1841 sizeof(adapter->fw_ver));
1842 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1843 sizeof(adapter->fw_on_flash));
6b7c5b94 1844 }
04b71175
SP		 1845err:
1846 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1847 return status;
1848}
1849
b31c50a7
SP		 1850/* set the EQ delay interval of an EQ to specified value
1851 * Uses async mcc
1852 */
b502ae8d
KA		 1853static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1854 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1855{
b31c50a7
SP		 1856 struct be_mcc_wrb *wrb;
1857 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1858 int status = 0, i;
6b7c5b94 1859
b31c50a7
SP		 1860 spin_lock_bh(&adapter->mcc_lock);
1861
1862 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1863 if (!wrb) {
1864 status = -EBUSY;
1865 goto err;
1866 }
b31c50a7 1867 req = embedded_payload(wrb);
6b7c5b94 1868
106df1e3 1869 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1870 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1871 NULL);
6b7c5b94 1872
2632bafd
SP		 1873 req->num_eq = cpu_to_le32(num);
1874 for (i = 0; i < num; i++) {
1875 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1876 req->set_eqd[i].phase = 0;
1877 req->set_eqd[i].delay_multiplier =
1878 cpu_to_le32(set_eqd[i].delay_multiplier);
1879 }
6b7c5b94 1880
efaa408e 1881 status = be_mcc_notify(adapter);
713d0394 1882err:
b31c50a7 1883 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1884 return status;
6b7c5b94
SP		 1885}
1886
93676703
KA		 1887int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1888 int num)
1889{
1890 int num_eqs, i = 0;
1891
c8ba4ad0
SR		 1892 while (num) {
1893 num_eqs = min(num, 8);
1894 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1895 i += num_eqs;
1896 num -= num_eqs;
93676703
KA		 1897 }
1898
1899 return 0;
1900}
1901
b31c50a7 1902/* Uses sycnhronous mcc */
8788fdc2 1903int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 1904 u32 num, u32 domain)
6b7c5b94 1905{
b31c50a7
SP		 1906 struct be_mcc_wrb *wrb;
1907 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1908 int status;
1909
b31c50a7
SP		 1910 spin_lock_bh(&adapter->mcc_lock);
1911
1912 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1913 if (!wrb) {
1914 status = -EBUSY;
1915 goto err;
1916 }
b31c50a7 1917 req = embedded_payload(wrb);
6b7c5b94 1918
106df1e3 1919 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1920 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1921 wrb, NULL);
435452aa 1922 req->hdr.domain = domain;
6b7c5b94
SP		 1923
1924 req->interface_id = if_id;
012bd387 1925 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1926 req->num_vlan = num;
4d567d97
KA		 1927 memcpy(req->normal_vlan, vtag_array,
1928 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1929
b31c50a7 1930 status = be_mcc_notify_wait(adapter);
713d0394 1931err:
b31c50a7 1932 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1933 return status;
1934}
1935
ac34b743 1936static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1937{
6ac7b687 1938 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1939 struct be_dma_mem *mem = &adapter->rx_filter;
1940 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1941 int status;
6b7c5b94 1942
8788fdc2 1943 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1944
b31c50a7 1945 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1946 if (!wrb) {
1947 status = -EBUSY;
1948 goto err;
1949 }
5b8821b7 1950 memset(req, 0, sizeof(*req));
106df1e3 1951 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1952 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1953 wrb, mem);
6b7c5b94 1954
5b8821b7 1955 req->if_id = cpu_to_le32(adapter->if_handle);
ac34b743
SP		 1956 req->if_flags_mask = cpu_to_le32(flags);
1957 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1958
1959 if (flags & BE_IF_FLAGS_MULTICAST) {
22bedad3 1960 struct netdev_hw_addr *ha;
5b8821b7 1961 int i = 0;
24307eef 1962
1610c79f
PR		 1963 /* Reset mcast promisc mode if already set by setting mask
1964 * and not setting flags field
1965 */
abb93951
PR		 1966 req->if_flags_mask |=
1967 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 1968 be_if_cap_flags(adapter));
016f97b1 1969 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1970 netdev_for_each_mc_addr(ha, adapter->netdev)
1971 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1972 }
1973
b6588879 1974 status = be_mcc_notify_wait(adapter);
713d0394 1975err:
8788fdc2 1976 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1977 return status;
6b7c5b94
SP		 1978}
1979
ac34b743
SP		 1980int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1981{
1982 struct device *dev = &adapter->pdev->dev;
1983
1984 if ((flags & be_if_cap_flags(adapter)) != flags) {
1985 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1986 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1987 be_if_cap_flags(adapter));
1988 }
1989 flags &= be_if_cap_flags(adapter);
196e3735
KA		 1990 if (!flags)
1991 return -ENOTSUPP;
ac34b743
SP		 1992
1993 return __be_cmd_rx_filter(adapter, flags, value);
1994}
1995
b31c50a7 1996/* Uses synchrounous mcc */
8788fdc2 1997int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1998{
b31c50a7
SP		 1999 struct be_mcc_wrb *wrb;
2000 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 2001 int status;
2002
f25b119c
PR		 2003 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2004 CMD_SUBSYSTEM_COMMON))
2005 return -EPERM;
2006
b31c50a7 2007 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2008
b31c50a7 2009 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2010 if (!wrb) {
2011 status = -EBUSY;
2012 goto err;
2013 }
b31c50a7 2014 req = embedded_payload(wrb);
6b7c5b94 2015
106df1e3 2016 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2017 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2018 wrb, NULL);
6b7c5b94 2019
b29812c1 2020 req->hdr.version = 1;
6b7c5b94
SP		 2021 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2022 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2023
b31c50a7 2024 status = be_mcc_notify_wait(adapter);
6b7c5b94 2025
713d0394 2026err:
b31c50a7 2027 spin_unlock_bh(&adapter->mcc_lock);
b29812c1
SR		 2028
2029 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2030 return -EOPNOTSUPP;
2031
6b7c5b94
SP		 2032 return status;
2033}
2034
b31c50a7 2035/* Uses sycn mcc */
8788fdc2 2036int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 2037{
b31c50a7
SP		 2038 struct be_mcc_wrb *wrb;
2039 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 2040 int status;
2041
f25b119c
PR		 2042 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2043 CMD_SUBSYSTEM_COMMON))
2044 return -EPERM;
2045
b31c50a7 2046 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 2047
b31c50a7 2048 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2049 if (!wrb) {
2050 status = -EBUSY;
2051 goto err;
2052 }
b31c50a7 2053 req = embedded_payload(wrb);
6b7c5b94 2054
106df1e3 2055 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2056 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2057 wrb, NULL);
6b7c5b94 2058
b31c50a7 2059 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2060 if (!status) {
2061 struct be_cmd_resp_get_flow_control *resp =
2062 embedded_payload(wrb);
03d28ffe 2063
6b7c5b94
SP		 2064 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2065 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2066 }
2067
713d0394 2068err:
b31c50a7 2069 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 2070 return status;
2071}
2072
b31c50a7 2073/* Uses mbox */
e97e3cda 2074int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2075{
b31c50a7
SP		 2076 struct be_mcc_wrb *wrb;
2077 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2078 int status;
2079
2984961c
IV		 2080 if (mutex_lock_interruptible(&adapter->mbox_lock))
2081 return -1;
6b7c5b94 2082
b31c50a7
SP		 2083 wrb = wrb_from_mbox(adapter);
2084 req = embedded_payload(wrb);
6b7c5b94 2085
106df1e3 2086 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2087 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2088 sizeof(*req), wrb, NULL);
6b7c5b94 2089
b31c50a7 2090 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2091 if (!status) {
2092 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2093
e97e3cda
KA		 2094 adapter->port_num = le32_to_cpu(resp->phys_port);
2095 adapter->function_mode = le32_to_cpu(resp->function_mode);
2096 adapter->function_caps = le32_to_cpu(resp->function_caps);
2097 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2098 dev_info(&adapter->pdev->dev,
2099 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2100 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2101 }
2102
2984961c 2103 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2104 return status;
2105}
14074eab 2106
b31c50a7 2107/* Uses mbox */
14074eab 2108int be_cmd_reset_function(struct be_adapter *adapter)
2109{
b31c50a7
SP		 2110 struct be_mcc_wrb *wrb;
2111 struct be_cmd_req_hdr *req;
14074eab 2112 int status;
2113
bf99e50d 2114 if (lancer_chip(adapter)) {
9fa465c0
SP		 2115 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2116 adapter->db + SLIPORT_CONTROL_OFFSET);
bf99e50d 2117 status = lancer_wait_ready(adapter);
9fa465c0 2118 if (status)
bf99e50d
PR		 2119 dev_err(&adapter->pdev->dev,
2120 "Adapter in non recoverable error\n");
bf99e50d
PR		 2121 return status;
2122 }
2123
2984961c
IV		 2124 if (mutex_lock_interruptible(&adapter->mbox_lock))
2125 return -1;
14074eab 2126
b31c50a7
SP		 2127 wrb = wrb_from_mbox(adapter);
2128 req = embedded_payload(wrb);
14074eab 2129
106df1e3 2130 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2131 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2132 NULL);
14074eab 2133
b31c50a7 2134 status = be_mbox_notify_wait(adapter);
14074eab 2135
2984961c 2136 mutex_unlock(&adapter->mbox_lock);
14074eab 2137 return status;
2138}
84517482 2139
594ad54a 2140int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2141 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2142{
2143 struct be_mcc_wrb *wrb;
2144 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2145 int status;
2146
da1388d6
VV		 2147 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2148 return 0;
2149
b51aa367 2150 spin_lock_bh(&adapter->mcc_lock);
3abcdeda 2151
b51aa367
KA		 2152 wrb = wrb_from_mccq(adapter);
2153 if (!wrb) {
2154 status = -EBUSY;
2155 goto err;
2156 }
3abcdeda
SP		 2157 req = embedded_payload(wrb);
2158
106df1e3 2159 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2160 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2161
2162 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2163 req->enable_rss = cpu_to_le16(rss_hash_opts);
2164 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2165
b51aa367 2166 if (!BEx_chip(adapter))
d3bd3a5e 2167 req->hdr.version = 1;
d3bd3a5e 2168
3abcdeda 2169 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2170 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2171 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2172
b51aa367
KA		 2173 status = be_mcc_notify_wait(adapter);
2174err:
2175 spin_unlock_bh(&adapter->mcc_lock);
3abcdeda
SP		 2176 return status;
2177}
2178
fad9ab2c
SB		 2179/* Uses sync mcc */
2180int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2181 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2182{
2183 struct be_mcc_wrb *wrb;
2184 struct be_cmd_req_enable_disable_beacon *req;
2185 int status;
2186
2187 spin_lock_bh(&adapter->mcc_lock);
2188
2189 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2190 if (!wrb) {
2191 status = -EBUSY;
2192 goto err;
2193 }
fad9ab2c
SB		 2194 req = embedded_payload(wrb);
2195
106df1e3 2196 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2197 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2198 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2199
2200 req->port_num = port_num;
2201 req->beacon_state = state;
2202 req->beacon_duration = bcn;
2203 req->status_duration = sts;
2204
2205 status = be_mcc_notify_wait(adapter);
2206
713d0394 2207err:
fad9ab2c
SB		 2208 spin_unlock_bh(&adapter->mcc_lock);
2209 return status;
2210}
2211
2212/* Uses sync mcc */
2213int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2214{
2215 struct be_mcc_wrb *wrb;
2216 struct be_cmd_req_get_beacon_state *req;
2217 int status;
2218
2219 spin_lock_bh(&adapter->mcc_lock);
2220
2221 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2222 if (!wrb) {
2223 status = -EBUSY;
2224 goto err;
2225 }
fad9ab2c
SB		 2226 req = embedded_payload(wrb);
2227
106df1e3 2228 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2229 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2230 wrb, NULL);
fad9ab2c
SB		 2231
2232 req->port_num = port_num;
2233
2234 status = be_mcc_notify_wait(adapter);
2235 if (!status) {
2236 struct be_cmd_resp_get_beacon_state *resp =
2237 embedded_payload(wrb);
03d28ffe 2238
fad9ab2c
SB		 2239 *state = resp->beacon_state;
2240 }
2241
713d0394 2242err:
fad9ab2c
SB		 2243 spin_unlock_bh(&adapter->mcc_lock);
2244 return status;
2245}
2246
e36edd9d
ML		 2247/* Uses sync mcc */
2248int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2249 u8 page_num, u8 *data)
2250{
2251 struct be_dma_mem cmd;
2252 struct be_mcc_wrb *wrb;
2253 struct be_cmd_req_port_type *req;
2254 int status;
2255
2256 if (page_num > TR_PAGE_A2)
2257 return -EINVAL;
2258
2259 cmd.size = sizeof(struct be_cmd_resp_port_type);
e51000db
SB		 2260 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2261 GFP_ATOMIC);
e36edd9d
ML		 2262 if (!cmd.va) {
2263 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2264 return -ENOMEM;
2265 }
e36edd9d
ML		 2266
2267 spin_lock_bh(&adapter->mcc_lock);
2268
2269 wrb = wrb_from_mccq(adapter);
2270 if (!wrb) {
2271 status = -EBUSY;
2272 goto err;
2273 }
2274 req = cmd.va;
2275
2276 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2277 OPCODE_COMMON_READ_TRANSRECV_DATA,
2278 cmd.size, wrb, &cmd);
2279
2280 req->port = cpu_to_le32(adapter->hba_port_num);
2281 req->page_num = cpu_to_le32(page_num);
2282 status = be_mcc_notify_wait(adapter);
2283 if (!status) {
2284 struct be_cmd_resp_port_type *resp = cmd.va;
2285
2286 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2287 }
2288err:
2289 spin_unlock_bh(&adapter->mcc_lock);
e51000db 2290 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
e36edd9d
ML		 2291 return status;
2292}
2293
a23113b5
SR		 2294static int lancer_cmd_write_object(struct be_adapter *adapter,
2295 struct be_dma_mem *cmd, u32 data_size,
2296 u32 data_offset, const char *obj_name,
2297 u32 *data_written, u8 *change_status,
2298 u8 *addn_status)
485bf569
SN		 2299{
2300 struct be_mcc_wrb *wrb;
2301 struct lancer_cmd_req_write_object *req;
2302 struct lancer_cmd_resp_write_object *resp;
2303 void *ctxt = NULL;
2304 int status;
2305
2306 spin_lock_bh(&adapter->mcc_lock);
2307 adapter->flash_status = 0;
2308
2309 wrb = wrb_from_mccq(adapter);
2310 if (!wrb) {
2311 status = -EBUSY;
2312 goto err_unlock;
2313 }
2314
2315 req = embedded_payload(wrb);
2316
106df1e3 2317 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2318 OPCODE_COMMON_WRITE_OBJECT,
2319 sizeof(struct lancer_cmd_req_write_object), wrb,
2320 NULL);
485bf569
SN		 2321
2322 ctxt = &req->context;
2323 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2324 write_length, ctxt, data_size);
485bf569
SN		 2325
2326 if (data_size == 0)
2327 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2328 eof, ctxt, 1);
485bf569
SN		 2329 else
2330 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2331 eof, ctxt, 0);
485bf569
SN		 2332
2333 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2334 req->write_offset = cpu_to_le32(data_offset);
242eb470 2335 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2336 req->descriptor_count = cpu_to_le32(1);
2337 req->buf_len = cpu_to_le32(data_size);
2338 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2339 sizeof(struct lancer_cmd_req_write_object))
2340 & 0xFFFFFFFF);
485bf569
SN		 2341 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2342 sizeof(struct lancer_cmd_req_write_object)));
2343
efaa408e
SR		 2344 status = be_mcc_notify(adapter);
2345 if (status)
2346 goto err_unlock;
2347
485bf569
SN		 2348 spin_unlock_bh(&adapter->mcc_lock);
2349
5eeff635 2350 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2351 msecs_to_jiffies(60000)))
fd45160c 2352 status = -ETIMEDOUT;
485bf569
SN		 2353 else
2354 status = adapter->flash_status;
2355
2356 resp = embedded_payload(wrb);
f67ef7ba 2357 if (!status) {
485bf569 2358 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2359 *change_status = resp->change_status;
2360 } else {
485bf569 2361 *addn_status = resp->additional_status;
f67ef7ba 2362 }
485bf569
SN		 2363
2364 return status;
2365
2366err_unlock:
2367 spin_unlock_bh(&adapter->mcc_lock);
2368 return status;
2369}
2370
6809cee0
RN		 2371int be_cmd_query_cable_type(struct be_adapter *adapter)
2372{
2373 u8 page_data[PAGE_DATA_LEN];
2374 int status;
2375
2376 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2377 page_data);
2378 if (!status) {
2379 switch (adapter->phy.interface_type) {
2380 case PHY_TYPE_QSFP:
2381 adapter->phy.cable_type =
2382 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2383 break;
2384 case PHY_TYPE_SFP_PLUS_10GB:
2385 adapter->phy.cable_type =
2386 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2387 break;
2388 default:
2389 adapter->phy.cable_type = 0;
2390 break;
2391 }
2392 }
2393 return status;
2394}
2395
21252377
VV		 2396int be_cmd_query_sfp_info(struct be_adapter *adapter)
2397{
2398 u8 page_data[PAGE_DATA_LEN];
2399 int status;
2400
2401 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2402 page_data);
2403 if (!status) {
2404 strlcpy(adapter->phy.vendor_name, page_data +
2405 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2406 strlcpy(adapter->phy.vendor_pn,
2407 page_data + SFP_VENDOR_PN_OFFSET,
2408 SFP_VENDOR_NAME_LEN - 1);
2409 }
2410
2411 return status;
2412}
2413
a23113b5
SR		 2414static int lancer_cmd_delete_object(struct be_adapter *adapter,
2415 const char *obj_name)
f0613380
KA		 2416{
2417 struct lancer_cmd_req_delete_object *req;
2418 struct be_mcc_wrb *wrb;
2419 int status;
2420
2421 spin_lock_bh(&adapter->mcc_lock);
2422
2423 wrb = wrb_from_mccq(adapter);
2424 if (!wrb) {
2425 status = -EBUSY;
2426 goto err;
2427 }
2428
2429 req = embedded_payload(wrb);
2430
2431 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2432 OPCODE_COMMON_DELETE_OBJECT,
2433 sizeof(*req), wrb, NULL);
2434
242eb470 2435 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2436
2437 status = be_mcc_notify_wait(adapter);
2438err:
2439 spin_unlock_bh(&adapter->mcc_lock);
2440 return status;
2441}
2442
de49bd5a 2443int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2444 u32 data_size, u32 data_offset, const char *obj_name,
2445 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2446{
2447 struct be_mcc_wrb *wrb;
2448 struct lancer_cmd_req_read_object *req;
2449 struct lancer_cmd_resp_read_object *resp;
2450 int status;
2451
2452 spin_lock_bh(&adapter->mcc_lock);
2453
2454 wrb = wrb_from_mccq(adapter);
2455 if (!wrb) {
2456 status = -EBUSY;
2457 goto err_unlock;
2458 }
2459
2460 req = embedded_payload(wrb);
2461
2462 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2463 OPCODE_COMMON_READ_OBJECT,
2464 sizeof(struct lancer_cmd_req_read_object), wrb,
2465 NULL);
de49bd5a
PR		 2466
2467 req->desired_read_len = cpu_to_le32(data_size);
2468 req->read_offset = cpu_to_le32(data_offset);
2469 strcpy(req->object_name, obj_name);
2470 req->descriptor_count = cpu_to_le32(1);
2471 req->buf_len = cpu_to_le32(data_size);
2472 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2473 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2474
2475 status = be_mcc_notify_wait(adapter);
2476
2477 resp = embedded_payload(wrb);
2478 if (!status) {
2479 *data_read = le32_to_cpu(resp->actual_read_len);
2480 *eof = le32_to_cpu(resp->eof);
2481 } else {
2482 *addn_status = resp->additional_status;
2483 }
2484
2485err_unlock:
2486 spin_unlock_bh(&adapter->mcc_lock);
2487 return status;
2488}
2489
a23113b5
SR		 2490static int be_cmd_write_flashrom(struct be_adapter *adapter,
2491 struct be_dma_mem *cmd, u32 flash_type,
2492 u32 flash_opcode, u32 img_offset, u32 buf_size)
84517482 2493{
b31c50a7 2494 struct be_mcc_wrb *wrb;
3f0d4560 2495 struct be_cmd_write_flashrom *req;
84517482
AK		 2496 int status;
2497
b31c50a7 2498 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2499 adapter->flash_status = 0;
b31c50a7
SP		 2500
2501 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2502 if (!wrb) {
2503 status = -EBUSY;
2892d9c2 2504 goto err_unlock;
713d0394
SP		 2505 }
2506 req = cmd->va;
84517482 2507
106df1e3 2508 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2509 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2510 cmd);
84517482
AK		 2511
2512 req->params.op_type = cpu_to_le32(flash_type);
70a7b525
VV		 2513 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2514 req->params.offset = cpu_to_le32(img_offset);
2515
84517482
AK		 2516 req->params.op_code = cpu_to_le32(flash_opcode);
2517 req->params.data_buf_size = cpu_to_le32(buf_size);
2518
efaa408e
SR		 2519 status = be_mcc_notify(adapter);
2520 if (status)
2521 goto err_unlock;
2522
dd131e76
SB		 2523 spin_unlock_bh(&adapter->mcc_lock);
2524
5eeff635
SR		 2525 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2526 msecs_to_jiffies(40000)))
fd45160c 2527 status = -ETIMEDOUT;
dd131e76
SB		 2528 else
2529 status = adapter->flash_status;
84517482 2530
2892d9c2
DC		 2531 return status;
2532
2533err_unlock:
2534 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2535 return status;
2536}
fa9a6fed 2537
a23113b5
SR		 2538static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2539 u16 img_optype, u32 img_offset, u32 crc_offset)
fa9a6fed 2540{
be716446 2541 struct be_cmd_read_flash_crc *req;
70a7b525 2542 struct be_mcc_wrb *wrb;
fa9a6fed
SB		 2543 int status;
2544
2545 spin_lock_bh(&adapter->mcc_lock);
2546
2547 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2548 if (!wrb) {
2549 status = -EBUSY;
2550 goto err;
2551 }
fa9a6fed
SB		 2552 req = embedded_payload(wrb);
2553
106df1e3 2554 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2555 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2556 wrb, NULL);
fa9a6fed 2557
70a7b525
VV		 2558 req->params.op_type = cpu_to_le32(img_optype);
2559 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2560 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2561 else
2562 req->params.offset = cpu_to_le32(crc_offset);
2563
fa9a6fed 2564 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710 2565 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2566
2567 status = be_mcc_notify_wait(adapter);
2568 if (!status)
be716446 2569 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2570
713d0394 2571err:
fa9a6fed
SB		 2572 spin_unlock_bh(&adapter->mcc_lock);
2573 return status;
2574}
71d8d1b5 2575
a23113b5
SR		 2576static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2577
2578static bool phy_flashing_required(struct be_adapter *adapter)
2579{
2580 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2581 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2582}
2583
2584static bool is_comp_in_ufi(struct be_adapter *adapter,
2585 struct flash_section_info *fsec, int type)
2586{
2587 int i = 0, img_type = 0;
2588 struct flash_section_info_g2 *fsec_g2 = NULL;
2589
2590 if (BE2_chip(adapter))
2591 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2592
2593 for (i = 0; i < MAX_FLASH_COMP; i++) {
2594 if (fsec_g2)
2595 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2596 else
2597 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2598
2599 if (img_type == type)
2600 return true;
2601 }
2602 return false;
2603}
2604
2605static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2606 int header_size,
2607 const struct firmware *fw)
2608{
2609 struct flash_section_info *fsec = NULL;
2610 const u8 *p = fw->data;
2611
2612 p += header_size;
2613 while (p < (fw->data + fw->size)) {
2614 fsec = (struct flash_section_info *)p;
2615 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2616 return fsec;
2617 p += 32;
2618 }
2619 return NULL;
2620}
2621
2622static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2623 u32 img_offset, u32 img_size, int hdr_size,
2624 u16 img_optype, bool *crc_match)
2625{
2626 u32 crc_offset;
2627 int status;
2628 u8 crc[4];
2629
2630 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2631 img_size - 4);
2632 if (status)
2633 return status;
2634
2635 crc_offset = hdr_size + img_offset + img_size - 4;
2636
2637 /* Skip flashing, if crc of flashed region matches */
2638 if (!memcmp(crc, p + crc_offset, 4))
2639 *crc_match = true;
2640 else
2641 *crc_match = false;
2642
2643 return status;
2644}
2645
2646static int be_flash(struct be_adapter *adapter, const u8 *img,
2647 struct be_dma_mem *flash_cmd, int optype, int img_size,
2648 u32 img_offset)
2649{
2650 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2651 struct be_cmd_write_flashrom *req = flash_cmd->va;
2652 int status;
2653
2654 while (total_bytes) {
2655 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2656
2657 total_bytes -= num_bytes;
2658
2659 if (!total_bytes) {
2660 if (optype == OPTYPE_PHY_FW)
2661 flash_op = FLASHROM_OPER_PHY_FLASH;
2662 else
2663 flash_op = FLASHROM_OPER_FLASH;
2664 } else {
2665 if (optype == OPTYPE_PHY_FW)
2666 flash_op = FLASHROM_OPER_PHY_SAVE;
2667 else
2668 flash_op = FLASHROM_OPER_SAVE;
2669 }
2670
2671 memcpy(req->data_buf, img, num_bytes);
2672 img += num_bytes;
2673 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2674 flash_op, img_offset +
2675 bytes_sent, num_bytes);
2676 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2677 optype == OPTYPE_PHY_FW)
2678 break;
2679 else if (status)
2680 return status;
2681
2682 bytes_sent += num_bytes;
2683 }
2684 return 0;
2685}
2686
2687/* For BE2, BE3 and BE3-R */
2688static int be_flash_BEx(struct be_adapter *adapter,
2689 const struct firmware *fw,
2690 struct be_dma_mem *flash_cmd, int num_of_images)
2691{
2692 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2693 struct device *dev = &adapter->pdev->dev;
2694 struct flash_section_info *fsec = NULL;
2695 int status, i, filehdr_size, num_comp;
2696 const struct flash_comp *pflashcomp;
2697 bool crc_match;
2698 const u8 *p;
2699
2700 struct flash_comp gen3_flash_types[] = {
2701 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2702 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2703 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2704 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2705 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2706 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2707 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2708 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2709 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2710 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2711 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2712 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2713 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2714 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2715 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2716 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2717 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2718 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2719 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2720 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2721 };
2722
2723 struct flash_comp gen2_flash_types[] = {
2724 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2725 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2726 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2727 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2728 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2729 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2730 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2731 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2732 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2733 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2734 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2735 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2736 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2737 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2738 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2739 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2740 };
2741
2742 if (BE3_chip(adapter)) {
2743 pflashcomp = gen3_flash_types;
2744 filehdr_size = sizeof(struct flash_file_hdr_g3);
2745 num_comp = ARRAY_SIZE(gen3_flash_types);
2746 } else {
2747 pflashcomp = gen2_flash_types;
2748 filehdr_size = sizeof(struct flash_file_hdr_g2);
2749 num_comp = ARRAY_SIZE(gen2_flash_types);
2750 img_hdrs_size = 0;
2751 }
2752
2753 /* Get flash section info*/
2754 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2755 if (!fsec) {
2756 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2757 return -1;
2758 }
2759 for (i = 0; i < num_comp; i++) {
2760 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2761 continue;
2762
2763 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2764 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2765 continue;
2766
2767 if (pflashcomp[i].optype == OPTYPE_PHY_FW &&
2768 !phy_flashing_required(adapter))
2769 continue;
2770
2771 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2772 status = be_check_flash_crc(adapter, fw->data,
2773 pflashcomp[i].offset,
2774 pflashcomp[i].size,
2775 filehdr_size +
2776 img_hdrs_size,
2777 OPTYPE_REDBOOT, &crc_match);
2778 if (status) {
2779 dev_err(dev,
2780 "Could not get CRC for 0x%x region\n",
2781 pflashcomp[i].optype);
2782 continue;
2783 }
2784
2785 if (crc_match)
2786 continue;
2787 }
2788
2789 p = fw->data + filehdr_size + pflashcomp[i].offset +
2790 img_hdrs_size;
2791 if (p + pflashcomp[i].size > fw->data + fw->size)
2792 return -1;
2793
2794 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2795 pflashcomp[i].size, 0);
2796 if (status) {
2797 dev_err(dev, "Flashing section type 0x%x failed\n",
2798 pflashcomp[i].img_type);
2799 return status;
2800 }
2801 }
2802 return 0;
2803}
2804
2805static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2806{
2807 u32 img_type = le32_to_cpu(fsec_entry.type);
2808 u16 img_optype = le16_to_cpu(fsec_entry.optype);
2809
2810 if (img_optype != 0xFFFF)
2811 return img_optype;
2812
2813 switch (img_type) {
2814 case IMAGE_FIRMWARE_ISCSI:
2815 img_optype = OPTYPE_ISCSI_ACTIVE;
2816 break;
2817 case IMAGE_BOOT_CODE:
2818 img_optype = OPTYPE_REDBOOT;
2819 break;
2820 case IMAGE_OPTION_ROM_ISCSI:
2821 img_optype = OPTYPE_BIOS;
2822 break;
2823 case IMAGE_OPTION_ROM_PXE:
2824 img_optype = OPTYPE_PXE_BIOS;
2825 break;
2826 case IMAGE_OPTION_ROM_FCOE:
2827 img_optype = OPTYPE_FCOE_BIOS;
2828 break;
2829 case IMAGE_FIRMWARE_BACKUP_ISCSI:
2830 img_optype = OPTYPE_ISCSI_BACKUP;
2831 break;
2832 case IMAGE_NCSI:
2833 img_optype = OPTYPE_NCSI_FW;
2834 break;
2835 case IMAGE_FLASHISM_JUMPVECTOR:
2836 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2837 break;
2838 case IMAGE_FIRMWARE_PHY:
2839 img_optype = OPTYPE_SH_PHY_FW;
2840 break;
2841 case IMAGE_REDBOOT_DIR:
2842 img_optype = OPTYPE_REDBOOT_DIR;
2843 break;
2844 case IMAGE_REDBOOT_CONFIG:
2845 img_optype = OPTYPE_REDBOOT_CONFIG;
2846 break;
2847 case IMAGE_UFI_DIR:
2848 img_optype = OPTYPE_UFI_DIR;
2849 break;
2850 default:
2851 break;
2852 }
2853
2854 return img_optype;
2855}
2856
2857static int be_flash_skyhawk(struct be_adapter *adapter,
2858 const struct firmware *fw,
2859 struct be_dma_mem *flash_cmd, int num_of_images)
2860{
2861 int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2862 bool crc_match, old_fw_img, flash_offset_support = true;
2863 struct device *dev = &adapter->pdev->dev;
2864 struct flash_section_info *fsec = NULL;
2865 u32 img_offset, img_size, img_type;
2866 u16 img_optype, flash_optype;
2867 int status, i, filehdr_size;
2868 const u8 *p;
2869
2870 filehdr_size = sizeof(struct flash_file_hdr_g3);
2871 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2872 if (!fsec) {
2873 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2874 return -EINVAL;
2875 }
2876
2877retry_flash:
2878 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2879 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2880 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2881 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2882 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2883 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2884
2885 if (img_optype == 0xFFFF)
2886 continue;
2887
2888 if (flash_offset_support)
2889 flash_optype = OPTYPE_OFFSET_SPECIFIED;
2890 else
2891 flash_optype = img_optype;
2892
2893 /* Don't bother verifying CRC if an old FW image is being
2894 * flashed
2895 */
2896 if (old_fw_img)
2897 goto flash;
2898
2899 status = be_check_flash_crc(adapter, fw->data, img_offset,
2900 img_size, filehdr_size +
2901 img_hdrs_size, flash_optype,
2902 &crc_match);
2903 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2904 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2905 /* The current FW image on the card does not support
2906 * OFFSET based flashing. Retry using older mechanism
2907 * of OPTYPE based flashing
2908 */
2909 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2910 flash_offset_support = false;
2911 goto retry_flash;
2912 }
2913
2914 /* The current FW image on the card does not recognize
2915 * the new FLASH op_type. The FW download is partially
2916 * complete. Reboot the server now to enable FW image
2917 * to recognize the new FLASH op_type. To complete the
2918 * remaining process, download the same FW again after
2919 * the reboot.
2920 */
2921 dev_err(dev, "Flash incomplete. Reset the server\n");
2922 dev_err(dev, "Download FW image again after reset\n");
2923 return -EAGAIN;
2924 } else if (status) {
2925 dev_err(dev, "Could not get CRC for 0x%x region\n",
2926 img_optype);
2927 return -EFAULT;
2928 }
2929
2930 if (crc_match)
2931 continue;
2932
2933flash:
2934 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2935 if (p + img_size > fw->data + fw->size)
2936 return -1;
2937
2938 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
2939 img_offset);
2940
2941 /* The current FW image on the card does not support OFFSET
2942 * based flashing. Retry using older mechanism of OPTYPE based
2943 * flashing
2944 */
2945 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
2946 flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2947 flash_offset_support = false;
2948 goto retry_flash;
2949 }
2950
2951 /* For old FW images ignore ILLEGAL_FIELD error or errors on
2952 * UFI_DIR region
2953 */
2954 if (old_fw_img &&
2955 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
2956 (img_optype == OPTYPE_UFI_DIR &&
2957 base_status(status) == MCC_STATUS_FAILED))) {
2958 continue;
2959 } else if (status) {
2960 dev_err(dev, "Flashing section type 0x%x failed\n",
2961 img_type);
2962 return -EFAULT;
2963 }
2964 }
2965 return 0;
2966}
2967
2968int lancer_fw_download(struct be_adapter *adapter,
2969 const struct firmware *fw)
2970{
2971 struct device *dev = &adapter->pdev->dev;
2972 struct be_dma_mem flash_cmd;
2973 const u8 *data_ptr = NULL;
2974 u8 *dest_image_ptr = NULL;
2975 size_t image_size = 0;
2976 u32 chunk_size = 0;
2977 u32 data_written = 0;
2978 u32 offset = 0;
2979 int status = 0;
2980 u8 add_status = 0;
2981 u8 change_status;
2982
2983 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
2984 dev_err(dev, "FW image size should be multiple of 4\n");
2985 return -EINVAL;
2986 }
2987
2988 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
2989 + LANCER_FW_DOWNLOAD_CHUNK;
2990 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
2991 &flash_cmd.dma, GFP_KERNEL);
2992 if (!flash_cmd.va)
2993 return -ENOMEM;
2994
2995 dest_image_ptr = flash_cmd.va +
2996 sizeof(struct lancer_cmd_req_write_object);
2997 image_size = fw->size;
2998 data_ptr = fw->data;
2999
3000 while (image_size) {
3001 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3002
3003 /* Copy the image chunk content. */
3004 memcpy(dest_image_ptr, data_ptr, chunk_size);
3005
3006 status = lancer_cmd_write_object(adapter, &flash_cmd,
3007 chunk_size, offset,
3008 LANCER_FW_DOWNLOAD_LOCATION,
3009 &data_written, &change_status,
3010 &add_status);
3011 if (status)
3012 break;
3013
3014 offset += data_written;
3015 data_ptr += data_written;
3016 image_size -= data_written;
3017 }
3018
3019 if (!status) {
3020 /* Commit the FW written */
3021 status = lancer_cmd_write_object(adapter, &flash_cmd,
3022 0, offset,
3023 LANCER_FW_DOWNLOAD_LOCATION,
3024 &data_written, &change_status,
3025 &add_status);
3026 }
3027
3028 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3029 if (status) {
3030 dev_err(dev, "Firmware load error\n");
3031 return be_cmd_status(status);
3032 }
3033
3034 dev_info(dev, "Firmware flashed successfully\n");
3035
3036 if (change_status == LANCER_FW_RESET_NEEDED) {
3037 dev_info(dev, "Resetting adapter to activate new FW\n");
3038 status = lancer_physdev_ctrl(adapter,
3039 PHYSDEV_CONTROL_FW_RESET_MASK);
3040 if (status) {
3041 dev_err(dev, "Adapter busy, could not reset FW\n");
3042 dev_err(dev, "Reboot server to activate new FW\n");
3043 }
3044 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3045 dev_info(dev, "Reboot server to activate new FW\n");
3046 }
3047
3048 return 0;
3049}
3050
3051/* Check if the flash image file is compatible with the adapter that
3052 * is being flashed.
3053 */
3054static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3055 struct flash_file_hdr_g3 *fhdr)
3056{
3057 if (!fhdr) {
3058 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3059 return false;
3060 }
3061
3062 /* First letter of the build version is used to identify
3063 * which chip this image file is meant for.
3064 */
3065 switch (fhdr->build[0]) {
3066 case BLD_STR_UFI_TYPE_SH:
3067 if (!skyhawk_chip(adapter))
3068 return false;
3069 break;
3070 case BLD_STR_UFI_TYPE_BE3:
3071 if (!BE3_chip(adapter))
3072 return false;
3073 break;
3074 case BLD_STR_UFI_TYPE_BE2:
3075 if (!BE2_chip(adapter))
3076 return false;
3077 break;
3078 default:
3079 return false;
3080 }
3081
3082 /* In BE3 FW images the "asic_type_rev" field doesn't track the
3083 * asic_rev of the chips it is compatible with.
3084 * When asic_type_rev is 0 the image is compatible only with
3085 * pre-BE3-R chips (asic_rev < 0x10)
3086 */
3087 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3088 return adapter->asic_rev < 0x10;
3089 else
3090 return (fhdr->asic_type_rev >= adapter->asic_rev);
3091}
3092
3093int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3094{
3095 struct device *dev = &adapter->pdev->dev;
3096 struct flash_file_hdr_g3 *fhdr3;
3097 struct image_hdr *img_hdr_ptr;
3098 int status = 0, i, num_imgs;
3099 struct be_dma_mem flash_cmd;
3100
3101 fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3102 if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3103 dev_err(dev, "Flash image is not compatible with adapter\n");
3104 return -EINVAL;
3105 }
3106
3107 flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3108 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3109 GFP_KERNEL);
3110 if (!flash_cmd.va)
3111 return -ENOMEM;
3112
3113 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3114 for (i = 0; i < num_imgs; i++) {
3115 img_hdr_ptr = (struct image_hdr *)(fw->data +
3116 (sizeof(struct flash_file_hdr_g3) +
3117 i * sizeof(struct image_hdr)));
3118 if (!BE2_chip(adapter) &&
3119 le32_to_cpu(img_hdr_ptr->imageid) != 1)
3120 continue;
3121
3122 if (skyhawk_chip(adapter))
3123 status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3124 num_imgs);
3125 else
3126 status = be_flash_BEx(adapter, fw, &flash_cmd,
3127 num_imgs);
3128 }
3129
3130 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3131 if (!status)
3132 dev_info(dev, "Firmware flashed successfully\n");
3133
3134 return status;
3135}
3136
c196b02c 3137int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 3138 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 3139{
3140 struct be_mcc_wrb *wrb;
3141 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 3142 int status;
3143
3144 spin_lock_bh(&adapter->mcc_lock);
3145
3146 wrb = wrb_from_mccq(adapter);
3147 if (!wrb) {
3148 status = -EBUSY;
3149 goto err;
3150 }
3151 req = nonemb_cmd->va;
71d8d1b5 3152
106df1e3 3153 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 3154 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3155 wrb, nonemb_cmd);
71d8d1b5
AK		 3156 memcpy(req->magic_mac, mac, ETH_ALEN);
3157
71d8d1b5
AK		 3158 status = be_mcc_notify_wait(adapter);
3159
3160err:
3161 spin_unlock_bh(&adapter->mcc_lock);
3162 return status;
3163}
ff33a6e2 3164
fced9999
SB		 3165int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3166 u8 loopback_type, u8 enable)
3167{
3168 struct be_mcc_wrb *wrb;
3169 struct be_cmd_req_set_lmode *req;
3170 int status;
3171
3172 spin_lock_bh(&adapter->mcc_lock);
3173
3174 wrb = wrb_from_mccq(adapter);
3175 if (!wrb) {
3176 status = -EBUSY;
9c855975 3177 goto err_unlock;
fced9999
SB		 3178 }
3179
3180 req = embedded_payload(wrb);
3181
106df1e3 3182 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3183 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3184 wrb, NULL);
fced9999
SB		 3185
3186 req->src_port = port_num;
3187 req->dest_port = port_num;
3188 req->loopback_type = loopback_type;
3189 req->loopback_state = enable;
3190
9c855975
SR		 3191 status = be_mcc_notify(adapter);
3192 if (status)
3193 goto err_unlock;
3194
3195 spin_unlock_bh(&adapter->mcc_lock);
3196
3197 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3198 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3199 status = -ETIMEDOUT;
3200
3201 return status;
3202
3203err_unlock:
fced9999
SB		 3204 spin_unlock_bh(&adapter->mcc_lock);
3205 return status;
3206}
3207
ff33a6e2 3208int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 3209 u32 loopback_type, u32 pkt_size, u32 num_pkts,
3210 u64 pattern)
ff33a6e2
S		 3211{
3212 struct be_mcc_wrb *wrb;
3213 struct be_cmd_req_loopback_test *req;
5eeff635 3214 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 3215 int status;
3216
3217 spin_lock_bh(&adapter->mcc_lock);
3218
3219 wrb = wrb_from_mccq(adapter);
3220 if (!wrb) {
3221 status = -EBUSY;
3222 goto err;
3223 }
3224
3225 req = embedded_payload(wrb);
3226
106df1e3 3227 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3228 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3229 NULL);
ff33a6e2 3230
5eeff635 3231 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 3232 req->pattern = cpu_to_le64(pattern);
3233 req->src_port = cpu_to_le32(port_num);
3234 req->dest_port = cpu_to_le32(port_num);
3235 req->pkt_size = cpu_to_le32(pkt_size);
3236 req->num_pkts = cpu_to_le32(num_pkts);
3237 req->loopback_type = cpu_to_le32(loopback_type);
3238
efaa408e
SR		 3239 status = be_mcc_notify(adapter);
3240 if (status)
3241 goto err;
5eeff635
SR		 3242
3243 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 3244
5eeff635
SR		 3245 wait_for_completion(&adapter->et_cmd_compl);
3246 resp = embedded_payload(wrb);
3247 status = le32_to_cpu(resp->status);
3248
3249 return status;
ff33a6e2
S		 3250err:
3251 spin_unlock_bh(&adapter->mcc_lock);
3252 return status;
3253}
3254
3255int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 3256 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 3257{
3258 struct be_mcc_wrb *wrb;
3259 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 3260 int status;
3261 int i, j = 0;
3262
3263 spin_lock_bh(&adapter->mcc_lock);
3264
3265 wrb = wrb_from_mccq(adapter);
3266 if (!wrb) {
3267 status = -EBUSY;
3268 goto err;
3269 }
3270 req = cmd->va;
106df1e3 3271 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3272 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3273 cmd);
ff33a6e2
S		 3274
3275 req->pattern = cpu_to_le64(pattern);
3276 req->byte_count = cpu_to_le32(byte_cnt);
3277 for (i = 0; i < byte_cnt; i++) {
3278 req->snd_buff[i] = (u8)(pattern >> (j*8));
3279 j++;
3280 if (j > 7)
3281 j = 0;
3282 }
3283
3284 status = be_mcc_notify_wait(adapter);
3285
3286 if (!status) {
3287 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 3288
ff33a6e2
S		 3289 resp = cmd->va;
3290 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
cd3307aa 3291 resp->snd_err) {
ff33a6e2
S		 3292 status = -1;
3293 }
3294 }
3295
3296err:
3297 spin_unlock_bh(&adapter->mcc_lock);
3298 return status;
3299}
368c0ca2 3300
c196b02c 3301int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 3302 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 3303{
3304 struct be_mcc_wrb *wrb;
3305 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 3306 int status;
3307
3308 spin_lock_bh(&adapter->mcc_lock);
3309
3310 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 3311 if (!wrb) {
3312 status = -EBUSY;
3313 goto err;
3314 }
368c0ca2 3315 req = nonemb_cmd->va;
368c0ca2 3316
106df1e3 3317 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3318 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3319 nonemb_cmd);
368c0ca2
SB		 3320
3321 status = be_mcc_notify_wait(adapter);
3322
e45ff01d 3323err:
368c0ca2
SB		 3324 spin_unlock_bh(&adapter->mcc_lock);
3325 return status;
3326}
ee3cb629 3327
42f11cf2 3328int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 3329{
3330 struct be_mcc_wrb *wrb;
3331 struct be_cmd_req_get_phy_info *req;
306f1348 3332 struct be_dma_mem cmd;
ee3cb629
AK		 3333 int status;
3334
f25b119c
PR		 3335 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3336 CMD_SUBSYSTEM_COMMON))
3337 return -EPERM;
3338
ee3cb629
AK		 3339 spin_lock_bh(&adapter->mcc_lock);
3340
3341 wrb = wrb_from_mccq(adapter);
3342 if (!wrb) {
3343 status = -EBUSY;
3344 goto err;
3345 }
306f1348 3346 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
e51000db
SB		 3347 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3348 GFP_ATOMIC);
306f1348
SP		 3349 if (!cmd.va) {
3350 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3351 status = -ENOMEM;
3352 goto err;
3353 }
ee3cb629 3354
306f1348 3355 req = cmd.va;
ee3cb629 3356
106df1e3 3357 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3358 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3359 wrb, &cmd);
ee3cb629
AK		 3360
3361 status = be_mcc_notify_wait(adapter);
306f1348
SP		 3362 if (!status) {
3363 struct be_phy_info *resp_phy_info =
3364 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 3365
42f11cf2
AK		 3366 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3367 adapter->phy.interface_type =
306f1348 3368 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 3369 adapter->phy.auto_speeds_supported =
3370 le16_to_cpu(resp_phy_info->auto_speeds_supported);
3371 adapter->phy.fixed_speeds_supported =
3372 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3373 adapter->phy.misc_params =
3374 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 3375
3376 if (BE2_chip(adapter)) {
3377 adapter->phy.fixed_speeds_supported =
3378 BE_SUPPORTED_SPEED_10GBPS |
3379 BE_SUPPORTED_SPEED_1GBPS;
3380 }
306f1348 3381 }
e51000db 3382 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
ee3cb629
AK		 3383err:
3384 spin_unlock_bh(&adapter->mcc_lock);
3385 return status;
3386}
e1d18735 3387
bc0ee163 3388static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
e1d18735
AK		 3389{
3390 struct be_mcc_wrb *wrb;
3391 struct be_cmd_req_set_qos *req;
3392 int status;
3393
3394 spin_lock_bh(&adapter->mcc_lock);
3395
3396 wrb = wrb_from_mccq(adapter);
3397 if (!wrb) {
3398 status = -EBUSY;
3399 goto err;
3400 }
3401
3402 req = embedded_payload(wrb);
3403
106df1e3 3404 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 3405 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 3406
3407 req->hdr.domain = domain;
6bff57a7
AK		 3408 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3409 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 3410
3411 status = be_mcc_notify_wait(adapter);
3412
3413err:
3414 spin_unlock_bh(&adapter->mcc_lock);
3415 return status;
3416}
9e1453c5
AK		 3417
3418int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3419{
3420 struct be_mcc_wrb *wrb;
3421 struct be_cmd_req_cntl_attribs *req;
3422 struct be_cmd_resp_cntl_attribs *resp;
a155a5db 3423 int status, i;
9e1453c5
AK		 3424 int payload_len = max(sizeof(*req), sizeof(*resp));
3425 struct mgmt_controller_attrib *attribs;
3426 struct be_dma_mem attribs_cmd;
a155a5db 3427 u32 *serial_num;
9e1453c5 3428
d98ef50f
SR		 3429 if (mutex_lock_interruptible(&adapter->mbox_lock))
3430 return -1;
3431
9e1453c5
AK		 3432 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3433 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
e51000db
SB		 3434 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3435 attribs_cmd.size,
3436 &attribs_cmd.dma, GFP_ATOMIC);
9e1453c5 3437 if (!attribs_cmd.va) {
a2cc4e0b 3438 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3439 status = -ENOMEM;
3440 goto err;
9e1453c5
AK		 3441 }
3442
9e1453c5
AK		 3443 wrb = wrb_from_mbox(adapter);
3444 if (!wrb) {
3445 status = -EBUSY;
3446 goto err;
3447 }
3448 req = attribs_cmd.va;
9e1453c5 3449
106df1e3 3450 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3451 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3452 wrb, &attribs_cmd);
9e1453c5
AK		 3453
3454 status = be_mbox_notify_wait(adapter);
3455 if (!status) {
43d620c8 3456 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5 3457 adapter->hba_port_num = attribs->hba_attribs.phy_port;
72ef3a88 3458 adapter->pci_func_num = attribs->pci_func_num;
a155a5db
SB		 3459 serial_num = attribs->hba_attribs.controller_serial_number;
3460 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3461 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3462 (BIT_MASK(16) - 1);
9e1453c5
AK		 3463 }
3464
3465err:
3466 mutex_unlock(&adapter->mbox_lock);
d98ef50f 3467 if (attribs_cmd.va)
e51000db
SB		 3468 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3469 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 3470 return status;
3471}
2e588f84
SP		 3472
3473/* Uses mbox */
2dc1deb6 3474int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 3475{
3476 struct be_mcc_wrb *wrb;
3477 struct be_cmd_req_set_func_cap *req;
3478 int status;
3479
3480 if (mutex_lock_interruptible(&adapter->mbox_lock))
3481 return -1;
3482
3483 wrb = wrb_from_mbox(adapter);
3484 if (!wrb) {
3485 status = -EBUSY;
3486 goto err;
3487 }
3488
3489 req = embedded_payload(wrb);
3490
106df1e3 3491 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3492 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3493 sizeof(*req), wrb, NULL);
2e588f84
SP		 3494
3495 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3496 CAPABILITY_BE3_NATIVE_ERX_API);
3497 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3498
3499 status = be_mbox_notify_wait(adapter);
3500 if (!status) {
3501 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 3502
2e588f84
SP		 3503 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3504 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 3505 if (!adapter->be3_native)
3506 dev_warn(&adapter->pdev->dev,
3507 "adapter not in advanced mode\n");
2e588f84
SP		 3508 }
3509err:
3510 mutex_unlock(&adapter->mbox_lock);
3511 return status;
3512}
590c391d 3513
f25b119c
PR		 3514/* Get privilege(s) for a function */
3515int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3516 u32 domain)
3517{
3518 struct be_mcc_wrb *wrb;
3519 struct be_cmd_req_get_fn_privileges *req;
3520 int status;
3521
3522 spin_lock_bh(&adapter->mcc_lock);
3523
3524 wrb = wrb_from_mccq(adapter);
3525 if (!wrb) {
3526 status = -EBUSY;
3527 goto err;
3528 }
3529
3530 req = embedded_payload(wrb);
3531
3532 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3533 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3534 wrb, NULL);
3535
3536 req->hdr.domain = domain;
3537
3538 status = be_mcc_notify_wait(adapter);
3539 if (!status) {
3540 struct be_cmd_resp_get_fn_privileges *resp =
3541 embedded_payload(wrb);
03d28ffe 3542
f25b119c 3543 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 3544
3545 /* In UMC mode FW does not return right privileges.
3546 * Override with correct privilege equivalent to PF.
3547 */
3548 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3549 be_physfn(adapter))
3550 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 3551 }
3552
3553err:
3554 spin_unlock_bh(&adapter->mcc_lock);
3555 return status;
3556}
3557
04a06028
SP		 3558/* Set privilege(s) for a function */
3559int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3560 u32 domain)
3561{
3562 struct be_mcc_wrb *wrb;
3563 struct be_cmd_req_set_fn_privileges *req;
3564 int status;
3565
3566 spin_lock_bh(&adapter->mcc_lock);
3567
3568 wrb = wrb_from_mccq(adapter);
3569 if (!wrb) {
3570 status = -EBUSY;
3571 goto err;
3572 }
3573
3574 req = embedded_payload(wrb);
3575 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3576 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3577 wrb, NULL);
3578 req->hdr.domain = domain;
3579 if (lancer_chip(adapter))
3580 req->privileges_lancer = cpu_to_le32(privileges);
3581 else
3582 req->privileges = cpu_to_le32(privileges);
3583
3584 status = be_mcc_notify_wait(adapter);
3585err:
3586 spin_unlock_bh(&adapter->mcc_lock);
3587 return status;
3588}
3589
5a712c13
SP		 3590/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3591 * pmac_id_valid: false => pmac_id or MAC address is requested.
3592 * If pmac_id is returned, pmac_id_valid is returned as true
3593 */
1578e777 3594int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 3595 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3596 u8 domain)
590c391d
PR		 3597{
3598 struct be_mcc_wrb *wrb;
3599 struct be_cmd_req_get_mac_list *req;
3600 int status;
3601 int mac_count;
e5e1ee89
PR		 3602 struct be_dma_mem get_mac_list_cmd;
3603 int i;
3604
3605 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3606 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
e51000db
SB		 3607 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3608 get_mac_list_cmd.size,
3609 &get_mac_list_cmd.dma,
3610 GFP_ATOMIC);
e5e1ee89
PR		 3611
3612 if (!get_mac_list_cmd.va) {
3613 dev_err(&adapter->pdev->dev,
a2cc4e0b 3614 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 3615 return -ENOMEM;
3616 }
590c391d
PR		 3617
3618 spin_lock_bh(&adapter->mcc_lock);
3619
3620 wrb = wrb_from_mccq(adapter);
3621 if (!wrb) {
3622 status = -EBUSY;
e5e1ee89 3623 goto out;
590c391d 3624 }
e5e1ee89
PR		 3625
3626 req = get_mac_list_cmd.va;
590c391d
PR		 3627
3628 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 3629 OPCODE_COMMON_GET_MAC_LIST,
3630 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 3631 req->hdr.domain = domain;
e5e1ee89 3632 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 3633 if (*pmac_id_valid) {
3634 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 3635 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 3636 req->perm_override = 0;
3637 } else {
3638 req->perm_override = 1;
3639 }
590c391d
PR		 3640
3641 status = be_mcc_notify_wait(adapter);
3642 if (!status) {
3643 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 3644 get_mac_list_cmd.va;
5a712c13
SP		 3645
3646 if (*pmac_id_valid) {
3647 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3648 ETH_ALEN);
3649 goto out;
3650 }
3651
e5e1ee89
PR		 3652 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3653 /* Mac list returned could contain one or more active mac_ids
dbedd44e 3654 * or one or more true or pseudo permanent mac addresses.
1578e777
PR		 3655 * If an active mac_id is present, return first active mac_id
3656 * found.
e5e1ee89 3657 */
590c391d 3658 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3659 struct get_list_macaddr *mac_entry;
3660 u16 mac_addr_size;
3661 u32 mac_id;
3662
3663 mac_entry = &resp->macaddr_list[i];
3664 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3665 /* mac_id is a 32 bit value and mac_addr size
3666 * is 6 bytes
3667 */
3668 if (mac_addr_size == sizeof(u32)) {
5a712c13 3669 *pmac_id_valid = true;
e5e1ee89
PR		 3670 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3671 *pmac_id = le32_to_cpu(mac_id);
3672 goto out;
590c391d 3673 }
590c391d 3674 }
1578e777 3675 /* If no active mac_id found, return first mac addr */
5a712c13 3676 *pmac_id_valid = false;
e5e1ee89 3677 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3678 ETH_ALEN);
590c391d
PR		 3679 }
3680
e5e1ee89 3681out:
590c391d 3682 spin_unlock_bh(&adapter->mcc_lock);
e51000db
SB		 3683 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3684 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3685 return status;
3686}
3687
a2cc4e0b
SP		 3688int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3689 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3690{
b188f090
SR		 3691 if (!active)
3692 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3693 if_handle, domain);
3175d8c2 3694 if (BEx_chip(adapter))
5a712c13 3695 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3696 if_handle, curr_pmac_id);
3175d8c2
SP		 3697 else
3698 /* Fetch the MAC address using pmac_id */
3699 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3700 &curr_pmac_id,
3701 if_handle, domain);
5a712c13
SP		 3702}
3703
95046b92
SP		 3704int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3705{
3706 int status;
3707 bool pmac_valid = false;
3708
c7bf7169 3709 eth_zero_addr(mac);
95046b92 3710
3175d8c2
SP		 3711 if (BEx_chip(adapter)) {
3712 if (be_physfn(adapter))
3713 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3714 0);
3715 else
3716 status = be_cmd_mac_addr_query(adapter, mac, false,
3717 adapter->if_handle, 0);
3718 } else {
95046b92 3719 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3720 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3721 }
3722
95046b92
SP		 3723 return status;
3724}
3725
590c391d
PR		 3726/* Uses synchronous MCCQ */
3727int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3728 u8 mac_count, u32 domain)
3729{
3730 struct be_mcc_wrb *wrb;
3731 struct be_cmd_req_set_mac_list *req;
3732 int status;
3733 struct be_dma_mem cmd;
3734
3735 memset(&cmd, 0, sizeof(struct be_dma_mem));
3736 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
e51000db
SB		 3737 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3738 GFP_KERNEL);
d0320f75 3739 if (!cmd.va)
590c391d 3740 return -ENOMEM;
590c391d
PR		 3741
3742 spin_lock_bh(&adapter->mcc_lock);
3743
3744 wrb = wrb_from_mccq(adapter);
3745 if (!wrb) {
3746 status = -EBUSY;
3747 goto err;
3748 }
3749
3750 req = cmd.va;
3751 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3752 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3753 wrb, &cmd);
590c391d
PR		 3754
3755 req->hdr.domain = domain;
3756 req->mac_count = mac_count;
3757 if (mac_count)
3758 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3759
3760 status = be_mcc_notify_wait(adapter);
3761
3762err:
a2cc4e0b 3763 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
590c391d
PR		 3764 spin_unlock_bh(&adapter->mcc_lock);
3765 return status;
3766}
4762f6ce 3767
3175d8c2
SP		 3768/* Wrapper to delete any active MACs and provision the new mac.
3769 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3770 * current list are active.
3771 */
3772int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3773{
3774 bool active_mac = false;
3775 u8 old_mac[ETH_ALEN];
3776 u32 pmac_id;
3777 int status;
3778
3779 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3780 &pmac_id, if_id, dom);
3781
3175d8c2
SP		 3782 if (!status && active_mac)
3783 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3784
3785 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3786}
3787
f1f3ee1b 3788int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
e7bcbd7b 3789 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
f1f3ee1b
AK		 3790{
3791 struct be_mcc_wrb *wrb;
3792 struct be_cmd_req_set_hsw_config *req;
3793 void *ctxt;
3794 int status;
3795
3796 spin_lock_bh(&adapter->mcc_lock);
3797
3798 wrb = wrb_from_mccq(adapter);
3799 if (!wrb) {
3800 status = -EBUSY;
3801 goto err;
3802 }
3803
3804 req = embedded_payload(wrb);
3805 ctxt = &req->context;
3806
3807 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3808 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3809 NULL);
f1f3ee1b
AK		 3810
3811 req->hdr.domain = domain;
3812 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3813 if (pvid) {
3814 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3815 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3816 }
a77dcb8c
AK		 3817 if (!BEx_chip(adapter) && hsw_mode) {
3818 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3819 ctxt, adapter->hba_port_num);
3820 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3821 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3822 ctxt, hsw_mode);
3823 }
f1f3ee1b 3824
e7bcbd7b
KA		 3825 /* Enable/disable both mac and vlan spoof checking */
3826 if (!BEx_chip(adapter) && spoofchk) {
3827 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3828 ctxt, spoofchk);
3829 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3830 ctxt, spoofchk);
3831 }
3832
f1f3ee1b
AK		 3833 be_dws_cpu_to_le(req->context, sizeof(req->context));
3834 status = be_mcc_notify_wait(adapter);
3835
3836err:
3837 spin_unlock_bh(&adapter->mcc_lock);
3838 return status;
3839}
3840
3841/* Get Hyper switch config */
3842int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
e7bcbd7b 3843 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
f1f3ee1b
AK		 3844{
3845 struct be_mcc_wrb *wrb;
3846 struct be_cmd_req_get_hsw_config *req;
3847 void *ctxt;
3848 int status;
3849 u16 vid;
3850
3851 spin_lock_bh(&adapter->mcc_lock);
3852
3853 wrb = wrb_from_mccq(adapter);
3854 if (!wrb) {
3855 status = -EBUSY;
3856 goto err;
3857 }
3858
3859 req = embedded_payload(wrb);
3860 ctxt = &req->context;
3861
3862 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3863 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3864 NULL);
f1f3ee1b
AK		 3865
3866 req->hdr.domain = domain;
a77dcb8c
AK		 3867 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3868 ctxt, intf_id);
f1f3ee1b 3869 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3870
2c07c1d7 3871 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3872 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3873 ctxt, adapter->hba_port_num);
3874 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3875 }
f1f3ee1b
AK		 3876 be_dws_cpu_to_le(req->context, sizeof(req->context));
3877
3878 status = be_mcc_notify_wait(adapter);
3879 if (!status) {
3880 struct be_cmd_resp_get_hsw_config *resp =
3881 embedded_payload(wrb);
03d28ffe 3882
a2cc4e0b 3883 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3884 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3885 pvid, &resp->context);
a77dcb8c
AK		 3886 if (pvid)
3887 *pvid = le16_to_cpu(vid);
3888 if (mode)
3889 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3890 port_fwd_type, &resp->context);
e7bcbd7b
KA		 3891 if (spoofchk)
3892 *spoofchk =
3893 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3894 spoofchk, &resp->context);
f1f3ee1b
AK		 3895 }
3896
3897err:
3898 spin_unlock_bh(&adapter->mcc_lock);
3899 return status;
3900}
3901
f7062ee5
SP		 3902static bool be_is_wol_excluded(struct be_adapter *adapter)
3903{
3904 struct pci_dev *pdev = adapter->pdev;
3905
18c57c74 3906 if (be_virtfn(adapter))
f7062ee5
SP		 3907 return true;
3908
3909 switch (pdev->subsystem_device) {
3910 case OC_SUBSYS_DEVICE_ID1:
3911 case OC_SUBSYS_DEVICE_ID2:
3912 case OC_SUBSYS_DEVICE_ID3:
3913 case OC_SUBSYS_DEVICE_ID4:
3914 return true;
3915 default:
3916 return false;
3917 }
3918}
3919
4762f6ce
AK		 3920int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3921{
3922 struct be_mcc_wrb *wrb;
3923 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3924 int status = 0;
4762f6ce
AK		 3925 struct be_dma_mem cmd;
3926
f25b119c
PR		 3927 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3928 CMD_SUBSYSTEM_ETH))
3929 return -EPERM;
3930
76a9e08e
SR		 3931 if (be_is_wol_excluded(adapter))
3932 return status;
3933
d98ef50f
SR		 3934 if (mutex_lock_interruptible(&adapter->mbox_lock))
3935 return -1;
3936
4762f6ce
AK		 3937 memset(&cmd, 0, sizeof(struct be_dma_mem));
3938 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
e51000db
SB		 3939 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3940 GFP_ATOMIC);
4762f6ce 3941 if (!cmd.va) {
a2cc4e0b 3942 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3943 status = -ENOMEM;
3944 goto err;
4762f6ce
AK		 3945 }
3946
4762f6ce
AK		 3947 wrb = wrb_from_mbox(adapter);
3948 if (!wrb) {
3949 status = -EBUSY;
3950 goto err;
3951 }
3952
3953 req = cmd.va;
3954
3955 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3956 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 3957 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 3958
3959 req->hdr.version = 1;
3960 req->query_options = BE_GET_WOL_CAP;
3961
3962 status = be_mbox_notify_wait(adapter);
3963 if (!status) {
3964 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 3965
504fbf1e 3966 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 3967
4762f6ce 3968 adapter->wol_cap = resp->wol_settings;
76a9e08e
SR		 3969 if (adapter->wol_cap & BE_WOL_CAP)
3970 adapter->wol_en = true;
4762f6ce
AK		 3971 }
3972err:
3973 mutex_unlock(&adapter->mbox_lock);
d98ef50f 3974 if (cmd.va)
e51000db
SB		 3975 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3976 cmd.dma);
4762f6ce 3977 return status;
941a77d5
SK		 3978
3979}
baaa08d1
VV		 3980
3981int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3982{
3983 struct be_dma_mem extfat_cmd;
3984 struct be_fat_conf_params *cfgs;
3985 int status;
3986 int i, j;
3987
3988 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3989 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
e51000db
SB		 3990 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3991 extfat_cmd.size, &extfat_cmd.dma,
3992 GFP_ATOMIC);
baaa08d1
VV		 3993 if (!extfat_cmd.va)
3994 return -ENOMEM;
3995
3996 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3997 if (status)
3998 goto err;
3999
4000 cfgs = (struct be_fat_conf_params *)
4001 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4002 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4003 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 4004
baaa08d1
VV		 4005 for (j = 0; j < num_modes; j++) {
4006 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4007 cfgs->module[i].trace_lvl[j].dbg_lvl =
4008 cpu_to_le32(level);
4009 }
4010 }
4011
4012 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4013err:
e51000db
SB		 4014 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4015 extfat_cmd.dma);
baaa08d1
VV		 4016 return status;
4017}
4018
4019int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4020{
4021 struct be_dma_mem extfat_cmd;
4022 struct be_fat_conf_params *cfgs;
4023 int status, j;
4024 int level = 0;
4025
4026 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4027 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
e51000db
SB		 4028 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4029 extfat_cmd.size, &extfat_cmd.dma,
4030 GFP_ATOMIC);
baaa08d1
VV		 4031
4032 if (!extfat_cmd.va) {
4033 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4034 __func__);
4035 goto err;
4036 }
4037
4038 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4039 if (!status) {
4040 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4041 sizeof(struct be_cmd_resp_hdr));
03d28ffe 4042
baaa08d1
VV		 4043 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4044 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4045 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4046 }
4047 }
e51000db
SB		 4048 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4049 extfat_cmd.dma);
baaa08d1
VV		 4050err:
4051 return level;
4052}
4053
941a77d5
SK		 4054int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4055 struct be_dma_mem *cmd)
4056{
4057 struct be_mcc_wrb *wrb;
4058 struct be_cmd_req_get_ext_fat_caps *req;
4059 int status;
4060
4061 if (mutex_lock_interruptible(&adapter->mbox_lock))
4062 return -1;
4063
4064 wrb = wrb_from_mbox(adapter);
4065 if (!wrb) {
4066 status = -EBUSY;
4067 goto err;
4068 }
4069
4070 req = cmd->va;
4071 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4072 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
4073 cmd->size, wrb, cmd);
4074 req->parameter_type = cpu_to_le32(1);
4075
4076 status = be_mbox_notify_wait(adapter);
4077err:
4078 mutex_unlock(&adapter->mbox_lock);
4079 return status;
4080}
4081
4082int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4083 struct be_dma_mem *cmd,
4084 struct be_fat_conf_params *configs)
4085{
4086 struct be_mcc_wrb *wrb;
4087 struct be_cmd_req_set_ext_fat_caps *req;
4088 int status;
4089
4090 spin_lock_bh(&adapter->mcc_lock);
4091
4092 wrb = wrb_from_mccq(adapter);
4093 if (!wrb) {
4094 status = -EBUSY;
4095 goto err;
4096 }
4097
4098 req = cmd->va;
4099 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4100 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4101 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
4102 cmd->size, wrb, cmd);
4103
4104 status = be_mcc_notify_wait(adapter);
4105err:
4106 spin_unlock_bh(&adapter->mcc_lock);
4107 return status;
4762f6ce 4108}
6a4ab669 4109
21252377 4110int be_cmd_query_port_name(struct be_adapter *adapter)
b4e32a71 4111{
b4e32a71 4112 struct be_cmd_req_get_port_name *req;
21252377 4113 struct be_mcc_wrb *wrb;
b4e32a71
PR		 4114 int status;
4115
21252377
VV		 4116 if (mutex_lock_interruptible(&adapter->mbox_lock))
4117 return -1;
b4e32a71 4118
21252377 4119 wrb = wrb_from_mbox(adapter);
b4e32a71
PR		 4120 req = embedded_payload(wrb);
4121
4122 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4123 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4124 NULL);
21252377
VV		 4125 if (!BEx_chip(adapter))
4126 req->hdr.version = 1;
b4e32a71 4127
21252377 4128 status = be_mbox_notify_wait(adapter);
b4e32a71
PR		 4129 if (!status) {
4130 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 4131
21252377 4132 adapter->port_name = resp->port_name[adapter->hba_port_num];
b4e32a71 4133 } else {
21252377 4134 adapter->port_name = adapter->hba_port_num + '0';
b4e32a71 4135 }
21252377
VV		 4136
4137 mutex_unlock(&adapter->mbox_lock);
b4e32a71
PR		 4138 return status;
4139}
4140
10cccf60
VV		 4141/* Descriptor type */
4142enum {
4143 FUNC_DESC = 1,
4144 VFT_DESC = 2
4145};
4146
4147static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4148 int desc_type)
abb93951 4149{
150d58c7 4150 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 4151 struct be_nic_res_desc *nic;
abb93951
PR		 4152 int i;
4153
4154 for (i = 0; i < desc_count; i++) {
150d58c7 4155 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 4156 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4157 nic = (struct be_nic_res_desc *)hdr;
4158 if (desc_type == FUNC_DESC ||
4159 (desc_type == VFT_DESC &&
4160 nic->flags & (1 << VFT_SHIFT)))
4161 return nic;
4162 }
abb93951 4163
150d58c7
VV		 4164 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4165 hdr = (void *)hdr + hdr->desc_len;
abb93951 4166 }
150d58c7
VV		 4167 return NULL;
4168}
4169
10cccf60
VV		 4170static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
4171{
4172 return be_get_nic_desc(buf, desc_count, VFT_DESC);
4173}
4174
4175static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
4176{
4177 return be_get_nic_desc(buf, desc_count, FUNC_DESC);
4178}
4179
150d58c7
VV		 4180static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
4181 u32 desc_count)
4182{
4183 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4184 struct be_pcie_res_desc *pcie;
4185 int i;
4186
4187 for (i = 0; i < desc_count; i++) {
4188 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4189 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
4190 pcie = (struct be_pcie_res_desc *)hdr;
4191 if (pcie->pf_num == devfn)
4192 return pcie;
4193 }
abb93951 4194
150d58c7
VV		 4195 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4196 hdr = (void *)hdr + hdr->desc_len;
4197 }
950e2958 4198 return NULL;
abb93951
PR		 4199}
4200
f93f160b
VV		 4201static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4202{
4203 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4204 int i;
4205
4206 for (i = 0; i < desc_count; i++) {
4207 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4208 return (struct be_port_res_desc *)hdr;
4209
4210 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4211 hdr = (void *)hdr + hdr->desc_len;
4212 }
4213 return NULL;
4214}
4215
92bf14ab
SP		 4216static void be_copy_nic_desc(struct be_resources *res,
4217 struct be_nic_res_desc *desc)
4218{
4219 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4220 res->max_vlans = le16_to_cpu(desc->vlan_count);
4221 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4222 res->max_tx_qs = le16_to_cpu(desc->txq_count);
4223 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4224 res->max_rx_qs = le16_to_cpu(desc->rq_count);
4225 res->max_evt_qs = le16_to_cpu(desc->eq_count);
f2858738
VV		 4226 res->max_cq_count = le16_to_cpu(desc->cq_count);
4227 res->max_iface_count = le16_to_cpu(desc->iface_count);
4228 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
92bf14ab
SP		 4229 /* Clear flags that driver is not interested in */
4230 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4231 BE_IF_CAP_FLAGS_WANT;
92bf14ab
SP		 4232}
4233
abb93951 4234/* Uses Mbox */
92bf14ab 4235int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 4236{
4237 struct be_mcc_wrb *wrb;
4238 struct be_cmd_req_get_func_config *req;
4239 int status;
4240 struct be_dma_mem cmd;
4241
d98ef50f
SR		 4242 if (mutex_lock_interruptible(&adapter->mbox_lock))
4243 return -1;
4244
abb93951
PR		 4245 memset(&cmd, 0, sizeof(struct be_dma_mem));
4246 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
e51000db
SB		 4247 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4248 GFP_ATOMIC);
abb93951
PR		 4249 if (!cmd.va) {
4250 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 4251 status = -ENOMEM;
4252 goto err;
abb93951 4253 }
abb93951
PR		 4254
4255 wrb = wrb_from_mbox(adapter);
4256 if (!wrb) {
4257 status = -EBUSY;
4258 goto err;
4259 }
4260
4261 req = cmd.va;
4262
4263 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4264 OPCODE_COMMON_GET_FUNC_CONFIG,
4265 cmd.size, wrb, &cmd);
4266
28710c55
KA		 4267 if (skyhawk_chip(adapter))
4268 req->hdr.version = 1;
4269
abb93951
PR		 4270 status = be_mbox_notify_wait(adapter);
4271 if (!status) {
4272 struct be_cmd_resp_get_func_config *resp = cmd.va;
4273 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 4274 struct be_nic_res_desc *desc;
abb93951 4275
10cccf60 4276 desc = be_get_func_nic_desc(resp->func_param, desc_count);
abb93951
PR		 4277 if (!desc) {
4278 status = -EINVAL;
4279 goto err;
4280 }
d5c18473 4281 adapter->pf_number = desc->pf_num;
92bf14ab 4282 be_copy_nic_desc(res, desc);
abb93951
PR		 4283 }
4284err:
4285 mutex_unlock(&adapter->mbox_lock);
d98ef50f 4286 if (cmd.va)
e51000db
SB		 4287 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4288 cmd.dma);
abb93951
PR		 4289 return status;
4290}
4291
72ef3a88
SK		 4292/* Will use MBOX only if MCCQ has not been created
4293 * non-zero domain => a PF is querying this on behalf of a VF
4294 * zero domain => a PF or a VF is querying this for itself
4295 */
92bf14ab 4296int be_cmd_get_profile_config(struct be_adapter *adapter,
f2858738 4297 struct be_resources *res, u8 query, u8 domain)
a05f99db 4298{
150d58c7 4299 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 4300 struct be_cmd_req_get_profile_config *req;
10cccf60 4301 struct be_nic_res_desc *vf_res;
150d58c7 4302 struct be_pcie_res_desc *pcie;
f93f160b 4303 struct be_port_res_desc *port;
150d58c7 4304 struct be_nic_res_desc *nic;
ba48c0c9 4305 struct be_mcc_wrb wrb = {0};
a05f99db 4306 struct be_dma_mem cmd;
f2858738 4307 u16 desc_count;
a05f99db
VV		 4308 int status;
4309
4310 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7 4311 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
e51000db
SB		 4312 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4313 GFP_ATOMIC);
150d58c7 4314 if (!cmd.va)
a05f99db 4315 return -ENOMEM;
a05f99db 4316
ba48c0c9
VV		 4317 req = cmd.va;
4318 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4319 OPCODE_COMMON_GET_PROFILE_CONFIG,
4320 cmd.size, &wrb, &cmd);
4321
ba48c0c9
VV		 4322 if (!lancer_chip(adapter))
4323 req->hdr.version = 1;
4324 req->type = ACTIVE_PROFILE_TYPE;
72ef3a88
SK		 4325 /* When a function is querying profile information relating to
4326 * itself hdr.pf_number must be set to it's pci_func_num + 1
4327 */
4328 req->hdr.domain = domain;
4329 if (domain == 0)
4330 req->hdr.pf_num = adapter->pci_func_num + 1;
ba48c0c9 4331
f2858738
VV		 4332 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4333 * descriptors with all bits set to "1" for the fields which can be
4334 * modified using SET_PROFILE_CONFIG cmd.
4335 */
4336 if (query == RESOURCE_MODIFIABLE)
4337 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4338
ba48c0c9 4339 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 4340 if (status)
4341 goto err;
abb93951 4342
150d58c7 4343 resp = cmd.va;
f2858738 4344 desc_count = le16_to_cpu(resp->desc_count);
abb93951 4345
a2cc4e0b
SP		 4346 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
4347 desc_count);
150d58c7 4348 if (pcie)
92bf14ab 4349 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 4350
f93f160b
VV		 4351 port = be_get_port_desc(resp->func_param, desc_count);
4352 if (port)
4353 adapter->mc_type = port->mc_type;
4354
10cccf60 4355 nic = be_get_func_nic_desc(resp->func_param, desc_count);
92bf14ab
SP		 4356 if (nic)
4357 be_copy_nic_desc(res, nic);
4358
10cccf60
VV		 4359 vf_res = be_get_vft_desc(resp->func_param, desc_count);
4360 if (vf_res)
4361 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 4362err:
a05f99db 4363 if (cmd.va)
e51000db
SB		 4364 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4365 cmd.dma);
abb93951
PR		 4366 return status;
4367}
4368
bec84e6b
VV		 4369/* Will use MBOX only if MCCQ has not been created */
4370static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4371 int size, int count, u8 version, u8 domain)
d5c18473 4372{
d5c18473 4373 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 4374 struct be_mcc_wrb wrb = {0};
4375 struct be_dma_mem cmd;
d5c18473
PR		 4376 int status;
4377
bec84e6b
VV		 4378 memset(&cmd, 0, sizeof(struct be_dma_mem));
4379 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
e51000db
SB		 4380 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4381 GFP_ATOMIC);
bec84e6b
VV		 4382 if (!cmd.va)
4383 return -ENOMEM;
d5c18473 4384
bec84e6b 4385 req = cmd.va;
d5c18473 4386 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 4387 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4388 &wrb, &cmd);
a401801c 4389 req->hdr.version = version;
d5c18473 4390 req->hdr.domain = domain;
bec84e6b 4391 req->desc_count = cpu_to_le32(count);
a401801c
SP		 4392 memcpy(req->desc, desc, size);
4393
bec84e6b
VV		 4394 status = be_cmd_notify_wait(adapter, &wrb);
4395
4396 if (cmd.va)
e51000db
SB		 4397 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4398 cmd.dma);
d5c18473
PR		 4399 return status;
4400}
4401
a401801c 4402/* Mark all fields invalid */
bec84e6b 4403static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 4404{
4405 memset(nic, 0, sizeof(*nic));
4406 nic->unicast_mac_count = 0xFFFF;
4407 nic->mcc_count = 0xFFFF;
4408 nic->vlan_count = 0xFFFF;
4409 nic->mcast_mac_count = 0xFFFF;
4410 nic->txq_count = 0xFFFF;
4411 nic->rq_count = 0xFFFF;
4412 nic->rssq_count = 0xFFFF;
4413 nic->lro_count = 0xFFFF;
4414 nic->cq_count = 0xFFFF;
4415 nic->toe_conn_count = 0xFFFF;
4416 nic->eq_count = 0xFFFF;
0f77ba73 4417 nic->iface_count = 0xFFFF;
a401801c 4418 nic->link_param = 0xFF;
0f77ba73 4419 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 4420 nic->acpi_params = 0xFF;
4421 nic->wol_param = 0x0F;
0f77ba73
RN		 4422 nic->tunnel_iface_count = 0xFFFF;
4423 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 4424 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 4425 nic->bw_max = 0xFFFFFFFF;
4426}
4427
bec84e6b
VV		 4428/* Mark all fields invalid */
4429static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4430{
4431 memset(pcie, 0, sizeof(*pcie));
4432 pcie->sriov_state = 0xFF;
4433 pcie->pf_state = 0xFF;
4434 pcie->pf_type = 0xFF;
4435 pcie->num_vfs = 0xFFFF;
4436}
4437
0f77ba73
RN		 4438int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4439 u8 domain)
a401801c 4440{
0f77ba73
RN		 4441 struct be_nic_res_desc nic_desc;
4442 u32 bw_percent;
4443 u16 version = 0;
4444
4445 if (BE3_chip(adapter))
4446 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 4447
0f77ba73
RN		 4448 be_reset_nic_desc(&nic_desc);
4449 nic_desc.pf_num = adapter->pf_number;
4450 nic_desc.vf_num = domain;
58bdeaa6 4451 nic_desc.bw_min = 0;
0f77ba73 4452 if (lancer_chip(adapter)) {
a401801c
SP		 4453 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4454 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4455 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4456 (1 << NOSV_SHIFT);
0f77ba73 4457 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 4458 } else {
0f77ba73
RN		 4459 version = 1;
4460 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4461 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4462 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4463 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4464 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 4465 }
0f77ba73
RN		 4466
4467 return be_cmd_set_profile_config(adapter, &nic_desc,
4468 nic_desc.hdr.desc_len,
bec84e6b
VV		 4469 1, version, domain);
4470}
4471
f2858738
VV		 4472static void be_fill_vf_res_template(struct be_adapter *adapter,
4473 struct be_resources pool_res,
4474 u16 num_vfs, u16 num_vf_qs,
4475 struct be_nic_res_desc *nic_vft)
4476{
4477 u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
4478 struct be_resources res_mod = {0};
4479
4480 /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
4481 * which are modifiable using SET_PROFILE_CONFIG cmd.
4482 */
4483 be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
4484
4485 /* If RSS IFACE capability flags are modifiable for a VF, set the
4486 * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
4487 * more than 1 RSSQ is available for a VF.
4488 * Otherwise, provision only 1 queue pair for VF.
4489 */
4490 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
4491 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4492 if (num_vf_qs > 1) {
4493 vf_if_cap_flags |= BE_IF_FLAGS_RSS;
4494 if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
4495 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
4496 } else {
4497 vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
4498 BE_IF_FLAGS_DEFQ_RSS);
4499 }
f2858738
VV		 4500 } else {
4501 num_vf_qs = 1;
4502 }
4503
196e3735
KA		 4504 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_VLAN_PROMISCUOUS) {
4505 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4506 vf_if_cap_flags &= ~BE_IF_FLAGS_VLAN_PROMISCUOUS;
4507 }
4508
4509 nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
f2858738
VV		 4510 nic_vft->rq_count = cpu_to_le16(num_vf_qs);
4511 nic_vft->txq_count = cpu_to_le16(num_vf_qs);
4512 nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
4513 nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
4514 (num_vfs + 1));
4515
4516 /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
4517 * among the PF and it's VFs, if the fields are changeable
4518 */
4519 if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
4520 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
4521 (num_vfs + 1));
4522
4523 if (res_mod.max_vlans == FIELD_MODIFIABLE)
4524 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
4525 (num_vfs + 1));
4526
4527 if (res_mod.max_iface_count == FIELD_MODIFIABLE)
4528 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
4529 (num_vfs + 1));
4530
4531 if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
4532 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
4533 (num_vfs + 1));
4534}
4535
bec84e6b 4536int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738
VV		 4537 struct be_resources pool_res, u16 num_vfs,
4538 u16 num_vf_qs)
bec84e6b
VV		 4539{
4540 struct {
4541 struct be_pcie_res_desc pcie;
4542 struct be_nic_res_desc nic_vft;
4543 } __packed desc;
bec84e6b 4544
bec84e6b
VV		 4545 /* PF PCIE descriptor */
4546 be_reset_pcie_desc(&desc.pcie);
4547 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4548 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 4549 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 4550 desc.pcie.pf_num = adapter->pdev->devfn;
4551 desc.pcie.sriov_state = num_vfs ? 1 : 0;
4552 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4553
4554 /* VF NIC Template descriptor */
4555 be_reset_nic_desc(&desc.nic_vft);
4556 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4557 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 4558 desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 4559 desc.nic_vft.pf_num = adapter->pdev->devfn;
4560 desc.nic_vft.vf_num = 0;
4561
f2858738
VV		 4562 be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
4563 &desc.nic_vft);
bec84e6b
VV		 4564
4565 return be_cmd_set_profile_config(adapter, &desc,
4566 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 4567}
4568
4569int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4570{
4571 struct be_mcc_wrb *wrb;
4572 struct be_cmd_req_manage_iface_filters *req;
4573 int status;
4574
4575 if (iface == 0xFFFFFFFF)
4576 return -1;
4577
4578 spin_lock_bh(&adapter->mcc_lock);
4579
4580 wrb = wrb_from_mccq(adapter);
4581 if (!wrb) {
4582 status = -EBUSY;
4583 goto err;
4584 }
4585 req = embedded_payload(wrb);
4586
4587 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4588 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4589 wrb, NULL);
4590 req->op = op;
4591 req->target_iface_id = cpu_to_le32(iface);
4592
4593 status = be_mcc_notify_wait(adapter);
4594err:
4595 spin_unlock_bh(&adapter->mcc_lock);
4596 return status;
4597}
4598
4599int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4600{
4601 struct be_port_res_desc port_desc;
4602
4603 memset(&port_desc, 0, sizeof(port_desc));
4604 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4605 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4606 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4607 port_desc.link_num = adapter->hba_port_num;
4608 if (port) {
4609 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4610 (1 << RCVID_SHIFT);
4611 port_desc.nv_port = swab16(port);
4612 } else {
4613 port_desc.nv_flags = NV_TYPE_DISABLED;
4614 port_desc.nv_port = 0;
4615 }
4616
4617 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 4618 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 4619}
4620
4c876616
SP		 4621int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4622 int vf_num)
4623{
4624 struct be_mcc_wrb *wrb;
4625 struct be_cmd_req_get_iface_list *req;
4626 struct be_cmd_resp_get_iface_list *resp;
4627 int status;
4628
4629 spin_lock_bh(&adapter->mcc_lock);
4630
4631 wrb = wrb_from_mccq(adapter);
4632 if (!wrb) {
4633 status = -EBUSY;
4634 goto err;
4635 }
4636 req = embedded_payload(wrb);
4637
4638 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4639 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4640 wrb, NULL);
4641 req->hdr.domain = vf_num + 1;
4642
4643 status = be_mcc_notify_wait(adapter);
4644 if (!status) {
4645 resp = (struct be_cmd_resp_get_iface_list *)req;
4646 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4647 }
4648
4649err:
4650 spin_unlock_bh(&adapter->mcc_lock);
4651 return status;
4652}
4653
5c510811
SK		 4654static int lancer_wait_idle(struct be_adapter *adapter)
4655{
4656#define SLIPORT_IDLE_TIMEOUT 30
4657 u32 reg_val;
4658 int status = 0, i;
4659
4660 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4661 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4662 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4663 break;
4664
4665 ssleep(1);
4666 }
4667
4668 if (i == SLIPORT_IDLE_TIMEOUT)
4669 status = -1;
4670
4671 return status;
4672}
4673
4674int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4675{
4676 int status = 0;
4677
4678 status = lancer_wait_idle(adapter);
4679 if (status)
4680 return status;
4681
4682 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4683
4684 return status;
4685}
4686
4687/* Routine to check whether dump image is present or not */
4688bool dump_present(struct be_adapter *adapter)
4689{
4690 u32 sliport_status = 0;
4691
4692 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4693 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4694}
4695
4696int lancer_initiate_dump(struct be_adapter *adapter)
4697{
f0613380 4698 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 4699 int status;
4700
f0613380
KA		 4701 if (dump_present(adapter)) {
4702 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4703 return -EEXIST;
4704 }
4705
5c510811
SK		 4706 /* give firmware reset and diagnostic dump */
4707 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4708 PHYSDEV_CONTROL_DD_MASK);
4709 if (status < 0) {
f0613380 4710 dev_err(dev, "FW reset failed\n");
5c510811
SK		 4711 return status;
4712 }
4713
4714 status = lancer_wait_idle(adapter);
4715 if (status)
4716 return status;
4717
4718 if (!dump_present(adapter)) {
f0613380
KA		 4719 dev_err(dev, "FW dump not generated\n");
4720 return -EIO;
5c510811
SK		 4721 }
4722
4723 return 0;
4724}
4725
f0613380
KA		 4726int lancer_delete_dump(struct be_adapter *adapter)
4727{
4728 int status;
4729
4730 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4731 return be_cmd_status(status);
4732}
4733
dcf7ebba
PR		 4734/* Uses sync mcc */
4735int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4736{
4737 struct be_mcc_wrb *wrb;
4738 struct be_cmd_enable_disable_vf *req;
4739 int status;
4740
0599863d 4741 if (BEx_chip(adapter))
dcf7ebba
PR		 4742 return 0;
4743
4744 spin_lock_bh(&adapter->mcc_lock);
4745
4746 wrb = wrb_from_mccq(adapter);
4747 if (!wrb) {
4748 status = -EBUSY;
4749 goto err;
4750 }
4751
4752 req = embedded_payload(wrb);
4753
4754 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4755 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4756 wrb, NULL);
4757
4758 req->hdr.domain = domain;
4759 req->enable = 1;
4760 status = be_mcc_notify_wait(adapter);
4761err:
4762 spin_unlock_bh(&adapter->mcc_lock);
4763 return status;
4764}
4765
68c45a2d
SK		 4766int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4767{
4768 struct be_mcc_wrb *wrb;
4769 struct be_cmd_req_intr_set *req;
4770 int status;
4771
4772 if (mutex_lock_interruptible(&adapter->mbox_lock))
4773 return -1;
4774
4775 wrb = wrb_from_mbox(adapter);
4776
4777 req = embedded_payload(wrb);
4778
4779 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4780 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4781 wrb, NULL);
4782
4783 req->intr_enabled = intr_enable;
4784
4785 status = be_mbox_notify_wait(adapter);
4786
4787 mutex_unlock(&adapter->mbox_lock);
4788 return status;
4789}
4790
542963b7
VV		 4791/* Uses MBOX */
4792int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4793{
4794 struct be_cmd_req_get_active_profile *req;
4795 struct be_mcc_wrb *wrb;
4796 int status;
4797
4798 if (mutex_lock_interruptible(&adapter->mbox_lock))
4799 return -1;
4800
4801 wrb = wrb_from_mbox(adapter);
4802 if (!wrb) {
4803 status = -EBUSY;
4804 goto err;
4805 }
4806
4807 req = embedded_payload(wrb);
4808
4809 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4810 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4811 wrb, NULL);
4812
4813 status = be_mbox_notify_wait(adapter);
4814 if (!status) {
4815 struct be_cmd_resp_get_active_profile *resp =
4816 embedded_payload(wrb);
03d28ffe 4817
542963b7
VV		 4818 *profile_id = le16_to_cpu(resp->active_profile_id);
4819 }
4820
4821err:
4822 mutex_unlock(&adapter->mbox_lock);
4823 return status;
4824}
4825
d9d426af
SR		 4826int __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4827 int link_state, int version, u8 domain)
bdce2ad7
SR		 4828{
4829 struct be_mcc_wrb *wrb;
4830 struct be_cmd_req_set_ll_link *req;
4831 int status;
4832
bdce2ad7
SR		 4833 spin_lock_bh(&adapter->mcc_lock);
4834
4835 wrb = wrb_from_mccq(adapter);
4836 if (!wrb) {
4837 status = -EBUSY;
4838 goto err;
4839 }
4840
4841 req = embedded_payload(wrb);
4842
4843 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4844 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4845 sizeof(*req), wrb, NULL);
4846
d9d426af 4847 req->hdr.version = version;
bdce2ad7
SR		 4848 req->hdr.domain = domain;
4849
d9d426af
SR		 4850 if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4851 link_state == IFLA_VF_LINK_STATE_AUTO)
4852 req->link_config |= PLINK_ENABLE;
bdce2ad7
SR		 4853
4854 if (link_state == IFLA_VF_LINK_STATE_AUTO)
d9d426af 4855 req->link_config |= PLINK_TRACK;
bdce2ad7
SR		 4856
4857 status = be_mcc_notify_wait(adapter);
4858err:
4859 spin_unlock_bh(&adapter->mcc_lock);
4860 return status;
4861}
4862
d9d426af
SR		 4863int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4864 int link_state, u8 domain)
4865{
4866 int status;
4867
4868 if (BEx_chip(adapter))
4869 return -EOPNOTSUPP;
4870
4871 status = __be_cmd_set_logical_link_config(adapter, link_state,
4872 2, domain);
4873
4874 /* Version 2 of the command will not be recognized by older FW.
4875 * On such a failure issue version 1 of the command.
4876 */
4877 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4878 status = __be_cmd_set_logical_link_config(adapter, link_state,
4879 1, domain);
4880 return status;
4881}
6a4ab669 4882int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 4883 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 4884{
4885 struct be_adapter *adapter = netdev_priv(netdev_handle);
4886 struct be_mcc_wrb *wrb;
504fbf1e 4887 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 4888 struct be_cmd_req_hdr *req;
4889 struct be_cmd_resp_hdr *resp;
4890 int status;
4891
4892 spin_lock_bh(&adapter->mcc_lock);
4893
4894 wrb = wrb_from_mccq(adapter);
4895 if (!wrb) {
4896 status = -EBUSY;
4897 goto err;
4898 }
4899 req = embedded_payload(wrb);
4900 resp = embedded_payload(wrb);
4901
4902 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4903 hdr->opcode, wrb_payload_size, wrb, NULL);
4904 memcpy(req, wrb_payload, wrb_payload_size);
4905 be_dws_cpu_to_le(req, wrb_payload_size);
4906
4907 status = be_mcc_notify_wait(adapter);
4908 if (cmd_status)
4909 *cmd_status = (status & 0xffff);
4910 if (ext_status)
4911 *ext_status = 0;
4912 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4913 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4914err:
4915 spin_unlock_bh(&adapter->mcc_lock);
4916 return status;
4917}
4918EXPORT_SYMBOL(be_roce_mcc_cmd);
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