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be2net: Fix configuring VLAN for VF for Lancer
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
3de09455
SK		 22static inline void *embedded_payload(struct be_mcc_wrb *wrb)
23{
24 return wrb->payload.embedded_payload;
25}
609ff3bb 26
8788fdc2 27static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 28{
8788fdc2 29 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 30 u32 val = 0;
31
6589ade0 32 if (be_error(adapter))
7acc2087 33 return;
7acc2087 34
5fb379ee
SP		 35 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
36 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 37
38 wmb();
8788fdc2 39 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 40}
41
42/* To check if valid bit is set, check the entire word as we don't know
43 * the endianness of the data (old entry is host endian while a new entry is
44 * little endian) */
efd2e40a 45static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee
SP		 46{
47 if (compl->flags != 0) {
48 compl->flags = le32_to_cpu(compl->flags);
49 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
50 return true;
51 } else {
52 return false;
53 }
54}
55
56/* Need to reset the entire word that houses the valid bit */
efd2e40a 57static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 58{
59 compl->flags = 0;
60}
61
652bf646
PR		 62static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
63{
64 unsigned long addr;
65
66 addr = tag1;
67 addr = ((addr << 16) << 16) | tag0;
68 return (void *)addr;
69}
70
8788fdc2 71static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 72 struct be_mcc_compl *compl)
5fb379ee
SP		 73{
74 u16 compl_status, extd_status;
652bf646
PR		 75 struct be_cmd_resp_hdr *resp_hdr;
76 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 77
78 /* Just swap the status to host endian; mcc tag is opaquely copied
79 * from mcc_wrb */
80 be_dws_le_to_cpu(compl, 4);
81
82 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
83 CQE_STATUS_COMPL_MASK;
dd131e76 84
652bf646
PR		 85 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
86
87 if (resp_hdr) {
88 opcode = resp_hdr->opcode;
89 subsystem = resp_hdr->subsystem;
90 }
91
92 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
93 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
94 (subsystem == CMD_SUBSYSTEM_COMMON)) {
dd131e76
SB		 95 adapter->flash_status = compl_status;
96 complete(&adapter->flash_compl);
97 }
98
b31c50a7 99 if (compl_status == MCC_STATUS_SUCCESS) {
652bf646
PR		 100 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
101 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
102 (subsystem == CMD_SUBSYSTEM_ETH)) {
89a88ab8 103 be_parse_stats(adapter);
b2aebe6d 104 adapter->stats_cmd_sent = false;
b31c50a7 105 }
652bf646
PR		 106 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
107 subsystem == CMD_SUBSYSTEM_COMMON) {
3de09455 108 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
652bf646 109 (void *)resp_hdr;
3de09455
SK		 110 adapter->drv_stats.be_on_die_temperature =
111 resp->on_die_temperature;
112 }
2b3f291b 113 } else {
652bf646 114 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
7aeb2156 115 adapter->be_get_temp_freq = 0;
3de09455 116
2b3f291b
SP		 117 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
118 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
119 goto done;
120
121 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 122 dev_warn(&adapter->pdev->dev,
522609f2 123 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 124 opcode, subsystem);
2b3f291b
SP		 125 } else {
126 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
127 CQE_STATUS_EXTD_MASK;
97f1d8cd
VV		 128 dev_err(&adapter->pdev->dev,
129 "opcode %d-%d failed:status %d-%d\n",
130 opcode, subsystem, compl_status, extd_status);
2b3f291b 131 }
5fb379ee 132 }
2b3f291b 133done:
b31c50a7 134 return compl_status;
5fb379ee
SP		 135}
136
a8f447bd 137/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 138static void be_async_link_state_process(struct be_adapter *adapter,
a8f447bd
SP		 139 struct be_async_event_link_state *evt)
140{
b236916a 141 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 142 adapter->phy.link_speed = -1;
b236916a 143
2e177a5c
PR		 144 /* Ignore physical link event */
145 if (lancer_chip(adapter) &&
146 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
147 return;
148
b236916a
AK		 149 /* For the initial link status do not rely on the ASYNC event as
150 * it may not be received in some cases.
151 */
152 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
153 be_link_status_update(adapter, evt->port_link_status);
a8f447bd
SP		 154}
155
cc4ce020
SK		 156/* Grp5 CoS Priority evt */
157static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
158 struct be_async_event_grp5_cos_priority *evt)
159{
160 if (evt->valid) {
161 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 162 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 163 adapter->recommended_prio =
164 evt->reco_default_priority << VLAN_PRIO_SHIFT;
165 }
166}
167
323ff71e 168/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020
SK		 169static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
170 struct be_async_event_grp5_qos_link_speed *evt)
171{
323ff71e
SP		 172 if (adapter->phy.link_speed >= 0 &&
173 evt->physical_port == adapter->port_num)
174 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 175}
176
3968fa1e
AK		 177/*Grp5 PVID evt*/
178static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
179 struct be_async_event_grp5_pvid_state *evt)
180{
181 if (evt->enabled)
939cf306 182 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
3968fa1e
AK		 183 else
184 adapter->pvid = 0;
185}
186
cc4ce020
SK		 187static void be_async_grp5_evt_process(struct be_adapter *adapter,
188 u32 trailer, struct be_mcc_compl *evt)
189{
190 u8 event_type = 0;
191
192 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
193 ASYNC_TRAILER_EVENT_TYPE_MASK;
194
195 switch (event_type) {
196 case ASYNC_EVENT_COS_PRIORITY:
197 be_async_grp5_cos_priority_process(adapter,
198 (struct be_async_event_grp5_cos_priority *)evt);
199 break;
200 case ASYNC_EVENT_QOS_SPEED:
201 be_async_grp5_qos_speed_process(adapter,
202 (struct be_async_event_grp5_qos_link_speed *)evt);
203 break;
3968fa1e
AK		 204 case ASYNC_EVENT_PVID_STATE:
205 be_async_grp5_pvid_state_process(adapter,
206 (struct be_async_event_grp5_pvid_state *)evt);
207 break;
cc4ce020
SK		 208 default:
209 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
210 break;
211 }
212}
213
a8f447bd
SP		 214static inline bool is_link_state_evt(u32 trailer)
215{
807540ba 216 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
a8f447bd 217 ASYNC_TRAILER_EVENT_CODE_MASK) ==
807540ba 218 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 219}
5fb379ee 220
cc4ce020
SK		 221static inline bool is_grp5_evt(u32 trailer)
222{
223 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
224 ASYNC_TRAILER_EVENT_CODE_MASK) ==
225 ASYNC_EVENT_CODE_GRP_5);
226}
227
efd2e40a 228static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 229{
8788fdc2 230 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 231 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 232
233 if (be_mcc_compl_is_new(compl)) {
234 queue_tail_inc(mcc_cq);
235 return compl;
236 }
237 return NULL;
238}
239
7a1e9b20
SP		 240void be_async_mcc_enable(struct be_adapter *adapter)
241{
242 spin_lock_bh(&adapter->mcc_cq_lock);
243
244 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
245 adapter->mcc_obj.rearm_cq = true;
246
247 spin_unlock_bh(&adapter->mcc_cq_lock);
248}
249
250void be_async_mcc_disable(struct be_adapter *adapter)
251{
252 adapter->mcc_obj.rearm_cq = false;
253}
254
10ef9ab4 255int be_process_mcc(struct be_adapter *adapter)
5fb379ee 256{
efd2e40a 257 struct be_mcc_compl *compl;
10ef9ab4 258 int num = 0, status = 0;
7a1e9b20 259 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 260
072a9c48 261 spin_lock(&adapter->mcc_cq_lock);
8788fdc2 262 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd
SP		 263 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
264 /* Interpret flags as an async trailer */
323f30b3
AK		 265 if (is_link_state_evt(compl->flags))
266 be_async_link_state_process(adapter,
a8f447bd 267 (struct be_async_event_link_state *) compl);
cc4ce020
SK		 268 else if (is_grp5_evt(compl->flags))
269 be_async_grp5_evt_process(adapter,
270 compl->flags, compl);
b31c50a7 271 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
10ef9ab4 272 status = be_mcc_compl_process(adapter, compl);
7a1e9b20 273 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 274 }
275 be_mcc_compl_use(compl);
276 num++;
277 }
b31c50a7 278
10ef9ab4
SP		 279 if (num)
280 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
281
072a9c48 282 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 283 return status;
5fb379ee
SP		 284}
285
6ac7b687 286/* Wait till no more pending mcc requests are present */
b31c50a7 287static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 288{
b31c50a7 289#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 290 int i, status = 0;
f31e50a8
SP		 291 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
292
6ac7b687 293 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 294 if (be_error(adapter))
295 return -EIO;
296
072a9c48 297 local_bh_disable();
10ef9ab4 298 status = be_process_mcc(adapter);
072a9c48 299 local_bh_enable();
b31c50a7 300
f31e50a8 301 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 302 break;
303 udelay(100);
304 }
b31c50a7 305 if (i == mcc_timeout) {
6589ade0
SP		 306 dev_err(&adapter->pdev->dev, "FW not responding\n");
307 adapter->fw_timeout = true;
652bf646 308 return -EIO;
b31c50a7 309 }
f31e50a8 310 return status;
6ac7b687
SP		 311}
312
313/* Notify MCC requests and wait for completion */
b31c50a7 314static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 315{
652bf646
PR		 316 int status;
317 struct be_mcc_wrb *wrb;
318 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
319 u16 index = mcc_obj->q.head;
320 struct be_cmd_resp_hdr *resp;
321
322 index_dec(&index, mcc_obj->q.len);
323 wrb = queue_index_node(&mcc_obj->q, index);
324
325 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
326
8788fdc2 327 be_mcc_notify(adapter);
652bf646
PR		 328
329 status = be_mcc_wait_compl(adapter);
330 if (status == -EIO)
331 goto out;
332
333 status = resp->status;
334out:
335 return status;
6ac7b687
SP		 336}
337
5f0b849e 338static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 339{
f25b03a7 340 int msecs = 0;
6b7c5b94
SP		 341 u32 ready;
342
343 do {
6589ade0
SP		 344 if (be_error(adapter))
345 return -EIO;
346
cf588477 347 ready = ioread32(db);
434b3648 348 if (ready == 0xffffffff)
cf588477 349 return -1;
cf588477
SP		 350
351 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 352 if (ready)
353 break;
354
f25b03a7 355 if (msecs > 4000) {
6589ade0
SP		 356 dev_err(&adapter->pdev->dev, "FW not responding\n");
357 adapter->fw_timeout = true;
f67ef7ba 358 be_detect_error(adapter);
6b7c5b94
SP		 359 return -1;
360 }
361
1dbf53a2 362 msleep(1);
f25b03a7 363 msecs++;
6b7c5b94
SP		 364 } while (true);
365
366 return 0;
367}
368
369/*
370 * Insert the mailbox address into the doorbell in two steps
5fb379ee 371 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 372 */
b31c50a7 373static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 374{
375 int status;
6b7c5b94 376 u32 val = 0;
8788fdc2
SP		 377 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
378 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 379 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 380 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 381
cf588477
SP		 382 /* wait for ready to be set */
383 status = be_mbox_db_ready_wait(adapter, db);
384 if (status != 0)
385 return status;
386
6b7c5b94
SP		 387 val |= MPU_MAILBOX_DB_HI_MASK;
388 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
389 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
390 iowrite32(val, db);
391
392 /* wait for ready to be set */
5f0b849e 393 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 394 if (status != 0)
395 return status;
396
397 val = 0;
6b7c5b94
SP		 398 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
399 val |= (u32)(mbox_mem->dma >> 4) << 2;
400 iowrite32(val, db);
401
5f0b849e 402 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 403 if (status != 0)
404 return status;
405
5fb379ee 406 /* A cq entry has been made now */
efd2e40a
SP		 407 if (be_mcc_compl_is_new(compl)) {
408 status = be_mcc_compl_process(adapter, &mbox->compl);
409 be_mcc_compl_use(compl);
5fb379ee
SP		 410 if (status)
411 return status;
412 } else {
5f0b849e 413 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 414 return -1;
415 }
5fb379ee 416 return 0;
6b7c5b94
SP		 417}
418
8788fdc2 419static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
6b7c5b94 420{
fe6d2a38
SP		 421 u32 sem;
422
423 if (lancer_chip(adapter))
424 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
425 else
426 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
6b7c5b94
SP		 427
428 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
429 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
430 return -1;
431 else
432 return 0;
433}
434
bf99e50d
PR		 435int lancer_wait_ready(struct be_adapter *adapter)
436{
437#define SLIPORT_READY_TIMEOUT 30
438 u32 sliport_status;
439 int status = 0, i;
440
441 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
442 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
443 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
444 break;
445
446 msleep(1000);
447 }
448
449 if (i == SLIPORT_READY_TIMEOUT)
450 status = -1;
451
452 return status;
453}
454
67297ad8
PR		 455static bool lancer_provisioning_error(struct be_adapter *adapter)
456{
457 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
458 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
459 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
460 sliport_err1 = ioread32(adapter->db +
461 SLIPORT_ERROR1_OFFSET);
462 sliport_err2 = ioread32(adapter->db +
463 SLIPORT_ERROR2_OFFSET);
464
465 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
466 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
467 return true;
468 }
469 return false;
470}
471
bf99e50d
PR		 472int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
473{
474 int status;
475 u32 sliport_status, err, reset_needed;
67297ad8
PR		 476 bool resource_error;
477
478 resource_error = lancer_provisioning_error(adapter);
479 if (resource_error)
480 return -1;
481
bf99e50d
PR		 482 status = lancer_wait_ready(adapter);
483 if (!status) {
484 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
485 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
486 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
487 if (err && reset_needed) {
488 iowrite32(SLI_PORT_CONTROL_IP_MASK,
489 adapter->db + SLIPORT_CONTROL_OFFSET);
490
491 /* check adapter has corrected the error */
492 status = lancer_wait_ready(adapter);
493 sliport_status = ioread32(adapter->db +
494 SLIPORT_STATUS_OFFSET);
495 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
496 SLIPORT_STATUS_RN_MASK);
497 if (status || sliport_status)
498 status = -1;
499 } else if (err || reset_needed) {
500 status = -1;
501 }
502 }
67297ad8
PR		 503 /* Stop error recovery if error is not recoverable.
504 * No resource error is temporary errors and will go away
505 * when PF provisions resources.
506 */
507 resource_error = lancer_provisioning_error(adapter);
508 if (status == -1 && !resource_error)
509 adapter->eeh_error = true;
510
bf99e50d
PR		 511 return status;
512}
513
514int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 515{
43a04fdc
SP		 516 u16 stage;
517 int status, timeout = 0;
6ed35eea 518 struct device *dev = &adapter->pdev->dev;
6b7c5b94 519
bf99e50d
PR		 520 if (lancer_chip(adapter)) {
521 status = lancer_wait_ready(adapter);
522 return status;
523 }
524
43a04fdc
SP		 525 do {
526 status = be_POST_stage_get(adapter, &stage);
527 if (status) {
6ed35eea 528 dev_err(dev, "POST error; stage=0x%x\n", stage);
43a04fdc
SP		 529 return -1;
530 } else if (stage != POST_STAGE_ARMFW_RDY) {
6ed35eea
SP		 531 if (msleep_interruptible(2000)) {
532 dev_err(dev, "Waiting for POST aborted\n");
533 return -EINTR;
534 }
43a04fdc
SP		 535 timeout += 2;
536 } else {
537 return 0;
538 }
3ab81b5f 539 } while (timeout < 60);
6b7c5b94 540
6ed35eea 541 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
43a04fdc 542 return -1;
6b7c5b94
SP		 543}
544
6b7c5b94
SP		 545
546static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
547{
548 return &wrb->payload.sgl[0];
549}
550
6b7c5b94
SP		 551
552/* Don't touch the hdr after it's prepared */
106df1e3
SK		 553/* mem will be NULL for embedded commands */
554static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
555 u8 subsystem, u8 opcode, int cmd_len,
556 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
6b7c5b94 557{
106df1e3 558 struct be_sge *sge;
652bf646
PR		 559 unsigned long addr = (unsigned long)req_hdr;
560 u64 req_addr = addr;
106df1e3 561
6b7c5b94
SP		 562 req_hdr->opcode = opcode;
563 req_hdr->subsystem = subsystem;
564 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 565 req_hdr->version = 0;
106df1e3 566
652bf646
PR		 567 wrb->tag0 = req_addr & 0xFFFFFFFF;
568 wrb->tag1 = upper_32_bits(req_addr);
569
106df1e3
SK		 570 wrb->payload_length = cmd_len;
571 if (mem) {
572 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
573 MCC_WRB_SGE_CNT_SHIFT;
574 sge = nonembedded_sgl(wrb);
575 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
576 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
577 sge->len = cpu_to_le32(mem->size);
578 } else
579 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
580 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 581}
582
583static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
584 struct be_dma_mem *mem)
585{
586 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
587 u64 dma = (u64)mem->dma;
588
589 for (i = 0; i < buf_pages; i++) {
590 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
591 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
592 dma += PAGE_SIZE_4K;
593 }
594}
595
596/* Converts interrupt delay in microseconds to multiplier value */
597static u32 eq_delay_to_mult(u32 usec_delay)
598{
599#define MAX_INTR_RATE 651042
600 const u32 round = 10;
601 u32 multiplier;
602
603 if (usec_delay == 0)
604 multiplier = 0;
605 else {
606 u32 interrupt_rate = 1000000 / usec_delay;
607 /* Max delay, corresponding to the lowest interrupt rate */
608 if (interrupt_rate == 0)
609 multiplier = 1023;
610 else {
611 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
612 multiplier /= interrupt_rate;
613 /* Round the multiplier to the closest value.*/
614 multiplier = (multiplier + round/2) / round;
615 multiplier = min(multiplier, (u32)1023);
616 }
617 }
618 return multiplier;
619}
620
b31c50a7 621static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 622{
b31c50a7
SP		 623 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
624 struct be_mcc_wrb *wrb
625 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
626 memset(wrb, 0, sizeof(*wrb));
627 return wrb;
6b7c5b94
SP		 628}
629
b31c50a7 630static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 631{
b31c50a7
SP		 632 struct be_queue_info *mccq = &adapter->mcc_obj.q;
633 struct be_mcc_wrb *wrb;
634
713d0394
SP		 635 if (atomic_read(&mccq->used) >= mccq->len) {
636 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
637 return NULL;
638 }
639
b31c50a7
SP		 640 wrb = queue_head_node(mccq);
641 queue_head_inc(mccq);
642 atomic_inc(&mccq->used);
643 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 644 return wrb;
645}
646
2243e2e9
SP		 647/* Tell fw we're about to start firing cmds by writing a
648 * special pattern across the wrb hdr; uses mbox
649 */
650int be_cmd_fw_init(struct be_adapter *adapter)
651{
652 u8 *wrb;
653 int status;
654
bf99e50d
PR		 655 if (lancer_chip(adapter))
656 return 0;
657
2984961c
IV		 658 if (mutex_lock_interruptible(&adapter->mbox_lock))
659 return -1;
2243e2e9
SP		 660
661 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 662 *wrb++ = 0xFF;
663 *wrb++ = 0x12;
664 *wrb++ = 0x34;
665 *wrb++ = 0xFF;
666 *wrb++ = 0xFF;
667 *wrb++ = 0x56;
668 *wrb++ = 0x78;
669 *wrb = 0xFF;
2243e2e9
SP		 670
671 status = be_mbox_notify_wait(adapter);
672
2984961c 673 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 674 return status;
675}
676
677/* Tell fw we're done with firing cmds by writing a
678 * special pattern across the wrb hdr; uses mbox
679 */
680int be_cmd_fw_clean(struct be_adapter *adapter)
681{
682 u8 *wrb;
683 int status;
684
bf99e50d
PR		 685 if (lancer_chip(adapter))
686 return 0;
687
2984961c
IV		 688 if (mutex_lock_interruptible(&adapter->mbox_lock))
689 return -1;
2243e2e9
SP		 690
691 wrb = (u8 *)wrb_from_mbox(adapter);
692 *wrb++ = 0xFF;
693 *wrb++ = 0xAA;
694 *wrb++ = 0xBB;
695 *wrb++ = 0xFF;
696 *wrb++ = 0xFF;
697 *wrb++ = 0xCC;
698 *wrb++ = 0xDD;
699 *wrb = 0xFF;
700
701 status = be_mbox_notify_wait(adapter);
702
2984961c 703 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 704 return status;
705}
bf99e50d 706
8788fdc2 707int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94
SP		 708 struct be_queue_info *eq, int eq_delay)
709{
b31c50a7
SP		 710 struct be_mcc_wrb *wrb;
711 struct be_cmd_req_eq_create *req;
6b7c5b94
SP		 712 struct be_dma_mem *q_mem = &eq->dma_mem;
713 int status;
714
2984961c
IV		 715 if (mutex_lock_interruptible(&adapter->mbox_lock))
716 return -1;
b31c50a7
SP		 717
718 wrb = wrb_from_mbox(adapter);
719 req = embedded_payload(wrb);
6b7c5b94 720
106df1e3
SK		 721 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
722 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 723
724 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
725
6b7c5b94
SP		 726 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
727 /* 4byte eqe*/
728 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
729 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
730 __ilog2_u32(eq->len/256));
731 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
732 eq_delay_to_mult(eq_delay));
733 be_dws_cpu_to_le(req->context, sizeof(req->context));
734
735 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
736
b31c50a7 737 status = be_mbox_notify_wait(adapter);
6b7c5b94 738 if (!status) {
b31c50a7 739 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 740 eq->id = le16_to_cpu(resp->eq_id);
741 eq->created = true;
742 }
b31c50a7 743
2984961c 744 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 745 return status;
746}
747
f9449ab7 748/* Use MCC */
8788fdc2 749int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 750 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 751{
b31c50a7
SP		 752 struct be_mcc_wrb *wrb;
753 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 754 int status;
755
f9449ab7 756 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 757
f9449ab7
SP		 758 wrb = wrb_from_mccq(adapter);
759 if (!wrb) {
760 status = -EBUSY;
761 goto err;
762 }
b31c50a7 763 req = embedded_payload(wrb);
6b7c5b94 764
106df1e3
SK		 765 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
766 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
5ee4979b 767 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 768 if (permanent) {
769 req->permanent = 1;
770 } else {
b31c50a7 771 req->if_id = cpu_to_le16((u16) if_handle);
590c391d 772 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 773 req->permanent = 0;
774 }
775
f9449ab7 776 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 777 if (!status) {
778 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
6b7c5b94 779 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 780 }
6b7c5b94 781
f9449ab7
SP		 782err:
783 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 784 return status;
785}
786
b31c50a7 787/* Uses synchronous MCCQ */
8788fdc2 788int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08 789 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 790{
b31c50a7
SP		 791 struct be_mcc_wrb *wrb;
792 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 793 int status;
794
b31c50a7
SP		 795 spin_lock_bh(&adapter->mcc_lock);
796
797 wrb = wrb_from_mccq(adapter);
713d0394
SP		 798 if (!wrb) {
799 status = -EBUSY;
800 goto err;
801 }
b31c50a7 802 req = embedded_payload(wrb);
6b7c5b94 803
106df1e3
SK		 804 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
805 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
6b7c5b94 806
f8617e08 807 req->hdr.domain = domain;
6b7c5b94
SP		 808 req->if_id = cpu_to_le32(if_id);
809 memcpy(req->mac_address, mac_addr, ETH_ALEN);
810
b31c50a7 811 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 812 if (!status) {
813 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
814 *pmac_id = le32_to_cpu(resp->pmac_id);
815 }
816
713d0394 817err:
b31c50a7 818 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 819
820 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
821 status = -EPERM;
822
6b7c5b94
SP		 823 return status;
824}
825
b31c50a7 826/* Uses synchronous MCCQ */
30128031 827int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 828{
b31c50a7
SP		 829 struct be_mcc_wrb *wrb;
830 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 831 int status;
832
30128031
SP		 833 if (pmac_id == -1)
834 return 0;
835
b31c50a7
SP		 836 spin_lock_bh(&adapter->mcc_lock);
837
838 wrb = wrb_from_mccq(adapter);
713d0394
SP		 839 if (!wrb) {
840 status = -EBUSY;
841 goto err;
842 }
b31c50a7 843 req = embedded_payload(wrb);
6b7c5b94 844
106df1e3
SK		 845 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
846 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
6b7c5b94 847
f8617e08 848 req->hdr.domain = dom;
6b7c5b94
SP		 849 req->if_id = cpu_to_le32(if_id);
850 req->pmac_id = cpu_to_le32(pmac_id);
851
b31c50a7
SP		 852 status = be_mcc_notify_wait(adapter);
853
713d0394 854err:
b31c50a7 855 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 856 return status;
857}
858
b31c50a7 859/* Uses Mbox */
10ef9ab4
SP		 860int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
861 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 862{
b31c50a7
SP		 863 struct be_mcc_wrb *wrb;
864 struct be_cmd_req_cq_create *req;
6b7c5b94 865 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 866 void *ctxt;
6b7c5b94
SP		 867 int status;
868
2984961c
IV		 869 if (mutex_lock_interruptible(&adapter->mbox_lock))
870 return -1;
b31c50a7
SP		 871
872 wrb = wrb_from_mbox(adapter);
873 req = embedded_payload(wrb);
874 ctxt = &req->context;
6b7c5b94 875
106df1e3
SK		 876 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
877 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 878
879 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38 880 if (lancer_chip(adapter)) {
8b7756ca 881 req->hdr.version = 2;
fe6d2a38 882 req->page_size = 1; /* 1 for 4K */
fe6d2a38
SP		 883 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
884 no_delay);
885 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
886 __ilog2_u32(cq->len/256));
887 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
888 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
889 ctxt, 1);
890 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
891 ctxt, eq->id);
fe6d2a38
SP		 892 } else {
893 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
894 coalesce_wm);
895 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
896 ctxt, no_delay);
897 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
898 __ilog2_u32(cq->len/256));
899 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 900 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
901 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
fe6d2a38 902 }
6b7c5b94 903
6b7c5b94
SP		 904 be_dws_cpu_to_le(ctxt, sizeof(req->context));
905
906 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
907
b31c50a7 908 status = be_mbox_notify_wait(adapter);
6b7c5b94 909 if (!status) {
b31c50a7 910 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 911 cq->id = le16_to_cpu(resp->cq_id);
912 cq->created = true;
913 }
b31c50a7 914
2984961c 915 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 916
917 return status;
918}
919
920static u32 be_encoded_q_len(int q_len)
921{
922 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
923 if (len_encoded == 16)
924 len_encoded = 0;
925 return len_encoded;
926}
927
34b1ef04 928int be_cmd_mccq_ext_create(struct be_adapter *adapter,
5fb379ee
SP		 929 struct be_queue_info *mccq,
930 struct be_queue_info *cq)
931{
b31c50a7 932 struct be_mcc_wrb *wrb;
34b1ef04 933 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 934 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 935 void *ctxt;
5fb379ee
SP		 936 int status;
937
2984961c
IV		 938 if (mutex_lock_interruptible(&adapter->mbox_lock))
939 return -1;
b31c50a7
SP		 940
941 wrb = wrb_from_mbox(adapter);
942 req = embedded_payload(wrb);
943 ctxt = &req->context;
5fb379ee 944
106df1e3
SK		 945 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
946 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
5fb379ee 947
d4a2ac3e 948 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38
SP		 949 if (lancer_chip(adapter)) {
950 req->hdr.version = 1;
951 req->cq_id = cpu_to_le16(cq->id);
952
953 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
954 be_encoded_q_len(mccq->len));
955 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
956 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
957 ctxt, cq->id);
958 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
959 ctxt, 1);
960
961 } else {
962 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
963 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
964 be_encoded_q_len(mccq->len));
965 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
966 }
5fb379ee 967
cc4ce020 968 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 969 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
5fb379ee
SP		 970 be_dws_cpu_to_le(ctxt, sizeof(req->context));
971
972 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
973
b31c50a7 974 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 975 if (!status) {
976 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
977 mccq->id = le16_to_cpu(resp->id);
978 mccq->created = true;
979 }
2984961c 980 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 981
982 return status;
983}
984
34b1ef04
SK		 985int be_cmd_mccq_org_create(struct be_adapter *adapter,
986 struct be_queue_info *mccq,
987 struct be_queue_info *cq)
988{
989 struct be_mcc_wrb *wrb;
990 struct be_cmd_req_mcc_create *req;
991 struct be_dma_mem *q_mem = &mccq->dma_mem;
992 void *ctxt;
993 int status;
994
995 if (mutex_lock_interruptible(&adapter->mbox_lock))
996 return -1;
997
998 wrb = wrb_from_mbox(adapter);
999 req = embedded_payload(wrb);
1000 ctxt = &req->context;
1001
106df1e3
SK		 1002 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1003 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
34b1ef04
SK		 1004
1005 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1006
1007 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1008 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1009 be_encoded_q_len(mccq->len));
1010 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1011
1012 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1013
1014 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1015
1016 status = be_mbox_notify_wait(adapter);
1017 if (!status) {
1018 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1019 mccq->id = le16_to_cpu(resp->id);
1020 mccq->created = true;
1021 }
1022
1023 mutex_unlock(&adapter->mbox_lock);
1024 return status;
1025}
1026
1027int be_cmd_mccq_create(struct be_adapter *adapter,
1028 struct be_queue_info *mccq,
1029 struct be_queue_info *cq)
1030{
1031 int status;
1032
1033 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1034 if (status && !lancer_chip(adapter)) {
1035 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1036 "or newer to avoid conflicting priorities between NIC "
1037 "and FCoE traffic");
1038 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1039 }
1040 return status;
1041}
1042
8788fdc2 1043int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 1044 struct be_queue_info *txq,
1045 struct be_queue_info *cq)
1046{
b31c50a7
SP		 1047 struct be_mcc_wrb *wrb;
1048 struct be_cmd_req_eth_tx_create *req;
6b7c5b94 1049 struct be_dma_mem *q_mem = &txq->dma_mem;
b31c50a7 1050 void *ctxt;
6b7c5b94 1051 int status;
6b7c5b94 1052
293c4a7d
PR		 1053 spin_lock_bh(&adapter->mcc_lock);
1054
1055 wrb = wrb_from_mccq(adapter);
1056 if (!wrb) {
1057 status = -EBUSY;
1058 goto err;
1059 }
b31c50a7 1060
b31c50a7
SP		 1061 req = embedded_payload(wrb);
1062 ctxt = &req->context;
6b7c5b94 1063
106df1e3
SK		 1064 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1065 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94 1066
8b7756ca
PR		 1067 if (lancer_chip(adapter)) {
1068 req->hdr.version = 1;
1069 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1070 adapter->if_handle);
1071 }
1072
6b7c5b94
SP		 1073 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1074 req->ulp_num = BE_ULP1_NUM;
1075 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1076
b31c50a7
SP		 1077 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1078 be_encoded_q_len(txq->len));
6b7c5b94
SP		 1079 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1080 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1081
1082 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1083
1084 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1085
293c4a7d 1086 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1087 if (!status) {
1088 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1089 txq->id = le16_to_cpu(resp->cid);
1090 txq->created = true;
1091 }
b31c50a7 1092
293c4a7d
PR		 1093err:
1094 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1095
1096 return status;
1097}
1098
482c9e79 1099/* Uses MCC */
8788fdc2 1100int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94 1101 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
10ef9ab4 1102 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1103{
b31c50a7
SP		 1104 struct be_mcc_wrb *wrb;
1105 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1106 struct be_dma_mem *q_mem = &rxq->dma_mem;
1107 int status;
1108
482c9e79 1109 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1110
482c9e79
SP		 1111 wrb = wrb_from_mccq(adapter);
1112 if (!wrb) {
1113 status = -EBUSY;
1114 goto err;
1115 }
b31c50a7 1116 req = embedded_payload(wrb);
6b7c5b94 1117
106df1e3
SK		 1118 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1119 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1120
1121 req->cq_id = cpu_to_le16(cq_id);
1122 req->frag_size = fls(frag_size) - 1;
1123 req->num_pages = 2;
1124 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1125 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1126 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1127 req->rss_queue = cpu_to_le32(rss);
1128
482c9e79 1129 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1130 if (!status) {
1131 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1132 rxq->id = le16_to_cpu(resp->id);
1133 rxq->created = true;
3abcdeda 1134 *rss_id = resp->rss_id;
6b7c5b94 1135 }
b31c50a7 1136
482c9e79
SP		 1137err:
1138 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1139 return status;
1140}
1141
b31c50a7
SP		 1142/* Generic destroyer function for all types of queues
1143 * Uses Mbox
1144 */
8788fdc2 1145int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94
SP		 1146 int queue_type)
1147{
b31c50a7
SP		 1148 struct be_mcc_wrb *wrb;
1149 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1150 u8 subsys = 0, opcode = 0;
1151 int status;
1152
2984961c
IV		 1153 if (mutex_lock_interruptible(&adapter->mbox_lock))
1154 return -1;
6b7c5b94 1155
b31c50a7
SP		 1156 wrb = wrb_from_mbox(adapter);
1157 req = embedded_payload(wrb);
1158
6b7c5b94
SP		 1159 switch (queue_type) {
1160 case QTYPE_EQ:
1161 subsys = CMD_SUBSYSTEM_COMMON;
1162 opcode = OPCODE_COMMON_EQ_DESTROY;
1163 break;
1164 case QTYPE_CQ:
1165 subsys = CMD_SUBSYSTEM_COMMON;
1166 opcode = OPCODE_COMMON_CQ_DESTROY;
1167 break;
1168 case QTYPE_TXQ:
1169 subsys = CMD_SUBSYSTEM_ETH;
1170 opcode = OPCODE_ETH_TX_DESTROY;
1171 break;
1172 case QTYPE_RXQ:
1173 subsys = CMD_SUBSYSTEM_ETH;
1174 opcode = OPCODE_ETH_RX_DESTROY;
1175 break;
5fb379ee
SP		 1176 case QTYPE_MCCQ:
1177 subsys = CMD_SUBSYSTEM_COMMON;
1178 opcode = OPCODE_COMMON_MCC_DESTROY;
1179 break;
6b7c5b94 1180 default:
5f0b849e 1181 BUG();
6b7c5b94 1182 }
d744b44e 1183
106df1e3
SK		 1184 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1185 NULL);
6b7c5b94
SP		 1186 req->id = cpu_to_le16(q->id);
1187
b31c50a7 1188 status = be_mbox_notify_wait(adapter);
482c9e79
SP		 1189 if (!status)
1190 q->created = false;
5f0b849e 1191
2984961c 1192 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1193 return status;
1194}
6b7c5b94 1195
482c9e79
SP		 1196/* Uses MCC */
1197int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1198{
1199 struct be_mcc_wrb *wrb;
1200 struct be_cmd_req_q_destroy *req;
1201 int status;
1202
1203 spin_lock_bh(&adapter->mcc_lock);
1204
1205 wrb = wrb_from_mccq(adapter);
1206 if (!wrb) {
1207 status = -EBUSY;
1208 goto err;
1209 }
1210 req = embedded_payload(wrb);
1211
106df1e3
SK		 1212 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1213 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1214 req->id = cpu_to_le16(q->id);
1215
1216 status = be_mcc_notify_wait(adapter);
1217 if (!status)
1218 q->created = false;
1219
1220err:
1221 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1222 return status;
1223}
1224
b31c50a7 1225/* Create an rx filtering policy configuration on an i/f
f9449ab7 1226 * Uses MCCQ
b31c50a7 1227 */
73d540f2 1228int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1229 u32 *if_handle, u32 domain)
6b7c5b94 1230{
b31c50a7
SP		 1231 struct be_mcc_wrb *wrb;
1232 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1233 int status;
1234
f9449ab7 1235 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1236
f9449ab7
SP		 1237 wrb = wrb_from_mccq(adapter);
1238 if (!wrb) {
1239 status = -EBUSY;
1240 goto err;
1241 }
b31c50a7 1242 req = embedded_payload(wrb);
6b7c5b94 1243
106df1e3
SK		 1244 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1245 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
ba343c77 1246 req->hdr.domain = domain;
73d540f2
SP		 1247 req->capability_flags = cpu_to_le32(cap_flags);
1248 req->enable_flags = cpu_to_le32(en_flags);
1578e777
PR		 1249
1250 req->pmac_invalid = true;
6b7c5b94 1251
f9449ab7 1252 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1253 if (!status) {
1254 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1255 *if_handle = le32_to_cpu(resp->interface_id);
6b7c5b94
SP		 1256 }
1257
f9449ab7
SP		 1258err:
1259 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1260 return status;
1261}
1262
f9449ab7 1263/* Uses MCCQ */
30128031 1264int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1265{
b31c50a7
SP		 1266 struct be_mcc_wrb *wrb;
1267 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1268 int status;
1269
30128031 1270 if (interface_id == -1)
f9449ab7 1271 return 0;
b31c50a7 1272
f9449ab7
SP		 1273 spin_lock_bh(&adapter->mcc_lock);
1274
1275 wrb = wrb_from_mccq(adapter);
1276 if (!wrb) {
1277 status = -EBUSY;
1278 goto err;
1279 }
b31c50a7 1280 req = embedded_payload(wrb);
6b7c5b94 1281
106df1e3
SK		 1282 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1283 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
658681f7 1284 req->hdr.domain = domain;
6b7c5b94 1285 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1286
f9449ab7
SP		 1287 status = be_mcc_notify_wait(adapter);
1288err:
1289 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1290 return status;
1291}
1292
1293/* Get stats is a non embedded command: the request is not embedded inside
1294 * WRB but is a separate dma memory block
b31c50a7 1295 * Uses asynchronous MCC
6b7c5b94 1296 */
8788fdc2 1297int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1298{
b31c50a7 1299 struct be_mcc_wrb *wrb;
89a88ab8 1300 struct be_cmd_req_hdr *hdr;
713d0394 1301 int status = 0;
6b7c5b94 1302
b31c50a7 1303 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1304
b31c50a7 1305 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1306 if (!wrb) {
1307 status = -EBUSY;
1308 goto err;
1309 }
89a88ab8 1310 hdr = nonemb_cmd->va;
6b7c5b94 1311
106df1e3
SK		 1312 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1313 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
89a88ab8
AK		 1314
1315 if (adapter->generation == BE_GEN3)
1316 hdr->version = 1;
1317
b31c50a7 1318 be_mcc_notify(adapter);
b2aebe6d 1319 adapter->stats_cmd_sent = true;
6b7c5b94 1320
713d0394 1321err:
b31c50a7 1322 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1323 return status;
6b7c5b94
SP		 1324}
1325
005d5696
SX		 1326/* Lancer Stats */
1327int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1328 struct be_dma_mem *nonemb_cmd)
1329{
1330
1331 struct be_mcc_wrb *wrb;
1332 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1333 int status = 0;
1334
1335 spin_lock_bh(&adapter->mcc_lock);
1336
1337 wrb = wrb_from_mccq(adapter);
1338 if (!wrb) {
1339 status = -EBUSY;
1340 goto err;
1341 }
1342 req = nonemb_cmd->va;
005d5696 1343
106df1e3
SK		 1344 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1345 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1346 nonemb_cmd);
005d5696 1347
d51ebd33 1348 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1349 req->cmd_params.params.reset_stats = 0;
1350
005d5696
SX		 1351 be_mcc_notify(adapter);
1352 adapter->stats_cmd_sent = true;
1353
1354err:
1355 spin_unlock_bh(&adapter->mcc_lock);
1356 return status;
1357}
1358
323ff71e
SP		 1359static int be_mac_to_link_speed(int mac_speed)
1360{
1361 switch (mac_speed) {
1362 case PHY_LINK_SPEED_ZERO:
1363 return 0;
1364 case PHY_LINK_SPEED_10MBPS:
1365 return 10;
1366 case PHY_LINK_SPEED_100MBPS:
1367 return 100;
1368 case PHY_LINK_SPEED_1GBPS:
1369 return 1000;
1370 case PHY_LINK_SPEED_10GBPS:
1371 return 10000;
1372 }
1373 return 0;
1374}
1375
1376/* Uses synchronous mcc
1377 * Returns link_speed in Mbps
1378 */
1379int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1380 u8 *link_status, u32 dom)
6b7c5b94 1381{
b31c50a7
SP		 1382 struct be_mcc_wrb *wrb;
1383 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1384 int status;
1385
b31c50a7
SP		 1386 spin_lock_bh(&adapter->mcc_lock);
1387
b236916a
AK		 1388 if (link_status)
1389 *link_status = LINK_DOWN;
1390
b31c50a7 1391 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1392 if (!wrb) {
1393 status = -EBUSY;
1394 goto err;
1395 }
b31c50a7 1396 req = embedded_payload(wrb);
a8f447bd 1397
57cd80d4
PR		 1398 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1399 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1400
b236916a 1401 if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
daad6167
PR		 1402 req->hdr.version = 1;
1403
57cd80d4 1404 req->hdr.domain = dom;
6b7c5b94 1405
b31c50a7 1406 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1407 if (!status) {
1408 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
323ff71e
SP		 1409 if (link_speed) {
1410 *link_speed = resp->link_speed ?
1411 le16_to_cpu(resp->link_speed) * 10 :
1412 be_mac_to_link_speed(resp->mac_speed);
1413
1414 if (!resp->logical_link_status)
1415 *link_speed = 0;
0388f251 1416 }
b236916a
AK		 1417 if (link_status)
1418 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1419 }
1420
713d0394 1421err:
b31c50a7 1422 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1423 return status;
1424}
1425
609ff3bb
AK		 1426/* Uses synchronous mcc */
1427int be_cmd_get_die_temperature(struct be_adapter *adapter)
1428{
1429 struct be_mcc_wrb *wrb;
1430 struct be_cmd_req_get_cntl_addnl_attribs *req;
1431 int status;
1432
1433 spin_lock_bh(&adapter->mcc_lock);
1434
1435 wrb = wrb_from_mccq(adapter);
1436 if (!wrb) {
1437 status = -EBUSY;
1438 goto err;
1439 }
1440 req = embedded_payload(wrb);
1441
106df1e3
SK		 1442 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1443 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1444 wrb, NULL);
609ff3bb 1445
3de09455 1446 be_mcc_notify(adapter);
609ff3bb
AK		 1447
1448err:
1449 spin_unlock_bh(&adapter->mcc_lock);
1450 return status;
1451}
1452
311fddc7
SK		 1453/* Uses synchronous mcc */
1454int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1455{
1456 struct be_mcc_wrb *wrb;
1457 struct be_cmd_req_get_fat *req;
1458 int status;
1459
1460 spin_lock_bh(&adapter->mcc_lock);
1461
1462 wrb = wrb_from_mccq(adapter);
1463 if (!wrb) {
1464 status = -EBUSY;
1465 goto err;
1466 }
1467 req = embedded_payload(wrb);
1468
106df1e3
SK		 1469 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1470 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
311fddc7
SK		 1471 req->fat_operation = cpu_to_le32(QUERY_FAT);
1472 status = be_mcc_notify_wait(adapter);
1473 if (!status) {
1474 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1475 if (log_size && resp->log_size)
fe2a70ee
SK		 1476 *log_size = le32_to_cpu(resp->log_size) -
1477 sizeof(u32);
311fddc7
SK		 1478 }
1479err:
1480 spin_unlock_bh(&adapter->mcc_lock);
1481 return status;
1482}
1483
1484void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1485{
1486 struct be_dma_mem get_fat_cmd;
1487 struct be_mcc_wrb *wrb;
1488 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1489 u32 offset = 0, total_size, buf_size,
1490 log_offset = sizeof(u32), payload_len;
311fddc7
SK		 1491 int status;
1492
1493 if (buf_len == 0)
1494 return;
1495
1496 total_size = buf_len;
1497
fe2a70ee
SK		 1498 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1499 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1500 get_fat_cmd.size,
1501 &get_fat_cmd.dma);
1502 if (!get_fat_cmd.va) {
1503 status = -ENOMEM;
1504 dev_err(&adapter->pdev->dev,
1505 "Memory allocation failure while retrieving FAT data\n");
1506 return;
1507 }
1508
311fddc7
SK		 1509 spin_lock_bh(&adapter->mcc_lock);
1510
311fddc7
SK		 1511 while (total_size) {
1512 buf_size = min(total_size, (u32)60*1024);
1513 total_size -= buf_size;
1514
fe2a70ee
SK		 1515 wrb = wrb_from_mccq(adapter);
1516 if (!wrb) {
1517 status = -EBUSY;
311fddc7
SK		 1518 goto err;
1519 }
1520 req = get_fat_cmd.va;
311fddc7 1521
fe2a70ee 1522 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3
SK		 1523 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1524 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1525 &get_fat_cmd);
311fddc7
SK		 1526
1527 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1528 req->read_log_offset = cpu_to_le32(log_offset);
1529 req->read_log_length = cpu_to_le32(buf_size);
1530 req->data_buffer_size = cpu_to_le32(buf_size);
1531
1532 status = be_mcc_notify_wait(adapter);
1533 if (!status) {
1534 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1535 memcpy(buf + offset,
1536 resp->data_buffer,
92aa9214 1537 le32_to_cpu(resp->read_log_length));
fe2a70ee 1538 } else {
311fddc7 1539 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1540 goto err;
1541 }
311fddc7
SK		 1542 offset += buf_size;
1543 log_offset += buf_size;
1544 }
1545err:
fe2a70ee
SK		 1546 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1547 get_fat_cmd.va,
1548 get_fat_cmd.dma);
311fddc7
SK		 1549 spin_unlock_bh(&adapter->mcc_lock);
1550}
1551
04b71175
SP		 1552/* Uses synchronous mcc */
1553int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1554 char *fw_on_flash)
6b7c5b94 1555{
b31c50a7
SP		 1556 struct be_mcc_wrb *wrb;
1557 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1558 int status;
1559
04b71175 1560 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1561
04b71175
SP		 1562 wrb = wrb_from_mccq(adapter);
1563 if (!wrb) {
1564 status = -EBUSY;
1565 goto err;
1566 }
6b7c5b94 1567
04b71175 1568 req = embedded_payload(wrb);
6b7c5b94 1569
106df1e3
SK		 1570 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1571 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
04b71175 1572 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1573 if (!status) {
1574 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
04b71175
SP		 1575 strcpy(fw_ver, resp->firmware_version_string);
1576 if (fw_on_flash)
1577 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
6b7c5b94 1578 }
04b71175
SP		 1579err:
1580 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1581 return status;
1582}
1583
b31c50a7
SP		 1584/* set the EQ delay interval of an EQ to specified value
1585 * Uses async mcc
1586 */
8788fdc2 1587int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
6b7c5b94 1588{
b31c50a7
SP		 1589 struct be_mcc_wrb *wrb;
1590 struct be_cmd_req_modify_eq_delay *req;
713d0394 1591 int status = 0;
6b7c5b94 1592
b31c50a7
SP		 1593 spin_lock_bh(&adapter->mcc_lock);
1594
1595 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1596 if (!wrb) {
1597 status = -EBUSY;
1598 goto err;
1599 }
b31c50a7 1600 req = embedded_payload(wrb);
6b7c5b94 1601
106df1e3
SK		 1602 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1603 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1604
1605 req->num_eq = cpu_to_le32(1);
1606 req->delay[0].eq_id = cpu_to_le32(eq_id);
1607 req->delay[0].phase = 0;
1608 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1609
b31c50a7 1610 be_mcc_notify(adapter);
6b7c5b94 1611
713d0394 1612err:
b31c50a7 1613 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1614 return status;
6b7c5b94
SP		 1615}
1616
b31c50a7 1617/* Uses sycnhronous mcc */
8788fdc2 1618int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
6b7c5b94
SP		 1619 u32 num, bool untagged, bool promiscuous)
1620{
b31c50a7
SP		 1621 struct be_mcc_wrb *wrb;
1622 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1623 int status;
1624
b31c50a7
SP		 1625 spin_lock_bh(&adapter->mcc_lock);
1626
1627 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1628 if (!wrb) {
1629 status = -EBUSY;
1630 goto err;
1631 }
b31c50a7 1632 req = embedded_payload(wrb);
6b7c5b94 1633
106df1e3
SK		 1634 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1635 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1636
1637 req->interface_id = if_id;
1638 req->promiscuous = promiscuous;
1639 req->untagged = untagged;
1640 req->num_vlan = num;
1641 if (!promiscuous) {
1642 memcpy(req->normal_vlan, vtag_array,
1643 req->num_vlan * sizeof(vtag_array[0]));
1644 }
1645
b31c50a7 1646 status = be_mcc_notify_wait(adapter);
6b7c5b94 1647
713d0394 1648err:
b31c50a7 1649 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1650 return status;
1651}
1652
5b8821b7 1653int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1654{
6ac7b687 1655 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1656 struct be_dma_mem *mem = &adapter->rx_filter;
1657 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1658 int status;
6b7c5b94 1659
8788fdc2 1660 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1661
b31c50a7 1662 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1663 if (!wrb) {
1664 status = -EBUSY;
1665 goto err;
1666 }
5b8821b7 1667 memset(req, 0, sizeof(*req));
106df1e3
SK		 1668 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1669 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1670 wrb, mem);
6b7c5b94 1671
5b8821b7
SP		 1672 req->if_id = cpu_to_le32(adapter->if_handle);
1673 if (flags & IFF_PROMISC) {
1674 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1675 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1676 if (value == ON)
1677 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
8e7d3f68 1678 BE_IF_FLAGS_VLAN_PROMISCUOUS);
5b8821b7
SP		 1679 } else if (flags & IFF_ALLMULTI) {
1680 req->if_flags_mask = req->if_flags =
8e7d3f68 1681 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7 1682 } else {
22bedad3 1683 struct netdev_hw_addr *ha;
5b8821b7 1684 int i = 0;
24307eef 1685
8e7d3f68
SP		 1686 req->if_flags_mask = req->if_flags =
1687 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1610c79f
PR		 1688
1689 /* Reset mcast promisc mode if already set by setting mask
1690 * and not setting flags field
1691 */
abb93951
PR		 1692 req->if_flags_mask |=
1693 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1694 adapter->if_cap_flags);
1610c79f 1695
016f97b1 1696 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1697 netdev_for_each_mc_addr(ha, adapter->netdev)
1698 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1699 }
1700
0d1d5875 1701 status = be_mcc_notify_wait(adapter);
713d0394 1702err:
8788fdc2 1703 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1704 return status;
6b7c5b94
SP		 1705}
1706
b31c50a7 1707/* Uses synchrounous mcc */
8788fdc2 1708int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1709{
b31c50a7
SP		 1710 struct be_mcc_wrb *wrb;
1711 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1712 int status;
1713
b31c50a7 1714 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1715
b31c50a7 1716 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1717 if (!wrb) {
1718 status = -EBUSY;
1719 goto err;
1720 }
b31c50a7 1721 req = embedded_payload(wrb);
6b7c5b94 1722
106df1e3
SK		 1723 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1724 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1725
1726 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1727 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1728
b31c50a7 1729 status = be_mcc_notify_wait(adapter);
6b7c5b94 1730
713d0394 1731err:
b31c50a7 1732 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1733 return status;
1734}
1735
b31c50a7 1736/* Uses sycn mcc */
8788fdc2 1737int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1738{
b31c50a7
SP		 1739 struct be_mcc_wrb *wrb;
1740 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1741 int status;
1742
b31c50a7 1743 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1744
b31c50a7 1745 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1746 if (!wrb) {
1747 status = -EBUSY;
1748 goto err;
1749 }
b31c50a7 1750 req = embedded_payload(wrb);
6b7c5b94 1751
106df1e3
SK		 1752 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1753 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94 1754
b31c50a7 1755 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1756 if (!status) {
1757 struct be_cmd_resp_get_flow_control *resp =
1758 embedded_payload(wrb);
1759 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1760 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1761 }
1762
713d0394 1763err:
b31c50a7 1764 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1765 return status;
1766}
1767
b31c50a7 1768/* Uses mbox */
3abcdeda
SP		 1769int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1770 u32 *mode, u32 *caps)
6b7c5b94 1771{
b31c50a7
SP		 1772 struct be_mcc_wrb *wrb;
1773 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 1774 int status;
1775
2984961c
IV		 1776 if (mutex_lock_interruptible(&adapter->mbox_lock))
1777 return -1;
6b7c5b94 1778
b31c50a7
SP		 1779 wrb = wrb_from_mbox(adapter);
1780 req = embedded_payload(wrb);
6b7c5b94 1781
106df1e3
SK		 1782 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1783 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94 1784
b31c50a7 1785 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 1786 if (!status) {
1787 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1788 *port_num = le32_to_cpu(resp->phys_port);
3486be29 1789 *mode = le32_to_cpu(resp->function_mode);
3abcdeda 1790 *caps = le32_to_cpu(resp->function_caps);
6b7c5b94
SP		 1791 }
1792
2984961c 1793 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1794 return status;
1795}
14074eab 1796
b31c50a7 1797/* Uses mbox */
14074eab 1798int be_cmd_reset_function(struct be_adapter *adapter)
1799{
b31c50a7
SP		 1800 struct be_mcc_wrb *wrb;
1801 struct be_cmd_req_hdr *req;
14074eab 1802 int status;
1803
bf99e50d
PR		 1804 if (lancer_chip(adapter)) {
1805 status = lancer_wait_ready(adapter);
1806 if (!status) {
1807 iowrite32(SLI_PORT_CONTROL_IP_MASK,
1808 adapter->db + SLIPORT_CONTROL_OFFSET);
1809 status = lancer_test_and_set_rdy_state(adapter);
1810 }
1811 if (status) {
1812 dev_err(&adapter->pdev->dev,
1813 "Adapter in non recoverable error\n");
1814 }
1815 return status;
1816 }
1817
2984961c
IV		 1818 if (mutex_lock_interruptible(&adapter->mbox_lock))
1819 return -1;
14074eab 1820
b31c50a7
SP		 1821 wrb = wrb_from_mbox(adapter);
1822 req = embedded_payload(wrb);
14074eab 1823
106df1e3
SK		 1824 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1825 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
14074eab 1826
b31c50a7 1827 status = be_mbox_notify_wait(adapter);
14074eab 1828
2984961c 1829 mutex_unlock(&adapter->mbox_lock);
14074eab 1830 return status;
1831}
84517482 1832
3abcdeda
SP		 1833int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1834{
1835 struct be_mcc_wrb *wrb;
1836 struct be_cmd_req_rss_config *req;
65f8584e
PR		 1837 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1838 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1839 0x3ea83c02, 0x4a110304};
3abcdeda
SP		 1840 int status;
1841
2984961c
IV		 1842 if (mutex_lock_interruptible(&adapter->mbox_lock))
1843 return -1;
3abcdeda
SP		 1844
1845 wrb = wrb_from_mbox(adapter);
1846 req = embedded_payload(wrb);
1847
106df1e3
SK		 1848 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1849 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 1850
1851 req->if_id = cpu_to_le32(adapter->if_handle);
1ca7ba92
SP		 1852 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1853 RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
d3bd3a5e
PR		 1854
1855 if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1856 req->hdr.version = 1;
1857 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1858 RSS_ENABLE_UDP_IPV6);
1859 }
1860
3abcdeda
SP		 1861 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1862 memcpy(req->cpu_table, rsstable, table_size);
1863 memcpy(req->hash, myhash, sizeof(myhash));
1864 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1865
1866 status = be_mbox_notify_wait(adapter);
1867
2984961c 1868 mutex_unlock(&adapter->mbox_lock);
3abcdeda
SP		 1869 return status;
1870}
1871
fad9ab2c
SB		 1872/* Uses sync mcc */
1873int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1874 u8 bcn, u8 sts, u8 state)
1875{
1876 struct be_mcc_wrb *wrb;
1877 struct be_cmd_req_enable_disable_beacon *req;
1878 int status;
1879
1880 spin_lock_bh(&adapter->mcc_lock);
1881
1882 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1883 if (!wrb) {
1884 status = -EBUSY;
1885 goto err;
1886 }
fad9ab2c
SB		 1887 req = embedded_payload(wrb);
1888
106df1e3
SK		 1889 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1890 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1891
1892 req->port_num = port_num;
1893 req->beacon_state = state;
1894 req->beacon_duration = bcn;
1895 req->status_duration = sts;
1896
1897 status = be_mcc_notify_wait(adapter);
1898
713d0394 1899err:
fad9ab2c
SB		 1900 spin_unlock_bh(&adapter->mcc_lock);
1901 return status;
1902}
1903
1904/* Uses sync mcc */
1905int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1906{
1907 struct be_mcc_wrb *wrb;
1908 struct be_cmd_req_get_beacon_state *req;
1909 int status;
1910
1911 spin_lock_bh(&adapter->mcc_lock);
1912
1913 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1914 if (!wrb) {
1915 status = -EBUSY;
1916 goto err;
1917 }
fad9ab2c
SB		 1918 req = embedded_payload(wrb);
1919
106df1e3
SK		 1920 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1921 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1922
1923 req->port_num = port_num;
1924
1925 status = be_mcc_notify_wait(adapter);
1926 if (!status) {
1927 struct be_cmd_resp_get_beacon_state *resp =
1928 embedded_payload(wrb);
1929 *state = resp->beacon_state;
1930 }
1931
713d0394 1932err:
fad9ab2c
SB		 1933 spin_unlock_bh(&adapter->mcc_lock);
1934 return status;
1935}
1936
485bf569 1937int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 1938 u32 data_size, u32 data_offset,
1939 const char *obj_name, u32 *data_written,
1940 u8 *change_status, u8 *addn_status)
485bf569
SN		 1941{
1942 struct be_mcc_wrb *wrb;
1943 struct lancer_cmd_req_write_object *req;
1944 struct lancer_cmd_resp_write_object *resp;
1945 void *ctxt = NULL;
1946 int status;
1947
1948 spin_lock_bh(&adapter->mcc_lock);
1949 adapter->flash_status = 0;
1950
1951 wrb = wrb_from_mccq(adapter);
1952 if (!wrb) {
1953 status = -EBUSY;
1954 goto err_unlock;
1955 }
1956
1957 req = embedded_payload(wrb);
1958
106df1e3 1959 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
485bf569 1960 OPCODE_COMMON_WRITE_OBJECT,
106df1e3
SK		 1961 sizeof(struct lancer_cmd_req_write_object), wrb,
1962 NULL);
485bf569
SN		 1963
1964 ctxt = &req->context;
1965 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1966 write_length, ctxt, data_size);
1967
1968 if (data_size == 0)
1969 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1970 eof, ctxt, 1);
1971 else
1972 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1973 eof, ctxt, 0);
1974
1975 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1976 req->write_offset = cpu_to_le32(data_offset);
1977 strcpy(req->object_name, obj_name);
1978 req->descriptor_count = cpu_to_le32(1);
1979 req->buf_len = cpu_to_le32(data_size);
1980 req->addr_low = cpu_to_le32((cmd->dma +
1981 sizeof(struct lancer_cmd_req_write_object))
1982 & 0xFFFFFFFF);
1983 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1984 sizeof(struct lancer_cmd_req_write_object)));
1985
1986 be_mcc_notify(adapter);
1987 spin_unlock_bh(&adapter->mcc_lock);
1988
1989 if (!wait_for_completion_timeout(&adapter->flash_compl,
804c7515 1990 msecs_to_jiffies(30000)))
485bf569
SN		 1991 status = -1;
1992 else
1993 status = adapter->flash_status;
1994
1995 resp = embedded_payload(wrb);
f67ef7ba 1996 if (!status) {
485bf569 1997 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 1998 *change_status = resp->change_status;
1999 } else {
485bf569 2000 *addn_status = resp->additional_status;
f67ef7ba 2001 }
485bf569
SN		 2002
2003 return status;
2004
2005err_unlock:
2006 spin_unlock_bh(&adapter->mcc_lock);
2007 return status;
2008}
2009
de49bd5a
PR		 2010int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2011 u32 data_size, u32 data_offset, const char *obj_name,
2012 u32 *data_read, u32 *eof, u8 *addn_status)
2013{
2014 struct be_mcc_wrb *wrb;
2015 struct lancer_cmd_req_read_object *req;
2016 struct lancer_cmd_resp_read_object *resp;
2017 int status;
2018
2019 spin_lock_bh(&adapter->mcc_lock);
2020
2021 wrb = wrb_from_mccq(adapter);
2022 if (!wrb) {
2023 status = -EBUSY;
2024 goto err_unlock;
2025 }
2026
2027 req = embedded_payload(wrb);
2028
2029 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2030 OPCODE_COMMON_READ_OBJECT,
2031 sizeof(struct lancer_cmd_req_read_object), wrb,
2032 NULL);
2033
2034 req->desired_read_len = cpu_to_le32(data_size);
2035 req->read_offset = cpu_to_le32(data_offset);
2036 strcpy(req->object_name, obj_name);
2037 req->descriptor_count = cpu_to_le32(1);
2038 req->buf_len = cpu_to_le32(data_size);
2039 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2040 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2041
2042 status = be_mcc_notify_wait(adapter);
2043
2044 resp = embedded_payload(wrb);
2045 if (!status) {
2046 *data_read = le32_to_cpu(resp->actual_read_len);
2047 *eof = le32_to_cpu(resp->eof);
2048 } else {
2049 *addn_status = resp->additional_status;
2050 }
2051
2052err_unlock:
2053 spin_unlock_bh(&adapter->mcc_lock);
2054 return status;
2055}
2056
84517482
AK		 2057int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2058 u32 flash_type, u32 flash_opcode, u32 buf_size)
2059{
b31c50a7 2060 struct be_mcc_wrb *wrb;
3f0d4560 2061 struct be_cmd_write_flashrom *req;
84517482
AK		 2062 int status;
2063
b31c50a7 2064 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2065 adapter->flash_status = 0;
b31c50a7
SP		 2066
2067 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2068 if (!wrb) {
2069 status = -EBUSY;
2892d9c2 2070 goto err_unlock;
713d0394
SP		 2071 }
2072 req = cmd->va;
84517482 2073
106df1e3
SK		 2074 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2075 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
84517482
AK		 2076
2077 req->params.op_type = cpu_to_le32(flash_type);
2078 req->params.op_code = cpu_to_le32(flash_opcode);
2079 req->params.data_buf_size = cpu_to_le32(buf_size);
2080
dd131e76
SB		 2081 be_mcc_notify(adapter);
2082 spin_unlock_bh(&adapter->mcc_lock);
2083
2084 if (!wait_for_completion_timeout(&adapter->flash_compl,
e2edb7d5 2085 msecs_to_jiffies(40000)))
dd131e76
SB		 2086 status = -1;
2087 else
2088 status = adapter->flash_status;
84517482 2089
2892d9c2
DC		 2090 return status;
2091
2092err_unlock:
2093 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2094 return status;
2095}
fa9a6fed 2096
3f0d4560
AK		 2097int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2098 int offset)
fa9a6fed
SB		 2099{
2100 struct be_mcc_wrb *wrb;
2101 struct be_cmd_write_flashrom *req;
2102 int status;
2103
2104 spin_lock_bh(&adapter->mcc_lock);
2105
2106 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2107 if (!wrb) {
2108 status = -EBUSY;
2109 goto err;
2110 }
fa9a6fed
SB		 2111 req = embedded_payload(wrb);
2112
106df1e3
SK		 2113 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2114 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
fa9a6fed 2115
c165541e 2116 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
fa9a6fed 2117 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710
AK		 2118 req->params.offset = cpu_to_le32(offset);
2119 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2120
2121 status = be_mcc_notify_wait(adapter);
2122 if (!status)
2123 memcpy(flashed_crc, req->params.data_buf, 4);
2124
713d0394 2125err:
fa9a6fed
SB		 2126 spin_unlock_bh(&adapter->mcc_lock);
2127 return status;
2128}
71d8d1b5 2129
c196b02c 2130int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
71d8d1b5
AK		 2131 struct be_dma_mem *nonemb_cmd)
2132{
2133 struct be_mcc_wrb *wrb;
2134 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2135 int status;
2136
2137 spin_lock_bh(&adapter->mcc_lock);
2138
2139 wrb = wrb_from_mccq(adapter);
2140 if (!wrb) {
2141 status = -EBUSY;
2142 goto err;
2143 }
2144 req = nonemb_cmd->va;
71d8d1b5 2145
106df1e3
SK		 2146 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2147 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2148 nonemb_cmd);
71d8d1b5
AK		 2149 memcpy(req->magic_mac, mac, ETH_ALEN);
2150
71d8d1b5
AK		 2151 status = be_mcc_notify_wait(adapter);
2152
2153err:
2154 spin_unlock_bh(&adapter->mcc_lock);
2155 return status;
2156}
ff33a6e2 2157
fced9999
SB		 2158int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2159 u8 loopback_type, u8 enable)
2160{
2161 struct be_mcc_wrb *wrb;
2162 struct be_cmd_req_set_lmode *req;
2163 int status;
2164
2165 spin_lock_bh(&adapter->mcc_lock);
2166
2167 wrb = wrb_from_mccq(adapter);
2168 if (!wrb) {
2169 status = -EBUSY;
2170 goto err;
2171 }
2172
2173 req = embedded_payload(wrb);
2174
106df1e3
SK		 2175 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2176 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2177 NULL);
fced9999
SB		 2178
2179 req->src_port = port_num;
2180 req->dest_port = port_num;
2181 req->loopback_type = loopback_type;
2182 req->loopback_state = enable;
2183
2184 status = be_mcc_notify_wait(adapter);
2185err:
2186 spin_unlock_bh(&adapter->mcc_lock);
2187 return status;
2188}
2189
ff33a6e2
S		 2190int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2191 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2192{
2193 struct be_mcc_wrb *wrb;
2194 struct be_cmd_req_loopback_test *req;
2195 int status;
2196
2197 spin_lock_bh(&adapter->mcc_lock);
2198
2199 wrb = wrb_from_mccq(adapter);
2200 if (!wrb) {
2201 status = -EBUSY;
2202 goto err;
2203 }
2204
2205 req = embedded_payload(wrb);
2206
106df1e3
SK		 2207 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2208 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
3ffd0515 2209 req->hdr.timeout = cpu_to_le32(4);
ff33a6e2
S		 2210
2211 req->pattern = cpu_to_le64(pattern);
2212 req->src_port = cpu_to_le32(port_num);
2213 req->dest_port = cpu_to_le32(port_num);
2214 req->pkt_size = cpu_to_le32(pkt_size);
2215 req->num_pkts = cpu_to_le32(num_pkts);
2216 req->loopback_type = cpu_to_le32(loopback_type);
2217
2218 status = be_mcc_notify_wait(adapter);
2219 if (!status) {
2220 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2221 status = le32_to_cpu(resp->status);
2222 }
2223
2224err:
2225 spin_unlock_bh(&adapter->mcc_lock);
2226 return status;
2227}
2228
2229int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2230 u32 byte_cnt, struct be_dma_mem *cmd)
2231{
2232 struct be_mcc_wrb *wrb;
2233 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2234 int status;
2235 int i, j = 0;
2236
2237 spin_lock_bh(&adapter->mcc_lock);
2238
2239 wrb = wrb_from_mccq(adapter);
2240 if (!wrb) {
2241 status = -EBUSY;
2242 goto err;
2243 }
2244 req = cmd->va;
106df1e3
SK		 2245 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2246 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
ff33a6e2
S		 2247
2248 req->pattern = cpu_to_le64(pattern);
2249 req->byte_count = cpu_to_le32(byte_cnt);
2250 for (i = 0; i < byte_cnt; i++) {
2251 req->snd_buff[i] = (u8)(pattern >> (j*8));
2252 j++;
2253 if (j > 7)
2254 j = 0;
2255 }
2256
2257 status = be_mcc_notify_wait(adapter);
2258
2259 if (!status) {
2260 struct be_cmd_resp_ddrdma_test *resp;
2261 resp = cmd->va;
2262 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2263 resp->snd_err) {
2264 status = -1;
2265 }
2266 }
2267
2268err:
2269 spin_unlock_bh(&adapter->mcc_lock);
2270 return status;
2271}
368c0ca2 2272
c196b02c 2273int be_cmd_get_seeprom_data(struct be_adapter *adapter,
368c0ca2
SB		 2274 struct be_dma_mem *nonemb_cmd)
2275{
2276 struct be_mcc_wrb *wrb;
2277 struct be_cmd_req_seeprom_read *req;
2278 struct be_sge *sge;
2279 int status;
2280
2281 spin_lock_bh(&adapter->mcc_lock);
2282
2283 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2284 if (!wrb) {
2285 status = -EBUSY;
2286 goto err;
2287 }
368c0ca2
SB		 2288 req = nonemb_cmd->va;
2289 sge = nonembedded_sgl(wrb);
2290
106df1e3
SK		 2291 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2292 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2293 nonemb_cmd);
368c0ca2
SB		 2294
2295 status = be_mcc_notify_wait(adapter);
2296
e45ff01d 2297err:
368c0ca2
SB		 2298 spin_unlock_bh(&adapter->mcc_lock);
2299 return status;
2300}
ee3cb629 2301
42f11cf2 2302int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2303{
2304 struct be_mcc_wrb *wrb;
2305 struct be_cmd_req_get_phy_info *req;
306f1348 2306 struct be_dma_mem cmd;
ee3cb629
AK		 2307 int status;
2308
2309 spin_lock_bh(&adapter->mcc_lock);
2310
2311 wrb = wrb_from_mccq(adapter);
2312 if (!wrb) {
2313 status = -EBUSY;
2314 goto err;
2315 }
306f1348
SP		 2316 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2317 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2318 &cmd.dma);
2319 if (!cmd.va) {
2320 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2321 status = -ENOMEM;
2322 goto err;
2323 }
ee3cb629 2324
306f1348 2325 req = cmd.va;
ee3cb629 2326
106df1e3
SK		 2327 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2328 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2329 wrb, &cmd);
ee3cb629
AK		 2330
2331 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2332 if (!status) {
2333 struct be_phy_info *resp_phy_info =
2334 cmd.va + sizeof(struct be_cmd_req_hdr);
42f11cf2
AK		 2335 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2336 adapter->phy.interface_type =
306f1348 2337 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2338 adapter->phy.auto_speeds_supported =
2339 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2340 adapter->phy.fixed_speeds_supported =
2341 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2342 adapter->phy.misc_params =
2343 le32_to_cpu(resp_phy_info->misc_params);
306f1348
SP		 2344 }
2345 pci_free_consistent(adapter->pdev, cmd.size,
2346 cmd.va, cmd.dma);
ee3cb629
AK		 2347err:
2348 spin_unlock_bh(&adapter->mcc_lock);
2349 return status;
2350}
e1d18735
AK		 2351
2352int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2353{
2354 struct be_mcc_wrb *wrb;
2355 struct be_cmd_req_set_qos *req;
2356 int status;
2357
2358 spin_lock_bh(&adapter->mcc_lock);
2359
2360 wrb = wrb_from_mccq(adapter);
2361 if (!wrb) {
2362 status = -EBUSY;
2363 goto err;
2364 }
2365
2366 req = embedded_payload(wrb);
2367
106df1e3
SK		 2368 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2369 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2370
2371 req->hdr.domain = domain;
6bff57a7
AK		 2372 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2373 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2374
2375 status = be_mcc_notify_wait(adapter);
2376
2377err:
2378 spin_unlock_bh(&adapter->mcc_lock);
2379 return status;
2380}
9e1453c5
AK		 2381
2382int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2383{
2384 struct be_mcc_wrb *wrb;
2385 struct be_cmd_req_cntl_attribs *req;
2386 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2387 int status;
2388 int payload_len = max(sizeof(*req), sizeof(*resp));
2389 struct mgmt_controller_attrib *attribs;
2390 struct be_dma_mem attribs_cmd;
2391
2392 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2393 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2394 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2395 &attribs_cmd.dma);
2396 if (!attribs_cmd.va) {
2397 dev_err(&adapter->pdev->dev,
2398 "Memory allocation failure\n");
2399 return -ENOMEM;
2400 }
2401
2402 if (mutex_lock_interruptible(&adapter->mbox_lock))
2403 return -1;
2404
2405 wrb = wrb_from_mbox(adapter);
2406 if (!wrb) {
2407 status = -EBUSY;
2408 goto err;
2409 }
2410 req = attribs_cmd.va;
9e1453c5 2411
106df1e3
SK		 2412 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2413 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2414 &attribs_cmd);
9e1453c5
AK		 2415
2416 status = be_mbox_notify_wait(adapter);
2417 if (!status) {
43d620c8 2418 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2419 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2420 }
2421
2422err:
2423 mutex_unlock(&adapter->mbox_lock);
2424 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2425 attribs_cmd.dma);
2426 return status;
2427}
2e588f84
SP		 2428
2429/* Uses mbox */
2dc1deb6 2430int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2431{
2432 struct be_mcc_wrb *wrb;
2433 struct be_cmd_req_set_func_cap *req;
2434 int status;
2435
2436 if (mutex_lock_interruptible(&adapter->mbox_lock))
2437 return -1;
2438
2439 wrb = wrb_from_mbox(adapter);
2440 if (!wrb) {
2441 status = -EBUSY;
2442 goto err;
2443 }
2444
2445 req = embedded_payload(wrb);
2446
106df1e3
SK		 2447 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2448 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2e588f84
SP		 2449
2450 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2451 CAPABILITY_BE3_NATIVE_ERX_API);
2452 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2453
2454 status = be_mbox_notify_wait(adapter);
2455 if (!status) {
2456 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2457 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2458 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 2459 if (!adapter->be3_native)
2460 dev_warn(&adapter->pdev->dev,
2461 "adapter not in advanced mode\n");
2e588f84
SP		 2462 }
2463err:
2464 mutex_unlock(&adapter->mbox_lock);
2465 return status;
2466}
590c391d
PR		 2467
2468/* Uses synchronous MCCQ */
1578e777
PR		 2469int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2470 bool *pmac_id_active, u32 *pmac_id, u8 domain)
590c391d
PR		 2471{
2472 struct be_mcc_wrb *wrb;
2473 struct be_cmd_req_get_mac_list *req;
2474 int status;
2475 int mac_count;
e5e1ee89
PR		 2476 struct be_dma_mem get_mac_list_cmd;
2477 int i;
2478
2479 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2480 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2481 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2482 get_mac_list_cmd.size,
2483 &get_mac_list_cmd.dma);
2484
2485 if (!get_mac_list_cmd.va) {
2486 dev_err(&adapter->pdev->dev,
2487 "Memory allocation failure during GET_MAC_LIST\n");
2488 return -ENOMEM;
2489 }
590c391d
PR		 2490
2491 spin_lock_bh(&adapter->mcc_lock);
2492
2493 wrb = wrb_from_mccq(adapter);
2494 if (!wrb) {
2495 status = -EBUSY;
e5e1ee89 2496 goto out;
590c391d 2497 }
e5e1ee89
PR		 2498
2499 req = get_mac_list_cmd.va;
590c391d
PR		 2500
2501 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2502 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
e5e1ee89 2503 wrb, &get_mac_list_cmd);
590c391d
PR		 2504
2505 req->hdr.domain = domain;
e5e1ee89
PR		 2506 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2507 req->perm_override = 1;
590c391d
PR		 2508
2509 status = be_mcc_notify_wait(adapter);
2510 if (!status) {
2511 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89
PR		 2512 get_mac_list_cmd.va;
2513 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2514 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 2515 * or one or more true or pseudo permanant mac addresses.
2516 * If an active mac_id is present, return first active mac_id
2517 * found.
e5e1ee89 2518 */
590c391d 2519 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 2520 struct get_list_macaddr *mac_entry;
2521 u16 mac_addr_size;
2522 u32 mac_id;
2523
2524 mac_entry = &resp->macaddr_list[i];
2525 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2526 /* mac_id is a 32 bit value and mac_addr size
2527 * is 6 bytes
2528 */
2529 if (mac_addr_size == sizeof(u32)) {
2530 *pmac_id_active = true;
2531 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2532 *pmac_id = le32_to_cpu(mac_id);
2533 goto out;
590c391d 2534 }
590c391d 2535 }
1578e777 2536 /* If no active mac_id found, return first mac addr */
e5e1ee89
PR		 2537 *pmac_id_active = false;
2538 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2539 ETH_ALEN);
590c391d
PR		 2540 }
2541
e5e1ee89 2542out:
590c391d 2543 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89
PR		 2544 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2545 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 2546 return status;
2547}
2548
2549/* Uses synchronous MCCQ */
2550int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2551 u8 mac_count, u32 domain)
2552{
2553 struct be_mcc_wrb *wrb;
2554 struct be_cmd_req_set_mac_list *req;
2555 int status;
2556 struct be_dma_mem cmd;
2557
2558 memset(&cmd, 0, sizeof(struct be_dma_mem));
2559 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2560 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2561 &cmd.dma, GFP_KERNEL);
2562 if (!cmd.va) {
2563 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2564 return -ENOMEM;
2565 }
2566
2567 spin_lock_bh(&adapter->mcc_lock);
2568
2569 wrb = wrb_from_mccq(adapter);
2570 if (!wrb) {
2571 status = -EBUSY;
2572 goto err;
2573 }
2574
2575 req = cmd.va;
2576 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2577 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2578 wrb, &cmd);
2579
2580 req->hdr.domain = domain;
2581 req->mac_count = mac_count;
2582 if (mac_count)
2583 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2584
2585 status = be_mcc_notify_wait(adapter);
2586
2587err:
2588 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2589 cmd.va, cmd.dma);
2590 spin_unlock_bh(&adapter->mcc_lock);
2591 return status;
2592}
4762f6ce 2593
f1f3ee1b
AK		 2594int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2595 u32 domain, u16 intf_id)
2596{
2597 struct be_mcc_wrb *wrb;
2598 struct be_cmd_req_set_hsw_config *req;
2599 void *ctxt;
2600 int status;
2601
2602 spin_lock_bh(&adapter->mcc_lock);
2603
2604 wrb = wrb_from_mccq(adapter);
2605 if (!wrb) {
2606 status = -EBUSY;
2607 goto err;
2608 }
2609
2610 req = embedded_payload(wrb);
2611 ctxt = &req->context;
2612
2613 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2614 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2615
2616 req->hdr.domain = domain;
2617 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2618 if (pvid) {
2619 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2620 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2621 }
2622
2623 be_dws_cpu_to_le(req->context, sizeof(req->context));
2624 status = be_mcc_notify_wait(adapter);
2625
2626err:
2627 spin_unlock_bh(&adapter->mcc_lock);
2628 return status;
2629}
2630
2631/* Get Hyper switch config */
2632int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2633 u32 domain, u16 intf_id)
2634{
2635 struct be_mcc_wrb *wrb;
2636 struct be_cmd_req_get_hsw_config *req;
2637 void *ctxt;
2638 int status;
2639 u16 vid;
2640
2641 spin_lock_bh(&adapter->mcc_lock);
2642
2643 wrb = wrb_from_mccq(adapter);
2644 if (!wrb) {
2645 status = -EBUSY;
2646 goto err;
2647 }
2648
2649 req = embedded_payload(wrb);
2650 ctxt = &req->context;
2651
2652 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2653 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2654
2655 req->hdr.domain = domain;
2656 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2657 intf_id);
2658 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2659 be_dws_cpu_to_le(req->context, sizeof(req->context));
2660
2661 status = be_mcc_notify_wait(adapter);
2662 if (!status) {
2663 struct be_cmd_resp_get_hsw_config *resp =
2664 embedded_payload(wrb);
2665 be_dws_le_to_cpu(&resp->context,
2666 sizeof(resp->context));
2667 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2668 pvid, &resp->context);
2669 *pvid = le16_to_cpu(vid);
2670 }
2671
2672err:
2673 spin_unlock_bh(&adapter->mcc_lock);
2674 return status;
2675}
2676
4762f6ce
AK		 2677int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2678{
2679 struct be_mcc_wrb *wrb;
2680 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2681 int status;
2682 int payload_len = sizeof(*req);
2683 struct be_dma_mem cmd;
2684
2685 memset(&cmd, 0, sizeof(struct be_dma_mem));
2686 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2687 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2688 &cmd.dma);
2689 if (!cmd.va) {
2690 dev_err(&adapter->pdev->dev,
2691 "Memory allocation failure\n");
2692 return -ENOMEM;
2693 }
2694
2695 if (mutex_lock_interruptible(&adapter->mbox_lock))
2696 return -1;
2697
2698 wrb = wrb_from_mbox(adapter);
2699 if (!wrb) {
2700 status = -EBUSY;
2701 goto err;
2702 }
2703
2704 req = cmd.va;
2705
2706 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2707 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2708 payload_len, wrb, &cmd);
2709
2710 req->hdr.version = 1;
2711 req->query_options = BE_GET_WOL_CAP;
2712
2713 status = be_mbox_notify_wait(adapter);
2714 if (!status) {
2715 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2716 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2717
2718 /* the command could succeed misleadingly on old f/w
2719 * which is not aware of the V1 version. fake an error. */
2720 if (resp->hdr.response_length < payload_len) {
2721 status = -1;
2722 goto err;
2723 }
2724 adapter->wol_cap = resp->wol_settings;
2725 }
2726err:
2727 mutex_unlock(&adapter->mbox_lock);
2728 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2729 return status;
941a77d5
SK		 2730
2731}
2732int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2733 struct be_dma_mem *cmd)
2734{
2735 struct be_mcc_wrb *wrb;
2736 struct be_cmd_req_get_ext_fat_caps *req;
2737 int status;
2738
2739 if (mutex_lock_interruptible(&adapter->mbox_lock))
2740 return -1;
2741
2742 wrb = wrb_from_mbox(adapter);
2743 if (!wrb) {
2744 status = -EBUSY;
2745 goto err;
2746 }
2747
2748 req = cmd->va;
2749 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2750 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2751 cmd->size, wrb, cmd);
2752 req->parameter_type = cpu_to_le32(1);
2753
2754 status = be_mbox_notify_wait(adapter);
2755err:
2756 mutex_unlock(&adapter->mbox_lock);
2757 return status;
2758}
2759
2760int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2761 struct be_dma_mem *cmd,
2762 struct be_fat_conf_params *configs)
2763{
2764 struct be_mcc_wrb *wrb;
2765 struct be_cmd_req_set_ext_fat_caps *req;
2766 int status;
2767
2768 spin_lock_bh(&adapter->mcc_lock);
2769
2770 wrb = wrb_from_mccq(adapter);
2771 if (!wrb) {
2772 status = -EBUSY;
2773 goto err;
2774 }
2775
2776 req = cmd->va;
2777 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2778 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2779 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2780 cmd->size, wrb, cmd);
2781
2782 status = be_mcc_notify_wait(adapter);
2783err:
2784 spin_unlock_bh(&adapter->mcc_lock);
2785 return status;
4762f6ce 2786}
6a4ab669 2787
b4e32a71
PR		 2788int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2789{
2790 struct be_mcc_wrb *wrb;
2791 struct be_cmd_req_get_port_name *req;
2792 int status;
2793
2794 if (!lancer_chip(adapter)) {
2795 *port_name = adapter->hba_port_num + '0';
2796 return 0;
2797 }
2798
2799 spin_lock_bh(&adapter->mcc_lock);
2800
2801 wrb = wrb_from_mccq(adapter);
2802 if (!wrb) {
2803 status = -EBUSY;
2804 goto err;
2805 }
2806
2807 req = embedded_payload(wrb);
2808
2809 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2810 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2811 NULL);
2812 req->hdr.version = 1;
2813
2814 status = be_mcc_notify_wait(adapter);
2815 if (!status) {
2816 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2817 *port_name = resp->port_name[adapter->hba_port_num];
2818 } else {
2819 *port_name = adapter->hba_port_num + '0';
2820 }
2821err:
2822 spin_unlock_bh(&adapter->mcc_lock);
2823 return status;
2824}
2825
abb93951
PR		 2826static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
2827 u32 max_buf_size)
2828{
2829 struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
2830 int i;
2831
2832 for (i = 0; i < desc_count; i++) {
2833 desc->desc_len = RESOURCE_DESC_SIZE;
2834 if (((void *)desc + desc->desc_len) >
2835 (void *)(buf + max_buf_size)) {
2836 desc = NULL;
2837 break;
2838 }
2839
2840 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_ID)
2841 break;
2842
2843 desc = (void *)desc + desc->desc_len;
2844 }
2845
2846 if (!desc || i == MAX_RESOURCE_DESC)
2847 return NULL;
2848
2849 return desc;
2850}
2851
2852/* Uses Mbox */
2853int be_cmd_get_func_config(struct be_adapter *adapter)
2854{
2855 struct be_mcc_wrb *wrb;
2856 struct be_cmd_req_get_func_config *req;
2857 int status;
2858 struct be_dma_mem cmd;
2859
2860 memset(&cmd, 0, sizeof(struct be_dma_mem));
2861 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
2862 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2863 &cmd.dma);
2864 if (!cmd.va) {
2865 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2866 return -ENOMEM;
2867 }
2868 if (mutex_lock_interruptible(&adapter->mbox_lock))
2869 return -1;
2870
2871 wrb = wrb_from_mbox(adapter);
2872 if (!wrb) {
2873 status = -EBUSY;
2874 goto err;
2875 }
2876
2877 req = cmd.va;
2878
2879 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2880 OPCODE_COMMON_GET_FUNC_CONFIG,
2881 cmd.size, wrb, &cmd);
2882
2883 status = be_mbox_notify_wait(adapter);
2884 if (!status) {
2885 struct be_cmd_resp_get_func_config *resp = cmd.va;
2886 u32 desc_count = le32_to_cpu(resp->desc_count);
2887 struct be_nic_resource_desc *desc;
2888
2889 desc = be_get_nic_desc(resp->func_param, desc_count,
2890 sizeof(resp->func_param));
2891 if (!desc) {
2892 status = -EINVAL;
2893 goto err;
2894 }
2895
d5c18473 2896 adapter->pf_number = desc->pf_num;
abb93951
PR		 2897 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
2898 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
2899 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
2900 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
2901 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
2902 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
2903
2904 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
2905 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
2906 }
2907err:
2908 mutex_unlock(&adapter->mbox_lock);
2909 pci_free_consistent(adapter->pdev, cmd.size,
2910 cmd.va, cmd.dma);
2911 return status;
2912}
2913
2914 /* Uses sync mcc */
2915int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
2916 u8 domain)
2917{
2918 struct be_mcc_wrb *wrb;
2919 struct be_cmd_req_get_profile_config *req;
2920 int status;
2921 struct be_dma_mem cmd;
2922
2923 memset(&cmd, 0, sizeof(struct be_dma_mem));
2924 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
2925 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2926 &cmd.dma);
2927 if (!cmd.va) {
2928 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2929 return -ENOMEM;
2930 }
2931
2932 spin_lock_bh(&adapter->mcc_lock);
2933
2934 wrb = wrb_from_mccq(adapter);
2935 if (!wrb) {
2936 status = -EBUSY;
2937 goto err;
2938 }
2939
2940 req = cmd.va;
2941
2942 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2943 OPCODE_COMMON_GET_PROFILE_CONFIG,
2944 cmd.size, wrb, &cmd);
2945
2946 req->type = ACTIVE_PROFILE_TYPE;
2947 req->hdr.domain = domain;
2948
2949 status = be_mcc_notify_wait(adapter);
2950 if (!status) {
2951 struct be_cmd_resp_get_profile_config *resp = cmd.va;
2952 u32 desc_count = le32_to_cpu(resp->desc_count);
2953 struct be_nic_resource_desc *desc;
2954
2955 desc = be_get_nic_desc(resp->func_param, desc_count,
2956 sizeof(resp->func_param));
2957
2958 if (!desc) {
2959 status = -EINVAL;
2960 goto err;
2961 }
2962 *cap_flags = le32_to_cpu(desc->cap_flags);
2963 }
2964err:
2965 spin_unlock_bh(&adapter->mcc_lock);
2966 pci_free_consistent(adapter->pdev, cmd.size,
2967 cmd.va, cmd.dma);
2968 return status;
2969}
2970
d5c18473
PR		 2971/* Uses sync mcc */
2972int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
2973 u8 domain)
2974{
2975 struct be_mcc_wrb *wrb;
2976 struct be_cmd_req_set_profile_config *req;
2977 int status;
2978
2979 spin_lock_bh(&adapter->mcc_lock);
2980
2981 wrb = wrb_from_mccq(adapter);
2982 if (!wrb) {
2983 status = -EBUSY;
2984 goto err;
2985 }
2986
2987 req = embedded_payload(wrb);
2988
2989 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2990 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
2991 wrb, NULL);
2992
2993 req->hdr.domain = domain;
2994 req->desc_count = cpu_to_le32(1);
2995
2996 req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_ID;
2997 req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
2998 req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
2999 req->nic_desc.pf_num = adapter->pf_number;
3000 req->nic_desc.vf_num = domain;
3001
3002 /* Mark fields invalid */
3003 req->nic_desc.unicast_mac_count = 0xFFFF;
3004 req->nic_desc.mcc_count = 0xFFFF;
3005 req->nic_desc.vlan_count = 0xFFFF;
3006 req->nic_desc.mcast_mac_count = 0xFFFF;
3007 req->nic_desc.txq_count = 0xFFFF;
3008 req->nic_desc.rq_count = 0xFFFF;
3009 req->nic_desc.rssq_count = 0xFFFF;
3010 req->nic_desc.lro_count = 0xFFFF;
3011 req->nic_desc.cq_count = 0xFFFF;
3012 req->nic_desc.toe_conn_count = 0xFFFF;
3013 req->nic_desc.eq_count = 0xFFFF;
3014 req->nic_desc.link_param = 0xFF;
3015 req->nic_desc.bw_min = 0xFFFFFFFF;
3016 req->nic_desc.acpi_params = 0xFF;
3017 req->nic_desc.wol_param = 0x0F;
3018
3019 /* Change BW */
3020 req->nic_desc.bw_min = cpu_to_le32(bps);
3021 req->nic_desc.bw_max = cpu_to_le32(bps);
3022 status = be_mcc_notify_wait(adapter);
3023err:
3024 spin_unlock_bh(&adapter->mcc_lock);
3025 return status;
3026}
3027
6a4ab669
PP		 3028int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3029 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3030{
3031 struct be_adapter *adapter = netdev_priv(netdev_handle);
3032 struct be_mcc_wrb *wrb;
3033 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3034 struct be_cmd_req_hdr *req;
3035 struct be_cmd_resp_hdr *resp;
3036 int status;
3037
3038 spin_lock_bh(&adapter->mcc_lock);
3039
3040 wrb = wrb_from_mccq(adapter);
3041 if (!wrb) {
3042 status = -EBUSY;
3043 goto err;
3044 }
3045 req = embedded_payload(wrb);
3046 resp = embedded_payload(wrb);
3047
3048 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3049 hdr->opcode, wrb_payload_size, wrb, NULL);
3050 memcpy(req, wrb_payload, wrb_payload_size);
3051 be_dws_cpu_to_le(req, wrb_payload_size);
3052
3053 status = be_mcc_notify_wait(adapter);
3054 if (cmd_status)
3055 *cmd_status = (status & 0xffff);
3056 if (ext_status)
3057 *ext_status = 0;
3058 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3059 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3060err:
3061 spin_unlock_bh(&adapter->mcc_lock);
3062 return status;
3063}
3064EXPORT_SYMBOL(be_roce_mcc_cmd);
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