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ipv4: PKTINFO doesnt need dst reference
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
6b7c5b94 20
609ff3bb 21/* Must be a power of 2 or else MODULO will BUG_ON */
3de09455
SK		 22static int be_get_temp_freq = 64;
23
24static inline void *embedded_payload(struct be_mcc_wrb *wrb)
25{
26 return wrb->payload.embedded_payload;
27}
609ff3bb 28
8788fdc2 29static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 30{
8788fdc2 31 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 32 u32 val = 0;
33
7acc2087
AK		 34 if (adapter->eeh_err) {
35 dev_info(&adapter->pdev->dev,
36 "Error in Card Detected! Cannot issue commands\n");
37 return;
38 }
39
5fb379ee
SP		 40 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
41 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 42
43 wmb();
8788fdc2 44 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 45}
46
47/* To check if valid bit is set, check the entire word as we don't know
48 * the endianness of the data (old entry is host endian while a new entry is
49 * little endian) */
efd2e40a 50static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee
SP		 51{
52 if (compl->flags != 0) {
53 compl->flags = le32_to_cpu(compl->flags);
54 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
55 return true;
56 } else {
57 return false;
58 }
59}
60
61/* Need to reset the entire word that houses the valid bit */
efd2e40a 62static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 63{
64 compl->flags = 0;
65}
66
8788fdc2 67static int be_mcc_compl_process(struct be_adapter *adapter,
efd2e40a 68 struct be_mcc_compl *compl)
5fb379ee
SP		 69{
70 u16 compl_status, extd_status;
71
72 /* Just swap the status to host endian; mcc tag is opaquely copied
73 * from mcc_wrb */
74 be_dws_le_to_cpu(compl, 4);
75
76 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
77 CQE_STATUS_COMPL_MASK;
dd131e76 78
485bf569
SN		 79 if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
80 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
dd131e76
SB		 81 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
82 adapter->flash_status = compl_status;
83 complete(&adapter->flash_compl);
84 }
85
b31c50a7 86 if (compl_status == MCC_STATUS_SUCCESS) {
005d5696
SX		 87 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
88 (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
6349935b 89 (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
89a88ab8 90 be_parse_stats(adapter);
b2aebe6d 91 adapter->stats_cmd_sent = false;
b31c50a7 92 }
3de09455
SK		 93 if (compl->tag0 ==
94 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) {
95 struct be_mcc_wrb *mcc_wrb =
96 queue_index_node(&adapter->mcc_obj.q,
97 compl->tag1);
98 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
99 embedded_payload(mcc_wrb);
100 adapter->drv_stats.be_on_die_temperature =
101 resp->on_die_temperature;
102 }
2b3f291b 103 } else {
3de09455
SK		 104 if (compl->tag0 == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
105 be_get_temp_freq = 0;
106
2b3f291b
SP		 107 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
108 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
109 goto done;
110
111 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
112 dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
113 "permitted to execute this cmd (opcode %d)\n",
114 compl->tag0);
115 } else {
116 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
117 CQE_STATUS_EXTD_MASK;
118 dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
119 "status %d, extd-status %d\n",
120 compl->tag0, compl_status, extd_status);
121 }
5fb379ee 122 }
2b3f291b 123done:
b31c50a7 124 return compl_status;
5fb379ee
SP		 125}
126
a8f447bd 127/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 128static void be_async_link_state_process(struct be_adapter *adapter,
a8f447bd
SP		 129 struct be_async_event_link_state *evt)
130{
ea172a01 131 be_link_status_update(adapter, evt->port_link_status);
a8f447bd
SP		 132}
133
cc4ce020
SK		 134/* Grp5 CoS Priority evt */
135static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
136 struct be_async_event_grp5_cos_priority *evt)
137{
138 if (evt->valid) {
139 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 140 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 141 adapter->recommended_prio =
142 evt->reco_default_priority << VLAN_PRIO_SHIFT;
143 }
144}
145
146/* Grp5 QOS Speed evt */
147static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
148 struct be_async_event_grp5_qos_link_speed *evt)
149{
150 if (evt->physical_port == adapter->port_num) {
151 /* qos_link_speed is in units of 10 Mbps */
152 adapter->link_speed = evt->qos_link_speed * 10;
153 }
154}
155
3968fa1e
AK		 156/*Grp5 PVID evt*/
157static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
158 struct be_async_event_grp5_pvid_state *evt)
159{
160 if (evt->enabled)
939cf306 161 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
3968fa1e
AK		 162 else
163 adapter->pvid = 0;
164}
165
cc4ce020
SK		 166static void be_async_grp5_evt_process(struct be_adapter *adapter,
167 u32 trailer, struct be_mcc_compl *evt)
168{
169 u8 event_type = 0;
170
171 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
172 ASYNC_TRAILER_EVENT_TYPE_MASK;
173
174 switch (event_type) {
175 case ASYNC_EVENT_COS_PRIORITY:
176 be_async_grp5_cos_priority_process(adapter,
177 (struct be_async_event_grp5_cos_priority *)evt);
178 break;
179 case ASYNC_EVENT_QOS_SPEED:
180 be_async_grp5_qos_speed_process(adapter,
181 (struct be_async_event_grp5_qos_link_speed *)evt);
182 break;
3968fa1e
AK		 183 case ASYNC_EVENT_PVID_STATE:
184 be_async_grp5_pvid_state_process(adapter,
185 (struct be_async_event_grp5_pvid_state *)evt);
186 break;
cc4ce020
SK		 187 default:
188 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
189 break;
190 }
191}
192
a8f447bd
SP		 193static inline bool is_link_state_evt(u32 trailer)
194{
807540ba 195 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
a8f447bd 196 ASYNC_TRAILER_EVENT_CODE_MASK) ==
807540ba 197 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 198}
5fb379ee 199
cc4ce020
SK		 200static inline bool is_grp5_evt(u32 trailer)
201{
202 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
203 ASYNC_TRAILER_EVENT_CODE_MASK) ==
204 ASYNC_EVENT_CODE_GRP_5);
205}
206
efd2e40a 207static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 208{
8788fdc2 209 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 210 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 211
212 if (be_mcc_compl_is_new(compl)) {
213 queue_tail_inc(mcc_cq);
214 return compl;
215 }
216 return NULL;
217}
218
7a1e9b20
SP		 219void be_async_mcc_enable(struct be_adapter *adapter)
220{
221 spin_lock_bh(&adapter->mcc_cq_lock);
222
223 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
224 adapter->mcc_obj.rearm_cq = true;
225
226 spin_unlock_bh(&adapter->mcc_cq_lock);
227}
228
229void be_async_mcc_disable(struct be_adapter *adapter)
230{
231 adapter->mcc_obj.rearm_cq = false;
232}
233
f31e50a8 234int be_process_mcc(struct be_adapter *adapter, int *status)
5fb379ee 235{
efd2e40a 236 struct be_mcc_compl *compl;
f31e50a8 237 int num = 0;
7a1e9b20 238 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 239
8788fdc2
SP		 240 spin_lock_bh(&adapter->mcc_cq_lock);
241 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd
SP		 242 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
243 /* Interpret flags as an async trailer */
323f30b3
AK		 244 if (is_link_state_evt(compl->flags))
245 be_async_link_state_process(adapter,
a8f447bd 246 (struct be_async_event_link_state *) compl);
cc4ce020
SK		 247 else if (is_grp5_evt(compl->flags))
248 be_async_grp5_evt_process(adapter,
249 compl->flags, compl);
b31c50a7 250 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
f31e50a8 251 *status = be_mcc_compl_process(adapter, compl);
7a1e9b20 252 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 253 }
254 be_mcc_compl_use(compl);
255 num++;
256 }
b31c50a7 257
8788fdc2 258 spin_unlock_bh(&adapter->mcc_cq_lock);
f31e50a8 259 return num;
5fb379ee
SP		 260}
261
6ac7b687 262/* Wait till no more pending mcc requests are present */
b31c50a7 263static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 264{
b31c50a7 265#define mcc_timeout 120000 /* 12s timeout */
f31e50a8
SP		 266 int i, num, status = 0;
267 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
268
7acc2087
AK		 269 if (adapter->eeh_err)
270 return -EIO;
271
6ac7b687 272 for (i = 0; i < mcc_timeout; i++) {
f31e50a8
SP		 273 num = be_process_mcc(adapter, &status);
274 if (num)
275 be_cq_notify(adapter, mcc_obj->cq.id,
276 mcc_obj->rearm_cq, num);
b31c50a7 277
f31e50a8 278 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 279 break;
280 udelay(100);
281 }
b31c50a7 282 if (i == mcc_timeout) {
5f0b849e 283 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
b31c50a7
SP		 284 return -1;
285 }
f31e50a8 286 return status;
6ac7b687
SP		 287}
288
289/* Notify MCC requests and wait for completion */
b31c50a7 290static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 291{
8788fdc2 292 be_mcc_notify(adapter);
b31c50a7 293 return be_mcc_wait_compl(adapter);
6ac7b687
SP		 294}
295
5f0b849e 296static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 297{
f25b03a7 298 int msecs = 0;
6b7c5b94
SP		 299 u32 ready;
300
7acc2087
AK		 301 if (adapter->eeh_err) {
302 dev_err(&adapter->pdev->dev,
303 "Error detected in card.Cannot issue commands\n");
304 return -EIO;
305 }
306
6b7c5b94 307 do {
cf588477
SP		 308 ready = ioread32(db);
309 if (ready == 0xffffffff) {
310 dev_err(&adapter->pdev->dev,
311 "pci slot disconnected\n");
312 return -1;
313 }
314
315 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 316 if (ready)
317 break;
318
f25b03a7 319 if (msecs > 4000) {
5f0b849e 320 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
e1cfb67a 321 be_detect_dump_ue(adapter);
6b7c5b94
SP		 322 return -1;
323 }
324
1dbf53a2 325 msleep(1);
f25b03a7 326 msecs++;
6b7c5b94
SP		 327 } while (true);
328
329 return 0;
330}
331
332/*
333 * Insert the mailbox address into the doorbell in two steps
5fb379ee 334 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 335 */
b31c50a7 336static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 337{
338 int status;
6b7c5b94 339 u32 val = 0;
8788fdc2
SP		 340 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
341 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 342 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 343 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 344
cf588477
SP		 345 /* wait for ready to be set */
346 status = be_mbox_db_ready_wait(adapter, db);
347 if (status != 0)
348 return status;
349
6b7c5b94
SP		 350 val |= MPU_MAILBOX_DB_HI_MASK;
351 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
352 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
353 iowrite32(val, db);
354
355 /* wait for ready to be set */
5f0b849e 356 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 357 if (status != 0)
358 return status;
359
360 val = 0;
6b7c5b94
SP		 361 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
362 val |= (u32)(mbox_mem->dma >> 4) << 2;
363 iowrite32(val, db);
364
5f0b849e 365 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 366 if (status != 0)
367 return status;
368
5fb379ee 369 /* A cq entry has been made now */
efd2e40a
SP		 370 if (be_mcc_compl_is_new(compl)) {
371 status = be_mcc_compl_process(adapter, &mbox->compl);
372 be_mcc_compl_use(compl);
5fb379ee
SP		 373 if (status)
374 return status;
375 } else {
5f0b849e 376 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 377 return -1;
378 }
5fb379ee 379 return 0;
6b7c5b94
SP		 380}
381
8788fdc2 382static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
6b7c5b94 383{
fe6d2a38
SP		 384 u32 sem;
385
386 if (lancer_chip(adapter))
387 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
388 else
389 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
6b7c5b94
SP		 390
391 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
392 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
393 return -1;
394 else
395 return 0;
396}
397
8788fdc2 398int be_cmd_POST(struct be_adapter *adapter)
6b7c5b94 399{
43a04fdc
SP		 400 u16 stage;
401 int status, timeout = 0;
6ed35eea 402 struct device *dev = &adapter->pdev->dev;
6b7c5b94 403
43a04fdc
SP		 404 do {
405 status = be_POST_stage_get(adapter, &stage);
406 if (status) {
6ed35eea 407 dev_err(dev, "POST error; stage=0x%x\n", stage);
43a04fdc
SP		 408 return -1;
409 } else if (stage != POST_STAGE_ARMFW_RDY) {
6ed35eea
SP		 410 if (msleep_interruptible(2000)) {
411 dev_err(dev, "Waiting for POST aborted\n");
412 return -EINTR;
413 }
43a04fdc
SP		 414 timeout += 2;
415 } else {
416 return 0;
417 }
3ab81b5f 418 } while (timeout < 60);
6b7c5b94 419
6ed35eea 420 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
43a04fdc 421 return -1;
6b7c5b94
SP		 422}
423
6b7c5b94
SP		 424
425static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
426{
427 return &wrb->payload.sgl[0];
428}
429
6b7c5b94
SP		 430
431/* Don't touch the hdr after it's prepared */
106df1e3
SK		 432/* mem will be NULL for embedded commands */
433static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
434 u8 subsystem, u8 opcode, int cmd_len,
435 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
6b7c5b94 436{
106df1e3
SK		 437 struct be_sge *sge;
438
6b7c5b94
SP		 439 req_hdr->opcode = opcode;
440 req_hdr->subsystem = subsystem;
441 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 442 req_hdr->version = 0;
106df1e3
SK		 443
444 wrb->tag0 = opcode;
445 wrb->tag1 = subsystem;
446 wrb->payload_length = cmd_len;
447 if (mem) {
448 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
449 MCC_WRB_SGE_CNT_SHIFT;
450 sge = nonembedded_sgl(wrb);
451 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
452 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
453 sge->len = cpu_to_le32(mem->size);
454 } else
455 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
456 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 457}
458
459static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
460 struct be_dma_mem *mem)
461{
462 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
463 u64 dma = (u64)mem->dma;
464
465 for (i = 0; i < buf_pages; i++) {
466 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
467 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
468 dma += PAGE_SIZE_4K;
469 }
470}
471
472/* Converts interrupt delay in microseconds to multiplier value */
473static u32 eq_delay_to_mult(u32 usec_delay)
474{
475#define MAX_INTR_RATE 651042
476 const u32 round = 10;
477 u32 multiplier;
478
479 if (usec_delay == 0)
480 multiplier = 0;
481 else {
482 u32 interrupt_rate = 1000000 / usec_delay;
483 /* Max delay, corresponding to the lowest interrupt rate */
484 if (interrupt_rate == 0)
485 multiplier = 1023;
486 else {
487 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
488 multiplier /= interrupt_rate;
489 /* Round the multiplier to the closest value.*/
490 multiplier = (multiplier + round/2) / round;
491 multiplier = min(multiplier, (u32)1023);
492 }
493 }
494 return multiplier;
495}
496
b31c50a7 497static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 498{
b31c50a7
SP		 499 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
500 struct be_mcc_wrb *wrb
501 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
502 memset(wrb, 0, sizeof(*wrb));
503 return wrb;
6b7c5b94
SP		 504}
505
b31c50a7 506static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 507{
b31c50a7
SP		 508 struct be_queue_info *mccq = &adapter->mcc_obj.q;
509 struct be_mcc_wrb *wrb;
510
713d0394
SP		 511 if (atomic_read(&mccq->used) >= mccq->len) {
512 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
513 return NULL;
514 }
515
b31c50a7
SP		 516 wrb = queue_head_node(mccq);
517 queue_head_inc(mccq);
518 atomic_inc(&mccq->used);
519 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 520 return wrb;
521}
522
2243e2e9
SP		 523/* Tell fw we're about to start firing cmds by writing a
524 * special pattern across the wrb hdr; uses mbox
525 */
526int be_cmd_fw_init(struct be_adapter *adapter)
527{
528 u8 *wrb;
529 int status;
530
2984961c
IV		 531 if (mutex_lock_interruptible(&adapter->mbox_lock))
532 return -1;
2243e2e9
SP		 533
534 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 535 *wrb++ = 0xFF;
536 *wrb++ = 0x12;
537 *wrb++ = 0x34;
538 *wrb++ = 0xFF;
539 *wrb++ = 0xFF;
540 *wrb++ = 0x56;
541 *wrb++ = 0x78;
542 *wrb = 0xFF;
2243e2e9
SP		 543
544 status = be_mbox_notify_wait(adapter);
545
2984961c 546 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 547 return status;
548}
549
550/* Tell fw we're done with firing cmds by writing a
551 * special pattern across the wrb hdr; uses mbox
552 */
553int be_cmd_fw_clean(struct be_adapter *adapter)
554{
555 u8 *wrb;
556 int status;
557
cf588477
SP		 558 if (adapter->eeh_err)
559 return -EIO;
560
2984961c
IV		 561 if (mutex_lock_interruptible(&adapter->mbox_lock))
562 return -1;
2243e2e9
SP		 563
564 wrb = (u8 *)wrb_from_mbox(adapter);
565 *wrb++ = 0xFF;
566 *wrb++ = 0xAA;
567 *wrb++ = 0xBB;
568 *wrb++ = 0xFF;
569 *wrb++ = 0xFF;
570 *wrb++ = 0xCC;
571 *wrb++ = 0xDD;
572 *wrb = 0xFF;
573
574 status = be_mbox_notify_wait(adapter);
575
2984961c 576 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 577 return status;
578}
8788fdc2 579int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94
SP		 580 struct be_queue_info *eq, int eq_delay)
581{
b31c50a7
SP		 582 struct be_mcc_wrb *wrb;
583 struct be_cmd_req_eq_create *req;
6b7c5b94
SP		 584 struct be_dma_mem *q_mem = &eq->dma_mem;
585 int status;
586
2984961c
IV		 587 if (mutex_lock_interruptible(&adapter->mbox_lock))
588 return -1;
b31c50a7
SP		 589
590 wrb = wrb_from_mbox(adapter);
591 req = embedded_payload(wrb);
6b7c5b94 592
106df1e3
SK		 593 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
594 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 595
596 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
597
6b7c5b94
SP		 598 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
599 /* 4byte eqe*/
600 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
601 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
602 __ilog2_u32(eq->len/256));
603 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
604 eq_delay_to_mult(eq_delay));
605 be_dws_cpu_to_le(req->context, sizeof(req->context));
606
607 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
608
b31c50a7 609 status = be_mbox_notify_wait(adapter);
6b7c5b94 610 if (!status) {
b31c50a7 611 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 612 eq->id = le16_to_cpu(resp->eq_id);
613 eq->created = true;
614 }
b31c50a7 615
2984961c 616 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 617 return status;
618}
619
f9449ab7 620/* Use MCC */
8788fdc2 621int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94
SP		 622 u8 type, bool permanent, u32 if_handle)
623{
b31c50a7
SP		 624 struct be_mcc_wrb *wrb;
625 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 626 int status;
627
f9449ab7 628 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 629
f9449ab7
SP		 630 wrb = wrb_from_mccq(adapter);
631 if (!wrb) {
632 status = -EBUSY;
633 goto err;
634 }
b31c50a7 635 req = embedded_payload(wrb);
6b7c5b94 636
106df1e3
SK		 637 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
638 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 639 req->type = type;
640 if (permanent) {
641 req->permanent = 1;
642 } else {
b31c50a7 643 req->if_id = cpu_to_le16((u16) if_handle);
6b7c5b94
SP		 644 req->permanent = 0;
645 }
646
f9449ab7 647 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 648 if (!status) {
649 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
6b7c5b94 650 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 651 }
6b7c5b94 652
f9449ab7
SP		 653err:
654 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 655 return status;
656}
657
b31c50a7 658/* Uses synchronous MCCQ */
8788fdc2 659int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08 660 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 661{
b31c50a7
SP		 662 struct be_mcc_wrb *wrb;
663 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 664 int status;
665
b31c50a7
SP		 666 spin_lock_bh(&adapter->mcc_lock);
667
668 wrb = wrb_from_mccq(adapter);
713d0394
SP		 669 if (!wrb) {
670 status = -EBUSY;
671 goto err;
672 }
b31c50a7 673 req = embedded_payload(wrb);
6b7c5b94 674
106df1e3
SK		 675 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
676 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
6b7c5b94 677
f8617e08 678 req->hdr.domain = domain;
6b7c5b94
SP		 679 req->if_id = cpu_to_le32(if_id);
680 memcpy(req->mac_address, mac_addr, ETH_ALEN);
681
b31c50a7 682 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 683 if (!status) {
684 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
685 *pmac_id = le32_to_cpu(resp->pmac_id);
686 }
687
713d0394 688err:
b31c50a7 689 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 690
691 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
692 status = -EPERM;
693
6b7c5b94
SP		 694 return status;
695}
696
b31c50a7 697/* Uses synchronous MCCQ */
f8617e08 698int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
6b7c5b94 699{
b31c50a7
SP		 700 struct be_mcc_wrb *wrb;
701 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 702 int status;
703
b31c50a7
SP		 704 spin_lock_bh(&adapter->mcc_lock);
705
706 wrb = wrb_from_mccq(adapter);
713d0394
SP		 707 if (!wrb) {
708 status = -EBUSY;
709 goto err;
710 }
b31c50a7 711 req = embedded_payload(wrb);
6b7c5b94 712
106df1e3
SK		 713 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
714 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
6b7c5b94 715
f8617e08 716 req->hdr.domain = dom;
6b7c5b94
SP		 717 req->if_id = cpu_to_le32(if_id);
718 req->pmac_id = cpu_to_le32(pmac_id);
719
b31c50a7
SP		 720 status = be_mcc_notify_wait(adapter);
721
713d0394 722err:
b31c50a7 723 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 724 return status;
725}
726
b31c50a7 727/* Uses Mbox */
8788fdc2 728int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 729 struct be_queue_info *cq, struct be_queue_info *eq,
730 bool sol_evts, bool no_delay, int coalesce_wm)
731{
b31c50a7
SP		 732 struct be_mcc_wrb *wrb;
733 struct be_cmd_req_cq_create *req;
6b7c5b94 734 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 735 void *ctxt;
6b7c5b94
SP		 736 int status;
737
2984961c
IV		 738 if (mutex_lock_interruptible(&adapter->mbox_lock))
739 return -1;
b31c50a7
SP		 740
741 wrb = wrb_from_mbox(adapter);
742 req = embedded_payload(wrb);
743 ctxt = &req->context;
6b7c5b94 744
106df1e3
SK		 745 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
746 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 747
748 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38 749 if (lancer_chip(adapter)) {
8b7756ca 750 req->hdr.version = 2;
fe6d2a38 751 req->page_size = 1; /* 1 for 4K */
fe6d2a38
SP		 752 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
753 no_delay);
754 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
755 __ilog2_u32(cq->len/256));
756 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
757 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
758 ctxt, 1);
759 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
760 ctxt, eq->id);
761 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
762 } else {
763 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
764 coalesce_wm);
765 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
766 ctxt, no_delay);
767 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
768 __ilog2_u32(cq->len/256));
769 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
770 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
771 ctxt, sol_evts);
772 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
773 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
774 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
775 }
6b7c5b94 776
6b7c5b94
SP		 777 be_dws_cpu_to_le(ctxt, sizeof(req->context));
778
779 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
780
b31c50a7 781 status = be_mbox_notify_wait(adapter);
6b7c5b94 782 if (!status) {
b31c50a7 783 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 784 cq->id = le16_to_cpu(resp->cq_id);
785 cq->created = true;
786 }
b31c50a7 787
2984961c 788 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 789
790 return status;
791}
792
793static u32 be_encoded_q_len(int q_len)
794{
795 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
796 if (len_encoded == 16)
797 len_encoded = 0;
798 return len_encoded;
799}
800
34b1ef04 801int be_cmd_mccq_ext_create(struct be_adapter *adapter,
5fb379ee
SP		 802 struct be_queue_info *mccq,
803 struct be_queue_info *cq)
804{
b31c50a7 805 struct be_mcc_wrb *wrb;
34b1ef04 806 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 807 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 808 void *ctxt;
5fb379ee
SP		 809 int status;
810
2984961c
IV		 811 if (mutex_lock_interruptible(&adapter->mbox_lock))
812 return -1;
b31c50a7
SP		 813
814 wrb = wrb_from_mbox(adapter);
815 req = embedded_payload(wrb);
816 ctxt = &req->context;
5fb379ee 817
106df1e3
SK		 818 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
819 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
5fb379ee 820
d4a2ac3e 821 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
fe6d2a38
SP		 822 if (lancer_chip(adapter)) {
823 req->hdr.version = 1;
824 req->cq_id = cpu_to_le16(cq->id);
825
826 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
827 be_encoded_q_len(mccq->len));
828 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
829 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
830 ctxt, cq->id);
831 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
832 ctxt, 1);
833
834 } else {
835 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
836 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
837 be_encoded_q_len(mccq->len));
838 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
839 }
5fb379ee 840
cc4ce020 841 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 842 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
5fb379ee
SP		 843 be_dws_cpu_to_le(ctxt, sizeof(req->context));
844
845 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
846
b31c50a7 847 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 848 if (!status) {
849 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
850 mccq->id = le16_to_cpu(resp->id);
851 mccq->created = true;
852 }
2984961c 853 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 854
855 return status;
856}
857
34b1ef04
SK		 858int be_cmd_mccq_org_create(struct be_adapter *adapter,
859 struct be_queue_info *mccq,
860 struct be_queue_info *cq)
861{
862 struct be_mcc_wrb *wrb;
863 struct be_cmd_req_mcc_create *req;
864 struct be_dma_mem *q_mem = &mccq->dma_mem;
865 void *ctxt;
866 int status;
867
868 if (mutex_lock_interruptible(&adapter->mbox_lock))
869 return -1;
870
871 wrb = wrb_from_mbox(adapter);
872 req = embedded_payload(wrb);
873 ctxt = &req->context;
874
106df1e3
SK		 875 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
876 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
34b1ef04
SK		 877
878 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
879
880 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
881 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
882 be_encoded_q_len(mccq->len));
883 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
884
885 be_dws_cpu_to_le(ctxt, sizeof(req->context));
886
887 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
888
889 status = be_mbox_notify_wait(adapter);
890 if (!status) {
891 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
892 mccq->id = le16_to_cpu(resp->id);
893 mccq->created = true;
894 }
895
896 mutex_unlock(&adapter->mbox_lock);
897 return status;
898}
899
900int be_cmd_mccq_create(struct be_adapter *adapter,
901 struct be_queue_info *mccq,
902 struct be_queue_info *cq)
903{
904 int status;
905
906 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
907 if (status && !lancer_chip(adapter)) {
908 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
909 "or newer to avoid conflicting priorities between NIC "
910 "and FCoE traffic");
911 status = be_cmd_mccq_org_create(adapter, mccq, cq);
912 }
913 return status;
914}
915
8788fdc2 916int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 917 struct be_queue_info *txq,
918 struct be_queue_info *cq)
919{
b31c50a7
SP		 920 struct be_mcc_wrb *wrb;
921 struct be_cmd_req_eth_tx_create *req;
6b7c5b94 922 struct be_dma_mem *q_mem = &txq->dma_mem;
b31c50a7 923 void *ctxt;
6b7c5b94 924 int status;
6b7c5b94 925
2984961c
IV		 926 if (mutex_lock_interruptible(&adapter->mbox_lock))
927 return -1;
b31c50a7
SP		 928
929 wrb = wrb_from_mbox(adapter);
930 req = embedded_payload(wrb);
931 ctxt = &req->context;
6b7c5b94 932
106df1e3
SK		 933 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
934 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94 935
8b7756ca
PR		 936 if (lancer_chip(adapter)) {
937 req->hdr.version = 1;
938 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
939 adapter->if_handle);
940 }
941
6b7c5b94
SP		 942 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
943 req->ulp_num = BE_ULP1_NUM;
944 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
945
b31c50a7
SP		 946 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
947 be_encoded_q_len(txq->len));
6b7c5b94
SP		 948 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
949 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
950
951 be_dws_cpu_to_le(ctxt, sizeof(req->context));
952
953 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
954
b31c50a7 955 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 956 if (!status) {
957 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
958 txq->id = le16_to_cpu(resp->cid);
959 txq->created = true;
960 }
b31c50a7 961
2984961c 962 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 963
964 return status;
965}
966
482c9e79 967/* Uses MCC */
8788fdc2 968int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94 969 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
3abcdeda 970 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 971{
b31c50a7
SP		 972 struct be_mcc_wrb *wrb;
973 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 974 struct be_dma_mem *q_mem = &rxq->dma_mem;
975 int status;
976
482c9e79 977 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 978
482c9e79
SP		 979 wrb = wrb_from_mccq(adapter);
980 if (!wrb) {
981 status = -EBUSY;
982 goto err;
983 }
b31c50a7 984 req = embedded_payload(wrb);
6b7c5b94 985
106df1e3
SK		 986 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
987 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 988
989 req->cq_id = cpu_to_le16(cq_id);
990 req->frag_size = fls(frag_size) - 1;
991 req->num_pages = 2;
992 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
993 req->interface_id = cpu_to_le32(if_id);
994 req->max_frame_size = cpu_to_le16(max_frame_size);
995 req->rss_queue = cpu_to_le32(rss);
996
482c9e79 997 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 998 if (!status) {
999 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1000 rxq->id = le16_to_cpu(resp->id);
1001 rxq->created = true;
3abcdeda 1002 *rss_id = resp->rss_id;
6b7c5b94 1003 }
b31c50a7 1004
482c9e79
SP		 1005err:
1006 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1007 return status;
1008}
1009
b31c50a7
SP		 1010/* Generic destroyer function for all types of queues
1011 * Uses Mbox
1012 */
8788fdc2 1013int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94
SP		 1014 int queue_type)
1015{
b31c50a7
SP		 1016 struct be_mcc_wrb *wrb;
1017 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1018 u8 subsys = 0, opcode = 0;
1019 int status;
1020
cf588477
SP		 1021 if (adapter->eeh_err)
1022 return -EIO;
1023
2984961c
IV		 1024 if (mutex_lock_interruptible(&adapter->mbox_lock))
1025 return -1;
6b7c5b94 1026
b31c50a7
SP		 1027 wrb = wrb_from_mbox(adapter);
1028 req = embedded_payload(wrb);
1029
6b7c5b94
SP		 1030 switch (queue_type) {
1031 case QTYPE_EQ:
1032 subsys = CMD_SUBSYSTEM_COMMON;
1033 opcode = OPCODE_COMMON_EQ_DESTROY;
1034 break;
1035 case QTYPE_CQ:
1036 subsys = CMD_SUBSYSTEM_COMMON;
1037 opcode = OPCODE_COMMON_CQ_DESTROY;
1038 break;
1039 case QTYPE_TXQ:
1040 subsys = CMD_SUBSYSTEM_ETH;
1041 opcode = OPCODE_ETH_TX_DESTROY;
1042 break;
1043 case QTYPE_RXQ:
1044 subsys = CMD_SUBSYSTEM_ETH;
1045 opcode = OPCODE_ETH_RX_DESTROY;
1046 break;
5fb379ee
SP		 1047 case QTYPE_MCCQ:
1048 subsys = CMD_SUBSYSTEM_COMMON;
1049 opcode = OPCODE_COMMON_MCC_DESTROY;
1050 break;
6b7c5b94 1051 default:
5f0b849e 1052 BUG();
6b7c5b94 1053 }
d744b44e 1054
106df1e3
SK		 1055 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1056 NULL);
6b7c5b94
SP		 1057 req->id = cpu_to_le16(q->id);
1058
b31c50a7 1059 status = be_mbox_notify_wait(adapter);
482c9e79
SP		 1060 if (!status)
1061 q->created = false;
5f0b849e 1062
2984961c 1063 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1064 return status;
1065}
6b7c5b94 1066
482c9e79
SP		 1067/* Uses MCC */
1068int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1069{
1070 struct be_mcc_wrb *wrb;
1071 struct be_cmd_req_q_destroy *req;
1072 int status;
1073
1074 spin_lock_bh(&adapter->mcc_lock);
1075
1076 wrb = wrb_from_mccq(adapter);
1077 if (!wrb) {
1078 status = -EBUSY;
1079 goto err;
1080 }
1081 req = embedded_payload(wrb);
1082
106df1e3
SK		 1083 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1084 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1085 req->id = cpu_to_le16(q->id);
1086
1087 status = be_mcc_notify_wait(adapter);
1088 if (!status)
1089 q->created = false;
1090
1091err:
1092 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1093 return status;
1094}
1095
b31c50a7 1096/* Create an rx filtering policy configuration on an i/f
f9449ab7 1097 * Uses MCCQ
b31c50a7 1098 */
73d540f2 1099int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
f9449ab7 1100 u8 *mac, u32 *if_handle, u32 *pmac_id, u32 domain)
6b7c5b94 1101{
b31c50a7
SP		 1102 struct be_mcc_wrb *wrb;
1103 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1104 int status;
1105
f9449ab7 1106 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1107
f9449ab7
SP		 1108 wrb = wrb_from_mccq(adapter);
1109 if (!wrb) {
1110 status = -EBUSY;
1111 goto err;
1112 }
b31c50a7 1113 req = embedded_payload(wrb);
6b7c5b94 1114
106df1e3
SK		 1115 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1116 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
ba343c77 1117 req->hdr.domain = domain;
73d540f2
SP		 1118 req->capability_flags = cpu_to_le32(cap_flags);
1119 req->enable_flags = cpu_to_le32(en_flags);
f9449ab7 1120 if (mac)
6b7c5b94 1121 memcpy(req->mac_addr, mac, ETH_ALEN);
f9449ab7
SP		 1122 else
1123 req->pmac_invalid = true;
6b7c5b94 1124
f9449ab7 1125 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1126 if (!status) {
1127 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1128 *if_handle = le32_to_cpu(resp->interface_id);
f9449ab7 1129 if (mac)
6b7c5b94
SP		 1130 *pmac_id = le32_to_cpu(resp->pmac_id);
1131 }
1132
f9449ab7
SP		 1133err:
1134 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1135 return status;
1136}
1137
f9449ab7 1138/* Uses MCCQ */
658681f7 1139int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
6b7c5b94 1140{
b31c50a7
SP		 1141 struct be_mcc_wrb *wrb;
1142 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1143 int status;
1144
cf588477
SP		 1145 if (adapter->eeh_err)
1146 return -EIO;
1147
f9449ab7
SP		 1148 if (!interface_id)
1149 return 0;
b31c50a7 1150
f9449ab7
SP		 1151 spin_lock_bh(&adapter->mcc_lock);
1152
1153 wrb = wrb_from_mccq(adapter);
1154 if (!wrb) {
1155 status = -EBUSY;
1156 goto err;
1157 }
b31c50a7 1158 req = embedded_payload(wrb);
6b7c5b94 1159
106df1e3
SK		 1160 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1161 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
658681f7 1162 req->hdr.domain = domain;
6b7c5b94 1163 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1164
f9449ab7
SP		 1165 status = be_mcc_notify_wait(adapter);
1166err:
1167 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1168 return status;
1169}
1170
1171/* Get stats is a non embedded command: the request is not embedded inside
1172 * WRB but is a separate dma memory block
b31c50a7 1173 * Uses asynchronous MCC
6b7c5b94 1174 */
8788fdc2 1175int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1176{
b31c50a7 1177 struct be_mcc_wrb *wrb;
89a88ab8 1178 struct be_cmd_req_hdr *hdr;
713d0394 1179 int status = 0;
6b7c5b94 1180
609ff3bb
AK		 1181 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1182 be_cmd_get_die_temperature(adapter);
1183
b31c50a7 1184 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1185
b31c50a7 1186 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1187 if (!wrb) {
1188 status = -EBUSY;
1189 goto err;
1190 }
89a88ab8 1191 hdr = nonemb_cmd->va;
6b7c5b94 1192
106df1e3
SK		 1193 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1194 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
89a88ab8
AK		 1195
1196 if (adapter->generation == BE_GEN3)
1197 hdr->version = 1;
1198
b31c50a7 1199 be_mcc_notify(adapter);
b2aebe6d 1200 adapter->stats_cmd_sent = true;
6b7c5b94 1201
713d0394 1202err:
b31c50a7 1203 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1204 return status;
6b7c5b94
SP		 1205}
1206
005d5696
SX		 1207/* Lancer Stats */
1208int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1209 struct be_dma_mem *nonemb_cmd)
1210{
1211
1212 struct be_mcc_wrb *wrb;
1213 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1214 int status = 0;
1215
1216 spin_lock_bh(&adapter->mcc_lock);
1217
1218 wrb = wrb_from_mccq(adapter);
1219 if (!wrb) {
1220 status = -EBUSY;
1221 goto err;
1222 }
1223 req = nonemb_cmd->va;
005d5696 1224
106df1e3
SK		 1225 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1226 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1227 nonemb_cmd);
005d5696
SX		 1228
1229 req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1230 req->cmd_params.params.reset_stats = 0;
1231
005d5696
SX		 1232 be_mcc_notify(adapter);
1233 adapter->stats_cmd_sent = true;
1234
1235err:
1236 spin_unlock_bh(&adapter->mcc_lock);
1237 return status;
1238}
1239
b31c50a7 1240/* Uses synchronous mcc */
ea172a01
SP		 1241int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1242 u16 *link_speed, u32 dom)
6b7c5b94 1243{
b31c50a7
SP		 1244 struct be_mcc_wrb *wrb;
1245 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1246 int status;
1247
b31c50a7
SP		 1248 spin_lock_bh(&adapter->mcc_lock);
1249
1250 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1251 if (!wrb) {
1252 status = -EBUSY;
1253 goto err;
1254 }
b31c50a7 1255 req = embedded_payload(wrb);
a8f447bd 1256
106df1e3
SK		 1257 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1258 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
6b7c5b94 1259
b31c50a7 1260 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1261 if (!status) {
1262 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
0388f251 1263 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
0388f251 1264 *link_speed = le16_to_cpu(resp->link_speed);
f9449ab7
SP		 1265 if (mac_speed)
1266 *mac_speed = resp->mac_speed;
0388f251 1267 }
6b7c5b94
SP		 1268 }
1269
713d0394 1270err:
b31c50a7 1271 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1272 return status;
1273}
1274
609ff3bb
AK		 1275/* Uses synchronous mcc */
1276int be_cmd_get_die_temperature(struct be_adapter *adapter)
1277{
1278 struct be_mcc_wrb *wrb;
1279 struct be_cmd_req_get_cntl_addnl_attribs *req;
3de09455 1280 u16 mccq_index;
609ff3bb
AK		 1281 int status;
1282
1283 spin_lock_bh(&adapter->mcc_lock);
1284
3de09455
SK		 1285 mccq_index = adapter->mcc_obj.q.head;
1286
609ff3bb
AK		 1287 wrb = wrb_from_mccq(adapter);
1288 if (!wrb) {
1289 status = -EBUSY;
1290 goto err;
1291 }
1292 req = embedded_payload(wrb);
1293
106df1e3
SK		 1294 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1295 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1296 wrb, NULL);
609ff3bb 1297
3de09455
SK		 1298 wrb->tag1 = mccq_index;
1299
1300 be_mcc_notify(adapter);
609ff3bb
AK		 1301
1302err:
1303 spin_unlock_bh(&adapter->mcc_lock);
1304 return status;
1305}
1306
311fddc7
SK		 1307/* Uses synchronous mcc */
1308int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1309{
1310 struct be_mcc_wrb *wrb;
1311 struct be_cmd_req_get_fat *req;
1312 int status;
1313
1314 spin_lock_bh(&adapter->mcc_lock);
1315
1316 wrb = wrb_from_mccq(adapter);
1317 if (!wrb) {
1318 status = -EBUSY;
1319 goto err;
1320 }
1321 req = embedded_payload(wrb);
1322
106df1e3
SK		 1323 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1324 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
311fddc7
SK		 1325 req->fat_operation = cpu_to_le32(QUERY_FAT);
1326 status = be_mcc_notify_wait(adapter);
1327 if (!status) {
1328 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1329 if (log_size && resp->log_size)
fe2a70ee
SK		 1330 *log_size = le32_to_cpu(resp->log_size) -
1331 sizeof(u32);
311fddc7
SK		 1332 }
1333err:
1334 spin_unlock_bh(&adapter->mcc_lock);
1335 return status;
1336}
1337
1338void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1339{
1340 struct be_dma_mem get_fat_cmd;
1341 struct be_mcc_wrb *wrb;
1342 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1343 u32 offset = 0, total_size, buf_size,
1344 log_offset = sizeof(u32), payload_len;
311fddc7
SK		 1345 int status;
1346
1347 if (buf_len == 0)
1348 return;
1349
1350 total_size = buf_len;
1351
fe2a70ee
SK		 1352 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1353 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1354 get_fat_cmd.size,
1355 &get_fat_cmd.dma);
1356 if (!get_fat_cmd.va) {
1357 status = -ENOMEM;
1358 dev_err(&adapter->pdev->dev,
1359 "Memory allocation failure while retrieving FAT data\n");
1360 return;
1361 }
1362
311fddc7
SK		 1363 spin_lock_bh(&adapter->mcc_lock);
1364
311fddc7
SK		 1365 while (total_size) {
1366 buf_size = min(total_size, (u32)60*1024);
1367 total_size -= buf_size;
1368
fe2a70ee
SK		 1369 wrb = wrb_from_mccq(adapter);
1370 if (!wrb) {
1371 status = -EBUSY;
311fddc7
SK		 1372 goto err;
1373 }
1374 req = get_fat_cmd.va;
311fddc7 1375
fe2a70ee 1376 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3
SK		 1377 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1378 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1379 &get_fat_cmd);
311fddc7
SK		 1380
1381 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1382 req->read_log_offset = cpu_to_le32(log_offset);
1383 req->read_log_length = cpu_to_le32(buf_size);
1384 req->data_buffer_size = cpu_to_le32(buf_size);
1385
1386 status = be_mcc_notify_wait(adapter);
1387 if (!status) {
1388 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1389 memcpy(buf + offset,
1390 resp->data_buffer,
92aa9214 1391 le32_to_cpu(resp->read_log_length));
fe2a70ee 1392 } else {
311fddc7 1393 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1394 goto err;
1395 }
311fddc7
SK		 1396 offset += buf_size;
1397 log_offset += buf_size;
1398 }
1399err:
fe2a70ee
SK		 1400 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1401 get_fat_cmd.va,
1402 get_fat_cmd.dma);
311fddc7
SK		 1403 spin_unlock_bh(&adapter->mcc_lock);
1404}
1405
04b71175
SP		 1406/* Uses synchronous mcc */
1407int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1408 char *fw_on_flash)
6b7c5b94 1409{
b31c50a7
SP		 1410 struct be_mcc_wrb *wrb;
1411 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1412 int status;
1413
04b71175 1414 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1415
04b71175
SP		 1416 wrb = wrb_from_mccq(adapter);
1417 if (!wrb) {
1418 status = -EBUSY;
1419 goto err;
1420 }
6b7c5b94 1421
04b71175 1422 req = embedded_payload(wrb);
6b7c5b94 1423
106df1e3
SK		 1424 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1425 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
04b71175 1426 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1427 if (!status) {
1428 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
04b71175
SP		 1429 strcpy(fw_ver, resp->firmware_version_string);
1430 if (fw_on_flash)
1431 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
6b7c5b94 1432 }
04b71175
SP		 1433err:
1434 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1435 return status;
1436}
1437
b31c50a7
SP		 1438/* set the EQ delay interval of an EQ to specified value
1439 * Uses async mcc
1440 */
8788fdc2 1441int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
6b7c5b94 1442{
b31c50a7
SP		 1443 struct be_mcc_wrb *wrb;
1444 struct be_cmd_req_modify_eq_delay *req;
713d0394 1445 int status = 0;
6b7c5b94 1446
b31c50a7
SP		 1447 spin_lock_bh(&adapter->mcc_lock);
1448
1449 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1450 if (!wrb) {
1451 status = -EBUSY;
1452 goto err;
1453 }
b31c50a7 1454 req = embedded_payload(wrb);
6b7c5b94 1455
106df1e3
SK		 1456 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1457 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1458
1459 req->num_eq = cpu_to_le32(1);
1460 req->delay[0].eq_id = cpu_to_le32(eq_id);
1461 req->delay[0].phase = 0;
1462 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1463
b31c50a7 1464 be_mcc_notify(adapter);
6b7c5b94 1465
713d0394 1466err:
b31c50a7 1467 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1468 return status;
6b7c5b94
SP		 1469}
1470
b31c50a7 1471/* Uses sycnhronous mcc */
8788fdc2 1472int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
6b7c5b94
SP		 1473 u32 num, bool untagged, bool promiscuous)
1474{
b31c50a7
SP		 1475 struct be_mcc_wrb *wrb;
1476 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1477 int status;
1478
b31c50a7
SP		 1479 spin_lock_bh(&adapter->mcc_lock);
1480
1481 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1482 if (!wrb) {
1483 status = -EBUSY;
1484 goto err;
1485 }
b31c50a7 1486 req = embedded_payload(wrb);
6b7c5b94 1487
106df1e3
SK		 1488 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1489 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1490
1491 req->interface_id = if_id;
1492 req->promiscuous = promiscuous;
1493 req->untagged = untagged;
1494 req->num_vlan = num;
1495 if (!promiscuous) {
1496 memcpy(req->normal_vlan, vtag_array,
1497 req->num_vlan * sizeof(vtag_array[0]));
1498 }
1499
b31c50a7 1500 status = be_mcc_notify_wait(adapter);
6b7c5b94 1501
713d0394 1502err:
b31c50a7 1503 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1504 return status;
1505}
1506
5b8821b7 1507int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1508{
6ac7b687 1509 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1510 struct be_dma_mem *mem = &adapter->rx_filter;
1511 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1512 int status;
6b7c5b94 1513
8788fdc2 1514 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1515
b31c50a7 1516 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1517 if (!wrb) {
1518 status = -EBUSY;
1519 goto err;
1520 }
5b8821b7 1521 memset(req, 0, sizeof(*req));
106df1e3
SK		 1522 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1523 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1524 wrb, mem);
6b7c5b94 1525
5b8821b7
SP		 1526 req->if_id = cpu_to_le32(adapter->if_handle);
1527 if (flags & IFF_PROMISC) {
1528 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1529 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1530 if (value == ON)
1531 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
8e7d3f68 1532 BE_IF_FLAGS_VLAN_PROMISCUOUS);
5b8821b7
SP		 1533 } else if (flags & IFF_ALLMULTI) {
1534 req->if_flags_mask = req->if_flags =
8e7d3f68 1535 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7 1536 } else {
22bedad3 1537 struct netdev_hw_addr *ha;
5b8821b7 1538 int i = 0;
24307eef 1539
8e7d3f68
SP		 1540 req->if_flags_mask = req->if_flags =
1541 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1610c79f
PR		 1542
1543 /* Reset mcast promisc mode if already set by setting mask
1544 * and not setting flags field
1545 */
1546 req->if_flags_mask |=
1547 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1548
016f97b1 1549 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1550 netdev_for_each_mc_addr(ha, adapter->netdev)
1551 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1552 }
1553
0d1d5875 1554 status = be_mcc_notify_wait(adapter);
713d0394 1555err:
8788fdc2 1556 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1557 return status;
6b7c5b94
SP		 1558}
1559
b31c50a7 1560/* Uses synchrounous mcc */
8788fdc2 1561int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1562{
b31c50a7
SP		 1563 struct be_mcc_wrb *wrb;
1564 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1565 int status;
1566
b31c50a7 1567 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1568
b31c50a7 1569 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1570 if (!wrb) {
1571 status = -EBUSY;
1572 goto err;
1573 }
b31c50a7 1574 req = embedded_payload(wrb);
6b7c5b94 1575
106df1e3
SK		 1576 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1577 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1578
1579 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1580 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1581
b31c50a7 1582 status = be_mcc_notify_wait(adapter);
6b7c5b94 1583
713d0394 1584err:
b31c50a7 1585 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1586 return status;
1587}
1588
b31c50a7 1589/* Uses sycn mcc */
8788fdc2 1590int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1591{
b31c50a7
SP		 1592 struct be_mcc_wrb *wrb;
1593 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1594 int status;
1595
b31c50a7 1596 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1597
b31c50a7 1598 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1599 if (!wrb) {
1600 status = -EBUSY;
1601 goto err;
1602 }
b31c50a7 1603 req = embedded_payload(wrb);
6b7c5b94 1604
106df1e3
SK		 1605 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1606 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
6b7c5b94 1607
b31c50a7 1608 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1609 if (!status) {
1610 struct be_cmd_resp_get_flow_control *resp =
1611 embedded_payload(wrb);
1612 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1613 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1614 }
1615
713d0394 1616err:
b31c50a7 1617 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1618 return status;
1619}
1620
b31c50a7 1621/* Uses mbox */
3abcdeda
SP		 1622int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1623 u32 *mode, u32 *caps)
6b7c5b94 1624{
b31c50a7
SP		 1625 struct be_mcc_wrb *wrb;
1626 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 1627 int status;
1628
2984961c
IV		 1629 if (mutex_lock_interruptible(&adapter->mbox_lock))
1630 return -1;
6b7c5b94 1631
b31c50a7
SP		 1632 wrb = wrb_from_mbox(adapter);
1633 req = embedded_payload(wrb);
6b7c5b94 1634
106df1e3
SK		 1635 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1636 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
6b7c5b94 1637
b31c50a7 1638 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 1639 if (!status) {
1640 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1641 *port_num = le32_to_cpu(resp->phys_port);
3486be29 1642 *mode = le32_to_cpu(resp->function_mode);
3abcdeda 1643 *caps = le32_to_cpu(resp->function_caps);
6b7c5b94
SP		 1644 }
1645
2984961c 1646 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1647 return status;
1648}
14074eab 1649
b31c50a7 1650/* Uses mbox */
14074eab 1651int be_cmd_reset_function(struct be_adapter *adapter)
1652{
b31c50a7
SP		 1653 struct be_mcc_wrb *wrb;
1654 struct be_cmd_req_hdr *req;
14074eab 1655 int status;
1656
2984961c
IV		 1657 if (mutex_lock_interruptible(&adapter->mbox_lock))
1658 return -1;
14074eab 1659
b31c50a7
SP		 1660 wrb = wrb_from_mbox(adapter);
1661 req = embedded_payload(wrb);
14074eab 1662
106df1e3
SK		 1663 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1664 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
14074eab 1665
b31c50a7 1666 status = be_mbox_notify_wait(adapter);
14074eab 1667
2984961c 1668 mutex_unlock(&adapter->mbox_lock);
14074eab 1669 return status;
1670}
84517482 1671
3abcdeda
SP		 1672int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1673{
1674 struct be_mcc_wrb *wrb;
1675 struct be_cmd_req_rss_config *req;
5d8bee67
SP		 1676 u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF,
1677 0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF};
3abcdeda
SP		 1678 int status;
1679
2984961c
IV		 1680 if (mutex_lock_interruptible(&adapter->mbox_lock))
1681 return -1;
3abcdeda
SP		 1682
1683 wrb = wrb_from_mbox(adapter);
1684 req = embedded_payload(wrb);
1685
106df1e3
SK		 1686 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1687 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 1688
1689 req->if_id = cpu_to_le32(adapter->if_handle);
1690 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1691 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1692 memcpy(req->cpu_table, rsstable, table_size);
1693 memcpy(req->hash, myhash, sizeof(myhash));
1694 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1695
1696 status = be_mbox_notify_wait(adapter);
1697
2984961c 1698 mutex_unlock(&adapter->mbox_lock);
3abcdeda
SP		 1699 return status;
1700}
1701
fad9ab2c
SB		 1702/* Uses sync mcc */
1703int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1704 u8 bcn, u8 sts, u8 state)
1705{
1706 struct be_mcc_wrb *wrb;
1707 struct be_cmd_req_enable_disable_beacon *req;
1708 int status;
1709
1710 spin_lock_bh(&adapter->mcc_lock);
1711
1712 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1713 if (!wrb) {
1714 status = -EBUSY;
1715 goto err;
1716 }
fad9ab2c
SB		 1717 req = embedded_payload(wrb);
1718
106df1e3
SK		 1719 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1720 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1721
1722 req->port_num = port_num;
1723 req->beacon_state = state;
1724 req->beacon_duration = bcn;
1725 req->status_duration = sts;
1726
1727 status = be_mcc_notify_wait(adapter);
1728
713d0394 1729err:
fad9ab2c
SB		 1730 spin_unlock_bh(&adapter->mcc_lock);
1731 return status;
1732}
1733
1734/* Uses sync mcc */
1735int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1736{
1737 struct be_mcc_wrb *wrb;
1738 struct be_cmd_req_get_beacon_state *req;
1739 int status;
1740
1741 spin_lock_bh(&adapter->mcc_lock);
1742
1743 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1744 if (!wrb) {
1745 status = -EBUSY;
1746 goto err;
1747 }
fad9ab2c
SB		 1748 req = embedded_payload(wrb);
1749
106df1e3
SK		 1750 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1751 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
fad9ab2c
SB		 1752
1753 req->port_num = port_num;
1754
1755 status = be_mcc_notify_wait(adapter);
1756 if (!status) {
1757 struct be_cmd_resp_get_beacon_state *resp =
1758 embedded_payload(wrb);
1759 *state = resp->beacon_state;
1760 }
1761
713d0394 1762err:
fad9ab2c
SB		 1763 spin_unlock_bh(&adapter->mcc_lock);
1764 return status;
1765}
1766
485bf569
SN		 1767int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1768 u32 data_size, u32 data_offset, const char *obj_name,
1769 u32 *data_written, u8 *addn_status)
1770{
1771 struct be_mcc_wrb *wrb;
1772 struct lancer_cmd_req_write_object *req;
1773 struct lancer_cmd_resp_write_object *resp;
1774 void *ctxt = NULL;
1775 int status;
1776
1777 spin_lock_bh(&adapter->mcc_lock);
1778 adapter->flash_status = 0;
1779
1780 wrb = wrb_from_mccq(adapter);
1781 if (!wrb) {
1782 status = -EBUSY;
1783 goto err_unlock;
1784 }
1785
1786 req = embedded_payload(wrb);
1787
106df1e3 1788 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
485bf569 1789 OPCODE_COMMON_WRITE_OBJECT,
106df1e3
SK		 1790 sizeof(struct lancer_cmd_req_write_object), wrb,
1791 NULL);
485bf569
SN		 1792
1793 ctxt = &req->context;
1794 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1795 write_length, ctxt, data_size);
1796
1797 if (data_size == 0)
1798 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1799 eof, ctxt, 1);
1800 else
1801 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1802 eof, ctxt, 0);
1803
1804 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1805 req->write_offset = cpu_to_le32(data_offset);
1806 strcpy(req->object_name, obj_name);
1807 req->descriptor_count = cpu_to_le32(1);
1808 req->buf_len = cpu_to_le32(data_size);
1809 req->addr_low = cpu_to_le32((cmd->dma +
1810 sizeof(struct lancer_cmd_req_write_object))
1811 & 0xFFFFFFFF);
1812 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1813 sizeof(struct lancer_cmd_req_write_object)));
1814
1815 be_mcc_notify(adapter);
1816 spin_unlock_bh(&adapter->mcc_lock);
1817
1818 if (!wait_for_completion_timeout(&adapter->flash_compl,
1819 msecs_to_jiffies(12000)))
1820 status = -1;
1821 else
1822 status = adapter->flash_status;
1823
1824 resp = embedded_payload(wrb);
1825 if (!status) {
1826 *data_written = le32_to_cpu(resp->actual_write_len);
1827 } else {
1828 *addn_status = resp->additional_status;
1829 status = resp->status;
1830 }
1831
1832 return status;
1833
1834err_unlock:
1835 spin_unlock_bh(&adapter->mcc_lock);
1836 return status;
1837}
1838
84517482
AK		 1839int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1840 u32 flash_type, u32 flash_opcode, u32 buf_size)
1841{
b31c50a7 1842 struct be_mcc_wrb *wrb;
3f0d4560 1843 struct be_cmd_write_flashrom *req;
84517482
AK		 1844 int status;
1845
b31c50a7 1846 spin_lock_bh(&adapter->mcc_lock);
dd131e76 1847 adapter->flash_status = 0;
b31c50a7
SP		 1848
1849 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1850 if (!wrb) {
1851 status = -EBUSY;
2892d9c2 1852 goto err_unlock;
713d0394
SP		 1853 }
1854 req = cmd->va;
84517482 1855
106df1e3
SK		 1856 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1857 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
84517482
AK		 1858
1859 req->params.op_type = cpu_to_le32(flash_type);
1860 req->params.op_code = cpu_to_le32(flash_opcode);
1861 req->params.data_buf_size = cpu_to_le32(buf_size);
1862
dd131e76
SB		 1863 be_mcc_notify(adapter);
1864 spin_unlock_bh(&adapter->mcc_lock);
1865
1866 if (!wait_for_completion_timeout(&adapter->flash_compl,
e2edb7d5 1867 msecs_to_jiffies(40000)))
dd131e76
SB		 1868 status = -1;
1869 else
1870 status = adapter->flash_status;
84517482 1871
2892d9c2
DC		 1872 return status;
1873
1874err_unlock:
1875 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 1876 return status;
1877}
fa9a6fed 1878
3f0d4560
AK		 1879int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1880 int offset)
fa9a6fed
SB		 1881{
1882 struct be_mcc_wrb *wrb;
1883 struct be_cmd_write_flashrom *req;
1884 int status;
1885
1886 spin_lock_bh(&adapter->mcc_lock);
1887
1888 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1889 if (!wrb) {
1890 status = -EBUSY;
1891 goto err;
1892 }
fa9a6fed
SB		 1893 req = embedded_payload(wrb);
1894
106df1e3
SK		 1895 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1896 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
fa9a6fed 1897
3f0d4560 1898 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
fa9a6fed 1899 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710
AK		 1900 req->params.offset = cpu_to_le32(offset);
1901 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 1902
1903 status = be_mcc_notify_wait(adapter);
1904 if (!status)
1905 memcpy(flashed_crc, req->params.data_buf, 4);
1906
713d0394 1907err:
fa9a6fed
SB		 1908 spin_unlock_bh(&adapter->mcc_lock);
1909 return status;
1910}
71d8d1b5 1911
c196b02c 1912int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
71d8d1b5
AK		 1913 struct be_dma_mem *nonemb_cmd)
1914{
1915 struct be_mcc_wrb *wrb;
1916 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 1917 int status;
1918
1919 spin_lock_bh(&adapter->mcc_lock);
1920
1921 wrb = wrb_from_mccq(adapter);
1922 if (!wrb) {
1923 status = -EBUSY;
1924 goto err;
1925 }
1926 req = nonemb_cmd->va;
71d8d1b5 1927
106df1e3
SK		 1928 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1929 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
1930 nonemb_cmd);
71d8d1b5
AK		 1931 memcpy(req->magic_mac, mac, ETH_ALEN);
1932
71d8d1b5
AK		 1933 status = be_mcc_notify_wait(adapter);
1934
1935err:
1936 spin_unlock_bh(&adapter->mcc_lock);
1937 return status;
1938}
ff33a6e2 1939
fced9999
SB		 1940int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1941 u8 loopback_type, u8 enable)
1942{
1943 struct be_mcc_wrb *wrb;
1944 struct be_cmd_req_set_lmode *req;
1945 int status;
1946
1947 spin_lock_bh(&adapter->mcc_lock);
1948
1949 wrb = wrb_from_mccq(adapter);
1950 if (!wrb) {
1951 status = -EBUSY;
1952 goto err;
1953 }
1954
1955 req = embedded_payload(wrb);
1956
106df1e3
SK		 1957 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1958 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
1959 NULL);
fced9999
SB		 1960
1961 req->src_port = port_num;
1962 req->dest_port = port_num;
1963 req->loopback_type = loopback_type;
1964 req->loopback_state = enable;
1965
1966 status = be_mcc_notify_wait(adapter);
1967err:
1968 spin_unlock_bh(&adapter->mcc_lock);
1969 return status;
1970}
1971
ff33a6e2
S		 1972int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1973 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1974{
1975 struct be_mcc_wrb *wrb;
1976 struct be_cmd_req_loopback_test *req;
1977 int status;
1978
1979 spin_lock_bh(&adapter->mcc_lock);
1980
1981 wrb = wrb_from_mccq(adapter);
1982 if (!wrb) {
1983 status = -EBUSY;
1984 goto err;
1985 }
1986
1987 req = embedded_payload(wrb);
1988
106df1e3
SK		 1989 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1990 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
3ffd0515 1991 req->hdr.timeout = cpu_to_le32(4);
ff33a6e2
S		 1992
1993 req->pattern = cpu_to_le64(pattern);
1994 req->src_port = cpu_to_le32(port_num);
1995 req->dest_port = cpu_to_le32(port_num);
1996 req->pkt_size = cpu_to_le32(pkt_size);
1997 req->num_pkts = cpu_to_le32(num_pkts);
1998 req->loopback_type = cpu_to_le32(loopback_type);
1999
2000 status = be_mcc_notify_wait(adapter);
2001 if (!status) {
2002 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2003 status = le32_to_cpu(resp->status);
2004 }
2005
2006err:
2007 spin_unlock_bh(&adapter->mcc_lock);
2008 return status;
2009}
2010
2011int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2012 u32 byte_cnt, struct be_dma_mem *cmd)
2013{
2014 struct be_mcc_wrb *wrb;
2015 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2016 int status;
2017 int i, j = 0;
2018
2019 spin_lock_bh(&adapter->mcc_lock);
2020
2021 wrb = wrb_from_mccq(adapter);
2022 if (!wrb) {
2023 status = -EBUSY;
2024 goto err;
2025 }
2026 req = cmd->va;
106df1e3
SK		 2027 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2028 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
ff33a6e2
S		 2029
2030 req->pattern = cpu_to_le64(pattern);
2031 req->byte_count = cpu_to_le32(byte_cnt);
2032 for (i = 0; i < byte_cnt; i++) {
2033 req->snd_buff[i] = (u8)(pattern >> (j*8));
2034 j++;
2035 if (j > 7)
2036 j = 0;
2037 }
2038
2039 status = be_mcc_notify_wait(adapter);
2040
2041 if (!status) {
2042 struct be_cmd_resp_ddrdma_test *resp;
2043 resp = cmd->va;
2044 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2045 resp->snd_err) {
2046 status = -1;
2047 }
2048 }
2049
2050err:
2051 spin_unlock_bh(&adapter->mcc_lock);
2052 return status;
2053}
368c0ca2 2054
c196b02c 2055int be_cmd_get_seeprom_data(struct be_adapter *adapter,
368c0ca2
SB		 2056 struct be_dma_mem *nonemb_cmd)
2057{
2058 struct be_mcc_wrb *wrb;
2059 struct be_cmd_req_seeprom_read *req;
2060 struct be_sge *sge;
2061 int status;
2062
2063 spin_lock_bh(&adapter->mcc_lock);
2064
2065 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2066 if (!wrb) {
2067 status = -EBUSY;
2068 goto err;
2069 }
368c0ca2
SB		 2070 req = nonemb_cmd->va;
2071 sge = nonembedded_sgl(wrb);
2072
106df1e3
SK		 2073 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2074 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2075 nonemb_cmd);
368c0ca2
SB		 2076
2077 status = be_mcc_notify_wait(adapter);
2078
e45ff01d 2079err:
368c0ca2
SB		 2080 spin_unlock_bh(&adapter->mcc_lock);
2081 return status;
2082}
ee3cb629 2083
306f1348
SP		 2084int be_cmd_get_phy_info(struct be_adapter *adapter,
2085 struct be_phy_info *phy_info)
ee3cb629
AK		 2086{
2087 struct be_mcc_wrb *wrb;
2088 struct be_cmd_req_get_phy_info *req;
306f1348 2089 struct be_dma_mem cmd;
ee3cb629
AK		 2090 int status;
2091
2092 spin_lock_bh(&adapter->mcc_lock);
2093
2094 wrb = wrb_from_mccq(adapter);
2095 if (!wrb) {
2096 status = -EBUSY;
2097 goto err;
2098 }
306f1348
SP		 2099 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2100 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2101 &cmd.dma);
2102 if (!cmd.va) {
2103 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2104 status = -ENOMEM;
2105 goto err;
2106 }
ee3cb629 2107
306f1348 2108 req = cmd.va;
ee3cb629 2109
106df1e3
SK		 2110 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2111 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2112 wrb, &cmd);
ee3cb629
AK		 2113
2114 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2115 if (!status) {
2116 struct be_phy_info *resp_phy_info =
2117 cmd.va + sizeof(struct be_cmd_req_hdr);
2118 phy_info->phy_type = le16_to_cpu(resp_phy_info->phy_type);
2119 phy_info->interface_type =
2120 le16_to_cpu(resp_phy_info->interface_type);
2121 }
2122 pci_free_consistent(adapter->pdev, cmd.size,
2123 cmd.va, cmd.dma);
ee3cb629
AK		 2124err:
2125 spin_unlock_bh(&adapter->mcc_lock);
2126 return status;
2127}
e1d18735
AK		 2128
2129int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2130{
2131 struct be_mcc_wrb *wrb;
2132 struct be_cmd_req_set_qos *req;
2133 int status;
2134
2135 spin_lock_bh(&adapter->mcc_lock);
2136
2137 wrb = wrb_from_mccq(adapter);
2138 if (!wrb) {
2139 status = -EBUSY;
2140 goto err;
2141 }
2142
2143 req = embedded_payload(wrb);
2144
106df1e3
SK		 2145 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2146 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2147
2148 req->hdr.domain = domain;
6bff57a7
AK		 2149 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2150 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2151
2152 status = be_mcc_notify_wait(adapter);
2153
2154err:
2155 spin_unlock_bh(&adapter->mcc_lock);
2156 return status;
2157}
9e1453c5
AK		 2158
2159int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2160{
2161 struct be_mcc_wrb *wrb;
2162 struct be_cmd_req_cntl_attribs *req;
2163 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2164 int status;
2165 int payload_len = max(sizeof(*req), sizeof(*resp));
2166 struct mgmt_controller_attrib *attribs;
2167 struct be_dma_mem attribs_cmd;
2168
2169 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2170 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2171 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2172 &attribs_cmd.dma);
2173 if (!attribs_cmd.va) {
2174 dev_err(&adapter->pdev->dev,
2175 "Memory allocation failure\n");
2176 return -ENOMEM;
2177 }
2178
2179 if (mutex_lock_interruptible(&adapter->mbox_lock))
2180 return -1;
2181
2182 wrb = wrb_from_mbox(adapter);
2183 if (!wrb) {
2184 status = -EBUSY;
2185 goto err;
2186 }
2187 req = attribs_cmd.va;
9e1453c5 2188
106df1e3
SK		 2189 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2190 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2191 &attribs_cmd);
9e1453c5
AK		 2192
2193 status = be_mbox_notify_wait(adapter);
2194 if (!status) {
43d620c8 2195 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2196 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2197 }
2198
2199err:
2200 mutex_unlock(&adapter->mbox_lock);
2201 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2202 attribs_cmd.dma);
2203 return status;
2204}
2e588f84
SP		 2205
2206/* Uses mbox */
2dc1deb6 2207int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2208{
2209 struct be_mcc_wrb *wrb;
2210 struct be_cmd_req_set_func_cap *req;
2211 int status;
2212
2213 if (mutex_lock_interruptible(&adapter->mbox_lock))
2214 return -1;
2215
2216 wrb = wrb_from_mbox(adapter);
2217 if (!wrb) {
2218 status = -EBUSY;
2219 goto err;
2220 }
2221
2222 req = embedded_payload(wrb);
2223
106df1e3
SK		 2224 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2225 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2e588f84
SP		 2226
2227 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2228 CAPABILITY_BE3_NATIVE_ERX_API);
2229 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2230
2231 status = be_mbox_notify_wait(adapter);
2232 if (!status) {
2233 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2234 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2235 CAPABILITY_BE3_NATIVE_ERX_API;
2236 }
2237err:
2238 mutex_unlock(&adapter->mbox_lock);
2239 return status;
2240}
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