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Commit | Line | Data |
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6b7c5b94 | 1 | /* |
c7bb15a6 | 2 | * Copyright (C) 2005 - 2013 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
6a4ab669 | 18 | #include <linux/module.h> |
6b7c5b94 | 19 | #include "be.h" |
8788fdc2 | 20 | #include "be_cmds.h" |
6b7c5b94 | 21 | |
f25b119c PR |
22 | static struct be_cmd_priv_map cmd_priv_map[] = { |
23 | { | |
24 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, | |
25 | CMD_SUBSYSTEM_ETH, | |
26 | BE_PRIV_LNKMGMT | BE_PRIV_VHADM | | |
27 | BE_PRIV_DEVCFG | BE_PRIV_DEVSEC | |
28 | }, | |
29 | { | |
30 | OPCODE_COMMON_GET_FLOW_CONTROL, | |
31 | CMD_SUBSYSTEM_COMMON, | |
32 | BE_PRIV_LNKQUERY | BE_PRIV_VHADM | | |
33 | BE_PRIV_DEVCFG | BE_PRIV_DEVSEC | |
34 | }, | |
35 | { | |
36 | OPCODE_COMMON_SET_FLOW_CONTROL, | |
37 | CMD_SUBSYSTEM_COMMON, | |
38 | BE_PRIV_LNKMGMT | BE_PRIV_VHADM | | |
39 | BE_PRIV_DEVCFG | BE_PRIV_DEVSEC | |
40 | }, | |
41 | { | |
42 | OPCODE_ETH_GET_PPORT_STATS, | |
43 | CMD_SUBSYSTEM_ETH, | |
44 | BE_PRIV_LNKMGMT | BE_PRIV_VHADM | | |
45 | BE_PRIV_DEVCFG | BE_PRIV_DEVSEC | |
46 | }, | |
47 | { | |
48 | OPCODE_COMMON_GET_PHY_DETAILS, | |
49 | CMD_SUBSYSTEM_COMMON, | |
50 | BE_PRIV_LNKMGMT | BE_PRIV_VHADM | | |
51 | BE_PRIV_DEVCFG | BE_PRIV_DEVSEC | |
52 | } | |
53 | }; | |
54 | ||
55 | static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, | |
56 | u8 subsystem) | |
57 | { | |
58 | int i; | |
59 | int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map); | |
60 | u32 cmd_privileges = adapter->cmd_privileges; | |
61 | ||
62 | for (i = 0; i < num_entries; i++) | |
63 | if (opcode == cmd_priv_map[i].opcode && | |
64 | subsystem == cmd_priv_map[i].subsystem) | |
65 | if (!(cmd_privileges & cmd_priv_map[i].priv_mask)) | |
66 | return false; | |
67 | ||
68 | return true; | |
69 | } | |
70 | ||
3de09455 SK |
71 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) |
72 | { | |
73 | return wrb->payload.embedded_payload; | |
74 | } | |
609ff3bb | 75 | |
8788fdc2 | 76 | static void be_mcc_notify(struct be_adapter *adapter) |
5fb379ee | 77 | { |
8788fdc2 | 78 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
5fb379ee SP |
79 | u32 val = 0; |
80 | ||
6589ade0 | 81 | if (be_error(adapter)) |
7acc2087 | 82 | return; |
7acc2087 | 83 | |
5fb379ee SP |
84 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; |
85 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | |
f3eb62d2 SP |
86 | |
87 | wmb(); | |
8788fdc2 | 88 | iowrite32(val, adapter->db + DB_MCCQ_OFFSET); |
5fb379ee SP |
89 | } |
90 | ||
91 | /* To check if valid bit is set, check the entire word as we don't know | |
92 | * the endianness of the data (old entry is host endian while a new entry is | |
93 | * little endian) */ | |
efd2e40a | 94 | static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) |
5fb379ee | 95 | { |
9e9ff4b7 SP |
96 | u32 flags; |
97 | ||
5fb379ee | 98 | if (compl->flags != 0) { |
9e9ff4b7 SP |
99 | flags = le32_to_cpu(compl->flags); |
100 | if (flags & CQE_FLAGS_VALID_MASK) { | |
101 | compl->flags = flags; | |
102 | return true; | |
103 | } | |
5fb379ee | 104 | } |
9e9ff4b7 | 105 | return false; |
5fb379ee SP |
106 | } |
107 | ||
108 | /* Need to reset the entire word that houses the valid bit */ | |
efd2e40a | 109 | static inline void be_mcc_compl_use(struct be_mcc_compl *compl) |
5fb379ee SP |
110 | { |
111 | compl->flags = 0; | |
112 | } | |
113 | ||
652bf646 PR |
114 | static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1) |
115 | { | |
116 | unsigned long addr; | |
117 | ||
118 | addr = tag1; | |
119 | addr = ((addr << 16) << 16) | tag0; | |
120 | return (void *)addr; | |
121 | } | |
122 | ||
8788fdc2 | 123 | static int be_mcc_compl_process(struct be_adapter *adapter, |
652bf646 | 124 | struct be_mcc_compl *compl) |
5fb379ee SP |
125 | { |
126 | u16 compl_status, extd_status; | |
652bf646 PR |
127 | struct be_cmd_resp_hdr *resp_hdr; |
128 | u8 opcode = 0, subsystem = 0; | |
5fb379ee SP |
129 | |
130 | /* Just swap the status to host endian; mcc tag is opaquely copied | |
131 | * from mcc_wrb */ | |
132 | be_dws_le_to_cpu(compl, 4); | |
133 | ||
134 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & | |
135 | CQE_STATUS_COMPL_MASK; | |
dd131e76 | 136 | |
652bf646 PR |
137 | resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1); |
138 | ||
139 | if (resp_hdr) { | |
140 | opcode = resp_hdr->opcode; | |
141 | subsystem = resp_hdr->subsystem; | |
142 | } | |
143 | ||
144 | if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) || | |
145 | (opcode == OPCODE_COMMON_WRITE_OBJECT)) && | |
146 | (subsystem == CMD_SUBSYSTEM_COMMON)) { | |
dd131e76 SB |
147 | adapter->flash_status = compl_status; |
148 | complete(&adapter->flash_compl); | |
149 | } | |
150 | ||
b31c50a7 | 151 | if (compl_status == MCC_STATUS_SUCCESS) { |
652bf646 PR |
152 | if (((opcode == OPCODE_ETH_GET_STATISTICS) || |
153 | (opcode == OPCODE_ETH_GET_PPORT_STATS)) && | |
154 | (subsystem == CMD_SUBSYSTEM_ETH)) { | |
89a88ab8 | 155 | be_parse_stats(adapter); |
b2aebe6d | 156 | adapter->stats_cmd_sent = false; |
b31c50a7 | 157 | } |
652bf646 PR |
158 | if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES && |
159 | subsystem == CMD_SUBSYSTEM_COMMON) { | |
3de09455 | 160 | struct be_cmd_resp_get_cntl_addnl_attribs *resp = |
652bf646 | 161 | (void *)resp_hdr; |
3de09455 SK |
162 | adapter->drv_stats.be_on_die_temperature = |
163 | resp->on_die_temperature; | |
164 | } | |
2b3f291b | 165 | } else { |
652bf646 | 166 | if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) |
7aeb2156 | 167 | adapter->be_get_temp_freq = 0; |
3de09455 | 168 | |
2b3f291b SP |
169 | if (compl_status == MCC_STATUS_NOT_SUPPORTED || |
170 | compl_status == MCC_STATUS_ILLEGAL_REQUEST) | |
171 | goto done; | |
172 | ||
173 | if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { | |
97f1d8cd | 174 | dev_warn(&adapter->pdev->dev, |
522609f2 | 175 | "VF is not privileged to issue opcode %d-%d\n", |
97f1d8cd | 176 | opcode, subsystem); |
2b3f291b SP |
177 | } else { |
178 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & | |
179 | CQE_STATUS_EXTD_MASK; | |
97f1d8cd VV |
180 | dev_err(&adapter->pdev->dev, |
181 | "opcode %d-%d failed:status %d-%d\n", | |
182 | opcode, subsystem, compl_status, extd_status); | |
2b3f291b | 183 | } |
5fb379ee | 184 | } |
2b3f291b | 185 | done: |
b31c50a7 | 186 | return compl_status; |
5fb379ee SP |
187 | } |
188 | ||
a8f447bd | 189 | /* Link state evt is a string of bytes; no need for endian swapping */ |
8788fdc2 | 190 | static void be_async_link_state_process(struct be_adapter *adapter, |
a8f447bd SP |
191 | struct be_async_event_link_state *evt) |
192 | { | |
b236916a | 193 | /* When link status changes, link speed must be re-queried from FW */ |
42f11cf2 | 194 | adapter->phy.link_speed = -1; |
b236916a | 195 | |
2e177a5c PR |
196 | /* Ignore physical link event */ |
197 | if (lancer_chip(adapter) && | |
198 | !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK)) | |
199 | return; | |
200 | ||
b236916a AK |
201 | /* For the initial link status do not rely on the ASYNC event as |
202 | * it may not be received in some cases. | |
203 | */ | |
204 | if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT) | |
205 | be_link_status_update(adapter, evt->port_link_status); | |
a8f447bd SP |
206 | } |
207 | ||
cc4ce020 SK |
208 | /* Grp5 CoS Priority evt */ |
209 | static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, | |
210 | struct be_async_event_grp5_cos_priority *evt) | |
211 | { | |
212 | if (evt->valid) { | |
213 | adapter->vlan_prio_bmap = evt->available_priority_bmap; | |
60964dd7 | 214 | adapter->recommended_prio &= ~VLAN_PRIO_MASK; |
cc4ce020 SK |
215 | adapter->recommended_prio = |
216 | evt->reco_default_priority << VLAN_PRIO_SHIFT; | |
217 | } | |
218 | } | |
219 | ||
323ff71e | 220 | /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */ |
cc4ce020 SK |
221 | static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, |
222 | struct be_async_event_grp5_qos_link_speed *evt) | |
223 | { | |
323ff71e SP |
224 | if (adapter->phy.link_speed >= 0 && |
225 | evt->physical_port == adapter->port_num) | |
226 | adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10; | |
cc4ce020 SK |
227 | } |
228 | ||
3968fa1e AK |
229 | /*Grp5 PVID evt*/ |
230 | static void be_async_grp5_pvid_state_process(struct be_adapter *adapter, | |
231 | struct be_async_event_grp5_pvid_state *evt) | |
232 | { | |
233 | if (evt->enabled) | |
939cf306 | 234 | adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK; |
3968fa1e AK |
235 | else |
236 | adapter->pvid = 0; | |
237 | } | |
238 | ||
cc4ce020 SK |
239 | static void be_async_grp5_evt_process(struct be_adapter *adapter, |
240 | u32 trailer, struct be_mcc_compl *evt) | |
241 | { | |
242 | u8 event_type = 0; | |
243 | ||
244 | event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & | |
245 | ASYNC_TRAILER_EVENT_TYPE_MASK; | |
246 | ||
247 | switch (event_type) { | |
248 | case ASYNC_EVENT_COS_PRIORITY: | |
249 | be_async_grp5_cos_priority_process(adapter, | |
250 | (struct be_async_event_grp5_cos_priority *)evt); | |
251 | break; | |
252 | case ASYNC_EVENT_QOS_SPEED: | |
253 | be_async_grp5_qos_speed_process(adapter, | |
254 | (struct be_async_event_grp5_qos_link_speed *)evt); | |
255 | break; | |
3968fa1e AK |
256 | case ASYNC_EVENT_PVID_STATE: |
257 | be_async_grp5_pvid_state_process(adapter, | |
258 | (struct be_async_event_grp5_pvid_state *)evt); | |
259 | break; | |
cc4ce020 SK |
260 | default: |
261 | dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n"); | |
262 | break; | |
263 | } | |
264 | } | |
265 | ||
bc0c3405 AK |
266 | static void be_async_dbg_evt_process(struct be_adapter *adapter, |
267 | u32 trailer, struct be_mcc_compl *cmp) | |
268 | { | |
269 | u8 event_type = 0; | |
270 | struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp; | |
271 | ||
272 | event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & | |
273 | ASYNC_TRAILER_EVENT_TYPE_MASK; | |
274 | ||
275 | switch (event_type) { | |
276 | case ASYNC_DEBUG_EVENT_TYPE_QNQ: | |
277 | if (evt->valid) | |
278 | adapter->qnq_vid = le16_to_cpu(evt->vlan_tag); | |
279 | adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD; | |
280 | break; | |
281 | default: | |
282 | dev_warn(&adapter->pdev->dev, "Unknown debug event\n"); | |
283 | break; | |
284 | } | |
285 | } | |
286 | ||
a8f447bd SP |
287 | static inline bool is_link_state_evt(u32 trailer) |
288 | { | |
807540ba | 289 | return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & |
a8f447bd | 290 | ASYNC_TRAILER_EVENT_CODE_MASK) == |
807540ba | 291 | ASYNC_EVENT_CODE_LINK_STATE; |
a8f447bd | 292 | } |
5fb379ee | 293 | |
cc4ce020 SK |
294 | static inline bool is_grp5_evt(u32 trailer) |
295 | { | |
296 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | |
297 | ASYNC_TRAILER_EVENT_CODE_MASK) == | |
298 | ASYNC_EVENT_CODE_GRP_5); | |
299 | } | |
300 | ||
bc0c3405 AK |
301 | static inline bool is_dbg_evt(u32 trailer) |
302 | { | |
303 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | |
304 | ASYNC_TRAILER_EVENT_CODE_MASK) == | |
305 | ASYNC_EVENT_CODE_QNQ); | |
306 | } | |
307 | ||
efd2e40a | 308 | static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) |
5fb379ee | 309 | { |
8788fdc2 | 310 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; |
efd2e40a | 311 | struct be_mcc_compl *compl = queue_tail_node(mcc_cq); |
5fb379ee SP |
312 | |
313 | if (be_mcc_compl_is_new(compl)) { | |
314 | queue_tail_inc(mcc_cq); | |
315 | return compl; | |
316 | } | |
317 | return NULL; | |
318 | } | |
319 | ||
7a1e9b20 SP |
320 | void be_async_mcc_enable(struct be_adapter *adapter) |
321 | { | |
322 | spin_lock_bh(&adapter->mcc_cq_lock); | |
323 | ||
324 | be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); | |
325 | adapter->mcc_obj.rearm_cq = true; | |
326 | ||
327 | spin_unlock_bh(&adapter->mcc_cq_lock); | |
328 | } | |
329 | ||
330 | void be_async_mcc_disable(struct be_adapter *adapter) | |
331 | { | |
a323d9bf SP |
332 | spin_lock_bh(&adapter->mcc_cq_lock); |
333 | ||
7a1e9b20 | 334 | adapter->mcc_obj.rearm_cq = false; |
a323d9bf SP |
335 | be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0); |
336 | ||
337 | spin_unlock_bh(&adapter->mcc_cq_lock); | |
7a1e9b20 SP |
338 | } |
339 | ||
10ef9ab4 | 340 | int be_process_mcc(struct be_adapter *adapter) |
5fb379ee | 341 | { |
efd2e40a | 342 | struct be_mcc_compl *compl; |
10ef9ab4 | 343 | int num = 0, status = 0; |
7a1e9b20 | 344 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; |
5fb379ee | 345 | |
072a9c48 | 346 | spin_lock(&adapter->mcc_cq_lock); |
8788fdc2 | 347 | while ((compl = be_mcc_compl_get(adapter))) { |
a8f447bd SP |
348 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { |
349 | /* Interpret flags as an async trailer */ | |
323f30b3 AK |
350 | if (is_link_state_evt(compl->flags)) |
351 | be_async_link_state_process(adapter, | |
a8f447bd | 352 | (struct be_async_event_link_state *) compl); |
cc4ce020 SK |
353 | else if (is_grp5_evt(compl->flags)) |
354 | be_async_grp5_evt_process(adapter, | |
355 | compl->flags, compl); | |
bc0c3405 AK |
356 | else if (is_dbg_evt(compl->flags)) |
357 | be_async_dbg_evt_process(adapter, | |
358 | compl->flags, compl); | |
b31c50a7 | 359 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
10ef9ab4 | 360 | status = be_mcc_compl_process(adapter, compl); |
7a1e9b20 | 361 | atomic_dec(&mcc_obj->q.used); |
5fb379ee SP |
362 | } |
363 | be_mcc_compl_use(compl); | |
364 | num++; | |
365 | } | |
b31c50a7 | 366 | |
10ef9ab4 SP |
367 | if (num) |
368 | be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num); | |
369 | ||
072a9c48 | 370 | spin_unlock(&adapter->mcc_cq_lock); |
10ef9ab4 | 371 | return status; |
5fb379ee SP |
372 | } |
373 | ||
6ac7b687 | 374 | /* Wait till no more pending mcc requests are present */ |
b31c50a7 | 375 | static int be_mcc_wait_compl(struct be_adapter *adapter) |
6ac7b687 | 376 | { |
b31c50a7 | 377 | #define mcc_timeout 120000 /* 12s timeout */ |
10ef9ab4 | 378 | int i, status = 0; |
f31e50a8 SP |
379 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; |
380 | ||
6ac7b687 | 381 | for (i = 0; i < mcc_timeout; i++) { |
6589ade0 SP |
382 | if (be_error(adapter)) |
383 | return -EIO; | |
384 | ||
072a9c48 | 385 | local_bh_disable(); |
10ef9ab4 | 386 | status = be_process_mcc(adapter); |
072a9c48 | 387 | local_bh_enable(); |
b31c50a7 | 388 | |
f31e50a8 | 389 | if (atomic_read(&mcc_obj->q.used) == 0) |
6ac7b687 SP |
390 | break; |
391 | udelay(100); | |
392 | } | |
b31c50a7 | 393 | if (i == mcc_timeout) { |
6589ade0 SP |
394 | dev_err(&adapter->pdev->dev, "FW not responding\n"); |
395 | adapter->fw_timeout = true; | |
652bf646 | 396 | return -EIO; |
b31c50a7 | 397 | } |
f31e50a8 | 398 | return status; |
6ac7b687 SP |
399 | } |
400 | ||
401 | /* Notify MCC requests and wait for completion */ | |
b31c50a7 | 402 | static int be_mcc_notify_wait(struct be_adapter *adapter) |
6ac7b687 | 403 | { |
652bf646 PR |
404 | int status; |
405 | struct be_mcc_wrb *wrb; | |
406 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; | |
407 | u16 index = mcc_obj->q.head; | |
408 | struct be_cmd_resp_hdr *resp; | |
409 | ||
410 | index_dec(&index, mcc_obj->q.len); | |
411 | wrb = queue_index_node(&mcc_obj->q, index); | |
412 | ||
413 | resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1); | |
414 | ||
8788fdc2 | 415 | be_mcc_notify(adapter); |
652bf646 PR |
416 | |
417 | status = be_mcc_wait_compl(adapter); | |
418 | if (status == -EIO) | |
419 | goto out; | |
420 | ||
421 | status = resp->status; | |
422 | out: | |
423 | return status; | |
6ac7b687 SP |
424 | } |
425 | ||
5f0b849e | 426 | static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) |
6b7c5b94 | 427 | { |
f25b03a7 | 428 | int msecs = 0; |
6b7c5b94 SP |
429 | u32 ready; |
430 | ||
431 | do { | |
6589ade0 SP |
432 | if (be_error(adapter)) |
433 | return -EIO; | |
434 | ||
cf588477 | 435 | ready = ioread32(db); |
434b3648 | 436 | if (ready == 0xffffffff) |
cf588477 | 437 | return -1; |
cf588477 SP |
438 | |
439 | ready &= MPU_MAILBOX_DB_RDY_MASK; | |
6b7c5b94 SP |
440 | if (ready) |
441 | break; | |
442 | ||
f25b03a7 | 443 | if (msecs > 4000) { |
6589ade0 SP |
444 | dev_err(&adapter->pdev->dev, "FW not responding\n"); |
445 | adapter->fw_timeout = true; | |
f67ef7ba | 446 | be_detect_error(adapter); |
6b7c5b94 SP |
447 | return -1; |
448 | } | |
449 | ||
1dbf53a2 | 450 | msleep(1); |
f25b03a7 | 451 | msecs++; |
6b7c5b94 SP |
452 | } while (true); |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | /* | |
458 | * Insert the mailbox address into the doorbell in two steps | |
5fb379ee | 459 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs |
6b7c5b94 | 460 | */ |
b31c50a7 | 461 | static int be_mbox_notify_wait(struct be_adapter *adapter) |
6b7c5b94 SP |
462 | { |
463 | int status; | |
6b7c5b94 | 464 | u32 val = 0; |
8788fdc2 SP |
465 | void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; |
466 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; | |
6b7c5b94 | 467 | struct be_mcc_mailbox *mbox = mbox_mem->va; |
efd2e40a | 468 | struct be_mcc_compl *compl = &mbox->compl; |
6b7c5b94 | 469 | |
cf588477 SP |
470 | /* wait for ready to be set */ |
471 | status = be_mbox_db_ready_wait(adapter, db); | |
472 | if (status != 0) | |
473 | return status; | |
474 | ||
6b7c5b94 SP |
475 | val |= MPU_MAILBOX_DB_HI_MASK; |
476 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | |
477 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | |
478 | iowrite32(val, db); | |
479 | ||
480 | /* wait for ready to be set */ | |
5f0b849e | 481 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
482 | if (status != 0) |
483 | return status; | |
484 | ||
485 | val = 0; | |
6b7c5b94 SP |
486 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ |
487 | val |= (u32)(mbox_mem->dma >> 4) << 2; | |
488 | iowrite32(val, db); | |
489 | ||
5f0b849e | 490 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
491 | if (status != 0) |
492 | return status; | |
493 | ||
5fb379ee | 494 | /* A cq entry has been made now */ |
efd2e40a SP |
495 | if (be_mcc_compl_is_new(compl)) { |
496 | status = be_mcc_compl_process(adapter, &mbox->compl); | |
497 | be_mcc_compl_use(compl); | |
5fb379ee SP |
498 | if (status) |
499 | return status; | |
500 | } else { | |
5f0b849e | 501 | dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); |
6b7c5b94 SP |
502 | return -1; |
503 | } | |
5fb379ee | 504 | return 0; |
6b7c5b94 SP |
505 | } |
506 | ||
c5b3ad4c | 507 | static u16 be_POST_stage_get(struct be_adapter *adapter) |
6b7c5b94 | 508 | { |
fe6d2a38 SP |
509 | u32 sem; |
510 | ||
c5b3ad4c SP |
511 | if (BEx_chip(adapter)) |
512 | sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx); | |
6b7c5b94 | 513 | else |
c5b3ad4c SP |
514 | pci_read_config_dword(adapter->pdev, |
515 | SLIPORT_SEMAPHORE_OFFSET_SH, &sem); | |
516 | ||
517 | return sem & POST_STAGE_MASK; | |
6b7c5b94 SP |
518 | } |
519 | ||
bf99e50d PR |
520 | int lancer_wait_ready(struct be_adapter *adapter) |
521 | { | |
522 | #define SLIPORT_READY_TIMEOUT 30 | |
523 | u32 sliport_status; | |
524 | int status = 0, i; | |
525 | ||
526 | for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { | |
527 | sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); | |
528 | if (sliport_status & SLIPORT_STATUS_RDY_MASK) | |
529 | break; | |
530 | ||
531 | msleep(1000); | |
532 | } | |
533 | ||
534 | if (i == SLIPORT_READY_TIMEOUT) | |
535 | status = -1; | |
536 | ||
537 | return status; | |
538 | } | |
539 | ||
67297ad8 PR |
540 | static bool lancer_provisioning_error(struct be_adapter *adapter) |
541 | { | |
542 | u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0; | |
543 | sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); | |
544 | if (sliport_status & SLIPORT_STATUS_ERR_MASK) { | |
545 | sliport_err1 = ioread32(adapter->db + | |
546 | SLIPORT_ERROR1_OFFSET); | |
547 | sliport_err2 = ioread32(adapter->db + | |
548 | SLIPORT_ERROR2_OFFSET); | |
549 | ||
550 | if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 && | |
551 | sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2) | |
552 | return true; | |
553 | } | |
554 | return false; | |
555 | } | |
556 | ||
bf99e50d PR |
557 | int lancer_test_and_set_rdy_state(struct be_adapter *adapter) |
558 | { | |
559 | int status; | |
560 | u32 sliport_status, err, reset_needed; | |
67297ad8 PR |
561 | bool resource_error; |
562 | ||
563 | resource_error = lancer_provisioning_error(adapter); | |
564 | if (resource_error) | |
01e5b2c4 | 565 | return -EAGAIN; |
67297ad8 | 566 | |
bf99e50d PR |
567 | status = lancer_wait_ready(adapter); |
568 | if (!status) { | |
569 | sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); | |
570 | err = sliport_status & SLIPORT_STATUS_ERR_MASK; | |
571 | reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK; | |
572 | if (err && reset_needed) { | |
573 | iowrite32(SLI_PORT_CONTROL_IP_MASK, | |
574 | adapter->db + SLIPORT_CONTROL_OFFSET); | |
575 | ||
576 | /* check adapter has corrected the error */ | |
577 | status = lancer_wait_ready(adapter); | |
578 | sliport_status = ioread32(adapter->db + | |
579 | SLIPORT_STATUS_OFFSET); | |
580 | sliport_status &= (SLIPORT_STATUS_ERR_MASK | | |
581 | SLIPORT_STATUS_RN_MASK); | |
582 | if (status || sliport_status) | |
583 | status = -1; | |
584 | } else if (err || reset_needed) { | |
585 | status = -1; | |
586 | } | |
587 | } | |
67297ad8 PR |
588 | /* Stop error recovery if error is not recoverable. |
589 | * No resource error is temporary errors and will go away | |
590 | * when PF provisions resources. | |
591 | */ | |
592 | resource_error = lancer_provisioning_error(adapter); | |
01e5b2c4 SK |
593 | if (resource_error) |
594 | status = -EAGAIN; | |
67297ad8 | 595 | |
bf99e50d PR |
596 | return status; |
597 | } | |
598 | ||
599 | int be_fw_wait_ready(struct be_adapter *adapter) | |
6b7c5b94 | 600 | { |
43a04fdc SP |
601 | u16 stage; |
602 | int status, timeout = 0; | |
6ed35eea | 603 | struct device *dev = &adapter->pdev->dev; |
6b7c5b94 | 604 | |
bf99e50d PR |
605 | if (lancer_chip(adapter)) { |
606 | status = lancer_wait_ready(adapter); | |
607 | return status; | |
608 | } | |
609 | ||
43a04fdc | 610 | do { |
c5b3ad4c | 611 | stage = be_POST_stage_get(adapter); |
66d29cbc | 612 | if (stage == POST_STAGE_ARMFW_RDY) |
43a04fdc | 613 | return 0; |
66d29cbc GS |
614 | |
615 | dev_info(dev, "Waiting for POST, %ds elapsed\n", | |
616 | timeout); | |
617 | if (msleep_interruptible(2000)) { | |
618 | dev_err(dev, "Waiting for POST aborted\n"); | |
619 | return -EINTR; | |
43a04fdc | 620 | } |
66d29cbc | 621 | timeout += 2; |
3ab81b5f | 622 | } while (timeout < 60); |
6b7c5b94 | 623 | |
6ed35eea | 624 | dev_err(dev, "POST timeout; stage=0x%x\n", stage); |
43a04fdc | 625 | return -1; |
6b7c5b94 SP |
626 | } |
627 | ||
6b7c5b94 SP |
628 | |
629 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) | |
630 | { | |
631 | return &wrb->payload.sgl[0]; | |
632 | } | |
633 | ||
6b7c5b94 SP |
634 | |
635 | /* Don't touch the hdr after it's prepared */ | |
106df1e3 SK |
636 | /* mem will be NULL for embedded commands */ |
637 | static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | |
638 | u8 subsystem, u8 opcode, int cmd_len, | |
639 | struct be_mcc_wrb *wrb, struct be_dma_mem *mem) | |
6b7c5b94 | 640 | { |
106df1e3 | 641 | struct be_sge *sge; |
652bf646 PR |
642 | unsigned long addr = (unsigned long)req_hdr; |
643 | u64 req_addr = addr; | |
106df1e3 | 644 | |
6b7c5b94 SP |
645 | req_hdr->opcode = opcode; |
646 | req_hdr->subsystem = subsystem; | |
647 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | |
07793d33 | 648 | req_hdr->version = 0; |
106df1e3 | 649 | |
652bf646 PR |
650 | wrb->tag0 = req_addr & 0xFFFFFFFF; |
651 | wrb->tag1 = upper_32_bits(req_addr); | |
652 | ||
106df1e3 SK |
653 | wrb->payload_length = cmd_len; |
654 | if (mem) { | |
655 | wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) << | |
656 | MCC_WRB_SGE_CNT_SHIFT; | |
657 | sge = nonembedded_sgl(wrb); | |
658 | sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); | |
659 | sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); | |
660 | sge->len = cpu_to_le32(mem->size); | |
661 | } else | |
662 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | |
663 | be_dws_cpu_to_le(wrb, 8); | |
6b7c5b94 SP |
664 | } |
665 | ||
666 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | |
667 | struct be_dma_mem *mem) | |
668 | { | |
669 | int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | |
670 | u64 dma = (u64)mem->dma; | |
671 | ||
672 | for (i = 0; i < buf_pages; i++) { | |
673 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | |
674 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | |
675 | dma += PAGE_SIZE_4K; | |
676 | } | |
677 | } | |
678 | ||
679 | /* Converts interrupt delay in microseconds to multiplier value */ | |
680 | static u32 eq_delay_to_mult(u32 usec_delay) | |
681 | { | |
682 | #define MAX_INTR_RATE 651042 | |
683 | const u32 round = 10; | |
684 | u32 multiplier; | |
685 | ||
686 | if (usec_delay == 0) | |
687 | multiplier = 0; | |
688 | else { | |
689 | u32 interrupt_rate = 1000000 / usec_delay; | |
690 | /* Max delay, corresponding to the lowest interrupt rate */ | |
691 | if (interrupt_rate == 0) | |
692 | multiplier = 1023; | |
693 | else { | |
694 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | |
695 | multiplier /= interrupt_rate; | |
696 | /* Round the multiplier to the closest value.*/ | |
697 | multiplier = (multiplier + round/2) / round; | |
698 | multiplier = min(multiplier, (u32)1023); | |
699 | } | |
700 | } | |
701 | return multiplier; | |
702 | } | |
703 | ||
b31c50a7 | 704 | static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) |
6b7c5b94 | 705 | { |
b31c50a7 SP |
706 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; |
707 | struct be_mcc_wrb *wrb | |
708 | = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | |
709 | memset(wrb, 0, sizeof(*wrb)); | |
710 | return wrb; | |
6b7c5b94 SP |
711 | } |
712 | ||
b31c50a7 | 713 | static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) |
5fb379ee | 714 | { |
b31c50a7 SP |
715 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
716 | struct be_mcc_wrb *wrb; | |
717 | ||
aa790db9 PR |
718 | if (!mccq->created) |
719 | return NULL; | |
720 | ||
4d277125 | 721 | if (atomic_read(&mccq->used) >= mccq->len) |
713d0394 | 722 | return NULL; |
713d0394 | 723 | |
b31c50a7 SP |
724 | wrb = queue_head_node(mccq); |
725 | queue_head_inc(mccq); | |
726 | atomic_inc(&mccq->used); | |
727 | memset(wrb, 0, sizeof(*wrb)); | |
5fb379ee SP |
728 | return wrb; |
729 | } | |
730 | ||
2243e2e9 SP |
731 | /* Tell fw we're about to start firing cmds by writing a |
732 | * special pattern across the wrb hdr; uses mbox | |
733 | */ | |
734 | int be_cmd_fw_init(struct be_adapter *adapter) | |
735 | { | |
736 | u8 *wrb; | |
737 | int status; | |
738 | ||
bf99e50d PR |
739 | if (lancer_chip(adapter)) |
740 | return 0; | |
741 | ||
2984961c IV |
742 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
743 | return -1; | |
2243e2e9 SP |
744 | |
745 | wrb = (u8 *)wrb_from_mbox(adapter); | |
359a972f SP |
746 | *wrb++ = 0xFF; |
747 | *wrb++ = 0x12; | |
748 | *wrb++ = 0x34; | |
749 | *wrb++ = 0xFF; | |
750 | *wrb++ = 0xFF; | |
751 | *wrb++ = 0x56; | |
752 | *wrb++ = 0x78; | |
753 | *wrb = 0xFF; | |
2243e2e9 SP |
754 | |
755 | status = be_mbox_notify_wait(adapter); | |
756 | ||
2984961c | 757 | mutex_unlock(&adapter->mbox_lock); |
2243e2e9 SP |
758 | return status; |
759 | } | |
760 | ||
761 | /* Tell fw we're done with firing cmds by writing a | |
762 | * special pattern across the wrb hdr; uses mbox | |
763 | */ | |
764 | int be_cmd_fw_clean(struct be_adapter *adapter) | |
765 | { | |
766 | u8 *wrb; | |
767 | int status; | |
768 | ||
bf99e50d PR |
769 | if (lancer_chip(adapter)) |
770 | return 0; | |
771 | ||
2984961c IV |
772 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
773 | return -1; | |
2243e2e9 SP |
774 | |
775 | wrb = (u8 *)wrb_from_mbox(adapter); | |
776 | *wrb++ = 0xFF; | |
777 | *wrb++ = 0xAA; | |
778 | *wrb++ = 0xBB; | |
779 | *wrb++ = 0xFF; | |
780 | *wrb++ = 0xFF; | |
781 | *wrb++ = 0xCC; | |
782 | *wrb++ = 0xDD; | |
783 | *wrb = 0xFF; | |
784 | ||
785 | status = be_mbox_notify_wait(adapter); | |
786 | ||
2984961c | 787 | mutex_unlock(&adapter->mbox_lock); |
2243e2e9 SP |
788 | return status; |
789 | } | |
bf99e50d | 790 | |
8788fdc2 | 791 | int be_cmd_eq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
792 | struct be_queue_info *eq, int eq_delay) |
793 | { | |
b31c50a7 SP |
794 | struct be_mcc_wrb *wrb; |
795 | struct be_cmd_req_eq_create *req; | |
6b7c5b94 SP |
796 | struct be_dma_mem *q_mem = &eq->dma_mem; |
797 | int status; | |
798 | ||
2984961c IV |
799 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
800 | return -1; | |
b31c50a7 SP |
801 | |
802 | wrb = wrb_from_mbox(adapter); | |
803 | req = embedded_payload(wrb); | |
6b7c5b94 | 804 | |
106df1e3 SK |
805 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
806 | OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL); | |
6b7c5b94 SP |
807 | |
808 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
809 | ||
6b7c5b94 SP |
810 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); |
811 | /* 4byte eqe*/ | |
812 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | |
813 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | |
814 | __ilog2_u32(eq->len/256)); | |
815 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | |
816 | eq_delay_to_mult(eq_delay)); | |
817 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
818 | ||
819 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
820 | ||
b31c50a7 | 821 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 822 | if (!status) { |
b31c50a7 | 823 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
824 | eq->id = le16_to_cpu(resp->eq_id); |
825 | eq->created = true; | |
826 | } | |
b31c50a7 | 827 | |
2984961c | 828 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
829 | return status; |
830 | } | |
831 | ||
f9449ab7 | 832 | /* Use MCC */ |
8788fdc2 | 833 | int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, |
5ee4979b | 834 | bool permanent, u32 if_handle, u32 pmac_id) |
6b7c5b94 | 835 | { |
b31c50a7 SP |
836 | struct be_mcc_wrb *wrb; |
837 | struct be_cmd_req_mac_query *req; | |
6b7c5b94 SP |
838 | int status; |
839 | ||
f9449ab7 | 840 | spin_lock_bh(&adapter->mcc_lock); |
b31c50a7 | 841 | |
f9449ab7 SP |
842 | wrb = wrb_from_mccq(adapter); |
843 | if (!wrb) { | |
844 | status = -EBUSY; | |
845 | goto err; | |
846 | } | |
b31c50a7 | 847 | req = embedded_payload(wrb); |
6b7c5b94 | 848 | |
106df1e3 SK |
849 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
850 | OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL); | |
5ee4979b | 851 | req->type = MAC_ADDRESS_TYPE_NETWORK; |
6b7c5b94 SP |
852 | if (permanent) { |
853 | req->permanent = 1; | |
854 | } else { | |
b31c50a7 | 855 | req->if_id = cpu_to_le16((u16) if_handle); |
590c391d | 856 | req->pmac_id = cpu_to_le32(pmac_id); |
6b7c5b94 SP |
857 | req->permanent = 0; |
858 | } | |
859 | ||
f9449ab7 | 860 | status = be_mcc_notify_wait(adapter); |
b31c50a7 SP |
861 | if (!status) { |
862 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | |
6b7c5b94 | 863 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); |
b31c50a7 | 864 | } |
6b7c5b94 | 865 | |
f9449ab7 SP |
866 | err: |
867 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
868 | return status; |
869 | } | |
870 | ||
b31c50a7 | 871 | /* Uses synchronous MCCQ */ |
8788fdc2 | 872 | int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, |
f8617e08 | 873 | u32 if_id, u32 *pmac_id, u32 domain) |
6b7c5b94 | 874 | { |
b31c50a7 SP |
875 | struct be_mcc_wrb *wrb; |
876 | struct be_cmd_req_pmac_add *req; | |
6b7c5b94 SP |
877 | int status; |
878 | ||
b31c50a7 SP |
879 | spin_lock_bh(&adapter->mcc_lock); |
880 | ||
881 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
882 | if (!wrb) { |
883 | status = -EBUSY; | |
884 | goto err; | |
885 | } | |
b31c50a7 | 886 | req = embedded_payload(wrb); |
6b7c5b94 | 887 | |
106df1e3 SK |
888 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
889 | OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL); | |
6b7c5b94 | 890 | |
f8617e08 | 891 | req->hdr.domain = domain; |
6b7c5b94 SP |
892 | req->if_id = cpu_to_le32(if_id); |
893 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | |
894 | ||
b31c50a7 | 895 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
896 | if (!status) { |
897 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | |
898 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
899 | } | |
900 | ||
713d0394 | 901 | err: |
b31c50a7 | 902 | spin_unlock_bh(&adapter->mcc_lock); |
e3a7ae2c SK |
903 | |
904 | if (status == MCC_STATUS_UNAUTHORIZED_REQUEST) | |
905 | status = -EPERM; | |
906 | ||
6b7c5b94 SP |
907 | return status; |
908 | } | |
909 | ||
b31c50a7 | 910 | /* Uses synchronous MCCQ */ |
30128031 | 911 | int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom) |
6b7c5b94 | 912 | { |
b31c50a7 SP |
913 | struct be_mcc_wrb *wrb; |
914 | struct be_cmd_req_pmac_del *req; | |
6b7c5b94 SP |
915 | int status; |
916 | ||
30128031 SP |
917 | if (pmac_id == -1) |
918 | return 0; | |
919 | ||
b31c50a7 SP |
920 | spin_lock_bh(&adapter->mcc_lock); |
921 | ||
922 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
923 | if (!wrb) { |
924 | status = -EBUSY; | |
925 | goto err; | |
926 | } | |
b31c50a7 | 927 | req = embedded_payload(wrb); |
6b7c5b94 | 928 | |
106df1e3 SK |
929 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
930 | OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL); | |
6b7c5b94 | 931 | |
f8617e08 | 932 | req->hdr.domain = dom; |
6b7c5b94 SP |
933 | req->if_id = cpu_to_le32(if_id); |
934 | req->pmac_id = cpu_to_le32(pmac_id); | |
935 | ||
b31c50a7 SP |
936 | status = be_mcc_notify_wait(adapter); |
937 | ||
713d0394 | 938 | err: |
b31c50a7 | 939 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
940 | return status; |
941 | } | |
942 | ||
b31c50a7 | 943 | /* Uses Mbox */ |
10ef9ab4 SP |
944 | int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, |
945 | struct be_queue_info *eq, bool no_delay, int coalesce_wm) | |
6b7c5b94 | 946 | { |
b31c50a7 SP |
947 | struct be_mcc_wrb *wrb; |
948 | struct be_cmd_req_cq_create *req; | |
6b7c5b94 | 949 | struct be_dma_mem *q_mem = &cq->dma_mem; |
b31c50a7 | 950 | void *ctxt; |
6b7c5b94 SP |
951 | int status; |
952 | ||
2984961c IV |
953 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
954 | return -1; | |
b31c50a7 SP |
955 | |
956 | wrb = wrb_from_mbox(adapter); | |
957 | req = embedded_payload(wrb); | |
958 | ctxt = &req->context; | |
6b7c5b94 | 959 | |
106df1e3 SK |
960 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
961 | OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL); | |
6b7c5b94 SP |
962 | |
963 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
bbdc42f8 AK |
964 | |
965 | if (BEx_chip(adapter)) { | |
fe6d2a38 SP |
966 | AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, |
967 | coalesce_wm); | |
968 | AMAP_SET_BITS(struct amap_cq_context_be, nodelay, | |
969 | ctxt, no_delay); | |
970 | AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, | |
971 | __ilog2_u32(cq->len/256)); | |
972 | AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); | |
fe6d2a38 SP |
973 | AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1); |
974 | AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id); | |
bbdc42f8 AK |
975 | } else { |
976 | req->hdr.version = 2; | |
977 | req->page_size = 1; /* 1 for 4K */ | |
978 | AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt, | |
979 | no_delay); | |
980 | AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, | |
981 | __ilog2_u32(cq->len/256)); | |
982 | AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); | |
983 | AMAP_SET_BITS(struct amap_cq_context_v2, eventable, | |
984 | ctxt, 1); | |
985 | AMAP_SET_BITS(struct amap_cq_context_v2, eqid, | |
986 | ctxt, eq->id); | |
fe6d2a38 | 987 | } |
6b7c5b94 | 988 | |
6b7c5b94 SP |
989 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
990 | ||
991 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
992 | ||
b31c50a7 | 993 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 994 | if (!status) { |
b31c50a7 | 995 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
996 | cq->id = le16_to_cpu(resp->cq_id); |
997 | cq->created = true; | |
998 | } | |
b31c50a7 | 999 | |
2984961c | 1000 | mutex_unlock(&adapter->mbox_lock); |
5fb379ee SP |
1001 | |
1002 | return status; | |
1003 | } | |
1004 | ||
1005 | static u32 be_encoded_q_len(int q_len) | |
1006 | { | |
1007 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
1008 | if (len_encoded == 16) | |
1009 | len_encoded = 0; | |
1010 | return len_encoded; | |
1011 | } | |
1012 | ||
34b1ef04 | 1013 | int be_cmd_mccq_ext_create(struct be_adapter *adapter, |
5fb379ee SP |
1014 | struct be_queue_info *mccq, |
1015 | struct be_queue_info *cq) | |
1016 | { | |
b31c50a7 | 1017 | struct be_mcc_wrb *wrb; |
34b1ef04 | 1018 | struct be_cmd_req_mcc_ext_create *req; |
5fb379ee | 1019 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
b31c50a7 | 1020 | void *ctxt; |
5fb379ee SP |
1021 | int status; |
1022 | ||
2984961c IV |
1023 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1024 | return -1; | |
b31c50a7 SP |
1025 | |
1026 | wrb = wrb_from_mbox(adapter); | |
1027 | req = embedded_payload(wrb); | |
1028 | ctxt = &req->context; | |
5fb379ee | 1029 | |
106df1e3 SK |
1030 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1031 | OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL); | |
5fb379ee | 1032 | |
d4a2ac3e | 1033 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); |
fe6d2a38 SP |
1034 | if (lancer_chip(adapter)) { |
1035 | req->hdr.version = 1; | |
1036 | req->cq_id = cpu_to_le16(cq->id); | |
1037 | ||
1038 | AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt, | |
1039 | be_encoded_q_len(mccq->len)); | |
1040 | AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1); | |
1041 | AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id, | |
1042 | ctxt, cq->id); | |
1043 | AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid, | |
1044 | ctxt, 1); | |
1045 | ||
1046 | } else { | |
1047 | AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); | |
1048 | AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, | |
1049 | be_encoded_q_len(mccq->len)); | |
1050 | AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); | |
1051 | } | |
5fb379ee | 1052 | |
cc4ce020 | 1053 | /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */ |
fe6d2a38 | 1054 | req->async_event_bitmap[0] = cpu_to_le32(0x00000022); |
bc0c3405 | 1055 | req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ); |
5fb379ee SP |
1056 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
1057 | ||
1058 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
1059 | ||
b31c50a7 | 1060 | status = be_mbox_notify_wait(adapter); |
5fb379ee SP |
1061 | if (!status) { |
1062 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
1063 | mccq->id = le16_to_cpu(resp->id); | |
1064 | mccq->created = true; | |
1065 | } | |
2984961c | 1066 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1067 | |
1068 | return status; | |
1069 | } | |
1070 | ||
34b1ef04 SK |
1071 | int be_cmd_mccq_org_create(struct be_adapter *adapter, |
1072 | struct be_queue_info *mccq, | |
1073 | struct be_queue_info *cq) | |
1074 | { | |
1075 | struct be_mcc_wrb *wrb; | |
1076 | struct be_cmd_req_mcc_create *req; | |
1077 | struct be_dma_mem *q_mem = &mccq->dma_mem; | |
1078 | void *ctxt; | |
1079 | int status; | |
1080 | ||
1081 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | |
1082 | return -1; | |
1083 | ||
1084 | wrb = wrb_from_mbox(adapter); | |
1085 | req = embedded_payload(wrb); | |
1086 | ctxt = &req->context; | |
1087 | ||
106df1e3 SK |
1088 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1089 | OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL); | |
34b1ef04 SK |
1090 | |
1091 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
1092 | ||
1093 | AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); | |
1094 | AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, | |
1095 | be_encoded_q_len(mccq->len)); | |
1096 | AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); | |
1097 | ||
1098 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
1099 | ||
1100 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
1101 | ||
1102 | status = be_mbox_notify_wait(adapter); | |
1103 | if (!status) { | |
1104 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
1105 | mccq->id = le16_to_cpu(resp->id); | |
1106 | mccq->created = true; | |
1107 | } | |
1108 | ||
1109 | mutex_unlock(&adapter->mbox_lock); | |
1110 | return status; | |
1111 | } | |
1112 | ||
1113 | int be_cmd_mccq_create(struct be_adapter *adapter, | |
1114 | struct be_queue_info *mccq, | |
1115 | struct be_queue_info *cq) | |
1116 | { | |
1117 | int status; | |
1118 | ||
1119 | status = be_cmd_mccq_ext_create(adapter, mccq, cq); | |
1120 | if (status && !lancer_chip(adapter)) { | |
1121 | dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 " | |
1122 | "or newer to avoid conflicting priorities between NIC " | |
1123 | "and FCoE traffic"); | |
1124 | status = be_cmd_mccq_org_create(adapter, mccq, cq); | |
1125 | } | |
1126 | return status; | |
1127 | } | |
1128 | ||
94d73aaa | 1129 | int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo) |
6b7c5b94 | 1130 | { |
b31c50a7 SP |
1131 | struct be_mcc_wrb *wrb; |
1132 | struct be_cmd_req_eth_tx_create *req; | |
94d73aaa VV |
1133 | struct be_queue_info *txq = &txo->q; |
1134 | struct be_queue_info *cq = &txo->cq; | |
6b7c5b94 | 1135 | struct be_dma_mem *q_mem = &txq->dma_mem; |
94d73aaa | 1136 | int status, ver = 0; |
6b7c5b94 | 1137 | |
293c4a7d PR |
1138 | spin_lock_bh(&adapter->mcc_lock); |
1139 | ||
1140 | wrb = wrb_from_mccq(adapter); | |
1141 | if (!wrb) { | |
1142 | status = -EBUSY; | |
1143 | goto err; | |
1144 | } | |
b31c50a7 | 1145 | |
b31c50a7 | 1146 | req = embedded_payload(wrb); |
6b7c5b94 | 1147 | |
106df1e3 SK |
1148 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, |
1149 | OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL); | |
6b7c5b94 | 1150 | |
8b7756ca PR |
1151 | if (lancer_chip(adapter)) { |
1152 | req->hdr.version = 1; | |
94d73aaa VV |
1153 | req->if_id = cpu_to_le16(adapter->if_handle); |
1154 | } else if (BEx_chip(adapter)) { | |
1155 | if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC) | |
1156 | req->hdr.version = 2; | |
1157 | } else { /* For SH */ | |
1158 | req->hdr.version = 2; | |
8b7756ca PR |
1159 | } |
1160 | ||
6b7c5b94 SP |
1161 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); |
1162 | req->ulp_num = BE_ULP1_NUM; | |
1163 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | |
94d73aaa VV |
1164 | req->cq_id = cpu_to_le16(cq->id); |
1165 | req->queue_size = be_encoded_q_len(txq->len); | |
6b7c5b94 SP |
1166 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); |
1167 | ||
94d73aaa VV |
1168 | ver = req->hdr.version; |
1169 | ||
293c4a7d | 1170 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1171 | if (!status) { |
1172 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | |
1173 | txq->id = le16_to_cpu(resp->cid); | |
94d73aaa VV |
1174 | if (ver == 2) |
1175 | txo->db_offset = le32_to_cpu(resp->db_offset); | |
1176 | else | |
1177 | txo->db_offset = DB_TXULP1_OFFSET; | |
6b7c5b94 SP |
1178 | txq->created = true; |
1179 | } | |
b31c50a7 | 1180 | |
293c4a7d PR |
1181 | err: |
1182 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
1183 | |
1184 | return status; | |
1185 | } | |
1186 | ||
482c9e79 | 1187 | /* Uses MCC */ |
8788fdc2 | 1188 | int be_cmd_rxq_create(struct be_adapter *adapter, |
6b7c5b94 | 1189 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, |
10ef9ab4 | 1190 | u32 if_id, u32 rss, u8 *rss_id) |
6b7c5b94 | 1191 | { |
b31c50a7 SP |
1192 | struct be_mcc_wrb *wrb; |
1193 | struct be_cmd_req_eth_rx_create *req; | |
6b7c5b94 SP |
1194 | struct be_dma_mem *q_mem = &rxq->dma_mem; |
1195 | int status; | |
1196 | ||
482c9e79 | 1197 | spin_lock_bh(&adapter->mcc_lock); |
b31c50a7 | 1198 | |
482c9e79 SP |
1199 | wrb = wrb_from_mccq(adapter); |
1200 | if (!wrb) { | |
1201 | status = -EBUSY; | |
1202 | goto err; | |
1203 | } | |
b31c50a7 | 1204 | req = embedded_payload(wrb); |
6b7c5b94 | 1205 | |
106df1e3 SK |
1206 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, |
1207 | OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL); | |
6b7c5b94 SP |
1208 | |
1209 | req->cq_id = cpu_to_le16(cq_id); | |
1210 | req->frag_size = fls(frag_size) - 1; | |
1211 | req->num_pages = 2; | |
1212 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
1213 | req->interface_id = cpu_to_le32(if_id); | |
10ef9ab4 | 1214 | req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE); |
6b7c5b94 SP |
1215 | req->rss_queue = cpu_to_le32(rss); |
1216 | ||
482c9e79 | 1217 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1218 | if (!status) { |
1219 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | |
1220 | rxq->id = le16_to_cpu(resp->id); | |
1221 | rxq->created = true; | |
3abcdeda | 1222 | *rss_id = resp->rss_id; |
6b7c5b94 | 1223 | } |
b31c50a7 | 1224 | |
482c9e79 SP |
1225 | err: |
1226 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
1227 | return status; |
1228 | } | |
1229 | ||
b31c50a7 SP |
1230 | /* Generic destroyer function for all types of queues |
1231 | * Uses Mbox | |
1232 | */ | |
8788fdc2 | 1233 | int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
6b7c5b94 SP |
1234 | int queue_type) |
1235 | { | |
b31c50a7 SP |
1236 | struct be_mcc_wrb *wrb; |
1237 | struct be_cmd_req_q_destroy *req; | |
6b7c5b94 SP |
1238 | u8 subsys = 0, opcode = 0; |
1239 | int status; | |
1240 | ||
2984961c IV |
1241 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1242 | return -1; | |
6b7c5b94 | 1243 | |
b31c50a7 SP |
1244 | wrb = wrb_from_mbox(adapter); |
1245 | req = embedded_payload(wrb); | |
1246 | ||
6b7c5b94 SP |
1247 | switch (queue_type) { |
1248 | case QTYPE_EQ: | |
1249 | subsys = CMD_SUBSYSTEM_COMMON; | |
1250 | opcode = OPCODE_COMMON_EQ_DESTROY; | |
1251 | break; | |
1252 | case QTYPE_CQ: | |
1253 | subsys = CMD_SUBSYSTEM_COMMON; | |
1254 | opcode = OPCODE_COMMON_CQ_DESTROY; | |
1255 | break; | |
1256 | case QTYPE_TXQ: | |
1257 | subsys = CMD_SUBSYSTEM_ETH; | |
1258 | opcode = OPCODE_ETH_TX_DESTROY; | |
1259 | break; | |
1260 | case QTYPE_RXQ: | |
1261 | subsys = CMD_SUBSYSTEM_ETH; | |
1262 | opcode = OPCODE_ETH_RX_DESTROY; | |
1263 | break; | |
5fb379ee SP |
1264 | case QTYPE_MCCQ: |
1265 | subsys = CMD_SUBSYSTEM_COMMON; | |
1266 | opcode = OPCODE_COMMON_MCC_DESTROY; | |
1267 | break; | |
6b7c5b94 | 1268 | default: |
5f0b849e | 1269 | BUG(); |
6b7c5b94 | 1270 | } |
d744b44e | 1271 | |
106df1e3 SK |
1272 | be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb, |
1273 | NULL); | |
6b7c5b94 SP |
1274 | req->id = cpu_to_le16(q->id); |
1275 | ||
b31c50a7 | 1276 | status = be_mbox_notify_wait(adapter); |
aa790db9 | 1277 | q->created = false; |
5f0b849e | 1278 | |
2984961c | 1279 | mutex_unlock(&adapter->mbox_lock); |
482c9e79 SP |
1280 | return status; |
1281 | } | |
6b7c5b94 | 1282 | |
482c9e79 SP |
1283 | /* Uses MCC */ |
1284 | int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q) | |
1285 | { | |
1286 | struct be_mcc_wrb *wrb; | |
1287 | struct be_cmd_req_q_destroy *req; | |
1288 | int status; | |
1289 | ||
1290 | spin_lock_bh(&adapter->mcc_lock); | |
1291 | ||
1292 | wrb = wrb_from_mccq(adapter); | |
1293 | if (!wrb) { | |
1294 | status = -EBUSY; | |
1295 | goto err; | |
1296 | } | |
1297 | req = embedded_payload(wrb); | |
1298 | ||
106df1e3 SK |
1299 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, |
1300 | OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL); | |
482c9e79 SP |
1301 | req->id = cpu_to_le16(q->id); |
1302 | ||
1303 | status = be_mcc_notify_wait(adapter); | |
aa790db9 | 1304 | q->created = false; |
482c9e79 SP |
1305 | |
1306 | err: | |
1307 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
1308 | return status; |
1309 | } | |
1310 | ||
b31c50a7 | 1311 | /* Create an rx filtering policy configuration on an i/f |
f9449ab7 | 1312 | * Uses MCCQ |
b31c50a7 | 1313 | */ |
73d540f2 | 1314 | int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, |
1578e777 | 1315 | u32 *if_handle, u32 domain) |
6b7c5b94 | 1316 | { |
b31c50a7 SP |
1317 | struct be_mcc_wrb *wrb; |
1318 | struct be_cmd_req_if_create *req; | |
6b7c5b94 SP |
1319 | int status; |
1320 | ||
f9449ab7 | 1321 | spin_lock_bh(&adapter->mcc_lock); |
b31c50a7 | 1322 | |
f9449ab7 SP |
1323 | wrb = wrb_from_mccq(adapter); |
1324 | if (!wrb) { | |
1325 | status = -EBUSY; | |
1326 | goto err; | |
1327 | } | |
b31c50a7 | 1328 | req = embedded_payload(wrb); |
6b7c5b94 | 1329 | |
106df1e3 SK |
1330 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1331 | OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL); | |
ba343c77 | 1332 | req->hdr.domain = domain; |
73d540f2 SP |
1333 | req->capability_flags = cpu_to_le32(cap_flags); |
1334 | req->enable_flags = cpu_to_le32(en_flags); | |
1578e777 PR |
1335 | |
1336 | req->pmac_invalid = true; | |
6b7c5b94 | 1337 | |
f9449ab7 | 1338 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1339 | if (!status) { |
1340 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | |
1341 | *if_handle = le32_to_cpu(resp->interface_id); | |
6b7c5b94 SP |
1342 | } |
1343 | ||
f9449ab7 SP |
1344 | err: |
1345 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
1346 | return status; |
1347 | } | |
1348 | ||
f9449ab7 | 1349 | /* Uses MCCQ */ |
30128031 | 1350 | int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain) |
6b7c5b94 | 1351 | { |
b31c50a7 SP |
1352 | struct be_mcc_wrb *wrb; |
1353 | struct be_cmd_req_if_destroy *req; | |
6b7c5b94 SP |
1354 | int status; |
1355 | ||
30128031 | 1356 | if (interface_id == -1) |
f9449ab7 | 1357 | return 0; |
b31c50a7 | 1358 | |
f9449ab7 SP |
1359 | spin_lock_bh(&adapter->mcc_lock); |
1360 | ||
1361 | wrb = wrb_from_mccq(adapter); | |
1362 | if (!wrb) { | |
1363 | status = -EBUSY; | |
1364 | goto err; | |
1365 | } | |
b31c50a7 | 1366 | req = embedded_payload(wrb); |
6b7c5b94 | 1367 | |
106df1e3 SK |
1368 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1369 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL); | |
658681f7 | 1370 | req->hdr.domain = domain; |
6b7c5b94 | 1371 | req->interface_id = cpu_to_le32(interface_id); |
b31c50a7 | 1372 | |
f9449ab7 SP |
1373 | status = be_mcc_notify_wait(adapter); |
1374 | err: | |
1375 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
1376 | return status; |
1377 | } | |
1378 | ||
1379 | /* Get stats is a non embedded command: the request is not embedded inside | |
1380 | * WRB but is a separate dma memory block | |
b31c50a7 | 1381 | * Uses asynchronous MCC |
6b7c5b94 | 1382 | */ |
8788fdc2 | 1383 | int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) |
6b7c5b94 | 1384 | { |
b31c50a7 | 1385 | struct be_mcc_wrb *wrb; |
89a88ab8 | 1386 | struct be_cmd_req_hdr *hdr; |
713d0394 | 1387 | int status = 0; |
6b7c5b94 | 1388 | |
b31c50a7 | 1389 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1390 | |
b31c50a7 | 1391 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1392 | if (!wrb) { |
1393 | status = -EBUSY; | |
1394 | goto err; | |
1395 | } | |
89a88ab8 | 1396 | hdr = nonemb_cmd->va; |
6b7c5b94 | 1397 | |
106df1e3 SK |
1398 | be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, |
1399 | OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd); | |
89a88ab8 | 1400 | |
ca34fe38 SP |
1401 | /* version 1 of the cmd is not supported only by BE2 */ |
1402 | if (!BE2_chip(adapter)) | |
89a88ab8 AK |
1403 | hdr->version = 1; |
1404 | ||
b31c50a7 | 1405 | be_mcc_notify(adapter); |
b2aebe6d | 1406 | adapter->stats_cmd_sent = true; |
6b7c5b94 | 1407 | |
713d0394 | 1408 | err: |
b31c50a7 | 1409 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 1410 | return status; |
6b7c5b94 SP |
1411 | } |
1412 | ||
005d5696 SX |
1413 | /* Lancer Stats */ |
1414 | int lancer_cmd_get_pport_stats(struct be_adapter *adapter, | |
1415 | struct be_dma_mem *nonemb_cmd) | |
1416 | { | |
1417 | ||
1418 | struct be_mcc_wrb *wrb; | |
1419 | struct lancer_cmd_req_pport_stats *req; | |
005d5696 SX |
1420 | int status = 0; |
1421 | ||
f25b119c PR |
1422 | if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS, |
1423 | CMD_SUBSYSTEM_ETH)) | |
1424 | return -EPERM; | |
1425 | ||
005d5696 SX |
1426 | spin_lock_bh(&adapter->mcc_lock); |
1427 | ||
1428 | wrb = wrb_from_mccq(adapter); | |
1429 | if (!wrb) { | |
1430 | status = -EBUSY; | |
1431 | goto err; | |
1432 | } | |
1433 | req = nonemb_cmd->va; | |
005d5696 | 1434 | |
106df1e3 SK |
1435 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, |
1436 | OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb, | |
1437 | nonemb_cmd); | |
005d5696 | 1438 | |
d51ebd33 | 1439 | req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num); |
005d5696 SX |
1440 | req->cmd_params.params.reset_stats = 0; |
1441 | ||
005d5696 SX |
1442 | be_mcc_notify(adapter); |
1443 | adapter->stats_cmd_sent = true; | |
1444 | ||
1445 | err: | |
1446 | spin_unlock_bh(&adapter->mcc_lock); | |
1447 | return status; | |
1448 | } | |
1449 | ||
323ff71e SP |
1450 | static int be_mac_to_link_speed(int mac_speed) |
1451 | { | |
1452 | switch (mac_speed) { | |
1453 | case PHY_LINK_SPEED_ZERO: | |
1454 | return 0; | |
1455 | case PHY_LINK_SPEED_10MBPS: | |
1456 | return 10; | |
1457 | case PHY_LINK_SPEED_100MBPS: | |
1458 | return 100; | |
1459 | case PHY_LINK_SPEED_1GBPS: | |
1460 | return 1000; | |
1461 | case PHY_LINK_SPEED_10GBPS: | |
1462 | return 10000; | |
1463 | } | |
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | /* Uses synchronous mcc | |
1468 | * Returns link_speed in Mbps | |
1469 | */ | |
1470 | int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, | |
1471 | u8 *link_status, u32 dom) | |
6b7c5b94 | 1472 | { |
b31c50a7 SP |
1473 | struct be_mcc_wrb *wrb; |
1474 | struct be_cmd_req_link_status *req; | |
6b7c5b94 SP |
1475 | int status; |
1476 | ||
b31c50a7 SP |
1477 | spin_lock_bh(&adapter->mcc_lock); |
1478 | ||
b236916a AK |
1479 | if (link_status) |
1480 | *link_status = LINK_DOWN; | |
1481 | ||
b31c50a7 | 1482 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1483 | if (!wrb) { |
1484 | status = -EBUSY; | |
1485 | goto err; | |
1486 | } | |
b31c50a7 | 1487 | req = embedded_payload(wrb); |
a8f447bd | 1488 | |
57cd80d4 PR |
1489 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1490 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL); | |
1491 | ||
ca34fe38 SP |
1492 | /* version 1 of the cmd is not supported only by BE2 */ |
1493 | if (!BE2_chip(adapter)) | |
daad6167 PR |
1494 | req->hdr.version = 1; |
1495 | ||
57cd80d4 | 1496 | req->hdr.domain = dom; |
6b7c5b94 | 1497 | |
b31c50a7 | 1498 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1499 | if (!status) { |
1500 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | |
323ff71e SP |
1501 | if (link_speed) { |
1502 | *link_speed = resp->link_speed ? | |
1503 | le16_to_cpu(resp->link_speed) * 10 : | |
1504 | be_mac_to_link_speed(resp->mac_speed); | |
1505 | ||
1506 | if (!resp->logical_link_status) | |
1507 | *link_speed = 0; | |
0388f251 | 1508 | } |
b236916a AK |
1509 | if (link_status) |
1510 | *link_status = resp->logical_link_status; | |
6b7c5b94 SP |
1511 | } |
1512 | ||
713d0394 | 1513 | err: |
b31c50a7 | 1514 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1515 | return status; |
1516 | } | |
1517 | ||
609ff3bb AK |
1518 | /* Uses synchronous mcc */ |
1519 | int be_cmd_get_die_temperature(struct be_adapter *adapter) | |
1520 | { | |
1521 | struct be_mcc_wrb *wrb; | |
1522 | struct be_cmd_req_get_cntl_addnl_attribs *req; | |
1523 | int status; | |
1524 | ||
1525 | spin_lock_bh(&adapter->mcc_lock); | |
1526 | ||
1527 | wrb = wrb_from_mccq(adapter); | |
1528 | if (!wrb) { | |
1529 | status = -EBUSY; | |
1530 | goto err; | |
1531 | } | |
1532 | req = embedded_payload(wrb); | |
1533 | ||
106df1e3 SK |
1534 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1535 | OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req), | |
1536 | wrb, NULL); | |
609ff3bb | 1537 | |
3de09455 | 1538 | be_mcc_notify(adapter); |
609ff3bb AK |
1539 | |
1540 | err: | |
1541 | spin_unlock_bh(&adapter->mcc_lock); | |
1542 | return status; | |
1543 | } | |
1544 | ||
311fddc7 SK |
1545 | /* Uses synchronous mcc */ |
1546 | int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size) | |
1547 | { | |
1548 | struct be_mcc_wrb *wrb; | |
1549 | struct be_cmd_req_get_fat *req; | |
1550 | int status; | |
1551 | ||
1552 | spin_lock_bh(&adapter->mcc_lock); | |
1553 | ||
1554 | wrb = wrb_from_mccq(adapter); | |
1555 | if (!wrb) { | |
1556 | status = -EBUSY; | |
1557 | goto err; | |
1558 | } | |
1559 | req = embedded_payload(wrb); | |
1560 | ||
106df1e3 SK |
1561 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1562 | OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL); | |
311fddc7 SK |
1563 | req->fat_operation = cpu_to_le32(QUERY_FAT); |
1564 | status = be_mcc_notify_wait(adapter); | |
1565 | if (!status) { | |
1566 | struct be_cmd_resp_get_fat *resp = embedded_payload(wrb); | |
1567 | if (log_size && resp->log_size) | |
fe2a70ee SK |
1568 | *log_size = le32_to_cpu(resp->log_size) - |
1569 | sizeof(u32); | |
311fddc7 SK |
1570 | } |
1571 | err: | |
1572 | spin_unlock_bh(&adapter->mcc_lock); | |
1573 | return status; | |
1574 | } | |
1575 | ||
1576 | void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf) | |
1577 | { | |
1578 | struct be_dma_mem get_fat_cmd; | |
1579 | struct be_mcc_wrb *wrb; | |
1580 | struct be_cmd_req_get_fat *req; | |
fe2a70ee SK |
1581 | u32 offset = 0, total_size, buf_size, |
1582 | log_offset = sizeof(u32), payload_len; | |
311fddc7 SK |
1583 | int status; |
1584 | ||
1585 | if (buf_len == 0) | |
1586 | return; | |
1587 | ||
1588 | total_size = buf_len; | |
1589 | ||
fe2a70ee SK |
1590 | get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024; |
1591 | get_fat_cmd.va = pci_alloc_consistent(adapter->pdev, | |
1592 | get_fat_cmd.size, | |
1593 | &get_fat_cmd.dma); | |
1594 | if (!get_fat_cmd.va) { | |
1595 | status = -ENOMEM; | |
1596 | dev_err(&adapter->pdev->dev, | |
1597 | "Memory allocation failure while retrieving FAT data\n"); | |
1598 | return; | |
1599 | } | |
1600 | ||
311fddc7 SK |
1601 | spin_lock_bh(&adapter->mcc_lock); |
1602 | ||
311fddc7 SK |
1603 | while (total_size) { |
1604 | buf_size = min(total_size, (u32)60*1024); | |
1605 | total_size -= buf_size; | |
1606 | ||
fe2a70ee SK |
1607 | wrb = wrb_from_mccq(adapter); |
1608 | if (!wrb) { | |
1609 | status = -EBUSY; | |
311fddc7 SK |
1610 | goto err; |
1611 | } | |
1612 | req = get_fat_cmd.va; | |
311fddc7 | 1613 | |
fe2a70ee | 1614 | payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; |
106df1e3 SK |
1615 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1616 | OPCODE_COMMON_MANAGE_FAT, payload_len, wrb, | |
1617 | &get_fat_cmd); | |
311fddc7 SK |
1618 | |
1619 | req->fat_operation = cpu_to_le32(RETRIEVE_FAT); | |
1620 | req->read_log_offset = cpu_to_le32(log_offset); | |
1621 | req->read_log_length = cpu_to_le32(buf_size); | |
1622 | req->data_buffer_size = cpu_to_le32(buf_size); | |
1623 | ||
1624 | status = be_mcc_notify_wait(adapter); | |
1625 | if (!status) { | |
1626 | struct be_cmd_resp_get_fat *resp = get_fat_cmd.va; | |
1627 | memcpy(buf + offset, | |
1628 | resp->data_buffer, | |
92aa9214 | 1629 | le32_to_cpu(resp->read_log_length)); |
fe2a70ee | 1630 | } else { |
311fddc7 | 1631 | dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n"); |
fe2a70ee SK |
1632 | goto err; |
1633 | } | |
311fddc7 SK |
1634 | offset += buf_size; |
1635 | log_offset += buf_size; | |
1636 | } | |
1637 | err: | |
fe2a70ee SK |
1638 | pci_free_consistent(adapter->pdev, get_fat_cmd.size, |
1639 | get_fat_cmd.va, | |
1640 | get_fat_cmd.dma); | |
311fddc7 SK |
1641 | spin_unlock_bh(&adapter->mcc_lock); |
1642 | } | |
1643 | ||
04b71175 SP |
1644 | /* Uses synchronous mcc */ |
1645 | int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, | |
1646 | char *fw_on_flash) | |
6b7c5b94 | 1647 | { |
b31c50a7 SP |
1648 | struct be_mcc_wrb *wrb; |
1649 | struct be_cmd_req_get_fw_version *req; | |
6b7c5b94 SP |
1650 | int status; |
1651 | ||
04b71175 | 1652 | spin_lock_bh(&adapter->mcc_lock); |
b31c50a7 | 1653 | |
04b71175 SP |
1654 | wrb = wrb_from_mccq(adapter); |
1655 | if (!wrb) { | |
1656 | status = -EBUSY; | |
1657 | goto err; | |
1658 | } | |
6b7c5b94 | 1659 | |
04b71175 | 1660 | req = embedded_payload(wrb); |
6b7c5b94 | 1661 | |
106df1e3 SK |
1662 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1663 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL); | |
04b71175 | 1664 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1665 | if (!status) { |
1666 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | |
04b71175 SP |
1667 | strcpy(fw_ver, resp->firmware_version_string); |
1668 | if (fw_on_flash) | |
1669 | strcpy(fw_on_flash, resp->fw_on_flash_version_string); | |
6b7c5b94 | 1670 | } |
04b71175 SP |
1671 | err: |
1672 | spin_unlock_bh(&adapter->mcc_lock); | |
6b7c5b94 SP |
1673 | return status; |
1674 | } | |
1675 | ||
b31c50a7 SP |
1676 | /* set the EQ delay interval of an EQ to specified value |
1677 | * Uses async mcc | |
1678 | */ | |
8788fdc2 | 1679 | int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd) |
6b7c5b94 | 1680 | { |
b31c50a7 SP |
1681 | struct be_mcc_wrb *wrb; |
1682 | struct be_cmd_req_modify_eq_delay *req; | |
713d0394 | 1683 | int status = 0; |
6b7c5b94 | 1684 | |
b31c50a7 SP |
1685 | spin_lock_bh(&adapter->mcc_lock); |
1686 | ||
1687 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1688 | if (!wrb) { |
1689 | status = -EBUSY; | |
1690 | goto err; | |
1691 | } | |
b31c50a7 | 1692 | req = embedded_payload(wrb); |
6b7c5b94 | 1693 | |
106df1e3 SK |
1694 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1695 | OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL); | |
6b7c5b94 SP |
1696 | |
1697 | req->num_eq = cpu_to_le32(1); | |
1698 | req->delay[0].eq_id = cpu_to_le32(eq_id); | |
1699 | req->delay[0].phase = 0; | |
1700 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | |
1701 | ||
b31c50a7 | 1702 | be_mcc_notify(adapter); |
6b7c5b94 | 1703 | |
713d0394 | 1704 | err: |
b31c50a7 | 1705 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 1706 | return status; |
6b7c5b94 SP |
1707 | } |
1708 | ||
b31c50a7 | 1709 | /* Uses sycnhronous mcc */ |
8788fdc2 | 1710 | int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, |
6b7c5b94 SP |
1711 | u32 num, bool untagged, bool promiscuous) |
1712 | { | |
b31c50a7 SP |
1713 | struct be_mcc_wrb *wrb; |
1714 | struct be_cmd_req_vlan_config *req; | |
6b7c5b94 SP |
1715 | int status; |
1716 | ||
b31c50a7 SP |
1717 | spin_lock_bh(&adapter->mcc_lock); |
1718 | ||
1719 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1720 | if (!wrb) { |
1721 | status = -EBUSY; | |
1722 | goto err; | |
1723 | } | |
b31c50a7 | 1724 | req = embedded_payload(wrb); |
6b7c5b94 | 1725 | |
106df1e3 SK |
1726 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1727 | OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL); | |
6b7c5b94 SP |
1728 | |
1729 | req->interface_id = if_id; | |
1730 | req->promiscuous = promiscuous; | |
1731 | req->untagged = untagged; | |
1732 | req->num_vlan = num; | |
1733 | if (!promiscuous) { | |
1734 | memcpy(req->normal_vlan, vtag_array, | |
1735 | req->num_vlan * sizeof(vtag_array[0])); | |
1736 | } | |
1737 | ||
b31c50a7 | 1738 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1739 | |
713d0394 | 1740 | err: |
b31c50a7 | 1741 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1742 | return status; |
1743 | } | |
1744 | ||
5b8821b7 | 1745 | int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value) |
6b7c5b94 | 1746 | { |
6ac7b687 | 1747 | struct be_mcc_wrb *wrb; |
5b8821b7 SP |
1748 | struct be_dma_mem *mem = &adapter->rx_filter; |
1749 | struct be_cmd_req_rx_filter *req = mem->va; | |
e7b909a6 | 1750 | int status; |
6b7c5b94 | 1751 | |
8788fdc2 | 1752 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 1753 | |
b31c50a7 | 1754 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1755 | if (!wrb) { |
1756 | status = -EBUSY; | |
1757 | goto err; | |
1758 | } | |
5b8821b7 | 1759 | memset(req, 0, sizeof(*req)); |
106df1e3 SK |
1760 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1761 | OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req), | |
1762 | wrb, mem); | |
6b7c5b94 | 1763 | |
5b8821b7 SP |
1764 | req->if_id = cpu_to_le32(adapter->if_handle); |
1765 | if (flags & IFF_PROMISC) { | |
1766 | req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | | |
c5dae588 AK |
1767 | BE_IF_FLAGS_VLAN_PROMISCUOUS | |
1768 | BE_IF_FLAGS_MCAST_PROMISCUOUS); | |
5b8821b7 SP |
1769 | if (value == ON) |
1770 | req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | | |
c5dae588 AK |
1771 | BE_IF_FLAGS_VLAN_PROMISCUOUS | |
1772 | BE_IF_FLAGS_MCAST_PROMISCUOUS); | |
5b8821b7 SP |
1773 | } else if (flags & IFF_ALLMULTI) { |
1774 | req->if_flags_mask = req->if_flags = | |
8e7d3f68 | 1775 | cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS); |
5b8821b7 | 1776 | } else { |
22bedad3 | 1777 | struct netdev_hw_addr *ha; |
5b8821b7 | 1778 | int i = 0; |
24307eef | 1779 | |
8e7d3f68 SP |
1780 | req->if_flags_mask = req->if_flags = |
1781 | cpu_to_le32(BE_IF_FLAGS_MULTICAST); | |
1610c79f PR |
1782 | |
1783 | /* Reset mcast promisc mode if already set by setting mask | |
1784 | * and not setting flags field | |
1785 | */ | |
abb93951 PR |
1786 | req->if_flags_mask |= |
1787 | cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS & | |
1788 | adapter->if_cap_flags); | |
1610c79f | 1789 | |
016f97b1 | 1790 | req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev)); |
5b8821b7 SP |
1791 | netdev_for_each_mc_addr(ha, adapter->netdev) |
1792 | memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN); | |
6b7c5b94 SP |
1793 | } |
1794 | ||
0d1d5875 | 1795 | status = be_mcc_notify_wait(adapter); |
713d0394 | 1796 | err: |
8788fdc2 | 1797 | spin_unlock_bh(&adapter->mcc_lock); |
e7b909a6 | 1798 | return status; |
6b7c5b94 SP |
1799 | } |
1800 | ||
b31c50a7 | 1801 | /* Uses synchrounous mcc */ |
8788fdc2 | 1802 | int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) |
6b7c5b94 | 1803 | { |
b31c50a7 SP |
1804 | struct be_mcc_wrb *wrb; |
1805 | struct be_cmd_req_set_flow_control *req; | |
6b7c5b94 SP |
1806 | int status; |
1807 | ||
f25b119c PR |
1808 | if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL, |
1809 | CMD_SUBSYSTEM_COMMON)) | |
1810 | return -EPERM; | |
1811 | ||
b31c50a7 | 1812 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1813 | |
b31c50a7 | 1814 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1815 | if (!wrb) { |
1816 | status = -EBUSY; | |
1817 | goto err; | |
1818 | } | |
b31c50a7 | 1819 | req = embedded_payload(wrb); |
6b7c5b94 | 1820 | |
106df1e3 SK |
1821 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1822 | OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL); | |
6b7c5b94 SP |
1823 | |
1824 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | |
1825 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | |
1826 | ||
b31c50a7 | 1827 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1828 | |
713d0394 | 1829 | err: |
b31c50a7 | 1830 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1831 | return status; |
1832 | } | |
1833 | ||
b31c50a7 | 1834 | /* Uses sycn mcc */ |
8788fdc2 | 1835 | int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) |
6b7c5b94 | 1836 | { |
b31c50a7 SP |
1837 | struct be_mcc_wrb *wrb; |
1838 | struct be_cmd_req_get_flow_control *req; | |
6b7c5b94 SP |
1839 | int status; |
1840 | ||
f25b119c PR |
1841 | if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL, |
1842 | CMD_SUBSYSTEM_COMMON)) | |
1843 | return -EPERM; | |
1844 | ||
b31c50a7 | 1845 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1846 | |
b31c50a7 | 1847 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1848 | if (!wrb) { |
1849 | status = -EBUSY; | |
1850 | goto err; | |
1851 | } | |
b31c50a7 | 1852 | req = embedded_payload(wrb); |
6b7c5b94 | 1853 | |
106df1e3 SK |
1854 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1855 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL); | |
6b7c5b94 | 1856 | |
b31c50a7 | 1857 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1858 | if (!status) { |
1859 | struct be_cmd_resp_get_flow_control *resp = | |
1860 | embedded_payload(wrb); | |
1861 | *tx_fc = le16_to_cpu(resp->tx_flow_control); | |
1862 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | |
1863 | } | |
1864 | ||
713d0394 | 1865 | err: |
b31c50a7 | 1866 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1867 | return status; |
1868 | } | |
1869 | ||
b31c50a7 | 1870 | /* Uses mbox */ |
3abcdeda | 1871 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, |
0ad3157e | 1872 | u32 *mode, u32 *caps, u16 *asic_rev) |
6b7c5b94 | 1873 | { |
b31c50a7 SP |
1874 | struct be_mcc_wrb *wrb; |
1875 | struct be_cmd_req_query_fw_cfg *req; | |
6b7c5b94 SP |
1876 | int status; |
1877 | ||
2984961c IV |
1878 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1879 | return -1; | |
6b7c5b94 | 1880 | |
b31c50a7 SP |
1881 | wrb = wrb_from_mbox(adapter); |
1882 | req = embedded_payload(wrb); | |
6b7c5b94 | 1883 | |
106df1e3 SK |
1884 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1885 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL); | |
6b7c5b94 | 1886 | |
b31c50a7 | 1887 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1888 | if (!status) { |
1889 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | |
1890 | *port_num = le32_to_cpu(resp->phys_port); | |
3486be29 | 1891 | *mode = le32_to_cpu(resp->function_mode); |
3abcdeda | 1892 | *caps = le32_to_cpu(resp->function_caps); |
0ad3157e | 1893 | *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF; |
6b7c5b94 SP |
1894 | } |
1895 | ||
2984961c | 1896 | mutex_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1897 | return status; |
1898 | } | |
14074eab | 1899 | |
b31c50a7 | 1900 | /* Uses mbox */ |
14074eab | 1901 | int be_cmd_reset_function(struct be_adapter *adapter) |
1902 | { | |
b31c50a7 SP |
1903 | struct be_mcc_wrb *wrb; |
1904 | struct be_cmd_req_hdr *req; | |
14074eab | 1905 | int status; |
1906 | ||
bf99e50d PR |
1907 | if (lancer_chip(adapter)) { |
1908 | status = lancer_wait_ready(adapter); | |
1909 | if (!status) { | |
1910 | iowrite32(SLI_PORT_CONTROL_IP_MASK, | |
1911 | adapter->db + SLIPORT_CONTROL_OFFSET); | |
1912 | status = lancer_test_and_set_rdy_state(adapter); | |
1913 | } | |
1914 | if (status) { | |
1915 | dev_err(&adapter->pdev->dev, | |
1916 | "Adapter in non recoverable error\n"); | |
1917 | } | |
1918 | return status; | |
1919 | } | |
1920 | ||
2984961c IV |
1921 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1922 | return -1; | |
14074eab | 1923 | |
b31c50a7 SP |
1924 | wrb = wrb_from_mbox(adapter); |
1925 | req = embedded_payload(wrb); | |
14074eab | 1926 | |
106df1e3 SK |
1927 | be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, |
1928 | OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL); | |
14074eab | 1929 | |
b31c50a7 | 1930 | status = be_mbox_notify_wait(adapter); |
14074eab | 1931 | |
2984961c | 1932 | mutex_unlock(&adapter->mbox_lock); |
14074eab | 1933 | return status; |
1934 | } | |
84517482 | 1935 | |
594ad54a SR |
1936 | int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, |
1937 | u32 rss_hash_opts, u16 table_size) | |
3abcdeda SP |
1938 | { |
1939 | struct be_mcc_wrb *wrb; | |
1940 | struct be_cmd_req_rss_config *req; | |
65f8584e PR |
1941 | u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e, |
1942 | 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2, | |
1943 | 0x3ea83c02, 0x4a110304}; | |
3abcdeda SP |
1944 | int status; |
1945 | ||
2984961c IV |
1946 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
1947 | return -1; | |
3abcdeda SP |
1948 | |
1949 | wrb = wrb_from_mbox(adapter); | |
1950 | req = embedded_payload(wrb); | |
1951 | ||
106df1e3 SK |
1952 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, |
1953 | OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); | |
3abcdeda SP |
1954 | |
1955 | req->if_id = cpu_to_le32(adapter->if_handle); | |
594ad54a SR |
1956 | req->enable_rss = cpu_to_le16(rss_hash_opts); |
1957 | req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); | |
d3bd3a5e | 1958 | |
594ad54a | 1959 | if (lancer_chip(adapter) || skyhawk_chip(adapter)) |
d3bd3a5e | 1960 | req->hdr.version = 1; |
d3bd3a5e | 1961 | |
3abcdeda SP |
1962 | memcpy(req->cpu_table, rsstable, table_size); |
1963 | memcpy(req->hash, myhash, sizeof(myhash)); | |
1964 | be_dws_cpu_to_le(req->hash, sizeof(req->hash)); | |
1965 | ||
1966 | status = be_mbox_notify_wait(adapter); | |
1967 | ||
2984961c | 1968 | mutex_unlock(&adapter->mbox_lock); |
3abcdeda SP |
1969 | return status; |
1970 | } | |
1971 | ||
fad9ab2c SB |
1972 | /* Uses sync mcc */ |
1973 | int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, | |
1974 | u8 bcn, u8 sts, u8 state) | |
1975 | { | |
1976 | struct be_mcc_wrb *wrb; | |
1977 | struct be_cmd_req_enable_disable_beacon *req; | |
1978 | int status; | |
1979 | ||
1980 | spin_lock_bh(&adapter->mcc_lock); | |
1981 | ||
1982 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1983 | if (!wrb) { |
1984 | status = -EBUSY; | |
1985 | goto err; | |
1986 | } | |
fad9ab2c SB |
1987 | req = embedded_payload(wrb); |
1988 | ||
106df1e3 SK |
1989 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
1990 | OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL); | |
fad9ab2c SB |
1991 | |
1992 | req->port_num = port_num; | |
1993 | req->beacon_state = state; | |
1994 | req->beacon_duration = bcn; | |
1995 | req->status_duration = sts; | |
1996 | ||
1997 | status = be_mcc_notify_wait(adapter); | |
1998 | ||
713d0394 | 1999 | err: |
fad9ab2c SB |
2000 | spin_unlock_bh(&adapter->mcc_lock); |
2001 | return status; | |
2002 | } | |
2003 | ||
2004 | /* Uses sync mcc */ | |
2005 | int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) | |
2006 | { | |
2007 | struct be_mcc_wrb *wrb; | |
2008 | struct be_cmd_req_get_beacon_state *req; | |
2009 | int status; | |
2010 | ||
2011 | spin_lock_bh(&adapter->mcc_lock); | |
2012 | ||
2013 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
2014 | if (!wrb) { |
2015 | status = -EBUSY; | |
2016 | goto err; | |
2017 | } | |
fad9ab2c SB |
2018 | req = embedded_payload(wrb); |
2019 | ||
106df1e3 SK |
2020 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
2021 | OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL); | |
fad9ab2c SB |
2022 | |
2023 | req->port_num = port_num; | |
2024 | ||
2025 | status = be_mcc_notify_wait(adapter); | |
2026 | if (!status) { | |
2027 | struct be_cmd_resp_get_beacon_state *resp = | |
2028 | embedded_payload(wrb); | |
2029 | *state = resp->beacon_state; | |
2030 | } | |
2031 | ||
713d0394 | 2032 | err: |
fad9ab2c SB |
2033 | spin_unlock_bh(&adapter->mcc_lock); |
2034 | return status; | |
2035 | } | |
2036 | ||
485bf569 | 2037 | int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, |
f67ef7ba PR |
2038 | u32 data_size, u32 data_offset, |
2039 | const char *obj_name, u32 *data_written, | |
2040 | u8 *change_status, u8 *addn_status) | |
485bf569 SN |
2041 | { |
2042 | struct be_mcc_wrb *wrb; | |
2043 | struct lancer_cmd_req_write_object *req; | |
2044 | struct lancer_cmd_resp_write_object *resp; | |
2045 | void *ctxt = NULL; | |
2046 | int status; | |
2047 | ||
2048 | spin_lock_bh(&adapter->mcc_lock); | |
2049 | adapter->flash_status = 0; | |
2050 | ||
2051 | wrb = wrb_from_mccq(adapter); | |
2052 | if (!wrb) { | |
2053 | status = -EBUSY; | |
2054 | goto err_unlock; | |
2055 | } | |
2056 | ||
2057 | req = embedded_payload(wrb); | |
2058 | ||
106df1e3 | 2059 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
485bf569 | 2060 | OPCODE_COMMON_WRITE_OBJECT, |
106df1e3 SK |
2061 | sizeof(struct lancer_cmd_req_write_object), wrb, |
2062 | NULL); | |
485bf569 SN |
2063 | |
2064 | ctxt = &req->context; | |
2065 | AMAP_SET_BITS(struct amap_lancer_write_obj_context, | |
2066 | write_length, ctxt, data_size); | |
2067 | ||
2068 | if (data_size == 0) | |
2069 | AMAP_SET_BITS(struct amap_lancer_write_obj_context, | |
2070 | eof, ctxt, 1); | |
2071 | else | |
2072 | AMAP_SET_BITS(struct amap_lancer_write_obj_context, | |
2073 | eof, ctxt, 0); | |
2074 | ||
2075 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
2076 | req->write_offset = cpu_to_le32(data_offset); | |
2077 | strcpy(req->object_name, obj_name); | |
2078 | req->descriptor_count = cpu_to_le32(1); | |
2079 | req->buf_len = cpu_to_le32(data_size); | |
2080 | req->addr_low = cpu_to_le32((cmd->dma + | |
2081 | sizeof(struct lancer_cmd_req_write_object)) | |
2082 | & 0xFFFFFFFF); | |
2083 | req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + | |
2084 | sizeof(struct lancer_cmd_req_write_object))); | |
2085 | ||
2086 | be_mcc_notify(adapter); | |
2087 | spin_unlock_bh(&adapter->mcc_lock); | |
2088 | ||
2089 | if (!wait_for_completion_timeout(&adapter->flash_compl, | |
701962d0 | 2090 | msecs_to_jiffies(60000))) |
485bf569 SN |
2091 | status = -1; |
2092 | else | |
2093 | status = adapter->flash_status; | |
2094 | ||
2095 | resp = embedded_payload(wrb); | |
f67ef7ba | 2096 | if (!status) { |
485bf569 | 2097 | *data_written = le32_to_cpu(resp->actual_write_len); |
f67ef7ba PR |
2098 | *change_status = resp->change_status; |
2099 | } else { | |
485bf569 | 2100 | *addn_status = resp->additional_status; |
f67ef7ba | 2101 | } |
485bf569 SN |
2102 | |
2103 | return status; | |
2104 | ||
2105 | err_unlock: | |
2106 | spin_unlock_bh(&adapter->mcc_lock); | |
2107 | return status; | |
2108 | } | |
2109 | ||
de49bd5a PR |
2110 | int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, |
2111 | u32 data_size, u32 data_offset, const char *obj_name, | |
2112 | u32 *data_read, u32 *eof, u8 *addn_status) | |
2113 | { | |
2114 | struct be_mcc_wrb *wrb; | |
2115 | struct lancer_cmd_req_read_object *req; | |
2116 | struct lancer_cmd_resp_read_object *resp; | |
2117 | int status; | |
2118 | ||
2119 | spin_lock_bh(&adapter->mcc_lock); | |
2120 | ||
2121 | wrb = wrb_from_mccq(adapter); | |
2122 | if (!wrb) { | |
2123 | status = -EBUSY; | |
2124 | goto err_unlock; | |
2125 | } | |
2126 | ||
2127 | req = embedded_payload(wrb); | |
2128 | ||
2129 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2130 | OPCODE_COMMON_READ_OBJECT, | |
2131 | sizeof(struct lancer_cmd_req_read_object), wrb, | |
2132 | NULL); | |
2133 | ||
2134 | req->desired_read_len = cpu_to_le32(data_size); | |
2135 | req->read_offset = cpu_to_le32(data_offset); | |
2136 | strcpy(req->object_name, obj_name); | |
2137 | req->descriptor_count = cpu_to_le32(1); | |
2138 | req->buf_len = cpu_to_le32(data_size); | |
2139 | req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF)); | |
2140 | req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma)); | |
2141 | ||
2142 | status = be_mcc_notify_wait(adapter); | |
2143 | ||
2144 | resp = embedded_payload(wrb); | |
2145 | if (!status) { | |
2146 | *data_read = le32_to_cpu(resp->actual_read_len); | |
2147 | *eof = le32_to_cpu(resp->eof); | |
2148 | } else { | |
2149 | *addn_status = resp->additional_status; | |
2150 | } | |
2151 | ||
2152 | err_unlock: | |
2153 | spin_unlock_bh(&adapter->mcc_lock); | |
2154 | return status; | |
2155 | } | |
2156 | ||
84517482 AK |
2157 | int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, |
2158 | u32 flash_type, u32 flash_opcode, u32 buf_size) | |
2159 | { | |
b31c50a7 | 2160 | struct be_mcc_wrb *wrb; |
3f0d4560 | 2161 | struct be_cmd_write_flashrom *req; |
84517482 AK |
2162 | int status; |
2163 | ||
b31c50a7 | 2164 | spin_lock_bh(&adapter->mcc_lock); |
dd131e76 | 2165 | adapter->flash_status = 0; |
b31c50a7 SP |
2166 | |
2167 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
2168 | if (!wrb) { |
2169 | status = -EBUSY; | |
2892d9c2 | 2170 | goto err_unlock; |
713d0394 SP |
2171 | } |
2172 | req = cmd->va; | |
84517482 | 2173 | |
106df1e3 SK |
2174 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
2175 | OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd); | |
84517482 AK |
2176 | |
2177 | req->params.op_type = cpu_to_le32(flash_type); | |
2178 | req->params.op_code = cpu_to_le32(flash_opcode); | |
2179 | req->params.data_buf_size = cpu_to_le32(buf_size); | |
2180 | ||
dd131e76 SB |
2181 | be_mcc_notify(adapter); |
2182 | spin_unlock_bh(&adapter->mcc_lock); | |
2183 | ||
2184 | if (!wait_for_completion_timeout(&adapter->flash_compl, | |
e2edb7d5 | 2185 | msecs_to_jiffies(40000))) |
dd131e76 SB |
2186 | status = -1; |
2187 | else | |
2188 | status = adapter->flash_status; | |
84517482 | 2189 | |
2892d9c2 DC |
2190 | return status; |
2191 | ||
2192 | err_unlock: | |
2193 | spin_unlock_bh(&adapter->mcc_lock); | |
84517482 AK |
2194 | return status; |
2195 | } | |
fa9a6fed | 2196 | |
3f0d4560 AK |
2197 | int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, |
2198 | int offset) | |
fa9a6fed SB |
2199 | { |
2200 | struct be_mcc_wrb *wrb; | |
be716446 | 2201 | struct be_cmd_read_flash_crc *req; |
fa9a6fed SB |
2202 | int status; |
2203 | ||
2204 | spin_lock_bh(&adapter->mcc_lock); | |
2205 | ||
2206 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
2207 | if (!wrb) { |
2208 | status = -EBUSY; | |
2209 | goto err; | |
2210 | } | |
fa9a6fed SB |
2211 | req = embedded_payload(wrb); |
2212 | ||
106df1e3 | 2213 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
be716446 PR |
2214 | OPCODE_COMMON_READ_FLASHROM, sizeof(*req), |
2215 | wrb, NULL); | |
fa9a6fed | 2216 | |
c165541e | 2217 | req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT); |
fa9a6fed | 2218 | req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); |
8b93b710 AK |
2219 | req->params.offset = cpu_to_le32(offset); |
2220 | req->params.data_buf_size = cpu_to_le32(0x4); | |
fa9a6fed SB |
2221 | |
2222 | status = be_mcc_notify_wait(adapter); | |
2223 | if (!status) | |
be716446 | 2224 | memcpy(flashed_crc, req->crc, 4); |
fa9a6fed | 2225 | |
713d0394 | 2226 | err: |
fa9a6fed SB |
2227 | spin_unlock_bh(&adapter->mcc_lock); |
2228 | return status; | |
2229 | } | |
71d8d1b5 | 2230 | |
c196b02c | 2231 | int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, |
71d8d1b5 AK |
2232 | struct be_dma_mem *nonemb_cmd) |
2233 | { | |
2234 | struct be_mcc_wrb *wrb; | |
2235 | struct be_cmd_req_acpi_wol_magic_config *req; | |
71d8d1b5 AK |
2236 | int status; |
2237 | ||
2238 | spin_lock_bh(&adapter->mcc_lock); | |
2239 | ||
2240 | wrb = wrb_from_mccq(adapter); | |
2241 | if (!wrb) { | |
2242 | status = -EBUSY; | |
2243 | goto err; | |
2244 | } | |
2245 | req = nonemb_cmd->va; | |
71d8d1b5 | 2246 | |
106df1e3 SK |
2247 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, |
2248 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb, | |
2249 | nonemb_cmd); | |
71d8d1b5 AK |
2250 | memcpy(req->magic_mac, mac, ETH_ALEN); |
2251 | ||
71d8d1b5 AK |
2252 | status = be_mcc_notify_wait(adapter); |
2253 | ||
2254 | err: | |
2255 | spin_unlock_bh(&adapter->mcc_lock); | |
2256 | return status; | |
2257 | } | |
ff33a6e2 | 2258 | |
fced9999 SB |
2259 | int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, |
2260 | u8 loopback_type, u8 enable) | |
2261 | { | |
2262 | struct be_mcc_wrb *wrb; | |
2263 | struct be_cmd_req_set_lmode *req; | |
2264 | int status; | |
2265 | ||
2266 | spin_lock_bh(&adapter->mcc_lock); | |
2267 | ||
2268 | wrb = wrb_from_mccq(adapter); | |
2269 | if (!wrb) { | |
2270 | status = -EBUSY; | |
2271 | goto err; | |
2272 | } | |
2273 | ||
2274 | req = embedded_payload(wrb); | |
2275 | ||
106df1e3 SK |
2276 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, |
2277 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb, | |
2278 | NULL); | |
fced9999 SB |
2279 | |
2280 | req->src_port = port_num; | |
2281 | req->dest_port = port_num; | |
2282 | req->loopback_type = loopback_type; | |
2283 | req->loopback_state = enable; | |
2284 | ||
2285 | status = be_mcc_notify_wait(adapter); | |
2286 | err: | |
2287 | spin_unlock_bh(&adapter->mcc_lock); | |
2288 | return status; | |
2289 | } | |
2290 | ||
ff33a6e2 S |
2291 | int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, |
2292 | u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) | |
2293 | { | |
2294 | struct be_mcc_wrb *wrb; | |
2295 | struct be_cmd_req_loopback_test *req; | |
2296 | int status; | |
2297 | ||
2298 | spin_lock_bh(&adapter->mcc_lock); | |
2299 | ||
2300 | wrb = wrb_from_mccq(adapter); | |
2301 | if (!wrb) { | |
2302 | status = -EBUSY; | |
2303 | goto err; | |
2304 | } | |
2305 | ||
2306 | req = embedded_payload(wrb); | |
2307 | ||
106df1e3 SK |
2308 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, |
2309 | OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL); | |
3ffd0515 | 2310 | req->hdr.timeout = cpu_to_le32(4); |
ff33a6e2 S |
2311 | |
2312 | req->pattern = cpu_to_le64(pattern); | |
2313 | req->src_port = cpu_to_le32(port_num); | |
2314 | req->dest_port = cpu_to_le32(port_num); | |
2315 | req->pkt_size = cpu_to_le32(pkt_size); | |
2316 | req->num_pkts = cpu_to_le32(num_pkts); | |
2317 | req->loopback_type = cpu_to_le32(loopback_type); | |
2318 | ||
2319 | status = be_mcc_notify_wait(adapter); | |
2320 | if (!status) { | |
2321 | struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb); | |
2322 | status = le32_to_cpu(resp->status); | |
2323 | } | |
2324 | ||
2325 | err: | |
2326 | spin_unlock_bh(&adapter->mcc_lock); | |
2327 | return status; | |
2328 | } | |
2329 | ||
2330 | int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, | |
2331 | u32 byte_cnt, struct be_dma_mem *cmd) | |
2332 | { | |
2333 | struct be_mcc_wrb *wrb; | |
2334 | struct be_cmd_req_ddrdma_test *req; | |
ff33a6e2 S |
2335 | int status; |
2336 | int i, j = 0; | |
2337 | ||
2338 | spin_lock_bh(&adapter->mcc_lock); | |
2339 | ||
2340 | wrb = wrb_from_mccq(adapter); | |
2341 | if (!wrb) { | |
2342 | status = -EBUSY; | |
2343 | goto err; | |
2344 | } | |
2345 | req = cmd->va; | |
106df1e3 SK |
2346 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, |
2347 | OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd); | |
ff33a6e2 S |
2348 | |
2349 | req->pattern = cpu_to_le64(pattern); | |
2350 | req->byte_count = cpu_to_le32(byte_cnt); | |
2351 | for (i = 0; i < byte_cnt; i++) { | |
2352 | req->snd_buff[i] = (u8)(pattern >> (j*8)); | |
2353 | j++; | |
2354 | if (j > 7) | |
2355 | j = 0; | |
2356 | } | |
2357 | ||
2358 | status = be_mcc_notify_wait(adapter); | |
2359 | ||
2360 | if (!status) { | |
2361 | struct be_cmd_resp_ddrdma_test *resp; | |
2362 | resp = cmd->va; | |
2363 | if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || | |
2364 | resp->snd_err) { | |
2365 | status = -1; | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | err: | |
2370 | spin_unlock_bh(&adapter->mcc_lock); | |
2371 | return status; | |
2372 | } | |
368c0ca2 | 2373 | |
c196b02c | 2374 | int be_cmd_get_seeprom_data(struct be_adapter *adapter, |
368c0ca2 SB |
2375 | struct be_dma_mem *nonemb_cmd) |
2376 | { | |
2377 | struct be_mcc_wrb *wrb; | |
2378 | struct be_cmd_req_seeprom_read *req; | |
368c0ca2 SB |
2379 | int status; |
2380 | ||
2381 | spin_lock_bh(&adapter->mcc_lock); | |
2382 | ||
2383 | wrb = wrb_from_mccq(adapter); | |
e45ff01d AK |
2384 | if (!wrb) { |
2385 | status = -EBUSY; | |
2386 | goto err; | |
2387 | } | |
368c0ca2 | 2388 | req = nonemb_cmd->va; |
368c0ca2 | 2389 | |
106df1e3 SK |
2390 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
2391 | OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, | |
2392 | nonemb_cmd); | |
368c0ca2 SB |
2393 | |
2394 | status = be_mcc_notify_wait(adapter); | |
2395 | ||
e45ff01d | 2396 | err: |
368c0ca2 SB |
2397 | spin_unlock_bh(&adapter->mcc_lock); |
2398 | return status; | |
2399 | } | |
ee3cb629 | 2400 | |
42f11cf2 | 2401 | int be_cmd_get_phy_info(struct be_adapter *adapter) |
ee3cb629 AK |
2402 | { |
2403 | struct be_mcc_wrb *wrb; | |
2404 | struct be_cmd_req_get_phy_info *req; | |
306f1348 | 2405 | struct be_dma_mem cmd; |
ee3cb629 AK |
2406 | int status; |
2407 | ||
f25b119c PR |
2408 | if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS, |
2409 | CMD_SUBSYSTEM_COMMON)) | |
2410 | return -EPERM; | |
2411 | ||
ee3cb629 AK |
2412 | spin_lock_bh(&adapter->mcc_lock); |
2413 | ||
2414 | wrb = wrb_from_mccq(adapter); | |
2415 | if (!wrb) { | |
2416 | status = -EBUSY; | |
2417 | goto err; | |
2418 | } | |
306f1348 SP |
2419 | cmd.size = sizeof(struct be_cmd_req_get_phy_info); |
2420 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, | |
2421 | &cmd.dma); | |
2422 | if (!cmd.va) { | |
2423 | dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); | |
2424 | status = -ENOMEM; | |
2425 | goto err; | |
2426 | } | |
ee3cb629 | 2427 | |
306f1348 | 2428 | req = cmd.va; |
ee3cb629 | 2429 | |
106df1e3 SK |
2430 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
2431 | OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req), | |
2432 | wrb, &cmd); | |
ee3cb629 AK |
2433 | |
2434 | status = be_mcc_notify_wait(adapter); | |
306f1348 SP |
2435 | if (!status) { |
2436 | struct be_phy_info *resp_phy_info = | |
2437 | cmd.va + sizeof(struct be_cmd_req_hdr); | |
42f11cf2 AK |
2438 | adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type); |
2439 | adapter->phy.interface_type = | |
306f1348 | 2440 | le16_to_cpu(resp_phy_info->interface_type); |
42f11cf2 AK |
2441 | adapter->phy.auto_speeds_supported = |
2442 | le16_to_cpu(resp_phy_info->auto_speeds_supported); | |
2443 | adapter->phy.fixed_speeds_supported = | |
2444 | le16_to_cpu(resp_phy_info->fixed_speeds_supported); | |
2445 | adapter->phy.misc_params = | |
2446 | le32_to_cpu(resp_phy_info->misc_params); | |
306f1348 SP |
2447 | } |
2448 | pci_free_consistent(adapter->pdev, cmd.size, | |
2449 | cmd.va, cmd.dma); | |
ee3cb629 AK |
2450 | err: |
2451 | spin_unlock_bh(&adapter->mcc_lock); | |
2452 | return status; | |
2453 | } | |
e1d18735 AK |
2454 | |
2455 | int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain) | |
2456 | { | |
2457 | struct be_mcc_wrb *wrb; | |
2458 | struct be_cmd_req_set_qos *req; | |
2459 | int status; | |
2460 | ||
2461 | spin_lock_bh(&adapter->mcc_lock); | |
2462 | ||
2463 | wrb = wrb_from_mccq(adapter); | |
2464 | if (!wrb) { | |
2465 | status = -EBUSY; | |
2466 | goto err; | |
2467 | } | |
2468 | ||
2469 | req = embedded_payload(wrb); | |
2470 | ||
106df1e3 SK |
2471 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
2472 | OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL); | |
e1d18735 AK |
2473 | |
2474 | req->hdr.domain = domain; | |
6bff57a7 AK |
2475 | req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); |
2476 | req->max_bps_nic = cpu_to_le32(bps); | |
e1d18735 AK |
2477 | |
2478 | status = be_mcc_notify_wait(adapter); | |
2479 | ||
2480 | err: | |
2481 | spin_unlock_bh(&adapter->mcc_lock); | |
2482 | return status; | |
2483 | } | |
9e1453c5 AK |
2484 | |
2485 | int be_cmd_get_cntl_attributes(struct be_adapter *adapter) | |
2486 | { | |
2487 | struct be_mcc_wrb *wrb; | |
2488 | struct be_cmd_req_cntl_attribs *req; | |
2489 | struct be_cmd_resp_cntl_attribs *resp; | |
9e1453c5 AK |
2490 | int status; |
2491 | int payload_len = max(sizeof(*req), sizeof(*resp)); | |
2492 | struct mgmt_controller_attrib *attribs; | |
2493 | struct be_dma_mem attribs_cmd; | |
2494 | ||
d98ef50f SR |
2495 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
2496 | return -1; | |
2497 | ||
9e1453c5 AK |
2498 | memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); |
2499 | attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); | |
2500 | attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, | |
2501 | &attribs_cmd.dma); | |
2502 | if (!attribs_cmd.va) { | |
2503 | dev_err(&adapter->pdev->dev, | |
2504 | "Memory allocation failure\n"); | |
d98ef50f SR |
2505 | status = -ENOMEM; |
2506 | goto err; | |
9e1453c5 AK |
2507 | } |
2508 | ||
9e1453c5 AK |
2509 | wrb = wrb_from_mbox(adapter); |
2510 | if (!wrb) { | |
2511 | status = -EBUSY; | |
2512 | goto err; | |
2513 | } | |
2514 | req = attribs_cmd.va; | |
9e1453c5 | 2515 | |
106df1e3 SK |
2516 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
2517 | OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb, | |
2518 | &attribs_cmd); | |
9e1453c5 AK |
2519 | |
2520 | status = be_mbox_notify_wait(adapter); | |
2521 | if (!status) { | |
43d620c8 | 2522 | attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr); |
9e1453c5 AK |
2523 | adapter->hba_port_num = attribs->hba_attribs.phy_port; |
2524 | } | |
2525 | ||
2526 | err: | |
2527 | mutex_unlock(&adapter->mbox_lock); | |
d98ef50f SR |
2528 | if (attribs_cmd.va) |
2529 | pci_free_consistent(adapter->pdev, attribs_cmd.size, | |
2530 | attribs_cmd.va, attribs_cmd.dma); | |
9e1453c5 AK |
2531 | return status; |
2532 | } | |
2e588f84 SP |
2533 | |
2534 | /* Uses mbox */ | |
2dc1deb6 | 2535 | int be_cmd_req_native_mode(struct be_adapter *adapter) |
2e588f84 SP |
2536 | { |
2537 | struct be_mcc_wrb *wrb; | |
2538 | struct be_cmd_req_set_func_cap *req; | |
2539 | int status; | |
2540 | ||
2541 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | |
2542 | return -1; | |
2543 | ||
2544 | wrb = wrb_from_mbox(adapter); | |
2545 | if (!wrb) { | |
2546 | status = -EBUSY; | |
2547 | goto err; | |
2548 | } | |
2549 | ||
2550 | req = embedded_payload(wrb); | |
2551 | ||
106df1e3 SK |
2552 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
2553 | OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL); | |
2e588f84 SP |
2554 | |
2555 | req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | | |
2556 | CAPABILITY_BE3_NATIVE_ERX_API); | |
2557 | req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API); | |
2558 | ||
2559 | status = be_mbox_notify_wait(adapter); | |
2560 | if (!status) { | |
2561 | struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb); | |
2562 | adapter->be3_native = le32_to_cpu(resp->cap_flags) & | |
2563 | CAPABILITY_BE3_NATIVE_ERX_API; | |
d379142b SP |
2564 | if (!adapter->be3_native) |
2565 | dev_warn(&adapter->pdev->dev, | |
2566 | "adapter not in advanced mode\n"); | |
2e588f84 SP |
2567 | } |
2568 | err: | |
2569 | mutex_unlock(&adapter->mbox_lock); | |
2570 | return status; | |
2571 | } | |
590c391d | 2572 | |
f25b119c PR |
2573 | /* Get privilege(s) for a function */ |
2574 | int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, | |
2575 | u32 domain) | |
2576 | { | |
2577 | struct be_mcc_wrb *wrb; | |
2578 | struct be_cmd_req_get_fn_privileges *req; | |
2579 | int status; | |
2580 | ||
2581 | spin_lock_bh(&adapter->mcc_lock); | |
2582 | ||
2583 | wrb = wrb_from_mccq(adapter); | |
2584 | if (!wrb) { | |
2585 | status = -EBUSY; | |
2586 | goto err; | |
2587 | } | |
2588 | ||
2589 | req = embedded_payload(wrb); | |
2590 | ||
2591 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2592 | OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req), | |
2593 | wrb, NULL); | |
2594 | ||
2595 | req->hdr.domain = domain; | |
2596 | ||
2597 | status = be_mcc_notify_wait(adapter); | |
2598 | if (!status) { | |
2599 | struct be_cmd_resp_get_fn_privileges *resp = | |
2600 | embedded_payload(wrb); | |
2601 | *privilege = le32_to_cpu(resp->privilege_mask); | |
2602 | } | |
2603 | ||
2604 | err: | |
2605 | spin_unlock_bh(&adapter->mcc_lock); | |
2606 | return status; | |
2607 | } | |
2608 | ||
590c391d | 2609 | /* Uses synchronous MCCQ */ |
1578e777 PR |
2610 | int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, |
2611 | bool *pmac_id_active, u32 *pmac_id, u8 domain) | |
590c391d PR |
2612 | { |
2613 | struct be_mcc_wrb *wrb; | |
2614 | struct be_cmd_req_get_mac_list *req; | |
2615 | int status; | |
2616 | int mac_count; | |
e5e1ee89 PR |
2617 | struct be_dma_mem get_mac_list_cmd; |
2618 | int i; | |
2619 | ||
2620 | memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem)); | |
2621 | get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list); | |
2622 | get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev, | |
2623 | get_mac_list_cmd.size, | |
2624 | &get_mac_list_cmd.dma); | |
2625 | ||
2626 | if (!get_mac_list_cmd.va) { | |
2627 | dev_err(&adapter->pdev->dev, | |
2628 | "Memory allocation failure during GET_MAC_LIST\n"); | |
2629 | return -ENOMEM; | |
2630 | } | |
590c391d PR |
2631 | |
2632 | spin_lock_bh(&adapter->mcc_lock); | |
2633 | ||
2634 | wrb = wrb_from_mccq(adapter); | |
2635 | if (!wrb) { | |
2636 | status = -EBUSY; | |
e5e1ee89 | 2637 | goto out; |
590c391d | 2638 | } |
e5e1ee89 PR |
2639 | |
2640 | req = get_mac_list_cmd.va; | |
590c391d PR |
2641 | |
2642 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
bf591f51 SP |
2643 | OPCODE_COMMON_GET_MAC_LIST, |
2644 | get_mac_list_cmd.size, wrb, &get_mac_list_cmd); | |
590c391d | 2645 | req->hdr.domain = domain; |
e5e1ee89 PR |
2646 | req->mac_type = MAC_ADDRESS_TYPE_NETWORK; |
2647 | req->perm_override = 1; | |
590c391d PR |
2648 | |
2649 | status = be_mcc_notify_wait(adapter); | |
2650 | if (!status) { | |
2651 | struct be_cmd_resp_get_mac_list *resp = | |
e5e1ee89 PR |
2652 | get_mac_list_cmd.va; |
2653 | mac_count = resp->true_mac_count + resp->pseudo_mac_count; | |
2654 | /* Mac list returned could contain one or more active mac_ids | |
1578e777 PR |
2655 | * or one or more true or pseudo permanant mac addresses. |
2656 | * If an active mac_id is present, return first active mac_id | |
2657 | * found. | |
e5e1ee89 | 2658 | */ |
590c391d | 2659 | for (i = 0; i < mac_count; i++) { |
e5e1ee89 PR |
2660 | struct get_list_macaddr *mac_entry; |
2661 | u16 mac_addr_size; | |
2662 | u32 mac_id; | |
2663 | ||
2664 | mac_entry = &resp->macaddr_list[i]; | |
2665 | mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size); | |
2666 | /* mac_id is a 32 bit value and mac_addr size | |
2667 | * is 6 bytes | |
2668 | */ | |
2669 | if (mac_addr_size == sizeof(u32)) { | |
2670 | *pmac_id_active = true; | |
2671 | mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id; | |
2672 | *pmac_id = le32_to_cpu(mac_id); | |
2673 | goto out; | |
590c391d | 2674 | } |
590c391d | 2675 | } |
1578e777 | 2676 | /* If no active mac_id found, return first mac addr */ |
e5e1ee89 PR |
2677 | *pmac_id_active = false; |
2678 | memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr, | |
2679 | ETH_ALEN); | |
590c391d PR |
2680 | } |
2681 | ||
e5e1ee89 | 2682 | out: |
590c391d | 2683 | spin_unlock_bh(&adapter->mcc_lock); |
e5e1ee89 PR |
2684 | pci_free_consistent(adapter->pdev, get_mac_list_cmd.size, |
2685 | get_mac_list_cmd.va, get_mac_list_cmd.dma); | |
590c391d PR |
2686 | return status; |
2687 | } | |
2688 | ||
2689 | /* Uses synchronous MCCQ */ | |
2690 | int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, | |
2691 | u8 mac_count, u32 domain) | |
2692 | { | |
2693 | struct be_mcc_wrb *wrb; | |
2694 | struct be_cmd_req_set_mac_list *req; | |
2695 | int status; | |
2696 | struct be_dma_mem cmd; | |
2697 | ||
2698 | memset(&cmd, 0, sizeof(struct be_dma_mem)); | |
2699 | cmd.size = sizeof(struct be_cmd_req_set_mac_list); | |
2700 | cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, | |
2701 | &cmd.dma, GFP_KERNEL); | |
d0320f75 | 2702 | if (!cmd.va) |
590c391d | 2703 | return -ENOMEM; |
590c391d PR |
2704 | |
2705 | spin_lock_bh(&adapter->mcc_lock); | |
2706 | ||
2707 | wrb = wrb_from_mccq(adapter); | |
2708 | if (!wrb) { | |
2709 | status = -EBUSY; | |
2710 | goto err; | |
2711 | } | |
2712 | ||
2713 | req = cmd.va; | |
2714 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2715 | OPCODE_COMMON_SET_MAC_LIST, sizeof(*req), | |
2716 | wrb, &cmd); | |
2717 | ||
2718 | req->hdr.domain = domain; | |
2719 | req->mac_count = mac_count; | |
2720 | if (mac_count) | |
2721 | memcpy(req->mac, mac_array, ETH_ALEN*mac_count); | |
2722 | ||
2723 | status = be_mcc_notify_wait(adapter); | |
2724 | ||
2725 | err: | |
2726 | dma_free_coherent(&adapter->pdev->dev, cmd.size, | |
2727 | cmd.va, cmd.dma); | |
2728 | spin_unlock_bh(&adapter->mcc_lock); | |
2729 | return status; | |
2730 | } | |
4762f6ce | 2731 | |
f1f3ee1b AK |
2732 | int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, |
2733 | u32 domain, u16 intf_id) | |
2734 | { | |
2735 | struct be_mcc_wrb *wrb; | |
2736 | struct be_cmd_req_set_hsw_config *req; | |
2737 | void *ctxt; | |
2738 | int status; | |
2739 | ||
2740 | spin_lock_bh(&adapter->mcc_lock); | |
2741 | ||
2742 | wrb = wrb_from_mccq(adapter); | |
2743 | if (!wrb) { | |
2744 | status = -EBUSY; | |
2745 | goto err; | |
2746 | } | |
2747 | ||
2748 | req = embedded_payload(wrb); | |
2749 | ctxt = &req->context; | |
2750 | ||
2751 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2752 | OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL); | |
2753 | ||
2754 | req->hdr.domain = domain; | |
2755 | AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id); | |
2756 | if (pvid) { | |
2757 | AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1); | |
2758 | AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid); | |
2759 | } | |
2760 | ||
2761 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
2762 | status = be_mcc_notify_wait(adapter); | |
2763 | ||
2764 | err: | |
2765 | spin_unlock_bh(&adapter->mcc_lock); | |
2766 | return status; | |
2767 | } | |
2768 | ||
2769 | /* Get Hyper switch config */ | |
2770 | int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, | |
2771 | u32 domain, u16 intf_id) | |
2772 | { | |
2773 | struct be_mcc_wrb *wrb; | |
2774 | struct be_cmd_req_get_hsw_config *req; | |
2775 | void *ctxt; | |
2776 | int status; | |
2777 | u16 vid; | |
2778 | ||
2779 | spin_lock_bh(&adapter->mcc_lock); | |
2780 | ||
2781 | wrb = wrb_from_mccq(adapter); | |
2782 | if (!wrb) { | |
2783 | status = -EBUSY; | |
2784 | goto err; | |
2785 | } | |
2786 | ||
2787 | req = embedded_payload(wrb); | |
2788 | ctxt = &req->context; | |
2789 | ||
2790 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2791 | OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL); | |
2792 | ||
2793 | req->hdr.domain = domain; | |
2794 | AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt, | |
2795 | intf_id); | |
2796 | AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1); | |
2797 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
2798 | ||
2799 | status = be_mcc_notify_wait(adapter); | |
2800 | if (!status) { | |
2801 | struct be_cmd_resp_get_hsw_config *resp = | |
2802 | embedded_payload(wrb); | |
2803 | be_dws_le_to_cpu(&resp->context, | |
2804 | sizeof(resp->context)); | |
2805 | vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context, | |
2806 | pvid, &resp->context); | |
2807 | *pvid = le16_to_cpu(vid); | |
2808 | } | |
2809 | ||
2810 | err: | |
2811 | spin_unlock_bh(&adapter->mcc_lock); | |
2812 | return status; | |
2813 | } | |
2814 | ||
4762f6ce AK |
2815 | int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) |
2816 | { | |
2817 | struct be_mcc_wrb *wrb; | |
2818 | struct be_cmd_req_acpi_wol_magic_config_v1 *req; | |
2819 | int status; | |
2820 | int payload_len = sizeof(*req); | |
2821 | struct be_dma_mem cmd; | |
2822 | ||
f25b119c PR |
2823 | if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, |
2824 | CMD_SUBSYSTEM_ETH)) | |
2825 | return -EPERM; | |
2826 | ||
d98ef50f SR |
2827 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
2828 | return -1; | |
2829 | ||
4762f6ce AK |
2830 | memset(&cmd, 0, sizeof(struct be_dma_mem)); |
2831 | cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); | |
2832 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, | |
2833 | &cmd.dma); | |
2834 | if (!cmd.va) { | |
2835 | dev_err(&adapter->pdev->dev, | |
2836 | "Memory allocation failure\n"); | |
d98ef50f SR |
2837 | status = -ENOMEM; |
2838 | goto err; | |
4762f6ce AK |
2839 | } |
2840 | ||
4762f6ce AK |
2841 | wrb = wrb_from_mbox(adapter); |
2842 | if (!wrb) { | |
2843 | status = -EBUSY; | |
2844 | goto err; | |
2845 | } | |
2846 | ||
2847 | req = cmd.va; | |
2848 | ||
2849 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
2850 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, | |
2851 | payload_len, wrb, &cmd); | |
2852 | ||
2853 | req->hdr.version = 1; | |
2854 | req->query_options = BE_GET_WOL_CAP; | |
2855 | ||
2856 | status = be_mbox_notify_wait(adapter); | |
2857 | if (!status) { | |
2858 | struct be_cmd_resp_acpi_wol_magic_config_v1 *resp; | |
2859 | resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va; | |
2860 | ||
2861 | /* the command could succeed misleadingly on old f/w | |
2862 | * which is not aware of the V1 version. fake an error. */ | |
2863 | if (resp->hdr.response_length < payload_len) { | |
2864 | status = -1; | |
2865 | goto err; | |
2866 | } | |
2867 | adapter->wol_cap = resp->wol_settings; | |
2868 | } | |
2869 | err: | |
2870 | mutex_unlock(&adapter->mbox_lock); | |
d98ef50f SR |
2871 | if (cmd.va) |
2872 | pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); | |
4762f6ce | 2873 | return status; |
941a77d5 SK |
2874 | |
2875 | } | |
2876 | int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, | |
2877 | struct be_dma_mem *cmd) | |
2878 | { | |
2879 | struct be_mcc_wrb *wrb; | |
2880 | struct be_cmd_req_get_ext_fat_caps *req; | |
2881 | int status; | |
2882 | ||
2883 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | |
2884 | return -1; | |
2885 | ||
2886 | wrb = wrb_from_mbox(adapter); | |
2887 | if (!wrb) { | |
2888 | status = -EBUSY; | |
2889 | goto err; | |
2890 | } | |
2891 | ||
2892 | req = cmd->va; | |
2893 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2894 | OPCODE_COMMON_GET_EXT_FAT_CAPABILITES, | |
2895 | cmd->size, wrb, cmd); | |
2896 | req->parameter_type = cpu_to_le32(1); | |
2897 | ||
2898 | status = be_mbox_notify_wait(adapter); | |
2899 | err: | |
2900 | mutex_unlock(&adapter->mbox_lock); | |
2901 | return status; | |
2902 | } | |
2903 | ||
2904 | int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, | |
2905 | struct be_dma_mem *cmd, | |
2906 | struct be_fat_conf_params *configs) | |
2907 | { | |
2908 | struct be_mcc_wrb *wrb; | |
2909 | struct be_cmd_req_set_ext_fat_caps *req; | |
2910 | int status; | |
2911 | ||
2912 | spin_lock_bh(&adapter->mcc_lock); | |
2913 | ||
2914 | wrb = wrb_from_mccq(adapter); | |
2915 | if (!wrb) { | |
2916 | status = -EBUSY; | |
2917 | goto err; | |
2918 | } | |
2919 | ||
2920 | req = cmd->va; | |
2921 | memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params)); | |
2922 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2923 | OPCODE_COMMON_SET_EXT_FAT_CAPABILITES, | |
2924 | cmd->size, wrb, cmd); | |
2925 | ||
2926 | status = be_mcc_notify_wait(adapter); | |
2927 | err: | |
2928 | spin_unlock_bh(&adapter->mcc_lock); | |
2929 | return status; | |
4762f6ce | 2930 | } |
6a4ab669 | 2931 | |
b4e32a71 PR |
2932 | int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name) |
2933 | { | |
2934 | struct be_mcc_wrb *wrb; | |
2935 | struct be_cmd_req_get_port_name *req; | |
2936 | int status; | |
2937 | ||
2938 | if (!lancer_chip(adapter)) { | |
2939 | *port_name = adapter->hba_port_num + '0'; | |
2940 | return 0; | |
2941 | } | |
2942 | ||
2943 | spin_lock_bh(&adapter->mcc_lock); | |
2944 | ||
2945 | wrb = wrb_from_mccq(adapter); | |
2946 | if (!wrb) { | |
2947 | status = -EBUSY; | |
2948 | goto err; | |
2949 | } | |
2950 | ||
2951 | req = embedded_payload(wrb); | |
2952 | ||
2953 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
2954 | OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb, | |
2955 | NULL); | |
2956 | req->hdr.version = 1; | |
2957 | ||
2958 | status = be_mcc_notify_wait(adapter); | |
2959 | if (!status) { | |
2960 | struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb); | |
2961 | *port_name = resp->port_name[adapter->hba_port_num]; | |
2962 | } else { | |
2963 | *port_name = adapter->hba_port_num + '0'; | |
2964 | } | |
2965 | err: | |
2966 | spin_unlock_bh(&adapter->mcc_lock); | |
2967 | return status; | |
2968 | } | |
2969 | ||
abb93951 PR |
2970 | static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count, |
2971 | u32 max_buf_size) | |
2972 | { | |
2973 | struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf; | |
2974 | int i; | |
2975 | ||
2976 | for (i = 0; i < desc_count; i++) { | |
28710c55 | 2977 | desc->desc_len = desc->desc_len ? : RESOURCE_DESC_SIZE; |
abb93951 | 2978 | if (((void *)desc + desc->desc_len) > |
950e2958 WY |
2979 | (void *)(buf + max_buf_size)) |
2980 | return NULL; | |
abb93951 | 2981 | |
a05f99db VV |
2982 | if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_V0 || |
2983 | desc->desc_type == NIC_RESOURCE_DESC_TYPE_V1) | |
950e2958 | 2984 | return desc; |
abb93951 PR |
2985 | |
2986 | desc = (void *)desc + desc->desc_len; | |
2987 | } | |
2988 | ||
950e2958 | 2989 | return NULL; |
abb93951 PR |
2990 | } |
2991 | ||
2992 | /* Uses Mbox */ | |
2993 | int be_cmd_get_func_config(struct be_adapter *adapter) | |
2994 | { | |
2995 | struct be_mcc_wrb *wrb; | |
2996 | struct be_cmd_req_get_func_config *req; | |
2997 | int status; | |
2998 | struct be_dma_mem cmd; | |
2999 | ||
d98ef50f SR |
3000 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
3001 | return -1; | |
3002 | ||
abb93951 PR |
3003 | memset(&cmd, 0, sizeof(struct be_dma_mem)); |
3004 | cmd.size = sizeof(struct be_cmd_resp_get_func_config); | |
3005 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, | |
3006 | &cmd.dma); | |
3007 | if (!cmd.va) { | |
3008 | dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); | |
d98ef50f SR |
3009 | status = -ENOMEM; |
3010 | goto err; | |
abb93951 | 3011 | } |
abb93951 PR |
3012 | |
3013 | wrb = wrb_from_mbox(adapter); | |
3014 | if (!wrb) { | |
3015 | status = -EBUSY; | |
3016 | goto err; | |
3017 | } | |
3018 | ||
3019 | req = cmd.va; | |
3020 | ||
3021 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
3022 | OPCODE_COMMON_GET_FUNC_CONFIG, | |
3023 | cmd.size, wrb, &cmd); | |
3024 | ||
28710c55 KA |
3025 | if (skyhawk_chip(adapter)) |
3026 | req->hdr.version = 1; | |
3027 | ||
abb93951 PR |
3028 | status = be_mbox_notify_wait(adapter); |
3029 | if (!status) { | |
3030 | struct be_cmd_resp_get_func_config *resp = cmd.va; | |
3031 | u32 desc_count = le32_to_cpu(resp->desc_count); | |
3032 | struct be_nic_resource_desc *desc; | |
3033 | ||
3034 | desc = be_get_nic_desc(resp->func_param, desc_count, | |
3035 | sizeof(resp->func_param)); | |
3036 | if (!desc) { | |
3037 | status = -EINVAL; | |
3038 | goto err; | |
3039 | } | |
3040 | ||
d5c18473 | 3041 | adapter->pf_number = desc->pf_num; |
abb93951 PR |
3042 | adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count); |
3043 | adapter->max_vlans = le16_to_cpu(desc->vlan_count); | |
3044 | adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count); | |
3045 | adapter->max_tx_queues = le16_to_cpu(desc->txq_count); | |
3046 | adapter->max_rss_queues = le16_to_cpu(desc->rssq_count); | |
3047 | adapter->max_rx_queues = le16_to_cpu(desc->rq_count); | |
3048 | ||
3049 | adapter->max_event_queues = le16_to_cpu(desc->eq_count); | |
3050 | adapter->if_cap_flags = le32_to_cpu(desc->cap_flags); | |
3da988c9 SB |
3051 | |
3052 | /* Clear flags that driver is not interested in */ | |
3053 | adapter->if_cap_flags &= BE_IF_CAP_FLAGS_WANT; | |
abb93951 PR |
3054 | } |
3055 | err: | |
3056 | mutex_unlock(&adapter->mbox_lock); | |
d98ef50f SR |
3057 | if (cmd.va) |
3058 | pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); | |
abb93951 PR |
3059 | return status; |
3060 | } | |
3061 | ||
a05f99db VV |
3062 | /* Uses mbox */ |
3063 | int be_cmd_get_profile_config_mbox(struct be_adapter *adapter, | |
3064 | u8 domain, struct be_dma_mem *cmd) | |
abb93951 PR |
3065 | { |
3066 | struct be_mcc_wrb *wrb; | |
3067 | struct be_cmd_req_get_profile_config *req; | |
3068 | int status; | |
abb93951 | 3069 | |
a05f99db VV |
3070 | if (mutex_lock_interruptible(&adapter->mbox_lock)) |
3071 | return -1; | |
3072 | wrb = wrb_from_mbox(adapter); | |
3073 | ||
3074 | req = cmd->va; | |
3075 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
3076 | OPCODE_COMMON_GET_PROFILE_CONFIG, | |
3077 | cmd->size, wrb, cmd); | |
3078 | ||
3079 | req->type = ACTIVE_PROFILE_TYPE; | |
3080 | req->hdr.domain = domain; | |
3081 | if (!lancer_chip(adapter)) | |
3082 | req->hdr.version = 1; | |
3083 | ||
3084 | status = be_mbox_notify_wait(adapter); | |
3085 | ||
3086 | mutex_unlock(&adapter->mbox_lock); | |
3087 | return status; | |
3088 | } | |
3089 | ||
3090 | /* Uses sync mcc */ | |
3091 | int be_cmd_get_profile_config_mccq(struct be_adapter *adapter, | |
3092 | u8 domain, struct be_dma_mem *cmd) | |
3093 | { | |
3094 | struct be_mcc_wrb *wrb; | |
3095 | struct be_cmd_req_get_profile_config *req; | |
3096 | int status; | |
abb93951 PR |
3097 | |
3098 | spin_lock_bh(&adapter->mcc_lock); | |
3099 | ||
3100 | wrb = wrb_from_mccq(adapter); | |
3101 | if (!wrb) { | |
3102 | status = -EBUSY; | |
3103 | goto err; | |
3104 | } | |
3105 | ||
a05f99db | 3106 | req = cmd->va; |
abb93951 PR |
3107 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, |
3108 | OPCODE_COMMON_GET_PROFILE_CONFIG, | |
a05f99db | 3109 | cmd->size, wrb, cmd); |
abb93951 PR |
3110 | |
3111 | req->type = ACTIVE_PROFILE_TYPE; | |
3112 | req->hdr.domain = domain; | |
a05f99db VV |
3113 | if (!lancer_chip(adapter)) |
3114 | req->hdr.version = 1; | |
abb93951 PR |
3115 | |
3116 | status = be_mcc_notify_wait(adapter); | |
a05f99db VV |
3117 | |
3118 | err: | |
3119 | spin_unlock_bh(&adapter->mcc_lock); | |
3120 | return status; | |
3121 | } | |
3122 | ||
3123 | /* Uses sync mcc, if MCCQ is already created otherwise mbox */ | |
3124 | int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags, | |
3125 | u16 *txq_count, u8 domain) | |
3126 | { | |
3127 | struct be_queue_info *mccq = &adapter->mcc_obj.q; | |
3128 | struct be_dma_mem cmd; | |
3129 | int status; | |
3130 | ||
3131 | memset(&cmd, 0, sizeof(struct be_dma_mem)); | |
3132 | if (!lancer_chip(adapter)) | |
3133 | cmd.size = sizeof(struct be_cmd_resp_get_profile_config_v1); | |
3134 | else | |
3135 | cmd.size = sizeof(struct be_cmd_resp_get_profile_config); | |
3136 | cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, | |
3137 | &cmd.dma); | |
3138 | if (!cmd.va) { | |
3139 | dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); | |
3140 | return -ENOMEM; | |
3141 | } | |
3142 | ||
3143 | if (!mccq->created) | |
3144 | status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd); | |
3145 | else | |
3146 | status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd); | |
abb93951 PR |
3147 | if (!status) { |
3148 | struct be_cmd_resp_get_profile_config *resp = cmd.va; | |
3149 | u32 desc_count = le32_to_cpu(resp->desc_count); | |
3150 | struct be_nic_resource_desc *desc; | |
3151 | ||
3152 | desc = be_get_nic_desc(resp->func_param, desc_count, | |
3153 | sizeof(resp->func_param)); | |
3154 | ||
3155 | if (!desc) { | |
3156 | status = -EINVAL; | |
3157 | goto err; | |
3158 | } | |
a05f99db VV |
3159 | if (cap_flags) |
3160 | *cap_flags = le32_to_cpu(desc->cap_flags); | |
3161 | if (txq_count) | |
3162 | *txq_count = le32_to_cpu(desc->txq_count); | |
abb93951 PR |
3163 | } |
3164 | err: | |
a05f99db VV |
3165 | if (cmd.va) |
3166 | pci_free_consistent(adapter->pdev, cmd.size, | |
3167 | cmd.va, cmd.dma); | |
abb93951 PR |
3168 | return status; |
3169 | } | |
3170 | ||
d5c18473 PR |
3171 | /* Uses sync mcc */ |
3172 | int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, | |
3173 | u8 domain) | |
3174 | { | |
3175 | struct be_mcc_wrb *wrb; | |
3176 | struct be_cmd_req_set_profile_config *req; | |
3177 | int status; | |
3178 | ||
3179 | spin_lock_bh(&adapter->mcc_lock); | |
3180 | ||
3181 | wrb = wrb_from_mccq(adapter); | |
3182 | if (!wrb) { | |
3183 | status = -EBUSY; | |
3184 | goto err; | |
3185 | } | |
3186 | ||
3187 | req = embedded_payload(wrb); | |
3188 | ||
3189 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
3190 | OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req), | |
3191 | wrb, NULL); | |
3192 | ||
3193 | req->hdr.domain = domain; | |
3194 | req->desc_count = cpu_to_le32(1); | |
3195 | ||
a05f99db | 3196 | req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_V0; |
d5c18473 PR |
3197 | req->nic_desc.desc_len = RESOURCE_DESC_SIZE; |
3198 | req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV); | |
3199 | req->nic_desc.pf_num = adapter->pf_number; | |
3200 | req->nic_desc.vf_num = domain; | |
3201 | ||
3202 | /* Mark fields invalid */ | |
3203 | req->nic_desc.unicast_mac_count = 0xFFFF; | |
3204 | req->nic_desc.mcc_count = 0xFFFF; | |
3205 | req->nic_desc.vlan_count = 0xFFFF; | |
3206 | req->nic_desc.mcast_mac_count = 0xFFFF; | |
3207 | req->nic_desc.txq_count = 0xFFFF; | |
3208 | req->nic_desc.rq_count = 0xFFFF; | |
3209 | req->nic_desc.rssq_count = 0xFFFF; | |
3210 | req->nic_desc.lro_count = 0xFFFF; | |
3211 | req->nic_desc.cq_count = 0xFFFF; | |
3212 | req->nic_desc.toe_conn_count = 0xFFFF; | |
3213 | req->nic_desc.eq_count = 0xFFFF; | |
3214 | req->nic_desc.link_param = 0xFF; | |
3215 | req->nic_desc.bw_min = 0xFFFFFFFF; | |
3216 | req->nic_desc.acpi_params = 0xFF; | |
3217 | req->nic_desc.wol_param = 0x0F; | |
3218 | ||
3219 | /* Change BW */ | |
3220 | req->nic_desc.bw_min = cpu_to_le32(bps); | |
3221 | req->nic_desc.bw_max = cpu_to_le32(bps); | |
3222 | status = be_mcc_notify_wait(adapter); | |
3223 | err: | |
3224 | spin_unlock_bh(&adapter->mcc_lock); | |
3225 | return status; | |
3226 | } | |
3227 | ||
4c876616 SP |
3228 | int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, |
3229 | int vf_num) | |
3230 | { | |
3231 | struct be_mcc_wrb *wrb; | |
3232 | struct be_cmd_req_get_iface_list *req; | |
3233 | struct be_cmd_resp_get_iface_list *resp; | |
3234 | int status; | |
3235 | ||
3236 | spin_lock_bh(&adapter->mcc_lock); | |
3237 | ||
3238 | wrb = wrb_from_mccq(adapter); | |
3239 | if (!wrb) { | |
3240 | status = -EBUSY; | |
3241 | goto err; | |
3242 | } | |
3243 | req = embedded_payload(wrb); | |
3244 | ||
3245 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
3246 | OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp), | |
3247 | wrb, NULL); | |
3248 | req->hdr.domain = vf_num + 1; | |
3249 | ||
3250 | status = be_mcc_notify_wait(adapter); | |
3251 | if (!status) { | |
3252 | resp = (struct be_cmd_resp_get_iface_list *)req; | |
3253 | vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id); | |
3254 | } | |
3255 | ||
3256 | err: | |
3257 | spin_unlock_bh(&adapter->mcc_lock); | |
3258 | return status; | |
3259 | } | |
3260 | ||
5c510811 SK |
3261 | static int lancer_wait_idle(struct be_adapter *adapter) |
3262 | { | |
3263 | #define SLIPORT_IDLE_TIMEOUT 30 | |
3264 | u32 reg_val; | |
3265 | int status = 0, i; | |
3266 | ||
3267 | for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) { | |
3268 | reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET); | |
3269 | if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0) | |
3270 | break; | |
3271 | ||
3272 | ssleep(1); | |
3273 | } | |
3274 | ||
3275 | if (i == SLIPORT_IDLE_TIMEOUT) | |
3276 | status = -1; | |
3277 | ||
3278 | return status; | |
3279 | } | |
3280 | ||
3281 | int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask) | |
3282 | { | |
3283 | int status = 0; | |
3284 | ||
3285 | status = lancer_wait_idle(adapter); | |
3286 | if (status) | |
3287 | return status; | |
3288 | ||
3289 | iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET); | |
3290 | ||
3291 | return status; | |
3292 | } | |
3293 | ||
3294 | /* Routine to check whether dump image is present or not */ | |
3295 | bool dump_present(struct be_adapter *adapter) | |
3296 | { | |
3297 | u32 sliport_status = 0; | |
3298 | ||
3299 | sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); | |
3300 | return !!(sliport_status & SLIPORT_STATUS_DIP_MASK); | |
3301 | } | |
3302 | ||
3303 | int lancer_initiate_dump(struct be_adapter *adapter) | |
3304 | { | |
3305 | int status; | |
3306 | ||
3307 | /* give firmware reset and diagnostic dump */ | |
3308 | status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK | | |
3309 | PHYSDEV_CONTROL_DD_MASK); | |
3310 | if (status < 0) { | |
3311 | dev_err(&adapter->pdev->dev, "Firmware reset failed\n"); | |
3312 | return status; | |
3313 | } | |
3314 | ||
3315 | status = lancer_wait_idle(adapter); | |
3316 | if (status) | |
3317 | return status; | |
3318 | ||
3319 | if (!dump_present(adapter)) { | |
3320 | dev_err(&adapter->pdev->dev, "Dump image not present\n"); | |
3321 | return -1; | |
3322 | } | |
3323 | ||
3324 | return 0; | |
3325 | } | |
3326 | ||
dcf7ebba PR |
3327 | /* Uses sync mcc */ |
3328 | int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain) | |
3329 | { | |
3330 | struct be_mcc_wrb *wrb; | |
3331 | struct be_cmd_enable_disable_vf *req; | |
3332 | int status; | |
3333 | ||
3334 | if (!lancer_chip(adapter)) | |
3335 | return 0; | |
3336 | ||
3337 | spin_lock_bh(&adapter->mcc_lock); | |
3338 | ||
3339 | wrb = wrb_from_mccq(adapter); | |
3340 | if (!wrb) { | |
3341 | status = -EBUSY; | |
3342 | goto err; | |
3343 | } | |
3344 | ||
3345 | req = embedded_payload(wrb); | |
3346 | ||
3347 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
3348 | OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req), | |
3349 | wrb, NULL); | |
3350 | ||
3351 | req->hdr.domain = domain; | |
3352 | req->enable = 1; | |
3353 | status = be_mcc_notify_wait(adapter); | |
3354 | err: | |
3355 | spin_unlock_bh(&adapter->mcc_lock); | |
3356 | return status; | |
3357 | } | |
3358 | ||
68c45a2d SK |
3359 | int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable) |
3360 | { | |
3361 | struct be_mcc_wrb *wrb; | |
3362 | struct be_cmd_req_intr_set *req; | |
3363 | int status; | |
3364 | ||
3365 | if (mutex_lock_interruptible(&adapter->mbox_lock)) | |
3366 | return -1; | |
3367 | ||
3368 | wrb = wrb_from_mbox(adapter); | |
3369 | ||
3370 | req = embedded_payload(wrb); | |
3371 | ||
3372 | be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
3373 | OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req), | |
3374 | wrb, NULL); | |
3375 | ||
3376 | req->intr_enabled = intr_enable; | |
3377 | ||
3378 | status = be_mbox_notify_wait(adapter); | |
3379 | ||
3380 | mutex_unlock(&adapter->mbox_lock); | |
3381 | return status; | |
3382 | } | |
3383 | ||
6a4ab669 PP |
3384 | int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, |
3385 | int wrb_payload_size, u16 *cmd_status, u16 *ext_status) | |
3386 | { | |
3387 | struct be_adapter *adapter = netdev_priv(netdev_handle); | |
3388 | struct be_mcc_wrb *wrb; | |
3389 | struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload; | |
3390 | struct be_cmd_req_hdr *req; | |
3391 | struct be_cmd_resp_hdr *resp; | |
3392 | int status; | |
3393 | ||
3394 | spin_lock_bh(&adapter->mcc_lock); | |
3395 | ||
3396 | wrb = wrb_from_mccq(adapter); | |
3397 | if (!wrb) { | |
3398 | status = -EBUSY; | |
3399 | goto err; | |
3400 | } | |
3401 | req = embedded_payload(wrb); | |
3402 | resp = embedded_payload(wrb); | |
3403 | ||
3404 | be_wrb_cmd_hdr_prepare(req, hdr->subsystem, | |
3405 | hdr->opcode, wrb_payload_size, wrb, NULL); | |
3406 | memcpy(req, wrb_payload, wrb_payload_size); | |
3407 | be_dws_cpu_to_le(req, wrb_payload_size); | |
3408 | ||
3409 | status = be_mcc_notify_wait(adapter); | |
3410 | if (cmd_status) | |
3411 | *cmd_status = (status & 0xffff); | |
3412 | if (ext_status) | |
3413 | *ext_status = 0; | |
3414 | memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length); | |
3415 | be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length); | |
3416 | err: | |
3417 | spin_unlock_bh(&adapter->mcc_lock); | |
3418 | return status; | |
3419 | } | |
3420 | EXPORT_SYMBOL(be_roce_mcc_cmd); |