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be2net: add ethtool "-m" option support
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6b7c5b94 1/*
40263820 2 * Copyright (C) 2005 - 2014 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
6a4ab669 18#include <linux/module.h>
6b7c5b94 19#include "be.h"
8788fdc2 20#include "be_cmds.h"
6b7c5b94 21
f25b119c
PR		 22static struct be_cmd_priv_map cmd_priv_map[] = {
23 {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
25 CMD_SUBSYSTEM_ETH,
26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
28 },
29 {
30 OPCODE_COMMON_GET_FLOW_CONTROL,
31 CMD_SUBSYSTEM_COMMON,
32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
34 },
35 {
36 OPCODE_COMMON_SET_FLOW_CONTROL,
37 CMD_SUBSYSTEM_COMMON,
38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
40 },
41 {
42 OPCODE_ETH_GET_PPORT_STATS,
43 CMD_SUBSYSTEM_ETH,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
46 },
47 {
48 OPCODE_COMMON_GET_PHY_DETAILS,
49 CMD_SUBSYSTEM_COMMON,
50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 }
53};
54
a2cc4e0b 55static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 56{
57 int i;
58 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
59 u32 cmd_privileges = adapter->cmd_privileges;
60
61 for (i = 0; i < num_entries; i++)
62 if (opcode == cmd_priv_map[i].opcode &&
63 subsystem == cmd_priv_map[i].subsystem)
64 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
65 return false;
66
67 return true;
68}
69
3de09455
SK		 70static inline void *embedded_payload(struct be_mcc_wrb *wrb)
71{
72 return wrb->payload.embedded_payload;
73}
609ff3bb 74
8788fdc2 75static void be_mcc_notify(struct be_adapter *adapter)
5fb379ee 76{
8788fdc2 77 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 78 u32 val = 0;
79
6589ade0 80 if (be_error(adapter))
7acc2087 81 return;
7acc2087 82
5fb379ee
SP		 83 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
84 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 85
86 wmb();
8788fdc2 87 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
5fb379ee
SP		 88}
89
90/* To check if valid bit is set, check the entire word as we don't know
91 * the endianness of the data (old entry is host endian while a new entry is
92 * little endian) */
efd2e40a 93static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 94{
9e9ff4b7
SP		 95 u32 flags;
96
5fb379ee 97 if (compl->flags != 0) {
9e9ff4b7
SP		 98 flags = le32_to_cpu(compl->flags);
99 if (flags & CQE_FLAGS_VALID_MASK) {
100 compl->flags = flags;
101 return true;
102 }
5fb379ee 103 }
9e9ff4b7 104 return false;
5fb379ee
SP		 105}
106
107/* Need to reset the entire word that houses the valid bit */
efd2e40a 108static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 109{
110 compl->flags = 0;
111}
112
652bf646
PR		 113static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
114{
115 unsigned long addr;
116
117 addr = tag1;
118 addr = ((addr << 16) << 16) | tag0;
119 return (void *)addr;
120}
121
4c60005f
KA		 122static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
123{
124 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
125 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
126 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
127 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
128 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
129 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
130 return true;
131 else
132 return false;
133}
134
559b633f
SP		 135/* Place holder for all the async MCC cmds wherein the caller is not in a busy
136 * loop (has not issued be_mcc_notify_wait())
137 */
138static void be_async_cmd_process(struct be_adapter *adapter,
139 struct be_mcc_compl *compl,
140 struct be_cmd_resp_hdr *resp_hdr)
141{
142 enum mcc_base_status base_status = base_status(compl->status);
143 u8 opcode = 0, subsystem = 0;
144
145 if (resp_hdr) {
146 opcode = resp_hdr->opcode;
147 subsystem = resp_hdr->subsystem;
148 }
149
150 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
151 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
152 complete(&adapter->et_cmd_compl);
153 return;
154 }
155
156 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
157 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
158 subsystem == CMD_SUBSYSTEM_COMMON) {
159 adapter->flash_status = compl->status;
160 complete(&adapter->et_cmd_compl);
161 return;
162 }
163
164 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
165 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
166 subsystem == CMD_SUBSYSTEM_ETH &&
167 base_status == MCC_STATUS_SUCCESS) {
168 be_parse_stats(adapter);
169 adapter->stats_cmd_sent = false;
170 return;
171 }
172
173 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
174 subsystem == CMD_SUBSYSTEM_COMMON) {
175 if (base_status == MCC_STATUS_SUCCESS) {
176 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
177 (void *)resp_hdr;
178 adapter->drv_stats.be_on_die_temperature =
179 resp->on_die_temperature;
180 } else {
181 adapter->be_get_temp_freq = 0;
182 }
183 return;
184 }
185}
186
8788fdc2 187static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 188 struct be_mcc_compl *compl)
5fb379ee 189{
4c60005f
KA		 190 enum mcc_base_status base_status;
191 enum mcc_addl_status addl_status;
652bf646
PR		 192 struct be_cmd_resp_hdr *resp_hdr;
193 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 194
195 /* Just swap the status to host endian; mcc tag is opaquely copied
196 * from mcc_wrb */
197 be_dws_le_to_cpu(compl, 4);
198
4c60005f
KA		 199 base_status = base_status(compl->status);
200 addl_status = addl_status(compl->status);
96c9b2e4 201
652bf646 202 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 203 if (resp_hdr) {
204 opcode = resp_hdr->opcode;
205 subsystem = resp_hdr->subsystem;
206 }
207
559b633f 208 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 209
559b633f
SP		 210 if (base_status != MCC_STATUS_SUCCESS &&
211 !be_skip_err_log(opcode, base_status, addl_status)) {
96c9b2e4 212
4c60005f 213 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
97f1d8cd 214 dev_warn(&adapter->pdev->dev,
522609f2 215 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 216 opcode, subsystem);
2b3f291b 217 } else {
97f1d8cd
VV		 218 dev_err(&adapter->pdev->dev,
219 "opcode %d-%d failed:status %d-%d\n",
4c60005f 220 opcode, subsystem, base_status, addl_status);
2b3f291b 221 }
5fb379ee 222 }
4c60005f 223 return compl->status;
5fb379ee
SP		 224}
225
a8f447bd 226/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 227static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 228 struct be_mcc_compl *compl)
a8f447bd 229{
3acf19d9
SP		 230 struct be_async_event_link_state *evt =
231 (struct be_async_event_link_state *)compl;
232
b236916a 233 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 234 adapter->phy.link_speed = -1;
b236916a 235
bdce2ad7
SR		 236 /* On BEx the FW does not send a separate link status
237 * notification for physical and logical link.
238 * On other chips just process the logical link
239 * status notification
240 */
241 if (!BEx_chip(adapter) &&
2e177a5c
PR		 242 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
243 return;
244
b236916a
AK		 245 /* For the initial link status do not rely on the ASYNC event as
246 * it may not be received in some cases.
247 */
248 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 249 be_link_status_update(adapter,
250 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 251}
252
cc4ce020
SK		 253/* Grp5 CoS Priority evt */
254static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 255 struct be_mcc_compl *compl)
cc4ce020 256{
3acf19d9
SP		 257 struct be_async_event_grp5_cos_priority *evt =
258 (struct be_async_event_grp5_cos_priority *)compl;
259
cc4ce020
SK		 260 if (evt->valid) {
261 adapter->vlan_prio_bmap = evt->available_priority_bmap;
60964dd7 262 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
cc4ce020
SK		 263 adapter->recommended_prio =
264 evt->reco_default_priority << VLAN_PRIO_SHIFT;
265 }
266}
267
323ff71e 268/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 269static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 270 struct be_mcc_compl *compl)
cc4ce020 271{
3acf19d9
SP		 272 struct be_async_event_grp5_qos_link_speed *evt =
273 (struct be_async_event_grp5_qos_link_speed *)compl;
274
323ff71e
SP		 275 if (adapter->phy.link_speed >= 0 &&
276 evt->physical_port == adapter->port_num)
277 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 278}
279
3968fa1e
AK		 280/*Grp5 PVID evt*/
281static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 282 struct be_mcc_compl *compl)
3968fa1e 283{
3acf19d9
SP		 284 struct be_async_event_grp5_pvid_state *evt =
285 (struct be_async_event_grp5_pvid_state *)compl;
286
bdac85b5 287 if (evt->enabled) {
939cf306 288 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 289 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
290 } else {
3968fa1e 291 adapter->pvid = 0;
bdac85b5 292 }
3968fa1e
AK		 293}
294
cc4ce020 295static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 296 struct be_mcc_compl *compl)
cc4ce020 297{
3acf19d9
SP		 298 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
299 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 300
301 switch (event_type) {
302 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 303 be_async_grp5_cos_priority_process(adapter, compl);
304 break;
cc4ce020 305 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 306 be_async_grp5_qos_speed_process(adapter, compl);
307 break;
3968fa1e 308 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 309 be_async_grp5_pvid_state_process(adapter, compl);
310 break;
cc4ce020 311 default:
cc4ce020
SK		 312 break;
313 }
314}
315
bc0c3405 316static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 317 struct be_mcc_compl *cmp)
bc0c3405
AK		 318{
319 u8 event_type = 0;
320 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
321
3acf19d9
SP		 322 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
323 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 324
325 switch (event_type) {
326 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
327 if (evt->valid)
328 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
329 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
330 break;
331 default:
05ccaa2b
VV		 332 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
333 event_type);
bc0c3405
AK		 334 break;
335 }
336}
337
3acf19d9 338static inline bool is_link_state_evt(u32 flags)
a8f447bd 339{
3acf19d9
SP		 340 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
341 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 342}
5fb379ee 343
3acf19d9 344static inline bool is_grp5_evt(u32 flags)
cc4ce020 345{
3acf19d9
SP		 346 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
347 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 348}
349
3acf19d9 350static inline bool is_dbg_evt(u32 flags)
bc0c3405 351{
3acf19d9
SP		 352 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
353 ASYNC_EVENT_CODE_QNQ;
354}
355
356static void be_mcc_event_process(struct be_adapter *adapter,
357 struct be_mcc_compl *compl)
358{
359 if (is_link_state_evt(compl->flags))
360 be_async_link_state_process(adapter, compl);
361 else if (is_grp5_evt(compl->flags))
362 be_async_grp5_evt_process(adapter, compl);
363 else if (is_dbg_evt(compl->flags))
364 be_async_dbg_evt_process(adapter, compl);
bc0c3405
AK		 365}
366
efd2e40a 367static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 368{
8788fdc2 369 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 370 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 371
372 if (be_mcc_compl_is_new(compl)) {
373 queue_tail_inc(mcc_cq);
374 return compl;
375 }
376 return NULL;
377}
378
7a1e9b20
SP		 379void be_async_mcc_enable(struct be_adapter *adapter)
380{
381 spin_lock_bh(&adapter->mcc_cq_lock);
382
383 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
384 adapter->mcc_obj.rearm_cq = true;
385
386 spin_unlock_bh(&adapter->mcc_cq_lock);
387}
388
389void be_async_mcc_disable(struct be_adapter *adapter)
390{
a323d9bf
SP		 391 spin_lock_bh(&adapter->mcc_cq_lock);
392
7a1e9b20 393 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 394 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
395
396 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 397}
398
10ef9ab4 399int be_process_mcc(struct be_adapter *adapter)
5fb379ee 400{
efd2e40a 401 struct be_mcc_compl *compl;
10ef9ab4 402 int num = 0, status = 0;
7a1e9b20 403 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 404
072a9c48 405 spin_lock(&adapter->mcc_cq_lock);
3acf19d9 406
8788fdc2 407 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 408 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 409 be_mcc_event_process(adapter, compl);
b31c50a7 410 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 411 status = be_mcc_compl_process(adapter, compl);
412 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 413 }
414 be_mcc_compl_use(compl);
415 num++;
416 }
b31c50a7 417
10ef9ab4
SP		 418 if (num)
419 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
420
072a9c48 421 spin_unlock(&adapter->mcc_cq_lock);
10ef9ab4 422 return status;
5fb379ee
SP		 423}
424
6ac7b687 425/* Wait till no more pending mcc requests are present */
b31c50a7 426static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 427{
b31c50a7 428#define mcc_timeout 120000 /* 12s timeout */
10ef9ab4 429 int i, status = 0;
f31e50a8
SP		 430 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
431
6ac7b687 432 for (i = 0; i < mcc_timeout; i++) {
6589ade0
SP		 433 if (be_error(adapter))
434 return -EIO;
435
072a9c48 436 local_bh_disable();
10ef9ab4 437 status = be_process_mcc(adapter);
072a9c48 438 local_bh_enable();
b31c50a7 439
f31e50a8 440 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687
SP		 441 break;
442 udelay(100);
443 }
b31c50a7 444 if (i == mcc_timeout) {
6589ade0
SP		 445 dev_err(&adapter->pdev->dev, "FW not responding\n");
446 adapter->fw_timeout = true;
652bf646 447 return -EIO;
b31c50a7 448 }
f31e50a8 449 return status;
6ac7b687
SP		 450}
451
452/* Notify MCC requests and wait for completion */
b31c50a7 453static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 454{
652bf646
PR		 455 int status;
456 struct be_mcc_wrb *wrb;
457 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
458 u16 index = mcc_obj->q.head;
459 struct be_cmd_resp_hdr *resp;
460
461 index_dec(&index, mcc_obj->q.len);
462 wrb = queue_index_node(&mcc_obj->q, index);
463
464 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
465
8788fdc2 466 be_mcc_notify(adapter);
652bf646
PR		 467
468 status = be_mcc_wait_compl(adapter);
469 if (status == -EIO)
470 goto out;
471
4c60005f
KA		 472 status = (resp->base_status |
473 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
474 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 475out:
476 return status;
6ac7b687
SP		 477}
478
5f0b849e 479static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 480{
f25b03a7 481 int msecs = 0;
6b7c5b94
SP		 482 u32 ready;
483
484 do {
6589ade0
SP		 485 if (be_error(adapter))
486 return -EIO;
487
cf588477 488 ready = ioread32(db);
434b3648 489 if (ready == 0xffffffff)
cf588477 490 return -1;
cf588477
SP		 491
492 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 493 if (ready)
494 break;
495
f25b03a7 496 if (msecs > 4000) {
6589ade0
SP		 497 dev_err(&adapter->pdev->dev, "FW not responding\n");
498 adapter->fw_timeout = true;
f67ef7ba 499 be_detect_error(adapter);
6b7c5b94
SP		 500 return -1;
501 }
502
1dbf53a2 503 msleep(1);
f25b03a7 504 msecs++;
6b7c5b94
SP		 505 } while (true);
506
507 return 0;
508}
509
510/*
511 * Insert the mailbox address into the doorbell in two steps
5fb379ee 512 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 513 */
b31c50a7 514static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 515{
516 int status;
6b7c5b94 517 u32 val = 0;
8788fdc2
SP		 518 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
519 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 520 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 521 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 522
cf588477
SP		 523 /* wait for ready to be set */
524 status = be_mbox_db_ready_wait(adapter, db);
525 if (status != 0)
526 return status;
527
6b7c5b94
SP		 528 val |= MPU_MAILBOX_DB_HI_MASK;
529 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
530 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
531 iowrite32(val, db);
532
533 /* wait for ready to be set */
5f0b849e 534 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 535 if (status != 0)
536 return status;
537
538 val = 0;
6b7c5b94
SP		 539 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
540 val |= (u32)(mbox_mem->dma >> 4) << 2;
541 iowrite32(val, db);
542
5f0b849e 543 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 544 if (status != 0)
545 return status;
546
5fb379ee 547 /* A cq entry has been made now */
efd2e40a
SP		 548 if (be_mcc_compl_is_new(compl)) {
549 status = be_mcc_compl_process(adapter, &mbox->compl);
550 be_mcc_compl_use(compl);
5fb379ee
SP		 551 if (status)
552 return status;
553 } else {
5f0b849e 554 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 555 return -1;
556 }
5fb379ee 557 return 0;
6b7c5b94
SP		 558}
559
c5b3ad4c 560static u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 561{
fe6d2a38
SP		 562 u32 sem;
563
c5b3ad4c
SP		 564 if (BEx_chip(adapter))
565 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 566 else
c5b3ad4c
SP		 567 pci_read_config_dword(adapter->pdev,
568 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
569
570 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 571}
572
87f20c26 573static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 574{
575#define SLIPORT_READY_TIMEOUT 30
576 u32 sliport_status;
577 int status = 0, i;
578
579 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
580 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
581 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
582 break;
583
584 msleep(1000);
585 }
586
587 if (i == SLIPORT_READY_TIMEOUT)
588 status = -1;
589
590 return status;
591}
592
67297ad8
PR		 593static bool lancer_provisioning_error(struct be_adapter *adapter)
594{
595 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
596 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
597 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
a2cc4e0b
SP		 598 sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET);
599 sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET);
67297ad8
PR		 600
601 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
602 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
603 return true;
604 }
605 return false;
606}
607
bf99e50d
PR		 608int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
609{
610 int status;
611 u32 sliport_status, err, reset_needed;
67297ad8
PR		 612 bool resource_error;
613
614 resource_error = lancer_provisioning_error(adapter);
615 if (resource_error)
01e5b2c4 616 return -EAGAIN;
67297ad8 617
bf99e50d
PR		 618 status = lancer_wait_ready(adapter);
619 if (!status) {
620 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
621 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
622 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
623 if (err && reset_needed) {
624 iowrite32(SLI_PORT_CONTROL_IP_MASK,
625 adapter->db + SLIPORT_CONTROL_OFFSET);
626
627 /* check adapter has corrected the error */
628 status = lancer_wait_ready(adapter);
629 sliport_status = ioread32(adapter->db +
630 SLIPORT_STATUS_OFFSET);
631 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
632 SLIPORT_STATUS_RN_MASK);
633 if (status || sliport_status)
634 status = -1;
635 } else if (err || reset_needed) {
636 status = -1;
637 }
638 }
67297ad8
PR		 639 /* Stop error recovery if error is not recoverable.
640 * No resource error is temporary errors and will go away
641 * when PF provisions resources.
642 */
643 resource_error = lancer_provisioning_error(adapter);
01e5b2c4
SK		 644 if (resource_error)
645 status = -EAGAIN;
67297ad8 646
bf99e50d
PR		 647 return status;
648}
649
650int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 651{
43a04fdc
SP		 652 u16 stage;
653 int status, timeout = 0;
6ed35eea 654 struct device *dev = &adapter->pdev->dev;
6b7c5b94 655
bf99e50d
PR		 656 if (lancer_chip(adapter)) {
657 status = lancer_wait_ready(adapter);
658 return status;
659 }
660
43a04fdc 661 do {
c5b3ad4c 662 stage = be_POST_stage_get(adapter);
66d29cbc 663 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 664 return 0;
66d29cbc 665
a2cc4e0b 666 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 667 if (msleep_interruptible(2000)) {
668 dev_err(dev, "Waiting for POST aborted\n");
669 return -EINTR;
43a04fdc 670 }
66d29cbc 671 timeout += 2;
3ab81b5f 672 } while (timeout < 60);
6b7c5b94 673
6ed35eea 674 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
43a04fdc 675 return -1;
6b7c5b94
SP		 676}
677
6b7c5b94
SP		 678
679static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
680{
681 return &wrb->payload.sgl[0];
682}
683
a2cc4e0b 684static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 685{
686 wrb->tag0 = addr & 0xFFFFFFFF;
687 wrb->tag1 = upper_32_bits(addr);
688}
6b7c5b94
SP		 689
690/* Don't touch the hdr after it's prepared */
106df1e3
SK		 691/* mem will be NULL for embedded commands */
692static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 693 u8 subsystem, u8 opcode, int cmd_len,
694 struct be_mcc_wrb *wrb,
695 struct be_dma_mem *mem)
6b7c5b94 696{
106df1e3
SK		 697 struct be_sge *sge;
698
6b7c5b94
SP		 699 req_hdr->opcode = opcode;
700 req_hdr->subsystem = subsystem;
701 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 702 req_hdr->version = 0;
bea50988 703 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 704 wrb->payload_length = cmd_len;
705 if (mem) {
706 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
707 MCC_WRB_SGE_CNT_SHIFT;
708 sge = nonembedded_sgl(wrb);
709 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
710 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
711 sge->len = cpu_to_le32(mem->size);
712 } else
713 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
714 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 715}
716
717static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 718 struct be_dma_mem *mem)
6b7c5b94
SP		 719{
720 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
721 u64 dma = (u64)mem->dma;
722
723 for (i = 0; i < buf_pages; i++) {
724 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
725 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
726 dma += PAGE_SIZE_4K;
727 }
728}
729
b31c50a7 730static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 731{
b31c50a7
SP		 732 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
733 struct be_mcc_wrb *wrb
734 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
735 memset(wrb, 0, sizeof(*wrb));
736 return wrb;
6b7c5b94
SP		 737}
738
b31c50a7 739static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 740{
b31c50a7
SP		 741 struct be_queue_info *mccq = &adapter->mcc_obj.q;
742 struct be_mcc_wrb *wrb;
743
aa790db9
PR		 744 if (!mccq->created)
745 return NULL;
746
4d277125 747 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 748 return NULL;
713d0394 749
b31c50a7
SP		 750 wrb = queue_head_node(mccq);
751 queue_head_inc(mccq);
752 atomic_inc(&mccq->used);
753 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 754 return wrb;
755}
756
bea50988
SP		 757static bool use_mcc(struct be_adapter *adapter)
758{
759 return adapter->mcc_obj.q.created;
760}
761
762/* Must be used only in process context */
763static int be_cmd_lock(struct be_adapter *adapter)
764{
765 if (use_mcc(adapter)) {
766 spin_lock_bh(&adapter->mcc_lock);
767 return 0;
768 } else {
769 return mutex_lock_interruptible(&adapter->mbox_lock);
770 }
771}
772
773/* Must be used only in process context */
774static void be_cmd_unlock(struct be_adapter *adapter)
775{
776 if (use_mcc(adapter))
777 spin_unlock_bh(&adapter->mcc_lock);
778 else
779 return mutex_unlock(&adapter->mbox_lock);
780}
781
782static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
783 struct be_mcc_wrb *wrb)
784{
785 struct be_mcc_wrb *dest_wrb;
786
787 if (use_mcc(adapter)) {
788 dest_wrb = wrb_from_mccq(adapter);
789 if (!dest_wrb)
790 return NULL;
791 } else {
792 dest_wrb = wrb_from_mbox(adapter);
793 }
794
795 memcpy(dest_wrb, wrb, sizeof(*wrb));
796 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
797 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
798
799 return dest_wrb;
800}
801
802/* Must be used only in process context */
803static int be_cmd_notify_wait(struct be_adapter *adapter,
804 struct be_mcc_wrb *wrb)
805{
806 struct be_mcc_wrb *dest_wrb;
807 int status;
808
809 status = be_cmd_lock(adapter);
810 if (status)
811 return status;
812
813 dest_wrb = be_cmd_copy(adapter, wrb);
814 if (!dest_wrb)
815 return -EBUSY;
816
817 if (use_mcc(adapter))
818 status = be_mcc_notify_wait(adapter);
819 else
820 status = be_mbox_notify_wait(adapter);
821
822 if (!status)
823 memcpy(wrb, dest_wrb, sizeof(*wrb));
824
825 be_cmd_unlock(adapter);
826 return status;
827}
828
2243e2e9
SP		 829/* Tell fw we're about to start firing cmds by writing a
830 * special pattern across the wrb hdr; uses mbox
831 */
832int be_cmd_fw_init(struct be_adapter *adapter)
833{
834 u8 *wrb;
835 int status;
836
bf99e50d
PR		 837 if (lancer_chip(adapter))
838 return 0;
839
2984961c
IV		 840 if (mutex_lock_interruptible(&adapter->mbox_lock))
841 return -1;
2243e2e9
SP		 842
843 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 844 *wrb++ = 0xFF;
845 *wrb++ = 0x12;
846 *wrb++ = 0x34;
847 *wrb++ = 0xFF;
848 *wrb++ = 0xFF;
849 *wrb++ = 0x56;
850 *wrb++ = 0x78;
851 *wrb = 0xFF;
2243e2e9
SP		 852
853 status = be_mbox_notify_wait(adapter);
854
2984961c 855 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 856 return status;
857}
858
859/* Tell fw we're done with firing cmds by writing a
860 * special pattern across the wrb hdr; uses mbox
861 */
862int be_cmd_fw_clean(struct be_adapter *adapter)
863{
864 u8 *wrb;
865 int status;
866
bf99e50d
PR		 867 if (lancer_chip(adapter))
868 return 0;
869
2984961c
IV		 870 if (mutex_lock_interruptible(&adapter->mbox_lock))
871 return -1;
2243e2e9
SP		 872
873 wrb = (u8 *)wrb_from_mbox(adapter);
874 *wrb++ = 0xFF;
875 *wrb++ = 0xAA;
876 *wrb++ = 0xBB;
877 *wrb++ = 0xFF;
878 *wrb++ = 0xFF;
879 *wrb++ = 0xCC;
880 *wrb++ = 0xDD;
881 *wrb = 0xFF;
882
883 status = be_mbox_notify_wait(adapter);
884
2984961c 885 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 886 return status;
887}
bf99e50d 888
f2f781a7 889int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 890{
b31c50a7
SP		 891 struct be_mcc_wrb *wrb;
892 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 893 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
894 int status, ver = 0;
6b7c5b94 895
2984961c
IV		 896 if (mutex_lock_interruptible(&adapter->mbox_lock))
897 return -1;
b31c50a7
SP		 898
899 wrb = wrb_from_mbox(adapter);
900 req = embedded_payload(wrb);
6b7c5b94 901
106df1e3 902 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 903 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
904 NULL);
6b7c5b94 905
f2f781a7
SP		 906 /* Support for EQ_CREATEv2 available only SH-R onwards */
907 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
908 ver = 2;
909
910 req->hdr.version = ver;
6b7c5b94
SP		 911 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
912
6b7c5b94
SP		 913 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
914 /* 4byte eqe*/
915 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
916 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 917 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 918 be_dws_cpu_to_le(req->context, sizeof(req->context));
919
920 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
921
b31c50a7 922 status = be_mbox_notify_wait(adapter);
6b7c5b94 923 if (!status) {
b31c50a7 924 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
f2f781a7
SP		 925 eqo->q.id = le16_to_cpu(resp->eq_id);
926 eqo->msix_idx =
927 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
928 eqo->q.created = true;
6b7c5b94 929 }
b31c50a7 930
2984961c 931 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 932 return status;
933}
934
f9449ab7 935/* Use MCC */
8788fdc2 936int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 937 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 938{
b31c50a7
SP		 939 struct be_mcc_wrb *wrb;
940 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 941 int status;
942
f9449ab7 943 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 944
f9449ab7
SP		 945 wrb = wrb_from_mccq(adapter);
946 if (!wrb) {
947 status = -EBUSY;
948 goto err;
949 }
b31c50a7 950 req = embedded_payload(wrb);
6b7c5b94 951
106df1e3 952 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 953 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
954 NULL);
5ee4979b 955 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 956 if (permanent) {
957 req->permanent = 1;
958 } else {
b31c50a7 959 req->if_id = cpu_to_le16((u16) if_handle);
590c391d 960 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 961 req->permanent = 0;
962 }
963
f9449ab7 964 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 965 if (!status) {
966 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
6b7c5b94 967 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 968 }
6b7c5b94 969
f9449ab7
SP		 970err:
971 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 972 return status;
973}
974
b31c50a7 975/* Uses synchronous MCCQ */
8788fdc2 976int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 977 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 978{
b31c50a7
SP		 979 struct be_mcc_wrb *wrb;
980 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 981 int status;
982
b31c50a7
SP		 983 spin_lock_bh(&adapter->mcc_lock);
984
985 wrb = wrb_from_mccq(adapter);
713d0394
SP		 986 if (!wrb) {
987 status = -EBUSY;
988 goto err;
989 }
b31c50a7 990 req = embedded_payload(wrb);
6b7c5b94 991
106df1e3 992 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 993 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
994 NULL);
6b7c5b94 995
f8617e08 996 req->hdr.domain = domain;
6b7c5b94
SP		 997 req->if_id = cpu_to_le32(if_id);
998 memcpy(req->mac_address, mac_addr, ETH_ALEN);
999
b31c50a7 1000 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1001 if (!status) {
1002 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1003 *pmac_id = le32_to_cpu(resp->pmac_id);
1004 }
1005
713d0394 1006err:
b31c50a7 1007 spin_unlock_bh(&adapter->mcc_lock);
e3a7ae2c
SK		 1008
1009 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1010 status = -EPERM;
1011
6b7c5b94
SP		 1012 return status;
1013}
1014
b31c50a7 1015/* Uses synchronous MCCQ */
30128031 1016int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1017{
b31c50a7
SP		 1018 struct be_mcc_wrb *wrb;
1019 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1020 int status;
1021
30128031
SP		 1022 if (pmac_id == -1)
1023 return 0;
1024
b31c50a7
SP		 1025 spin_lock_bh(&adapter->mcc_lock);
1026
1027 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1028 if (!wrb) {
1029 status = -EBUSY;
1030 goto err;
1031 }
b31c50a7 1032 req = embedded_payload(wrb);
6b7c5b94 1033
106df1e3
SK		 1034 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1035 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
6b7c5b94 1036
f8617e08 1037 req->hdr.domain = dom;
6b7c5b94
SP		 1038 req->if_id = cpu_to_le32(if_id);
1039 req->pmac_id = cpu_to_le32(pmac_id);
1040
b31c50a7
SP		 1041 status = be_mcc_notify_wait(adapter);
1042
713d0394 1043err:
b31c50a7 1044 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1045 return status;
1046}
1047
b31c50a7 1048/* Uses Mbox */
10ef9ab4 1049int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1050 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1051{
b31c50a7
SP		 1052 struct be_mcc_wrb *wrb;
1053 struct be_cmd_req_cq_create *req;
6b7c5b94 1054 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1055 void *ctxt;
6b7c5b94
SP		 1056 int status;
1057
2984961c
IV		 1058 if (mutex_lock_interruptible(&adapter->mbox_lock))
1059 return -1;
b31c50a7
SP		 1060
1061 wrb = wrb_from_mbox(adapter);
1062 req = embedded_payload(wrb);
1063 ctxt = &req->context;
6b7c5b94 1064
106df1e3 1065 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1066 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1067 NULL);
6b7c5b94
SP		 1068
1069 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1070
1071 if (BEx_chip(adapter)) {
fe6d2a38 1072 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1073 coalesce_wm);
fe6d2a38 1074 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1075 ctxt, no_delay);
fe6d2a38 1076 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1077 __ilog2_u32(cq->len / 256));
fe6d2a38 1078 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1079 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1080 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1081 } else {
1082 req->hdr.version = 2;
1083 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1084
1085 /* coalesce-wm field in this cmd is not relevant to Lancer.
1086 * Lancer uses COMMON_MODIFY_CQ to set this field
1087 */
1088 if (!lancer_chip(adapter))
1089 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1090 ctxt, coalesce_wm);
bbdc42f8 1091 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1092 no_delay);
bbdc42f8 1093 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1094 __ilog2_u32(cq->len / 256));
bbdc42f8 1095 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1096 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1097 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1098 }
6b7c5b94 1099
6b7c5b94
SP		 1100 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1101
1102 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1103
b31c50a7 1104 status = be_mbox_notify_wait(adapter);
6b7c5b94 1105 if (!status) {
b31c50a7 1106 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
6b7c5b94
SP		 1107 cq->id = le16_to_cpu(resp->cq_id);
1108 cq->created = true;
1109 }
b31c50a7 1110
2984961c 1111 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1112
1113 return status;
1114}
1115
1116static u32 be_encoded_q_len(int q_len)
1117{
1118 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1119 if (len_encoded == 16)
1120 len_encoded = 0;
1121 return len_encoded;
1122}
1123
4188e7df 1124static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1125 struct be_queue_info *mccq,
1126 struct be_queue_info *cq)
5fb379ee 1127{
b31c50a7 1128 struct be_mcc_wrb *wrb;
34b1ef04 1129 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1130 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1131 void *ctxt;
5fb379ee
SP		 1132 int status;
1133
2984961c
IV		 1134 if (mutex_lock_interruptible(&adapter->mbox_lock))
1135 return -1;
b31c50a7
SP		 1136
1137 wrb = wrb_from_mbox(adapter);
1138 req = embedded_payload(wrb);
1139 ctxt = &req->context;
5fb379ee 1140
106df1e3 1141 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1142 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1143 NULL);
5fb379ee 1144
d4a2ac3e 1145 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1146 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1147 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1148 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1149 be_encoded_q_len(mccq->len));
fe6d2a38 1150 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1151 } else {
1152 req->hdr.version = 1;
1153 req->cq_id = cpu_to_le16(cq->id);
1154
1155 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1156 be_encoded_q_len(mccq->len));
1157 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1158 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1159 ctxt, cq->id);
1160 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1161 ctxt, 1);
fe6d2a38 1162 }
5fb379ee 1163
cc4ce020 1164 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
fe6d2a38 1165 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
bc0c3405 1166 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
5fb379ee
SP		 1167 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1168
1169 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1170
b31c50a7 1171 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1172 if (!status) {
1173 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1174 mccq->id = le16_to_cpu(resp->id);
1175 mccq->created = true;
1176 }
2984961c 1177 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1178
1179 return status;
1180}
1181
4188e7df 1182static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1183 struct be_queue_info *mccq,
1184 struct be_queue_info *cq)
34b1ef04
SK		 1185{
1186 struct be_mcc_wrb *wrb;
1187 struct be_cmd_req_mcc_create *req;
1188 struct be_dma_mem *q_mem = &mccq->dma_mem;
1189 void *ctxt;
1190 int status;
1191
1192 if (mutex_lock_interruptible(&adapter->mbox_lock))
1193 return -1;
1194
1195 wrb = wrb_from_mbox(adapter);
1196 req = embedded_payload(wrb);
1197 ctxt = &req->context;
1198
106df1e3 1199 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1200 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1201 NULL);
34b1ef04
SK		 1202
1203 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1204
1205 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1206 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1207 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1208 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1209
1210 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1211
1212 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1213
1214 status = be_mbox_notify_wait(adapter);
1215 if (!status) {
1216 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1217 mccq->id = le16_to_cpu(resp->id);
1218 mccq->created = true;
1219 }
1220
1221 mutex_unlock(&adapter->mbox_lock);
1222 return status;
1223}
1224
1225int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1226 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1227{
1228 int status;
1229
1230 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1231 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1232 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1233 "or newer to avoid conflicting priorities between NIC "
1234 "and FCoE traffic");
1235 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1236 }
1237 return status;
1238}
1239
94d73aaa 1240int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1241{
7707133c 1242 struct be_mcc_wrb wrb = {0};
b31c50a7 1243 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1244 struct be_queue_info *txq = &txo->q;
1245 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1246 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1247 int status, ver = 0;
6b7c5b94 1248
7707133c 1249 req = embedded_payload(&wrb);
106df1e3 1250 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1251 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1252
8b7756ca
PR		 1253 if (lancer_chip(adapter)) {
1254 req->hdr.version = 1;
94d73aaa
VV		 1255 } else if (BEx_chip(adapter)) {
1256 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1257 req->hdr.version = 2;
1258 } else { /* For SH */
1259 req->hdr.version = 2;
8b7756ca
PR		 1260 }
1261
81b02655
VV		 1262 if (req->hdr.version > 0)
1263 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1264 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1265 req->ulp_num = BE_ULP1_NUM;
1266 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1267 req->cq_id = cpu_to_le16(cq->id);
1268 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1269 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1270 ver = req->hdr.version;
1271
7707133c 1272 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1273 if (!status) {
7707133c 1274 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
6b7c5b94 1275 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1276 if (ver == 2)
1277 txo->db_offset = le32_to_cpu(resp->db_offset);
1278 else
1279 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1280 txq->created = true;
1281 }
b31c50a7 1282
6b7c5b94
SP		 1283 return status;
1284}
1285
482c9e79 1286/* Uses MCC */
8788fdc2 1287int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1288 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1289 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1290{
b31c50a7
SP		 1291 struct be_mcc_wrb *wrb;
1292 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1293 struct be_dma_mem *q_mem = &rxq->dma_mem;
1294 int status;
1295
482c9e79 1296 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1297
482c9e79
SP		 1298 wrb = wrb_from_mccq(adapter);
1299 if (!wrb) {
1300 status = -EBUSY;
1301 goto err;
1302 }
b31c50a7 1303 req = embedded_payload(wrb);
6b7c5b94 1304
106df1e3 1305 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1306 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1307
1308 req->cq_id = cpu_to_le16(cq_id);
1309 req->frag_size = fls(frag_size) - 1;
1310 req->num_pages = 2;
1311 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1312 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1313 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1314 req->rss_queue = cpu_to_le32(rss);
1315
482c9e79 1316 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1317 if (!status) {
1318 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1319 rxq->id = le16_to_cpu(resp->id);
1320 rxq->created = true;
3abcdeda 1321 *rss_id = resp->rss_id;
6b7c5b94 1322 }
b31c50a7 1323
482c9e79
SP		 1324err:
1325 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1326 return status;
1327}
1328
b31c50a7
SP		 1329/* Generic destroyer function for all types of queues
1330 * Uses Mbox
1331 */
8788fdc2 1332int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1333 int queue_type)
6b7c5b94 1334{
b31c50a7
SP		 1335 struct be_mcc_wrb *wrb;
1336 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1337 u8 subsys = 0, opcode = 0;
1338 int status;
1339
2984961c
IV		 1340 if (mutex_lock_interruptible(&adapter->mbox_lock))
1341 return -1;
6b7c5b94 1342
b31c50a7
SP		 1343 wrb = wrb_from_mbox(adapter);
1344 req = embedded_payload(wrb);
1345
6b7c5b94
SP		 1346 switch (queue_type) {
1347 case QTYPE_EQ:
1348 subsys = CMD_SUBSYSTEM_COMMON;
1349 opcode = OPCODE_COMMON_EQ_DESTROY;
1350 break;
1351 case QTYPE_CQ:
1352 subsys = CMD_SUBSYSTEM_COMMON;
1353 opcode = OPCODE_COMMON_CQ_DESTROY;
1354 break;
1355 case QTYPE_TXQ:
1356 subsys = CMD_SUBSYSTEM_ETH;
1357 opcode = OPCODE_ETH_TX_DESTROY;
1358 break;
1359 case QTYPE_RXQ:
1360 subsys = CMD_SUBSYSTEM_ETH;
1361 opcode = OPCODE_ETH_RX_DESTROY;
1362 break;
5fb379ee
SP		 1363 case QTYPE_MCCQ:
1364 subsys = CMD_SUBSYSTEM_COMMON;
1365 opcode = OPCODE_COMMON_MCC_DESTROY;
1366 break;
6b7c5b94 1367 default:
5f0b849e 1368 BUG();
6b7c5b94 1369 }
d744b44e 1370
106df1e3 1371 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1372 NULL);
6b7c5b94
SP		 1373 req->id = cpu_to_le16(q->id);
1374
b31c50a7 1375 status = be_mbox_notify_wait(adapter);
aa790db9 1376 q->created = false;
5f0b849e 1377
2984961c 1378 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1379 return status;
1380}
6b7c5b94 1381
482c9e79
SP		 1382/* Uses MCC */
1383int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1384{
1385 struct be_mcc_wrb *wrb;
1386 struct be_cmd_req_q_destroy *req;
1387 int status;
1388
1389 spin_lock_bh(&adapter->mcc_lock);
1390
1391 wrb = wrb_from_mccq(adapter);
1392 if (!wrb) {
1393 status = -EBUSY;
1394 goto err;
1395 }
1396 req = embedded_payload(wrb);
1397
106df1e3 1398 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1399 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1400 req->id = cpu_to_le16(q->id);
1401
1402 status = be_mcc_notify_wait(adapter);
aa790db9 1403 q->created = false;
482c9e79
SP		 1404
1405err:
1406 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1407 return status;
1408}
1409
b31c50a7 1410/* Create an rx filtering policy configuration on an i/f
bea50988 1411 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1412 */
73d540f2 1413int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1414 u32 *if_handle, u32 domain)
6b7c5b94 1415{
bea50988 1416 struct be_mcc_wrb wrb = {0};
b31c50a7 1417 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1418 int status;
1419
bea50988 1420 req = embedded_payload(&wrb);
106df1e3 1421 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1422 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1423 sizeof(*req), &wrb, NULL);
ba343c77 1424 req->hdr.domain = domain;
73d540f2
SP		 1425 req->capability_flags = cpu_to_le32(cap_flags);
1426 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1427 req->pmac_invalid = true;
6b7c5b94 1428
bea50988 1429 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1430 if (!status) {
bea50988 1431 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
6b7c5b94 1432 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1433
1434 /* Hack to retrieve VF's pmac-id on BE3 */
1435 if (BE3_chip(adapter) && !be_physfn(adapter))
1436 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1437 }
6b7c5b94
SP		 1438 return status;
1439}
1440
f9449ab7 1441/* Uses MCCQ */
30128031 1442int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1443{
b31c50a7
SP		 1444 struct be_mcc_wrb *wrb;
1445 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1446 int status;
1447
30128031 1448 if (interface_id == -1)
f9449ab7 1449 return 0;
b31c50a7 1450
f9449ab7
SP		 1451 spin_lock_bh(&adapter->mcc_lock);
1452
1453 wrb = wrb_from_mccq(adapter);
1454 if (!wrb) {
1455 status = -EBUSY;
1456 goto err;
1457 }
b31c50a7 1458 req = embedded_payload(wrb);
6b7c5b94 1459
106df1e3 1460 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1461 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1462 sizeof(*req), wrb, NULL);
658681f7 1463 req->hdr.domain = domain;
6b7c5b94 1464 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1465
f9449ab7
SP		 1466 status = be_mcc_notify_wait(adapter);
1467err:
1468 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1469 return status;
1470}
1471
1472/* Get stats is a non embedded command: the request is not embedded inside
1473 * WRB but is a separate dma memory block
b31c50a7 1474 * Uses asynchronous MCC
6b7c5b94 1475 */
8788fdc2 1476int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1477{
b31c50a7 1478 struct be_mcc_wrb *wrb;
89a88ab8 1479 struct be_cmd_req_hdr *hdr;
713d0394 1480 int status = 0;
6b7c5b94 1481
b31c50a7 1482 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1483
b31c50a7 1484 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1485 if (!wrb) {
1486 status = -EBUSY;
1487 goto err;
1488 }
89a88ab8 1489 hdr = nonemb_cmd->va;
6b7c5b94 1490
106df1e3 1491 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1492 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1493 nonemb_cmd);
89a88ab8 1494
ca34fe38 1495 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1496 if (BE2_chip(adapter))
1497 hdr->version = 0;
1498 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1499 hdr->version = 1;
61000861
AK		 1500 else
1501 hdr->version = 2;
89a88ab8 1502
b31c50a7 1503 be_mcc_notify(adapter);
b2aebe6d 1504 adapter->stats_cmd_sent = true;
6b7c5b94 1505
713d0394 1506err:
b31c50a7 1507 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1508 return status;
6b7c5b94
SP		 1509}
1510
005d5696
SX		 1511/* Lancer Stats */
1512int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1513 struct be_dma_mem *nonemb_cmd)
005d5696
SX		 1514{
1515
1516 struct be_mcc_wrb *wrb;
1517 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1518 int status = 0;
1519
f25b119c
PR		 1520 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1521 CMD_SUBSYSTEM_ETH))
1522 return -EPERM;
1523
005d5696
SX		 1524 spin_lock_bh(&adapter->mcc_lock);
1525
1526 wrb = wrb_from_mccq(adapter);
1527 if (!wrb) {
1528 status = -EBUSY;
1529 goto err;
1530 }
1531 req = nonemb_cmd->va;
005d5696 1532
106df1e3 1533 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1534 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1535 wrb, nonemb_cmd);
005d5696 1536
d51ebd33 1537 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1538 req->cmd_params.params.reset_stats = 0;
1539
005d5696
SX		 1540 be_mcc_notify(adapter);
1541 adapter->stats_cmd_sent = true;
1542
1543err:
1544 spin_unlock_bh(&adapter->mcc_lock);
1545 return status;
1546}
1547
323ff71e
SP		 1548static int be_mac_to_link_speed(int mac_speed)
1549{
1550 switch (mac_speed) {
1551 case PHY_LINK_SPEED_ZERO:
1552 return 0;
1553 case PHY_LINK_SPEED_10MBPS:
1554 return 10;
1555 case PHY_LINK_SPEED_100MBPS:
1556 return 100;
1557 case PHY_LINK_SPEED_1GBPS:
1558 return 1000;
1559 case PHY_LINK_SPEED_10GBPS:
1560 return 10000;
b971f847
VV		 1561 case PHY_LINK_SPEED_20GBPS:
1562 return 20000;
1563 case PHY_LINK_SPEED_25GBPS:
1564 return 25000;
1565 case PHY_LINK_SPEED_40GBPS:
1566 return 40000;
323ff71e
SP		 1567 }
1568 return 0;
1569}
1570
1571/* Uses synchronous mcc
1572 * Returns link_speed in Mbps
1573 */
1574int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1575 u8 *link_status, u32 dom)
6b7c5b94 1576{
b31c50a7
SP		 1577 struct be_mcc_wrb *wrb;
1578 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1579 int status;
1580
b31c50a7
SP		 1581 spin_lock_bh(&adapter->mcc_lock);
1582
b236916a
AK		 1583 if (link_status)
1584 *link_status = LINK_DOWN;
1585
b31c50a7 1586 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1587 if (!wrb) {
1588 status = -EBUSY;
1589 goto err;
1590 }
b31c50a7 1591 req = embedded_payload(wrb);
a8f447bd 1592
57cd80d4 1593 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1594 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1595 sizeof(*req), wrb, NULL);
57cd80d4 1596
ca34fe38
SP		 1597 /* version 1 of the cmd is not supported only by BE2 */
1598 if (!BE2_chip(adapter))
daad6167
PR		 1599 req->hdr.version = 1;
1600
57cd80d4 1601 req->hdr.domain = dom;
6b7c5b94 1602
b31c50a7 1603 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1604 if (!status) {
1605 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
323ff71e
SP		 1606 if (link_speed) {
1607 *link_speed = resp->link_speed ?
1608 le16_to_cpu(resp->link_speed) * 10 :
1609 be_mac_to_link_speed(resp->mac_speed);
1610
1611 if (!resp->logical_link_status)
1612 *link_speed = 0;
0388f251 1613 }
b236916a
AK		 1614 if (link_status)
1615 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1616 }
1617
713d0394 1618err:
b31c50a7 1619 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1620 return status;
1621}
1622
609ff3bb
AK		 1623/* Uses synchronous mcc */
1624int be_cmd_get_die_temperature(struct be_adapter *adapter)
1625{
1626 struct be_mcc_wrb *wrb;
1627 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1628 int status = 0;
609ff3bb
AK		 1629
1630 spin_lock_bh(&adapter->mcc_lock);
1631
1632 wrb = wrb_from_mccq(adapter);
1633 if (!wrb) {
1634 status = -EBUSY;
1635 goto err;
1636 }
1637 req = embedded_payload(wrb);
1638
106df1e3 1639 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1640 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1641 sizeof(*req), wrb, NULL);
609ff3bb 1642
3de09455 1643 be_mcc_notify(adapter);
609ff3bb
AK		 1644
1645err:
1646 spin_unlock_bh(&adapter->mcc_lock);
1647 return status;
1648}
1649
311fddc7
SK		 1650/* Uses synchronous mcc */
1651int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1652{
1653 struct be_mcc_wrb *wrb;
1654 struct be_cmd_req_get_fat *req;
1655 int status;
1656
1657 spin_lock_bh(&adapter->mcc_lock);
1658
1659 wrb = wrb_from_mccq(adapter);
1660 if (!wrb) {
1661 status = -EBUSY;
1662 goto err;
1663 }
1664 req = embedded_payload(wrb);
1665
106df1e3 1666 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1667 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1668 NULL);
311fddc7
SK		 1669 req->fat_operation = cpu_to_le32(QUERY_FAT);
1670 status = be_mcc_notify_wait(adapter);
1671 if (!status) {
1672 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1673 if (log_size && resp->log_size)
fe2a70ee
SK		 1674 *log_size = le32_to_cpu(resp->log_size) -
1675 sizeof(u32);
311fddc7
SK		 1676 }
1677err:
1678 spin_unlock_bh(&adapter->mcc_lock);
1679 return status;
1680}
1681
c5f156de 1682int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1683{
1684 struct be_dma_mem get_fat_cmd;
1685 struct be_mcc_wrb *wrb;
1686 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1687 u32 offset = 0, total_size, buf_size,
1688 log_offset = sizeof(u32), payload_len;
c5f156de 1689 int status = 0;
311fddc7
SK		 1690
1691 if (buf_len == 0)
c5f156de 1692 return -EIO;
311fddc7
SK		 1693
1694 total_size = buf_len;
1695
fe2a70ee
SK		 1696 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1697 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 1698 get_fat_cmd.size,
1699 &get_fat_cmd.dma);
fe2a70ee 1700 if (!get_fat_cmd.va) {
fe2a70ee
SK		 1701 dev_err(&adapter->pdev->dev,
1702 "Memory allocation failure while retrieving FAT data\n");
c5f156de 1703 return -ENOMEM;
fe2a70ee
SK		 1704 }
1705
311fddc7
SK		 1706 spin_lock_bh(&adapter->mcc_lock);
1707
311fddc7
SK		 1708 while (total_size) {
1709 buf_size = min(total_size, (u32)60*1024);
1710 total_size -= buf_size;
1711
fe2a70ee
SK		 1712 wrb = wrb_from_mccq(adapter);
1713 if (!wrb) {
1714 status = -EBUSY;
311fddc7
SK		 1715 goto err;
1716 }
1717 req = get_fat_cmd.va;
311fddc7 1718
fe2a70ee 1719 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1720 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1721 OPCODE_COMMON_MANAGE_FAT, payload_len,
1722 wrb, &get_fat_cmd);
311fddc7
SK		 1723
1724 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1725 req->read_log_offset = cpu_to_le32(log_offset);
1726 req->read_log_length = cpu_to_le32(buf_size);
1727 req->data_buffer_size = cpu_to_le32(buf_size);
1728
1729 status = be_mcc_notify_wait(adapter);
1730 if (!status) {
1731 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1732 memcpy(buf + offset,
a2cc4e0b
SP		 1733 resp->data_buffer,
1734 le32_to_cpu(resp->read_log_length));
fe2a70ee 1735 } else {
311fddc7 1736 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1737 goto err;
1738 }
311fddc7
SK		 1739 offset += buf_size;
1740 log_offset += buf_size;
1741 }
1742err:
fe2a70ee 1743 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
a2cc4e0b 1744 get_fat_cmd.va, get_fat_cmd.dma);
311fddc7 1745 spin_unlock_bh(&adapter->mcc_lock);
c5f156de 1746 return status;
311fddc7
SK		 1747}
1748
04b71175 1749/* Uses synchronous mcc */
e97e3cda 1750int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1751{
b31c50a7
SP		 1752 struct be_mcc_wrb *wrb;
1753 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1754 int status;
1755
04b71175 1756 spin_lock_bh(&adapter->mcc_lock);
b31c50a7 1757
04b71175
SP		 1758 wrb = wrb_from_mccq(adapter);
1759 if (!wrb) {
1760 status = -EBUSY;
1761 goto err;
1762 }
6b7c5b94 1763
04b71175 1764 req = embedded_payload(wrb);
6b7c5b94 1765
106df1e3 1766 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1767 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1768 NULL);
04b71175 1769 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1770 if (!status) {
1771 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1772
242eb470
VV		 1773 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1774 sizeof(adapter->fw_ver));
1775 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1776 sizeof(adapter->fw_on_flash));
6b7c5b94 1777 }
04b71175
SP		 1778err:
1779 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1780 return status;
1781}
1782
b31c50a7
SP		 1783/* set the EQ delay interval of an EQ to specified value
1784 * Uses async mcc
1785 */
2632bafd
SP		 1786int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1787 int num)
6b7c5b94 1788{
b31c50a7
SP		 1789 struct be_mcc_wrb *wrb;
1790 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1791 int status = 0, i;
6b7c5b94 1792
b31c50a7
SP		 1793 spin_lock_bh(&adapter->mcc_lock);
1794
1795 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1796 if (!wrb) {
1797 status = -EBUSY;
1798 goto err;
1799 }
b31c50a7 1800 req = embedded_payload(wrb);
6b7c5b94 1801
106df1e3 1802 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1803 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1804 NULL);
6b7c5b94 1805
2632bafd
SP		 1806 req->num_eq = cpu_to_le32(num);
1807 for (i = 0; i < num; i++) {
1808 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1809 req->set_eqd[i].phase = 0;
1810 req->set_eqd[i].delay_multiplier =
1811 cpu_to_le32(set_eqd[i].delay_multiplier);
1812 }
6b7c5b94 1813
b31c50a7 1814 be_mcc_notify(adapter);
713d0394 1815err:
b31c50a7 1816 spin_unlock_bh(&adapter->mcc_lock);
713d0394 1817 return status;
6b7c5b94
SP		 1818}
1819
b31c50a7 1820/* Uses sycnhronous mcc */
8788fdc2 1821int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
4d567d97 1822 u32 num)
6b7c5b94 1823{
b31c50a7
SP		 1824 struct be_mcc_wrb *wrb;
1825 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1826 int status;
1827
b31c50a7
SP		 1828 spin_lock_bh(&adapter->mcc_lock);
1829
1830 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1831 if (!wrb) {
1832 status = -EBUSY;
1833 goto err;
1834 }
b31c50a7 1835 req = embedded_payload(wrb);
6b7c5b94 1836
106df1e3 1837 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1838 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1839 wrb, NULL);
6b7c5b94
SP		 1840
1841 req->interface_id = if_id;
012bd387 1842 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1843 req->num_vlan = num;
4d567d97
KA		 1844 memcpy(req->normal_vlan, vtag_array,
1845 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1846
b31c50a7 1847 status = be_mcc_notify_wait(adapter);
713d0394 1848err:
b31c50a7 1849 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 1850 return status;
1851}
1852
5b8821b7 1853int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1854{
6ac7b687 1855 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1856 struct be_dma_mem *mem = &adapter->rx_filter;
1857 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1858 int status;
6b7c5b94 1859
8788fdc2 1860 spin_lock_bh(&adapter->mcc_lock);
6ac7b687 1861
b31c50a7 1862 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1863 if (!wrb) {
1864 status = -EBUSY;
1865 goto err;
1866 }
5b8821b7 1867 memset(req, 0, sizeof(*req));
106df1e3 1868 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1869 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1870 wrb, mem);
6b7c5b94 1871
5b8821b7
SP		 1872 req->if_id = cpu_to_le32(adapter->if_handle);
1873 if (flags & IFF_PROMISC) {
1874 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
a2cc4e0b
SP		 1875 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1876 BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7 1877 if (value == ON)
a2cc4e0b
SP		 1878 req->if_flags =
1879 cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1880 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1881 BE_IF_FLAGS_MCAST_PROMISCUOUS);
5b8821b7
SP		 1882 } else if (flags & IFF_ALLMULTI) {
1883 req->if_flags_mask = req->if_flags =
8e7d3f68 1884 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
d9d604f8
AK		 1885 } else if (flags & BE_FLAGS_VLAN_PROMISC) {
1886 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1887
1888 if (value == ON)
1889 req->if_flags =
1890 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
5b8821b7 1891 } else {
22bedad3 1892 struct netdev_hw_addr *ha;
5b8821b7 1893 int i = 0;
24307eef 1894
8e7d3f68
SP		 1895 req->if_flags_mask = req->if_flags =
1896 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1610c79f
PR		 1897
1898 /* Reset mcast promisc mode if already set by setting mask
1899 * and not setting flags field
1900 */
abb93951
PR		 1901 req->if_flags_mask |=
1902 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 1903 be_if_cap_flags(adapter));
016f97b1 1904 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
5b8821b7
SP		 1905 netdev_for_each_mc_addr(ha, adapter->netdev)
1906 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
6b7c5b94
SP		 1907 }
1908
012bd387 1909 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) !=
a2cc4e0b 1910 req->if_flags_mask) {
012bd387
AK		 1911 dev_warn(&adapter->pdev->dev,
1912 "Cannot set rx filter flags 0x%x\n",
1913 req->if_flags_mask);
1914 dev_warn(&adapter->pdev->dev,
1915 "Interface is capable of 0x%x flags only\n",
1916 be_if_cap_flags(adapter));
1917 }
1918 req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter));
1919
0d1d5875 1920 status = be_mcc_notify_wait(adapter);
012bd387 1921
713d0394 1922err:
8788fdc2 1923 spin_unlock_bh(&adapter->mcc_lock);
e7b909a6 1924 return status;
6b7c5b94
SP		 1925}
1926
b31c50a7 1927/* Uses synchrounous mcc */
8788fdc2 1928int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 1929{
b31c50a7
SP		 1930 struct be_mcc_wrb *wrb;
1931 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 1932 int status;
1933
f25b119c
PR		 1934 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1935 CMD_SUBSYSTEM_COMMON))
1936 return -EPERM;
1937
b31c50a7 1938 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1939
b31c50a7 1940 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1941 if (!wrb) {
1942 status = -EBUSY;
1943 goto err;
1944 }
b31c50a7 1945 req = embedded_payload(wrb);
6b7c5b94 1946
106df1e3 1947 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1948 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
1949 wrb, NULL);
6b7c5b94 1950
b29812c1 1951 req->hdr.version = 1;
6b7c5b94
SP		 1952 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1953 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1954
b31c50a7 1955 status = be_mcc_notify_wait(adapter);
6b7c5b94 1956
713d0394 1957err:
b31c50a7 1958 spin_unlock_bh(&adapter->mcc_lock);
b29812c1
SR		 1959
1960 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
1961 return -EOPNOTSUPP;
1962
6b7c5b94
SP		 1963 return status;
1964}
1965
b31c50a7 1966/* Uses sycn mcc */
8788fdc2 1967int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 1968{
b31c50a7
SP		 1969 struct be_mcc_wrb *wrb;
1970 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 1971 int status;
1972
f25b119c
PR		 1973 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1974 CMD_SUBSYSTEM_COMMON))
1975 return -EPERM;
1976
b31c50a7 1977 spin_lock_bh(&adapter->mcc_lock);
6b7c5b94 1978
b31c50a7 1979 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1980 if (!wrb) {
1981 status = -EBUSY;
1982 goto err;
1983 }
b31c50a7 1984 req = embedded_payload(wrb);
6b7c5b94 1985
106df1e3 1986 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1987 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
1988 wrb, NULL);
6b7c5b94 1989
b31c50a7 1990 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1991 if (!status) {
1992 struct be_cmd_resp_get_flow_control *resp =
1993 embedded_payload(wrb);
1994 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1995 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1996 }
1997
713d0394 1998err:
b31c50a7 1999 spin_unlock_bh(&adapter->mcc_lock);
6b7c5b94
SP		 2000 return status;
2001}
2002
b31c50a7 2003/* Uses mbox */
e97e3cda 2004int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2005{
b31c50a7
SP		 2006 struct be_mcc_wrb *wrb;
2007 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2008 int status;
2009
2984961c
IV		 2010 if (mutex_lock_interruptible(&adapter->mbox_lock))
2011 return -1;
6b7c5b94 2012
b31c50a7
SP		 2013 wrb = wrb_from_mbox(adapter);
2014 req = embedded_payload(wrb);
6b7c5b94 2015
106df1e3 2016 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2017 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2018 sizeof(*req), wrb, NULL);
6b7c5b94 2019
b31c50a7 2020 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2021 if (!status) {
2022 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
e97e3cda
KA		 2023 adapter->port_num = le32_to_cpu(resp->phys_port);
2024 adapter->function_mode = le32_to_cpu(resp->function_mode);
2025 adapter->function_caps = le32_to_cpu(resp->function_caps);
2026 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2027 dev_info(&adapter->pdev->dev,
2028 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2029 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2030 }
2031
2984961c 2032 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2033 return status;
2034}
14074eab 2035
b31c50a7 2036/* Uses mbox */
14074eab 2037int be_cmd_reset_function(struct be_adapter *adapter)
2038{
b31c50a7
SP		 2039 struct be_mcc_wrb *wrb;
2040 struct be_cmd_req_hdr *req;
14074eab 2041 int status;
2042
bf99e50d
PR		 2043 if (lancer_chip(adapter)) {
2044 status = lancer_wait_ready(adapter);
2045 if (!status) {
2046 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2047 adapter->db + SLIPORT_CONTROL_OFFSET);
2048 status = lancer_test_and_set_rdy_state(adapter);
2049 }
2050 if (status) {
2051 dev_err(&adapter->pdev->dev,
2052 "Adapter in non recoverable error\n");
2053 }
2054 return status;
2055 }
2056
2984961c
IV		 2057 if (mutex_lock_interruptible(&adapter->mbox_lock))
2058 return -1;
14074eab 2059
b31c50a7
SP		 2060 wrb = wrb_from_mbox(adapter);
2061 req = embedded_payload(wrb);
14074eab 2062
106df1e3 2063 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2064 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2065 NULL);
14074eab 2066
b31c50a7 2067 status = be_mbox_notify_wait(adapter);
14074eab 2068
2984961c 2069 mutex_unlock(&adapter->mbox_lock);
14074eab 2070 return status;
2071}
84517482 2072
594ad54a 2073int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2074 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2075{
2076 struct be_mcc_wrb *wrb;
2077 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2078 int status;
2079
da1388d6
VV		 2080 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2081 return 0;
2082
b51aa367 2083 spin_lock_bh(&adapter->mcc_lock);
3abcdeda 2084
b51aa367
KA		 2085 wrb = wrb_from_mccq(adapter);
2086 if (!wrb) {
2087 status = -EBUSY;
2088 goto err;
2089 }
3abcdeda
SP		 2090 req = embedded_payload(wrb);
2091
106df1e3 2092 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2093 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2094
2095 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2096 req->enable_rss = cpu_to_le16(rss_hash_opts);
2097 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2098
b51aa367 2099 if (!BEx_chip(adapter))
d3bd3a5e 2100 req->hdr.version = 1;
d3bd3a5e 2101
3abcdeda 2102 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2103 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2104 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2105
b51aa367
KA		 2106 status = be_mcc_notify_wait(adapter);
2107err:
2108 spin_unlock_bh(&adapter->mcc_lock);
3abcdeda
SP		 2109 return status;
2110}
2111
fad9ab2c
SB		 2112/* Uses sync mcc */
2113int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2114 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2115{
2116 struct be_mcc_wrb *wrb;
2117 struct be_cmd_req_enable_disable_beacon *req;
2118 int status;
2119
2120 spin_lock_bh(&adapter->mcc_lock);
2121
2122 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2123 if (!wrb) {
2124 status = -EBUSY;
2125 goto err;
2126 }
fad9ab2c
SB		 2127 req = embedded_payload(wrb);
2128
106df1e3 2129 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2130 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2131 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2132
2133 req->port_num = port_num;
2134 req->beacon_state = state;
2135 req->beacon_duration = bcn;
2136 req->status_duration = sts;
2137
2138 status = be_mcc_notify_wait(adapter);
2139
713d0394 2140err:
fad9ab2c
SB		 2141 spin_unlock_bh(&adapter->mcc_lock);
2142 return status;
2143}
2144
2145/* Uses sync mcc */
2146int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2147{
2148 struct be_mcc_wrb *wrb;
2149 struct be_cmd_req_get_beacon_state *req;
2150 int status;
2151
2152 spin_lock_bh(&adapter->mcc_lock);
2153
2154 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2155 if (!wrb) {
2156 status = -EBUSY;
2157 goto err;
2158 }
fad9ab2c
SB		 2159 req = embedded_payload(wrb);
2160
106df1e3 2161 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2162 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2163 wrb, NULL);
fad9ab2c
SB		 2164
2165 req->port_num = port_num;
2166
2167 status = be_mcc_notify_wait(adapter);
2168 if (!status) {
2169 struct be_cmd_resp_get_beacon_state *resp =
2170 embedded_payload(wrb);
2171 *state = resp->beacon_state;
2172 }
2173
713d0394 2174err:
fad9ab2c
SB		 2175 spin_unlock_bh(&adapter->mcc_lock);
2176 return status;
2177}
2178
e36edd9d
ML		 2179/* Uses sync mcc */
2180int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2181 u8 page_num, u8 *data)
2182{
2183 struct be_dma_mem cmd;
2184 struct be_mcc_wrb *wrb;
2185 struct be_cmd_req_port_type *req;
2186 int status;
2187
2188 if (page_num > TR_PAGE_A2)
2189 return -EINVAL;
2190
2191 cmd.size = sizeof(struct be_cmd_resp_port_type);
2192 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2193 if (!cmd.va) {
2194 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2195 return -ENOMEM;
2196 }
2197 memset(cmd.va, 0, cmd.size);
2198
2199 spin_lock_bh(&adapter->mcc_lock);
2200
2201 wrb = wrb_from_mccq(adapter);
2202 if (!wrb) {
2203 status = -EBUSY;
2204 goto err;
2205 }
2206 req = cmd.va;
2207
2208 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2209 OPCODE_COMMON_READ_TRANSRECV_DATA,
2210 cmd.size, wrb, &cmd);
2211
2212 req->port = cpu_to_le32(adapter->hba_port_num);
2213 req->page_num = cpu_to_le32(page_num);
2214 status = be_mcc_notify_wait(adapter);
2215 if (!status) {
2216 struct be_cmd_resp_port_type *resp = cmd.va;
2217
2218 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2219 }
2220err:
2221 spin_unlock_bh(&adapter->mcc_lock);
2222 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2223 return status;
2224}
2225
485bf569 2226int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
f67ef7ba
PR		 2227 u32 data_size, u32 data_offset,
2228 const char *obj_name, u32 *data_written,
2229 u8 *change_status, u8 *addn_status)
485bf569
SN		 2230{
2231 struct be_mcc_wrb *wrb;
2232 struct lancer_cmd_req_write_object *req;
2233 struct lancer_cmd_resp_write_object *resp;
2234 void *ctxt = NULL;
2235 int status;
2236
2237 spin_lock_bh(&adapter->mcc_lock);
2238 adapter->flash_status = 0;
2239
2240 wrb = wrb_from_mccq(adapter);
2241 if (!wrb) {
2242 status = -EBUSY;
2243 goto err_unlock;
2244 }
2245
2246 req = embedded_payload(wrb);
2247
106df1e3 2248 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2249 OPCODE_COMMON_WRITE_OBJECT,
2250 sizeof(struct lancer_cmd_req_write_object), wrb,
2251 NULL);
485bf569
SN		 2252
2253 ctxt = &req->context;
2254 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2255 write_length, ctxt, data_size);
485bf569
SN		 2256
2257 if (data_size == 0)
2258 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2259 eof, ctxt, 1);
485bf569
SN		 2260 else
2261 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2262 eof, ctxt, 0);
485bf569
SN		 2263
2264 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2265 req->write_offset = cpu_to_le32(data_offset);
242eb470 2266 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2267 req->descriptor_count = cpu_to_le32(1);
2268 req->buf_len = cpu_to_le32(data_size);
2269 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2270 sizeof(struct lancer_cmd_req_write_object))
2271 & 0xFFFFFFFF);
485bf569
SN		 2272 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2273 sizeof(struct lancer_cmd_req_write_object)));
2274
2275 be_mcc_notify(adapter);
2276 spin_unlock_bh(&adapter->mcc_lock);
2277
5eeff635 2278 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2279 msecs_to_jiffies(60000)))
fd45160c 2280 status = -ETIMEDOUT;
485bf569
SN		 2281 else
2282 status = adapter->flash_status;
2283
2284 resp = embedded_payload(wrb);
f67ef7ba 2285 if (!status) {
485bf569 2286 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2287 *change_status = resp->change_status;
2288 } else {
485bf569 2289 *addn_status = resp->additional_status;
f67ef7ba 2290 }
485bf569
SN		 2291
2292 return status;
2293
2294err_unlock:
2295 spin_unlock_bh(&adapter->mcc_lock);
2296 return status;
2297}
2298
f0613380
KA		 2299int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2300{
2301 struct lancer_cmd_req_delete_object *req;
2302 struct be_mcc_wrb *wrb;
2303 int status;
2304
2305 spin_lock_bh(&adapter->mcc_lock);
2306
2307 wrb = wrb_from_mccq(adapter);
2308 if (!wrb) {
2309 status = -EBUSY;
2310 goto err;
2311 }
2312
2313 req = embedded_payload(wrb);
2314
2315 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2316 OPCODE_COMMON_DELETE_OBJECT,
2317 sizeof(*req), wrb, NULL);
2318
242eb470 2319 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2320
2321 status = be_mcc_notify_wait(adapter);
2322err:
2323 spin_unlock_bh(&adapter->mcc_lock);
2324 return status;
2325}
2326
de49bd5a 2327int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2328 u32 data_size, u32 data_offset, const char *obj_name,
2329 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2330{
2331 struct be_mcc_wrb *wrb;
2332 struct lancer_cmd_req_read_object *req;
2333 struct lancer_cmd_resp_read_object *resp;
2334 int status;
2335
2336 spin_lock_bh(&adapter->mcc_lock);
2337
2338 wrb = wrb_from_mccq(adapter);
2339 if (!wrb) {
2340 status = -EBUSY;
2341 goto err_unlock;
2342 }
2343
2344 req = embedded_payload(wrb);
2345
2346 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2347 OPCODE_COMMON_READ_OBJECT,
2348 sizeof(struct lancer_cmd_req_read_object), wrb,
2349 NULL);
de49bd5a
PR		 2350
2351 req->desired_read_len = cpu_to_le32(data_size);
2352 req->read_offset = cpu_to_le32(data_offset);
2353 strcpy(req->object_name, obj_name);
2354 req->descriptor_count = cpu_to_le32(1);
2355 req->buf_len = cpu_to_le32(data_size);
2356 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2357 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2358
2359 status = be_mcc_notify_wait(adapter);
2360
2361 resp = embedded_payload(wrb);
2362 if (!status) {
2363 *data_read = le32_to_cpu(resp->actual_read_len);
2364 *eof = le32_to_cpu(resp->eof);
2365 } else {
2366 *addn_status = resp->additional_status;
2367 }
2368
2369err_unlock:
2370 spin_unlock_bh(&adapter->mcc_lock);
2371 return status;
2372}
2373
84517482 2374int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b 2375 u32 flash_type, u32 flash_opcode, u32 buf_size)
84517482 2376{
b31c50a7 2377 struct be_mcc_wrb *wrb;
3f0d4560 2378 struct be_cmd_write_flashrom *req;
84517482
AK		 2379 int status;
2380
b31c50a7 2381 spin_lock_bh(&adapter->mcc_lock);
dd131e76 2382 adapter->flash_status = 0;
b31c50a7
SP		 2383
2384 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2385 if (!wrb) {
2386 status = -EBUSY;
2892d9c2 2387 goto err_unlock;
713d0394
SP		 2388 }
2389 req = cmd->va;
84517482 2390
106df1e3 2391 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2392 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2393 cmd);
84517482
AK		 2394
2395 req->params.op_type = cpu_to_le32(flash_type);
2396 req->params.op_code = cpu_to_le32(flash_opcode);
2397 req->params.data_buf_size = cpu_to_le32(buf_size);
2398
dd131e76
SB		 2399 be_mcc_notify(adapter);
2400 spin_unlock_bh(&adapter->mcc_lock);
2401
5eeff635
SR		 2402 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2403 msecs_to_jiffies(40000)))
fd45160c 2404 status = -ETIMEDOUT;
dd131e76
SB		 2405 else
2406 status = adapter->flash_status;
84517482 2407
2892d9c2
DC		 2408 return status;
2409
2410err_unlock:
2411 spin_unlock_bh(&adapter->mcc_lock);
84517482
AK		 2412 return status;
2413}
fa9a6fed 2414
3f0d4560 2415int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
96c9b2e4 2416 u16 optype, int offset)
fa9a6fed
SB		 2417{
2418 struct be_mcc_wrb *wrb;
be716446 2419 struct be_cmd_read_flash_crc *req;
fa9a6fed
SB		 2420 int status;
2421
2422 spin_lock_bh(&adapter->mcc_lock);
2423
2424 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2425 if (!wrb) {
2426 status = -EBUSY;
2427 goto err;
2428 }
fa9a6fed
SB		 2429 req = embedded_payload(wrb);
2430
106df1e3 2431 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2432 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2433 wrb, NULL);
fa9a6fed 2434
96c9b2e4 2435 req->params.op_type = cpu_to_le32(optype);
fa9a6fed 2436 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710
AK		 2437 req->params.offset = cpu_to_le32(offset);
2438 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2439
2440 status = be_mcc_notify_wait(adapter);
2441 if (!status)
be716446 2442 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2443
713d0394 2444err:
fa9a6fed
SB		 2445 spin_unlock_bh(&adapter->mcc_lock);
2446 return status;
2447}
71d8d1b5 2448
c196b02c 2449int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 2450 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 2451{
2452 struct be_mcc_wrb *wrb;
2453 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 2454 int status;
2455
2456 spin_lock_bh(&adapter->mcc_lock);
2457
2458 wrb = wrb_from_mccq(adapter);
2459 if (!wrb) {
2460 status = -EBUSY;
2461 goto err;
2462 }
2463 req = nonemb_cmd->va;
71d8d1b5 2464
106df1e3 2465 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 2466 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2467 wrb, nonemb_cmd);
71d8d1b5
AK		 2468 memcpy(req->magic_mac, mac, ETH_ALEN);
2469
71d8d1b5
AK		 2470 status = be_mcc_notify_wait(adapter);
2471
2472err:
2473 spin_unlock_bh(&adapter->mcc_lock);
2474 return status;
2475}
ff33a6e2 2476
fced9999
SB		 2477int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2478 u8 loopback_type, u8 enable)
2479{
2480 struct be_mcc_wrb *wrb;
2481 struct be_cmd_req_set_lmode *req;
2482 int status;
2483
2484 spin_lock_bh(&adapter->mcc_lock);
2485
2486 wrb = wrb_from_mccq(adapter);
2487 if (!wrb) {
2488 status = -EBUSY;
2489 goto err;
2490 }
2491
2492 req = embedded_payload(wrb);
2493
106df1e3 2494 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2495 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2496 wrb, NULL);
fced9999
SB		 2497
2498 req->src_port = port_num;
2499 req->dest_port = port_num;
2500 req->loopback_type = loopback_type;
2501 req->loopback_state = enable;
2502
2503 status = be_mcc_notify_wait(adapter);
2504err:
2505 spin_unlock_bh(&adapter->mcc_lock);
2506 return status;
2507}
2508
ff33a6e2 2509int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 2510 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2511 u64 pattern)
ff33a6e2
S		 2512{
2513 struct be_mcc_wrb *wrb;
2514 struct be_cmd_req_loopback_test *req;
5eeff635 2515 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 2516 int status;
2517
2518 spin_lock_bh(&adapter->mcc_lock);
2519
2520 wrb = wrb_from_mccq(adapter);
2521 if (!wrb) {
2522 status = -EBUSY;
2523 goto err;
2524 }
2525
2526 req = embedded_payload(wrb);
2527
106df1e3 2528 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2529 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2530 NULL);
ff33a6e2 2531
5eeff635 2532 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 2533 req->pattern = cpu_to_le64(pattern);
2534 req->src_port = cpu_to_le32(port_num);
2535 req->dest_port = cpu_to_le32(port_num);
2536 req->pkt_size = cpu_to_le32(pkt_size);
2537 req->num_pkts = cpu_to_le32(num_pkts);
2538 req->loopback_type = cpu_to_le32(loopback_type);
2539
5eeff635
SR		 2540 be_mcc_notify(adapter);
2541
2542 spin_unlock_bh(&adapter->mcc_lock);
ff33a6e2 2543
5eeff635
SR		 2544 wait_for_completion(&adapter->et_cmd_compl);
2545 resp = embedded_payload(wrb);
2546 status = le32_to_cpu(resp->status);
2547
2548 return status;
ff33a6e2
S		 2549err:
2550 spin_unlock_bh(&adapter->mcc_lock);
2551 return status;
2552}
2553
2554int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 2555 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 2556{
2557 struct be_mcc_wrb *wrb;
2558 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 2559 int status;
2560 int i, j = 0;
2561
2562 spin_lock_bh(&adapter->mcc_lock);
2563
2564 wrb = wrb_from_mccq(adapter);
2565 if (!wrb) {
2566 status = -EBUSY;
2567 goto err;
2568 }
2569 req = cmd->va;
106df1e3 2570 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 2571 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2572 cmd);
ff33a6e2
S		 2573
2574 req->pattern = cpu_to_le64(pattern);
2575 req->byte_count = cpu_to_le32(byte_cnt);
2576 for (i = 0; i < byte_cnt; i++) {
2577 req->snd_buff[i] = (u8)(pattern >> (j*8));
2578 j++;
2579 if (j > 7)
2580 j = 0;
2581 }
2582
2583 status = be_mcc_notify_wait(adapter);
2584
2585 if (!status) {
2586 struct be_cmd_resp_ddrdma_test *resp;
2587 resp = cmd->va;
2588 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2589 resp->snd_err) {
2590 status = -1;
2591 }
2592 }
2593
2594err:
2595 spin_unlock_bh(&adapter->mcc_lock);
2596 return status;
2597}
368c0ca2 2598
c196b02c 2599int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 2600 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 2601{
2602 struct be_mcc_wrb *wrb;
2603 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 2604 int status;
2605
2606 spin_lock_bh(&adapter->mcc_lock);
2607
2608 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 2609 if (!wrb) {
2610 status = -EBUSY;
2611 goto err;
2612 }
368c0ca2 2613 req = nonemb_cmd->va;
368c0ca2 2614
106df1e3 2615 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2616 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2617 nonemb_cmd);
368c0ca2
SB		 2618
2619 status = be_mcc_notify_wait(adapter);
2620
e45ff01d 2621err:
368c0ca2
SB		 2622 spin_unlock_bh(&adapter->mcc_lock);
2623 return status;
2624}
ee3cb629 2625
42f11cf2 2626int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 2627{
2628 struct be_mcc_wrb *wrb;
2629 struct be_cmd_req_get_phy_info *req;
306f1348 2630 struct be_dma_mem cmd;
ee3cb629
AK		 2631 int status;
2632
f25b119c
PR		 2633 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2634 CMD_SUBSYSTEM_COMMON))
2635 return -EPERM;
2636
ee3cb629
AK		 2637 spin_lock_bh(&adapter->mcc_lock);
2638
2639 wrb = wrb_from_mccq(adapter);
2640 if (!wrb) {
2641 status = -EBUSY;
2642 goto err;
2643 }
306f1348 2644 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
a2cc4e0b 2645 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
306f1348
SP		 2646 if (!cmd.va) {
2647 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2648 status = -ENOMEM;
2649 goto err;
2650 }
ee3cb629 2651
306f1348 2652 req = cmd.va;
ee3cb629 2653
106df1e3 2654 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2655 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2656 wrb, &cmd);
ee3cb629
AK		 2657
2658 status = be_mcc_notify_wait(adapter);
306f1348
SP		 2659 if (!status) {
2660 struct be_phy_info *resp_phy_info =
2661 cmd.va + sizeof(struct be_cmd_req_hdr);
42f11cf2
AK		 2662 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2663 adapter->phy.interface_type =
306f1348 2664 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 2665 adapter->phy.auto_speeds_supported =
2666 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2667 adapter->phy.fixed_speeds_supported =
2668 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2669 adapter->phy.misc_params =
2670 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 2671
2672 if (BE2_chip(adapter)) {
2673 adapter->phy.fixed_speeds_supported =
2674 BE_SUPPORTED_SPEED_10GBPS |
2675 BE_SUPPORTED_SPEED_1GBPS;
2676 }
306f1348 2677 }
a2cc4e0b 2678 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
ee3cb629
AK		 2679err:
2680 spin_unlock_bh(&adapter->mcc_lock);
2681 return status;
2682}
e1d18735
AK		 2683
2684int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2685{
2686 struct be_mcc_wrb *wrb;
2687 struct be_cmd_req_set_qos *req;
2688 int status;
2689
2690 spin_lock_bh(&adapter->mcc_lock);
2691
2692 wrb = wrb_from_mccq(adapter);
2693 if (!wrb) {
2694 status = -EBUSY;
2695 goto err;
2696 }
2697
2698 req = embedded_payload(wrb);
2699
106df1e3 2700 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 2701 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 2702
2703 req->hdr.domain = domain;
6bff57a7
AK		 2704 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2705 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 2706
2707 status = be_mcc_notify_wait(adapter);
2708
2709err:
2710 spin_unlock_bh(&adapter->mcc_lock);
2711 return status;
2712}
9e1453c5
AK		 2713
2714int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2715{
2716 struct be_mcc_wrb *wrb;
2717 struct be_cmd_req_cntl_attribs *req;
2718 struct be_cmd_resp_cntl_attribs *resp;
9e1453c5
AK		 2719 int status;
2720 int payload_len = max(sizeof(*req), sizeof(*resp));
2721 struct mgmt_controller_attrib *attribs;
2722 struct be_dma_mem attribs_cmd;
2723
d98ef50f
SR		 2724 if (mutex_lock_interruptible(&adapter->mbox_lock))
2725 return -1;
2726
9e1453c5
AK		 2727 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2728 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2729 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
a2cc4e0b 2730 &attribs_cmd.dma);
9e1453c5 2731 if (!attribs_cmd.va) {
a2cc4e0b 2732 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 2733 status = -ENOMEM;
2734 goto err;
9e1453c5
AK		 2735 }
2736
9e1453c5
AK		 2737 wrb = wrb_from_mbox(adapter);
2738 if (!wrb) {
2739 status = -EBUSY;
2740 goto err;
2741 }
2742 req = attribs_cmd.va;
9e1453c5 2743
106df1e3 2744 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2745 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2746 wrb, &attribs_cmd);
9e1453c5
AK		 2747
2748 status = be_mbox_notify_wait(adapter);
2749 if (!status) {
43d620c8 2750 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5
AK		 2751 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2752 }
2753
2754err:
2755 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 2756 if (attribs_cmd.va)
2757 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2758 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 2759 return status;
2760}
2e588f84
SP		 2761
2762/* Uses mbox */
2dc1deb6 2763int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 2764{
2765 struct be_mcc_wrb *wrb;
2766 struct be_cmd_req_set_func_cap *req;
2767 int status;
2768
2769 if (mutex_lock_interruptible(&adapter->mbox_lock))
2770 return -1;
2771
2772 wrb = wrb_from_mbox(adapter);
2773 if (!wrb) {
2774 status = -EBUSY;
2775 goto err;
2776 }
2777
2778 req = embedded_payload(wrb);
2779
106df1e3 2780 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2781 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2782 sizeof(*req), wrb, NULL);
2e588f84
SP		 2783
2784 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2785 CAPABILITY_BE3_NATIVE_ERX_API);
2786 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2787
2788 status = be_mbox_notify_wait(adapter);
2789 if (!status) {
2790 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2791 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2792 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 2793 if (!adapter->be3_native)
2794 dev_warn(&adapter->pdev->dev,
2795 "adapter not in advanced mode\n");
2e588f84
SP		 2796 }
2797err:
2798 mutex_unlock(&adapter->mbox_lock);
2799 return status;
2800}
590c391d 2801
f25b119c
PR		 2802/* Get privilege(s) for a function */
2803int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2804 u32 domain)
2805{
2806 struct be_mcc_wrb *wrb;
2807 struct be_cmd_req_get_fn_privileges *req;
2808 int status;
2809
2810 spin_lock_bh(&adapter->mcc_lock);
2811
2812 wrb = wrb_from_mccq(adapter);
2813 if (!wrb) {
2814 status = -EBUSY;
2815 goto err;
2816 }
2817
2818 req = embedded_payload(wrb);
2819
2820 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2821 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2822 wrb, NULL);
2823
2824 req->hdr.domain = domain;
2825
2826 status = be_mcc_notify_wait(adapter);
2827 if (!status) {
2828 struct be_cmd_resp_get_fn_privileges *resp =
2829 embedded_payload(wrb);
2830 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 2831
2832 /* In UMC mode FW does not return right privileges.
2833 * Override with correct privilege equivalent to PF.
2834 */
2835 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2836 be_physfn(adapter))
2837 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 2838 }
2839
2840err:
2841 spin_unlock_bh(&adapter->mcc_lock);
2842 return status;
2843}
2844
04a06028
SP		 2845/* Set privilege(s) for a function */
2846int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2847 u32 domain)
2848{
2849 struct be_mcc_wrb *wrb;
2850 struct be_cmd_req_set_fn_privileges *req;
2851 int status;
2852
2853 spin_lock_bh(&adapter->mcc_lock);
2854
2855 wrb = wrb_from_mccq(adapter);
2856 if (!wrb) {
2857 status = -EBUSY;
2858 goto err;
2859 }
2860
2861 req = embedded_payload(wrb);
2862 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2863 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2864 wrb, NULL);
2865 req->hdr.domain = domain;
2866 if (lancer_chip(adapter))
2867 req->privileges_lancer = cpu_to_le32(privileges);
2868 else
2869 req->privileges = cpu_to_le32(privileges);
2870
2871 status = be_mcc_notify_wait(adapter);
2872err:
2873 spin_unlock_bh(&adapter->mcc_lock);
2874 return status;
2875}
2876
5a712c13
SP		 2877/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2878 * pmac_id_valid: false => pmac_id or MAC address is requested.
2879 * If pmac_id is returned, pmac_id_valid is returned as true
2880 */
1578e777 2881int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 2882 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2883 u8 domain)
590c391d
PR		 2884{
2885 struct be_mcc_wrb *wrb;
2886 struct be_cmd_req_get_mac_list *req;
2887 int status;
2888 int mac_count;
e5e1ee89
PR		 2889 struct be_dma_mem get_mac_list_cmd;
2890 int i;
2891
2892 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2893 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2894 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
a2cc4e0b
SP		 2895 get_mac_list_cmd.size,
2896 &get_mac_list_cmd.dma);
e5e1ee89
PR		 2897
2898 if (!get_mac_list_cmd.va) {
2899 dev_err(&adapter->pdev->dev,
a2cc4e0b 2900 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 2901 return -ENOMEM;
2902 }
590c391d
PR		 2903
2904 spin_lock_bh(&adapter->mcc_lock);
2905
2906 wrb = wrb_from_mccq(adapter);
2907 if (!wrb) {
2908 status = -EBUSY;
e5e1ee89 2909 goto out;
590c391d 2910 }
e5e1ee89
PR		 2911
2912 req = get_mac_list_cmd.va;
590c391d
PR		 2913
2914 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 2915 OPCODE_COMMON_GET_MAC_LIST,
2916 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 2917 req->hdr.domain = domain;
e5e1ee89 2918 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 2919 if (*pmac_id_valid) {
2920 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 2921 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 2922 req->perm_override = 0;
2923 } else {
2924 req->perm_override = 1;
2925 }
590c391d
PR		 2926
2927 status = be_mcc_notify_wait(adapter);
2928 if (!status) {
2929 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 2930 get_mac_list_cmd.va;
5a712c13
SP		 2931
2932 if (*pmac_id_valid) {
2933 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2934 ETH_ALEN);
2935 goto out;
2936 }
2937
e5e1ee89
PR		 2938 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2939 /* Mac list returned could contain one or more active mac_ids
1578e777
PR		 2940 * or one or more true or pseudo permanant mac addresses.
2941 * If an active mac_id is present, return first active mac_id
2942 * found.
e5e1ee89 2943 */
590c391d 2944 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 2945 struct get_list_macaddr *mac_entry;
2946 u16 mac_addr_size;
2947 u32 mac_id;
2948
2949 mac_entry = &resp->macaddr_list[i];
2950 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2951 /* mac_id is a 32 bit value and mac_addr size
2952 * is 6 bytes
2953 */
2954 if (mac_addr_size == sizeof(u32)) {
5a712c13 2955 *pmac_id_valid = true;
e5e1ee89
PR		 2956 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2957 *pmac_id = le32_to_cpu(mac_id);
2958 goto out;
590c391d 2959 }
590c391d 2960 }
1578e777 2961 /* If no active mac_id found, return first mac addr */
5a712c13 2962 *pmac_id_valid = false;
e5e1ee89 2963 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 2964 ETH_ALEN);
590c391d
PR		 2965 }
2966
e5e1ee89 2967out:
590c391d 2968 spin_unlock_bh(&adapter->mcc_lock);
e5e1ee89 2969 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
a2cc4e0b 2970 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 2971 return status;
2972}
2973
a2cc4e0b
SP		 2974int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
2975 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 2976{
5a712c13 2977
b188f090
SR		 2978 if (!active)
2979 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
2980 if_handle, domain);
3175d8c2 2981 if (BEx_chip(adapter))
5a712c13 2982 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 2983 if_handle, curr_pmac_id);
3175d8c2
SP		 2984 else
2985 /* Fetch the MAC address using pmac_id */
2986 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 2987 &curr_pmac_id,
2988 if_handle, domain);
5a712c13
SP		 2989}
2990
95046b92
SP		 2991int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2992{
2993 int status;
2994 bool pmac_valid = false;
2995
2996 memset(mac, 0, ETH_ALEN);
2997
3175d8c2
SP		 2998 if (BEx_chip(adapter)) {
2999 if (be_physfn(adapter))
3000 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3001 0);
3002 else
3003 status = be_cmd_mac_addr_query(adapter, mac, false,
3004 adapter->if_handle, 0);
3005 } else {
95046b92 3006 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3007 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3008 }
3009
95046b92
SP		 3010 return status;
3011}
3012
590c391d
PR		 3013/* Uses synchronous MCCQ */
3014int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3015 u8 mac_count, u32 domain)
3016{
3017 struct be_mcc_wrb *wrb;
3018 struct be_cmd_req_set_mac_list *req;
3019 int status;
3020 struct be_dma_mem cmd;
3021
3022 memset(&cmd, 0, sizeof(struct be_dma_mem));
3023 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3024 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
a2cc4e0b 3025 &cmd.dma, GFP_KERNEL);
d0320f75 3026 if (!cmd.va)
590c391d 3027 return -ENOMEM;
590c391d
PR		 3028
3029 spin_lock_bh(&adapter->mcc_lock);
3030
3031 wrb = wrb_from_mccq(adapter);
3032 if (!wrb) {
3033 status = -EBUSY;
3034 goto err;
3035 }
3036
3037 req = cmd.va;
3038 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3039 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3040 wrb, &cmd);
590c391d
PR		 3041
3042 req->hdr.domain = domain;
3043 req->mac_count = mac_count;
3044 if (mac_count)
3045 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3046
3047 status = be_mcc_notify_wait(adapter);
3048
3049err:
a2cc4e0b 3050 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
590c391d
PR		 3051 spin_unlock_bh(&adapter->mcc_lock);
3052 return status;
3053}
4762f6ce 3054
3175d8c2
SP		 3055/* Wrapper to delete any active MACs and provision the new mac.
3056 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3057 * current list are active.
3058 */
3059int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3060{
3061 bool active_mac = false;
3062 u8 old_mac[ETH_ALEN];
3063 u32 pmac_id;
3064 int status;
3065
3066 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3067 &pmac_id, if_id, dom);
3068
3175d8c2
SP		 3069 if (!status && active_mac)
3070 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3071
3072 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3073}
3074
f1f3ee1b 3075int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
a77dcb8c 3076 u32 domain, u16 intf_id, u16 hsw_mode)
f1f3ee1b
AK		 3077{
3078 struct be_mcc_wrb *wrb;
3079 struct be_cmd_req_set_hsw_config *req;
3080 void *ctxt;
3081 int status;
3082
3083 spin_lock_bh(&adapter->mcc_lock);
3084
3085 wrb = wrb_from_mccq(adapter);
3086 if (!wrb) {
3087 status = -EBUSY;
3088 goto err;
3089 }
3090
3091 req = embedded_payload(wrb);
3092 ctxt = &req->context;
3093
3094 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3095 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3096 NULL);
f1f3ee1b
AK		 3097
3098 req->hdr.domain = domain;
3099 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3100 if (pvid) {
3101 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3102 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3103 }
a77dcb8c
AK		 3104 if (!BEx_chip(adapter) && hsw_mode) {
3105 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3106 ctxt, adapter->hba_port_num);
3107 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3108 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3109 ctxt, hsw_mode);
3110 }
f1f3ee1b
AK		 3111
3112 be_dws_cpu_to_le(req->context, sizeof(req->context));
3113 status = be_mcc_notify_wait(adapter);
3114
3115err:
3116 spin_unlock_bh(&adapter->mcc_lock);
3117 return status;
3118}
3119
3120/* Get Hyper switch config */
3121int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
a77dcb8c 3122 u32 domain, u16 intf_id, u8 *mode)
f1f3ee1b
AK		 3123{
3124 struct be_mcc_wrb *wrb;
3125 struct be_cmd_req_get_hsw_config *req;
3126 void *ctxt;
3127 int status;
3128 u16 vid;
3129
3130 spin_lock_bh(&adapter->mcc_lock);
3131
3132 wrb = wrb_from_mccq(adapter);
3133 if (!wrb) {
3134 status = -EBUSY;
3135 goto err;
3136 }
3137
3138 req = embedded_payload(wrb);
3139 ctxt = &req->context;
3140
3141 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3142 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3143 NULL);
f1f3ee1b
AK		 3144
3145 req->hdr.domain = domain;
a77dcb8c
AK		 3146 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3147 ctxt, intf_id);
f1f3ee1b 3148 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3149
2c07c1d7 3150 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3151 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3152 ctxt, adapter->hba_port_num);
3153 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3154 }
f1f3ee1b
AK		 3155 be_dws_cpu_to_le(req->context, sizeof(req->context));
3156
3157 status = be_mcc_notify_wait(adapter);
3158 if (!status) {
3159 struct be_cmd_resp_get_hsw_config *resp =
3160 embedded_payload(wrb);
a2cc4e0b 3161 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3162 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3163 pvid, &resp->context);
a77dcb8c
AK		 3164 if (pvid)
3165 *pvid = le16_to_cpu(vid);
3166 if (mode)
3167 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3168 port_fwd_type, &resp->context);
f1f3ee1b
AK		 3169 }
3170
3171err:
3172 spin_unlock_bh(&adapter->mcc_lock);
3173 return status;
3174}
3175
4762f6ce
AK		 3176int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3177{
3178 struct be_mcc_wrb *wrb;
3179 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 3180 int status = 0;
4762f6ce
AK		 3181 struct be_dma_mem cmd;
3182
f25b119c
PR		 3183 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3184 CMD_SUBSYSTEM_ETH))
3185 return -EPERM;
3186
76a9e08e
SR		 3187 if (be_is_wol_excluded(adapter))
3188 return status;
3189
d98ef50f
SR		 3190 if (mutex_lock_interruptible(&adapter->mbox_lock))
3191 return -1;
3192
4762f6ce
AK		 3193 memset(&cmd, 0, sizeof(struct be_dma_mem));
3194 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
a2cc4e0b 3195 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
4762f6ce 3196 if (!cmd.va) {
a2cc4e0b 3197 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3198 status = -ENOMEM;
3199 goto err;
4762f6ce
AK		 3200 }
3201
4762f6ce
AK		 3202 wrb = wrb_from_mbox(adapter);
3203 if (!wrb) {
3204 status = -EBUSY;
3205 goto err;
3206 }
3207
3208 req = cmd.va;
3209
3210 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3211 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 3212 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 3213
3214 req->hdr.version = 1;
3215 req->query_options = BE_GET_WOL_CAP;
3216
3217 status = be_mbox_notify_wait(adapter);
3218 if (!status) {
3219 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3220 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
3221
4762f6ce 3222 adapter->wol_cap = resp->wol_settings;
76a9e08e
SR		 3223 if (adapter->wol_cap & BE_WOL_CAP)
3224 adapter->wol_en = true;
4762f6ce
AK		 3225 }
3226err:
3227 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3228 if (cmd.va)
3229 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
4762f6ce 3230 return status;
941a77d5
SK		 3231
3232}
baaa08d1
VV		 3233
3234int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3235{
3236 struct be_dma_mem extfat_cmd;
3237 struct be_fat_conf_params *cfgs;
3238 int status;
3239 int i, j;
3240
3241 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3242 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3243 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3244 &extfat_cmd.dma);
3245 if (!extfat_cmd.va)
3246 return -ENOMEM;
3247
3248 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3249 if (status)
3250 goto err;
3251
3252 cfgs = (struct be_fat_conf_params *)
3253 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3254 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3255 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3256 for (j = 0; j < num_modes; j++) {
3257 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3258 cfgs->module[i].trace_lvl[j].dbg_lvl =
3259 cpu_to_le32(level);
3260 }
3261 }
3262
3263 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3264err:
3265 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3266 extfat_cmd.dma);
3267 return status;
3268}
3269
3270int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3271{
3272 struct be_dma_mem extfat_cmd;
3273 struct be_fat_conf_params *cfgs;
3274 int status, j;
3275 int level = 0;
3276
3277 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3278 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3279 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3280 &extfat_cmd.dma);
3281
3282 if (!extfat_cmd.va) {
3283 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3284 __func__);
3285 goto err;
3286 }
3287
3288 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3289 if (!status) {
3290 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3291 sizeof(struct be_cmd_resp_hdr));
3292 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3293 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3294 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3295 }
3296 }
3297 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3298 extfat_cmd.dma);
3299err:
3300 return level;
3301}
3302
941a77d5
SK		 3303int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3304 struct be_dma_mem *cmd)
3305{
3306 struct be_mcc_wrb *wrb;
3307 struct be_cmd_req_get_ext_fat_caps *req;
3308 int status;
3309
3310 if (mutex_lock_interruptible(&adapter->mbox_lock))
3311 return -1;
3312
3313 wrb = wrb_from_mbox(adapter);
3314 if (!wrb) {
3315 status = -EBUSY;
3316 goto err;
3317 }
3318
3319 req = cmd->va;
3320 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3321 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3322 cmd->size, wrb, cmd);
3323 req->parameter_type = cpu_to_le32(1);
3324
3325 status = be_mbox_notify_wait(adapter);
3326err:
3327 mutex_unlock(&adapter->mbox_lock);
3328 return status;
3329}
3330
3331int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3332 struct be_dma_mem *cmd,
3333 struct be_fat_conf_params *configs)
3334{
3335 struct be_mcc_wrb *wrb;
3336 struct be_cmd_req_set_ext_fat_caps *req;
3337 int status;
3338
3339 spin_lock_bh(&adapter->mcc_lock);
3340
3341 wrb = wrb_from_mccq(adapter);
3342 if (!wrb) {
3343 status = -EBUSY;
3344 goto err;
3345 }
3346
3347 req = cmd->va;
3348 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3349 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3350 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3351 cmd->size, wrb, cmd);
3352
3353 status = be_mcc_notify_wait(adapter);
3354err:
3355 spin_unlock_bh(&adapter->mcc_lock);
3356 return status;
4762f6ce 3357}
6a4ab669 3358
b4e32a71
PR		 3359int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3360{
3361 struct be_mcc_wrb *wrb;
3362 struct be_cmd_req_get_port_name *req;
3363 int status;
3364
3365 if (!lancer_chip(adapter)) {
3366 *port_name = adapter->hba_port_num + '0';
3367 return 0;
3368 }
3369
3370 spin_lock_bh(&adapter->mcc_lock);
3371
3372 wrb = wrb_from_mccq(adapter);
3373 if (!wrb) {
3374 status = -EBUSY;
3375 goto err;
3376 }
3377
3378 req = embedded_payload(wrb);
3379
3380 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3381 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3382 NULL);
3383 req->hdr.version = 1;
3384
3385 status = be_mcc_notify_wait(adapter);
3386 if (!status) {
3387 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3388 *port_name = resp->port_name[adapter->hba_port_num];
3389 } else {
3390 *port_name = adapter->hba_port_num + '0';
3391 }
3392err:
3393 spin_unlock_bh(&adapter->mcc_lock);
3394 return status;
3395}
3396
10cccf60
VV		 3397/* Descriptor type */
3398enum {
3399 FUNC_DESC = 1,
3400 VFT_DESC = 2
3401};
3402
3403static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3404 int desc_type)
abb93951 3405{
150d58c7 3406 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 3407 struct be_nic_res_desc *nic;
abb93951
PR		 3408 int i;
3409
3410 for (i = 0; i < desc_count; i++) {
150d58c7 3411 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 3412 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3413 nic = (struct be_nic_res_desc *)hdr;
3414 if (desc_type == FUNC_DESC ||
3415 (desc_type == VFT_DESC &&
3416 nic->flags & (1 << VFT_SHIFT)))
3417 return nic;
3418 }
abb93951 3419
150d58c7
VV		 3420 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3421 hdr = (void *)hdr + hdr->desc_len;
abb93951 3422 }
150d58c7
VV		 3423 return NULL;
3424}
3425
10cccf60
VV		 3426static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3427{
3428 return be_get_nic_desc(buf, desc_count, VFT_DESC);
3429}
3430
3431static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3432{
3433 return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3434}
3435
150d58c7
VV		 3436static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3437 u32 desc_count)
3438{
3439 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3440 struct be_pcie_res_desc *pcie;
3441 int i;
3442
3443 for (i = 0; i < desc_count; i++) {
3444 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3445 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3446 pcie = (struct be_pcie_res_desc *)hdr;
3447 if (pcie->pf_num == devfn)
3448 return pcie;
3449 }
abb93951 3450
150d58c7
VV		 3451 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3452 hdr = (void *)hdr + hdr->desc_len;
3453 }
950e2958 3454 return NULL;
abb93951
PR		 3455}
3456
f93f160b
VV		 3457static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3458{
3459 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3460 int i;
3461
3462 for (i = 0; i < desc_count; i++) {
3463 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3464 return (struct be_port_res_desc *)hdr;
3465
3466 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3467 hdr = (void *)hdr + hdr->desc_len;
3468 }
3469 return NULL;
3470}
3471
92bf14ab
SP		 3472static void be_copy_nic_desc(struct be_resources *res,
3473 struct be_nic_res_desc *desc)
3474{
3475 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3476 res->max_vlans = le16_to_cpu(desc->vlan_count);
3477 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3478 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3479 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3480 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3481 res->max_evt_qs = le16_to_cpu(desc->eq_count);
3482 /* Clear flags that driver is not interested in */
3483 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3484 BE_IF_CAP_FLAGS_WANT;
3485 /* Need 1 RXQ as the default RXQ */
3486 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3487 res->max_rss_qs -= 1;
3488}
3489
abb93951 3490/* Uses Mbox */
92bf14ab 3491int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 3492{
3493 struct be_mcc_wrb *wrb;
3494 struct be_cmd_req_get_func_config *req;
3495 int status;
3496 struct be_dma_mem cmd;
3497
d98ef50f
SR		 3498 if (mutex_lock_interruptible(&adapter->mbox_lock))
3499 return -1;
3500
abb93951
PR		 3501 memset(&cmd, 0, sizeof(struct be_dma_mem));
3502 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
a2cc4e0b 3503 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
abb93951
PR		 3504 if (!cmd.va) {
3505 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 3506 status = -ENOMEM;
3507 goto err;
abb93951 3508 }
abb93951
PR		 3509
3510 wrb = wrb_from_mbox(adapter);
3511 if (!wrb) {
3512 status = -EBUSY;
3513 goto err;
3514 }
3515
3516 req = cmd.va;
3517
3518 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3519 OPCODE_COMMON_GET_FUNC_CONFIG,
3520 cmd.size, wrb, &cmd);
3521
28710c55
KA		 3522 if (skyhawk_chip(adapter))
3523 req->hdr.version = 1;
3524
abb93951
PR		 3525 status = be_mbox_notify_wait(adapter);
3526 if (!status) {
3527 struct be_cmd_resp_get_func_config *resp = cmd.va;
3528 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 3529 struct be_nic_res_desc *desc;
abb93951 3530
10cccf60 3531 desc = be_get_func_nic_desc(resp->func_param, desc_count);
abb93951
PR		 3532 if (!desc) {
3533 status = -EINVAL;
3534 goto err;
3535 }
3536
d5c18473 3537 adapter->pf_number = desc->pf_num;
92bf14ab 3538 be_copy_nic_desc(res, desc);
abb93951
PR		 3539 }
3540err:
3541 mutex_unlock(&adapter->mbox_lock);
d98ef50f
SR		 3542 if (cmd.va)
3543 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3544 return status;
3545}
3546
ba48c0c9 3547/* Will use MBOX only if MCCQ has not been created */
92bf14ab
SP		 3548int be_cmd_get_profile_config(struct be_adapter *adapter,
3549 struct be_resources *res, u8 domain)
a05f99db 3550{
150d58c7 3551 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 3552 struct be_cmd_req_get_profile_config *req;
10cccf60 3553 struct be_nic_res_desc *vf_res;
150d58c7 3554 struct be_pcie_res_desc *pcie;
f93f160b 3555 struct be_port_res_desc *port;
150d58c7 3556 struct be_nic_res_desc *nic;
ba48c0c9 3557 struct be_mcc_wrb wrb = {0};
a05f99db 3558 struct be_dma_mem cmd;
150d58c7 3559 u32 desc_count;
a05f99db
VV		 3560 int status;
3561
3562 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7
VV		 3563 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3564 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3565 if (!cmd.va)
a05f99db 3566 return -ENOMEM;
a05f99db 3567
ba48c0c9
VV		 3568 req = cmd.va;
3569 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3570 OPCODE_COMMON_GET_PROFILE_CONFIG,
3571 cmd.size, &wrb, &cmd);
3572
3573 req->hdr.domain = domain;
3574 if (!lancer_chip(adapter))
3575 req->hdr.version = 1;
3576 req->type = ACTIVE_PROFILE_TYPE;
3577
3578 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 3579 if (status)
3580 goto err;
abb93951 3581
150d58c7
VV		 3582 resp = cmd.va;
3583 desc_count = le32_to_cpu(resp->desc_count);
abb93951 3584
a2cc4e0b
SP		 3585 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3586 desc_count);
150d58c7 3587 if (pcie)
92bf14ab 3588 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 3589
f93f160b
VV		 3590 port = be_get_port_desc(resp->func_param, desc_count);
3591 if (port)
3592 adapter->mc_type = port->mc_type;
3593
10cccf60 3594 nic = be_get_func_nic_desc(resp->func_param, desc_count);
92bf14ab
SP		 3595 if (nic)
3596 be_copy_nic_desc(res, nic);
3597
10cccf60
VV		 3598 vf_res = be_get_vft_desc(resp->func_param, desc_count);
3599 if (vf_res)
3600 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 3601err:
a05f99db 3602 if (cmd.va)
150d58c7 3603 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
abb93951
PR		 3604 return status;
3605}
3606
bec84e6b
VV		 3607/* Will use MBOX only if MCCQ has not been created */
3608static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3609 int size, int count, u8 version, u8 domain)
d5c18473 3610{
d5c18473 3611 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 3612 struct be_mcc_wrb wrb = {0};
3613 struct be_dma_mem cmd;
d5c18473
PR		 3614 int status;
3615
bec84e6b
VV		 3616 memset(&cmd, 0, sizeof(struct be_dma_mem));
3617 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
3618 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3619 if (!cmd.va)
3620 return -ENOMEM;
d5c18473 3621
bec84e6b 3622 req = cmd.va;
d5c18473 3623 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 3624 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3625 &wrb, &cmd);
a401801c 3626 req->hdr.version = version;
d5c18473 3627 req->hdr.domain = domain;
bec84e6b 3628 req->desc_count = cpu_to_le32(count);
a401801c
SP		 3629 memcpy(req->desc, desc, size);
3630
bec84e6b
VV		 3631 status = be_cmd_notify_wait(adapter, &wrb);
3632
3633 if (cmd.va)
3634 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
d5c18473
PR		 3635 return status;
3636}
3637
a401801c 3638/* Mark all fields invalid */
bec84e6b 3639static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 3640{
3641 memset(nic, 0, sizeof(*nic));
3642 nic->unicast_mac_count = 0xFFFF;
3643 nic->mcc_count = 0xFFFF;
3644 nic->vlan_count = 0xFFFF;
3645 nic->mcast_mac_count = 0xFFFF;
3646 nic->txq_count = 0xFFFF;
3647 nic->rq_count = 0xFFFF;
3648 nic->rssq_count = 0xFFFF;
3649 nic->lro_count = 0xFFFF;
3650 nic->cq_count = 0xFFFF;
3651 nic->toe_conn_count = 0xFFFF;
3652 nic->eq_count = 0xFFFF;
0f77ba73 3653 nic->iface_count = 0xFFFF;
a401801c 3654 nic->link_param = 0xFF;
0f77ba73 3655 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 3656 nic->acpi_params = 0xFF;
3657 nic->wol_param = 0x0F;
0f77ba73
RN		 3658 nic->tunnel_iface_count = 0xFFFF;
3659 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 3660 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 3661 nic->bw_max = 0xFFFFFFFF;
3662}
3663
bec84e6b
VV		 3664/* Mark all fields invalid */
3665static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3666{
3667 memset(pcie, 0, sizeof(*pcie));
3668 pcie->sriov_state = 0xFF;
3669 pcie->pf_state = 0xFF;
3670 pcie->pf_type = 0xFF;
3671 pcie->num_vfs = 0xFFFF;
3672}
3673
0f77ba73
RN		 3674int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3675 u8 domain)
a401801c 3676{
0f77ba73
RN		 3677 struct be_nic_res_desc nic_desc;
3678 u32 bw_percent;
3679 u16 version = 0;
3680
3681 if (BE3_chip(adapter))
3682 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 3683
0f77ba73
RN		 3684 be_reset_nic_desc(&nic_desc);
3685 nic_desc.pf_num = adapter->pf_number;
3686 nic_desc.vf_num = domain;
3687 if (lancer_chip(adapter)) {
a401801c
SP		 3688 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3689 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3690 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3691 (1 << NOSV_SHIFT);
0f77ba73 3692 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 3693 } else {
0f77ba73
RN		 3694 version = 1;
3695 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3696 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3697 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3698 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3699 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 3700 }
0f77ba73
RN		 3701
3702 return be_cmd_set_profile_config(adapter, &nic_desc,
3703 nic_desc.hdr.desc_len,
bec84e6b
VV		 3704 1, version, domain);
3705}
3706
3707int be_cmd_set_sriov_config(struct be_adapter *adapter,
3708 struct be_resources res, u16 num_vfs)
3709{
3710 struct {
3711 struct be_pcie_res_desc pcie;
3712 struct be_nic_res_desc nic_vft;
3713 } __packed desc;
3714 u16 vf_q_count;
3715
3716 if (BEx_chip(adapter) || lancer_chip(adapter))
3717 return 0;
3718
3719 /* PF PCIE descriptor */
3720 be_reset_pcie_desc(&desc.pcie);
3721 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3722 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3723 desc.pcie.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3724 desc.pcie.pf_num = adapter->pdev->devfn;
3725 desc.pcie.sriov_state = num_vfs ? 1 : 0;
3726 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3727
3728 /* VF NIC Template descriptor */
3729 be_reset_nic_desc(&desc.nic_vft);
3730 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3731 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3732 desc.nic_vft.flags = (1 << VFT_SHIFT) | (1 << IMM_SHIFT) |
3733 (1 << NOSV_SHIFT);
3734 desc.nic_vft.pf_num = adapter->pdev->devfn;
3735 desc.nic_vft.vf_num = 0;
3736
3737 if (num_vfs && res.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3738 /* If number of VFs requested is 8 less than max supported,
3739 * assign 8 queue pairs to the PF and divide the remaining
3740 * resources evenly among the VFs
3741 */
3742 if (num_vfs < (be_max_vfs(adapter) - 8))
3743 vf_q_count = (res.max_rss_qs - 8) / num_vfs;
3744 else
3745 vf_q_count = res.max_rss_qs / num_vfs;
3746
3747 desc.nic_vft.rq_count = cpu_to_le16(vf_q_count);
3748 desc.nic_vft.txq_count = cpu_to_le16(vf_q_count);
3749 desc.nic_vft.rssq_count = cpu_to_le16(vf_q_count - 1);
3750 desc.nic_vft.cq_count = cpu_to_le16(3 * vf_q_count);
3751 } else {
3752 desc.nic_vft.txq_count = cpu_to_le16(1);
3753 desc.nic_vft.rq_count = cpu_to_le16(1);
3754 desc.nic_vft.rssq_count = cpu_to_le16(0);
3755 /* One CQ for each TX, RX and MCCQ */
3756 desc.nic_vft.cq_count = cpu_to_le16(3);
3757 }
3758
3759 return be_cmd_set_profile_config(adapter, &desc,
3760 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 3761}
3762
3763int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3764{
3765 struct be_mcc_wrb *wrb;
3766 struct be_cmd_req_manage_iface_filters *req;
3767 int status;
3768
3769 if (iface == 0xFFFFFFFF)
3770 return -1;
3771
3772 spin_lock_bh(&adapter->mcc_lock);
3773
3774 wrb = wrb_from_mccq(adapter);
3775 if (!wrb) {
3776 status = -EBUSY;
3777 goto err;
3778 }
3779 req = embedded_payload(wrb);
3780
3781 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3782 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3783 wrb, NULL);
3784 req->op = op;
3785 req->target_iface_id = cpu_to_le32(iface);
3786
3787 status = be_mcc_notify_wait(adapter);
3788err:
3789 spin_unlock_bh(&adapter->mcc_lock);
3790 return status;
3791}
3792
3793int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3794{
3795 struct be_port_res_desc port_desc;
3796
3797 memset(&port_desc, 0, sizeof(port_desc));
3798 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3799 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3800 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3801 port_desc.link_num = adapter->hba_port_num;
3802 if (port) {
3803 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3804 (1 << RCVID_SHIFT);
3805 port_desc.nv_port = swab16(port);
3806 } else {
3807 port_desc.nv_flags = NV_TYPE_DISABLED;
3808 port_desc.nv_port = 0;
3809 }
3810
3811 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 3812 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 3813}
3814
4c876616
SP		 3815int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3816 int vf_num)
3817{
3818 struct be_mcc_wrb *wrb;
3819 struct be_cmd_req_get_iface_list *req;
3820 struct be_cmd_resp_get_iface_list *resp;
3821 int status;
3822
3823 spin_lock_bh(&adapter->mcc_lock);
3824
3825 wrb = wrb_from_mccq(adapter);
3826 if (!wrb) {
3827 status = -EBUSY;
3828 goto err;
3829 }
3830 req = embedded_payload(wrb);
3831
3832 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3833 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3834 wrb, NULL);
3835 req->hdr.domain = vf_num + 1;
3836
3837 status = be_mcc_notify_wait(adapter);
3838 if (!status) {
3839 resp = (struct be_cmd_resp_get_iface_list *)req;
3840 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3841 }
3842
3843err:
3844 spin_unlock_bh(&adapter->mcc_lock);
3845 return status;
3846}
3847
5c510811
SK		 3848static int lancer_wait_idle(struct be_adapter *adapter)
3849{
3850#define SLIPORT_IDLE_TIMEOUT 30
3851 u32 reg_val;
3852 int status = 0, i;
3853
3854 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3855 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3856 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3857 break;
3858
3859 ssleep(1);
3860 }
3861
3862 if (i == SLIPORT_IDLE_TIMEOUT)
3863 status = -1;
3864
3865 return status;
3866}
3867
3868int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3869{
3870 int status = 0;
3871
3872 status = lancer_wait_idle(adapter);
3873 if (status)
3874 return status;
3875
3876 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3877
3878 return status;
3879}
3880
3881/* Routine to check whether dump image is present or not */
3882bool dump_present(struct be_adapter *adapter)
3883{
3884 u32 sliport_status = 0;
3885
3886 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3887 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3888}
3889
3890int lancer_initiate_dump(struct be_adapter *adapter)
3891{
f0613380 3892 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 3893 int status;
3894
f0613380
KA		 3895 if (dump_present(adapter)) {
3896 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
3897 return -EEXIST;
3898 }
3899
5c510811
SK		 3900 /* give firmware reset and diagnostic dump */
3901 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3902 PHYSDEV_CONTROL_DD_MASK);
3903 if (status < 0) {
f0613380 3904 dev_err(dev, "FW reset failed\n");
5c510811
SK		 3905 return status;
3906 }
3907
3908 status = lancer_wait_idle(adapter);
3909 if (status)
3910 return status;
3911
3912 if (!dump_present(adapter)) {
f0613380
KA		 3913 dev_err(dev, "FW dump not generated\n");
3914 return -EIO;
5c510811
SK		 3915 }
3916
3917 return 0;
3918}
3919
f0613380
KA		 3920int lancer_delete_dump(struct be_adapter *adapter)
3921{
3922 int status;
3923
3924 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
3925 return be_cmd_status(status);
3926}
3927
dcf7ebba
PR		 3928/* Uses sync mcc */
3929int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3930{
3931 struct be_mcc_wrb *wrb;
3932 struct be_cmd_enable_disable_vf *req;
3933 int status;
3934
0599863d 3935 if (BEx_chip(adapter))
dcf7ebba
PR		 3936 return 0;
3937
3938 spin_lock_bh(&adapter->mcc_lock);
3939
3940 wrb = wrb_from_mccq(adapter);
3941 if (!wrb) {
3942 status = -EBUSY;
3943 goto err;
3944 }
3945
3946 req = embedded_payload(wrb);
3947
3948 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3949 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3950 wrb, NULL);
3951
3952 req->hdr.domain = domain;
3953 req->enable = 1;
3954 status = be_mcc_notify_wait(adapter);
3955err:
3956 spin_unlock_bh(&adapter->mcc_lock);
3957 return status;
3958}
3959
68c45a2d
SK		 3960int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3961{
3962 struct be_mcc_wrb *wrb;
3963 struct be_cmd_req_intr_set *req;
3964 int status;
3965
3966 if (mutex_lock_interruptible(&adapter->mbox_lock))
3967 return -1;
3968
3969 wrb = wrb_from_mbox(adapter);
3970
3971 req = embedded_payload(wrb);
3972
3973 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3974 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3975 wrb, NULL);
3976
3977 req->intr_enabled = intr_enable;
3978
3979 status = be_mbox_notify_wait(adapter);
3980
3981 mutex_unlock(&adapter->mbox_lock);
3982 return status;
3983}
3984
542963b7
VV		 3985/* Uses MBOX */
3986int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
3987{
3988 struct be_cmd_req_get_active_profile *req;
3989 struct be_mcc_wrb *wrb;
3990 int status;
3991
3992 if (mutex_lock_interruptible(&adapter->mbox_lock))
3993 return -1;
3994
3995 wrb = wrb_from_mbox(adapter);
3996 if (!wrb) {
3997 status = -EBUSY;
3998 goto err;
3999 }
4000
4001 req = embedded_payload(wrb);
4002
4003 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4004 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4005 wrb, NULL);
4006
4007 status = be_mbox_notify_wait(adapter);
4008 if (!status) {
4009 struct be_cmd_resp_get_active_profile *resp =
4010 embedded_payload(wrb);
4011 *profile_id = le16_to_cpu(resp->active_profile_id);
4012 }
4013
4014err:
4015 mutex_unlock(&adapter->mbox_lock);
4016 return status;
4017}
4018
bdce2ad7
SR		 4019int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4020 int link_state, u8 domain)
4021{
4022 struct be_mcc_wrb *wrb;
4023 struct be_cmd_req_set_ll_link *req;
4024 int status;
4025
4026 if (BEx_chip(adapter) || lancer_chip(adapter))
4027 return 0;
4028
4029 spin_lock_bh(&adapter->mcc_lock);
4030
4031 wrb = wrb_from_mccq(adapter);
4032 if (!wrb) {
4033 status = -EBUSY;
4034 goto err;
4035 }
4036
4037 req = embedded_payload(wrb);
4038
4039 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4040 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4041 sizeof(*req), wrb, NULL);
4042
4043 req->hdr.version = 1;
4044 req->hdr.domain = domain;
4045
4046 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4047 req->link_config |= 1;
4048
4049 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4050 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4051
4052 status = be_mcc_notify_wait(adapter);
4053err:
4054 spin_unlock_bh(&adapter->mcc_lock);
4055 return status;
4056}
4057
6a4ab669 4058int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 4059 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 4060{
4061 struct be_adapter *adapter = netdev_priv(netdev_handle);
4062 struct be_mcc_wrb *wrb;
4063 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
4064 struct be_cmd_req_hdr *req;
4065 struct be_cmd_resp_hdr *resp;
4066 int status;
4067
4068 spin_lock_bh(&adapter->mcc_lock);
4069
4070 wrb = wrb_from_mccq(adapter);
4071 if (!wrb) {
4072 status = -EBUSY;
4073 goto err;
4074 }
4075 req = embedded_payload(wrb);
4076 resp = embedded_payload(wrb);
4077
4078 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4079 hdr->opcode, wrb_payload_size, wrb, NULL);
4080 memcpy(req, wrb_payload, wrb_payload_size);
4081 be_dws_cpu_to_le(req, wrb_payload_size);
4082
4083 status = be_mcc_notify_wait(adapter);
4084 if (cmd_status)
4085 *cmd_status = (status & 0xffff);
4086 if (ext_status)
4087 *ext_status = 0;
4088 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4089 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4090err:
4091 spin_unlock_bh(&adapter->mcc_lock);
4092 return status;
4093}
4094EXPORT_SYMBOL(be_roce_mcc_cmd);
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