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Merge tag 'for-5.4-rc2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
CommitLineData
6e9ef509 1// SPDX-License-Identifier: GPL-2.0-only
6b7c5b94 2/*
7dfbe7d7 3 * Copyright (C) 2005 - 2016 Broadcom
6b7c5b94
SP		 4 * All rights reserved.
5 *
6b7c5b94 6 * Contact Information:
d2145cde 7 * linux-drivers@emulex.com
6b7c5b94 8 *
d2145cde
AK		 9 * Emulex
10 * 3333 Susan Street
11 * Costa Mesa, CA 92626
6b7c5b94
SP		 12 */
13
6a4ab669 14#include <linux/module.h>
6b7c5b94 15#include "be.h"
8788fdc2 16#include "be_cmds.h"
6b7c5b94 17
262c9740 18const char * const be_misconfig_evt_port_state[] = {
51d1f98a
AK		 19 "Physical Link is functional",
20 "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
21 "Optics of two types installed – Remove one optic or install matching pair of optics.",
22 "Incompatible optics – Replace with compatible optics for card to function.",
23 "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
24 "Uncertified optics – Replace with Avago-certified optics to enable link operation."
21252377
VV		 25};
26
51d1f98a
AK		 27static char *be_port_misconfig_evt_severity[] = {
28 "KERN_WARN",
29 "KERN_INFO",
30 "KERN_ERR",
31 "KERN_WARN"
32};
33
34static char *phy_state_oper_desc[] = {
35 "Link is non-operational",
36 "Link is operational",
21252377
VV		 37 ""
38};
39
f25b119c
PR		 40static struct be_cmd_priv_map cmd_priv_map[] = {
41 {
42 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
43 CMD_SUBSYSTEM_ETH,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
46 },
47 {
48 OPCODE_COMMON_GET_FLOW_CONTROL,
49 CMD_SUBSYSTEM_COMMON,
50 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 },
53 {
54 OPCODE_COMMON_SET_FLOW_CONTROL,
55 CMD_SUBSYSTEM_COMMON,
56 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
57 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
58 },
59 {
60 OPCODE_ETH_GET_PPORT_STATS,
61 CMD_SUBSYSTEM_ETH,
62 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
63 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
64 },
65 {
66 OPCODE_COMMON_GET_PHY_DETAILS,
67 CMD_SUBSYSTEM_COMMON,
68 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
69 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
2e365b1b
SK		 70 },
71 {
72 OPCODE_LOWLEVEL_HOST_DDR_DMA,
73 CMD_SUBSYSTEM_LOWLEVEL,
74 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
75 },
76 {
77 OPCODE_LOWLEVEL_LOOPBACK_TEST,
78 CMD_SUBSYSTEM_LOWLEVEL,
79 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
80 },
81 {
82 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
83 CMD_SUBSYSTEM_LOWLEVEL,
84 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
85 },
884476be
SK		 86 {
87 OPCODE_COMMON_SET_HSW_CONFIG,
88 CMD_SUBSYSTEM_COMMON,
d14584d9
VD		 89 BE_PRIV_DEVCFG | BE_PRIV_VHADM |
90 BE_PRIV_DEVSEC
884476be 91 },
62259ac4
SK		 92 {
93 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
94 CMD_SUBSYSTEM_COMMON,
95 BE_PRIV_DEVCFG
96 }
f25b119c
PR		 97};
98
a2cc4e0b 99static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
f25b119c
PR		 100{
101 int i;
2b1eaa66 102 int num_entries = ARRAY_SIZE(cmd_priv_map);
f25b119c
PR		 103 u32 cmd_privileges = adapter->cmd_privileges;
104
105 for (i = 0; i < num_entries; i++)
106 if (opcode == cmd_priv_map[i].opcode &&
107 subsystem == cmd_priv_map[i].subsystem)
108 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
109 return false;
110
111 return true;
112}
113
3de09455
SK		 114static inline void *embedded_payload(struct be_mcc_wrb *wrb)
115{
116 return wrb->payload.embedded_payload;
117}
609ff3bb 118
efaa408e 119static int be_mcc_notify(struct be_adapter *adapter)
5fb379ee 120{
8788fdc2 121 struct be_queue_info *mccq = &adapter->mcc_obj.q;
5fb379ee
SP		 122 u32 val = 0;
123
954f6825 124 if (be_check_error(adapter, BE_ERROR_ANY))
efaa408e 125 return -EIO;
7acc2087 126
5fb379ee
SP		 127 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
128 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 129
130 wmb();
8788fdc2 131 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
efaa408e
SR		 132
133 return 0;
5fb379ee
SP		 134}
135
136/* To check if valid bit is set, check the entire word as we don't know
137 * the endianness of the data (old entry is host endian while a new entry is
138 * little endian) */
efd2e40a 139static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
5fb379ee 140{
9e9ff4b7
SP		 141 u32 flags;
142
5fb379ee 143 if (compl->flags != 0) {
9e9ff4b7
SP		 144 flags = le32_to_cpu(compl->flags);
145 if (flags & CQE_FLAGS_VALID_MASK) {
146 compl->flags = flags;
147 return true;
148 }
5fb379ee 149 }
9e9ff4b7 150 return false;
5fb379ee
SP		 151}
152
153/* Need to reset the entire word that houses the valid bit */
efd2e40a 154static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
5fb379ee
SP		 155{
156 compl->flags = 0;
157}
158
652bf646
PR		 159static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
160{
161 unsigned long addr;
162
163 addr = tag1;
164 addr = ((addr << 16) << 16) | tag0;
165 return (void *)addr;
166}
167
4c60005f
KA		 168static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
169{
170 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
171 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
172 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
77be8c1c 173 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
4c60005f
KA		 174 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
175 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
176 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
177 return true;
178 else
179 return false;
180}
181
559b633f
SP		 182/* Place holder for all the async MCC cmds wherein the caller is not in a busy
183 * loop (has not issued be_mcc_notify_wait())
184 */
185static void be_async_cmd_process(struct be_adapter *adapter,
186 struct be_mcc_compl *compl,
187 struct be_cmd_resp_hdr *resp_hdr)
188{
189 enum mcc_base_status base_status = base_status(compl->status);
190 u8 opcode = 0, subsystem = 0;
191
192 if (resp_hdr) {
193 opcode = resp_hdr->opcode;
194 subsystem = resp_hdr->subsystem;
195 }
196
197 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
198 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
199 complete(&adapter->et_cmd_compl);
200 return;
201 }
202
9c855975
SR		 203 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
204 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
205 complete(&adapter->et_cmd_compl);
206 return;
207 }
208
559b633f
SP		 209 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
210 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
211 subsystem == CMD_SUBSYSTEM_COMMON) {
212 adapter->flash_status = compl->status;
213 complete(&adapter->et_cmd_compl);
214 return;
215 }
216
217 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
218 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
219 subsystem == CMD_SUBSYSTEM_ETH &&
220 base_status == MCC_STATUS_SUCCESS) {
221 be_parse_stats(adapter);
222 adapter->stats_cmd_sent = false;
223 return;
224 }
225
226 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
227 subsystem == CMD_SUBSYSTEM_COMMON) {
228 if (base_status == MCC_STATUS_SUCCESS) {
229 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
230 (void *)resp_hdr;
29e9122b 231 adapter->hwmon_info.be_on_die_temp =
559b633f
SP		 232 resp->on_die_temperature;
233 } else {
234 adapter->be_get_temp_freq = 0;
29e9122b
VD		 235 adapter->hwmon_info.be_on_die_temp =
236 BE_INVALID_DIE_TEMP;
559b633f
SP		 237 }
238 return;
239 }
240}
241
8788fdc2 242static int be_mcc_compl_process(struct be_adapter *adapter,
652bf646 243 struct be_mcc_compl *compl)
5fb379ee 244{
4c60005f
KA		 245 enum mcc_base_status base_status;
246 enum mcc_addl_status addl_status;
652bf646
PR		 247 struct be_cmd_resp_hdr *resp_hdr;
248 u8 opcode = 0, subsystem = 0;
5fb379ee
SP		 249
250 /* Just swap the status to host endian; mcc tag is opaquely copied
251 * from mcc_wrb */
252 be_dws_le_to_cpu(compl, 4);
253
4c60005f
KA		 254 base_status = base_status(compl->status);
255 addl_status = addl_status(compl->status);
96c9b2e4 256
652bf646 257 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
652bf646
PR		 258 if (resp_hdr) {
259 opcode = resp_hdr->opcode;
260 subsystem = resp_hdr->subsystem;
261 }
262
559b633f 263 be_async_cmd_process(adapter, compl, resp_hdr);
3de09455 264
559b633f
SP		 265 if (base_status != MCC_STATUS_SUCCESS &&
266 !be_skip_err_log(opcode, base_status, addl_status)) {
fa5c867d
SR		 267 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
268 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
97f1d8cd 269 dev_warn(&adapter->pdev->dev,
522609f2 270 "VF is not privileged to issue opcode %d-%d\n",
97f1d8cd 271 opcode, subsystem);
2b3f291b 272 } else {
97f1d8cd
VV		 273 dev_err(&adapter->pdev->dev,
274 "opcode %d-%d failed:status %d-%d\n",
4c60005f 275 opcode, subsystem, base_status, addl_status);
2b3f291b 276 }
5fb379ee 277 }
4c60005f 278 return compl->status;
5fb379ee
SP		 279}
280
a8f447bd 281/* Link state evt is a string of bytes; no need for endian swapping */
8788fdc2 282static void be_async_link_state_process(struct be_adapter *adapter,
3acf19d9 283 struct be_mcc_compl *compl)
a8f447bd 284{
3acf19d9
SP		 285 struct be_async_event_link_state *evt =
286 (struct be_async_event_link_state *)compl;
287
b236916a 288 /* When link status changes, link speed must be re-queried from FW */
42f11cf2 289 adapter->phy.link_speed = -1;
b236916a 290
bdce2ad7
SR		 291 /* On BEx the FW does not send a separate link status
292 * notification for physical and logical link.
293 * On other chips just process the logical link
294 * status notification
295 */
296 if (!BEx_chip(adapter) &&
2e177a5c
PR		 297 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
298 return;
299
b236916a
AK		 300 /* For the initial link status do not rely on the ASYNC event as
301 * it may not be received in some cases.
302 */
303 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
bdce2ad7
SR		 304 be_link_status_update(adapter,
305 evt->port_link_status & LINK_STATUS_MASK);
a8f447bd
SP		 306}
307
21252377
VV		 308static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
309 struct be_mcc_compl *compl)
310{
311 struct be_async_event_misconfig_port *evt =
312 (struct be_async_event_misconfig_port *)compl;
51d1f98a
AK		 313 u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
314 u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
315 u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
21252377 316 struct device *dev = &adapter->pdev->dev;
51d1f98a
AK		 317 u8 msg_severity = DEFAULT_MSG_SEVERITY;
318 u8 phy_state_info;
319 u8 new_phy_state;
320
321 new_phy_state =
322 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
323
324 if (new_phy_state == adapter->phy_state)
325 return;
326
327 adapter->phy_state = new_phy_state;
21252377 328
51d1f98a
AK		 329 /* for older fw that doesn't populate link effect data */
330 if (!sfp_misconfig_evt_word2)
331 goto log_message;
21252377 332
51d1f98a
AK		 333 phy_state_info =
334 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
335
336 if (phy_state_info & PHY_STATE_INFO_VALID) {
337 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
338
339 if (be_phy_unqualified(new_phy_state))
340 phy_oper_state = (phy_state_info & PHY_STATE_OPER);
341 }
342
343log_message:
21252377
VV		 344 /* Log an error message that would allow a user to determine
345 * whether the SFPs have an issue
346 */
51d1f98a
AK		 347 if (be_phy_state_unknown(new_phy_state))
348 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
349 "Port %c: Unrecognized Optics state: 0x%x. %s",
350 adapter->port_name,
351 new_phy_state,
352 phy_state_oper_desc[phy_oper_state]);
353 else
354 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
355 "Port %c: %s %s",
356 adapter->port_name,
357 be_misconfig_evt_port_state[new_phy_state],
358 phy_state_oper_desc[phy_oper_state]);
359
360 /* Log Vendor name and part no. if a misconfigured SFP is detected */
361 if (be_phy_misconfigured(new_phy_state))
362 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
21252377
VV		 363}
364
cc4ce020
SK		 365/* Grp5 CoS Priority evt */
366static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
3acf19d9 367 struct be_mcc_compl *compl)
cc4ce020 368{
3acf19d9
SP		 369 struct be_async_event_grp5_cos_priority *evt =
370 (struct be_async_event_grp5_cos_priority *)compl;
371
cc4ce020
SK		 372 if (evt->valid) {
373 adapter->vlan_prio_bmap = evt->available_priority_bmap;
fdf81bfb 374 adapter->recommended_prio_bits =
cc4ce020
SK		 375 evt->reco_default_priority << VLAN_PRIO_SHIFT;
376 }
377}
378
323ff71e 379/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
cc4ce020 380static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
3acf19d9 381 struct be_mcc_compl *compl)
cc4ce020 382{
3acf19d9
SP		 383 struct be_async_event_grp5_qos_link_speed *evt =
384 (struct be_async_event_grp5_qos_link_speed *)compl;
385
323ff71e
SP		 386 if (adapter->phy.link_speed >= 0 &&
387 evt->physical_port == adapter->port_num)
388 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
cc4ce020
SK		 389}
390
3968fa1e
AK		 391/*Grp5 PVID evt*/
392static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
3acf19d9 393 struct be_mcc_compl *compl)
3968fa1e 394{
3acf19d9
SP		 395 struct be_async_event_grp5_pvid_state *evt =
396 (struct be_async_event_grp5_pvid_state *)compl;
397
bdac85b5 398 if (evt->enabled) {
939cf306 399 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
bdac85b5
RN		 400 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
401 } else {
3968fa1e 402 adapter->pvid = 0;
bdac85b5 403 }
3968fa1e
AK		 404}
405
760c295e
VD		 406#define MGMT_ENABLE_MASK 0x4
407static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
408 struct be_mcc_compl *compl)
409{
410 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
411 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
412
413 if (evt_dw1 & MGMT_ENABLE_MASK) {
414 adapter->flags |= BE_FLAGS_OS2BMC;
415 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
416 } else {
417 adapter->flags &= ~BE_FLAGS_OS2BMC;
418 }
419}
420
cc4ce020 421static void be_async_grp5_evt_process(struct be_adapter *adapter,
3acf19d9 422 struct be_mcc_compl *compl)
cc4ce020 423{
3acf19d9
SP		 424 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
425 ASYNC_EVENT_TYPE_MASK;
cc4ce020
SK		 426
427 switch (event_type) {
428 case ASYNC_EVENT_COS_PRIORITY:
3acf19d9
SP		 429 be_async_grp5_cos_priority_process(adapter, compl);
430 break;
cc4ce020 431 case ASYNC_EVENT_QOS_SPEED:
3acf19d9
SP		 432 be_async_grp5_qos_speed_process(adapter, compl);
433 break;
3968fa1e 434 case ASYNC_EVENT_PVID_STATE:
3acf19d9
SP		 435 be_async_grp5_pvid_state_process(adapter, compl);
436 break;
760c295e
VD		 437 /* Async event to disable/enable os2bmc and/or mac-learning */
438 case ASYNC_EVENT_FW_CONTROL:
439 be_async_grp5_fw_control_process(adapter, compl);
440 break;
cc4ce020 441 default:
cc4ce020
SK		 442 break;
443 }
444}
445
bc0c3405 446static void be_async_dbg_evt_process(struct be_adapter *adapter,
3acf19d9 447 struct be_mcc_compl *cmp)
bc0c3405
AK		 448{
449 u8 event_type = 0;
504fbf1e 450 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
bc0c3405 451
3acf19d9
SP		 452 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
453 ASYNC_EVENT_TYPE_MASK;
bc0c3405
AK		 454
455 switch (event_type) {
456 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
457 if (evt->valid)
458 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
459 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
460 break;
461 default:
05ccaa2b
VV		 462 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
463 event_type);
bc0c3405
AK		 464 break;
465 }
466}
467
21252377
VV		 468static void be_async_sliport_evt_process(struct be_adapter *adapter,
469 struct be_mcc_compl *cmp)
470{
471 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
472 ASYNC_EVENT_TYPE_MASK;
473
474 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
475 be_async_port_misconfig_event_process(adapter, cmp);
476}
477
3acf19d9 478static inline bool is_link_state_evt(u32 flags)
a8f447bd 479{
3acf19d9
SP		 480 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
481 ASYNC_EVENT_CODE_LINK_STATE;
a8f447bd 482}
5fb379ee 483
3acf19d9 484static inline bool is_grp5_evt(u32 flags)
cc4ce020 485{
3acf19d9
SP		 486 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
487 ASYNC_EVENT_CODE_GRP_5;
cc4ce020
SK		 488}
489
3acf19d9 490static inline bool is_dbg_evt(u32 flags)
bc0c3405 491{
3acf19d9
SP		 492 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
493 ASYNC_EVENT_CODE_QNQ;
494}
495
21252377
VV		 496static inline bool is_sliport_evt(u32 flags)
497{
498 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
499 ASYNC_EVENT_CODE_SLIPORT;
500}
501
3acf19d9
SP		 502static void be_mcc_event_process(struct be_adapter *adapter,
503 struct be_mcc_compl *compl)
504{
505 if (is_link_state_evt(compl->flags))
506 be_async_link_state_process(adapter, compl);
507 else if (is_grp5_evt(compl->flags))
508 be_async_grp5_evt_process(adapter, compl);
509 else if (is_dbg_evt(compl->flags))
510 be_async_dbg_evt_process(adapter, compl);
21252377
VV		 511 else if (is_sliport_evt(compl->flags))
512 be_async_sliport_evt_process(adapter, compl);
bc0c3405
AK		 513}
514
efd2e40a 515static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
5fb379ee 516{
8788fdc2 517 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
efd2e40a 518 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
5fb379ee
SP		 519
520 if (be_mcc_compl_is_new(compl)) {
521 queue_tail_inc(mcc_cq);
522 return compl;
523 }
524 return NULL;
525}
526
7a1e9b20
SP		 527void be_async_mcc_enable(struct be_adapter *adapter)
528{
529 spin_lock_bh(&adapter->mcc_cq_lock);
530
531 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
532 adapter->mcc_obj.rearm_cq = true;
533
534 spin_unlock_bh(&adapter->mcc_cq_lock);
535}
536
537void be_async_mcc_disable(struct be_adapter *adapter)
538{
a323d9bf
SP		 539 spin_lock_bh(&adapter->mcc_cq_lock);
540
7a1e9b20 541 adapter->mcc_obj.rearm_cq = false;
a323d9bf
SP		 542 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
543
544 spin_unlock_bh(&adapter->mcc_cq_lock);
7a1e9b20
SP		 545}
546
10ef9ab4 547int be_process_mcc(struct be_adapter *adapter)
5fb379ee 548{
efd2e40a 549 struct be_mcc_compl *compl;
10ef9ab4 550 int num = 0, status = 0;
7a1e9b20 551 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
5fb379ee 552
d0d006a4 553 spin_lock_bh(&adapter->mcc_cq_lock);
3acf19d9 554
8788fdc2 555 while ((compl = be_mcc_compl_get(adapter))) {
a8f447bd 556 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
3acf19d9 557 be_mcc_event_process(adapter, compl);
b31c50a7 558 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
3acf19d9
SP		 559 status = be_mcc_compl_process(adapter, compl);
560 atomic_dec(&mcc_obj->q.used);
5fb379ee
SP		 561 }
562 be_mcc_compl_use(compl);
563 num++;
564 }
b31c50a7 565
10ef9ab4
SP		 566 if (num)
567 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
568
d0d006a4 569 spin_unlock_bh(&adapter->mcc_cq_lock);
10ef9ab4 570 return status;
5fb379ee
SP		 571}
572
6ac7b687 573/* Wait till no more pending mcc requests are present */
b31c50a7 574static int be_mcc_wait_compl(struct be_adapter *adapter)
6ac7b687 575{
b7172414 576#define mcc_timeout 12000 /* 12s timeout */
10ef9ab4 577 int i, status = 0;
f31e50a8
SP		 578 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
579
6ac7b687 580 for (i = 0; i < mcc_timeout; i++) {
954f6825 581 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 582 return -EIO;
583
10ef9ab4 584 status = be_process_mcc(adapter);
b31c50a7 585
f31e50a8 586 if (atomic_read(&mcc_obj->q.used) == 0)
6ac7b687 587 break;
b7172414 588 usleep_range(500, 1000);
6ac7b687 589 }
b31c50a7 590 if (i == mcc_timeout) {
6589ade0 591 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 592 be_set_error(adapter, BE_ERROR_FW);
652bf646 593 return -EIO;
b31c50a7 594 }
f31e50a8 595 return status;
6ac7b687
SP		 596}
597
598/* Notify MCC requests and wait for completion */
b31c50a7 599static int be_mcc_notify_wait(struct be_adapter *adapter)
6ac7b687 600{
652bf646
PR		 601 int status;
602 struct be_mcc_wrb *wrb;
603 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
b0fd2eb2 604 u32 index = mcc_obj->q.head;
652bf646
PR		 605 struct be_cmd_resp_hdr *resp;
606
607 index_dec(&index, mcc_obj->q.len);
608 wrb = queue_index_node(&mcc_obj->q, index);
609
610 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
611
efaa408e
SR		 612 status = be_mcc_notify(adapter);
613 if (status)
614 goto out;
652bf646
PR		 615
616 status = be_mcc_wait_compl(adapter);
617 if (status == -EIO)
618 goto out;
619
4c60005f
KA		 620 status = (resp->base_status |
621 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
622 CQE_ADDL_STATUS_SHIFT));
652bf646
PR		 623out:
624 return status;
6ac7b687
SP		 625}
626
5f0b849e 627static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
6b7c5b94 628{
f25b03a7 629 int msecs = 0;
6b7c5b94
SP		 630 u32 ready;
631
632 do {
954f6825 633 if (be_check_error(adapter, BE_ERROR_ANY))
6589ade0
SP		 634 return -EIO;
635
cf588477 636 ready = ioread32(db);
434b3648 637 if (ready == 0xffffffff)
cf588477 638 return -1;
cf588477
SP		 639
640 ready &= MPU_MAILBOX_DB_RDY_MASK;
6b7c5b94
SP		 641 if (ready)
642 break;
643
f25b03a7 644 if (msecs > 4000) {
6589ade0 645 dev_err(&adapter->pdev->dev, "FW not responding\n");
954f6825 646 be_set_error(adapter, BE_ERROR_FW);
f67ef7ba 647 be_detect_error(adapter);
6b7c5b94
SP		 648 return -1;
649 }
650
1dbf53a2 651 msleep(1);
f25b03a7 652 msecs++;
6b7c5b94
SP		 653 } while (true);
654
655 return 0;
656}
657
658/*
659 * Insert the mailbox address into the doorbell in two steps
5fb379ee 660 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
6b7c5b94 661 */
b31c50a7 662static int be_mbox_notify_wait(struct be_adapter *adapter)
6b7c5b94
SP		 663{
664 int status;
6b7c5b94 665 u32 val = 0;
8788fdc2
SP		 666 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
667 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
6b7c5b94 668 struct be_mcc_mailbox *mbox = mbox_mem->va;
efd2e40a 669 struct be_mcc_compl *compl = &mbox->compl;
6b7c5b94 670
cf588477
SP		 671 /* wait for ready to be set */
672 status = be_mbox_db_ready_wait(adapter, db);
673 if (status != 0)
674 return status;
675
6b7c5b94
SP		 676 val |= MPU_MAILBOX_DB_HI_MASK;
677 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
678 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
679 iowrite32(val, db);
680
681 /* wait for ready to be set */
5f0b849e 682 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 683 if (status != 0)
684 return status;
685
686 val = 0;
6b7c5b94
SP		 687 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
688 val |= (u32)(mbox_mem->dma >> 4) << 2;
689 iowrite32(val, db);
690
5f0b849e 691 status = be_mbox_db_ready_wait(adapter, db);
6b7c5b94
SP		 692 if (status != 0)
693 return status;
694
5fb379ee 695 /* A cq entry has been made now */
efd2e40a
SP		 696 if (be_mcc_compl_is_new(compl)) {
697 status = be_mcc_compl_process(adapter, &mbox->compl);
698 be_mcc_compl_use(compl);
5fb379ee
SP		 699 if (status)
700 return status;
701 } else {
5f0b849e 702 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
6b7c5b94
SP		 703 return -1;
704 }
5fb379ee 705 return 0;
6b7c5b94
SP		 706}
707
710f3e59 708u16 be_POST_stage_get(struct be_adapter *adapter)
6b7c5b94 709{
fe6d2a38
SP		 710 u32 sem;
711
c5b3ad4c
SP		 712 if (BEx_chip(adapter))
713 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
6b7c5b94 714 else
c5b3ad4c
SP		 715 pci_read_config_dword(adapter->pdev,
716 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
717
718 return sem & POST_STAGE_MASK;
6b7c5b94
SP		 719}
720
87f20c26 721static int lancer_wait_ready(struct be_adapter *adapter)
bf99e50d
PR		 722{
723#define SLIPORT_READY_TIMEOUT 30
724 u32 sliport_status;
e673244a 725 int i;
bf99e50d
PR		 726
727 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
728 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
729 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
9fa465c0 730 return 0;
67297ad8 731
9fa465c0
SP		 732 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
733 !(sliport_status & SLIPORT_STATUS_RN_MASK))
734 return -EIO;
67297ad8 735
9fa465c0 736 msleep(1000);
bf99e50d 737 }
67297ad8 738
9fa465c0 739 return sliport_status ? : -1;
bf99e50d
PR		 740}
741
742int be_fw_wait_ready(struct be_adapter *adapter)
6b7c5b94 743{
43a04fdc
SP		 744 u16 stage;
745 int status, timeout = 0;
6ed35eea 746 struct device *dev = &adapter->pdev->dev;
6b7c5b94 747
bf99e50d
PR		 748 if (lancer_chip(adapter)) {
749 status = lancer_wait_ready(adapter);
e673244a
KA		 750 if (status) {
751 stage = status;
752 goto err;
753 }
754 return 0;
bf99e50d
PR		 755 }
756
43a04fdc 757 do {
ca3de6b2
SP		 758 /* There's no means to poll POST state on BE2/3 VFs */
759 if (BEx_chip(adapter) && be_virtfn(adapter))
760 return 0;
761
c5b3ad4c 762 stage = be_POST_stage_get(adapter);
66d29cbc 763 if (stage == POST_STAGE_ARMFW_RDY)
43a04fdc 764 return 0;
66d29cbc 765
a2cc4e0b 766 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
66d29cbc
GS		 767 if (msleep_interruptible(2000)) {
768 dev_err(dev, "Waiting for POST aborted\n");
769 return -EINTR;
43a04fdc 770 }
66d29cbc 771 timeout += 2;
3ab81b5f 772 } while (timeout < 60);
6b7c5b94 773
e673244a
KA		 774err:
775 dev_err(dev, "POST timeout; stage=%#x\n", stage);
9fa465c0 776 return -ETIMEDOUT;
6b7c5b94
SP		 777}
778
6b7c5b94
SP		 779static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
780{
781 return &wrb->payload.sgl[0];
782}
783
a2cc4e0b 784static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
bea50988
SP		 785{
786 wrb->tag0 = addr & 0xFFFFFFFF;
787 wrb->tag1 = upper_32_bits(addr);
788}
6b7c5b94
SP		 789
790/* Don't touch the hdr after it's prepared */
106df1e3
SK		 791/* mem will be NULL for embedded commands */
792static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
a2cc4e0b
SP		 793 u8 subsystem, u8 opcode, int cmd_len,
794 struct be_mcc_wrb *wrb,
795 struct be_dma_mem *mem)
6b7c5b94 796{
106df1e3
SK		 797 struct be_sge *sge;
798
6b7c5b94
SP		 799 req_hdr->opcode = opcode;
800 req_hdr->subsystem = subsystem;
801 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
07793d33 802 req_hdr->version = 0;
bea50988 803 fill_wrb_tags(wrb, (ulong) req_hdr);
106df1e3
SK		 804 wrb->payload_length = cmd_len;
805 if (mem) {
806 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
807 MCC_WRB_SGE_CNT_SHIFT;
808 sge = nonembedded_sgl(wrb);
809 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
810 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
811 sge->len = cpu_to_le32(mem->size);
812 } else
813 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
814 be_dws_cpu_to_le(wrb, 8);
6b7c5b94
SP		 815}
816
817static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
a2cc4e0b 818 struct be_dma_mem *mem)
6b7c5b94
SP		 819{
820 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
821 u64 dma = (u64)mem->dma;
822
823 for (i = 0; i < buf_pages; i++) {
824 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
825 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
826 dma += PAGE_SIZE_4K;
827 }
828}
829
b31c50a7 830static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
6b7c5b94 831{
b31c50a7
SP		 832 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
833 struct be_mcc_wrb *wrb
834 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
835 memset(wrb, 0, sizeof(*wrb));
836 return wrb;
6b7c5b94
SP		 837}
838
b31c50a7 839static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
5fb379ee 840{
b31c50a7
SP		 841 struct be_queue_info *mccq = &adapter->mcc_obj.q;
842 struct be_mcc_wrb *wrb;
843
aa790db9
PR		 844 if (!mccq->created)
845 return NULL;
846
4d277125 847 if (atomic_read(&mccq->used) >= mccq->len)
713d0394 848 return NULL;
713d0394 849
b31c50a7
SP		 850 wrb = queue_head_node(mccq);
851 queue_head_inc(mccq);
852 atomic_inc(&mccq->used);
853 memset(wrb, 0, sizeof(*wrb));
5fb379ee
SP		 854 return wrb;
855}
856
bea50988
SP		 857static bool use_mcc(struct be_adapter *adapter)
858{
859 return adapter->mcc_obj.q.created;
860}
861
862/* Must be used only in process context */
863static int be_cmd_lock(struct be_adapter *adapter)
864{
865 if (use_mcc(adapter)) {
b7172414 866 mutex_lock(&adapter->mcc_lock);
bea50988
SP		 867 return 0;
868 } else {
869 return mutex_lock_interruptible(&adapter->mbox_lock);
870 }
871}
872
873/* Must be used only in process context */
874static void be_cmd_unlock(struct be_adapter *adapter)
875{
876 if (use_mcc(adapter))
b7172414 877 return mutex_unlock(&adapter->mcc_lock);
bea50988
SP		 878 else
879 return mutex_unlock(&adapter->mbox_lock);
880}
881
882static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
883 struct be_mcc_wrb *wrb)
884{
885 struct be_mcc_wrb *dest_wrb;
886
887 if (use_mcc(adapter)) {
888 dest_wrb = wrb_from_mccq(adapter);
889 if (!dest_wrb)
890 return NULL;
891 } else {
892 dest_wrb = wrb_from_mbox(adapter);
893 }
894
895 memcpy(dest_wrb, wrb, sizeof(*wrb));
896 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
897 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
898
899 return dest_wrb;
900}
901
902/* Must be used only in process context */
903static int be_cmd_notify_wait(struct be_adapter *adapter,
904 struct be_mcc_wrb *wrb)
905{
906 struct be_mcc_wrb *dest_wrb;
907 int status;
908
909 status = be_cmd_lock(adapter);
910 if (status)
911 return status;
912
913 dest_wrb = be_cmd_copy(adapter, wrb);
0c884567
SR		 914 if (!dest_wrb) {
915 status = -EBUSY;
916 goto unlock;
917 }
bea50988
SP		 918
919 if (use_mcc(adapter))
920 status = be_mcc_notify_wait(adapter);
921 else
922 status = be_mbox_notify_wait(adapter);
923
924 if (!status)
925 memcpy(wrb, dest_wrb, sizeof(*wrb));
926
0c884567 927unlock:
bea50988
SP		 928 be_cmd_unlock(adapter);
929 return status;
930}
931
2243e2e9
SP		 932/* Tell fw we're about to start firing cmds by writing a
933 * special pattern across the wrb hdr; uses mbox
934 */
935int be_cmd_fw_init(struct be_adapter *adapter)
936{
937 u8 *wrb;
938 int status;
939
bf99e50d
PR		 940 if (lancer_chip(adapter))
941 return 0;
942
2984961c
IV		 943 if (mutex_lock_interruptible(&adapter->mbox_lock))
944 return -1;
2243e2e9
SP		 945
946 wrb = (u8 *)wrb_from_mbox(adapter);
359a972f
SP		 947 *wrb++ = 0xFF;
948 *wrb++ = 0x12;
949 *wrb++ = 0x34;
950 *wrb++ = 0xFF;
951 *wrb++ = 0xFF;
952 *wrb++ = 0x56;
953 *wrb++ = 0x78;
954 *wrb = 0xFF;
2243e2e9
SP		 955
956 status = be_mbox_notify_wait(adapter);
957
2984961c 958 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 959 return status;
960}
961
962/* Tell fw we're done with firing cmds by writing a
963 * special pattern across the wrb hdr; uses mbox
964 */
965int be_cmd_fw_clean(struct be_adapter *adapter)
966{
967 u8 *wrb;
968 int status;
969
bf99e50d
PR		 970 if (lancer_chip(adapter))
971 return 0;
972
2984961c
IV		 973 if (mutex_lock_interruptible(&adapter->mbox_lock))
974 return -1;
2243e2e9
SP		 975
976 wrb = (u8 *)wrb_from_mbox(adapter);
977 *wrb++ = 0xFF;
978 *wrb++ = 0xAA;
979 *wrb++ = 0xBB;
980 *wrb++ = 0xFF;
981 *wrb++ = 0xFF;
982 *wrb++ = 0xCC;
983 *wrb++ = 0xDD;
984 *wrb = 0xFF;
985
986 status = be_mbox_notify_wait(adapter);
987
2984961c 988 mutex_unlock(&adapter->mbox_lock);
2243e2e9
SP		 989 return status;
990}
bf99e50d 991
f2f781a7 992int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
6b7c5b94 993{
b31c50a7
SP		 994 struct be_mcc_wrb *wrb;
995 struct be_cmd_req_eq_create *req;
f2f781a7
SP		 996 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
997 int status, ver = 0;
6b7c5b94 998
2984961c
IV		 999 if (mutex_lock_interruptible(&adapter->mbox_lock))
1000 return -1;
b31c50a7
SP		 1001
1002 wrb = wrb_from_mbox(adapter);
1003 req = embedded_payload(wrb);
6b7c5b94 1004
106df1e3 1005 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1006 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1007 NULL);
6b7c5b94 1008
f2f781a7
SP		 1009 /* Support for EQ_CREATEv2 available only SH-R onwards */
1010 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1011 ver = 2;
1012
1013 req->hdr.version = ver;
6b7c5b94
SP		 1014 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1015
6b7c5b94
SP		 1016 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1017 /* 4byte eqe*/
1018 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1019 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
f2f781a7 1020 __ilog2_u32(eqo->q.len / 256));
6b7c5b94
SP		 1021 be_dws_cpu_to_le(req->context, sizeof(req->context));
1022
1023 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1024
b31c50a7 1025 status = be_mbox_notify_wait(adapter);
6b7c5b94 1026 if (!status) {
b31c50a7 1027 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
03d28ffe 1028
f2f781a7
SP		 1029 eqo->q.id = le16_to_cpu(resp->eq_id);
1030 eqo->msix_idx =
1031 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1032 eqo->q.created = true;
6b7c5b94 1033 }
b31c50a7 1034
2984961c 1035 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1036 return status;
1037}
1038
f9449ab7 1039/* Use MCC */
8788fdc2 1040int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 1041 bool permanent, u32 if_handle, u32 pmac_id)
6b7c5b94 1042{
b31c50a7
SP		 1043 struct be_mcc_wrb *wrb;
1044 struct be_cmd_req_mac_query *req;
6b7c5b94
SP		 1045 int status;
1046
b7172414 1047 mutex_lock(&adapter->mcc_lock);
b31c50a7 1048
f9449ab7
SP		 1049 wrb = wrb_from_mccq(adapter);
1050 if (!wrb) {
1051 status = -EBUSY;
1052 goto err;
1053 }
b31c50a7 1054 req = embedded_payload(wrb);
6b7c5b94 1055
106df1e3 1056 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1057 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1058 NULL);
5ee4979b 1059 req->type = MAC_ADDRESS_TYPE_NETWORK;
6b7c5b94
SP		 1060 if (permanent) {
1061 req->permanent = 1;
1062 } else {
504fbf1e 1063 req->if_id = cpu_to_le16((u16)if_handle);
590c391d 1064 req->pmac_id = cpu_to_le32(pmac_id);
6b7c5b94
SP		 1065 req->permanent = 0;
1066 }
1067
f9449ab7 1068 status = be_mcc_notify_wait(adapter);
b31c50a7
SP		 1069 if (!status) {
1070 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
03d28ffe 1071
6b7c5b94 1072 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
b31c50a7 1073 }
6b7c5b94 1074
f9449ab7 1075err:
b7172414 1076 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1077 return status;
1078}
1079
b31c50a7 1080/* Uses synchronous MCCQ */
8788fdc2 1081int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
a2cc4e0b 1082 u32 if_id, u32 *pmac_id, u32 domain)
6b7c5b94 1083{
b31c50a7
SP		 1084 struct be_mcc_wrb *wrb;
1085 struct be_cmd_req_pmac_add *req;
6b7c5b94
SP		 1086 int status;
1087
b7172414 1088 mutex_lock(&adapter->mcc_lock);
b31c50a7
SP		 1089
1090 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1091 if (!wrb) {
1092 status = -EBUSY;
1093 goto err;
1094 }
b31c50a7 1095 req = embedded_payload(wrb);
6b7c5b94 1096
106df1e3 1097 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1098 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1099 NULL);
6b7c5b94 1100
f8617e08 1101 req->hdr.domain = domain;
6b7c5b94
SP		 1102 req->if_id = cpu_to_le32(if_id);
1103 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1104
b31c50a7 1105 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1106 if (!status) {
1107 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
03d28ffe 1108
6b7c5b94
SP		 1109 *pmac_id = le32_to_cpu(resp->pmac_id);
1110 }
1111
713d0394 1112err:
b7172414 1113 mutex_unlock(&adapter->mcc_lock);
e3a7ae2c 1114
fe68d8bf 1115 if (base_status(status) == MCC_STATUS_UNAUTHORIZED_REQUEST)
e3a7ae2c
SK		 1116 status = -EPERM;
1117
6b7c5b94
SP		 1118 return status;
1119}
1120
b31c50a7 1121/* Uses synchronous MCCQ */
30128031 1122int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
6b7c5b94 1123{
b31c50a7
SP		 1124 struct be_mcc_wrb *wrb;
1125 struct be_cmd_req_pmac_del *req;
6b7c5b94
SP		 1126 int status;
1127
30128031
SP		 1128 if (pmac_id == -1)
1129 return 0;
1130
b7172414 1131 mutex_lock(&adapter->mcc_lock);
b31c50a7
SP		 1132
1133 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1134 if (!wrb) {
1135 status = -EBUSY;
1136 goto err;
1137 }
b31c50a7 1138 req = embedded_payload(wrb);
6b7c5b94 1139
106df1e3 1140 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
cd3307aa
KA		 1141 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1142 wrb, NULL);
6b7c5b94 1143
f8617e08 1144 req->hdr.domain = dom;
6b7c5b94
SP		 1145 req->if_id = cpu_to_le32(if_id);
1146 req->pmac_id = cpu_to_le32(pmac_id);
1147
b31c50a7
SP		 1148 status = be_mcc_notify_wait(adapter);
1149
713d0394 1150err:
b7172414 1151 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1152 return status;
1153}
1154
b31c50a7 1155/* Uses Mbox */
10ef9ab4 1156int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
a2cc4e0b 1157 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
6b7c5b94 1158{
b31c50a7
SP		 1159 struct be_mcc_wrb *wrb;
1160 struct be_cmd_req_cq_create *req;
6b7c5b94 1161 struct be_dma_mem *q_mem = &cq->dma_mem;
b31c50a7 1162 void *ctxt;
6b7c5b94
SP		 1163 int status;
1164
2984961c
IV		 1165 if (mutex_lock_interruptible(&adapter->mbox_lock))
1166 return -1;
b31c50a7
SP		 1167
1168 wrb = wrb_from_mbox(adapter);
1169 req = embedded_payload(wrb);
1170 ctxt = &req->context;
6b7c5b94 1171
106df1e3 1172 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1173 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1174 NULL);
6b7c5b94
SP		 1175
1176 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
bbdc42f8
AK		 1177
1178 if (BEx_chip(adapter)) {
fe6d2a38 1179 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
a2cc4e0b 1180 coalesce_wm);
fe6d2a38 1181 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
a2cc4e0b 1182 ctxt, no_delay);
fe6d2a38 1183 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
a2cc4e0b 1184 __ilog2_u32(cq->len / 256));
fe6d2a38 1185 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
fe6d2a38
SP		 1186 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1187 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
bbdc42f8
AK		 1188 } else {
1189 req->hdr.version = 2;
1190 req->page_size = 1; /* 1 for 4K */
09e83a9d
AK		 1191
1192 /* coalesce-wm field in this cmd is not relevant to Lancer.
1193 * Lancer uses COMMON_MODIFY_CQ to set this field
1194 */
1195 if (!lancer_chip(adapter))
1196 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1197 ctxt, coalesce_wm);
bbdc42f8 1198 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
a2cc4e0b 1199 no_delay);
bbdc42f8 1200 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
a2cc4e0b 1201 __ilog2_u32(cq->len / 256));
bbdc42f8 1202 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
a2cc4e0b
SP		 1203 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1204 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
fe6d2a38 1205 }
6b7c5b94 1206
6b7c5b94
SP		 1207 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1208
1209 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1210
b31c50a7 1211 status = be_mbox_notify_wait(adapter);
6b7c5b94 1212 if (!status) {
b31c50a7 1213 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
03d28ffe 1214
6b7c5b94
SP		 1215 cq->id = le16_to_cpu(resp->cq_id);
1216 cq->created = true;
1217 }
b31c50a7 1218
2984961c 1219 mutex_unlock(&adapter->mbox_lock);
5fb379ee
SP		 1220
1221 return status;
1222}
1223
1224static u32 be_encoded_q_len(int q_len)
1225{
1226 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
03d28ffe 1227
5fb379ee
SP		 1228 if (len_encoded == 16)
1229 len_encoded = 0;
1230 return len_encoded;
1231}
1232
4188e7df 1233static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1234 struct be_queue_info *mccq,
1235 struct be_queue_info *cq)
5fb379ee 1236{
b31c50a7 1237 struct be_mcc_wrb *wrb;
34b1ef04 1238 struct be_cmd_req_mcc_ext_create *req;
5fb379ee 1239 struct be_dma_mem *q_mem = &mccq->dma_mem;
b31c50a7 1240 void *ctxt;
5fb379ee
SP		 1241 int status;
1242
2984961c
IV		 1243 if (mutex_lock_interruptible(&adapter->mbox_lock))
1244 return -1;
b31c50a7
SP		 1245
1246 wrb = wrb_from_mbox(adapter);
1247 req = embedded_payload(wrb);
1248 ctxt = &req->context;
5fb379ee 1249
106df1e3 1250 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1251 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1252 NULL);
5fb379ee 1253
d4a2ac3e 1254 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
666d39c7 1255 if (BEx_chip(adapter)) {
fe6d2a38
SP		 1256 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1257 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1258 be_encoded_q_len(mccq->len));
fe6d2a38 1259 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
666d39c7
VV		 1260 } else {
1261 req->hdr.version = 1;
1262 req->cq_id = cpu_to_le16(cq->id);
1263
1264 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1265 be_encoded_q_len(mccq->len));
1266 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1267 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1268 ctxt, cq->id);
1269 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1270 ctxt, 1);
fe6d2a38 1271 }
5fb379ee 1272
21252377
VV		 1273 /* Subscribe to Link State, Sliport Event and Group 5 Events
1274 * (bits 1, 5 and 17 set)
1275 */
1276 req->async_event_bitmap[0] =
1277 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1278 BIT(ASYNC_EVENT_CODE_GRP_5) |
1279 BIT(ASYNC_EVENT_CODE_QNQ) |
1280 BIT(ASYNC_EVENT_CODE_SLIPORT));
1281
5fb379ee
SP		 1282 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1283
1284 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1285
b31c50a7 1286 status = be_mbox_notify_wait(adapter);
5fb379ee
SP		 1287 if (!status) {
1288 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1289
5fb379ee
SP		 1290 mccq->id = le16_to_cpu(resp->id);
1291 mccq->created = true;
1292 }
2984961c 1293 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 1294
1295 return status;
1296}
1297
4188e7df 1298static int be_cmd_mccq_org_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1299 struct be_queue_info *mccq,
1300 struct be_queue_info *cq)
34b1ef04
SK		 1301{
1302 struct be_mcc_wrb *wrb;
1303 struct be_cmd_req_mcc_create *req;
1304 struct be_dma_mem *q_mem = &mccq->dma_mem;
1305 void *ctxt;
1306 int status;
1307
1308 if (mutex_lock_interruptible(&adapter->mbox_lock))
1309 return -1;
1310
1311 wrb = wrb_from_mbox(adapter);
1312 req = embedded_payload(wrb);
1313 ctxt = &req->context;
1314
106df1e3 1315 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1316 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1317 NULL);
34b1ef04
SK		 1318
1319 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1320
1321 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1322 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
a2cc4e0b 1323 be_encoded_q_len(mccq->len));
34b1ef04
SK		 1324 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1325
1326 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1327
1328 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1329
1330 status = be_mbox_notify_wait(adapter);
1331 if (!status) {
1332 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
03d28ffe 1333
34b1ef04
SK		 1334 mccq->id = le16_to_cpu(resp->id);
1335 mccq->created = true;
1336 }
1337
1338 mutex_unlock(&adapter->mbox_lock);
1339 return status;
1340}
1341
1342int be_cmd_mccq_create(struct be_adapter *adapter,
a2cc4e0b 1343 struct be_queue_info *mccq, struct be_queue_info *cq)
34b1ef04
SK		 1344{
1345 int status;
1346
1347 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
666d39c7 1348 if (status && BEx_chip(adapter)) {
34b1ef04
SK		 1349 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1350 "or newer to avoid conflicting priorities between NIC "
1351 "and FCoE traffic");
1352 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1353 }
1354 return status;
1355}
1356
94d73aaa 1357int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
6b7c5b94 1358{
7707133c 1359 struct be_mcc_wrb wrb = {0};
b31c50a7 1360 struct be_cmd_req_eth_tx_create *req;
94d73aaa
VV		 1361 struct be_queue_info *txq = &txo->q;
1362 struct be_queue_info *cq = &txo->cq;
6b7c5b94 1363 struct be_dma_mem *q_mem = &txq->dma_mem;
94d73aaa 1364 int status, ver = 0;
6b7c5b94 1365
7707133c 1366 req = embedded_payload(&wrb);
106df1e3 1367 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1368 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
6b7c5b94 1369
8b7756ca
PR		 1370 if (lancer_chip(adapter)) {
1371 req->hdr.version = 1;
94d73aaa
VV		 1372 } else if (BEx_chip(adapter)) {
1373 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1374 req->hdr.version = 2;
1375 } else { /* For SH */
1376 req->hdr.version = 2;
8b7756ca
PR		 1377 }
1378
81b02655
VV		 1379 if (req->hdr.version > 0)
1380 req->if_id = cpu_to_le16(adapter->if_handle);
6b7c5b94
SP		 1381 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1382 req->ulp_num = BE_ULP1_NUM;
1383 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
94d73aaa
VV		 1384 req->cq_id = cpu_to_le16(cq->id);
1385 req->queue_size = be_encoded_q_len(txq->len);
6b7c5b94 1386 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
94d73aaa
VV		 1387 ver = req->hdr.version;
1388
7707133c 1389 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1390 if (!status) {
7707133c 1391 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
03d28ffe 1392
6b7c5b94 1393 txq->id = le16_to_cpu(resp->cid);
94d73aaa
VV		 1394 if (ver == 2)
1395 txo->db_offset = le32_to_cpu(resp->db_offset);
1396 else
1397 txo->db_offset = DB_TXULP1_OFFSET;
6b7c5b94
SP		 1398 txq->created = true;
1399 }
b31c50a7 1400
6b7c5b94
SP		 1401 return status;
1402}
1403
482c9e79 1404/* Uses MCC */
8788fdc2 1405int be_cmd_rxq_create(struct be_adapter *adapter,
a2cc4e0b
SP		 1406 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1407 u32 if_id, u32 rss, u8 *rss_id)
6b7c5b94 1408{
b31c50a7
SP		 1409 struct be_mcc_wrb *wrb;
1410 struct be_cmd_req_eth_rx_create *req;
6b7c5b94
SP		 1411 struct be_dma_mem *q_mem = &rxq->dma_mem;
1412 int status;
1413
b7172414 1414 mutex_lock(&adapter->mcc_lock);
b31c50a7 1415
482c9e79
SP		 1416 wrb = wrb_from_mccq(adapter);
1417 if (!wrb) {
1418 status = -EBUSY;
1419 goto err;
1420 }
b31c50a7 1421 req = embedded_payload(wrb);
6b7c5b94 1422
106df1e3 1423 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1424 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
6b7c5b94
SP		 1425
1426 req->cq_id = cpu_to_le16(cq_id);
1427 req->frag_size = fls(frag_size) - 1;
1428 req->num_pages = 2;
1429 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1430 req->interface_id = cpu_to_le32(if_id);
10ef9ab4 1431 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
6b7c5b94
SP		 1432 req->rss_queue = cpu_to_le32(rss);
1433
482c9e79 1434 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1435 if (!status) {
1436 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
03d28ffe 1437
6b7c5b94
SP		 1438 rxq->id = le16_to_cpu(resp->id);
1439 rxq->created = true;
3abcdeda 1440 *rss_id = resp->rss_id;
6b7c5b94 1441 }
b31c50a7 1442
482c9e79 1443err:
b7172414 1444 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1445 return status;
1446}
1447
b31c50a7
SP		 1448/* Generic destroyer function for all types of queues
1449 * Uses Mbox
1450 */
8788fdc2 1451int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
a2cc4e0b 1452 int queue_type)
6b7c5b94 1453{
b31c50a7
SP		 1454 struct be_mcc_wrb *wrb;
1455 struct be_cmd_req_q_destroy *req;
6b7c5b94
SP		 1456 u8 subsys = 0, opcode = 0;
1457 int status;
1458
2984961c
IV		 1459 if (mutex_lock_interruptible(&adapter->mbox_lock))
1460 return -1;
6b7c5b94 1461
b31c50a7
SP		 1462 wrb = wrb_from_mbox(adapter);
1463 req = embedded_payload(wrb);
1464
6b7c5b94
SP		 1465 switch (queue_type) {
1466 case QTYPE_EQ:
1467 subsys = CMD_SUBSYSTEM_COMMON;
1468 opcode = OPCODE_COMMON_EQ_DESTROY;
1469 break;
1470 case QTYPE_CQ:
1471 subsys = CMD_SUBSYSTEM_COMMON;
1472 opcode = OPCODE_COMMON_CQ_DESTROY;
1473 break;
1474 case QTYPE_TXQ:
1475 subsys = CMD_SUBSYSTEM_ETH;
1476 opcode = OPCODE_ETH_TX_DESTROY;
1477 break;
1478 case QTYPE_RXQ:
1479 subsys = CMD_SUBSYSTEM_ETH;
1480 opcode = OPCODE_ETH_RX_DESTROY;
1481 break;
5fb379ee
SP		 1482 case QTYPE_MCCQ:
1483 subsys = CMD_SUBSYSTEM_COMMON;
1484 opcode = OPCODE_COMMON_MCC_DESTROY;
1485 break;
6b7c5b94 1486 default:
5f0b849e 1487 BUG();
6b7c5b94 1488 }
d744b44e 1489
106df1e3 1490 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
a2cc4e0b 1491 NULL);
6b7c5b94
SP		 1492 req->id = cpu_to_le16(q->id);
1493
b31c50a7 1494 status = be_mbox_notify_wait(adapter);
aa790db9 1495 q->created = false;
5f0b849e 1496
2984961c 1497 mutex_unlock(&adapter->mbox_lock);
482c9e79
SP		 1498 return status;
1499}
6b7c5b94 1500
482c9e79
SP		 1501/* Uses MCC */
1502int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1503{
1504 struct be_mcc_wrb *wrb;
1505 struct be_cmd_req_q_destroy *req;
1506 int status;
1507
b7172414 1508 mutex_lock(&adapter->mcc_lock);
482c9e79
SP		 1509
1510 wrb = wrb_from_mccq(adapter);
1511 if (!wrb) {
1512 status = -EBUSY;
1513 goto err;
1514 }
1515 req = embedded_payload(wrb);
1516
106df1e3 1517 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 1518 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
482c9e79
SP		 1519 req->id = cpu_to_le16(q->id);
1520
1521 status = be_mcc_notify_wait(adapter);
aa790db9 1522 q->created = false;
482c9e79
SP		 1523
1524err:
b7172414 1525 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1526 return status;
1527}
1528
b31c50a7 1529/* Create an rx filtering policy configuration on an i/f
bea50988 1530 * Will use MBOX only if MCCQ has not been created.
b31c50a7 1531 */
73d540f2 1532int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1578e777 1533 u32 *if_handle, u32 domain)
6b7c5b94 1534{
bea50988 1535 struct be_mcc_wrb wrb = {0};
b31c50a7 1536 struct be_cmd_req_if_create *req;
6b7c5b94
SP		 1537 int status;
1538
bea50988 1539 req = embedded_payload(&wrb);
106df1e3 1540 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1541 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1542 sizeof(*req), &wrb, NULL);
ba343c77 1543 req->hdr.domain = domain;
73d540f2
SP		 1544 req->capability_flags = cpu_to_le32(cap_flags);
1545 req->enable_flags = cpu_to_le32(en_flags);
1578e777 1546 req->pmac_invalid = true;
6b7c5b94 1547
bea50988 1548 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94 1549 if (!status) {
bea50988 1550 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
03d28ffe 1551
6b7c5b94 1552 *if_handle = le32_to_cpu(resp->interface_id);
b5bb9776
SP		 1553
1554 /* Hack to retrieve VF's pmac-id on BE3 */
18c57c74 1555 if (BE3_chip(adapter) && be_virtfn(adapter))
b5bb9776 1556 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
6b7c5b94 1557 }
6b7c5b94
SP		 1558 return status;
1559}
1560
62219066 1561/* Uses MCCQ if available else MBOX */
30128031 1562int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
6b7c5b94 1563{
62219066 1564 struct be_mcc_wrb wrb = {0};
b31c50a7 1565 struct be_cmd_req_if_destroy *req;
6b7c5b94
SP		 1566 int status;
1567
30128031 1568 if (interface_id == -1)
f9449ab7 1569 return 0;
b31c50a7 1570
62219066 1571 req = embedded_payload(&wrb);
6b7c5b94 1572
106df1e3 1573 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 1574 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
62219066 1575 sizeof(*req), &wrb, NULL);
658681f7 1576 req->hdr.domain = domain;
6b7c5b94 1577 req->interface_id = cpu_to_le32(interface_id);
b31c50a7 1578
62219066 1579 status = be_cmd_notify_wait(adapter, &wrb);
6b7c5b94
SP		 1580 return status;
1581}
1582
1583/* Get stats is a non embedded command: the request is not embedded inside
1584 * WRB but is a separate dma memory block
b31c50a7 1585 * Uses asynchronous MCC
6b7c5b94 1586 */
8788fdc2 1587int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
6b7c5b94 1588{
b31c50a7 1589 struct be_mcc_wrb *wrb;
89a88ab8 1590 struct be_cmd_req_hdr *hdr;
713d0394 1591 int status = 0;
6b7c5b94 1592
b7172414 1593 mutex_lock(&adapter->mcc_lock);
6b7c5b94 1594
b31c50a7 1595 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1596 if (!wrb) {
1597 status = -EBUSY;
1598 goto err;
1599 }
89a88ab8 1600 hdr = nonemb_cmd->va;
6b7c5b94 1601
106df1e3 1602 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1603 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1604 nonemb_cmd);
89a88ab8 1605
ca34fe38 1606 /* version 1 of the cmd is not supported only by BE2 */
61000861
AK		 1607 if (BE2_chip(adapter))
1608 hdr->version = 0;
1609 if (BE3_chip(adapter) || lancer_chip(adapter))
89a88ab8 1610 hdr->version = 1;
61000861
AK		 1611 else
1612 hdr->version = 2;
89a88ab8 1613
efaa408e
SR		 1614 status = be_mcc_notify(adapter);
1615 if (status)
1616 goto err;
1617
b2aebe6d 1618 adapter->stats_cmd_sent = true;
6b7c5b94 1619
713d0394 1620err:
b7172414 1621 mutex_unlock(&adapter->mcc_lock);
713d0394 1622 return status;
6b7c5b94
SP		 1623}
1624
005d5696
SX		 1625/* Lancer Stats */
1626int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
a2cc4e0b 1627 struct be_dma_mem *nonemb_cmd)
005d5696 1628{
005d5696
SX		 1629 struct be_mcc_wrb *wrb;
1630 struct lancer_cmd_req_pport_stats *req;
005d5696
SX		 1631 int status = 0;
1632
f25b119c
PR		 1633 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1634 CMD_SUBSYSTEM_ETH))
1635 return -EPERM;
1636
b7172414 1637 mutex_lock(&adapter->mcc_lock);
005d5696
SX		 1638
1639 wrb = wrb_from_mccq(adapter);
1640 if (!wrb) {
1641 status = -EBUSY;
1642 goto err;
1643 }
1644 req = nonemb_cmd->va;
005d5696 1645
106df1e3 1646 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 1647 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1648 wrb, nonemb_cmd);
005d5696 1649
d51ebd33 1650 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
005d5696
SX		 1651 req->cmd_params.params.reset_stats = 0;
1652
efaa408e
SR		 1653 status = be_mcc_notify(adapter);
1654 if (status)
1655 goto err;
1656
005d5696
SX		 1657 adapter->stats_cmd_sent = true;
1658
1659err:
b7172414 1660 mutex_unlock(&adapter->mcc_lock);
005d5696
SX		 1661 return status;
1662}
1663
323ff71e
SP		 1664static int be_mac_to_link_speed(int mac_speed)
1665{
1666 switch (mac_speed) {
1667 case PHY_LINK_SPEED_ZERO:
1668 return 0;
1669 case PHY_LINK_SPEED_10MBPS:
1670 return 10;
1671 case PHY_LINK_SPEED_100MBPS:
1672 return 100;
1673 case PHY_LINK_SPEED_1GBPS:
1674 return 1000;
1675 case PHY_LINK_SPEED_10GBPS:
1676 return 10000;
b971f847
VV		 1677 case PHY_LINK_SPEED_20GBPS:
1678 return 20000;
1679 case PHY_LINK_SPEED_25GBPS:
1680 return 25000;
1681 case PHY_LINK_SPEED_40GBPS:
1682 return 40000;
323ff71e
SP		 1683 }
1684 return 0;
1685}
1686
1687/* Uses synchronous mcc
1688 * Returns link_speed in Mbps
1689 */
1690int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1691 u8 *link_status, u32 dom)
6b7c5b94 1692{
b31c50a7
SP		 1693 struct be_mcc_wrb *wrb;
1694 struct be_cmd_req_link_status *req;
6b7c5b94
SP		 1695 int status;
1696
b7172414 1697 mutex_lock(&adapter->mcc_lock);
b31c50a7 1698
b236916a
AK		 1699 if (link_status)
1700 *link_status = LINK_DOWN;
1701
b31c50a7 1702 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1703 if (!wrb) {
1704 status = -EBUSY;
1705 goto err;
1706 }
b31c50a7 1707 req = embedded_payload(wrb);
a8f447bd 1708
57cd80d4 1709 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1710 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1711 sizeof(*req), wrb, NULL);
57cd80d4 1712
ca34fe38
SP		 1713 /* version 1 of the cmd is not supported only by BE2 */
1714 if (!BE2_chip(adapter))
daad6167
PR		 1715 req->hdr.version = 1;
1716
57cd80d4 1717 req->hdr.domain = dom;
6b7c5b94 1718
b31c50a7 1719 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1720 if (!status) {
1721 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
03d28ffe 1722
323ff71e
SP		 1723 if (link_speed) {
1724 *link_speed = resp->link_speed ?
1725 le16_to_cpu(resp->link_speed) * 10 :
1726 be_mac_to_link_speed(resp->mac_speed);
1727
1728 if (!resp->logical_link_status)
1729 *link_speed = 0;
0388f251 1730 }
b236916a
AK		 1731 if (link_status)
1732 *link_status = resp->logical_link_status;
6b7c5b94
SP		 1733 }
1734
713d0394 1735err:
b7172414 1736 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1737 return status;
1738}
1739
609ff3bb
AK		 1740/* Uses synchronous mcc */
1741int be_cmd_get_die_temperature(struct be_adapter *adapter)
1742{
1743 struct be_mcc_wrb *wrb;
1744 struct be_cmd_req_get_cntl_addnl_attribs *req;
117affe3 1745 int status = 0;
609ff3bb 1746
b7172414 1747 mutex_lock(&adapter->mcc_lock);
609ff3bb
AK		 1748
1749 wrb = wrb_from_mccq(adapter);
1750 if (!wrb) {
1751 status = -EBUSY;
1752 goto err;
1753 }
1754 req = embedded_payload(wrb);
1755
106df1e3 1756 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1757 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1758 sizeof(*req), wrb, NULL);
609ff3bb 1759
efaa408e 1760 status = be_mcc_notify(adapter);
609ff3bb 1761err:
b7172414 1762 mutex_unlock(&adapter->mcc_lock);
609ff3bb
AK		 1763 return status;
1764}
1765
311fddc7 1766/* Uses synchronous mcc */
fd7ff6f0 1767int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
311fddc7 1768{
fd7ff6f0 1769 struct be_mcc_wrb wrb = {0};
311fddc7
SK		 1770 struct be_cmd_req_get_fat *req;
1771 int status;
1772
fd7ff6f0 1773 req = embedded_payload(&wrb);
311fddc7 1774
106df1e3 1775 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
fd7ff6f0
VD		 1776 OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1777 &wrb, NULL);
311fddc7 1778 req->fat_operation = cpu_to_le32(QUERY_FAT);
fd7ff6f0 1779 status = be_cmd_notify_wait(adapter, &wrb);
311fddc7 1780 if (!status) {
fd7ff6f0 1781 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
03d28ffe 1782
fd7ff6f0
VD		 1783 if (dump_size && resp->log_size)
1784 *dump_size = le32_to_cpu(resp->log_size) -
fe2a70ee 1785 sizeof(u32);
311fddc7 1786 }
311fddc7
SK		 1787 return status;
1788}
1789
fd7ff6f0 1790int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
311fddc7
SK		 1791{
1792 struct be_dma_mem get_fat_cmd;
1793 struct be_mcc_wrb *wrb;
1794 struct be_cmd_req_get_fat *req;
fe2a70ee
SK		 1795 u32 offset = 0, total_size, buf_size,
1796 log_offset = sizeof(u32), payload_len;
fd7ff6f0 1797 int status;
311fddc7
SK		 1798
1799 if (buf_len == 0)
fd7ff6f0 1800 return 0;
311fddc7
SK		 1801
1802 total_size = buf_len;
1803
fe2a70ee 1804 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
750afb08
LC		 1805 get_fat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
1806 get_fat_cmd.size,
1807 &get_fat_cmd.dma, GFP_ATOMIC);
fd7ff6f0 1808 if (!get_fat_cmd.va)
c5f156de 1809 return -ENOMEM;
fe2a70ee 1810
b7172414 1811 mutex_lock(&adapter->mcc_lock);
311fddc7 1812
311fddc7
SK		 1813 while (total_size) {
1814 buf_size = min(total_size, (u32)60*1024);
1815 total_size -= buf_size;
1816
fe2a70ee
SK		 1817 wrb = wrb_from_mccq(adapter);
1818 if (!wrb) {
1819 status = -EBUSY;
311fddc7
SK		 1820 goto err;
1821 }
1822 req = get_fat_cmd.va;
311fddc7 1823
fe2a70ee 1824 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
106df1e3 1825 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1826 OPCODE_COMMON_MANAGE_FAT, payload_len,
1827 wrb, &get_fat_cmd);
311fddc7
SK		 1828
1829 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1830 req->read_log_offset = cpu_to_le32(log_offset);
1831 req->read_log_length = cpu_to_le32(buf_size);
1832 req->data_buffer_size = cpu_to_le32(buf_size);
1833
1834 status = be_mcc_notify_wait(adapter);
1835 if (!status) {
1836 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
03d28ffe 1837
311fddc7 1838 memcpy(buf + offset,
a2cc4e0b
SP		 1839 resp->data_buffer,
1840 le32_to_cpu(resp->read_log_length));
fe2a70ee 1841 } else {
311fddc7 1842 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
fe2a70ee
SK		 1843 goto err;
1844 }
311fddc7
SK		 1845 offset += buf_size;
1846 log_offset += buf_size;
1847 }
1848err:
e51000db
SB		 1849 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1850 get_fat_cmd.va, get_fat_cmd.dma);
b7172414 1851 mutex_unlock(&adapter->mcc_lock);
c5f156de 1852 return status;
311fddc7
SK		 1853}
1854
04b71175 1855/* Uses synchronous mcc */
e97e3cda 1856int be_cmd_get_fw_ver(struct be_adapter *adapter)
6b7c5b94 1857{
b31c50a7
SP		 1858 struct be_mcc_wrb *wrb;
1859 struct be_cmd_req_get_fw_version *req;
6b7c5b94
SP		 1860 int status;
1861
b7172414 1862 mutex_lock(&adapter->mcc_lock);
b31c50a7 1863
04b71175
SP		 1864 wrb = wrb_from_mccq(adapter);
1865 if (!wrb) {
1866 status = -EBUSY;
1867 goto err;
1868 }
6b7c5b94 1869
04b71175 1870 req = embedded_payload(wrb);
6b7c5b94 1871
106df1e3 1872 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1873 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1874 NULL);
04b71175 1875 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 1876 if (!status) {
1877 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
acbafeb1 1878
242eb470
VV		 1879 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1880 sizeof(adapter->fw_ver));
1881 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1882 sizeof(adapter->fw_on_flash));
6b7c5b94 1883 }
04b71175 1884err:
b7172414 1885 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1886 return status;
1887}
1888
b31c50a7
SP		 1889/* set the EQ delay interval of an EQ to specified value
1890 * Uses async mcc
1891 */
b502ae8d
KA		 1892static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1893 struct be_set_eqd *set_eqd, int num)
6b7c5b94 1894{
b31c50a7
SP		 1895 struct be_mcc_wrb *wrb;
1896 struct be_cmd_req_modify_eq_delay *req;
2632bafd 1897 int status = 0, i;
6b7c5b94 1898
b7172414 1899 mutex_lock(&adapter->mcc_lock);
b31c50a7
SP		 1900
1901 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1902 if (!wrb) {
1903 status = -EBUSY;
1904 goto err;
1905 }
b31c50a7 1906 req = embedded_payload(wrb);
6b7c5b94 1907
106df1e3 1908 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1909 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1910 NULL);
6b7c5b94 1911
2632bafd
SP		 1912 req->num_eq = cpu_to_le32(num);
1913 for (i = 0; i < num; i++) {
1914 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1915 req->set_eqd[i].phase = 0;
1916 req->set_eqd[i].delay_multiplier =
1917 cpu_to_le32(set_eqd[i].delay_multiplier);
1918 }
6b7c5b94 1919
efaa408e 1920 status = be_mcc_notify(adapter);
713d0394 1921err:
b7172414 1922 mutex_unlock(&adapter->mcc_lock);
713d0394 1923 return status;
6b7c5b94
SP		 1924}
1925
93676703
KA		 1926int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1927 int num)
1928{
1929 int num_eqs, i = 0;
1930
c8ba4ad0
SR		 1931 while (num) {
1932 num_eqs = min(num, 8);
1933 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1934 i += num_eqs;
1935 num -= num_eqs;
93676703
KA		 1936 }
1937
1938 return 0;
1939}
1940
b31c50a7 1941/* Uses sycnhronous mcc */
8788fdc2 1942int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 1943 u32 num, u32 domain)
6b7c5b94 1944{
b31c50a7
SP		 1945 struct be_mcc_wrb *wrb;
1946 struct be_cmd_req_vlan_config *req;
6b7c5b94
SP		 1947 int status;
1948
b7172414 1949 mutex_lock(&adapter->mcc_lock);
b31c50a7
SP		 1950
1951 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1952 if (!wrb) {
1953 status = -EBUSY;
1954 goto err;
1955 }
b31c50a7 1956 req = embedded_payload(wrb);
6b7c5b94 1957
106df1e3 1958 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1959 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1960 wrb, NULL);
435452aa 1961 req->hdr.domain = domain;
6b7c5b94
SP		 1962
1963 req->interface_id = if_id;
012bd387 1964 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
6b7c5b94 1965 req->num_vlan = num;
4d567d97
KA		 1966 memcpy(req->normal_vlan, vtag_array,
1967 req->num_vlan * sizeof(vtag_array[0]));
6b7c5b94 1968
b31c50a7 1969 status = be_mcc_notify_wait(adapter);
713d0394 1970err:
b7172414 1971 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 1972 return status;
1973}
1974
ac34b743 1975static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
6b7c5b94 1976{
6ac7b687 1977 struct be_mcc_wrb *wrb;
5b8821b7
SP		 1978 struct be_dma_mem *mem = &adapter->rx_filter;
1979 struct be_cmd_req_rx_filter *req = mem->va;
e7b909a6 1980 int status;
6b7c5b94 1981
b7172414 1982 mutex_lock(&adapter->mcc_lock);
6ac7b687 1983
b31c50a7 1984 wrb = wrb_from_mccq(adapter);
713d0394
SP		 1985 if (!wrb) {
1986 status = -EBUSY;
1987 goto err;
1988 }
5b8821b7 1989 memset(req, 0, sizeof(*req));
106df1e3 1990 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 1991 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1992 wrb, mem);
6b7c5b94 1993
5b8821b7 1994 req->if_id = cpu_to_le32(adapter->if_handle);
ac34b743
SP		 1995 req->if_flags_mask = cpu_to_le32(flags);
1996 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1997
1998 if (flags & BE_IF_FLAGS_MULTICAST) {
b7172414 1999 int i;
24307eef 2000
1610c79f
PR		 2001 /* Reset mcast promisc mode if already set by setting mask
2002 * and not setting flags field
2003 */
abb93951
PR		 2004 req->if_flags_mask |=
2005 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
92bf14ab 2006 be_if_cap_flags(adapter));
b7172414
SP		 2007 req->mcast_num = cpu_to_le32(adapter->mc_count);
2008 for (i = 0; i < adapter->mc_count; i++)
2009 ether_addr_copy(req->mcast_mac[i].byte,
2010 adapter->mc_list[i].mac);
6b7c5b94
SP		 2011 }
2012
b6588879 2013 status = be_mcc_notify_wait(adapter);
713d0394 2014err:
b7172414 2015 mutex_unlock(&adapter->mcc_lock);
e7b909a6 2016 return status;
6b7c5b94
SP		 2017}
2018
ac34b743
SP		 2019int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2020{
2021 struct device *dev = &adapter->pdev->dev;
2022
2023 if ((flags & be_if_cap_flags(adapter)) != flags) {
2024 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2025 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2026 be_if_cap_flags(adapter));
2027 }
2028 flags &= be_if_cap_flags(adapter);
196e3735
KA		 2029 if (!flags)
2030 return -ENOTSUPP;
ac34b743
SP		 2031
2032 return __be_cmd_rx_filter(adapter, flags, value);
2033}
2034
b31c50a7 2035/* Uses synchrounous mcc */
8788fdc2 2036int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
6b7c5b94 2037{
b31c50a7
SP		 2038 struct be_mcc_wrb *wrb;
2039 struct be_cmd_req_set_flow_control *req;
6b7c5b94
SP		 2040 int status;
2041
f25b119c
PR		 2042 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2043 CMD_SUBSYSTEM_COMMON))
2044 return -EPERM;
2045
b7172414 2046 mutex_lock(&adapter->mcc_lock);
6b7c5b94 2047
b31c50a7 2048 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2049 if (!wrb) {
2050 status = -EBUSY;
2051 goto err;
2052 }
b31c50a7 2053 req = embedded_payload(wrb);
6b7c5b94 2054
106df1e3 2055 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2056 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2057 wrb, NULL);
6b7c5b94 2058
b29812c1 2059 req->hdr.version = 1;
6b7c5b94
SP		 2060 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2061 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2062
b31c50a7 2063 status = be_mcc_notify_wait(adapter);
6b7c5b94 2064
713d0394 2065err:
b7172414 2066 mutex_unlock(&adapter->mcc_lock);
b29812c1
SR		 2067
2068 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2069 return -EOPNOTSUPP;
2070
6b7c5b94
SP		 2071 return status;
2072}
2073
b31c50a7 2074/* Uses sycn mcc */
8788fdc2 2075int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
6b7c5b94 2076{
b31c50a7
SP		 2077 struct be_mcc_wrb *wrb;
2078 struct be_cmd_req_get_flow_control *req;
6b7c5b94
SP		 2079 int status;
2080
f25b119c
PR		 2081 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2082 CMD_SUBSYSTEM_COMMON))
2083 return -EPERM;
2084
b7172414 2085 mutex_lock(&adapter->mcc_lock);
6b7c5b94 2086
b31c50a7 2087 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2088 if (!wrb) {
2089 status = -EBUSY;
2090 goto err;
2091 }
b31c50a7 2092 req = embedded_payload(wrb);
6b7c5b94 2093
106df1e3 2094 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2095 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2096 wrb, NULL);
6b7c5b94 2097
b31c50a7 2098 status = be_mcc_notify_wait(adapter);
6b7c5b94
SP		 2099 if (!status) {
2100 struct be_cmd_resp_get_flow_control *resp =
2101 embedded_payload(wrb);
03d28ffe 2102
6b7c5b94
SP		 2103 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2104 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2105 }
2106
713d0394 2107err:
b7172414 2108 mutex_unlock(&adapter->mcc_lock);
6b7c5b94
SP		 2109 return status;
2110}
2111
b31c50a7 2112/* Uses mbox */
e97e3cda 2113int be_cmd_query_fw_cfg(struct be_adapter *adapter)
6b7c5b94 2114{
b31c50a7
SP		 2115 struct be_mcc_wrb *wrb;
2116 struct be_cmd_req_query_fw_cfg *req;
6b7c5b94
SP		 2117 int status;
2118
2984961c
IV		 2119 if (mutex_lock_interruptible(&adapter->mbox_lock))
2120 return -1;
6b7c5b94 2121
b31c50a7
SP		 2122 wrb = wrb_from_mbox(adapter);
2123 req = embedded_payload(wrb);
6b7c5b94 2124
106df1e3 2125 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2126 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2127 sizeof(*req), wrb, NULL);
6b7c5b94 2128
b31c50a7 2129 status = be_mbox_notify_wait(adapter);
6b7c5b94
SP		 2130 if (!status) {
2131 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
03d28ffe 2132
e97e3cda
KA		 2133 adapter->port_num = le32_to_cpu(resp->phys_port);
2134 adapter->function_mode = le32_to_cpu(resp->function_mode);
2135 adapter->function_caps = le32_to_cpu(resp->function_caps);
2136 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
acbafeb1
SP		 2137 dev_info(&adapter->pdev->dev,
2138 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2139 adapter->function_mode, adapter->function_caps);
6b7c5b94
SP		 2140 }
2141
2984961c 2142 mutex_unlock(&adapter->mbox_lock);
6b7c5b94
SP		 2143 return status;
2144}
14074eab 2145
b31c50a7 2146/* Uses mbox */
14074eab 2147int be_cmd_reset_function(struct be_adapter *adapter)
2148{
b31c50a7
SP		 2149 struct be_mcc_wrb *wrb;
2150 struct be_cmd_req_hdr *req;
14074eab 2151 int status;
2152
bf99e50d 2153 if (lancer_chip(adapter)) {
9fa465c0
SP		 2154 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2155 adapter->db + SLIPORT_CONTROL_OFFSET);
bf99e50d 2156 status = lancer_wait_ready(adapter);
9fa465c0 2157 if (status)
bf99e50d
PR		 2158 dev_err(&adapter->pdev->dev,
2159 "Adapter in non recoverable error\n");
bf99e50d
PR		 2160 return status;
2161 }
2162
2984961c
IV		 2163 if (mutex_lock_interruptible(&adapter->mbox_lock))
2164 return -1;
14074eab 2165
b31c50a7
SP		 2166 wrb = wrb_from_mbox(adapter);
2167 req = embedded_payload(wrb);
14074eab 2168
106df1e3 2169 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2170 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2171 NULL);
14074eab 2172
b31c50a7 2173 status = be_mbox_notify_wait(adapter);
14074eab 2174
2984961c 2175 mutex_unlock(&adapter->mbox_lock);
14074eab 2176 return status;
2177}
84517482 2178
594ad54a 2179int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2180 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
3abcdeda
SP		 2181{
2182 struct be_mcc_wrb *wrb;
2183 struct be_cmd_req_rss_config *req;
3abcdeda
SP		 2184 int status;
2185
da1388d6
VV		 2186 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2187 return 0;
2188
b7172414 2189 mutex_lock(&adapter->mcc_lock);
3abcdeda 2190
b51aa367
KA		 2191 wrb = wrb_from_mccq(adapter);
2192 if (!wrb) {
2193 status = -EBUSY;
2194 goto err;
2195 }
3abcdeda
SP		 2196 req = embedded_payload(wrb);
2197
106df1e3 2198 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b 2199 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
3abcdeda
SP		 2200
2201 req->if_id = cpu_to_le32(adapter->if_handle);
594ad54a
SR		 2202 req->enable_rss = cpu_to_le16(rss_hash_opts);
2203 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
d3bd3a5e 2204
b51aa367 2205 if (!BEx_chip(adapter))
d3bd3a5e 2206 req->hdr.version = 1;
d3bd3a5e 2207
3abcdeda 2208 memcpy(req->cpu_table, rsstable, table_size);
e2557877 2209 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
3abcdeda
SP		 2210 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2211
b51aa367
KA		 2212 status = be_mcc_notify_wait(adapter);
2213err:
b7172414 2214 mutex_unlock(&adapter->mcc_lock);
3abcdeda
SP		 2215 return status;
2216}
2217
fad9ab2c
SB		 2218/* Uses sync mcc */
2219int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
a2cc4e0b 2220 u8 bcn, u8 sts, u8 state)
fad9ab2c
SB		 2221{
2222 struct be_mcc_wrb *wrb;
2223 struct be_cmd_req_enable_disable_beacon *req;
2224 int status;
2225
b7172414 2226 mutex_lock(&adapter->mcc_lock);
fad9ab2c
SB		 2227
2228 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2229 if (!wrb) {
2230 status = -EBUSY;
2231 goto err;
2232 }
fad9ab2c
SB		 2233 req = embedded_payload(wrb);
2234
106df1e3 2235 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2236 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2237 sizeof(*req), wrb, NULL);
fad9ab2c
SB		 2238
2239 req->port_num = port_num;
2240 req->beacon_state = state;
2241 req->beacon_duration = bcn;
2242 req->status_duration = sts;
2243
2244 status = be_mcc_notify_wait(adapter);
2245
713d0394 2246err:
b7172414 2247 mutex_unlock(&adapter->mcc_lock);
fad9ab2c
SB		 2248 return status;
2249}
2250
2251/* Uses sync mcc */
2252int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2253{
2254 struct be_mcc_wrb *wrb;
2255 struct be_cmd_req_get_beacon_state *req;
2256 int status;
2257
b7172414 2258 mutex_lock(&adapter->mcc_lock);
fad9ab2c
SB		 2259
2260 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2261 if (!wrb) {
2262 status = -EBUSY;
2263 goto err;
2264 }
fad9ab2c
SB		 2265 req = embedded_payload(wrb);
2266
106df1e3 2267 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2268 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2269 wrb, NULL);
fad9ab2c
SB		 2270
2271 req->port_num = port_num;
2272
2273 status = be_mcc_notify_wait(adapter);
2274 if (!status) {
2275 struct be_cmd_resp_get_beacon_state *resp =
2276 embedded_payload(wrb);
03d28ffe 2277
fad9ab2c
SB		 2278 *state = resp->beacon_state;
2279 }
2280
713d0394 2281err:
b7172414 2282 mutex_unlock(&adapter->mcc_lock);
fad9ab2c
SB		 2283 return status;
2284}
2285
e36edd9d
ML		 2286/* Uses sync mcc */
2287int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2288 u8 page_num, u8 *data)
2289{
2290 struct be_dma_mem cmd;
2291 struct be_mcc_wrb *wrb;
2292 struct be_cmd_req_port_type *req;
2293 int status;
2294
2295 if (page_num > TR_PAGE_A2)
2296 return -EINVAL;
2297
2298 cmd.size = sizeof(struct be_cmd_resp_port_type);
750afb08
LC		 2299 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2300 GFP_ATOMIC);
e36edd9d
ML		 2301 if (!cmd.va) {
2302 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2303 return -ENOMEM;
2304 }
e36edd9d 2305
b7172414 2306 mutex_lock(&adapter->mcc_lock);
e36edd9d
ML		 2307
2308 wrb = wrb_from_mccq(adapter);
2309 if (!wrb) {
2310 status = -EBUSY;
2311 goto err;
2312 }
2313 req = cmd.va;
2314
2315 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2316 OPCODE_COMMON_READ_TRANSRECV_DATA,
2317 cmd.size, wrb, &cmd);
2318
2319 req->port = cpu_to_le32(adapter->hba_port_num);
2320 req->page_num = cpu_to_le32(page_num);
2321 status = be_mcc_notify_wait(adapter);
2322 if (!status) {
2323 struct be_cmd_resp_port_type *resp = cmd.va;
2324
2325 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2326 }
2327err:
b7172414 2328 mutex_unlock(&adapter->mcc_lock);
e51000db 2329 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
e36edd9d
ML		 2330 return status;
2331}
2332
a23113b5
SR		 2333static int lancer_cmd_write_object(struct be_adapter *adapter,
2334 struct be_dma_mem *cmd, u32 data_size,
2335 u32 data_offset, const char *obj_name,
2336 u32 *data_written, u8 *change_status,
2337 u8 *addn_status)
485bf569
SN		 2338{
2339 struct be_mcc_wrb *wrb;
2340 struct lancer_cmd_req_write_object *req;
2341 struct lancer_cmd_resp_write_object *resp;
2342 void *ctxt = NULL;
2343 int status;
2344
b7172414 2345 mutex_lock(&adapter->mcc_lock);
485bf569
SN		 2346 adapter->flash_status = 0;
2347
2348 wrb = wrb_from_mccq(adapter);
2349 if (!wrb) {
2350 status = -EBUSY;
2351 goto err_unlock;
2352 }
2353
2354 req = embedded_payload(wrb);
2355
106df1e3 2356 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2357 OPCODE_COMMON_WRITE_OBJECT,
2358 sizeof(struct lancer_cmd_req_write_object), wrb,
2359 NULL);
485bf569
SN		 2360
2361 ctxt = &req->context;
2362 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2363 write_length, ctxt, data_size);
485bf569
SN		 2364
2365 if (data_size == 0)
2366 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2367 eof, ctxt, 1);
485bf569
SN		 2368 else
2369 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
a2cc4e0b 2370 eof, ctxt, 0);
485bf569
SN		 2371
2372 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2373 req->write_offset = cpu_to_le32(data_offset);
242eb470 2374 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
485bf569
SN		 2375 req->descriptor_count = cpu_to_le32(1);
2376 req->buf_len = cpu_to_le32(data_size);
2377 req->addr_low = cpu_to_le32((cmd->dma +
a2cc4e0b
SP		 2378 sizeof(struct lancer_cmd_req_write_object))
2379 & 0xFFFFFFFF);
485bf569
SN		 2380 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2381 sizeof(struct lancer_cmd_req_write_object)));
2382
efaa408e
SR		 2383 status = be_mcc_notify(adapter);
2384 if (status)
2385 goto err_unlock;
2386
b7172414 2387 mutex_unlock(&adapter->mcc_lock);
485bf569 2388
5eeff635 2389 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
701962d0 2390 msecs_to_jiffies(60000)))
fd45160c 2391 status = -ETIMEDOUT;
485bf569
SN		 2392 else
2393 status = adapter->flash_status;
2394
2395 resp = embedded_payload(wrb);
f67ef7ba 2396 if (!status) {
485bf569 2397 *data_written = le32_to_cpu(resp->actual_write_len);
f67ef7ba
PR		 2398 *change_status = resp->change_status;
2399 } else {
485bf569 2400 *addn_status = resp->additional_status;
f67ef7ba 2401 }
485bf569
SN		 2402
2403 return status;
2404
2405err_unlock:
b7172414 2406 mutex_unlock(&adapter->mcc_lock);
485bf569
SN		 2407 return status;
2408}
2409
6809cee0
RN		 2410int be_cmd_query_cable_type(struct be_adapter *adapter)
2411{
2412 u8 page_data[PAGE_DATA_LEN];
2413 int status;
2414
2415 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2416 page_data);
2417 if (!status) {
2418 switch (adapter->phy.interface_type) {
2419 case PHY_TYPE_QSFP:
2420 adapter->phy.cable_type =
2421 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2422 break;
2423 case PHY_TYPE_SFP_PLUS_10GB:
2424 adapter->phy.cable_type =
2425 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2426 break;
2427 default:
2428 adapter->phy.cable_type = 0;
2429 break;
2430 }
2431 }
2432 return status;
2433}
2434
21252377
VV		 2435int be_cmd_query_sfp_info(struct be_adapter *adapter)
2436{
2437 u8 page_data[PAGE_DATA_LEN];
2438 int status;
2439
2440 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2441 page_data);
2442 if (!status) {
2443 strlcpy(adapter->phy.vendor_name, page_data +
2444 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2445 strlcpy(adapter->phy.vendor_pn,
2446 page_data + SFP_VENDOR_PN_OFFSET,
2447 SFP_VENDOR_NAME_LEN - 1);
2448 }
2449
2450 return status;
2451}
2452
a23113b5
SR		 2453static int lancer_cmd_delete_object(struct be_adapter *adapter,
2454 const char *obj_name)
f0613380
KA		 2455{
2456 struct lancer_cmd_req_delete_object *req;
2457 struct be_mcc_wrb *wrb;
2458 int status;
2459
b7172414 2460 mutex_lock(&adapter->mcc_lock);
f0613380
KA		 2461
2462 wrb = wrb_from_mccq(adapter);
2463 if (!wrb) {
2464 status = -EBUSY;
2465 goto err;
2466 }
2467
2468 req = embedded_payload(wrb);
2469
2470 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2471 OPCODE_COMMON_DELETE_OBJECT,
2472 sizeof(*req), wrb, NULL);
2473
242eb470 2474 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
f0613380
KA		 2475
2476 status = be_mcc_notify_wait(adapter);
2477err:
b7172414 2478 mutex_unlock(&adapter->mcc_lock);
f0613380
KA		 2479 return status;
2480}
2481
de49bd5a 2482int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
a2cc4e0b
SP		 2483 u32 data_size, u32 data_offset, const char *obj_name,
2484 u32 *data_read, u32 *eof, u8 *addn_status)
de49bd5a
PR		 2485{
2486 struct be_mcc_wrb *wrb;
2487 struct lancer_cmd_req_read_object *req;
2488 struct lancer_cmd_resp_read_object *resp;
2489 int status;
2490
b7172414 2491 mutex_lock(&adapter->mcc_lock);
de49bd5a
PR		 2492
2493 wrb = wrb_from_mccq(adapter);
2494 if (!wrb) {
2495 status = -EBUSY;
2496 goto err_unlock;
2497 }
2498
2499 req = embedded_payload(wrb);
2500
2501 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2502 OPCODE_COMMON_READ_OBJECT,
2503 sizeof(struct lancer_cmd_req_read_object), wrb,
2504 NULL);
de49bd5a
PR		 2505
2506 req->desired_read_len = cpu_to_le32(data_size);
2507 req->read_offset = cpu_to_le32(data_offset);
2508 strcpy(req->object_name, obj_name);
2509 req->descriptor_count = cpu_to_le32(1);
2510 req->buf_len = cpu_to_le32(data_size);
2511 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2512 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2513
2514 status = be_mcc_notify_wait(adapter);
2515
2516 resp = embedded_payload(wrb);
2517 if (!status) {
2518 *data_read = le32_to_cpu(resp->actual_read_len);
2519 *eof = le32_to_cpu(resp->eof);
2520 } else {
2521 *addn_status = resp->additional_status;
2522 }
2523
2524err_unlock:
b7172414 2525 mutex_unlock(&adapter->mcc_lock);
de49bd5a
PR		 2526 return status;
2527}
2528
a23113b5
SR		 2529static int be_cmd_write_flashrom(struct be_adapter *adapter,
2530 struct be_dma_mem *cmd, u32 flash_type,
2531 u32 flash_opcode, u32 img_offset, u32 buf_size)
84517482 2532{
b31c50a7 2533 struct be_mcc_wrb *wrb;
3f0d4560 2534 struct be_cmd_write_flashrom *req;
84517482
AK		 2535 int status;
2536
b7172414 2537 mutex_lock(&adapter->mcc_lock);
dd131e76 2538 adapter->flash_status = 0;
b31c50a7
SP		 2539
2540 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2541 if (!wrb) {
2542 status = -EBUSY;
2892d9c2 2543 goto err_unlock;
713d0394
SP		 2544 }
2545 req = cmd->va;
84517482 2546
106df1e3 2547 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 2548 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2549 cmd);
84517482
AK		 2550
2551 req->params.op_type = cpu_to_le32(flash_type);
70a7b525
VV		 2552 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2553 req->params.offset = cpu_to_le32(img_offset);
2554
84517482
AK		 2555 req->params.op_code = cpu_to_le32(flash_opcode);
2556 req->params.data_buf_size = cpu_to_le32(buf_size);
2557
efaa408e
SR		 2558 status = be_mcc_notify(adapter);
2559 if (status)
2560 goto err_unlock;
2561
b7172414 2562 mutex_unlock(&adapter->mcc_lock);
dd131e76 2563
5eeff635
SR		 2564 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2565 msecs_to_jiffies(40000)))
fd45160c 2566 status = -ETIMEDOUT;
dd131e76
SB		 2567 else
2568 status = adapter->flash_status;
84517482 2569
2892d9c2
DC		 2570 return status;
2571
2572err_unlock:
b7172414 2573 mutex_unlock(&adapter->mcc_lock);
84517482
AK		 2574 return status;
2575}
fa9a6fed 2576
a23113b5
SR		 2577static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2578 u16 img_optype, u32 img_offset, u32 crc_offset)
fa9a6fed 2579{
be716446 2580 struct be_cmd_read_flash_crc *req;
70a7b525 2581 struct be_mcc_wrb *wrb;
fa9a6fed
SB		 2582 int status;
2583
b7172414 2584 mutex_lock(&adapter->mcc_lock);
fa9a6fed
SB		 2585
2586 wrb = wrb_from_mccq(adapter);
713d0394
SP		 2587 if (!wrb) {
2588 status = -EBUSY;
2589 goto err;
2590 }
fa9a6fed
SB		 2591 req = embedded_payload(wrb);
2592
106df1e3 2593 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
be716446
PR		 2594 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2595 wrb, NULL);
fa9a6fed 2596
70a7b525
VV		 2597 req->params.op_type = cpu_to_le32(img_optype);
2598 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2599 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2600 else
2601 req->params.offset = cpu_to_le32(crc_offset);
2602
fa9a6fed 2603 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
8b93b710 2604 req->params.data_buf_size = cpu_to_le32(0x4);
fa9a6fed
SB		 2605
2606 status = be_mcc_notify_wait(adapter);
2607 if (!status)
be716446 2608 memcpy(flashed_crc, req->crc, 4);
fa9a6fed 2609
713d0394 2610err:
b7172414 2611 mutex_unlock(&adapter->mcc_lock);
fa9a6fed
SB		 2612 return status;
2613}
71d8d1b5 2614
a23113b5
SR		 2615static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2616
2617static bool phy_flashing_required(struct be_adapter *adapter)
2618{
2619 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2620 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2621}
2622
2623static bool is_comp_in_ufi(struct be_adapter *adapter,
2624 struct flash_section_info *fsec, int type)
2625{
2626 int i = 0, img_type = 0;
2627 struct flash_section_info_g2 *fsec_g2 = NULL;
2628
2629 if (BE2_chip(adapter))
2630 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2631
2632 for (i = 0; i < MAX_FLASH_COMP; i++) {
2633 if (fsec_g2)
2634 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2635 else
2636 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2637
2638 if (img_type == type)
2639 return true;
2640 }
2641 return false;
2642}
2643
2644static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2645 int header_size,
2646 const struct firmware *fw)
2647{
2648 struct flash_section_info *fsec = NULL;
2649 const u8 *p = fw->data;
2650
2651 p += header_size;
2652 while (p < (fw->data + fw->size)) {
2653 fsec = (struct flash_section_info *)p;
2654 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2655 return fsec;
2656 p += 32;
2657 }
2658 return NULL;
2659}
2660
2661static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2662 u32 img_offset, u32 img_size, int hdr_size,
2663 u16 img_optype, bool *crc_match)
2664{
2665 u32 crc_offset;
2666 int status;
2667 u8 crc[4];
2668
2669 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2670 img_size - 4);
2671 if (status)
2672 return status;
2673
2674 crc_offset = hdr_size + img_offset + img_size - 4;
2675
2676 /* Skip flashing, if crc of flashed region matches */
2677 if (!memcmp(crc, p + crc_offset, 4))
2678 *crc_match = true;
2679 else
2680 *crc_match = false;
2681
2682 return status;
2683}
2684
2685static int be_flash(struct be_adapter *adapter, const u8 *img,
2686 struct be_dma_mem *flash_cmd, int optype, int img_size,
2687 u32 img_offset)
2688{
2689 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2690 struct be_cmd_write_flashrom *req = flash_cmd->va;
2691 int status;
2692
2693 while (total_bytes) {
2694 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2695
2696 total_bytes -= num_bytes;
2697
2698 if (!total_bytes) {
2699 if (optype == OPTYPE_PHY_FW)
2700 flash_op = FLASHROM_OPER_PHY_FLASH;
2701 else
2702 flash_op = FLASHROM_OPER_FLASH;
2703 } else {
2704 if (optype == OPTYPE_PHY_FW)
2705 flash_op = FLASHROM_OPER_PHY_SAVE;
2706 else
2707 flash_op = FLASHROM_OPER_SAVE;
2708 }
2709
2710 memcpy(req->data_buf, img, num_bytes);
2711 img += num_bytes;
2712 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2713 flash_op, img_offset +
2714 bytes_sent, num_bytes);
2715 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2716 optype == OPTYPE_PHY_FW)
2717 break;
2718 else if (status)
2719 return status;
2720
2721 bytes_sent += num_bytes;
2722 }
2723 return 0;
2724}
2725
f5ef017e
SB		 2726#define NCSI_UPDATE_LOG "NCSI section update is not supported in FW ver %s\n"
2727static bool be_fw_ncsi_supported(char *ver)
2728{
2729 int v1[4] = {3, 102, 148, 0}; /* Min ver that supports NCSI FW */
2730 int v2[4];
2731 int i;
2732
2733 if (sscanf(ver, "%d.%d.%d.%d", &v2[0], &v2[1], &v2[2], &v2[3]) != 4)
2734 return false;
2735
2736 for (i = 0; i < 4; i++) {
2737 if (v1[i] < v2[i])
2738 return true;
2739 else if (v1[i] > v2[i])
2740 return false;
2741 }
2742
2743 return true;
2744}
2745
a23113b5
SR		 2746/* For BE2, BE3 and BE3-R */
2747static int be_flash_BEx(struct be_adapter *adapter,
2748 const struct firmware *fw,
2749 struct be_dma_mem *flash_cmd, int num_of_images)
2750{
2751 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2752 struct device *dev = &adapter->pdev->dev;
2753 struct flash_section_info *fsec = NULL;
2754 int status, i, filehdr_size, num_comp;
2755 const struct flash_comp *pflashcomp;
2756 bool crc_match;
2757 const u8 *p;
2758
f4ee1476 2759 static const struct flash_comp gen3_flash_types[] = {
a23113b5
SR		 2760 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2761 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2762 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2763 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2764 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2765 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2766 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2767 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2768 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2769 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2770 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2771 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2772 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2773 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2774 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2775 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2776 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2777 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2778 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2779 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2780 };
2781
f4ee1476 2782 static const struct flash_comp gen2_flash_types[] = {
a23113b5
SR		 2783 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2784 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2785 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2786 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2787 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2788 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2789 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2790 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2791 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2792 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2793 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2794 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2795 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2796 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2797 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2798 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2799 };
2800
2801 if (BE3_chip(adapter)) {
2802 pflashcomp = gen3_flash_types;
2803 filehdr_size = sizeof(struct flash_file_hdr_g3);
2804 num_comp = ARRAY_SIZE(gen3_flash_types);
2805 } else {
2806 pflashcomp = gen2_flash_types;
2807 filehdr_size = sizeof(struct flash_file_hdr_g2);
2808 num_comp = ARRAY_SIZE(gen2_flash_types);
2809 img_hdrs_size = 0;
2810 }
2811
2812 /* Get flash section info*/
2813 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2814 if (!fsec) {
2815 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2816 return -1;
2817 }
2818 for (i = 0; i < num_comp; i++) {
2819 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2820 continue;
2821
2822 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
f5ef017e
SB		 2823 !be_fw_ncsi_supported(adapter->fw_ver)) {
2824 dev_info(dev, NCSI_UPDATE_LOG, adapter->fw_ver);
a23113b5 2825 continue;
f5ef017e 2826 }
a23113b5
SR		 2827
2828 if (pflashcomp[i].optype == OPTYPE_PHY_FW &&
2829 !phy_flashing_required(adapter))
2830 continue;
2831
2832 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2833 status = be_check_flash_crc(adapter, fw->data,
2834 pflashcomp[i].offset,
2835 pflashcomp[i].size,
2836 filehdr_size +
2837 img_hdrs_size,
2838 OPTYPE_REDBOOT, &crc_match);
2839 if (status) {
2840 dev_err(dev,
2841 "Could not get CRC for 0x%x region\n",
2842 pflashcomp[i].optype);
2843 continue;
2844 }
2845
2846 if (crc_match)
2847 continue;
2848 }
2849
2850 p = fw->data + filehdr_size + pflashcomp[i].offset +
2851 img_hdrs_size;
2852 if (p + pflashcomp[i].size > fw->data + fw->size)
2853 return -1;
2854
2855 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2856 pflashcomp[i].size, 0);
2857 if (status) {
2858 dev_err(dev, "Flashing section type 0x%x failed\n",
2859 pflashcomp[i].img_type);
2860 return status;
2861 }
2862 }
2863 return 0;
2864}
2865
2866static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2867{
2868 u32 img_type = le32_to_cpu(fsec_entry.type);
2869 u16 img_optype = le16_to_cpu(fsec_entry.optype);
2870
2871 if (img_optype != 0xFFFF)
2872 return img_optype;
2873
2874 switch (img_type) {
2875 case IMAGE_FIRMWARE_ISCSI:
2876 img_optype = OPTYPE_ISCSI_ACTIVE;
2877 break;
2878 case IMAGE_BOOT_CODE:
2879 img_optype = OPTYPE_REDBOOT;
2880 break;
2881 case IMAGE_OPTION_ROM_ISCSI:
2882 img_optype = OPTYPE_BIOS;
2883 break;
2884 case IMAGE_OPTION_ROM_PXE:
2885 img_optype = OPTYPE_PXE_BIOS;
2886 break;
2887 case IMAGE_OPTION_ROM_FCOE:
2888 img_optype = OPTYPE_FCOE_BIOS;
2889 break;
2890 case IMAGE_FIRMWARE_BACKUP_ISCSI:
2891 img_optype = OPTYPE_ISCSI_BACKUP;
2892 break;
2893 case IMAGE_NCSI:
2894 img_optype = OPTYPE_NCSI_FW;
2895 break;
2896 case IMAGE_FLASHISM_JUMPVECTOR:
2897 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2898 break;
2899 case IMAGE_FIRMWARE_PHY:
2900 img_optype = OPTYPE_SH_PHY_FW;
2901 break;
2902 case IMAGE_REDBOOT_DIR:
2903 img_optype = OPTYPE_REDBOOT_DIR;
2904 break;
2905 case IMAGE_REDBOOT_CONFIG:
2906 img_optype = OPTYPE_REDBOOT_CONFIG;
2907 break;
2908 case IMAGE_UFI_DIR:
2909 img_optype = OPTYPE_UFI_DIR;
2910 break;
2911 default:
2912 break;
2913 }
2914
2915 return img_optype;
2916}
2917
2918static int be_flash_skyhawk(struct be_adapter *adapter,
2919 const struct firmware *fw,
2920 struct be_dma_mem *flash_cmd, int num_of_images)
2921{
2922 int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2923 bool crc_match, old_fw_img, flash_offset_support = true;
2924 struct device *dev = &adapter->pdev->dev;
2925 struct flash_section_info *fsec = NULL;
2926 u32 img_offset, img_size, img_type;
2927 u16 img_optype, flash_optype;
2928 int status, i, filehdr_size;
2929 const u8 *p;
2930
2931 filehdr_size = sizeof(struct flash_file_hdr_g3);
2932 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2933 if (!fsec) {
2934 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2935 return -EINVAL;
2936 }
2937
2938retry_flash:
2939 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2940 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2941 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2942 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2943 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2944 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2945
2946 if (img_optype == 0xFFFF)
2947 continue;
2948
2949 if (flash_offset_support)
2950 flash_optype = OPTYPE_OFFSET_SPECIFIED;
2951 else
2952 flash_optype = img_optype;
2953
2954 /* Don't bother verifying CRC if an old FW image is being
2955 * flashed
2956 */
2957 if (old_fw_img)
2958 goto flash;
2959
2960 status = be_check_flash_crc(adapter, fw->data, img_offset,
2961 img_size, filehdr_size +
2962 img_hdrs_size, flash_optype,
2963 &crc_match);
2964 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2965 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2966 /* The current FW image on the card does not support
2967 * OFFSET based flashing. Retry using older mechanism
2968 * of OPTYPE based flashing
2969 */
2970 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2971 flash_offset_support = false;
2972 goto retry_flash;
2973 }
2974
2975 /* The current FW image on the card does not recognize
2976 * the new FLASH op_type. The FW download is partially
2977 * complete. Reboot the server now to enable FW image
2978 * to recognize the new FLASH op_type. To complete the
2979 * remaining process, download the same FW again after
2980 * the reboot.
2981 */
2982 dev_err(dev, "Flash incomplete. Reset the server\n");
2983 dev_err(dev, "Download FW image again after reset\n");
2984 return -EAGAIN;
2985 } else if (status) {
2986 dev_err(dev, "Could not get CRC for 0x%x region\n",
2987 img_optype);
2988 return -EFAULT;
2989 }
2990
2991 if (crc_match)
2992 continue;
2993
2994flash:
2995 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2996 if (p + img_size > fw->data + fw->size)
2997 return -1;
2998
2999 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
3000 img_offset);
3001
3002 /* The current FW image on the card does not support OFFSET
3003 * based flashing. Retry using older mechanism of OPTYPE based
3004 * flashing
3005 */
3006 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
3007 flash_optype == OPTYPE_OFFSET_SPECIFIED) {
3008 flash_offset_support = false;
3009 goto retry_flash;
3010 }
3011
3012 /* For old FW images ignore ILLEGAL_FIELD error or errors on
3013 * UFI_DIR region
3014 */
3015 if (old_fw_img &&
3016 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
3017 (img_optype == OPTYPE_UFI_DIR &&
3018 base_status(status) == MCC_STATUS_FAILED))) {
3019 continue;
3020 } else if (status) {
3021 dev_err(dev, "Flashing section type 0x%x failed\n",
3022 img_type);
6b525782
SR		 3023
3024 switch (addl_status(status)) {
3025 case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3026 dev_err(dev,
3027 "Digital signature missing in FW\n");
3028 return -EINVAL;
3029 case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3030 dev_err(dev,
3031 "Invalid digital signature in FW\n");
3032 return -EINVAL;
3033 default:
3034 return -EFAULT;
3035 }
a23113b5
SR		 3036 }
3037 }
3038 return 0;
3039}
3040
3041int lancer_fw_download(struct be_adapter *adapter,
3042 const struct firmware *fw)
3043{
3044 struct device *dev = &adapter->pdev->dev;
3045 struct be_dma_mem flash_cmd;
3046 const u8 *data_ptr = NULL;
3047 u8 *dest_image_ptr = NULL;
3048 size_t image_size = 0;
3049 u32 chunk_size = 0;
3050 u32 data_written = 0;
3051 u32 offset = 0;
3052 int status = 0;
3053 u8 add_status = 0;
3054 u8 change_status;
3055
3056 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3057 dev_err(dev, "FW image size should be multiple of 4\n");
3058 return -EINVAL;
3059 }
3060
3061 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3062 + LANCER_FW_DOWNLOAD_CHUNK;
750afb08
LC		 3063 flash_cmd.va = dma_alloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3064 GFP_KERNEL);
a23113b5
SR		 3065 if (!flash_cmd.va)
3066 return -ENOMEM;
3067
3068 dest_image_ptr = flash_cmd.va +
3069 sizeof(struct lancer_cmd_req_write_object);
3070 image_size = fw->size;
3071 data_ptr = fw->data;
3072
3073 while (image_size) {
3074 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3075
3076 /* Copy the image chunk content. */
3077 memcpy(dest_image_ptr, data_ptr, chunk_size);
3078
3079 status = lancer_cmd_write_object(adapter, &flash_cmd,
3080 chunk_size, offset,
3081 LANCER_FW_DOWNLOAD_LOCATION,
3082 &data_written, &change_status,
3083 &add_status);
3084 if (status)
3085 break;
3086
3087 offset += data_written;
3088 data_ptr += data_written;
3089 image_size -= data_written;
3090 }
3091
3092 if (!status) {
3093 /* Commit the FW written */
3094 status = lancer_cmd_write_object(adapter, &flash_cmd,
3095 0, offset,
3096 LANCER_FW_DOWNLOAD_LOCATION,
3097 &data_written, &change_status,
3098 &add_status);
3099 }
3100
3101 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3102 if (status) {
3103 dev_err(dev, "Firmware load error\n");
3104 return be_cmd_status(status);
3105 }
3106
3107 dev_info(dev, "Firmware flashed successfully\n");
3108
3109 if (change_status == LANCER_FW_RESET_NEEDED) {
3110 dev_info(dev, "Resetting adapter to activate new FW\n");
3111 status = lancer_physdev_ctrl(adapter,
3112 PHYSDEV_CONTROL_FW_RESET_MASK);
3113 if (status) {
3114 dev_err(dev, "Adapter busy, could not reset FW\n");
3115 dev_err(dev, "Reboot server to activate new FW\n");
3116 }
3117 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3118 dev_info(dev, "Reboot server to activate new FW\n");
3119 }
3120
3121 return 0;
3122}
3123
3124/* Check if the flash image file is compatible with the adapter that
3125 * is being flashed.
3126 */
3127static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3128 struct flash_file_hdr_g3 *fhdr)
3129{
3130 if (!fhdr) {
3131 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3132 return false;
3133 }
3134
3135 /* First letter of the build version is used to identify
3136 * which chip this image file is meant for.
3137 */
3138 switch (fhdr->build[0]) {
3139 case BLD_STR_UFI_TYPE_SH:
3140 if (!skyhawk_chip(adapter))
3141 return false;
3142 break;
3143 case BLD_STR_UFI_TYPE_BE3:
3144 if (!BE3_chip(adapter))
3145 return false;
3146 break;
3147 case BLD_STR_UFI_TYPE_BE2:
3148 if (!BE2_chip(adapter))
3149 return false;
3150 break;
3151 default:
3152 return false;
3153 }
3154
3155 /* In BE3 FW images the "asic_type_rev" field doesn't track the
3156 * asic_rev of the chips it is compatible with.
3157 * When asic_type_rev is 0 the image is compatible only with
3158 * pre-BE3-R chips (asic_rev < 0x10)
3159 */
3160 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3161 return adapter->asic_rev < 0x10;
3162 else
3163 return (fhdr->asic_type_rev >= adapter->asic_rev);
3164}
3165
3166int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3167{
3168 struct device *dev = &adapter->pdev->dev;
3169 struct flash_file_hdr_g3 *fhdr3;
3170 struct image_hdr *img_hdr_ptr;
3171 int status = 0, i, num_imgs;
3172 struct be_dma_mem flash_cmd;
3173
3174 fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3175 if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3176 dev_err(dev, "Flash image is not compatible with adapter\n");
3177 return -EINVAL;
3178 }
3179
3180 flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
750afb08
LC		 3181 flash_cmd.va = dma_alloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3182 GFP_KERNEL);
a23113b5
SR		 3183 if (!flash_cmd.va)
3184 return -ENOMEM;
3185
3186 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3187 for (i = 0; i < num_imgs; i++) {
3188 img_hdr_ptr = (struct image_hdr *)(fw->data +
3189 (sizeof(struct flash_file_hdr_g3) +
3190 i * sizeof(struct image_hdr)));
3191 if (!BE2_chip(adapter) &&
3192 le32_to_cpu(img_hdr_ptr->imageid) != 1)
3193 continue;
3194
3195 if (skyhawk_chip(adapter))
3196 status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3197 num_imgs);
3198 else
3199 status = be_flash_BEx(adapter, fw, &flash_cmd,
3200 num_imgs);
3201 }
3202
3203 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3204 if (!status)
3205 dev_info(dev, "Firmware flashed successfully\n");
3206
3207 return status;
3208}
3209
c196b02c 3210int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
a2cc4e0b 3211 struct be_dma_mem *nonemb_cmd)
71d8d1b5
AK		 3212{
3213 struct be_mcc_wrb *wrb;
3214 struct be_cmd_req_acpi_wol_magic_config *req;
71d8d1b5
AK		 3215 int status;
3216
b7172414 3217 mutex_lock(&adapter->mcc_lock);
71d8d1b5
AK		 3218
3219 wrb = wrb_from_mccq(adapter);
3220 if (!wrb) {
3221 status = -EBUSY;
3222 goto err;
3223 }
3224 req = nonemb_cmd->va;
71d8d1b5 3225
106df1e3 3226 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
a2cc4e0b
SP		 3227 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3228 wrb, nonemb_cmd);
71d8d1b5
AK		 3229 memcpy(req->magic_mac, mac, ETH_ALEN);
3230
71d8d1b5
AK		 3231 status = be_mcc_notify_wait(adapter);
3232
3233err:
b7172414 3234 mutex_unlock(&adapter->mcc_lock);
71d8d1b5
AK		 3235 return status;
3236}
ff33a6e2 3237
fced9999
SB		 3238int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3239 u8 loopback_type, u8 enable)
3240{
3241 struct be_mcc_wrb *wrb;
3242 struct be_cmd_req_set_lmode *req;
3243 int status;
3244
2e365b1b
SK		 3245 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3246 CMD_SUBSYSTEM_LOWLEVEL))
3247 return -EPERM;
3248
b7172414 3249 mutex_lock(&adapter->mcc_lock);
fced9999
SB		 3250
3251 wrb = wrb_from_mccq(adapter);
3252 if (!wrb) {
3253 status = -EBUSY;
9c855975 3254 goto err_unlock;
fced9999
SB		 3255 }
3256
3257 req = embedded_payload(wrb);
3258
106df1e3 3259 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3260 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3261 wrb, NULL);
fced9999
SB		 3262
3263 req->src_port = port_num;
3264 req->dest_port = port_num;
3265 req->loopback_type = loopback_type;
3266 req->loopback_state = enable;
3267
9c855975
SR		 3268 status = be_mcc_notify(adapter);
3269 if (status)
3270 goto err_unlock;
3271
b7172414 3272 mutex_unlock(&adapter->mcc_lock);
9c855975
SR		 3273
3274 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3275 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3276 status = -ETIMEDOUT;
3277
3278 return status;
3279
3280err_unlock:
b7172414 3281 mutex_unlock(&adapter->mcc_lock);
fced9999
SB		 3282 return status;
3283}
3284
ff33a6e2 3285int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
a2cc4e0b
SP		 3286 u32 loopback_type, u32 pkt_size, u32 num_pkts,
3287 u64 pattern)
ff33a6e2
S		 3288{
3289 struct be_mcc_wrb *wrb;
3290 struct be_cmd_req_loopback_test *req;
5eeff635 3291 struct be_cmd_resp_loopback_test *resp;
ff33a6e2
S		 3292 int status;
3293
2e365b1b
SK		 3294 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3295 CMD_SUBSYSTEM_LOWLEVEL))
3296 return -EPERM;
3297
b7172414 3298 mutex_lock(&adapter->mcc_lock);
ff33a6e2
S		 3299
3300 wrb = wrb_from_mccq(adapter);
3301 if (!wrb) {
3302 status = -EBUSY;
3303 goto err;
3304 }
3305
3306 req = embedded_payload(wrb);
3307
106df1e3 3308 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3309 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3310 NULL);
ff33a6e2 3311
5eeff635 3312 req->hdr.timeout = cpu_to_le32(15);
ff33a6e2
S		 3313 req->pattern = cpu_to_le64(pattern);
3314 req->src_port = cpu_to_le32(port_num);
3315 req->dest_port = cpu_to_le32(port_num);
3316 req->pkt_size = cpu_to_le32(pkt_size);
3317 req->num_pkts = cpu_to_le32(num_pkts);
3318 req->loopback_type = cpu_to_le32(loopback_type);
3319
efaa408e
SR		 3320 status = be_mcc_notify(adapter);
3321 if (status)
3322 goto err;
5eeff635 3323
b7172414 3324 mutex_unlock(&adapter->mcc_lock);
ff33a6e2 3325
5eeff635
SR		 3326 wait_for_completion(&adapter->et_cmd_compl);
3327 resp = embedded_payload(wrb);
3328 status = le32_to_cpu(resp->status);
3329
3330 return status;
ff33a6e2 3331err:
b7172414 3332 mutex_unlock(&adapter->mcc_lock);
ff33a6e2
S		 3333 return status;
3334}
3335
3336int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
a2cc4e0b 3337 u32 byte_cnt, struct be_dma_mem *cmd)
ff33a6e2
S		 3338{
3339 struct be_mcc_wrb *wrb;
3340 struct be_cmd_req_ddrdma_test *req;
ff33a6e2
S		 3341 int status;
3342 int i, j = 0;
3343
2e365b1b
SK		 3344 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3345 CMD_SUBSYSTEM_LOWLEVEL))
3346 return -EPERM;
3347
b7172414 3348 mutex_lock(&adapter->mcc_lock);
ff33a6e2
S		 3349
3350 wrb = wrb_from_mccq(adapter);
3351 if (!wrb) {
3352 status = -EBUSY;
3353 goto err;
3354 }
3355 req = cmd->va;
106df1e3 3356 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
a2cc4e0b
SP		 3357 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3358 cmd);
ff33a6e2
S		 3359
3360 req->pattern = cpu_to_le64(pattern);
3361 req->byte_count = cpu_to_le32(byte_cnt);
3362 for (i = 0; i < byte_cnt; i++) {
3363 req->snd_buff[i] = (u8)(pattern >> (j*8));
3364 j++;
3365 if (j > 7)
3366 j = 0;
3367 }
3368
3369 status = be_mcc_notify_wait(adapter);
3370
3371 if (!status) {
3372 struct be_cmd_resp_ddrdma_test *resp;
03d28ffe 3373
ff33a6e2
S		 3374 resp = cmd->va;
3375 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
cd3307aa 3376 resp->snd_err) {
ff33a6e2
S		 3377 status = -1;
3378 }
3379 }
3380
3381err:
b7172414 3382 mutex_unlock(&adapter->mcc_lock);
ff33a6e2
S		 3383 return status;
3384}
368c0ca2 3385
c196b02c 3386int be_cmd_get_seeprom_data(struct be_adapter *adapter,
a2cc4e0b 3387 struct be_dma_mem *nonemb_cmd)
368c0ca2
SB		 3388{
3389 struct be_mcc_wrb *wrb;
3390 struct be_cmd_req_seeprom_read *req;
368c0ca2
SB		 3391 int status;
3392
b7172414 3393 mutex_lock(&adapter->mcc_lock);
368c0ca2
SB		 3394
3395 wrb = wrb_from_mccq(adapter);
e45ff01d
AK		 3396 if (!wrb) {
3397 status = -EBUSY;
3398 goto err;
3399 }
368c0ca2 3400 req = nonemb_cmd->va;
368c0ca2 3401
106df1e3 3402 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3403 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3404 nonemb_cmd);
368c0ca2
SB		 3405
3406 status = be_mcc_notify_wait(adapter);
3407
e45ff01d 3408err:
b7172414 3409 mutex_unlock(&adapter->mcc_lock);
368c0ca2
SB		 3410 return status;
3411}
ee3cb629 3412
42f11cf2 3413int be_cmd_get_phy_info(struct be_adapter *adapter)
ee3cb629
AK		 3414{
3415 struct be_mcc_wrb *wrb;
3416 struct be_cmd_req_get_phy_info *req;
306f1348 3417 struct be_dma_mem cmd;
ee3cb629
AK		 3418 int status;
3419
f25b119c
PR		 3420 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3421 CMD_SUBSYSTEM_COMMON))
3422 return -EPERM;
3423
b7172414 3424 mutex_lock(&adapter->mcc_lock);
ee3cb629
AK		 3425
3426 wrb = wrb_from_mccq(adapter);
3427 if (!wrb) {
3428 status = -EBUSY;
3429 goto err;
3430 }
306f1348 3431 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
750afb08
LC		 3432 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3433 GFP_ATOMIC);
306f1348
SP		 3434 if (!cmd.va) {
3435 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3436 status = -ENOMEM;
3437 goto err;
3438 }
ee3cb629 3439
306f1348 3440 req = cmd.va;
ee3cb629 3441
106df1e3 3442 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3443 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3444 wrb, &cmd);
ee3cb629
AK		 3445
3446 status = be_mcc_notify_wait(adapter);
306f1348
SP		 3447 if (!status) {
3448 struct be_phy_info *resp_phy_info =
3449 cmd.va + sizeof(struct be_cmd_req_hdr);
03d28ffe 3450
42f11cf2
AK		 3451 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3452 adapter->phy.interface_type =
306f1348 3453 le16_to_cpu(resp_phy_info->interface_type);
42f11cf2
AK		 3454 adapter->phy.auto_speeds_supported =
3455 le16_to_cpu(resp_phy_info->auto_speeds_supported);
3456 adapter->phy.fixed_speeds_supported =
3457 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3458 adapter->phy.misc_params =
3459 le32_to_cpu(resp_phy_info->misc_params);
68cb7e47
VV		 3460
3461 if (BE2_chip(adapter)) {
3462 adapter->phy.fixed_speeds_supported =
3463 BE_SUPPORTED_SPEED_10GBPS |
3464 BE_SUPPORTED_SPEED_1GBPS;
3465 }
306f1348 3466 }
e51000db 3467 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
ee3cb629 3468err:
b7172414 3469 mutex_unlock(&adapter->mcc_lock);
ee3cb629
AK		 3470 return status;
3471}
e1d18735 3472
bc0ee163 3473static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
e1d18735
AK		 3474{
3475 struct be_mcc_wrb *wrb;
3476 struct be_cmd_req_set_qos *req;
3477 int status;
3478
b7172414 3479 mutex_lock(&adapter->mcc_lock);
e1d18735
AK		 3480
3481 wrb = wrb_from_mccq(adapter);
3482 if (!wrb) {
3483 status = -EBUSY;
3484 goto err;
3485 }
3486
3487 req = embedded_payload(wrb);
3488
106df1e3 3489 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b 3490 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
e1d18735
AK		 3491
3492 req->hdr.domain = domain;
6bff57a7
AK		 3493 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3494 req->max_bps_nic = cpu_to_le32(bps);
e1d18735
AK		 3495
3496 status = be_mcc_notify_wait(adapter);
3497
3498err:
b7172414 3499 mutex_unlock(&adapter->mcc_lock);
e1d18735
AK		 3500 return status;
3501}
9e1453c5
AK		 3502
3503int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3504{
3505 struct be_mcc_wrb *wrb;
3506 struct be_cmd_req_cntl_attribs *req;
3507 struct be_cmd_resp_cntl_attribs *resp;
a155a5db 3508 int status, i;
9e1453c5
AK		 3509 int payload_len = max(sizeof(*req), sizeof(*resp));
3510 struct mgmt_controller_attrib *attribs;
3511 struct be_dma_mem attribs_cmd;
a155a5db 3512 u32 *serial_num;
9e1453c5 3513
d98ef50f
SR		 3514 if (mutex_lock_interruptible(&adapter->mbox_lock))
3515 return -1;
3516
9e1453c5
AK		 3517 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3518 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
750afb08
LC		 3519 attribs_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
3520 attribs_cmd.size,
3521 &attribs_cmd.dma, GFP_ATOMIC);
9e1453c5 3522 if (!attribs_cmd.va) {
a2cc4e0b 3523 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 3524 status = -ENOMEM;
3525 goto err;
9e1453c5
AK		 3526 }
3527
9e1453c5
AK		 3528 wrb = wrb_from_mbox(adapter);
3529 if (!wrb) {
3530 status = -EBUSY;
3531 goto err;
3532 }
3533 req = attribs_cmd.va;
9e1453c5 3534
106df1e3 3535 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3536 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3537 wrb, &attribs_cmd);
9e1453c5
AK		 3538
3539 status = be_mbox_notify_wait(adapter);
3540 if (!status) {
43d620c8 3541 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
9e1453c5 3542 adapter->hba_port_num = attribs->hba_attribs.phy_port;
a155a5db
SB		 3543 serial_num = attribs->hba_attribs.controller_serial_number;
3544 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3545 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3546 (BIT_MASK(16) - 1);
6ee080bb
SB		 3547 /* For BEx, since GET_FUNC_CONFIG command is not
3548 * supported, we read funcnum here as a workaround.
3549 */
3550 if (BEx_chip(adapter))
3551 adapter->pf_num = attribs->hba_attribs.pci_funcnum;
9e1453c5
AK		 3552 }
3553
3554err:
3555 mutex_unlock(&adapter->mbox_lock);
d98ef50f 3556 if (attribs_cmd.va)
e51000db
SB		 3557 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3558 attribs_cmd.va, attribs_cmd.dma);
9e1453c5
AK		 3559 return status;
3560}
2e588f84
SP		 3561
3562/* Uses mbox */
2dc1deb6 3563int be_cmd_req_native_mode(struct be_adapter *adapter)
2e588f84
SP		 3564{
3565 struct be_mcc_wrb *wrb;
3566 struct be_cmd_req_set_func_cap *req;
3567 int status;
3568
3569 if (mutex_lock_interruptible(&adapter->mbox_lock))
3570 return -1;
3571
3572 wrb = wrb_from_mbox(adapter);
3573 if (!wrb) {
3574 status = -EBUSY;
3575 goto err;
3576 }
3577
3578 req = embedded_payload(wrb);
3579
106df1e3 3580 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3581 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3582 sizeof(*req), wrb, NULL);
2e588f84
SP		 3583
3584 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3585 CAPABILITY_BE3_NATIVE_ERX_API);
3586 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3587
3588 status = be_mbox_notify_wait(adapter);
3589 if (!status) {
3590 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
03d28ffe 3591
2e588f84
SP		 3592 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3593 CAPABILITY_BE3_NATIVE_ERX_API;
d379142b
SP		 3594 if (!adapter->be3_native)
3595 dev_warn(&adapter->pdev->dev,
3596 "adapter not in advanced mode\n");
2e588f84
SP		 3597 }
3598err:
3599 mutex_unlock(&adapter->mbox_lock);
3600 return status;
3601}
590c391d 3602
f25b119c
PR		 3603/* Get privilege(s) for a function */
3604int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3605 u32 domain)
3606{
3607 struct be_mcc_wrb *wrb;
3608 struct be_cmd_req_get_fn_privileges *req;
3609 int status;
3610
b7172414 3611 mutex_lock(&adapter->mcc_lock);
f25b119c
PR		 3612
3613 wrb = wrb_from_mccq(adapter);
3614 if (!wrb) {
3615 status = -EBUSY;
3616 goto err;
3617 }
3618
3619 req = embedded_payload(wrb);
3620
3621 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3622 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3623 wrb, NULL);
3624
3625 req->hdr.domain = domain;
3626
3627 status = be_mcc_notify_wait(adapter);
3628 if (!status) {
3629 struct be_cmd_resp_get_fn_privileges *resp =
3630 embedded_payload(wrb);
03d28ffe 3631
f25b119c 3632 *privilege = le32_to_cpu(resp->privilege_mask);
02308d74
SR		 3633
3634 /* In UMC mode FW does not return right privileges.
3635 * Override with correct privilege equivalent to PF.
3636 */
3637 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3638 be_physfn(adapter))
3639 *privilege = MAX_PRIVILEGES;
f25b119c
PR		 3640 }
3641
3642err:
b7172414 3643 mutex_unlock(&adapter->mcc_lock);
f25b119c
PR		 3644 return status;
3645}
3646
04a06028
SP		 3647/* Set privilege(s) for a function */
3648int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3649 u32 domain)
3650{
3651 struct be_mcc_wrb *wrb;
3652 struct be_cmd_req_set_fn_privileges *req;
3653 int status;
3654
b7172414 3655 mutex_lock(&adapter->mcc_lock);
04a06028
SP		 3656
3657 wrb = wrb_from_mccq(adapter);
3658 if (!wrb) {
3659 status = -EBUSY;
3660 goto err;
3661 }
3662
3663 req = embedded_payload(wrb);
3664 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3665 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3666 wrb, NULL);
3667 req->hdr.domain = domain;
3668 if (lancer_chip(adapter))
3669 req->privileges_lancer = cpu_to_le32(privileges);
3670 else
3671 req->privileges = cpu_to_le32(privileges);
3672
3673 status = be_mcc_notify_wait(adapter);
3674err:
b7172414 3675 mutex_unlock(&adapter->mcc_lock);
04a06028
SP		 3676 return status;
3677}
3678
5a712c13
SP		 3679/* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3680 * pmac_id_valid: false => pmac_id or MAC address is requested.
3681 * If pmac_id is returned, pmac_id_valid is returned as true
3682 */
1578e777 3683int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 3684 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3685 u8 domain)
590c391d
PR		 3686{
3687 struct be_mcc_wrb *wrb;
3688 struct be_cmd_req_get_mac_list *req;
3689 int status;
3690 int mac_count;
e5e1ee89
PR		 3691 struct be_dma_mem get_mac_list_cmd;
3692 int i;
3693
3694 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3695 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
750afb08
LC		 3696 get_mac_list_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
3697 get_mac_list_cmd.size,
3698 &get_mac_list_cmd.dma,
3699 GFP_ATOMIC);
e5e1ee89
PR		 3700
3701 if (!get_mac_list_cmd.va) {
3702 dev_err(&adapter->pdev->dev,
a2cc4e0b 3703 "Memory allocation failure during GET_MAC_LIST\n");
e5e1ee89
PR		 3704 return -ENOMEM;
3705 }
590c391d 3706
b7172414 3707 mutex_lock(&adapter->mcc_lock);
590c391d
PR		 3708
3709 wrb = wrb_from_mccq(adapter);
3710 if (!wrb) {
3711 status = -EBUSY;
e5e1ee89 3712 goto out;
590c391d 3713 }
e5e1ee89
PR		 3714
3715 req = get_mac_list_cmd.va;
590c391d
PR		 3716
3717 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bf591f51
SP		 3718 OPCODE_COMMON_GET_MAC_LIST,
3719 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
590c391d 3720 req->hdr.domain = domain;
e5e1ee89 3721 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
5a712c13
SP		 3722 if (*pmac_id_valid) {
3723 req->mac_id = cpu_to_le32(*pmac_id);
b188f090 3724 req->iface_id = cpu_to_le16(if_handle);
5a712c13
SP		 3725 req->perm_override = 0;
3726 } else {
3727 req->perm_override = 1;
3728 }
590c391d
PR		 3729
3730 status = be_mcc_notify_wait(adapter);
3731 if (!status) {
3732 struct be_cmd_resp_get_mac_list *resp =
e5e1ee89 3733 get_mac_list_cmd.va;
5a712c13
SP		 3734
3735 if (*pmac_id_valid) {
3736 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3737 ETH_ALEN);
3738 goto out;
3739 }
3740
e5e1ee89
PR		 3741 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3742 /* Mac list returned could contain one or more active mac_ids
dbedd44e 3743 * or one or more true or pseudo permanent mac addresses.
1578e777
PR		 3744 * If an active mac_id is present, return first active mac_id
3745 * found.
e5e1ee89 3746 */
590c391d 3747 for (i = 0; i < mac_count; i++) {
e5e1ee89
PR		 3748 struct get_list_macaddr *mac_entry;
3749 u16 mac_addr_size;
3750 u32 mac_id;
3751
3752 mac_entry = &resp->macaddr_list[i];
3753 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3754 /* mac_id is a 32 bit value and mac_addr size
3755 * is 6 bytes
3756 */
3757 if (mac_addr_size == sizeof(u32)) {
5a712c13 3758 *pmac_id_valid = true;
e5e1ee89
PR		 3759 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3760 *pmac_id = le32_to_cpu(mac_id);
3761 goto out;
590c391d 3762 }
590c391d 3763 }
1578e777 3764 /* If no active mac_id found, return first mac addr */
5a712c13 3765 *pmac_id_valid = false;
e5e1ee89 3766 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
a2cc4e0b 3767 ETH_ALEN);
590c391d
PR		 3768 }
3769
e5e1ee89 3770out:
b7172414 3771 mutex_unlock(&adapter->mcc_lock);
e51000db
SB		 3772 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3773 get_mac_list_cmd.va, get_mac_list_cmd.dma);
590c391d
PR		 3774 return status;
3775}
3776
a2cc4e0b
SP		 3777int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3778 u8 *mac, u32 if_handle, bool active, u32 domain)
5a712c13 3779{
b188f090
SR		 3780 if (!active)
3781 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3782 if_handle, domain);
3175d8c2 3783 if (BEx_chip(adapter))
5a712c13 3784 return be_cmd_mac_addr_query(adapter, mac, false,
b188f090 3785 if_handle, curr_pmac_id);
3175d8c2
SP		 3786 else
3787 /* Fetch the MAC address using pmac_id */
3788 return be_cmd_get_mac_from_list(adapter, mac, &active,
b188f090
SR		 3789 &curr_pmac_id,
3790 if_handle, domain);
5a712c13
SP		 3791}
3792
95046b92
SP		 3793int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3794{
3795 int status;
3796 bool pmac_valid = false;
3797
c7bf7169 3798 eth_zero_addr(mac);
95046b92 3799
3175d8c2
SP		 3800 if (BEx_chip(adapter)) {
3801 if (be_physfn(adapter))
3802 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3803 0);
3804 else
3805 status = be_cmd_mac_addr_query(adapter, mac, false,
3806 adapter->if_handle, 0);
3807 } else {
95046b92 3808 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
b188f090 3809 NULL, adapter->if_handle, 0);
3175d8c2
SP		 3810 }
3811
95046b92
SP		 3812 return status;
3813}
3814
590c391d
PR		 3815/* Uses synchronous MCCQ */
3816int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3817 u8 mac_count, u32 domain)
3818{
3819 struct be_mcc_wrb *wrb;
3820 struct be_cmd_req_set_mac_list *req;
3821 int status;
3822 struct be_dma_mem cmd;
3823
3824 memset(&cmd, 0, sizeof(struct be_dma_mem));
3825 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
750afb08
LC		 3826 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3827 GFP_KERNEL);
d0320f75 3828 if (!cmd.va)
590c391d 3829 return -ENOMEM;
590c391d 3830
b7172414 3831 mutex_lock(&adapter->mcc_lock);
590c391d
PR		 3832
3833 wrb = wrb_from_mccq(adapter);
3834 if (!wrb) {
3835 status = -EBUSY;
3836 goto err;
3837 }
3838
3839 req = cmd.va;
3840 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3841 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3842 wrb, &cmd);
590c391d
PR		 3843
3844 req->hdr.domain = domain;
3845 req->mac_count = mac_count;
3846 if (mac_count)
3847 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3848
3849 status = be_mcc_notify_wait(adapter);
3850
3851err:
a2cc4e0b 3852 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
b7172414 3853 mutex_unlock(&adapter->mcc_lock);
590c391d
PR		 3854 return status;
3855}
4762f6ce 3856
3175d8c2
SP		 3857/* Wrapper to delete any active MACs and provision the new mac.
3858 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3859 * current list are active.
3860 */
3861int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3862{
3863 bool active_mac = false;
3864 u8 old_mac[ETH_ALEN];
3865 u32 pmac_id;
3866 int status;
3867
3868 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
b188f090
SR		 3869 &pmac_id, if_id, dom);
3870
3175d8c2
SP		 3871 if (!status && active_mac)
3872 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3873
3874 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3875}
3876
f1f3ee1b 3877int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
e7bcbd7b 3878 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
f1f3ee1b
AK		 3879{
3880 struct be_mcc_wrb *wrb;
3881 struct be_cmd_req_set_hsw_config *req;
3882 void *ctxt;
3883 int status;
3884
884476be
SK		 3885 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3886 CMD_SUBSYSTEM_COMMON))
3887 return -EPERM;
3888
b7172414 3889 mutex_lock(&adapter->mcc_lock);
f1f3ee1b
AK		 3890
3891 wrb = wrb_from_mccq(adapter);
3892 if (!wrb) {
3893 status = -EBUSY;
3894 goto err;
3895 }
3896
3897 req = embedded_payload(wrb);
3898 ctxt = &req->context;
3899
3900 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3901 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3902 NULL);
f1f3ee1b
AK		 3903
3904 req->hdr.domain = domain;
3905 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3906 if (pvid) {
3907 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3908 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3909 }
884476be 3910 if (hsw_mode) {
a77dcb8c
AK		 3911 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3912 ctxt, adapter->hba_port_num);
3913 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3914 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3915 ctxt, hsw_mode);
3916 }
f1f3ee1b 3917
e7bcbd7b
KA		 3918 /* Enable/disable both mac and vlan spoof checking */
3919 if (!BEx_chip(adapter) && spoofchk) {
3920 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3921 ctxt, spoofchk);
3922 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3923 ctxt, spoofchk);
3924 }
3925
f1f3ee1b
AK		 3926 be_dws_cpu_to_le(req->context, sizeof(req->context));
3927 status = be_mcc_notify_wait(adapter);
3928
3929err:
b7172414 3930 mutex_unlock(&adapter->mcc_lock);
f1f3ee1b
AK		 3931 return status;
3932}
3933
3934/* Get Hyper switch config */
3935int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
e7bcbd7b 3936 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
f1f3ee1b
AK		 3937{
3938 struct be_mcc_wrb *wrb;
3939 struct be_cmd_req_get_hsw_config *req;
3940 void *ctxt;
3941 int status;
3942 u16 vid;
3943
b7172414 3944 mutex_lock(&adapter->mcc_lock);
f1f3ee1b
AK		 3945
3946 wrb = wrb_from_mccq(adapter);
3947 if (!wrb) {
3948 status = -EBUSY;
3949 goto err;
3950 }
3951
3952 req = embedded_payload(wrb);
3953 ctxt = &req->context;
3954
3955 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
a2cc4e0b
SP		 3956 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3957 NULL);
f1f3ee1b
AK		 3958
3959 req->hdr.domain = domain;
a77dcb8c
AK		 3960 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3961 ctxt, intf_id);
f1f3ee1b 3962 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
a77dcb8c 3963
2c07c1d7 3964 if (!BEx_chip(adapter) && mode) {
a77dcb8c
AK		 3965 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3966 ctxt, adapter->hba_port_num);
3967 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3968 }
f1f3ee1b
AK		 3969 be_dws_cpu_to_le(req->context, sizeof(req->context));
3970
3971 status = be_mcc_notify_wait(adapter);
3972 if (!status) {
3973 struct be_cmd_resp_get_hsw_config *resp =
3974 embedded_payload(wrb);
03d28ffe 3975
a2cc4e0b 3976 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
f1f3ee1b 3977 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
a2cc4e0b 3978 pvid, &resp->context);
a77dcb8c
AK		 3979 if (pvid)
3980 *pvid = le16_to_cpu(vid);
3981 if (mode)
3982 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3983 port_fwd_type, &resp->context);
e7bcbd7b
KA		 3984 if (spoofchk)
3985 *spoofchk =
3986 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3987 spoofchk, &resp->context);
f1f3ee1b
AK		 3988 }
3989
3990err:
b7172414 3991 mutex_unlock(&adapter->mcc_lock);
f1f3ee1b
AK		 3992 return status;
3993}
3994
f7062ee5
SP		 3995static bool be_is_wol_excluded(struct be_adapter *adapter)
3996{
3997 struct pci_dev *pdev = adapter->pdev;
3998
18c57c74 3999 if (be_virtfn(adapter))
f7062ee5
SP		 4000 return true;
4001
4002 switch (pdev->subsystem_device) {
4003 case OC_SUBSYS_DEVICE_ID1:
4004 case OC_SUBSYS_DEVICE_ID2:
4005 case OC_SUBSYS_DEVICE_ID3:
4006 case OC_SUBSYS_DEVICE_ID4:
4007 return true;
4008 default:
4009 return false;
4010 }
4011}
4012
4762f6ce
AK		 4013int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
4014{
4015 struct be_mcc_wrb *wrb;
4016 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
76a9e08e 4017 int status = 0;
4762f6ce
AK		 4018 struct be_dma_mem cmd;
4019
f25b119c
PR		 4020 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4021 CMD_SUBSYSTEM_ETH))
4022 return -EPERM;
4023
76a9e08e
SR		 4024 if (be_is_wol_excluded(adapter))
4025 return status;
4026
d98ef50f
SR		 4027 if (mutex_lock_interruptible(&adapter->mbox_lock))
4028 return -1;
4029
4762f6ce
AK		 4030 memset(&cmd, 0, sizeof(struct be_dma_mem));
4031 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
750afb08
LC		 4032 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4033 GFP_ATOMIC);
4762f6ce 4034 if (!cmd.va) {
a2cc4e0b 4035 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
d98ef50f
SR		 4036 status = -ENOMEM;
4037 goto err;
4762f6ce
AK		 4038 }
4039
4762f6ce
AK		 4040 wrb = wrb_from_mbox(adapter);
4041 if (!wrb) {
4042 status = -EBUSY;
4043 goto err;
4044 }
4045
4046 req = cmd.va;
4047
4048 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4049 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
76a9e08e 4050 sizeof(*req), wrb, &cmd);
4762f6ce
AK		 4051
4052 req->hdr.version = 1;
4053 req->query_options = BE_GET_WOL_CAP;
4054
4055 status = be_mbox_notify_wait(adapter);
4056 if (!status) {
4057 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
03d28ffe 4058
504fbf1e 4059 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4762f6ce 4060
4762f6ce 4061 adapter->wol_cap = resp->wol_settings;
45f13df7
SB		 4062
4063 /* Non-zero macaddr indicates WOL is enabled */
4064 if (adapter->wol_cap & BE_WOL_CAP &&
4065 !is_zero_ether_addr(resp->magic_mac))
76a9e08e 4066 adapter->wol_en = true;
4762f6ce
AK		 4067 }
4068err:
4069 mutex_unlock(&adapter->mbox_lock);
d98ef50f 4070 if (cmd.va)
e51000db
SB		 4071 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4072 cmd.dma);
4762f6ce 4073 return status;
941a77d5
SK		 4074
4075}
baaa08d1
VV		 4076
4077int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4078{
4079 struct be_dma_mem extfat_cmd;
4080 struct be_fat_conf_params *cfgs;
4081 int status;
4082 int i, j;
4083
4084 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4085 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
750afb08
LC		 4086 extfat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
4087 extfat_cmd.size, &extfat_cmd.dma,
4088 GFP_ATOMIC);
baaa08d1
VV		 4089 if (!extfat_cmd.va)
4090 return -ENOMEM;
4091
4092 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4093 if (status)
4094 goto err;
4095
4096 cfgs = (struct be_fat_conf_params *)
4097 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4098 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4099 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
03d28ffe 4100
baaa08d1
VV		 4101 for (j = 0; j < num_modes; j++) {
4102 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4103 cfgs->module[i].trace_lvl[j].dbg_lvl =
4104 cpu_to_le32(level);
4105 }
4106 }
4107
4108 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4109err:
e51000db
SB		 4110 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4111 extfat_cmd.dma);
baaa08d1
VV		 4112 return status;
4113}
4114
4115int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4116{
4117 struct be_dma_mem extfat_cmd;
4118 struct be_fat_conf_params *cfgs;
4119 int status, j;
4120 int level = 0;
4121
4122 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4123 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
750afb08
LC		 4124 extfat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
4125 extfat_cmd.size, &extfat_cmd.dma,
4126 GFP_ATOMIC);
baaa08d1
VV		 4127
4128 if (!extfat_cmd.va) {
4129 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4130 __func__);
4131 goto err;
4132 }
4133
4134 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4135 if (!status) {
4136 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4137 sizeof(struct be_cmd_resp_hdr));
03d28ffe 4138
baaa08d1
VV		 4139 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4140 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4141 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4142 }
4143 }
e51000db
SB		 4144 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4145 extfat_cmd.dma);
baaa08d1
VV		 4146err:
4147 return level;
4148}
4149
941a77d5
SK		 4150int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4151 struct be_dma_mem *cmd)
4152{
4153 struct be_mcc_wrb *wrb;
4154 struct be_cmd_req_get_ext_fat_caps *req;
4155 int status;
4156
62259ac4
SK		 4157 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4158 CMD_SUBSYSTEM_COMMON))
4159 return -EPERM;
4160
941a77d5
SK		 4161 if (mutex_lock_interruptible(&adapter->mbox_lock))
4162 return -1;
4163
4164 wrb = wrb_from_mbox(adapter);
4165 if (!wrb) {
4166 status = -EBUSY;
4167 goto err;
4168 }
4169
4170 req = cmd->va;
4171 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
62259ac4 4172 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
941a77d5
SK		 4173 cmd->size, wrb, cmd);
4174 req->parameter_type = cpu_to_le32(1);
4175
4176 status = be_mbox_notify_wait(adapter);
4177err:
4178 mutex_unlock(&adapter->mbox_lock);
4179 return status;
4180}
4181
4182int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4183 struct be_dma_mem *cmd,
4184 struct be_fat_conf_params *configs)
4185{
4186 struct be_mcc_wrb *wrb;
4187 struct be_cmd_req_set_ext_fat_caps *req;
4188 int status;
4189
b7172414 4190 mutex_lock(&adapter->mcc_lock);
941a77d5
SK		 4191
4192 wrb = wrb_from_mccq(adapter);
4193 if (!wrb) {
4194 status = -EBUSY;
4195 goto err;
4196 }
4197
4198 req = cmd->va;
4199 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4200 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
62259ac4 4201 OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES,
941a77d5
SK		 4202 cmd->size, wrb, cmd);
4203
4204 status = be_mcc_notify_wait(adapter);
4205err:
b7172414 4206 mutex_unlock(&adapter->mcc_lock);
941a77d5 4207 return status;
4762f6ce 4208}
6a4ab669 4209
21252377 4210int be_cmd_query_port_name(struct be_adapter *adapter)
b4e32a71 4211{
b4e32a71 4212 struct be_cmd_req_get_port_name *req;
21252377 4213 struct be_mcc_wrb *wrb;
b4e32a71
PR		 4214 int status;
4215
21252377
VV		 4216 if (mutex_lock_interruptible(&adapter->mbox_lock))
4217 return -1;
b4e32a71 4218
21252377 4219 wrb = wrb_from_mbox(adapter);
b4e32a71
PR		 4220 req = embedded_payload(wrb);
4221
4222 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4223 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4224 NULL);
21252377
VV		 4225 if (!BEx_chip(adapter))
4226 req->hdr.version = 1;
b4e32a71 4227
21252377 4228 status = be_mbox_notify_wait(adapter);
b4e32a71
PR		 4229 if (!status) {
4230 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
03d28ffe 4231
21252377 4232 adapter->port_name = resp->port_name[adapter->hba_port_num];
b4e32a71 4233 } else {
21252377 4234 adapter->port_name = adapter->hba_port_num + '0';
b4e32a71 4235 }
21252377
VV		 4236
4237 mutex_unlock(&adapter->mbox_lock);
b4e32a71
PR		 4238 return status;
4239}
4240
980df249
SR		 4241/* When more than 1 NIC descriptor is present in the descriptor list,
4242 * the caller must specify the pf_num to obtain the NIC descriptor
4243 * corresponding to its pci function.
4244 * get_vft must be true when the caller wants the VF-template desc of the
4245 * PF-pool.
4246 * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4247 * that only it's NIC descriptor is present in the descriptor list.
4248 */
10cccf60 4249static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
980df249 4250 bool get_vft, u8 pf_num)
abb93951 4251{
150d58c7 4252 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
10cccf60 4253 struct be_nic_res_desc *nic;
abb93951
PR		 4254 int i;
4255
4256 for (i = 0; i < desc_count; i++) {
150d58c7 4257 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
10cccf60
VV		 4258 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4259 nic = (struct be_nic_res_desc *)hdr;
980df249
SR		 4260
4261 if ((pf_num == PF_NUM_IGNORE ||
4262 nic->pf_num == pf_num) &&
4263 (!get_vft || nic->flags & BIT(VFT_SHIFT)))
10cccf60
VV		 4264 return nic;
4265 }
150d58c7
VV		 4266 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4267 hdr = (void *)hdr + hdr->desc_len;
abb93951 4268 }
150d58c7
VV		 4269 return NULL;
4270}
4271
980df249
SR		 4272static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4273 u8 pf_num)
10cccf60 4274{
980df249 4275 return be_get_nic_desc(buf, desc_count, true, pf_num);
10cccf60
VV		 4276}
4277
980df249
SR		 4278static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4279 u8 pf_num)
10cccf60 4280{
980df249 4281 return be_get_nic_desc(buf, desc_count, false, pf_num);
10cccf60
VV		 4282}
4283
980df249
SR		 4284static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4285 u8 pf_num)
150d58c7
VV		 4286{
4287 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4288 struct be_pcie_res_desc *pcie;
4289 int i;
4290
4291 for (i = 0; i < desc_count; i++) {
980df249
SR		 4292 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4293 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4294 pcie = (struct be_pcie_res_desc *)hdr;
4295 if (pcie->pf_num == pf_num)
150d58c7
VV		 4296 return pcie;
4297 }
abb93951 4298
150d58c7
VV		 4299 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4300 hdr = (void *)hdr + hdr->desc_len;
4301 }
950e2958 4302 return NULL;
abb93951
PR		 4303}
4304
f93f160b
VV		 4305static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4306{
4307 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4308 int i;
4309
4310 for (i = 0; i < desc_count; i++) {
4311 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4312 return (struct be_port_res_desc *)hdr;
4313
4314 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4315 hdr = (void *)hdr + hdr->desc_len;
4316 }
4317 return NULL;
4318}
4319
92bf14ab
SP		 4320static void be_copy_nic_desc(struct be_resources *res,
4321 struct be_nic_res_desc *desc)
4322{
4323 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4324 res->max_vlans = le16_to_cpu(desc->vlan_count);
4325 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4326 res->max_tx_qs = le16_to_cpu(desc->txq_count);
4327 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4328 res->max_rx_qs = le16_to_cpu(desc->rq_count);
4329 res->max_evt_qs = le16_to_cpu(desc->eq_count);
f2858738
VV		 4330 res->max_cq_count = le16_to_cpu(desc->cq_count);
4331 res->max_iface_count = le16_to_cpu(desc->iface_count);
4332 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
92bf14ab
SP		 4333 /* Clear flags that driver is not interested in */
4334 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4335 BE_IF_CAP_FLAGS_WANT;
92bf14ab
SP		 4336}
4337
abb93951 4338/* Uses Mbox */
92bf14ab 4339int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
abb93951
PR		 4340{
4341 struct be_mcc_wrb *wrb;
4342 struct be_cmd_req_get_func_config *req;
4343 int status;
4344 struct be_dma_mem cmd;
4345
d98ef50f
SR		 4346 if (mutex_lock_interruptible(&adapter->mbox_lock))
4347 return -1;
4348
abb93951
PR		 4349 memset(&cmd, 0, sizeof(struct be_dma_mem));
4350 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
750afb08
LC		 4351 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4352 GFP_ATOMIC);
abb93951
PR		 4353 if (!cmd.va) {
4354 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
d98ef50f
SR		 4355 status = -ENOMEM;
4356 goto err;
abb93951 4357 }
abb93951
PR		 4358
4359 wrb = wrb_from_mbox(adapter);
4360 if (!wrb) {
4361 status = -EBUSY;
4362 goto err;
4363 }
4364
4365 req = cmd.va;
4366
4367 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4368 OPCODE_COMMON_GET_FUNC_CONFIG,
4369 cmd.size, wrb, &cmd);
4370
28710c55
KA		 4371 if (skyhawk_chip(adapter))
4372 req->hdr.version = 1;
4373
abb93951
PR		 4374 status = be_mbox_notify_wait(adapter);
4375 if (!status) {
4376 struct be_cmd_resp_get_func_config *resp = cmd.va;
4377 u32 desc_count = le32_to_cpu(resp->desc_count);
150d58c7 4378 struct be_nic_res_desc *desc;
abb93951 4379
980df249
SR		 4380 /* GET_FUNC_CONFIG returns resource descriptors of the
4381 * current function only. So, pf_num should be set to
4382 * PF_NUM_IGNORE.
4383 */
4384 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4385 PF_NUM_IGNORE);
abb93951
PR		 4386 if (!desc) {
4387 status = -EINVAL;
4388 goto err;
4389 }
980df249
SR		 4390
4391 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4392 adapter->pf_num = desc->pf_num;
4393 adapter->vf_num = desc->vf_num;
4394
4395 if (res)
4396 be_copy_nic_desc(res, desc);
abb93951
PR		 4397 }
4398err:
4399 mutex_unlock(&adapter->mbox_lock);
d98ef50f 4400 if (cmd.va)
e51000db
SB		 4401 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4402 cmd.dma);
abb93951
PR		 4403 return status;
4404}
4405
de2b1e03 4406/* This routine returns a list of all the NIC PF_nums in the adapter */
d766e7e6 4407static u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
de2b1e03
SK		 4408{
4409 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4410 struct be_pcie_res_desc *pcie = NULL;
4411 int i;
4412 u16 nic_pf_count = 0;
4413
4414 for (i = 0; i < desc_count; i++) {
4415 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4416 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4417 pcie = (struct be_pcie_res_desc *)hdr;
4418 if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4419 pcie->pf_type == MISSION_RDMA)) {
4420 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4421 }
4422 }
4423
4424 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4425 hdr = (void *)hdr + hdr->desc_len;
4426 }
4427 return nic_pf_count;
4428}
4429
980df249 4430/* Will use MBOX only if MCCQ has not been created */
92bf14ab 4431int be_cmd_get_profile_config(struct be_adapter *adapter,
de2b1e03
SK		 4432 struct be_resources *res,
4433 struct be_port_resources *port_res,
4434 u8 profile_type, u8 query, u8 domain)
a05f99db 4435{
150d58c7 4436 struct be_cmd_resp_get_profile_config *resp;
ba48c0c9 4437 struct be_cmd_req_get_profile_config *req;
10cccf60 4438 struct be_nic_res_desc *vf_res;
150d58c7 4439 struct be_pcie_res_desc *pcie;
f93f160b 4440 struct be_port_res_desc *port;
150d58c7 4441 struct be_nic_res_desc *nic;
ba48c0c9 4442 struct be_mcc_wrb wrb = {0};
a05f99db 4443 struct be_dma_mem cmd;
f2858738 4444 u16 desc_count;
a05f99db
VV		 4445 int status;
4446
4447 memset(&cmd, 0, sizeof(struct be_dma_mem));
150d58c7 4448 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
750afb08
LC		 4449 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4450 GFP_ATOMIC);
150d58c7 4451 if (!cmd.va)
a05f99db 4452 return -ENOMEM;
a05f99db 4453
ba48c0c9
VV		 4454 req = cmd.va;
4455 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4456 OPCODE_COMMON_GET_PROFILE_CONFIG,
4457 cmd.size, &wrb, &cmd);
4458
ba48c0c9
VV		 4459 if (!lancer_chip(adapter))
4460 req->hdr.version = 1;
de2b1e03 4461 req->type = profile_type;
72ef3a88 4462 req->hdr.domain = domain;
ba48c0c9 4463
f2858738
VV		 4464 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4465 * descriptors with all bits set to "1" for the fields which can be
4466 * modified using SET_PROFILE_CONFIG cmd.
4467 */
4468 if (query == RESOURCE_MODIFIABLE)
4469 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4470
ba48c0c9 4471 status = be_cmd_notify_wait(adapter, &wrb);
150d58c7
VV		 4472 if (status)
4473 goto err;
abb93951 4474
150d58c7 4475 resp = cmd.va;
f2858738 4476 desc_count = le16_to_cpu(resp->desc_count);
abb93951 4477
de2b1e03
SK		 4478 if (port_res) {
4479 u16 nic_pf_cnt = 0, i;
4480 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4481
4482 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4483 desc_count,
4484 nic_pf_num_list);
4485
4486 for (i = 0; i < nic_pf_cnt; i++) {
4487 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4488 nic_pf_num_list[i]);
4489 if (nic->link_param == adapter->port_num) {
4490 port_res->nic_pfs++;
4491 pcie = be_get_pcie_desc(resp->func_param,
4492 desc_count,
4493 nic_pf_num_list[i]);
4494 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4495 }
4496 }
9d7f19dc 4497 goto err;
de2b1e03
SK		 4498 }
4499
980df249
SR		 4500 pcie = be_get_pcie_desc(resp->func_param, desc_count,
4501 adapter->pf_num);
150d58c7 4502 if (pcie)
92bf14ab 4503 res->max_vfs = le16_to_cpu(pcie->num_vfs);
150d58c7 4504
f93f160b
VV		 4505 port = be_get_port_desc(resp->func_param, desc_count);
4506 if (port)
4507 adapter->mc_type = port->mc_type;
4508
980df249
SR		 4509 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4510 adapter->pf_num);
92bf14ab
SP		 4511 if (nic)
4512 be_copy_nic_desc(res, nic);
4513
980df249
SR		 4514 vf_res = be_get_vft_desc(resp->func_param, desc_count,
4515 adapter->pf_num);
10cccf60
VV		 4516 if (vf_res)
4517 res->vf_if_cap_flags = vf_res->cap_flags;
abb93951 4518err:
a05f99db 4519 if (cmd.va)
e51000db
SB		 4520 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4521 cmd.dma);
abb93951
PR		 4522 return status;
4523}
4524
bec84e6b
VV		 4525/* Will use MBOX only if MCCQ has not been created */
4526static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4527 int size, int count, u8 version, u8 domain)
d5c18473 4528{
d5c18473 4529 struct be_cmd_req_set_profile_config *req;
bec84e6b
VV		 4530 struct be_mcc_wrb wrb = {0};
4531 struct be_dma_mem cmd;
d5c18473
PR		 4532 int status;
4533
bec84e6b
VV		 4534 memset(&cmd, 0, sizeof(struct be_dma_mem));
4535 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
750afb08
LC		 4536 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4537 GFP_ATOMIC);
bec84e6b
VV		 4538 if (!cmd.va)
4539 return -ENOMEM;
d5c18473 4540
bec84e6b 4541 req = cmd.va;
d5c18473 4542 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
bec84e6b
VV		 4543 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4544 &wrb, &cmd);
a401801c 4545 req->hdr.version = version;
d5c18473 4546 req->hdr.domain = domain;
bec84e6b 4547 req->desc_count = cpu_to_le32(count);
a401801c
SP		 4548 memcpy(req->desc, desc, size);
4549
bec84e6b
VV		 4550 status = be_cmd_notify_wait(adapter, &wrb);
4551
4552 if (cmd.va)
e51000db
SB		 4553 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4554 cmd.dma);
d5c18473
PR		 4555 return status;
4556}
4557
a401801c 4558/* Mark all fields invalid */
d766e7e6 4559static void be_reset_nic_desc(struct be_nic_res_desc *nic)
a401801c
SP		 4560{
4561 memset(nic, 0, sizeof(*nic));
4562 nic->unicast_mac_count = 0xFFFF;
4563 nic->mcc_count = 0xFFFF;
4564 nic->vlan_count = 0xFFFF;
4565 nic->mcast_mac_count = 0xFFFF;
4566 nic->txq_count = 0xFFFF;
4567 nic->rq_count = 0xFFFF;
4568 nic->rssq_count = 0xFFFF;
4569 nic->lro_count = 0xFFFF;
4570 nic->cq_count = 0xFFFF;
4571 nic->toe_conn_count = 0xFFFF;
4572 nic->eq_count = 0xFFFF;
0f77ba73 4573 nic->iface_count = 0xFFFF;
a401801c 4574 nic->link_param = 0xFF;
0f77ba73 4575 nic->channel_id_param = cpu_to_le16(0xF000);
a401801c
SP		 4576 nic->acpi_params = 0xFF;
4577 nic->wol_param = 0x0F;
0f77ba73
RN		 4578 nic->tunnel_iface_count = 0xFFFF;
4579 nic->direct_tenant_iface_count = 0xFFFF;
bec84e6b 4580 nic->bw_min = 0xFFFFFFFF;
a401801c
SP		 4581 nic->bw_max = 0xFFFFFFFF;
4582}
4583
bec84e6b
VV		 4584/* Mark all fields invalid */
4585static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4586{
4587 memset(pcie, 0, sizeof(*pcie));
4588 pcie->sriov_state = 0xFF;
4589 pcie->pf_state = 0xFF;
4590 pcie->pf_type = 0xFF;
4591 pcie->num_vfs = 0xFFFF;
4592}
4593
0f77ba73
RN		 4594int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4595 u8 domain)
a401801c 4596{
0f77ba73
RN		 4597 struct be_nic_res_desc nic_desc;
4598 u32 bw_percent;
4599 u16 version = 0;
4600
4601 if (BE3_chip(adapter))
4602 return be_cmd_set_qos(adapter, max_rate / 10, domain);
a401801c 4603
0f77ba73 4604 be_reset_nic_desc(&nic_desc);
980df249 4605 nic_desc.pf_num = adapter->pf_num;
0f77ba73 4606 nic_desc.vf_num = domain;
58bdeaa6 4607 nic_desc.bw_min = 0;
0f77ba73 4608 if (lancer_chip(adapter)) {
a401801c
SP		 4609 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4610 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4611 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4612 (1 << NOSV_SHIFT);
0f77ba73 4613 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
a401801c 4614 } else {
0f77ba73
RN		 4615 version = 1;
4616 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4617 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4618 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4619 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4620 nic_desc.bw_max = cpu_to_le32(bw_percent);
a401801c 4621 }
0f77ba73
RN		 4622
4623 return be_cmd_set_profile_config(adapter, &nic_desc,
4624 nic_desc.hdr.desc_len,
bec84e6b
VV		 4625 1, version, domain);
4626}
4627
4628int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738 4629 struct be_resources pool_res, u16 num_vfs,
b9263cbf 4630 struct be_resources *vft_res)
bec84e6b
VV		 4631{
4632 struct {
4633 struct be_pcie_res_desc pcie;
4634 struct be_nic_res_desc nic_vft;
4635 } __packed desc;
bec84e6b 4636
bec84e6b
VV		 4637 /* PF PCIE descriptor */
4638 be_reset_pcie_desc(&desc.pcie);
4639 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4640 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
f2858738 4641 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 4642 desc.pcie.pf_num = adapter->pdev->devfn;
4643 desc.pcie.sriov_state = num_vfs ? 1 : 0;
4644 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4645
4646 /* VF NIC Template descriptor */
4647 be_reset_nic_desc(&desc.nic_vft);
4648 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4649 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
b9263cbf
SR		 4650 desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4651 BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
bec84e6b
VV		 4652 desc.nic_vft.pf_num = adapter->pdev->devfn;
4653 desc.nic_vft.vf_num = 0;
b9263cbf
SR		 4654 desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4655 desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4656 desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4657 desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4658 desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4659
4660 if (vft_res->max_uc_mac)
4661 desc.nic_vft.unicast_mac_count =
4662 cpu_to_le16(vft_res->max_uc_mac);
4663 if (vft_res->max_vlans)
4664 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4665 if (vft_res->max_iface_count)
4666 desc.nic_vft.iface_count =
4667 cpu_to_le16(vft_res->max_iface_count);
4668 if (vft_res->max_mcc_count)
4669 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
bec84e6b
VV		 4670
4671 return be_cmd_set_profile_config(adapter, &desc,
4672 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
a401801c
SP		 4673}
4674
4675int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4676{
4677 struct be_mcc_wrb *wrb;
4678 struct be_cmd_req_manage_iface_filters *req;
4679 int status;
4680
4681 if (iface == 0xFFFFFFFF)
4682 return -1;
4683
b7172414 4684 mutex_lock(&adapter->mcc_lock);
a401801c
SP		 4685
4686 wrb = wrb_from_mccq(adapter);
4687 if (!wrb) {
4688 status = -EBUSY;
4689 goto err;
4690 }
4691 req = embedded_payload(wrb);
4692
4693 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4694 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4695 wrb, NULL);
4696 req->op = op;
4697 req->target_iface_id = cpu_to_le32(iface);
4698
4699 status = be_mcc_notify_wait(adapter);
4700err:
b7172414 4701 mutex_unlock(&adapter->mcc_lock);
a401801c
SP		 4702 return status;
4703}
4704
4705int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4706{
4707 struct be_port_res_desc port_desc;
4708
4709 memset(&port_desc, 0, sizeof(port_desc));
4710 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4711 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4712 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4713 port_desc.link_num = adapter->hba_port_num;
4714 if (port) {
4715 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4716 (1 << RCVID_SHIFT);
4717 port_desc.nv_port = swab16(port);
4718 } else {
4719 port_desc.nv_flags = NV_TYPE_DISABLED;
4720 port_desc.nv_port = 0;
4721 }
4722
4723 return be_cmd_set_profile_config(adapter, &port_desc,
bec84e6b 4724 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
a401801c
SP		 4725}
4726
4c876616
SP		 4727int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4728 int vf_num)
4729{
4730 struct be_mcc_wrb *wrb;
4731 struct be_cmd_req_get_iface_list *req;
4732 struct be_cmd_resp_get_iface_list *resp;
4733 int status;
4734
b7172414 4735 mutex_lock(&adapter->mcc_lock);
4c876616
SP		 4736
4737 wrb = wrb_from_mccq(adapter);
4738 if (!wrb) {
4739 status = -EBUSY;
4740 goto err;
4741 }
4742 req = embedded_payload(wrb);
4743
4744 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4745 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4746 wrb, NULL);
4747 req->hdr.domain = vf_num + 1;
4748
4749 status = be_mcc_notify_wait(adapter);
4750 if (!status) {
4751 resp = (struct be_cmd_resp_get_iface_list *)req;
4752 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4753 }
4754
4755err:
b7172414 4756 mutex_unlock(&adapter->mcc_lock);
4c876616
SP		 4757 return status;
4758}
4759
5c510811
SK		 4760static int lancer_wait_idle(struct be_adapter *adapter)
4761{
4762#define SLIPORT_IDLE_TIMEOUT 30
4763 u32 reg_val;
4764 int status = 0, i;
4765
4766 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4767 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4768 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4769 break;
4770
4771 ssleep(1);
4772 }
4773
4774 if (i == SLIPORT_IDLE_TIMEOUT)
4775 status = -1;
4776
4777 return status;
4778}
4779
4780int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4781{
4782 int status = 0;
4783
4784 status = lancer_wait_idle(adapter);
4785 if (status)
4786 return status;
4787
4788 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4789
4790 return status;
4791}
4792
4793/* Routine to check whether dump image is present or not */
4794bool dump_present(struct be_adapter *adapter)
4795{
4796 u32 sliport_status = 0;
4797
4798 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4799 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4800}
4801
4802int lancer_initiate_dump(struct be_adapter *adapter)
4803{
f0613380 4804 struct device *dev = &adapter->pdev->dev;
5c510811
SK		 4805 int status;
4806
f0613380
KA		 4807 if (dump_present(adapter)) {
4808 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4809 return -EEXIST;
4810 }
4811
5c510811
SK		 4812 /* give firmware reset and diagnostic dump */
4813 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4814 PHYSDEV_CONTROL_DD_MASK);
4815 if (status < 0) {
f0613380 4816 dev_err(dev, "FW reset failed\n");
5c510811
SK		 4817 return status;
4818 }
4819
4820 status = lancer_wait_idle(adapter);
4821 if (status)
4822 return status;
4823
4824 if (!dump_present(adapter)) {
f0613380
KA		 4825 dev_err(dev, "FW dump not generated\n");
4826 return -EIO;
5c510811
SK		 4827 }
4828
4829 return 0;
4830}
4831
f0613380
KA		 4832int lancer_delete_dump(struct be_adapter *adapter)
4833{
4834 int status;
4835
4836 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4837 return be_cmd_status(status);
4838}
4839
dcf7ebba
PR		 4840/* Uses sync mcc */
4841int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4842{
4843 struct be_mcc_wrb *wrb;
4844 struct be_cmd_enable_disable_vf *req;
4845 int status;
4846
0599863d 4847 if (BEx_chip(adapter))
dcf7ebba
PR		 4848 return 0;
4849
b7172414 4850 mutex_lock(&adapter->mcc_lock);
dcf7ebba
PR		 4851
4852 wrb = wrb_from_mccq(adapter);
4853 if (!wrb) {
4854 status = -EBUSY;
4855 goto err;
4856 }
4857
4858 req = embedded_payload(wrb);
4859
4860 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4861 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4862 wrb, NULL);
4863
4864 req->hdr.domain = domain;
4865 req->enable = 1;
4866 status = be_mcc_notify_wait(adapter);
4867err:
b7172414 4868 mutex_unlock(&adapter->mcc_lock);
dcf7ebba
PR		 4869 return status;
4870}
4871
68c45a2d
SK		 4872int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4873{
4874 struct be_mcc_wrb *wrb;
4875 struct be_cmd_req_intr_set *req;
4876 int status;
4877
4878 if (mutex_lock_interruptible(&adapter->mbox_lock))
4879 return -1;
4880
4881 wrb = wrb_from_mbox(adapter);
4882
4883 req = embedded_payload(wrb);
4884
4885 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4886 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4887 wrb, NULL);
4888
4889 req->intr_enabled = intr_enable;
4890
4891 status = be_mbox_notify_wait(adapter);
4892
4893 mutex_unlock(&adapter->mbox_lock);
4894 return status;
4895}
4896
542963b7
VV		 4897/* Uses MBOX */
4898int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4899{
4900 struct be_cmd_req_get_active_profile *req;
4901 struct be_mcc_wrb *wrb;
4902 int status;
4903
4904 if (mutex_lock_interruptible(&adapter->mbox_lock))
4905 return -1;
4906
4907 wrb = wrb_from_mbox(adapter);
4908 if (!wrb) {
4909 status = -EBUSY;
4910 goto err;
4911 }
4912
4913 req = embedded_payload(wrb);
4914
4915 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4916 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4917 wrb, NULL);
4918
4919 status = be_mbox_notify_wait(adapter);
4920 if (!status) {
4921 struct be_cmd_resp_get_active_profile *resp =
4922 embedded_payload(wrb);
03d28ffe 4923
542963b7
VV		 4924 *profile_id = le16_to_cpu(resp->active_profile_id);
4925 }
4926
4927err:
4928 mutex_unlock(&adapter->mbox_lock);
4929 return status;
4930}
4931
d766e7e6
BX		 4932static int
4933__be_cmd_set_logical_link_config(struct be_adapter *adapter,
4934 int link_state, int version, u8 domain)
bdce2ad7 4935{
bdce2ad7 4936 struct be_cmd_req_set_ll_link *req;
0b98ca2a
SR		 4937 struct be_mcc_wrb *wrb;
4938 u32 link_config = 0;
bdce2ad7
SR		 4939 int status;
4940
b7172414 4941 mutex_lock(&adapter->mcc_lock);
bdce2ad7
SR		 4942
4943 wrb = wrb_from_mccq(adapter);
4944 if (!wrb) {
4945 status = -EBUSY;
4946 goto err;
4947 }
4948
4949 req = embedded_payload(wrb);
4950
4951 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4952 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4953 sizeof(*req), wrb, NULL);
4954
d9d426af 4955 req->hdr.version = version;
bdce2ad7
SR		 4956 req->hdr.domain = domain;
4957
d9d426af
SR		 4958 if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4959 link_state == IFLA_VF_LINK_STATE_AUTO)
0b98ca2a 4960 link_config |= PLINK_ENABLE;
bdce2ad7
SR		 4961
4962 if (link_state == IFLA_VF_LINK_STATE_AUTO)
0b98ca2a
SR		 4963 link_config |= PLINK_TRACK;
4964
4965 req->link_config = cpu_to_le32(link_config);
bdce2ad7
SR		 4966
4967 status = be_mcc_notify_wait(adapter);
4968err:
b7172414 4969 mutex_unlock(&adapter->mcc_lock);
bdce2ad7
SR		 4970 return status;
4971}
4972
d9d426af
SR		 4973int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4974 int link_state, u8 domain)
4975{
4976 int status;
4977
dc6e8511 4978 if (BE2_chip(adapter))
d9d426af
SR		 4979 return -EOPNOTSUPP;
4980
4981 status = __be_cmd_set_logical_link_config(adapter, link_state,
4982 2, domain);
4983
4984 /* Version 2 of the command will not be recognized by older FW.
4985 * On such a failure issue version 1 of the command.
4986 */
4987 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4988 status = __be_cmd_set_logical_link_config(adapter, link_state,
4989 1, domain);
4990 return status;
4991}
710f3e59
SB		 4992
4993int be_cmd_set_features(struct be_adapter *adapter)
4994{
4995 struct be_cmd_resp_set_features *resp;
4996 struct be_cmd_req_set_features *req;
4997 struct be_mcc_wrb *wrb;
4998 int status;
4999
5000 if (mutex_lock_interruptible(&adapter->mcc_lock))
5001 return -1;
5002
5003 wrb = wrb_from_mccq(adapter);
5004 if (!wrb) {
5005 status = -EBUSY;
5006 goto err;
5007 }
5008
5009 req = embedded_payload(wrb);
5010
5011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
5012 OPCODE_COMMON_SET_FEATURES,
5013 sizeof(*req), wrb, NULL);
5014
5015 req->features = cpu_to_le32(BE_FEATURE_UE_RECOVERY);
5016 req->parameter_len = cpu_to_le32(sizeof(struct be_req_ue_recovery));
5017 req->parameter.req.uer = cpu_to_le32(BE_UE_RECOVERY_UER_MASK);
5018
5019 status = be_mcc_notify_wait(adapter);
5020 if (status)
5021 goto err;
5022
5023 resp = embedded_payload(wrb);
5024
5025 adapter->error_recovery.ue_to_poll_time =
5026 le16_to_cpu(resp->parameter.resp.ue2rp);
5027 adapter->error_recovery.ue_to_reset_time =
5028 le16_to_cpu(resp->parameter.resp.ue2sr);
5029 adapter->error_recovery.recovery_supported = true;
5030err:
5031 /* Checking "MCC_STATUS_INVALID_LENGTH" for SKH as FW
5032 * returns this error in older firmware versions
5033 */
5034 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
5035 base_status(status) == MCC_STATUS_INVALID_LENGTH)
5036 dev_info(&adapter->pdev->dev,
5037 "Adapter does not support HW error recovery\n");
5038
5039 mutex_unlock(&adapter->mcc_lock);
5040 return status;
5041}
5042
6a4ab669 5043int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
a2cc4e0b 5044 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
6a4ab669
PP		 5045{
5046 struct be_adapter *adapter = netdev_priv(netdev_handle);
5047 struct be_mcc_wrb *wrb;
504fbf1e 5048 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
6a4ab669
PP		 5049 struct be_cmd_req_hdr *req;
5050 struct be_cmd_resp_hdr *resp;
5051 int status;
5052
b7172414 5053 mutex_lock(&adapter->mcc_lock);
6a4ab669
PP		 5054
5055 wrb = wrb_from_mccq(adapter);
5056 if (!wrb) {
5057 status = -EBUSY;
5058 goto err;
5059 }
5060 req = embedded_payload(wrb);
5061 resp = embedded_payload(wrb);
5062
5063 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
5064 hdr->opcode, wrb_payload_size, wrb, NULL);
5065 memcpy(req, wrb_payload, wrb_payload_size);
5066 be_dws_cpu_to_le(req, wrb_payload_size);
5067
5068 status = be_mcc_notify_wait(adapter);
5069 if (cmd_status)
5070 *cmd_status = (status & 0xffff);
5071 if (ext_status)
5072 *ext_status = 0;
5073 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
5074 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
5075err:
b7172414 5076 mutex_unlock(&adapter->mcc_lock);
6a4ab669
PP		 5077 return status;
5078}
5079EXPORT_SYMBOL(be_roce_mcc_cmd);
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