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be2net: stop checking the UE registers after an EEH error
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / emulex / benet / be_main.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
70c71606 18#include <linux/prefetch.h>
9d9779e7 19#include <linux/module.h>
6b7c5b94 20#include "be.h"
8788fdc2 21#include "be_cmds.h"
65f71b8b 22#include <asm/div64.h>
6b7c5b94
SP		 23
24MODULE_VERSION(DRV_VER);
25MODULE_DEVICE_TABLE(pci, be_dev_ids);
26MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
27MODULE_AUTHOR("ServerEngines Corporation");
28MODULE_LICENSE("GPL");
29
2e588f84 30static ushort rx_frag_size = 2048;
ba343c77 31static unsigned int num_vfs;
2e588f84 32module_param(rx_frag_size, ushort, S_IRUGO);
ba343c77 33module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 34MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 35MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 36
6b7c5b94 37static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 38 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 39 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 40 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
41 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
fe6d2a38 42 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID3)},
12f4d0a8 43 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID4)},
6b7c5b94
SP		 44 { 0 }
45};
46MODULE_DEVICE_TABLE(pci, be_dev_ids);
7c185276 47/* UE Status Low CSR */
42c8b11e 48static const char * const ue_status_low_desc[] = {
7c185276
AK		 49 "CEV",
50 "CTX",
51 "DBUF",
52 "ERX",
53 "Host",
54 "MPU",
55 "NDMA",
56 "PTC ",
57 "RDMA ",
58 "RXF ",
59 "RXIPS ",
60 "RXULP0 ",
61 "RXULP1 ",
62 "RXULP2 ",
63 "TIM ",
64 "TPOST ",
65 "TPRE ",
66 "TXIPS ",
67 "TXULP0 ",
68 "TXULP1 ",
69 "UC ",
70 "WDMA ",
71 "TXULP2 ",
72 "HOST1 ",
73 "P0_OB_LINK ",
74 "P1_OB_LINK ",
75 "HOST_GPIO ",
76 "MBOX ",
77 "AXGMAC0",
78 "AXGMAC1",
79 "JTAG",
80 "MPU_INTPEND"
81};
82/* UE Status High CSR */
42c8b11e 83static const char * const ue_status_hi_desc[] = {
7c185276
AK		 84 "LPCMEMHOST",
85 "MGMT_MAC",
86 "PCS0ONLINE",
87 "MPU_IRAM",
88 "PCS1ONLINE",
89 "PCTL0",
90 "PCTL1",
91 "PMEM",
92 "RR",
93 "TXPB",
94 "RXPP",
95 "XAUI",
96 "TXP",
97 "ARM",
98 "IPC",
99 "HOST2",
100 "HOST3",
101 "HOST4",
102 "HOST5",
103 "HOST6",
104 "HOST7",
105 "HOST8",
106 "HOST9",
42c8b11e 107 "NETC",
7c185276
AK		 108 "Unknown",
109 "Unknown",
110 "Unknown",
111 "Unknown",
112 "Unknown",
113 "Unknown",
114 "Unknown",
115 "Unknown"
116};
6b7c5b94 117
752961a1
SP		 118/* Is BE in a multi-channel mode */
119static inline bool be_is_mc(struct be_adapter *adapter) {
120 return (adapter->function_mode & FLEX10_MODE ||
121 adapter->function_mode & VNIC_MODE ||
122 adapter->function_mode & UMC_ENABLED);
123}
124
6b7c5b94
SP		 125static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
126{
127 struct be_dma_mem *mem = &q->dma_mem;
128 if (mem->va)
2b7bcebf
IV		 129 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
130 mem->dma);
6b7c5b94
SP		 131}
132
133static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
134 u16 len, u16 entry_size)
135{
136 struct be_dma_mem *mem = &q->dma_mem;
137
138 memset(q, 0, sizeof(*q));
139 q->len = len;
140 q->entry_size = entry_size;
141 mem->size = len * entry_size;
2b7bcebf
IV		 142 mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma,
143 GFP_KERNEL);
6b7c5b94
SP		 144 if (!mem->va)
145 return -1;
146 memset(mem->va, 0, mem->size);
147 return 0;
148}
149
8788fdc2 150static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 151{
db3ea781 152 u32 reg, enabled;
5f0b849e 153
cf588477
SP		 154 if (adapter->eeh_err)
155 return;
156
db3ea781
SP		 157 pci_read_config_dword(adapter->pdev, PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET,
158 &reg);
159 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
160
5f0b849e 161 if (!enabled && enable)
6b7c5b94 162 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 163 else if (enabled && !enable)
6b7c5b94 164 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 165 else
6b7c5b94 166 return;
5f0b849e 167
db3ea781
SP		 168 pci_write_config_dword(adapter->pdev,
169 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET, reg);
6b7c5b94
SP		 170}
171
8788fdc2 172static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 173{
174 u32 val = 0;
175 val |= qid & DB_RQ_RING_ID_MASK;
176 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 177
178 wmb();
8788fdc2 179 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 180}
181
8788fdc2 182static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 183{
184 u32 val = 0;
185 val |= qid & DB_TXULP_RING_ID_MASK;
186 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 187
188 wmb();
8788fdc2 189 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 190}
191
8788fdc2 192static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 193 bool arm, bool clear_int, u16 num_popped)
194{
195 u32 val = 0;
196 val |= qid & DB_EQ_RING_ID_MASK;
fe6d2a38
SP		 197 val |= ((qid & DB_EQ_RING_ID_EXT_MASK) <<
198 DB_EQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 199
200 if (adapter->eeh_err)
201 return;
202
6b7c5b94
SP		 203 if (arm)
204 val |= 1 << DB_EQ_REARM_SHIFT;
205 if (clear_int)
206 val |= 1 << DB_EQ_CLR_SHIFT;
207 val |= 1 << DB_EQ_EVNT_SHIFT;
208 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 209 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 210}
211
8788fdc2 212void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 213{
214 u32 val = 0;
215 val |= qid & DB_CQ_RING_ID_MASK;
fe6d2a38
SP		 216 val |= ((qid & DB_CQ_RING_ID_EXT_MASK) <<
217 DB_CQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 218
219 if (adapter->eeh_err)
220 return;
221
6b7c5b94
SP		 222 if (arm)
223 val |= 1 << DB_CQ_REARM_SHIFT;
224 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 225 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 226}
227
6b7c5b94
SP		 228static int be_mac_addr_set(struct net_device *netdev, void *p)
229{
230 struct be_adapter *adapter = netdev_priv(netdev);
231 struct sockaddr *addr = p;
232 int status = 0;
e3a7ae2c
SK		 233 u8 current_mac[ETH_ALEN];
234 u32 pmac_id = adapter->pmac_id;
6b7c5b94 235
ca9e4988
AK		 236 if (!is_valid_ether_addr(addr->sa_data))
237 return -EADDRNOTAVAIL;
238
e3a7ae2c
SK		 239 status = be_cmd_mac_addr_query(adapter, current_mac,
240 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
a65027e4 241 if (status)
e3a7ae2c 242 goto err;
6b7c5b94 243
e3a7ae2c
SK		 244 if (memcmp(addr->sa_data, current_mac, ETH_ALEN)) {
245 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
f8617e08 246 adapter->if_handle, &adapter->pmac_id, 0);
e3a7ae2c
SK		 247 if (status)
248 goto err;
6b7c5b94 249
e3a7ae2c
SK		 250 be_cmd_pmac_del(adapter, adapter->if_handle, pmac_id, 0);
251 }
252 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
253 return 0;
254err:
255 dev_err(&adapter->pdev->dev, "MAC %pM set Failed\n", addr->sa_data);
6b7c5b94
SP		 256 return status;
257}
258
89a88ab8
AK		 259static void populate_be2_stats(struct be_adapter *adapter)
260{
ac124ff9
SP		 261 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
262 struct be_pmem_stats *pmem_sts = &hw_stats->pmem;
263 struct be_rxf_stats_v0 *rxf_stats = &hw_stats->rxf;
89a88ab8 264 struct be_port_rxf_stats_v0 *port_stats =
ac124ff9
SP		 265 &rxf_stats->port[adapter->port_num];
266 struct be_drv_stats *drvs = &adapter->drv_stats;
89a88ab8 267
ac124ff9 268 be_dws_le_to_cpu(hw_stats, sizeof(*hw_stats));
89a88ab8
AK		 269 drvs->rx_pause_frames = port_stats->rx_pause_frames;
270 drvs->rx_crc_errors = port_stats->rx_crc_errors;
271 drvs->rx_control_frames = port_stats->rx_control_frames;
272 drvs->rx_in_range_errors = port_stats->rx_in_range_errors;
273 drvs->rx_frame_too_long = port_stats->rx_frame_too_long;
274 drvs->rx_dropped_runt = port_stats->rx_dropped_runt;
275 drvs->rx_ip_checksum_errs = port_stats->rx_ip_checksum_errs;
276 drvs->rx_tcp_checksum_errs = port_stats->rx_tcp_checksum_errs;
277 drvs->rx_udp_checksum_errs = port_stats->rx_udp_checksum_errs;
278 drvs->rxpp_fifo_overflow_drop = port_stats->rx_fifo_overflow;
279 drvs->rx_dropped_tcp_length = port_stats->rx_dropped_tcp_length;
280 drvs->rx_dropped_too_small = port_stats->rx_dropped_too_small;
281 drvs->rx_dropped_too_short = port_stats->rx_dropped_too_short;
282 drvs->rx_out_range_errors = port_stats->rx_out_range_errors;
ac124ff9 283 drvs->rx_input_fifo_overflow_drop = port_stats->rx_input_fifo_overflow;
89a88ab8
AK		 284 drvs->rx_dropped_header_too_small =
285 port_stats->rx_dropped_header_too_small;
ac124ff9 286 drvs->rx_address_match_errors = port_stats->rx_address_match_errors;
89a88ab8
AK		 287 drvs->rx_alignment_symbol_errors =
288 port_stats->rx_alignment_symbol_errors;
289
290 drvs->tx_pauseframes = port_stats->tx_pauseframes;
291 drvs->tx_controlframes = port_stats->tx_controlframes;
292
293 if (adapter->port_num)
ac124ff9 294 drvs->jabber_events = rxf_stats->port1_jabber_events;
89a88ab8 295 else
ac124ff9 296 drvs->jabber_events = rxf_stats->port0_jabber_events;
89a88ab8
AK		 297 drvs->rx_drops_no_pbuf = rxf_stats->rx_drops_no_pbuf;
298 drvs->rx_drops_no_txpb = rxf_stats->rx_drops_no_txpb;
299 drvs->rx_drops_no_erx_descr = rxf_stats->rx_drops_no_erx_descr;
300 drvs->rx_drops_invalid_ring = rxf_stats->rx_drops_invalid_ring;
301 drvs->forwarded_packets = rxf_stats->forwarded_packets;
302 drvs->rx_drops_mtu = rxf_stats->rx_drops_mtu;
ac124ff9
SP		 303 drvs->rx_drops_no_tpre_descr = rxf_stats->rx_drops_no_tpre_descr;
304 drvs->rx_drops_too_many_frags = rxf_stats->rx_drops_too_many_frags;
89a88ab8
AK		 305 adapter->drv_stats.eth_red_drops = pmem_sts->eth_red_drops;
306}
307
308static void populate_be3_stats(struct be_adapter *adapter)
309{
ac124ff9
SP		 310 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
311 struct be_pmem_stats *pmem_sts = &hw_stats->pmem;
312 struct be_rxf_stats_v1 *rxf_stats = &hw_stats->rxf;
89a88ab8 313 struct be_port_rxf_stats_v1 *port_stats =
ac124ff9
SP		 314 &rxf_stats->port[adapter->port_num];
315 struct be_drv_stats *drvs = &adapter->drv_stats;
89a88ab8 316
ac124ff9 317 be_dws_le_to_cpu(hw_stats, sizeof(*hw_stats));
89a88ab8
AK		 318 drvs->rx_pause_frames = port_stats->rx_pause_frames;
319 drvs->rx_crc_errors = port_stats->rx_crc_errors;
320 drvs->rx_control_frames = port_stats->rx_control_frames;
321 drvs->rx_in_range_errors = port_stats->rx_in_range_errors;
322 drvs->rx_frame_too_long = port_stats->rx_frame_too_long;
323 drvs->rx_dropped_runt = port_stats->rx_dropped_runt;
324 drvs->rx_ip_checksum_errs = port_stats->rx_ip_checksum_errs;
325 drvs->rx_tcp_checksum_errs = port_stats->rx_tcp_checksum_errs;
326 drvs->rx_udp_checksum_errs = port_stats->rx_udp_checksum_errs;
327 drvs->rx_dropped_tcp_length = port_stats->rx_dropped_tcp_length;
328 drvs->rx_dropped_too_small = port_stats->rx_dropped_too_small;
329 drvs->rx_dropped_too_short = port_stats->rx_dropped_too_short;
330 drvs->rx_out_range_errors = port_stats->rx_out_range_errors;
331 drvs->rx_dropped_header_too_small =
332 port_stats->rx_dropped_header_too_small;
333 drvs->rx_input_fifo_overflow_drop =
334 port_stats->rx_input_fifo_overflow_drop;
ac124ff9 335 drvs->rx_address_match_errors = port_stats->rx_address_match_errors;
89a88ab8
AK		 336 drvs->rx_alignment_symbol_errors =
337 port_stats->rx_alignment_symbol_errors;
ac124ff9 338 drvs->rxpp_fifo_overflow_drop = port_stats->rxpp_fifo_overflow_drop;
89a88ab8
AK		 339 drvs->tx_pauseframes = port_stats->tx_pauseframes;
340 drvs->tx_controlframes = port_stats->tx_controlframes;
341 drvs->jabber_events = port_stats->jabber_events;
342 drvs->rx_drops_no_pbuf = rxf_stats->rx_drops_no_pbuf;
343 drvs->rx_drops_no_txpb = rxf_stats->rx_drops_no_txpb;
344 drvs->rx_drops_no_erx_descr = rxf_stats->rx_drops_no_erx_descr;
345 drvs->rx_drops_invalid_ring = rxf_stats->rx_drops_invalid_ring;
346 drvs->forwarded_packets = rxf_stats->forwarded_packets;
347 drvs->rx_drops_mtu = rxf_stats->rx_drops_mtu;
ac124ff9
SP		 348 drvs->rx_drops_no_tpre_descr = rxf_stats->rx_drops_no_tpre_descr;
349 drvs->rx_drops_too_many_frags = rxf_stats->rx_drops_too_many_frags;
89a88ab8
AK		 350 adapter->drv_stats.eth_red_drops = pmem_sts->eth_red_drops;
351}
352
005d5696
SX		 353static void populate_lancer_stats(struct be_adapter *adapter)
354{
89a88ab8 355
005d5696 356 struct be_drv_stats *drvs = &adapter->drv_stats;
ac124ff9
SP		 357 struct lancer_pport_stats *pport_stats =
358 pport_stats_from_cmd(adapter);
359
360 be_dws_le_to_cpu(pport_stats, sizeof(*pport_stats));
361 drvs->rx_pause_frames = pport_stats->rx_pause_frames_lo;
362 drvs->rx_crc_errors = pport_stats->rx_crc_errors_lo;
363 drvs->rx_control_frames = pport_stats->rx_control_frames_lo;
005d5696 364 drvs->rx_in_range_errors = pport_stats->rx_in_range_errors;
ac124ff9 365 drvs->rx_frame_too_long = pport_stats->rx_frames_too_long_lo;
005d5696
SX		 366 drvs->rx_dropped_runt = pport_stats->rx_dropped_runt;
367 drvs->rx_ip_checksum_errs = pport_stats->rx_ip_checksum_errors;
368 drvs->rx_tcp_checksum_errs = pport_stats->rx_tcp_checksum_errors;
369 drvs->rx_udp_checksum_errs = pport_stats->rx_udp_checksum_errors;
370 drvs->rx_dropped_tcp_length =
371 pport_stats->rx_dropped_invalid_tcp_length;
372 drvs->rx_dropped_too_small = pport_stats->rx_dropped_too_small;
373 drvs->rx_dropped_too_short = pport_stats->rx_dropped_too_short;
374 drvs->rx_out_range_errors = pport_stats->rx_out_of_range_errors;
375 drvs->rx_dropped_header_too_small =
376 pport_stats->rx_dropped_header_too_small;
377 drvs->rx_input_fifo_overflow_drop = pport_stats->rx_fifo_overflow;
378 drvs->rx_address_match_errors = pport_stats->rx_address_match_errors;
ac124ff9 379 drvs->rx_alignment_symbol_errors = pport_stats->rx_symbol_errors_lo;
005d5696 380 drvs->rxpp_fifo_overflow_drop = pport_stats->rx_fifo_overflow;
ac124ff9
SP		 381 drvs->tx_pauseframes = pport_stats->tx_pause_frames_lo;
382 drvs->tx_controlframes = pport_stats->tx_control_frames_lo;
005d5696 383 drvs->jabber_events = pport_stats->rx_jabbers;
005d5696 384 drvs->rx_drops_invalid_ring = pport_stats->rx_drops_invalid_queue;
ac124ff9
SP		 385 drvs->forwarded_packets = pport_stats->num_forwards_lo;
386 drvs->rx_drops_mtu = pport_stats->rx_drops_mtu_lo;
005d5696 387 drvs->rx_drops_too_many_frags =
ac124ff9 388 pport_stats->rx_drops_too_many_frags_lo;
005d5696 389}
89a88ab8 390
09c1c68f
SP		 391static void accumulate_16bit_val(u32 *acc, u16 val)
392{
393#define lo(x) (x & 0xFFFF)
394#define hi(x) (x & 0xFFFF0000)
395 bool wrapped = val < lo(*acc);
396 u32 newacc = hi(*acc) + val;
397
398 if (wrapped)
399 newacc += 65536;
400 ACCESS_ONCE(*acc) = newacc;
401}
402
89a88ab8
AK		 403void be_parse_stats(struct be_adapter *adapter)
404{
ac124ff9
SP		 405 struct be_erx_stats_v1 *erx = be_erx_stats_from_cmd(adapter);
406 struct be_rx_obj *rxo;
407 int i;
408
005d5696
SX		 409 if (adapter->generation == BE_GEN3) {
410 if (lancer_chip(adapter))
411 populate_lancer_stats(adapter);
412 else
413 populate_be3_stats(adapter);
414 } else {
89a88ab8 415 populate_be2_stats(adapter);
005d5696 416 }
ac124ff9
SP		 417
418 /* as erx_v1 is longer than v0, ok to use v1 defn for v0 access */
09c1c68f
SP		 419 for_all_rx_queues(adapter, rxo, i) {
420 /* below erx HW counter can actually wrap around after
421 * 65535. Driver accumulates a 32-bit value
422 */
423 accumulate_16bit_val(&rx_stats(rxo)->rx_drops_no_frags,
424 (u16)erx->rx_drops_no_fragments[rxo->q.id]);
425 }
89a88ab8
AK		 426}
427
ab1594e9
SP		 428static struct rtnl_link_stats64 *be_get_stats64(struct net_device *netdev,
429 struct rtnl_link_stats64 *stats)
6b7c5b94 430{
ab1594e9 431 struct be_adapter *adapter = netdev_priv(netdev);
89a88ab8 432 struct be_drv_stats *drvs = &adapter->drv_stats;
3abcdeda 433 struct be_rx_obj *rxo;
3c8def97 434 struct be_tx_obj *txo;
ab1594e9
SP		 435 u64 pkts, bytes;
436 unsigned int start;
3abcdeda 437 int i;
6b7c5b94 438
3abcdeda 439 for_all_rx_queues(adapter, rxo, i) {
ab1594e9
SP		 440 const struct be_rx_stats *rx_stats = rx_stats(rxo);
441 do {
442 start = u64_stats_fetch_begin_bh(&rx_stats->sync);
443 pkts = rx_stats(rxo)->rx_pkts;
444 bytes = rx_stats(rxo)->rx_bytes;
445 } while (u64_stats_fetch_retry_bh(&rx_stats->sync, start));
446 stats->rx_packets += pkts;
447 stats->rx_bytes += bytes;
448 stats->multicast += rx_stats(rxo)->rx_mcast_pkts;
449 stats->rx_dropped += rx_stats(rxo)->rx_drops_no_skbs +
450 rx_stats(rxo)->rx_drops_no_frags;
3abcdeda
SP		 451 }
452
3c8def97 453 for_all_tx_queues(adapter, txo, i) {
ab1594e9
SP		 454 const struct be_tx_stats *tx_stats = tx_stats(txo);
455 do {
456 start = u64_stats_fetch_begin_bh(&tx_stats->sync);
457 pkts = tx_stats(txo)->tx_pkts;
458 bytes = tx_stats(txo)->tx_bytes;
459 } while (u64_stats_fetch_retry_bh(&tx_stats->sync, start));
460 stats->tx_packets += pkts;
461 stats->tx_bytes += bytes;
3c8def97 462 }
6b7c5b94
SP		 463
464 /* bad pkts received */
ab1594e9 465 stats->rx_errors = drvs->rx_crc_errors +
89a88ab8
AK		 466 drvs->rx_alignment_symbol_errors +
467 drvs->rx_in_range_errors +
468 drvs->rx_out_range_errors +
469 drvs->rx_frame_too_long +
470 drvs->rx_dropped_too_small +
471 drvs->rx_dropped_too_short +
472 drvs->rx_dropped_header_too_small +
473 drvs->rx_dropped_tcp_length +
ab1594e9 474 drvs->rx_dropped_runt;
68110868 475
6b7c5b94 476 /* detailed rx errors */
ab1594e9 477 stats->rx_length_errors = drvs->rx_in_range_errors +
89a88ab8
AK		 478 drvs->rx_out_range_errors +
479 drvs->rx_frame_too_long;
68110868 480
ab1594e9 481 stats->rx_crc_errors = drvs->rx_crc_errors;
6b7c5b94
SP		 482
483 /* frame alignment errors */
ab1594e9 484 stats->rx_frame_errors = drvs->rx_alignment_symbol_errors;
68110868 485
6b7c5b94
SP		 486 /* receiver fifo overrun */
487 /* drops_no_pbuf is no per i/f, it's per BE card */
ab1594e9 488 stats->rx_fifo_errors = drvs->rxpp_fifo_overflow_drop +
89a88ab8
AK		 489 drvs->rx_input_fifo_overflow_drop +
490 drvs->rx_drops_no_pbuf;
ab1594e9 491 return stats;
6b7c5b94
SP		 492}
493
ea172a01 494void be_link_status_update(struct be_adapter *adapter, u32 link_status)
6b7c5b94 495{
6b7c5b94
SP		 496 struct net_device *netdev = adapter->netdev;
497
ea172a01
SP		 498 /* when link status changes, link speed must be re-queried from card */
499 adapter->link_speed = -1;
500 if ((link_status & LINK_STATUS_MASK) == LINK_UP) {
501 netif_carrier_on(netdev);
502 dev_info(&adapter->pdev->dev, "%s: Link up\n", netdev->name);
503 } else {
504 netif_carrier_off(netdev);
505 dev_info(&adapter->pdev->dev, "%s: Link down\n", netdev->name);
6b7c5b94 506 }
6b7c5b94
SP		 507}
508
3c8def97 509static void be_tx_stats_update(struct be_tx_obj *txo,
91992e44 510 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 511{
3c8def97
SP		 512 struct be_tx_stats *stats = tx_stats(txo);
513
ab1594e9 514 u64_stats_update_begin(&stats->sync);
ac124ff9
SP		 515 stats->tx_reqs++;
516 stats->tx_wrbs += wrb_cnt;
517 stats->tx_bytes += copied;
518 stats->tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94 519 if (stopped)
ac124ff9 520 stats->tx_stops++;
ab1594e9 521 u64_stats_update_end(&stats->sync);
6b7c5b94
SP		 522}
523
524/* Determine number of WRB entries needed to xmit data in an skb */
fe6d2a38
SP		 525static u32 wrb_cnt_for_skb(struct be_adapter *adapter, struct sk_buff *skb,
526 bool *dummy)
6b7c5b94 527{
ebc8d2ab
DM		 528 int cnt = (skb->len > skb->data_len);
529
530 cnt += skb_shinfo(skb)->nr_frags;
531
6b7c5b94
SP		 532 /* to account for hdr wrb */
533 cnt++;
fe6d2a38
SP		 534 if (lancer_chip(adapter) || !(cnt & 1)) {
535 *dummy = false;
536 } else {
6b7c5b94
SP		 537 /* add a dummy to make it an even num */
538 cnt++;
539 *dummy = true;
fe6d2a38 540 }
6b7c5b94
SP		 541 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
542 return cnt;
543}
544
545static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
546{
547 wrb->frag_pa_hi = upper_32_bits(addr);
548 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
549 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
550}
551
cc4ce020
SK		 552static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr,
553 struct sk_buff *skb, u32 wrb_cnt, u32 len)
6b7c5b94 554{
cc4ce020
SK		 555 u8 vlan_prio = 0;
556 u16 vlan_tag = 0;
557
6b7c5b94
SP		 558 memset(hdr, 0, sizeof(*hdr));
559
560 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
561
49e4b847 562 if (skb_is_gso(skb)) {
6b7c5b94
SP		 563 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
564 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
565 hdr, skb_shinfo(skb)->gso_size);
fe6d2a38 566 if (skb_is_gso_v6(skb) && !lancer_chip(adapter))
49e4b847 567 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
fe6d2a38
SP		 568 if (lancer_chip(adapter) && adapter->sli_family ==
569 LANCER_A0_SLI_FAMILY) {
570 AMAP_SET_BITS(struct amap_eth_hdr_wrb, ipcs, hdr, 1);
571 if (is_tcp_pkt(skb))
572 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
573 tcpcs, hdr, 1);
574 else if (is_udp_pkt(skb))
575 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
576 udpcs, hdr, 1);
577 }
6b7c5b94
SP		 578 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
579 if (is_tcp_pkt(skb))
580 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
581 else if (is_udp_pkt(skb))
582 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
583 }
584
4c5102f9 585 if (vlan_tx_tag_present(skb)) {
6b7c5b94 586 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
cc4ce020
SK		 587 vlan_tag = vlan_tx_tag_get(skb);
588 vlan_prio = (vlan_tag & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
589 /* If vlan priority provided by OS is NOT in available bmap */
590 if (!(adapter->vlan_prio_bmap & (1 << vlan_prio)))
591 vlan_tag = (vlan_tag & ~VLAN_PRIO_MASK) |
592 adapter->recommended_prio;
593 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag);
6b7c5b94
SP		 594 }
595
596 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
597 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
598 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
599 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
600}
601
2b7bcebf 602static void unmap_tx_frag(struct device *dev, struct be_eth_wrb *wrb,
7101e111
SP		 603 bool unmap_single)
604{
605 dma_addr_t dma;
606
607 be_dws_le_to_cpu(wrb, sizeof(*wrb));
608
609 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 610 if (wrb->frag_len) {
7101e111 611 if (unmap_single)
2b7bcebf
IV		 612 dma_unmap_single(dev, dma, wrb->frag_len,
613 DMA_TO_DEVICE);
7101e111 614 else
2b7bcebf 615 dma_unmap_page(dev, dma, wrb->frag_len, DMA_TO_DEVICE);
7101e111
SP		 616 }
617}
6b7c5b94 618
3c8def97 619static int make_tx_wrbs(struct be_adapter *adapter, struct be_queue_info *txq,
6b7c5b94
SP		 620 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
621{
7101e111
SP		 622 dma_addr_t busaddr;
623 int i, copied = 0;
2b7bcebf 624 struct device *dev = &adapter->pdev->dev;
6b7c5b94 625 struct sk_buff *first_skb = skb;
6b7c5b94
SP		 626 struct be_eth_wrb *wrb;
627 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 628 bool map_single = false;
629 u16 map_head;
6b7c5b94 630
6b7c5b94
SP		 631 hdr = queue_head_node(txq);
632 queue_head_inc(txq);
7101e111 633 map_head = txq->head;
6b7c5b94 634
ebc8d2ab 635 if (skb->len > skb->data_len) {
e743d313 636 int len = skb_headlen(skb);
2b7bcebf
IV		 637 busaddr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
638 if (dma_mapping_error(dev, busaddr))
7101e111
SP		 639 goto dma_err;
640 map_single = true;
ebc8d2ab
DM		 641 wrb = queue_head_node(txq);
642 wrb_fill(wrb, busaddr, len);
643 be_dws_cpu_to_le(wrb, sizeof(*wrb));
644 queue_head_inc(txq);
645 copied += len;
646 }
6b7c5b94 647
ebc8d2ab 648 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 649 const struct skb_frag_struct *frag =
ebc8d2ab 650 &skb_shinfo(skb)->frags[i];
b061b39e 651 busaddr = skb_frag_dma_map(dev, frag, 0,
9e903e08 652 skb_frag_size(frag), DMA_TO_DEVICE);
2b7bcebf 653 if (dma_mapping_error(dev, busaddr))
7101e111 654 goto dma_err;
ebc8d2ab 655 wrb = queue_head_node(txq);
9e903e08 656 wrb_fill(wrb, busaddr, skb_frag_size(frag));
ebc8d2ab
DM		 657 be_dws_cpu_to_le(wrb, sizeof(*wrb));
658 queue_head_inc(txq);
9e903e08 659 copied += skb_frag_size(frag);
6b7c5b94
SP		 660 }
661
662 if (dummy_wrb) {
663 wrb = queue_head_node(txq);
664 wrb_fill(wrb, 0, 0);
665 be_dws_cpu_to_le(wrb, sizeof(*wrb));
666 queue_head_inc(txq);
667 }
668
cc4ce020 669 wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied);
6b7c5b94
SP		 670 be_dws_cpu_to_le(hdr, sizeof(*hdr));
671
672 return copied;
7101e111
SP		 673dma_err:
674 txq->head = map_head;
675 while (copied) {
676 wrb = queue_head_node(txq);
2b7bcebf 677 unmap_tx_frag(dev, wrb, map_single);
7101e111
SP		 678 map_single = false;
679 copied -= wrb->frag_len;
680 queue_head_inc(txq);
681 }
682 return 0;
6b7c5b94
SP		 683}
684
61357325 685static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 686 struct net_device *netdev)
6b7c5b94
SP		 687{
688 struct be_adapter *adapter = netdev_priv(netdev);
3c8def97
SP		 689 struct be_tx_obj *txo = &adapter->tx_obj[skb_get_queue_mapping(skb)];
690 struct be_queue_info *txq = &txo->q;
6b7c5b94
SP		 691 u32 wrb_cnt = 0, copied = 0;
692 u32 start = txq->head;
693 bool dummy_wrb, stopped = false;
694
fe6d2a38 695 wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb);
6b7c5b94 696
3c8def97 697 copied = make_tx_wrbs(adapter, txq, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 698 if (copied) {
699 /* record the sent skb in the sent_skb table */
3c8def97
SP		 700 BUG_ON(txo->sent_skb_list[start]);
701 txo->sent_skb_list[start] = skb;
c190e3c8
AK		 702
703 /* Ensure txq has space for the next skb; Else stop the queue
704 * *BEFORE* ringing the tx doorbell, so that we serialze the
705 * tx compls of the current transmit which'll wake up the queue
706 */
7101e111 707 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 708 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
709 txq->len) {
3c8def97 710 netif_stop_subqueue(netdev, skb_get_queue_mapping(skb));
c190e3c8
AK		 711 stopped = true;
712 }
6b7c5b94 713
c190e3c8 714 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 715
3c8def97 716 be_tx_stats_update(txo, wrb_cnt, copied,
91992e44 717 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 718 } else {
719 txq->head = start;
720 dev_kfree_skb_any(skb);
6b7c5b94 721 }
6b7c5b94
SP		 722 return NETDEV_TX_OK;
723}
724
725static int be_change_mtu(struct net_device *netdev, int new_mtu)
726{
727 struct be_adapter *adapter = netdev_priv(netdev);
728 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 729 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
730 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 731 dev_info(&adapter->pdev->dev,
732 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 733 BE_MIN_MTU,
734 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 735 return -EINVAL;
736 }
737 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
738 netdev->mtu, new_mtu);
739 netdev->mtu = new_mtu;
740 return 0;
741}
742
743/*
82903e4b
AK		 744 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
745 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 746 */
1da87b7f 747static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num)
6b7c5b94 748{
6b7c5b94
SP		 749 u16 vtag[BE_NUM_VLANS_SUPPORTED];
750 u16 ntags = 0, i;
82903e4b 751 int status = 0;
1da87b7f
AK		 752 u32 if_handle;
753
754 if (vf) {
755 if_handle = adapter->vf_cfg[vf_num].vf_if_handle;
756 vtag[0] = cpu_to_le16(adapter->vf_cfg[vf_num].vf_vlan_tag);
757 status = be_cmd_vlan_config(adapter, if_handle, vtag, 1, 1, 0);
758 }
6b7c5b94 759
c0e64ef4
SP		 760 /* No need to further configure vids if in promiscuous mode */
761 if (adapter->promiscuous)
762 return 0;
763
82903e4b 764 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94 765 /* Construct VLAN Table to give to HW */
b738127d 766 for (i = 0; i < VLAN_N_VID; i++) {
6b7c5b94
SP		 767 if (adapter->vlan_tag[i]) {
768 vtag[ntags] = cpu_to_le16(i);
769 ntags++;
770 }
771 }
b31c50a7
SP		 772 status = be_cmd_vlan_config(adapter, adapter->if_handle,
773 vtag, ntags, 1, 0);
6b7c5b94 774 } else {
b31c50a7
SP		 775 status = be_cmd_vlan_config(adapter, adapter->if_handle,
776 NULL, 0, 1, 1);
6b7c5b94 777 }
1da87b7f 778
b31c50a7 779 return status;
6b7c5b94
SP		 780}
781
6b7c5b94
SP		 782static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
783{
784 struct be_adapter *adapter = netdev_priv(netdev);
785
1da87b7f 786 adapter->vlans_added++;
ba343c77
SB		 787 if (!be_physfn(adapter))
788 return;
789
6b7c5b94 790 adapter->vlan_tag[vid] = 1;
82903e4b 791 if (adapter->vlans_added <= (adapter->max_vlans + 1))
1da87b7f 792 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 793}
794
795static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
796{
797 struct be_adapter *adapter = netdev_priv(netdev);
798
1da87b7f 799 adapter->vlans_added--;
1da87b7f 800
ba343c77
SB		 801 if (!be_physfn(adapter))
802 return;
803
6b7c5b94 804 adapter->vlan_tag[vid] = 0;
82903e4b 805 if (adapter->vlans_added <= adapter->max_vlans)
1da87b7f 806 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 807}
808
a54769f5 809static void be_set_rx_mode(struct net_device *netdev)
6b7c5b94
SP		 810{
811 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 812
24307eef 813 if (netdev->flags & IFF_PROMISC) {
5b8821b7 814 be_cmd_rx_filter(adapter, IFF_PROMISC, ON);
24307eef
SP		 815 adapter->promiscuous = true;
816 goto done;
6b7c5b94
SP		 817 }
818
25985edc 819 /* BE was previously in promiscuous mode; disable it */
24307eef
SP		 820 if (adapter->promiscuous) {
821 adapter->promiscuous = false;
5b8821b7 822 be_cmd_rx_filter(adapter, IFF_PROMISC, OFF);
c0e64ef4
SP		 823
824 if (adapter->vlans_added)
825 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 826 }
827
e7b909a6 828 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf 829 if (netdev->flags & IFF_ALLMULTI ||
5b8821b7
SP		 830 netdev_mc_count(netdev) > BE_MAX_MC) {
831 be_cmd_rx_filter(adapter, IFF_ALLMULTI, ON);
24307eef 832 goto done;
6b7c5b94 833 }
6b7c5b94 834
5b8821b7 835 be_cmd_rx_filter(adapter, IFF_MULTICAST, ON);
24307eef
SP		 836done:
837 return;
6b7c5b94
SP		 838}
839
ba343c77
SB		 840static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
841{
842 struct be_adapter *adapter = netdev_priv(netdev);
843 int status;
844
845 if (!adapter->sriov_enabled)
846 return -EPERM;
847
848 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
849 return -EINVAL;
850
30128031
SP		 851 status = be_cmd_pmac_del(adapter, adapter->vf_cfg[vf].vf_if_handle,
852 adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
ba343c77 853
30128031 854 status = be_cmd_pmac_add(adapter, mac, adapter->vf_cfg[vf].vf_if_handle,
f8617e08 855 &adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
64600ea5 856 if (status)
ba343c77
SB		 857 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
858 mac, vf);
64600ea5
AK		 859 else
860 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
861
ba343c77
SB		 862 return status;
863}
864
64600ea5
AK		 865static int be_get_vf_config(struct net_device *netdev, int vf,
866 struct ifla_vf_info *vi)
867{
868 struct be_adapter *adapter = netdev_priv(netdev);
869
870 if (!adapter->sriov_enabled)
871 return -EPERM;
872
873 if (vf >= num_vfs)
874 return -EINVAL;
875
876 vi->vf = vf;
e1d18735 877 vi->tx_rate = adapter->vf_cfg[vf].vf_tx_rate;
1da87b7f 878 vi->vlan = adapter->vf_cfg[vf].vf_vlan_tag;
64600ea5
AK		 879 vi->qos = 0;
880 memcpy(&vi->mac, adapter->vf_cfg[vf].vf_mac_addr, ETH_ALEN);
881
882 return 0;
883}
884
1da87b7f
AK		 885static int be_set_vf_vlan(struct net_device *netdev,
886 int vf, u16 vlan, u8 qos)
887{
888 struct be_adapter *adapter = netdev_priv(netdev);
889 int status = 0;
890
891 if (!adapter->sriov_enabled)
892 return -EPERM;
893
894 if ((vf >= num_vfs) || (vlan > 4095))
895 return -EINVAL;
896
897 if (vlan) {
898 adapter->vf_cfg[vf].vf_vlan_tag = vlan;
899 adapter->vlans_added++;
900 } else {
901 adapter->vf_cfg[vf].vf_vlan_tag = 0;
902 adapter->vlans_added--;
903 }
904
905 status = be_vid_config(adapter, true, vf);
906
907 if (status)
908 dev_info(&adapter->pdev->dev,
909 "VLAN %d config on VF %d failed\n", vlan, vf);
910 return status;
911}
912
e1d18735
AK		 913static int be_set_vf_tx_rate(struct net_device *netdev,
914 int vf, int rate)
915{
916 struct be_adapter *adapter = netdev_priv(netdev);
917 int status = 0;
918
919 if (!adapter->sriov_enabled)
920 return -EPERM;
921
922 if ((vf >= num_vfs) || (rate < 0))
923 return -EINVAL;
924
925 if (rate > 10000)
926 rate = 10000;
927
928 adapter->vf_cfg[vf].vf_tx_rate = rate;
856c4012 929 status = be_cmd_set_qos(adapter, rate / 10, vf + 1);
e1d18735
AK		 930
931 if (status)
932 dev_info(&adapter->pdev->dev,
933 "tx rate %d on VF %d failed\n", rate, vf);
934 return status;
935}
936
ac124ff9 937static void be_rx_eqd_update(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94 938{
ac124ff9
SP		 939 struct be_eq_obj *rx_eq = &rxo->rx_eq;
940 struct be_rx_stats *stats = rx_stats(rxo);
4097f663 941 ulong now = jiffies;
ac124ff9 942 ulong delta = now - stats->rx_jiffies;
ab1594e9
SP		 943 u64 pkts;
944 unsigned int start, eqd;
ac124ff9
SP		 945
946 if (!rx_eq->enable_aic)
947 return;
6b7c5b94 948
4097f663 949 /* Wrapped around */
3abcdeda
SP		 950 if (time_before(now, stats->rx_jiffies)) {
951 stats->rx_jiffies = now;
4097f663
SP		 952 return;
953 }
6b7c5b94 954
ac124ff9
SP		 955 /* Update once a second */
956 if (delta < HZ)
6b7c5b94
SP		 957 return;
958
ab1594e9
SP		 959 do {
960 start = u64_stats_fetch_begin_bh(&stats->sync);
961 pkts = stats->rx_pkts;
962 } while (u64_stats_fetch_retry_bh(&stats->sync, start));
963
68c3e5a7 964 stats->rx_pps = (unsigned long)(pkts - stats->rx_pkts_prev) / (delta / HZ);
ab1594e9 965 stats->rx_pkts_prev = pkts;
3abcdeda 966 stats->rx_jiffies = now;
ac124ff9
SP		 967 eqd = stats->rx_pps / 110000;
968 eqd = eqd << 3;
969 if (eqd > rx_eq->max_eqd)
970 eqd = rx_eq->max_eqd;
971 if (eqd < rx_eq->min_eqd)
972 eqd = rx_eq->min_eqd;
973 if (eqd < 10)
974 eqd = 0;
975 if (eqd != rx_eq->cur_eqd) {
976 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
977 rx_eq->cur_eqd = eqd;
978 }
6b7c5b94
SP		 979}
980
3abcdeda 981static void be_rx_stats_update(struct be_rx_obj *rxo,
2e588f84 982 struct be_rx_compl_info *rxcp)
4097f663 983{
ac124ff9 984 struct be_rx_stats *stats = rx_stats(rxo);
1ef78abe 985
ab1594e9 986 u64_stats_update_begin(&stats->sync);
3abcdeda 987 stats->rx_compl++;
2e588f84 988 stats->rx_bytes += rxcp->pkt_size;
3abcdeda 989 stats->rx_pkts++;
2e588f84 990 if (rxcp->pkt_type == BE_MULTICAST_PACKET)
3abcdeda 991 stats->rx_mcast_pkts++;
2e588f84 992 if (rxcp->err)
ac124ff9 993 stats->rx_compl_err++;
ab1594e9 994 u64_stats_update_end(&stats->sync);
4097f663
SP		 995}
996
2e588f84 997static inline bool csum_passed(struct be_rx_compl_info *rxcp)
728a9972 998{
19fad86f
PR		 999 /* L4 checksum is not reliable for non TCP/UDP packets.
1000 * Also ignore ipcksm for ipv6 pkts */
2e588f84
SP		 1001 return (rxcp->tcpf || rxcp->udpf) && rxcp->l4_csum &&
1002 (rxcp->ip_csum || rxcp->ipv6);
728a9972
AK		 1003}
1004
6b7c5b94 1005static struct be_rx_page_info *
3abcdeda
SP		 1006get_rx_page_info(struct be_adapter *adapter,
1007 struct be_rx_obj *rxo,
1008 u16 frag_idx)
6b7c5b94
SP		 1009{
1010 struct be_rx_page_info *rx_page_info;
3abcdeda 1011 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 1012
3abcdeda 1013 rx_page_info = &rxo->page_info_tbl[frag_idx];
6b7c5b94
SP		 1014 BUG_ON(!rx_page_info->page);
1015
205859a2 1016 if (rx_page_info->last_page_user) {
2b7bcebf
IV		 1017 dma_unmap_page(&adapter->pdev->dev,
1018 dma_unmap_addr(rx_page_info, bus),
1019 adapter->big_page_size, DMA_FROM_DEVICE);
205859a2
AK		 1020 rx_page_info->last_page_user = false;
1021 }
6b7c5b94
SP		 1022
1023 atomic_dec(&rxq->used);
1024 return rx_page_info;
1025}
1026
1027/* Throwaway the data in the Rx completion */
1028static void be_rx_compl_discard(struct be_adapter *adapter,
3abcdeda 1029 struct be_rx_obj *rxo,
2e588f84 1030 struct be_rx_compl_info *rxcp)
6b7c5b94 1031{
3abcdeda 1032 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 1033 struct be_rx_page_info *page_info;
2e588f84 1034 u16 i, num_rcvd = rxcp->num_rcvd;
6b7c5b94 1035
e80d9da6 1036 for (i = 0; i < num_rcvd; i++) {
2e588f84 1037 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
e80d9da6
PR		 1038 put_page(page_info->page);
1039 memset(page_info, 0, sizeof(*page_info));
2e588f84 1040 index_inc(&rxcp->rxq_idx, rxq->len);
6b7c5b94
SP		 1041 }
1042}
1043
1044/*
1045 * skb_fill_rx_data forms a complete skb for an ether frame
1046 * indicated by rxcp.
1047 */
3abcdeda 1048static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo,
2e588f84 1049 struct sk_buff *skb, struct be_rx_compl_info *rxcp)
6b7c5b94 1050{
3abcdeda 1051 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 1052 struct be_rx_page_info *page_info;
2e588f84
SP		 1053 u16 i, j;
1054 u16 hdr_len, curr_frag_len, remaining;
6b7c5b94 1055 u8 *start;
6b7c5b94 1056
2e588f84 1057 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
6b7c5b94
SP		 1058 start = page_address(page_info->page) + page_info->page_offset;
1059 prefetch(start);
1060
1061 /* Copy data in the first descriptor of this completion */
2e588f84 1062 curr_frag_len = min(rxcp->pkt_size, rx_frag_size);
6b7c5b94
SP		 1063
1064 /* Copy the header portion into skb_data */
2e588f84 1065 hdr_len = min(BE_HDR_LEN, curr_frag_len);
6b7c5b94
SP		 1066 memcpy(skb->data, start, hdr_len);
1067 skb->len = curr_frag_len;
1068 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
1069 /* Complete packet has now been moved to data */
1070 put_page(page_info->page);
1071 skb->data_len = 0;
1072 skb->tail += curr_frag_len;
1073 } else {
1074 skb_shinfo(skb)->nr_frags = 1;
b061b39e 1075 skb_frag_set_page(skb, 0, page_info->page);
6b7c5b94
SP		 1076 skb_shinfo(skb)->frags[0].page_offset =
1077 page_info->page_offset + hdr_len;
9e903e08 1078 skb_frag_size_set(&skb_shinfo(skb)->frags[0], curr_frag_len - hdr_len);
6b7c5b94 1079 skb->data_len = curr_frag_len - hdr_len;
bdb28a97 1080 skb->truesize += rx_frag_size;
6b7c5b94
SP		 1081 skb->tail += hdr_len;
1082 }
205859a2 1083 page_info->page = NULL;
6b7c5b94 1084
2e588f84
SP		 1085 if (rxcp->pkt_size <= rx_frag_size) {
1086 BUG_ON(rxcp->num_rcvd != 1);
1087 return;
6b7c5b94
SP		 1088 }
1089
1090 /* More frags present for this completion */
2e588f84
SP		 1091 index_inc(&rxcp->rxq_idx, rxq->len);
1092 remaining = rxcp->pkt_size - curr_frag_len;
1093 for (i = 1, j = 0; i < rxcp->num_rcvd; i++) {
1094 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
1095 curr_frag_len = min(remaining, rx_frag_size);
6b7c5b94 1096
bd46cb6c
AK		 1097 /* Coalesce all frags from the same physical page in one slot */
1098 if (page_info->page_offset == 0) {
1099 /* Fresh page */
1100 j++;
b061b39e 1101 skb_frag_set_page(skb, j, page_info->page);
bd46cb6c
AK		 1102 skb_shinfo(skb)->frags[j].page_offset =
1103 page_info->page_offset;
9e903e08 1104 skb_frag_size_set(&skb_shinfo(skb)->frags[j], 0);
bd46cb6c
AK		 1105 skb_shinfo(skb)->nr_frags++;
1106 } else {
1107 put_page(page_info->page);
1108 }
1109
9e903e08 1110 skb_frag_size_add(&skb_shinfo(skb)->frags[j], curr_frag_len);
6b7c5b94
SP		 1111 skb->len += curr_frag_len;
1112 skb->data_len += curr_frag_len;
bdb28a97 1113 skb->truesize += rx_frag_size;
2e588f84
SP		 1114 remaining -= curr_frag_len;
1115 index_inc(&rxcp->rxq_idx, rxq->len);
205859a2 1116 page_info->page = NULL;
6b7c5b94 1117 }
bd46cb6c 1118 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94
SP		 1119}
1120
5be93b9a 1121/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94 1122static void be_rx_compl_process(struct be_adapter *adapter,
3abcdeda 1123 struct be_rx_obj *rxo,
2e588f84 1124 struct be_rx_compl_info *rxcp)
6b7c5b94 1125{
6332c8d3 1126 struct net_device *netdev = adapter->netdev;
6b7c5b94 1127 struct sk_buff *skb;
89420424 1128
6332c8d3 1129 skb = netdev_alloc_skb_ip_align(netdev, BE_HDR_LEN);
a058a632 1130 if (unlikely(!skb)) {
ac124ff9 1131 rx_stats(rxo)->rx_drops_no_skbs++;
3abcdeda 1132 be_rx_compl_discard(adapter, rxo, rxcp);
6b7c5b94
SP		 1133 return;
1134 }
1135
2e588f84 1136 skb_fill_rx_data(adapter, rxo, skb, rxcp);
6b7c5b94 1137
6332c8d3 1138 if (likely((netdev->features & NETIF_F_RXCSUM) && csum_passed(rxcp)))
728a9972 1139 skb->ip_summed = CHECKSUM_UNNECESSARY;
c6ce2f4b
SK		 1140 else
1141 skb_checksum_none_assert(skb);
6b7c5b94 1142
6332c8d3 1143 skb->protocol = eth_type_trans(skb, netdev);
4b972914
AK		 1144 if (adapter->netdev->features & NETIF_F_RXHASH)
1145 skb->rxhash = rxcp->rss_hash;
1146
6b7c5b94 1147
343e43c0 1148 if (rxcp->vlanf)
4c5102f9
AK		 1149 __vlan_hwaccel_put_tag(skb, rxcp->vlan_tag);
1150
1151 netif_receive_skb(skb);
6b7c5b94
SP		 1152}
1153
5be93b9a
AK		 1154/* Process the RX completion indicated by rxcp when GRO is enabled */
1155static void be_rx_compl_process_gro(struct be_adapter *adapter,
3abcdeda 1156 struct be_rx_obj *rxo,
2e588f84 1157 struct be_rx_compl_info *rxcp)
6b7c5b94
SP		 1158{
1159 struct be_rx_page_info *page_info;
5be93b9a 1160 struct sk_buff *skb = NULL;
3abcdeda
SP		 1161 struct be_queue_info *rxq = &rxo->q;
1162 struct be_eq_obj *eq_obj = &rxo->rx_eq;
2e588f84
SP		 1163 u16 remaining, curr_frag_len;
1164 u16 i, j;
3968fa1e 1165
5be93b9a
AK		 1166 skb = napi_get_frags(&eq_obj->napi);
1167 if (!skb) {
3abcdeda 1168 be_rx_compl_discard(adapter, rxo, rxcp);
5be93b9a
AK		 1169 return;
1170 }
1171
2e588f84
SP		 1172 remaining = rxcp->pkt_size;
1173 for (i = 0, j = -1; i < rxcp->num_rcvd; i++) {
1174 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
6b7c5b94
SP		 1175
1176 curr_frag_len = min(remaining, rx_frag_size);
1177
bd46cb6c
AK		 1178 /* Coalesce all frags from the same physical page in one slot */
1179 if (i == 0 || page_info->page_offset == 0) {
1180 /* First frag or Fresh page */
1181 j++;
b061b39e 1182 skb_frag_set_page(skb, j, page_info->page);
5be93b9a
AK		 1183 skb_shinfo(skb)->frags[j].page_offset =
1184 page_info->page_offset;
9e903e08 1185 skb_frag_size_set(&skb_shinfo(skb)->frags[j], 0);
bd46cb6c
AK		 1186 } else {
1187 put_page(page_info->page);
1188 }
9e903e08 1189 skb_frag_size_add(&skb_shinfo(skb)->frags[j], curr_frag_len);
bdb28a97 1190 skb->truesize += rx_frag_size;
bd46cb6c 1191 remaining -= curr_frag_len;
2e588f84 1192 index_inc(&rxcp->rxq_idx, rxq->len);
6b7c5b94
SP		 1193 memset(page_info, 0, sizeof(*page_info));
1194 }
bd46cb6c 1195 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1196
5be93b9a 1197 skb_shinfo(skb)->nr_frags = j + 1;
2e588f84
SP		 1198 skb->len = rxcp->pkt_size;
1199 skb->data_len = rxcp->pkt_size;
5be93b9a 1200 skb->ip_summed = CHECKSUM_UNNECESSARY;
4b972914
AK		 1201 if (adapter->netdev->features & NETIF_F_RXHASH)
1202 skb->rxhash = rxcp->rss_hash;
5be93b9a 1203
343e43c0 1204 if (rxcp->vlanf)
4c5102f9
AK		 1205 __vlan_hwaccel_put_tag(skb, rxcp->vlan_tag);
1206
1207 napi_gro_frags(&eq_obj->napi);
2e588f84
SP		 1208}
1209
1210static void be_parse_rx_compl_v1(struct be_adapter *adapter,
1211 struct be_eth_rx_compl *compl,
1212 struct be_rx_compl_info *rxcp)
1213{
1214 rxcp->pkt_size =
1215 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, pktsize, compl);
1216 rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtp, compl);
1217 rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, err, compl);
1218 rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, tcpf, compl);
9ecb42fd 1219 rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, udpf, compl);
2e588f84
SP		 1220 rxcp->ip_csum =
1221 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ipcksm, compl);
1222 rxcp->l4_csum =
1223 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, l4_cksm, compl);
1224 rxcp->ipv6 =
1225 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ip_version, compl);
1226 rxcp->rxq_idx =
1227 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, fragndx, compl);
1228 rxcp->num_rcvd =
1229 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, numfrags, compl);
1230 rxcp->pkt_type =
1231 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, cast_enc, compl);
4b972914
AK		 1232 rxcp->rss_hash =
1233 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, rsshash, rxcp);
15d72184
SP		 1234 if (rxcp->vlanf) {
1235 rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtm,
3c709f8f
DM		 1236 compl);
1237 rxcp->vlan_tag = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vlan_tag,
1238 compl);
15d72184 1239 }
12004ae9 1240 rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, port, compl);
2e588f84
SP		 1241}
1242
1243static void be_parse_rx_compl_v0(struct be_adapter *adapter,
1244 struct be_eth_rx_compl *compl,
1245 struct be_rx_compl_info *rxcp)
1246{
1247 rxcp->pkt_size =
1248 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, pktsize, compl);
1249 rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtp, compl);
1250 rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, err, compl);
1251 rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, tcpf, compl);
9ecb42fd 1252 rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, udpf, compl);
2e588f84
SP		 1253 rxcp->ip_csum =
1254 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ipcksm, compl);
1255 rxcp->l4_csum =
1256 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, l4_cksm, compl);
1257 rxcp->ipv6 =
1258 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ip_version, compl);
1259 rxcp->rxq_idx =
1260 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, fragndx, compl);
1261 rxcp->num_rcvd =
1262 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, numfrags, compl);
1263 rxcp->pkt_type =
1264 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, cast_enc, compl);
4b972914
AK		 1265 rxcp->rss_hash =
1266 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, rsshash, rxcp);
15d72184
SP		 1267 if (rxcp->vlanf) {
1268 rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtm,
3c709f8f
DM		 1269 compl);
1270 rxcp->vlan_tag = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vlan_tag,
1271 compl);
15d72184 1272 }
12004ae9 1273 rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, port, compl);
2e588f84
SP		 1274}
1275
1276static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
1277{
1278 struct be_eth_rx_compl *compl = queue_tail_node(&rxo->cq);
1279 struct be_rx_compl_info *rxcp = &rxo->rxcp;
1280 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1281
2e588f84
SP		 1282 /* For checking the valid bit it is Ok to use either definition as the
1283 * valid bit is at the same position in both v0 and v1 Rx compl */
1284 if (compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] == 0)
1285 return NULL;
6b7c5b94 1286
2e588f84
SP		 1287 rmb();
1288 be_dws_le_to_cpu(compl, sizeof(*compl));
6b7c5b94 1289
2e588f84
SP		 1290 if (adapter->be3_native)
1291 be_parse_rx_compl_v1(adapter, compl, rxcp);
1292 else
1293 be_parse_rx_compl_v0(adapter, compl, rxcp);
6b7c5b94 1294
15d72184
SP		 1295 if (rxcp->vlanf) {
1296 /* vlanf could be wrongly set in some cards.
1297 * ignore if vtm is not set */
752961a1 1298 if ((adapter->function_mode & FLEX10_MODE) && !rxcp->vtm)
15d72184 1299 rxcp->vlanf = 0;
6b7c5b94 1300
15d72184 1301 if (!lancer_chip(adapter))
3c709f8f 1302 rxcp->vlan_tag = swab16(rxcp->vlan_tag);
6b7c5b94 1303
939cf306 1304 if (adapter->pvid == (rxcp->vlan_tag & VLAN_VID_MASK) &&
3c709f8f 1305 !adapter->vlan_tag[rxcp->vlan_tag])
15d72184
SP		 1306 rxcp->vlanf = 0;
1307 }
2e588f84
SP		 1308
1309 /* As the compl has been parsed, reset it; we wont touch it again */
1310 compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] = 0;
6b7c5b94 1311
3abcdeda 1312 queue_tail_inc(&rxo->cq);
6b7c5b94
SP		 1313 return rxcp;
1314}
1315
1829b086 1316static inline struct page *be_alloc_pages(u32 size, gfp_t gfp)
6b7c5b94 1317{
6b7c5b94 1318 u32 order = get_order(size);
1829b086 1319
6b7c5b94 1320 if (order > 0)
1829b086
ED		 1321 gfp |= __GFP_COMP;
1322 return alloc_pages(gfp, order);
6b7c5b94
SP		 1323}
1324
1325/*
1326 * Allocate a page, split it to fragments of size rx_frag_size and post as
1327 * receive buffers to BE
1328 */
1829b086 1329static void be_post_rx_frags(struct be_rx_obj *rxo, gfp_t gfp)
6b7c5b94 1330{
3abcdeda
SP		 1331 struct be_adapter *adapter = rxo->adapter;
1332 struct be_rx_page_info *page_info_tbl = rxo->page_info_tbl;
26d92f92 1333 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
3abcdeda 1334 struct be_queue_info *rxq = &rxo->q;
6b7c5b94
SP		 1335 struct page *pagep = NULL;
1336 struct be_eth_rx_d *rxd;
1337 u64 page_dmaaddr = 0, frag_dmaaddr;
1338 u32 posted, page_offset = 0;
1339
3abcdeda 1340 page_info = &rxo->page_info_tbl[rxq->head];
6b7c5b94
SP		 1341 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1342 if (!pagep) {
1829b086 1343 pagep = be_alloc_pages(adapter->big_page_size, gfp);
6b7c5b94 1344 if (unlikely(!pagep)) {
ac124ff9 1345 rx_stats(rxo)->rx_post_fail++;
6b7c5b94
SP		 1346 break;
1347 }
2b7bcebf
IV		 1348 page_dmaaddr = dma_map_page(&adapter->pdev->dev, pagep,
1349 0, adapter->big_page_size,
1350 DMA_FROM_DEVICE);
6b7c5b94
SP		 1351 page_info->page_offset = 0;
1352 } else {
1353 get_page(pagep);
1354 page_info->page_offset = page_offset + rx_frag_size;
1355 }
1356 page_offset = page_info->page_offset;
1357 page_info->page = pagep;
fac6da5b 1358 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1359 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1360
1361 rxd = queue_head_node(rxq);
1362 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1363 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1364
1365 /* Any space left in the current big page for another frag? */
1366 if ((page_offset + rx_frag_size + rx_frag_size) >
1367 adapter->big_page_size) {
1368 pagep = NULL;
1369 page_info->last_page_user = true;
1370 }
26d92f92
SP		 1371
1372 prev_page_info = page_info;
1373 queue_head_inc(rxq);
6b7c5b94
SP		 1374 page_info = &page_info_tbl[rxq->head];
1375 }
1376 if (pagep)
26d92f92 1377 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1378
1379 if (posted) {
6b7c5b94 1380 atomic_add(posted, &rxq->used);
8788fdc2 1381 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1382 } else if (atomic_read(&rxq->used) == 0) {
1383 /* Let be_worker replenish when memory is available */
3abcdeda 1384 rxo->rx_post_starved = true;
6b7c5b94 1385 }
6b7c5b94
SP		 1386}
1387
5fb379ee 1388static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1389{
6b7c5b94
SP		 1390 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1391
1392 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1393 return NULL;
1394
f3eb62d2 1395 rmb();
6b7c5b94
SP		 1396 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1397
1398 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1399
1400 queue_tail_inc(tx_cq);
1401 return txcp;
1402}
1403
3c8def97
SP		 1404static u16 be_tx_compl_process(struct be_adapter *adapter,
1405 struct be_tx_obj *txo, u16 last_index)
6b7c5b94 1406{
3c8def97 1407 struct be_queue_info *txq = &txo->q;
a73b796e 1408 struct be_eth_wrb *wrb;
3c8def97 1409 struct sk_buff **sent_skbs = txo->sent_skb_list;
6b7c5b94 1410 struct sk_buff *sent_skb;
ec43b1a6
SP		 1411 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1412 bool unmap_skb_hdr = true;
6b7c5b94 1413
ec43b1a6 1414 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1415 BUG_ON(!sent_skb);
ec43b1a6
SP		 1416 sent_skbs[txq->tail] = NULL;
1417
1418 /* skip header wrb */
a73b796e 1419 queue_tail_inc(txq);
6b7c5b94 1420
ec43b1a6 1421 do {
6b7c5b94 1422 cur_index = txq->tail;
a73b796e 1423 wrb = queue_tail_node(txq);
2b7bcebf
IV		 1424 unmap_tx_frag(&adapter->pdev->dev, wrb,
1425 (unmap_skb_hdr && skb_headlen(sent_skb)));
ec43b1a6
SP		 1426 unmap_skb_hdr = false;
1427
6b7c5b94
SP		 1428 num_wrbs++;
1429 queue_tail_inc(txq);
ec43b1a6 1430 } while (cur_index != last_index);
6b7c5b94 1431
6b7c5b94 1432 kfree_skb(sent_skb);
4d586b82 1433 return num_wrbs;
6b7c5b94
SP		 1434}
1435
859b1e4e
SP		 1436static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1437{
1438 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1439
1440 if (!eqe->evt)
1441 return NULL;
1442
f3eb62d2 1443 rmb();
859b1e4e
SP		 1444 eqe->evt = le32_to_cpu(eqe->evt);
1445 queue_tail_inc(&eq_obj->q);
1446 return eqe;
1447}
1448
1449static int event_handle(struct be_adapter *adapter,
3c8def97
SP		 1450 struct be_eq_obj *eq_obj,
1451 bool rearm)
859b1e4e
SP		 1452{
1453 struct be_eq_entry *eqe;
1454 u16 num = 0;
1455
1456 while ((eqe = event_get(eq_obj)) != NULL) {
1457 eqe->evt = 0;
1458 num++;
1459 }
1460
1461 /* Deal with any spurious interrupts that come
1462 * without events
1463 */
3c8def97
SP		 1464 if (!num)
1465 rearm = true;
1466
1467 be_eq_notify(adapter, eq_obj->q.id, rearm, true, num);
859b1e4e
SP		 1468 if (num)
1469 napi_schedule(&eq_obj->napi);
1470
1471 return num;
1472}
1473
1474/* Just read and notify events without processing them.
1475 * Used at the time of destroying event queues */
1476static void be_eq_clean(struct be_adapter *adapter,
1477 struct be_eq_obj *eq_obj)
1478{
1479 struct be_eq_entry *eqe;
1480 u16 num = 0;
1481
1482 while ((eqe = event_get(eq_obj)) != NULL) {
1483 eqe->evt = 0;
1484 num++;
1485 }
1486
1487 if (num)
1488 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1489}
1490
3abcdeda 1491static void be_rx_q_clean(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94
SP		 1492{
1493 struct be_rx_page_info *page_info;
3abcdeda
SP		 1494 struct be_queue_info *rxq = &rxo->q;
1495 struct be_queue_info *rx_cq = &rxo->cq;
2e588f84 1496 struct be_rx_compl_info *rxcp;
6b7c5b94
SP		 1497 u16 tail;
1498
1499 /* First cleanup pending rx completions */
3abcdeda
SP		 1500 while ((rxcp = be_rx_compl_get(rxo)) != NULL) {
1501 be_rx_compl_discard(adapter, rxo, rxcp);
64642811 1502 be_cq_notify(adapter, rx_cq->id, false, 1);
6b7c5b94
SP		 1503 }
1504
1505 /* Then free posted rx buffer that were not used */
1506 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1507 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
3abcdeda 1508 page_info = get_rx_page_info(adapter, rxo, tail);
6b7c5b94
SP		 1509 put_page(page_info->page);
1510 memset(page_info, 0, sizeof(*page_info));
1511 }
1512 BUG_ON(atomic_read(&rxq->used));
482c9e79 1513 rxq->tail = rxq->head = 0;
6b7c5b94
SP		 1514}
1515
3c8def97
SP		 1516static void be_tx_compl_clean(struct be_adapter *adapter,
1517 struct be_tx_obj *txo)
6b7c5b94 1518{
3c8def97
SP		 1519 struct be_queue_info *tx_cq = &txo->cq;
1520 struct be_queue_info *txq = &txo->q;
a8e9179a 1521 struct be_eth_tx_compl *txcp;
4d586b82 1522 u16 end_idx, cmpl = 0, timeo = 0, num_wrbs = 0;
3c8def97 1523 struct sk_buff **sent_skbs = txo->sent_skb_list;
b03388d6
SP		 1524 struct sk_buff *sent_skb;
1525 bool dummy_wrb;
a8e9179a
SP		 1526
1527 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1528 do {
1529 while ((txcp = be_tx_compl_get(tx_cq))) {
1530 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1531 wrb_index, txcp);
3c8def97 1532 num_wrbs += be_tx_compl_process(adapter, txo, end_idx);
a8e9179a
SP		 1533 cmpl++;
1534 }
1535 if (cmpl) {
1536 be_cq_notify(adapter, tx_cq->id, false, cmpl);
4d586b82 1537 atomic_sub(num_wrbs, &txq->used);
a8e9179a 1538 cmpl = 0;
4d586b82 1539 num_wrbs = 0;
a8e9179a
SP		 1540 }
1541
1542 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1543 break;
1544
1545 mdelay(1);
1546 } while (true);
1547
1548 if (atomic_read(&txq->used))
1549 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1550 atomic_read(&txq->used));
b03388d6
SP		 1551
1552 /* free posted tx for which compls will never arrive */
1553 while (atomic_read(&txq->used)) {
1554 sent_skb = sent_skbs[txq->tail];
1555 end_idx = txq->tail;
1556 index_adv(&end_idx,
fe6d2a38
SP		 1557 wrb_cnt_for_skb(adapter, sent_skb, &dummy_wrb) - 1,
1558 txq->len);
3c8def97 1559 num_wrbs = be_tx_compl_process(adapter, txo, end_idx);
4d586b82 1560 atomic_sub(num_wrbs, &txq->used);
b03388d6 1561 }
6b7c5b94
SP		 1562}
1563
5fb379ee
SP		 1564static void be_mcc_queues_destroy(struct be_adapter *adapter)
1565{
1566 struct be_queue_info *q;
5fb379ee 1567
8788fdc2 1568 q = &adapter->mcc_obj.q;
5fb379ee 1569 if (q->created)
8788fdc2 1570 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1571 be_queue_free(adapter, q);
1572
8788fdc2 1573 q = &adapter->mcc_obj.cq;
5fb379ee 1574 if (q->created)
8788fdc2 1575 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1576 be_queue_free(adapter, q);
1577}
1578
1579/* Must be called only after TX qs are created as MCC shares TX EQ */
1580static int be_mcc_queues_create(struct be_adapter *adapter)
1581{
1582 struct be_queue_info *q, *cq;
5fb379ee
SP		 1583
1584 /* Alloc MCC compl queue */
8788fdc2 1585 cq = &adapter->mcc_obj.cq;
5fb379ee 1586 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1587 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1588 goto err;
1589
1590 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1591 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1592 goto mcc_cq_free;
1593
1594 /* Alloc MCC queue */
8788fdc2 1595 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1596 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1597 goto mcc_cq_destroy;
1598
1599 /* Ask BE to create MCC queue */
8788fdc2 1600 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1601 goto mcc_q_free;
1602
1603 return 0;
1604
1605mcc_q_free:
1606 be_queue_free(adapter, q);
1607mcc_cq_destroy:
8788fdc2 1608 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1609mcc_cq_free:
1610 be_queue_free(adapter, cq);
1611err:
1612 return -1;
1613}
1614
6b7c5b94
SP		 1615static void be_tx_queues_destroy(struct be_adapter *adapter)
1616{
1617 struct be_queue_info *q;
3c8def97
SP		 1618 struct be_tx_obj *txo;
1619 u8 i;
6b7c5b94 1620
3c8def97
SP		 1621 for_all_tx_queues(adapter, txo, i) {
1622 q = &txo->q;
1623 if (q->created)
1624 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
1625 be_queue_free(adapter, q);
6b7c5b94 1626
3c8def97
SP		 1627 q = &txo->cq;
1628 if (q->created)
1629 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1630 be_queue_free(adapter, q);
1631 }
6b7c5b94 1632
859b1e4e
SP		 1633 /* Clear any residual events */
1634 be_eq_clean(adapter, &adapter->tx_eq);
1635
6b7c5b94
SP		 1636 q = &adapter->tx_eq.q;
1637 if (q->created)
8788fdc2 1638 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1639 be_queue_free(adapter, q);
1640}
1641
dafc0fe3
SP		 1642static int be_num_txqs_want(struct be_adapter *adapter)
1643{
1644 if ((num_vfs && adapter->sriov_enabled) ||
752961a1 1645 be_is_mc(adapter) ||
dafc0fe3
SP		 1646 lancer_chip(adapter) || !be_physfn(adapter) ||
1647 adapter->generation == BE_GEN2)
1648 return 1;
1649 else
1650 return MAX_TX_QS;
1651}
1652
3c8def97 1653/* One TX event queue is shared by all TX compl qs */
6b7c5b94
SP		 1654static int be_tx_queues_create(struct be_adapter *adapter)
1655{
1656 struct be_queue_info *eq, *q, *cq;
3c8def97
SP		 1657 struct be_tx_obj *txo;
1658 u8 i;
6b7c5b94 1659
dafc0fe3
SP		 1660 adapter->num_tx_qs = be_num_txqs_want(adapter);
1661 if (adapter->num_tx_qs != MAX_TX_QS)
1662 netif_set_real_num_tx_queues(adapter->netdev,
1663 adapter->num_tx_qs);
1664
6b7c5b94
SP		 1665 adapter->tx_eq.max_eqd = 0;
1666 adapter->tx_eq.min_eqd = 0;
1667 adapter->tx_eq.cur_eqd = 96;
1668 adapter->tx_eq.enable_aic = false;
3c8def97 1669
6b7c5b94 1670 eq = &adapter->tx_eq.q;
3c8def97
SP		 1671 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1672 sizeof(struct be_eq_entry)))
6b7c5b94
SP		 1673 return -1;
1674
8788fdc2 1675 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
3c8def97 1676 goto err;
ecd62107 1677 adapter->tx_eq.eq_idx = adapter->eq_next_idx++;
fe6d2a38 1678
3c8def97
SP		 1679 for_all_tx_queues(adapter, txo, i) {
1680 cq = &txo->cq;
1681 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
6b7c5b94 1682 sizeof(struct be_eth_tx_compl)))
3c8def97 1683 goto err;
6b7c5b94 1684
3c8def97
SP		 1685 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
1686 goto err;
6b7c5b94 1687
3c8def97
SP		 1688 q = &txo->q;
1689 if (be_queue_alloc(adapter, q, TX_Q_LEN,
1690 sizeof(struct be_eth_wrb)))
1691 goto err;
6b7c5b94 1692
3c8def97
SP		 1693 if (be_cmd_txq_create(adapter, q, cq))
1694 goto err;
1695 }
6b7c5b94
SP		 1696 return 0;
1697
3c8def97
SP		 1698err:
1699 be_tx_queues_destroy(adapter);
6b7c5b94
SP		 1700 return -1;
1701}
1702
1703static void be_rx_queues_destroy(struct be_adapter *adapter)
1704{
1705 struct be_queue_info *q;
3abcdeda
SP		 1706 struct be_rx_obj *rxo;
1707 int i;
1708
1709 for_all_rx_queues(adapter, rxo, i) {
482c9e79 1710 be_queue_free(adapter, &rxo->q);
3abcdeda
SP		 1711
1712 q = &rxo->cq;
1713 if (q->created)
1714 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1715 be_queue_free(adapter, q);
1716
3abcdeda 1717 q = &rxo->rx_eq.q;
482c9e79 1718 if (q->created)
3abcdeda 1719 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
3abcdeda 1720 be_queue_free(adapter, q);
6b7c5b94 1721 }
6b7c5b94
SP		 1722}
1723
ac6a0c4a
SP		 1724static u32 be_num_rxqs_want(struct be_adapter *adapter)
1725{
c814fd36 1726 if ((adapter->function_caps & BE_FUNCTION_CAPS_RSS) &&
752961a1
SP		 1727 !adapter->sriov_enabled && be_physfn(adapter) &&
1728 !be_is_mc(adapter)) {
ac6a0c4a
SP		 1729 return 1 + MAX_RSS_QS; /* one default non-RSS queue */
1730 } else {
1731 dev_warn(&adapter->pdev->dev,
1732 "No support for multiple RX queues\n");
1733 return 1;
1734 }
1735}
1736
6b7c5b94
SP		 1737static int be_rx_queues_create(struct be_adapter *adapter)
1738{
1739 struct be_queue_info *eq, *q, *cq;
3abcdeda
SP		 1740 struct be_rx_obj *rxo;
1741 int rc, i;
6b7c5b94 1742
ac6a0c4a
SP		 1743 adapter->num_rx_qs = min(be_num_rxqs_want(adapter),
1744 msix_enabled(adapter) ?
1745 adapter->num_msix_vec - 1 : 1);
1746 if (adapter->num_rx_qs != MAX_RX_QS)
1747 dev_warn(&adapter->pdev->dev,
1748 "Can create only %d RX queues", adapter->num_rx_qs);
1749
6b7c5b94 1750 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
3abcdeda
SP		 1751 for_all_rx_queues(adapter, rxo, i) {
1752 rxo->adapter = adapter;
1753 rxo->rx_eq.max_eqd = BE_MAX_EQD;
1754 rxo->rx_eq.enable_aic = true;
1755
1756 /* EQ */
1757 eq = &rxo->rx_eq.q;
1758 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1759 sizeof(struct be_eq_entry));
1760 if (rc)
1761 goto err;
1762
1763 rc = be_cmd_eq_create(adapter, eq, rxo->rx_eq.cur_eqd);
1764 if (rc)
1765 goto err;
1766
ecd62107 1767 rxo->rx_eq.eq_idx = adapter->eq_next_idx++;
fe6d2a38 1768
3abcdeda
SP		 1769 /* CQ */
1770 cq = &rxo->cq;
1771 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1772 sizeof(struct be_eth_rx_compl));
1773 if (rc)
1774 goto err;
1775
1776 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
1777 if (rc)
1778 goto err;
482c9e79
SP		 1779
1780 /* Rx Q - will be created in be_open() */
3abcdeda
SP		 1781 q = &rxo->q;
1782 rc = be_queue_alloc(adapter, q, RX_Q_LEN,
1783 sizeof(struct be_eth_rx_d));
1784 if (rc)
1785 goto err;
1786
3abcdeda 1787 }
6b7c5b94
SP		 1788
1789 return 0;
3abcdeda
SP		 1790err:
1791 be_rx_queues_destroy(adapter);
1792 return -1;
6b7c5b94 1793}
6b7c5b94 1794
fe6d2a38 1795static bool event_peek(struct be_eq_obj *eq_obj)
b628bde2 1796{
fe6d2a38
SP		 1797 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1798 if (!eqe->evt)
1799 return false;
1800 else
1801 return true;
b628bde2
SP		 1802}
1803
6b7c5b94
SP		 1804static irqreturn_t be_intx(int irq, void *dev)
1805{
1806 struct be_adapter *adapter = dev;
3abcdeda 1807 struct be_rx_obj *rxo;
fe6d2a38 1808 int isr, i, tx = 0 , rx = 0;
6b7c5b94 1809
fe6d2a38
SP		 1810 if (lancer_chip(adapter)) {
1811 if (event_peek(&adapter->tx_eq))
3c8def97 1812 tx = event_handle(adapter, &adapter->tx_eq, false);
fe6d2a38
SP		 1813 for_all_rx_queues(adapter, rxo, i) {
1814 if (event_peek(&rxo->rx_eq))
3c8def97 1815 rx |= event_handle(adapter, &rxo->rx_eq, true);
fe6d2a38 1816 }
6b7c5b94 1817
fe6d2a38
SP		 1818 if (!(tx || rx))
1819 return IRQ_NONE;
3abcdeda 1820
fe6d2a38
SP		 1821 } else {
1822 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
1823 (adapter->tx_eq.q.id / 8) * CEV_ISR_SIZE);
1824 if (!isr)
1825 return IRQ_NONE;
1826
ecd62107 1827 if ((1 << adapter->tx_eq.eq_idx & isr))
3c8def97 1828 event_handle(adapter, &adapter->tx_eq, false);
fe6d2a38
SP		 1829
1830 for_all_rx_queues(adapter, rxo, i) {
ecd62107 1831 if ((1 << rxo->rx_eq.eq_idx & isr))
3c8def97 1832 event_handle(adapter, &rxo->rx_eq, true);
fe6d2a38 1833 }
3abcdeda 1834 }
c001c213 1835
8788fdc2 1836 return IRQ_HANDLED;
6b7c5b94
SP		 1837}
1838
1839static irqreturn_t be_msix_rx(int irq, void *dev)
1840{
3abcdeda
SP		 1841 struct be_rx_obj *rxo = dev;
1842 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1843
3c8def97 1844 event_handle(adapter, &rxo->rx_eq, true);
6b7c5b94
SP		 1845
1846 return IRQ_HANDLED;
1847}
1848
5fb379ee 1849static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1850{
1851 struct be_adapter *adapter = dev;
1852
3c8def97 1853 event_handle(adapter, &adapter->tx_eq, false);
6b7c5b94
SP		 1854
1855 return IRQ_HANDLED;
1856}
1857
2e588f84 1858static inline bool do_gro(struct be_rx_compl_info *rxcp)
6b7c5b94 1859{
2e588f84 1860 return (rxcp->tcpf && !rxcp->err) ? true : false;
6b7c5b94
SP		 1861}
1862
49b05221 1863static int be_poll_rx(struct napi_struct *napi, int budget)
6b7c5b94
SP		 1864{
1865 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
3abcdeda
SP		 1866 struct be_rx_obj *rxo = container_of(rx_eq, struct be_rx_obj, rx_eq);
1867 struct be_adapter *adapter = rxo->adapter;
1868 struct be_queue_info *rx_cq = &rxo->cq;
2e588f84 1869 struct be_rx_compl_info *rxcp;
6b7c5b94
SP		 1870 u32 work_done;
1871
ac124ff9 1872 rx_stats(rxo)->rx_polls++;
6b7c5b94 1873 for (work_done = 0; work_done < budget; work_done++) {
3abcdeda 1874 rxcp = be_rx_compl_get(rxo);
6b7c5b94
SP		 1875 if (!rxcp)
1876 break;
1877
12004ae9
SP		 1878 /* Is it a flush compl that has no data */
1879 if (unlikely(rxcp->num_rcvd == 0))
1880 goto loop_continue;
1881
1882 /* Discard compl with partial DMA Lancer B0 */
1883 if (unlikely(!rxcp->pkt_size)) {
1884 be_rx_compl_discard(adapter, rxo, rxcp);
1885 goto loop_continue;
1886 }
1887
1888 /* On BE drop pkts that arrive due to imperfect filtering in
1889 * promiscuous mode on some skews
1890 */
1891 if (unlikely(rxcp->port != adapter->port_num &&
1892 !lancer_chip(adapter))) {
009dd872 1893 be_rx_compl_discard(adapter, rxo, rxcp);
12004ae9 1894 goto loop_continue;
64642811 1895 }
009dd872 1896
12004ae9
SP		 1897 if (do_gro(rxcp))
1898 be_rx_compl_process_gro(adapter, rxo, rxcp);
1899 else
1900 be_rx_compl_process(adapter, rxo, rxcp);
1901loop_continue:
2e588f84 1902 be_rx_stats_update(rxo, rxcp);
6b7c5b94
SP		 1903 }
1904
9372cacb
PR		 1905 be_cq_notify(adapter, rx_cq->id, false, work_done);
1906
6b7c5b94 1907 /* Refill the queue */
857c9905 1908 if (work_done && atomic_read(&rxo->q.used) < RX_FRAGS_REFILL_WM)
1829b086 1909 be_post_rx_frags(rxo, GFP_ATOMIC);
6b7c5b94
SP		 1910
1911 /* All consumed */
1912 if (work_done < budget) {
1913 napi_complete(napi);
9372cacb
PR		 1914 /* Arm CQ */
1915 be_cq_notify(adapter, rx_cq->id, true, 0);
6b7c5b94
SP		 1916 }
1917 return work_done;
1918}
1919
f31e50a8
SP		 1920/* As TX and MCC share the same EQ check for both TX and MCC completions.
1921 * For TX/MCC we don't honour budget; consume everything
1922 */
1923static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1924{
f31e50a8
SP		 1925 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1926 struct be_adapter *adapter =
1927 container_of(tx_eq, struct be_adapter, tx_eq);
3c8def97 1928 struct be_tx_obj *txo;
6b7c5b94 1929 struct be_eth_tx_compl *txcp;
3c8def97
SP		 1930 int tx_compl, mcc_compl, status = 0;
1931 u8 i;
1932 u16 num_wrbs;
1933
1934 for_all_tx_queues(adapter, txo, i) {
1935 tx_compl = 0;
1936 num_wrbs = 0;
1937 while ((txcp = be_tx_compl_get(&txo->cq))) {
1938 num_wrbs += be_tx_compl_process(adapter, txo,
1939 AMAP_GET_BITS(struct amap_eth_tx_compl,
1940 wrb_index, txcp));
1941 tx_compl++;
1942 }
1943 if (tx_compl) {
1944 be_cq_notify(adapter, txo->cq.id, true, tx_compl);
1945
1946 atomic_sub(num_wrbs, &txo->q.used);
6b7c5b94 1947
3c8def97
SP		 1948 /* As Tx wrbs have been freed up, wake up netdev queue
1949 * if it was stopped due to lack of tx wrbs. */
1950 if (__netif_subqueue_stopped(adapter->netdev, i) &&
1951 atomic_read(&txo->q.used) < txo->q.len / 2) {
1952 netif_wake_subqueue(adapter->netdev, i);
1953 }
1954
ab1594e9 1955 u64_stats_update_begin(&tx_stats(txo)->sync_compl);
ac124ff9 1956 tx_stats(txo)->tx_compl += tx_compl;
ab1594e9 1957 u64_stats_update_end(&tx_stats(txo)->sync_compl);
3c8def97 1958 }
6b7c5b94
SP		 1959 }
1960
f31e50a8
SP		 1961 mcc_compl = be_process_mcc(adapter, &status);
1962
f31e50a8
SP		 1963 if (mcc_compl) {
1964 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1965 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1966 }
1967
3c8def97 1968 napi_complete(napi);
6b7c5b94 1969
3c8def97 1970 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
ab1594e9 1971 adapter->drv_stats.tx_events++;
6b7c5b94
SP		 1972 return 1;
1973}
1974
d053de91 1975void be_detect_dump_ue(struct be_adapter *adapter)
7c185276 1976{
e1cfb67a
PR		 1977 u32 ue_lo = 0, ue_hi = 0, ue_lo_mask = 0, ue_hi_mask = 0;
1978 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
7c185276
AK		 1979 u32 i;
1980
72f02485
SP		 1981 if (adapter->eeh_err || adapter->ue_detected)
1982 return;
1983
e1cfb67a
PR		 1984 if (lancer_chip(adapter)) {
1985 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
1986 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
1987 sliport_err1 = ioread32(adapter->db +
1988 SLIPORT_ERROR1_OFFSET);
1989 sliport_err2 = ioread32(adapter->db +
1990 SLIPORT_ERROR2_OFFSET);
1991 }
1992 } else {
1993 pci_read_config_dword(adapter->pdev,
1994 PCICFG_UE_STATUS_LOW, &ue_lo);
1995 pci_read_config_dword(adapter->pdev,
1996 PCICFG_UE_STATUS_HIGH, &ue_hi);
1997 pci_read_config_dword(adapter->pdev,
1998 PCICFG_UE_STATUS_LOW_MASK, &ue_lo_mask);
1999 pci_read_config_dword(adapter->pdev,
2000 PCICFG_UE_STATUS_HI_MASK, &ue_hi_mask);
2001
2002 ue_lo = (ue_lo & (~ue_lo_mask));
2003 ue_hi = (ue_hi & (~ue_hi_mask));
2004 }
7c185276 2005
e1cfb67a
PR		 2006 if (ue_lo || ue_hi ||
2007 sliport_status & SLIPORT_STATUS_ERR_MASK) {
d053de91 2008 adapter->ue_detected = true;
7acc2087 2009 adapter->eeh_err = true;
d053de91
AK		 2010 dev_err(&adapter->pdev->dev, "UE Detected!!\n");
2011 }
2012
e1cfb67a
PR		 2013 if (ue_lo) {
2014 for (i = 0; ue_lo; ue_lo >>= 1, i++) {
2015 if (ue_lo & 1)
7c185276
AK		 2016 dev_err(&adapter->pdev->dev,
2017 "UE: %s bit set\n", ue_status_low_desc[i]);
2018 }
2019 }
e1cfb67a
PR		 2020 if (ue_hi) {
2021 for (i = 0; ue_hi; ue_hi >>= 1, i++) {
2022 if (ue_hi & 1)
7c185276
AK		 2023 dev_err(&adapter->pdev->dev,
2024 "UE: %s bit set\n", ue_status_hi_desc[i]);
2025 }
2026 }
2027
e1cfb67a
PR		 2028 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
2029 dev_err(&adapter->pdev->dev,
2030 "sliport status 0x%x\n", sliport_status);
2031 dev_err(&adapter->pdev->dev,
2032 "sliport error1 0x%x\n", sliport_err1);
2033 dev_err(&adapter->pdev->dev,
2034 "sliport error2 0x%x\n", sliport_err2);
2035 }
7c185276
AK		 2036}
2037
ea1dae11
SP		 2038static void be_worker(struct work_struct *work)
2039{
2040 struct be_adapter *adapter =
2041 container_of(work, struct be_adapter, work.work);
3abcdeda
SP		 2042 struct be_rx_obj *rxo;
2043 int i;
ea1dae11 2044
72f02485 2045 be_detect_dump_ue(adapter);
16da8250 2046
f203af70
SK		 2047 /* when interrupts are not yet enabled, just reap any pending
2048 * mcc completions */
2049 if (!netif_running(adapter->netdev)) {
2050 int mcc_compl, status = 0;
2051
2052 mcc_compl = be_process_mcc(adapter, &status);
2053
2054 if (mcc_compl) {
2055 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
2056 be_cq_notify(adapter, mcc_obj->cq.id, false, mcc_compl);
2057 }
9b037f38 2058
f203af70
SK		 2059 goto reschedule;
2060 }
2061
005d5696
SX		 2062 if (!adapter->stats_cmd_sent) {
2063 if (lancer_chip(adapter))
2064 lancer_cmd_get_pport_stats(adapter,
2065 &adapter->stats_cmd);
2066 else
2067 be_cmd_get_stats(adapter, &adapter->stats_cmd);
2068 }
3c8def97 2069
3abcdeda 2070 for_all_rx_queues(adapter, rxo, i) {
3abcdeda
SP		 2071 be_rx_eqd_update(adapter, rxo);
2072
2073 if (rxo->rx_post_starved) {
2074 rxo->rx_post_starved = false;
1829b086 2075 be_post_rx_frags(rxo, GFP_KERNEL);
3abcdeda 2076 }
ea1dae11
SP		 2077 }
2078
f203af70 2079reschedule:
e74fbd03 2080 adapter->work_counter++;
ea1dae11
SP		 2081 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
2082}
2083
8d56ff11
SP		 2084static void be_msix_disable(struct be_adapter *adapter)
2085{
ac6a0c4a 2086 if (msix_enabled(adapter)) {
8d56ff11 2087 pci_disable_msix(adapter->pdev);
ac6a0c4a 2088 adapter->num_msix_vec = 0;
3abcdeda
SP		 2089 }
2090}
2091
6b7c5b94
SP		 2092static void be_msix_enable(struct be_adapter *adapter)
2093{
3abcdeda 2094#define BE_MIN_MSIX_VECTORS (1 + 1) /* Rx + Tx */
ac6a0c4a 2095 int i, status, num_vec;
6b7c5b94 2096
ac6a0c4a 2097 num_vec = be_num_rxqs_want(adapter) + 1;
3abcdeda 2098
ac6a0c4a 2099 for (i = 0; i < num_vec; i++)
6b7c5b94
SP		 2100 adapter->msix_entries[i].entry = i;
2101
ac6a0c4a 2102 status = pci_enable_msix(adapter->pdev, adapter->msix_entries, num_vec);
3abcdeda
SP		 2103 if (status == 0) {
2104 goto done;
2105 } else if (status >= BE_MIN_MSIX_VECTORS) {
ac6a0c4a 2106 num_vec = status;
3abcdeda 2107 if (pci_enable_msix(adapter->pdev, adapter->msix_entries,
ac6a0c4a 2108 num_vec) == 0)
3abcdeda 2109 goto done;
3abcdeda
SP		 2110 }
2111 return;
2112done:
ac6a0c4a
SP		 2113 adapter->num_msix_vec = num_vec;
2114 return;
6b7c5b94
SP		 2115}
2116
f9449ab7 2117static int be_sriov_enable(struct be_adapter *adapter)
ba343c77 2118{
344dbf10 2119 be_check_sriov_fn_type(adapter);
6dedec81 2120#ifdef CONFIG_PCI_IOV
ba343c77 2121 if (be_physfn(adapter) && num_vfs) {
81be8f0a
AK		 2122 int status, pos;
2123 u16 nvfs;
2124
2125 pos = pci_find_ext_capability(adapter->pdev,
2126 PCI_EXT_CAP_ID_SRIOV);
2127 pci_read_config_word(adapter->pdev,
2128 pos + PCI_SRIOV_TOTAL_VF, &nvfs);
2129
2130 if (num_vfs > nvfs) {
2131 dev_info(&adapter->pdev->dev,
2132 "Device supports %d VFs and not %d\n",
2133 nvfs, num_vfs);
2134 num_vfs = nvfs;
2135 }
6dedec81 2136
ba343c77
SB		 2137 status = pci_enable_sriov(adapter->pdev, num_vfs);
2138 adapter->sriov_enabled = status ? false : true;
f9449ab7
SP		 2139
2140 if (adapter->sriov_enabled) {
2141 adapter->vf_cfg = kcalloc(num_vfs,
2142 sizeof(struct be_vf_cfg),
2143 GFP_KERNEL);
2144 if (!adapter->vf_cfg)
2145 return -ENOMEM;
2146 }
ba343c77
SB		 2147 }
2148#endif
f9449ab7 2149 return 0;
ba343c77
SB		 2150}
2151
2152static void be_sriov_disable(struct be_adapter *adapter)
2153{
2154#ifdef CONFIG_PCI_IOV
2155 if (adapter->sriov_enabled) {
2156 pci_disable_sriov(adapter->pdev);
f9449ab7 2157 kfree(adapter->vf_cfg);
ba343c77
SB		 2158 adapter->sriov_enabled = false;
2159 }
2160#endif
2161}
2162
fe6d2a38
SP		 2163static inline int be_msix_vec_get(struct be_adapter *adapter,
2164 struct be_eq_obj *eq_obj)
6b7c5b94 2165{
ecd62107 2166 return adapter->msix_entries[eq_obj->eq_idx].vector;
6b7c5b94
SP		 2167}
2168
b628bde2
SP		 2169static int be_request_irq(struct be_adapter *adapter,
2170 struct be_eq_obj *eq_obj,
3abcdeda 2171 void *handler, char *desc, void *context)
6b7c5b94
SP		 2172{
2173 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 2174 int vec;
2175
2176 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
fe6d2a38 2177 vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 2178 return request_irq(vec, handler, 0, eq_obj->desc, context);
b628bde2
SP		 2179}
2180
3abcdeda
SP		 2181static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj,
2182 void *context)
b628bde2 2183{
fe6d2a38 2184 int vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 2185 free_irq(vec, context);
b628bde2 2186}
6b7c5b94 2187
b628bde2
SP		 2188static int be_msix_register(struct be_adapter *adapter)
2189{
3abcdeda
SP		 2190 struct be_rx_obj *rxo;
2191 int status, i;
2192 char qname[10];
b628bde2 2193
3abcdeda
SP		 2194 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx",
2195 adapter);
6b7c5b94
SP		 2196 if (status)
2197 goto err;
2198
3abcdeda
SP		 2199 for_all_rx_queues(adapter, rxo, i) {
2200 sprintf(qname, "rxq%d", i);
2201 status = be_request_irq(adapter, &rxo->rx_eq, be_msix_rx,
2202 qname, rxo);
2203 if (status)
2204 goto err_msix;
2205 }
b628bde2 2206
6b7c5b94 2207 return 0;
b628bde2 2208
3abcdeda
SP		 2209err_msix:
2210 be_free_irq(adapter, &adapter->tx_eq, adapter);
2211
2212 for (i--, rxo = &adapter->rx_obj[i]; i >= 0; i--, rxo--)
2213 be_free_irq(adapter, &rxo->rx_eq, rxo);
2214
6b7c5b94
SP		 2215err:
2216 dev_warn(&adapter->pdev->dev,
2217 "MSIX Request IRQ failed - err %d\n", status);
ac6a0c4a 2218 be_msix_disable(adapter);
6b7c5b94
SP		 2219 return status;
2220}
2221
2222static int be_irq_register(struct be_adapter *adapter)
2223{
2224 struct net_device *netdev = adapter->netdev;
2225 int status;
2226
ac6a0c4a 2227 if (msix_enabled(adapter)) {
6b7c5b94
SP		 2228 status = be_msix_register(adapter);
2229 if (status == 0)
2230 goto done;
ba343c77
SB		 2231 /* INTx is not supported for VF */
2232 if (!be_physfn(adapter))
2233 return status;
6b7c5b94
SP		 2234 }
2235
2236 /* INTx */
2237 netdev->irq = adapter->pdev->irq;
2238 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
2239 adapter);
2240 if (status) {
2241 dev_err(&adapter->pdev->dev,
2242 "INTx request IRQ failed - err %d\n", status);
2243 return status;
2244 }
2245done:
2246 adapter->isr_registered = true;
2247 return 0;
2248}
2249
2250static void be_irq_unregister(struct be_adapter *adapter)
2251{
2252 struct net_device *netdev = adapter->netdev;
3abcdeda
SP		 2253 struct be_rx_obj *rxo;
2254 int i;
6b7c5b94
SP		 2255
2256 if (!adapter->isr_registered)
2257 return;
2258
2259 /* INTx */
ac6a0c4a 2260 if (!msix_enabled(adapter)) {
6b7c5b94
SP		 2261 free_irq(netdev->irq, adapter);
2262 goto done;
2263 }
2264
2265 /* MSIx */
3abcdeda
SP		 2266 be_free_irq(adapter, &adapter->tx_eq, adapter);
2267
2268 for_all_rx_queues(adapter, rxo, i)
2269 be_free_irq(adapter, &rxo->rx_eq, rxo);
2270
6b7c5b94
SP		 2271done:
2272 adapter->isr_registered = false;
6b7c5b94
SP		 2273}
2274
482c9e79
SP		 2275static void be_rx_queues_clear(struct be_adapter *adapter)
2276{
2277 struct be_queue_info *q;
2278 struct be_rx_obj *rxo;
2279 int i;
2280
2281 for_all_rx_queues(adapter, rxo, i) {
2282 q = &rxo->q;
2283 if (q->created) {
2284 be_cmd_rxq_destroy(adapter, q);
2285 /* After the rxq is invalidated, wait for a grace time
2286 * of 1ms for all dma to end and the flush compl to
2287 * arrive
2288 */
2289 mdelay(1);
2290 be_rx_q_clean(adapter, rxo);
2291 }
2292
2293 /* Clear any residual events */
2294 q = &rxo->rx_eq.q;
2295 if (q->created)
2296 be_eq_clean(adapter, &rxo->rx_eq);
2297 }
2298}
2299
889cd4b2
SP		 2300static int be_close(struct net_device *netdev)
2301{
2302 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda 2303 struct be_rx_obj *rxo;
3c8def97 2304 struct be_tx_obj *txo;
889cd4b2 2305 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2306 int vec, i;
889cd4b2 2307
889cd4b2
SP		 2308 be_async_mcc_disable(adapter);
2309
fe6d2a38
SP		 2310 if (!lancer_chip(adapter))
2311 be_intr_set(adapter, false);
889cd4b2 2312
63fcb27f
PR		 2313 for_all_rx_queues(adapter, rxo, i)
2314 napi_disable(&rxo->rx_eq.napi);
2315
2316 napi_disable(&tx_eq->napi);
2317
2318 if (lancer_chip(adapter)) {
63fcb27f
PR		 2319 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
2320 for_all_rx_queues(adapter, rxo, i)
2321 be_cq_notify(adapter, rxo->cq.id, false, 0);
3c8def97
SP		 2322 for_all_tx_queues(adapter, txo, i)
2323 be_cq_notify(adapter, txo->cq.id, false, 0);
63fcb27f
PR		 2324 }
2325
ac6a0c4a 2326 if (msix_enabled(adapter)) {
fe6d2a38 2327 vec = be_msix_vec_get(adapter, tx_eq);
889cd4b2 2328 synchronize_irq(vec);
3abcdeda
SP		 2329
2330 for_all_rx_queues(adapter, rxo, i) {
fe6d2a38 2331 vec = be_msix_vec_get(adapter, &rxo->rx_eq);
3abcdeda
SP		 2332 synchronize_irq(vec);
2333 }
889cd4b2
SP		 2334 } else {
2335 synchronize_irq(netdev->irq);
2336 }
2337 be_irq_unregister(adapter);
2338
889cd4b2
SP		 2339 /* Wait for all pending tx completions to arrive so that
2340 * all tx skbs are freed.
2341 */
3c8def97
SP		 2342 for_all_tx_queues(adapter, txo, i)
2343 be_tx_compl_clean(adapter, txo);
889cd4b2 2344
482c9e79
SP		 2345 be_rx_queues_clear(adapter);
2346 return 0;
2347}
2348
2349static int be_rx_queues_setup(struct be_adapter *adapter)
2350{
2351 struct be_rx_obj *rxo;
2352 int rc, i;
2353 u8 rsstable[MAX_RSS_QS];
2354
2355 for_all_rx_queues(adapter, rxo, i) {
2356 rc = be_cmd_rxq_create(adapter, &rxo->q, rxo->cq.id,
2357 rx_frag_size, BE_MAX_JUMBO_FRAME_SIZE,
2358 adapter->if_handle,
2359 (i > 0) ? 1 : 0/* rss enable */, &rxo->rss_id);
2360 if (rc)
2361 return rc;
2362 }
2363
2364 if (be_multi_rxq(adapter)) {
2365 for_all_rss_queues(adapter, rxo, i)
2366 rsstable[i] = rxo->rss_id;
2367
2368 rc = be_cmd_rss_config(adapter, rsstable,
2369 adapter->num_rx_qs - 1);
2370 if (rc)
2371 return rc;
2372 }
2373
2374 /* First time posting */
2375 for_all_rx_queues(adapter, rxo, i) {
2376 be_post_rx_frags(rxo, GFP_KERNEL);
2377 napi_enable(&rxo->rx_eq.napi);
2378 }
889cd4b2
SP		 2379 return 0;
2380}
2381
6b7c5b94
SP		 2382static int be_open(struct net_device *netdev)
2383{
2384 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 2385 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2386 struct be_rx_obj *rxo;
3abcdeda 2387 int status, i;
5fb379ee 2388
482c9e79
SP		 2389 status = be_rx_queues_setup(adapter);
2390 if (status)
2391 goto err;
2392
5fb379ee
SP		 2393 napi_enable(&tx_eq->napi);
2394
2395 be_irq_register(adapter);
2396
fe6d2a38
SP		 2397 if (!lancer_chip(adapter))
2398 be_intr_set(adapter, true);
5fb379ee
SP		 2399
2400 /* The evt queues are created in unarmed state; arm them */
3abcdeda
SP		 2401 for_all_rx_queues(adapter, rxo, i) {
2402 be_eq_notify(adapter, rxo->rx_eq.q.id, true, false, 0);
2403 be_cq_notify(adapter, rxo->cq.id, true, 0);
2404 }
8788fdc2 2405 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee 2406
7a1e9b20
SP		 2407 /* Now that interrupts are on we can process async mcc */
2408 be_async_mcc_enable(adapter);
2409
889cd4b2
SP		 2410 return 0;
2411err:
2412 be_close(adapter->netdev);
2413 return -EIO;
5fb379ee
SP		 2414}
2415
71d8d1b5
AK		 2416static int be_setup_wol(struct be_adapter *adapter, bool enable)
2417{
2418 struct be_dma_mem cmd;
2419 int status = 0;
2420 u8 mac[ETH_ALEN];
2421
2422 memset(mac, 0, ETH_ALEN);
2423
2424 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
2b7bcebf
IV		 2425 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2426 GFP_KERNEL);
71d8d1b5
AK		 2427 if (cmd.va == NULL)
2428 return -1;
2429 memset(cmd.va, 0, cmd.size);
2430
2431 if (enable) {
2432 status = pci_write_config_dword(adapter->pdev,
2433 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
2434 if (status) {
2435 dev_err(&adapter->pdev->dev,
2381a55c 2436 "Could not enable Wake-on-lan\n");
2b7bcebf
IV		 2437 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
2438 cmd.dma);
71d8d1b5
AK		 2439 return status;
2440 }
2441 status = be_cmd_enable_magic_wol(adapter,
2442 adapter->netdev->dev_addr, &cmd);
2443 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
2444 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
2445 } else {
2446 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
2447 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
2448 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
2449 }
2450
2b7bcebf 2451 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
71d8d1b5
AK		 2452 return status;
2453}
2454
6d87f5c3
AK		 2455/*
2456 * Generate a seed MAC address from the PF MAC Address using jhash.
2457 * MAC Address for VFs are assigned incrementally starting from the seed.
2458 * These addresses are programmed in the ASIC by the PF and the VF driver
2459 * queries for the MAC address during its probe.
2460 */
2461static inline int be_vf_eth_addr_config(struct be_adapter *adapter)
2462{
f9449ab7 2463 u32 vf;
3abcdeda 2464 int status = 0;
6d87f5c3
AK		 2465 u8 mac[ETH_ALEN];
2466
2467 be_vf_eth_addr_generate(adapter, mac);
2468
2469 for (vf = 0; vf < num_vfs; vf++) {
2470 status = be_cmd_pmac_add(adapter, mac,
2471 adapter->vf_cfg[vf].vf_if_handle,
f8617e08
AK		 2472 &adapter->vf_cfg[vf].vf_pmac_id,
2473 vf + 1);
6d87f5c3
AK		 2474 if (status)
2475 dev_err(&adapter->pdev->dev,
2476 "Mac address add failed for VF %d\n", vf);
2477 else
2478 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
2479
2480 mac[5] += 1;
2481 }
2482 return status;
2483}
2484
f9449ab7 2485static void be_vf_clear(struct be_adapter *adapter)
6d87f5c3
AK		 2486{
2487 u32 vf;
2488
30128031
SP		 2489 for (vf = 0; vf < num_vfs; vf++)
2490 be_cmd_pmac_del(adapter, adapter->vf_cfg[vf].vf_if_handle,
2491 adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
f9449ab7
SP		 2492
2493 for (vf = 0; vf < num_vfs; vf++)
30128031
SP		 2494 be_cmd_if_destroy(adapter, adapter->vf_cfg[vf].vf_if_handle,
2495 vf + 1);
6d87f5c3
AK		 2496}
2497
a54769f5
SP		 2498static int be_clear(struct be_adapter *adapter)
2499{
a54769f5 2500 if (be_physfn(adapter) && adapter->sriov_enabled)
f9449ab7
SP		 2501 be_vf_clear(adapter);
2502
2503 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
a54769f5
SP		 2504
2505 be_mcc_queues_destroy(adapter);
2506 be_rx_queues_destroy(adapter);
2507 be_tx_queues_destroy(adapter);
a54769f5
SP		 2508
2509 /* tell fw we're done with firing cmds */
2510 be_cmd_fw_clean(adapter);
2511 return 0;
2512}
2513
30128031
SP		 2514static void be_vf_setup_init(struct be_adapter *adapter)
2515{
2516 int vf;
2517
2518 for (vf = 0; vf < num_vfs; vf++) {
2519 adapter->vf_cfg[vf].vf_if_handle = -1;
2520 adapter->vf_cfg[vf].vf_pmac_id = -1;
2521 }
2522}
2523
f9449ab7
SP		 2524static int be_vf_setup(struct be_adapter *adapter)
2525{
2526 u32 cap_flags, en_flags, vf;
2527 u16 lnk_speed;
2528 int status;
2529
30128031
SP		 2530 be_vf_setup_init(adapter);
2531
f9449ab7
SP		 2532 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
2533 for (vf = 0; vf < num_vfs; vf++) {
2534 status = be_cmd_if_create(adapter, cap_flags, en_flags, NULL,
2535 &adapter->vf_cfg[vf].vf_if_handle,
2536 NULL, vf+1);
2537 if (status)
2538 goto err;
f9449ab7
SP		 2539 }
2540
2541 if (!lancer_chip(adapter)) {
2542 status = be_vf_eth_addr_config(adapter);
2543 if (status)
2544 goto err;
2545 }
2546
2547 for (vf = 0; vf < num_vfs; vf++) {
2548 status = be_cmd_link_status_query(adapter, NULL, &lnk_speed,
2549 vf + 1);
2550 if (status)
2551 goto err;
2552 adapter->vf_cfg[vf].vf_tx_rate = lnk_speed * 10;
2553 }
2554 return 0;
2555err:
2556 return status;
2557}
2558
30128031
SP		 2559static void be_setup_init(struct be_adapter *adapter)
2560{
2561 adapter->vlan_prio_bmap = 0xff;
2562 adapter->link_speed = -1;
2563 adapter->if_handle = -1;
2564 adapter->be3_native = false;
2565 adapter->promiscuous = false;
2566 adapter->eq_next_idx = 0;
2567}
2568
5fb379ee
SP		 2569static int be_setup(struct be_adapter *adapter)
2570{
5fb379ee 2571 struct net_device *netdev = adapter->netdev;
f9449ab7 2572 u32 cap_flags, en_flags;
a54769f5 2573 u32 tx_fc, rx_fc;
6b7c5b94 2574 int status;
ba343c77
SB		 2575 u8 mac[ETH_ALEN];
2576
30128031 2577 be_setup_init(adapter);
6b7c5b94 2578
f9449ab7 2579 be_cmd_req_native_mode(adapter);
73d540f2 2580
f9449ab7 2581 status = be_tx_queues_create(adapter);
6b7c5b94 2582 if (status != 0)
a54769f5 2583 goto err;
6b7c5b94 2584
f9449ab7 2585 status = be_rx_queues_create(adapter);
6b7c5b94 2586 if (status != 0)
a54769f5 2587 goto err;
6b7c5b94 2588
f9449ab7 2589 status = be_mcc_queues_create(adapter);
6b7c5b94 2590 if (status != 0)
a54769f5 2591 goto err;
6b7c5b94 2592
f9449ab7
SP		 2593 memset(mac, 0, ETH_ALEN);
2594 status = be_cmd_mac_addr_query(adapter, mac, MAC_ADDRESS_TYPE_NETWORK,
2595 true /*permanent */, 0);
2596 if (status)
2597 return status;
2598 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2599 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2903dd65 2600
f9449ab7
SP		 2601 en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
2602 BE_IF_FLAGS_MULTICAST | BE_IF_FLAGS_PASS_L3L4_ERRORS;
2603 cap_flags = en_flags | BE_IF_FLAGS_MCAST_PROMISCUOUS |
2604 BE_IF_FLAGS_PROMISCUOUS;
2605 if (adapter->function_caps & BE_FUNCTION_CAPS_RSS) {
2606 cap_flags |= BE_IF_FLAGS_RSS;
2607 en_flags |= BE_IF_FLAGS_RSS;
2608 }
2609 status = be_cmd_if_create(adapter, cap_flags, en_flags,
2610 netdev->dev_addr, &adapter->if_handle,
2611 &adapter->pmac_id, 0);
5fb379ee 2612 if (status != 0)
a54769f5 2613 goto err;
6b7c5b94 2614
f9449ab7
SP		 2615 /* For BEx, the VF's permanent mac queried from card is incorrect.
2616 * Query the mac configued by the PF using if_handle
2617 */
2618 if (!be_physfn(adapter) && !lancer_chip(adapter)) {
2619 status = be_cmd_mac_addr_query(adapter, mac,
2620 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
2621 if (!status) {
2622 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2623 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2624 }
2625 }
0dffc83e 2626
04b71175 2627 be_cmd_get_fw_ver(adapter, adapter->fw_ver, NULL);
5a56eb10 2628
a54769f5
SP		 2629 status = be_vid_config(adapter, false, 0);
2630 if (status)
2631 goto err;
7ab8b0b4 2632
a54769f5 2633 be_set_rx_mode(adapter->netdev);
5fb379ee 2634
a54769f5
SP		 2635 status = be_cmd_get_flow_control(adapter, &tx_fc, &rx_fc);
2636 if (status)
2637 goto err;
2638 if (rx_fc != adapter->rx_fc || tx_fc != adapter->tx_fc) {
2639 status = be_cmd_set_flow_control(adapter, adapter->tx_fc,
2640 adapter->rx_fc);
2641 if (status)
2642 goto err;
2643 }
2dc1deb6 2644
a54769f5 2645 pcie_set_readrq(adapter->pdev, 4096);
5fb379ee 2646
f9449ab7
SP		 2647 if (be_physfn(adapter) && adapter->sriov_enabled) {
2648 status = be_vf_setup(adapter);
2649 if (status)
2650 goto err;
2651 }
2652
2653 return 0;
a54769f5
SP		 2654err:
2655 be_clear(adapter);
2656 return status;
2657}
6b7c5b94 2658
84517482 2659#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
fa9a6fed 2660static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 2661 const u8 *p, u32 img_start, int image_size,
2662 int hdr_size)
fa9a6fed
SB		 2663{
2664 u32 crc_offset;
2665 u8 flashed_crc[4];
2666 int status;
3f0d4560
AK		 2667
2668 crc_offset = hdr_size + img_start + image_size - 4;
2669
fa9a6fed 2670 p += crc_offset;
3f0d4560
AK		 2671
2672 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 2673 (image_size - 4));
fa9a6fed
SB		 2674 if (status) {
2675 dev_err(&adapter->pdev->dev,
2676 "could not get crc from flash, not flashing redboot\n");
2677 return false;
2678 }
2679
2680 /*update redboot only if crc does not match*/
2681 if (!memcmp(flashed_crc, p, 4))
2682 return false;
2683 else
2684 return true;
fa9a6fed
SB		 2685}
2686
306f1348
SP		 2687static bool phy_flashing_required(struct be_adapter *adapter)
2688{
2689 int status = 0;
2690 struct be_phy_info phy_info;
2691
2692 status = be_cmd_get_phy_info(adapter, &phy_info);
2693 if (status)
2694 return false;
2695 if ((phy_info.phy_type == TN_8022) &&
2696 (phy_info.interface_type == PHY_TYPE_BASET_10GB)) {
2697 return true;
2698 }
2699 return false;
2700}
2701
3f0d4560 2702static int be_flash_data(struct be_adapter *adapter,
84517482 2703 const struct firmware *fw,
3f0d4560
AK		 2704 struct be_dma_mem *flash_cmd, int num_of_images)
2705
84517482 2706{
3f0d4560
AK		 2707 int status = 0, i, filehdr_size = 0;
2708 u32 total_bytes = 0, flash_op;
84517482
AK		 2709 int num_bytes;
2710 const u8 *p = fw->data;
2711 struct be_cmd_write_flashrom *req = flash_cmd->va;
215faf9c 2712 const struct flash_comp *pflashcomp;
9fe96934 2713 int num_comp;
3f0d4560 2714
306f1348 2715 static const struct flash_comp gen3_flash_types[10] = {
3f0d4560
AK		 2716 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2717 FLASH_IMAGE_MAX_SIZE_g3},
2718 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2719 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2720 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2721 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2722 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2723 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2724 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2725 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2726 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2727 FLASH_IMAGE_MAX_SIZE_g3},
2728 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2729 FLASH_IMAGE_MAX_SIZE_g3},
2730 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2731 FLASH_IMAGE_MAX_SIZE_g3},
2732 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
306f1348
SP		 2733 FLASH_NCSI_IMAGE_MAX_SIZE_g3},
2734 { FLASH_PHY_FW_START_g3, IMG_TYPE_PHY_FW,
2735 FLASH_PHY_FW_IMAGE_MAX_SIZE_g3}
3f0d4560 2736 };
215faf9c 2737 static const struct flash_comp gen2_flash_types[8] = {
3f0d4560
AK		 2738 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2739 FLASH_IMAGE_MAX_SIZE_g2},
2740 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2741 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2742 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2743 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2744 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2745 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2746 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2747 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2748 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2749 FLASH_IMAGE_MAX_SIZE_g2},
2750 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2751 FLASH_IMAGE_MAX_SIZE_g2},
2752 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2753 FLASH_IMAGE_MAX_SIZE_g2}
2754 };
2755
2756 if (adapter->generation == BE_GEN3) {
2757 pflashcomp = gen3_flash_types;
2758 filehdr_size = sizeof(struct flash_file_hdr_g3);
215faf9c 2759 num_comp = ARRAY_SIZE(gen3_flash_types);
3f0d4560
AK		 2760 } else {
2761 pflashcomp = gen2_flash_types;
2762 filehdr_size = sizeof(struct flash_file_hdr_g2);
215faf9c 2763 num_comp = ARRAY_SIZE(gen2_flash_types);
84517482 2764 }
9fe96934
SB		 2765 for (i = 0; i < num_comp; i++) {
2766 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2767 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2768 continue;
306f1348
SP		 2769 if (pflashcomp[i].optype == IMG_TYPE_PHY_FW) {
2770 if (!phy_flashing_required(adapter))
2771 continue;
2772 }
3f0d4560
AK		 2773 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2774 (!be_flash_redboot(adapter, fw->data,
fae21a4d
AK		 2775 pflashcomp[i].offset, pflashcomp[i].size, filehdr_size +
2776 (num_of_images * sizeof(struct image_hdr)))))
3f0d4560
AK		 2777 continue;
2778 p = fw->data;
2779 p += filehdr_size + pflashcomp[i].offset
2780 + (num_of_images * sizeof(struct image_hdr));
306f1348
SP		 2781 if (p + pflashcomp[i].size > fw->data + fw->size)
2782 return -1;
2783 total_bytes = pflashcomp[i].size;
3f0d4560
AK		 2784 while (total_bytes) {
2785 if (total_bytes > 32*1024)
2786 num_bytes = 32*1024;
2787 else
2788 num_bytes = total_bytes;
2789 total_bytes -= num_bytes;
306f1348
SP		 2790 if (!total_bytes) {
2791 if (pflashcomp[i].optype == IMG_TYPE_PHY_FW)
2792 flash_op = FLASHROM_OPER_PHY_FLASH;
2793 else
2794 flash_op = FLASHROM_OPER_FLASH;
2795 } else {
2796 if (pflashcomp[i].optype == IMG_TYPE_PHY_FW)
2797 flash_op = FLASHROM_OPER_PHY_SAVE;
2798 else
2799 flash_op = FLASHROM_OPER_SAVE;
2800 }
3f0d4560
AK		 2801 memcpy(req->params.data_buf, p, num_bytes);
2802 p += num_bytes;
2803 status = be_cmd_write_flashrom(adapter, flash_cmd,
2804 pflashcomp[i].optype, flash_op, num_bytes);
2805 if (status) {
306f1348
SP		 2806 if ((status == ILLEGAL_IOCTL_REQ) &&
2807 (pflashcomp[i].optype ==
2808 IMG_TYPE_PHY_FW))
2809 break;
3f0d4560
AK		 2810 dev_err(&adapter->pdev->dev,
2811 "cmd to write to flash rom failed.\n");
2812 return -1;
2813 }
84517482 2814 }
84517482 2815 }
84517482
AK		 2816 return 0;
2817}
2818
3f0d4560
AK		 2819static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2820{
2821 if (fhdr == NULL)
2822 return 0;
2823 if (fhdr->build[0] == '3')
2824 return BE_GEN3;
2825 else if (fhdr->build[0] == '2')
2826 return BE_GEN2;
2827 else
2828 return 0;
2829}
2830
485bf569
SN		 2831static int lancer_fw_download(struct be_adapter *adapter,
2832 const struct firmware *fw)
84517482 2833{
485bf569
SN		 2834#define LANCER_FW_DOWNLOAD_CHUNK (32 * 1024)
2835#define LANCER_FW_DOWNLOAD_LOCATION "/prg"
84517482 2836 struct be_dma_mem flash_cmd;
485bf569
SN		 2837 const u8 *data_ptr = NULL;
2838 u8 *dest_image_ptr = NULL;
2839 size_t image_size = 0;
2840 u32 chunk_size = 0;
2841 u32 data_written = 0;
2842 u32 offset = 0;
2843 int status = 0;
2844 u8 add_status = 0;
84517482 2845
485bf569 2846 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
d9efd2af 2847 dev_err(&adapter->pdev->dev,
485bf569
SN		 2848 "FW Image not properly aligned. "
2849 "Length must be 4 byte aligned.\n");
2850 status = -EINVAL;
2851 goto lancer_fw_exit;
d9efd2af
SB		 2852 }
2853
485bf569
SN		 2854 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
2855 + LANCER_FW_DOWNLOAD_CHUNK;
2856 flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
2857 &flash_cmd.dma, GFP_KERNEL);
2858 if (!flash_cmd.va) {
2859 status = -ENOMEM;
2860 dev_err(&adapter->pdev->dev,
2861 "Memory allocation failure while flashing\n");
2862 goto lancer_fw_exit;
2863 }
84517482 2864
485bf569
SN		 2865 dest_image_ptr = flash_cmd.va +
2866 sizeof(struct lancer_cmd_req_write_object);
2867 image_size = fw->size;
2868 data_ptr = fw->data;
2869
2870 while (image_size) {
2871 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
2872
2873 /* Copy the image chunk content. */
2874 memcpy(dest_image_ptr, data_ptr, chunk_size);
2875
2876 status = lancer_cmd_write_object(adapter, &flash_cmd,
2877 chunk_size, offset, LANCER_FW_DOWNLOAD_LOCATION,
2878 &data_written, &add_status);
2879
2880 if (status)
2881 break;
2882
2883 offset += data_written;
2884 data_ptr += data_written;
2885 image_size -= data_written;
2886 }
2887
2888 if (!status) {
2889 /* Commit the FW written */
2890 status = lancer_cmd_write_object(adapter, &flash_cmd,
2891 0, offset, LANCER_FW_DOWNLOAD_LOCATION,
2892 &data_written, &add_status);
2893 }
2894
2895 dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
2896 flash_cmd.dma);
2897 if (status) {
2898 dev_err(&adapter->pdev->dev,
2899 "Firmware load error. "
2900 "Status code: 0x%x Additional Status: 0x%x\n",
2901 status, add_status);
2902 goto lancer_fw_exit;
2903 }
2904
2905 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
2906lancer_fw_exit:
2907 return status;
2908}
2909
2910static int be_fw_download(struct be_adapter *adapter, const struct firmware* fw)
2911{
2912 struct flash_file_hdr_g2 *fhdr;
2913 struct flash_file_hdr_g3 *fhdr3;
2914 struct image_hdr *img_hdr_ptr = NULL;
2915 struct be_dma_mem flash_cmd;
2916 const u8 *p;
2917 int status = 0, i = 0, num_imgs = 0;
84517482
AK		 2918
2919 p = fw->data;
3f0d4560 2920 fhdr = (struct flash_file_hdr_g2 *) p;
84517482 2921
84517482 2922 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2b7bcebf
IV		 2923 flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
2924 &flash_cmd.dma, GFP_KERNEL);
84517482
AK		 2925 if (!flash_cmd.va) {
2926 status = -ENOMEM;
2927 dev_err(&adapter->pdev->dev,
2928 "Memory allocation failure while flashing\n");
485bf569 2929 goto be_fw_exit;
84517482
AK		 2930 }
2931
3f0d4560
AK		 2932 if ((adapter->generation == BE_GEN3) &&
2933 (get_ufigen_type(fhdr) == BE_GEN3)) {
2934 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2935 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2936 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2937 img_hdr_ptr = (struct image_hdr *) (fw->data +
2938 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2939 i * sizeof(struct image_hdr)));
2940 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2941 status = be_flash_data(adapter, fw, &flash_cmd,
2942 num_imgs);
3f0d4560
AK		 2943 }
2944 } else if ((adapter->generation == BE_GEN2) &&
2945 (get_ufigen_type(fhdr) == BE_GEN2)) {
2946 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2947 } else {
2948 dev_err(&adapter->pdev->dev,
2949 "UFI and Interface are not compatible for flashing\n");
2950 status = -1;
84517482
AK		 2951 }
2952
2b7bcebf
IV		 2953 dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
2954 flash_cmd.dma);
84517482
AK		 2955 if (status) {
2956 dev_err(&adapter->pdev->dev, "Firmware load error\n");
485bf569 2957 goto be_fw_exit;
84517482
AK		 2958 }
2959
af901ca1 2960 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482 2961
485bf569
SN		 2962be_fw_exit:
2963 return status;
2964}
2965
2966int be_load_fw(struct be_adapter *adapter, u8 *fw_file)
2967{
2968 const struct firmware *fw;
2969 int status;
2970
2971 if (!netif_running(adapter->netdev)) {
2972 dev_err(&adapter->pdev->dev,
2973 "Firmware load not allowed (interface is down)\n");
2974 return -1;
2975 }
2976
2977 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2978 if (status)
2979 goto fw_exit;
2980
2981 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2982
2983 if (lancer_chip(adapter))
2984 status = lancer_fw_download(adapter, fw);
2985 else
2986 status = be_fw_download(adapter, fw);
2987
84517482
AK		 2988fw_exit:
2989 release_firmware(fw);
2990 return status;
2991}
2992
6b7c5b94
SP		 2993static struct net_device_ops be_netdev_ops = {
2994 .ndo_open = be_open,
2995 .ndo_stop = be_close,
2996 .ndo_start_xmit = be_xmit,
a54769f5 2997 .ndo_set_rx_mode = be_set_rx_mode,
6b7c5b94
SP		 2998 .ndo_set_mac_address = be_mac_addr_set,
2999 .ndo_change_mtu = be_change_mtu,
ab1594e9 3000 .ndo_get_stats64 = be_get_stats64,
6b7c5b94 3001 .ndo_validate_addr = eth_validate_addr,
6b7c5b94
SP		 3002 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
3003 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
64600ea5 3004 .ndo_set_vf_mac = be_set_vf_mac,
1da87b7f 3005 .ndo_set_vf_vlan = be_set_vf_vlan,
e1d18735 3006 .ndo_set_vf_tx_rate = be_set_vf_tx_rate,
64600ea5 3007 .ndo_get_vf_config = be_get_vf_config
6b7c5b94
SP		 3008};
3009
3010static void be_netdev_init(struct net_device *netdev)
3011{
3012 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda
SP		 3013 struct be_rx_obj *rxo;
3014 int i;
6b7c5b94 3015
6332c8d3 3016 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
8b8ddc68
MM		 3017 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
3018 NETIF_F_HW_VLAN_TX;
3019 if (be_multi_rxq(adapter))
3020 netdev->hw_features |= NETIF_F_RXHASH;
6332c8d3
MM		 3021
3022 netdev->features |= netdev->hw_features |
8b8ddc68 3023 NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
4b972914 3024
eb8a50d9 3025 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
79032644 3026 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
51c59870 3027
6b7c5b94
SP		 3028 netdev->flags |= IFF_MULTICAST;
3029
c190e3c8
AK		 3030 netif_set_gso_max_size(netdev, 65535);
3031
6b7c5b94
SP		 3032 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
3033
3034 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
3035
3abcdeda
SP		 3036 for_all_rx_queues(adapter, rxo, i)
3037 netif_napi_add(netdev, &rxo->rx_eq.napi, be_poll_rx,
3038 BE_NAPI_WEIGHT);
3039
5fb379ee 3040 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94 3041 BE_NAPI_WEIGHT);
6b7c5b94
SP		 3042}
3043
3044static void be_unmap_pci_bars(struct be_adapter *adapter)
3045{
8788fdc2
SP		 3046 if (adapter->csr)
3047 iounmap(adapter->csr);
3048 if (adapter->db)
3049 iounmap(adapter->db);
6b7c5b94
SP		 3050}
3051
3052static int be_map_pci_bars(struct be_adapter *adapter)
3053{
3054 u8 __iomem *addr;
db3ea781 3055 int db_reg;
6b7c5b94 3056
fe6d2a38
SP		 3057 if (lancer_chip(adapter)) {
3058 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 0),
3059 pci_resource_len(adapter->pdev, 0));
3060 if (addr == NULL)
3061 return -ENOMEM;
3062 adapter->db = addr;
3063 return 0;
3064 }
3065
ba343c77
SB		 3066 if (be_physfn(adapter)) {
3067 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
3068 pci_resource_len(adapter->pdev, 2));
3069 if (addr == NULL)
3070 return -ENOMEM;
3071 adapter->csr = addr;
3072 }
6b7c5b94 3073
ba343c77 3074 if (adapter->generation == BE_GEN2) {
ba343c77
SB		 3075 db_reg = 4;
3076 } else {
ba343c77
SB		 3077 if (be_physfn(adapter))
3078 db_reg = 4;
3079 else
3080 db_reg = 0;
3081 }
3082 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
3083 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 3084 if (addr == NULL)
3085 goto pci_map_err;
ba343c77
SB		 3086 adapter->db = addr;
3087
6b7c5b94
SP		 3088 return 0;
3089pci_map_err:
3090 be_unmap_pci_bars(adapter);
3091 return -ENOMEM;
3092}
3093
3094
3095static void be_ctrl_cleanup(struct be_adapter *adapter)
3096{
8788fdc2 3097 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 3098
3099 be_unmap_pci_bars(adapter);
3100
3101 if (mem->va)
2b7bcebf
IV		 3102 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
3103 mem->dma);
e7b909a6 3104
5b8821b7 3105 mem = &adapter->rx_filter;
e7b909a6 3106 if (mem->va)
2b7bcebf
IV		 3107 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
3108 mem->dma);
6b7c5b94
SP		 3109}
3110
6b7c5b94
SP		 3111static int be_ctrl_init(struct be_adapter *adapter)
3112{
8788fdc2
SP		 3113 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
3114 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
5b8821b7 3115 struct be_dma_mem *rx_filter = &adapter->rx_filter;
6b7c5b94 3116 int status;
6b7c5b94
SP		 3117
3118 status = be_map_pci_bars(adapter);
3119 if (status)
e7b909a6 3120 goto done;
6b7c5b94
SP		 3121
3122 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2b7bcebf
IV		 3123 mbox_mem_alloc->va = dma_alloc_coherent(&adapter->pdev->dev,
3124 mbox_mem_alloc->size,
3125 &mbox_mem_alloc->dma,
3126 GFP_KERNEL);
6b7c5b94 3127 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 3128 status = -ENOMEM;
3129 goto unmap_pci_bars;
6b7c5b94
SP		 3130 }
3131 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
3132 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
3133 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
3134 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6 3135
5b8821b7
SP		 3136 rx_filter->size = sizeof(struct be_cmd_req_rx_filter);
3137 rx_filter->va = dma_alloc_coherent(&adapter->pdev->dev, rx_filter->size,
3138 &rx_filter->dma, GFP_KERNEL);
3139 if (rx_filter->va == NULL) {
e7b909a6
SP		 3140 status = -ENOMEM;
3141 goto free_mbox;
3142 }
5b8821b7 3143 memset(rx_filter->va, 0, rx_filter->size);
e7b909a6 3144
2984961c 3145 mutex_init(&adapter->mbox_lock);
8788fdc2
SP		 3146 spin_lock_init(&adapter->mcc_lock);
3147 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 3148
dd131e76 3149 init_completion(&adapter->flash_compl);
cf588477 3150 pci_save_state(adapter->pdev);
6b7c5b94 3151 return 0;
e7b909a6
SP		 3152
3153free_mbox:
2b7bcebf
IV		 3154 dma_free_coherent(&adapter->pdev->dev, mbox_mem_alloc->size,
3155 mbox_mem_alloc->va, mbox_mem_alloc->dma);
e7b909a6
SP		 3156
3157unmap_pci_bars:
3158 be_unmap_pci_bars(adapter);
3159
3160done:
3161 return status;
6b7c5b94
SP		 3162}
3163
3164static void be_stats_cleanup(struct be_adapter *adapter)
3165{
3abcdeda 3166 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 3167
3168 if (cmd->va)
2b7bcebf
IV		 3169 dma_free_coherent(&adapter->pdev->dev, cmd->size,
3170 cmd->va, cmd->dma);
6b7c5b94
SP		 3171}
3172
3173static int be_stats_init(struct be_adapter *adapter)
3174{
3abcdeda 3175 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94 3176
005d5696 3177 if (adapter->generation == BE_GEN2) {
89a88ab8 3178 cmd->size = sizeof(struct be_cmd_req_get_stats_v0);
005d5696
SX		 3179 } else {
3180 if (lancer_chip(adapter))
3181 cmd->size = sizeof(struct lancer_cmd_req_pport_stats);
3182 else
3183 cmd->size = sizeof(struct be_cmd_req_get_stats_v1);
3184 }
2b7bcebf
IV		 3185 cmd->va = dma_alloc_coherent(&adapter->pdev->dev, cmd->size, &cmd->dma,
3186 GFP_KERNEL);
6b7c5b94
SP		 3187 if (cmd->va == NULL)
3188 return -1;
d291b9af 3189 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 3190 return 0;
3191}
3192
3193static void __devexit be_remove(struct pci_dev *pdev)
3194{
3195 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 3196
6b7c5b94
SP		 3197 if (!adapter)
3198 return;
3199
f203af70
SK		 3200 cancel_delayed_work_sync(&adapter->work);
3201
6b7c5b94
SP		 3202 unregister_netdev(adapter->netdev);
3203
5fb379ee
SP		 3204 be_clear(adapter);
3205
6b7c5b94
SP		 3206 be_stats_cleanup(adapter);
3207
3208 be_ctrl_cleanup(adapter);
3209
ba343c77
SB		 3210 be_sriov_disable(adapter);
3211
8d56ff11 3212 be_msix_disable(adapter);
6b7c5b94
SP		 3213
3214 pci_set_drvdata(pdev, NULL);
3215 pci_release_regions(pdev);
3216 pci_disable_device(pdev);
3217
3218 free_netdev(adapter->netdev);
3219}
3220
2243e2e9 3221static int be_get_config(struct be_adapter *adapter)
6b7c5b94 3222{
6b7c5b94
SP		 3223 int status;
3224
3abcdeda
SP		 3225 status = be_cmd_query_fw_cfg(adapter, &adapter->port_num,
3226 &adapter->function_mode, &adapter->function_caps);
43a04fdc
SP		 3227 if (status)
3228 return status;
3229
752961a1 3230 if (adapter->function_mode & FLEX10_MODE)
82903e4b
AK		 3231 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
3232 else
3233 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
3234
9e1453c5
AK		 3235 status = be_cmd_get_cntl_attributes(adapter);
3236 if (status)
3237 return status;
3238
2243e2e9 3239 return 0;
6b7c5b94
SP		 3240}
3241
fe6d2a38
SP		 3242static int be_dev_family_check(struct be_adapter *adapter)
3243{
3244 struct pci_dev *pdev = adapter->pdev;
3245 u32 sli_intf = 0, if_type;
3246
3247 switch (pdev->device) {
3248 case BE_DEVICE_ID1:
3249 case OC_DEVICE_ID1:
3250 adapter->generation = BE_GEN2;
3251 break;
3252 case BE_DEVICE_ID2:
3253 case OC_DEVICE_ID2:
3254 adapter->generation = BE_GEN3;
3255 break;
3256 case OC_DEVICE_ID3:
12f4d0a8 3257 case OC_DEVICE_ID4:
fe6d2a38
SP		 3258 pci_read_config_dword(pdev, SLI_INTF_REG_OFFSET, &sli_intf);
3259 if_type = (sli_intf & SLI_INTF_IF_TYPE_MASK) >>
3260 SLI_INTF_IF_TYPE_SHIFT;
3261
3262 if (((sli_intf & SLI_INTF_VALID_MASK) != SLI_INTF_VALID) ||
3263 if_type != 0x02) {
3264 dev_err(&pdev->dev, "SLI_INTF reg val is not valid\n");
3265 return -EINVAL;
3266 }
fe6d2a38
SP		 3267 adapter->sli_family = ((sli_intf & SLI_INTF_FAMILY_MASK) >>
3268 SLI_INTF_FAMILY_SHIFT);
3269 adapter->generation = BE_GEN3;
3270 break;
3271 default:
3272 adapter->generation = 0;
3273 }
3274 return 0;
3275}
3276
37eed1cb
PR		 3277static int lancer_wait_ready(struct be_adapter *adapter)
3278{
3279#define SLIPORT_READY_TIMEOUT 500
3280 u32 sliport_status;
3281 int status = 0, i;
3282
3283 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
3284 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3285 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
3286 break;
3287
3288 msleep(20);
3289 }
3290
3291 if (i == SLIPORT_READY_TIMEOUT)
3292 status = -1;
3293
3294 return status;
3295}
3296
3297static int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
3298{
3299 int status;
3300 u32 sliport_status, err, reset_needed;
3301 status = lancer_wait_ready(adapter);
3302 if (!status) {
3303 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3304 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
3305 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
3306 if (err && reset_needed) {
3307 iowrite32(SLI_PORT_CONTROL_IP_MASK,
3308 adapter->db + SLIPORT_CONTROL_OFFSET);
3309
3310 /* check adapter has corrected the error */
3311 status = lancer_wait_ready(adapter);
3312 sliport_status = ioread32(adapter->db +
3313 SLIPORT_STATUS_OFFSET);
3314 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
3315 SLIPORT_STATUS_RN_MASK);
3316 if (status || sliport_status)
3317 status = -1;
3318 } else if (err || reset_needed) {
3319 status = -1;
3320 }
3321 }
3322 return status;
3323}
3324
6b7c5b94
SP		 3325static int __devinit be_probe(struct pci_dev *pdev,
3326 const struct pci_device_id *pdev_id)
3327{
3328 int status = 0;
3329 struct be_adapter *adapter;
3330 struct net_device *netdev;
6b7c5b94
SP		 3331
3332 status = pci_enable_device(pdev);
3333 if (status)
3334 goto do_none;
3335
3336 status = pci_request_regions(pdev, DRV_NAME);
3337 if (status)
3338 goto disable_dev;
3339 pci_set_master(pdev);
3340
3c8def97 3341 netdev = alloc_etherdev_mq(sizeof(struct be_adapter), MAX_TX_QS);
6b7c5b94
SP		 3342 if (netdev == NULL) {
3343 status = -ENOMEM;
3344 goto rel_reg;
3345 }
3346 adapter = netdev_priv(netdev);
3347 adapter->pdev = pdev;
3348 pci_set_drvdata(pdev, adapter);
fe6d2a38
SP		 3349
3350 status = be_dev_family_check(adapter);
63657b9c 3351 if (status)
fe6d2a38
SP		 3352 goto free_netdev;
3353
6b7c5b94 3354 adapter->netdev = netdev;
2243e2e9 3355 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94 3356
2b7bcebf 3357 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
6b7c5b94
SP		 3358 if (!status) {
3359 netdev->features |= NETIF_F_HIGHDMA;
3360 } else {
2b7bcebf 3361 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6b7c5b94
SP		 3362 if (status) {
3363 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
3364 goto free_netdev;
3365 }
3366 }
3367
f9449ab7
SP		 3368 status = be_sriov_enable(adapter);
3369 if (status)
3370 goto free_netdev;
ba343c77 3371
6b7c5b94
SP		 3372 status = be_ctrl_init(adapter);
3373 if (status)
f9449ab7 3374 goto disable_sriov;
6b7c5b94 3375
37eed1cb
PR		 3376 if (lancer_chip(adapter)) {
3377 status = lancer_test_and_set_rdy_state(adapter);
3378 if (status) {
3379 dev_err(&pdev->dev, "Adapter in non recoverable error\n");
48f5a191 3380 goto ctrl_clean;
37eed1cb
PR		 3381 }
3382 }
3383
2243e2e9 3384 /* sync up with fw's ready state */
ba343c77
SB		 3385 if (be_physfn(adapter)) {
3386 status = be_cmd_POST(adapter);
3387 if (status)
3388 goto ctrl_clean;
ba343c77 3389 }
6b7c5b94 3390
2243e2e9
SP		 3391 /* tell fw we're ready to fire cmds */
3392 status = be_cmd_fw_init(adapter);
6b7c5b94 3393 if (status)
2243e2e9
SP		 3394 goto ctrl_clean;
3395
a4b4dfab
AK		 3396 status = be_cmd_reset_function(adapter);
3397 if (status)
3398 goto ctrl_clean;
556ae191 3399
2243e2e9
SP		 3400 status = be_stats_init(adapter);
3401 if (status)
3402 goto ctrl_clean;
3403
3404 status = be_get_config(adapter);
6b7c5b94
SP		 3405 if (status)
3406 goto stats_clean;
6b7c5b94 3407
b9ab82c7
SP		 3408 /* The INTR bit may be set in the card when probed by a kdump kernel
3409 * after a crash.
3410 */
3411 if (!lancer_chip(adapter))
3412 be_intr_set(adapter, false);
3413
3abcdeda
SP		 3414 be_msix_enable(adapter);
3415
6b7c5b94 3416 INIT_DELAYED_WORK(&adapter->work, be_worker);
a54769f5 3417 adapter->rx_fc = adapter->tx_fc = true;
6b7c5b94 3418
5fb379ee
SP		 3419 status = be_setup(adapter);
3420 if (status)
3abcdeda 3421 goto msix_disable;
2243e2e9 3422
3abcdeda 3423 be_netdev_init(netdev);
6b7c5b94
SP		 3424 status = register_netdev(netdev);
3425 if (status != 0)
5fb379ee 3426 goto unsetup;
6b7c5b94 3427
c4ca2374 3428 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
34b1ef04 3429
f203af70 3430 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 3431 return 0;
3432
5fb379ee
SP		 3433unsetup:
3434 be_clear(adapter);
3abcdeda
SP		 3435msix_disable:
3436 be_msix_disable(adapter);
6b7c5b94
SP		 3437stats_clean:
3438 be_stats_cleanup(adapter);
3439ctrl_clean:
3440 be_ctrl_cleanup(adapter);
f9449ab7 3441disable_sriov:
ba343c77 3442 be_sriov_disable(adapter);
f9449ab7 3443free_netdev:
fe6d2a38 3444 free_netdev(netdev);
8d56ff11 3445 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 3446rel_reg:
3447 pci_release_regions(pdev);
3448disable_dev:
3449 pci_disable_device(pdev);
3450do_none:
c4ca2374 3451 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 3452 return status;
3453}
3454
3455static int be_suspend(struct pci_dev *pdev, pm_message_t state)
3456{
3457 struct be_adapter *adapter = pci_get_drvdata(pdev);
3458 struct net_device *netdev = adapter->netdev;
3459
a4ca055f 3460 cancel_delayed_work_sync(&adapter->work);
71d8d1b5
AK		 3461 if (adapter->wol)
3462 be_setup_wol(adapter, true);
3463
6b7c5b94
SP		 3464 netif_device_detach(netdev);
3465 if (netif_running(netdev)) {
3466 rtnl_lock();
3467 be_close(netdev);
3468 rtnl_unlock();
3469 }
9b0365f1 3470 be_clear(adapter);
6b7c5b94 3471
a4ca055f 3472 be_msix_disable(adapter);
6b7c5b94
SP		 3473 pci_save_state(pdev);
3474 pci_disable_device(pdev);
3475 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3476 return 0;
3477}
3478
3479static int be_resume(struct pci_dev *pdev)
3480{
3481 int status = 0;
3482 struct be_adapter *adapter = pci_get_drvdata(pdev);
3483 struct net_device *netdev = adapter->netdev;
3484
3485 netif_device_detach(netdev);
3486
3487 status = pci_enable_device(pdev);
3488 if (status)
3489 return status;
3490
3491 pci_set_power_state(pdev, 0);
3492 pci_restore_state(pdev);
3493
a4ca055f 3494 be_msix_enable(adapter);
2243e2e9
SP		 3495 /* tell fw we're ready to fire cmds */
3496 status = be_cmd_fw_init(adapter);
3497 if (status)
3498 return status;
3499
9b0365f1 3500 be_setup(adapter);
6b7c5b94
SP		 3501 if (netif_running(netdev)) {
3502 rtnl_lock();
3503 be_open(netdev);
3504 rtnl_unlock();
3505 }
3506 netif_device_attach(netdev);
71d8d1b5
AK		 3507
3508 if (adapter->wol)
3509 be_setup_wol(adapter, false);
a4ca055f
AK		 3510
3511 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 3512 return 0;
3513}
3514
82456b03
SP		 3515/*
3516 * An FLR will stop BE from DMAing any data.
3517 */
3518static void be_shutdown(struct pci_dev *pdev)
3519{
3520 struct be_adapter *adapter = pci_get_drvdata(pdev);
82456b03 3521
2d5d4154
AK		 3522 if (!adapter)
3523 return;
82456b03 3524
0f4a6828 3525 cancel_delayed_work_sync(&adapter->work);
a4ca055f 3526
2d5d4154 3527 netif_device_detach(adapter->netdev);
82456b03 3528
82456b03
SP		 3529 if (adapter->wol)
3530 be_setup_wol(adapter, true);
3531
57841869
AK		 3532 be_cmd_reset_function(adapter);
3533
82456b03 3534 pci_disable_device(pdev);
82456b03
SP		 3535}
3536
cf588477
SP		 3537static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
3538 pci_channel_state_t state)
3539{
3540 struct be_adapter *adapter = pci_get_drvdata(pdev);
3541 struct net_device *netdev = adapter->netdev;
3542
3543 dev_err(&adapter->pdev->dev, "EEH error detected\n");
3544
3545 adapter->eeh_err = true;
3546
3547 netif_device_detach(netdev);
3548
3549 if (netif_running(netdev)) {
3550 rtnl_lock();
3551 be_close(netdev);
3552 rtnl_unlock();
3553 }
3554 be_clear(adapter);
3555
3556 if (state == pci_channel_io_perm_failure)
3557 return PCI_ERS_RESULT_DISCONNECT;
3558
3559 pci_disable_device(pdev);
3560
3561 return PCI_ERS_RESULT_NEED_RESET;
3562}
3563
3564static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
3565{
3566 struct be_adapter *adapter = pci_get_drvdata(pdev);
3567 int status;
3568
3569 dev_info(&adapter->pdev->dev, "EEH reset\n");
3570 adapter->eeh_err = false;
3571
3572 status = pci_enable_device(pdev);
3573 if (status)
3574 return PCI_ERS_RESULT_DISCONNECT;
3575
3576 pci_set_master(pdev);
3577 pci_set_power_state(pdev, 0);
3578 pci_restore_state(pdev);
3579
3580 /* Check if card is ok and fw is ready */
3581 status = be_cmd_POST(adapter);
3582 if (status)
3583 return PCI_ERS_RESULT_DISCONNECT;
3584
3585 return PCI_ERS_RESULT_RECOVERED;
3586}
3587
3588static void be_eeh_resume(struct pci_dev *pdev)
3589{
3590 int status = 0;
3591 struct be_adapter *adapter = pci_get_drvdata(pdev);
3592 struct net_device *netdev = adapter->netdev;
3593
3594 dev_info(&adapter->pdev->dev, "EEH resume\n");
3595
3596 pci_save_state(pdev);
3597
3598 /* tell fw we're ready to fire cmds */
3599 status = be_cmd_fw_init(adapter);
3600 if (status)
3601 goto err;
3602
3603 status = be_setup(adapter);
3604 if (status)
3605 goto err;
3606
3607 if (netif_running(netdev)) {
3608 status = be_open(netdev);
3609 if (status)
3610 goto err;
3611 }
3612 netif_device_attach(netdev);
3613 return;
3614err:
3615 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 3616}
3617
3618static struct pci_error_handlers be_eeh_handlers = {
3619 .error_detected = be_eeh_err_detected,
3620 .slot_reset = be_eeh_reset,
3621 .resume = be_eeh_resume,
3622};
3623
6b7c5b94
SP		 3624static struct pci_driver be_driver = {
3625 .name = DRV_NAME,
3626 .id_table = be_dev_ids,
3627 .probe = be_probe,
3628 .remove = be_remove,
3629 .suspend = be_suspend,
cf588477 3630 .resume = be_resume,
82456b03 3631 .shutdown = be_shutdown,
cf588477 3632 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 3633};
3634
3635static int __init be_init_module(void)
3636{
8e95a202
JP		 3637 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
3638 rx_frag_size != 2048) {
6b7c5b94
SP		 3639 printk(KERN_WARNING DRV_NAME
3640 " : Module param rx_frag_size must be 2048/4096/8192."
3641 " Using 2048\n");
3642 rx_frag_size = 2048;
3643 }
6b7c5b94
SP		 3644
3645 return pci_register_driver(&be_driver);
3646}
3647module_init(be_init_module);
3648
3649static void __exit be_exit_module(void)
3650{
3651 pci_unregister_driver(&be_driver);
3652}
3653module_exit(be_exit_module);
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