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Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a1702857 | 2 | /* |
3396c782 | 3 | * linux/drivers/net/ethernet/ethoc.c |
a1702857 TR |
4 | * |
5 | * Copyright (C) 2007-2008 Avionic Design Development GmbH | |
6 | * Copyright (C) 2008-2009 Avionic Design GmbH | |
7 | * | |
a1702857 TR |
8 | * Written by Thierry Reding <thierry.reding@avionic-design.de> |
9 | */ | |
10 | ||
b7f080cf | 11 | #include <linux/dma-mapping.h> |
a1702857 | 12 | #include <linux/etherdevice.h> |
a13aff06 | 13 | #include <linux/clk.h> |
a1702857 | 14 | #include <linux/crc32.h> |
a6b7a407 | 15 | #include <linux/interrupt.h> |
a1702857 TR |
16 | #include <linux/io.h> |
17 | #include <linux/mii.h> | |
18 | #include <linux/phy.h> | |
19 | #include <linux/platform_device.h> | |
d43c36dc | 20 | #include <linux/sched.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
e0f4258b | 22 | #include <linux/of.h> |
b34296a9 | 23 | #include <linux/of_net.h> |
9d9779e7 | 24 | #include <linux/module.h> |
a1702857 TR |
25 | #include <net/ethoc.h> |
26 | ||
0baa080c TC |
27 | static int buffer_size = 0x8000; /* 32 KBytes */ |
28 | module_param(buffer_size, int, 0); | |
29 | MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size"); | |
30 | ||
a1702857 TR |
31 | /* register offsets */ |
32 | #define MODER 0x00 | |
33 | #define INT_SOURCE 0x04 | |
34 | #define INT_MASK 0x08 | |
35 | #define IPGT 0x0c | |
36 | #define IPGR1 0x10 | |
37 | #define IPGR2 0x14 | |
38 | #define PACKETLEN 0x18 | |
39 | #define COLLCONF 0x1c | |
40 | #define TX_BD_NUM 0x20 | |
41 | #define CTRLMODER 0x24 | |
42 | #define MIIMODER 0x28 | |
43 | #define MIICOMMAND 0x2c | |
44 | #define MIIADDRESS 0x30 | |
45 | #define MIITX_DATA 0x34 | |
46 | #define MIIRX_DATA 0x38 | |
47 | #define MIISTATUS 0x3c | |
48 | #define MAC_ADDR0 0x40 | |
49 | #define MAC_ADDR1 0x44 | |
50 | #define ETH_HASH0 0x48 | |
51 | #define ETH_HASH1 0x4c | |
52 | #define ETH_TXCTRL 0x50 | |
1112909f | 53 | #define ETH_END 0x54 |
a1702857 TR |
54 | |
55 | /* mode register */ | |
56 | #define MODER_RXEN (1 << 0) /* receive enable */ | |
57 | #define MODER_TXEN (1 << 1) /* transmit enable */ | |
58 | #define MODER_NOPRE (1 << 2) /* no preamble */ | |
59 | #define MODER_BRO (1 << 3) /* broadcast address */ | |
60 | #define MODER_IAM (1 << 4) /* individual address mode */ | |
61 | #define MODER_PRO (1 << 5) /* promiscuous mode */ | |
62 | #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ | |
63 | #define MODER_LOOP (1 << 7) /* loopback */ | |
64 | #define MODER_NBO (1 << 8) /* no back-off */ | |
65 | #define MODER_EDE (1 << 9) /* excess defer enable */ | |
66 | #define MODER_FULLD (1 << 10) /* full duplex */ | |
67 | #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ | |
68 | #define MODER_DCRC (1 << 12) /* delayed CRC enable */ | |
69 | #define MODER_CRC (1 << 13) /* CRC enable */ | |
70 | #define MODER_HUGE (1 << 14) /* huge packets enable */ | |
71 | #define MODER_PAD (1 << 15) /* padding enabled */ | |
72 | #define MODER_RSM (1 << 16) /* receive small packets */ | |
73 | ||
74 | /* interrupt source and mask registers */ | |
75 | #define INT_MASK_TXF (1 << 0) /* transmit frame */ | |
76 | #define INT_MASK_TXE (1 << 1) /* transmit error */ | |
77 | #define INT_MASK_RXF (1 << 2) /* receive frame */ | |
78 | #define INT_MASK_RXE (1 << 3) /* receive error */ | |
79 | #define INT_MASK_BUSY (1 << 4) | |
80 | #define INT_MASK_TXC (1 << 5) /* transmit control frame */ | |
81 | #define INT_MASK_RXC (1 << 6) /* receive control frame */ | |
82 | ||
83 | #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) | |
84 | #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) | |
85 | ||
86 | #define INT_MASK_ALL ( \ | |
87 | INT_MASK_TXF | INT_MASK_TXE | \ | |
88 | INT_MASK_RXF | INT_MASK_RXE | \ | |
89 | INT_MASK_TXC | INT_MASK_RXC | \ | |
90 | INT_MASK_BUSY \ | |
91 | ) | |
92 | ||
93 | /* packet length register */ | |
94 | #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) | |
95 | #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) | |
96 | #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ | |
97 | PACKETLEN_MAX(max)) | |
98 | ||
99 | /* transmit buffer number register */ | |
100 | #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) | |
101 | ||
102 | /* control module mode register */ | |
103 | #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ | |
104 | #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ | |
105 | #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ | |
106 | ||
107 | /* MII mode register */ | |
108 | #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ | |
109 | #define MIIMODER_NOPRE (1 << 8) /* no preamble */ | |
110 | ||
111 | /* MII command register */ | |
112 | #define MIICOMMAND_SCAN (1 << 0) /* scan status */ | |
113 | #define MIICOMMAND_READ (1 << 1) /* read status */ | |
114 | #define MIICOMMAND_WRITE (1 << 2) /* write control data */ | |
115 | ||
116 | /* MII address register */ | |
117 | #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) | |
118 | #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) | |
119 | #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ | |
120 | MIIADDRESS_RGAD(reg)) | |
121 | ||
122 | /* MII transmit data register */ | |
123 | #define MIITX_DATA_VAL(x) ((x) & 0xffff) | |
124 | ||
125 | /* MII receive data register */ | |
126 | #define MIIRX_DATA_VAL(x) ((x) & 0xffff) | |
127 | ||
128 | /* MII status register */ | |
129 | #define MIISTATUS_LINKFAIL (1 << 0) | |
130 | #define MIISTATUS_BUSY (1 << 1) | |
131 | #define MIISTATUS_INVALID (1 << 2) | |
132 | ||
133 | /* TX buffer descriptor */ | |
134 | #define TX_BD_CS (1 << 0) /* carrier sense lost */ | |
135 | #define TX_BD_DF (1 << 1) /* defer indication */ | |
136 | #define TX_BD_LC (1 << 2) /* late collision */ | |
137 | #define TX_BD_RL (1 << 3) /* retransmission limit */ | |
138 | #define TX_BD_RETRY_MASK (0x00f0) | |
139 | #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) | |
140 | #define TX_BD_UR (1 << 8) /* transmitter underrun */ | |
141 | #define TX_BD_CRC (1 << 11) /* TX CRC enable */ | |
142 | #define TX_BD_PAD (1 << 12) /* pad enable for short packets */ | |
143 | #define TX_BD_WRAP (1 << 13) | |
144 | #define TX_BD_IRQ (1 << 14) /* interrupt request enable */ | |
145 | #define TX_BD_READY (1 << 15) /* TX buffer ready */ | |
146 | #define TX_BD_LEN(x) (((x) & 0xffff) << 16) | |
147 | #define TX_BD_LEN_MASK (0xffff << 16) | |
148 | ||
149 | #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ | |
150 | TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) | |
151 | ||
152 | /* RX buffer descriptor */ | |
153 | #define RX_BD_LC (1 << 0) /* late collision */ | |
154 | #define RX_BD_CRC (1 << 1) /* RX CRC error */ | |
155 | #define RX_BD_SF (1 << 2) /* short frame */ | |
156 | #define RX_BD_TL (1 << 3) /* too long */ | |
157 | #define RX_BD_DN (1 << 4) /* dribble nibble */ | |
158 | #define RX_BD_IS (1 << 5) /* invalid symbol */ | |
159 | #define RX_BD_OR (1 << 6) /* receiver overrun */ | |
160 | #define RX_BD_MISS (1 << 7) | |
161 | #define RX_BD_CF (1 << 8) /* control frame */ | |
162 | #define RX_BD_WRAP (1 << 13) | |
163 | #define RX_BD_IRQ (1 << 14) /* interrupt request enable */ | |
164 | #define RX_BD_EMPTY (1 << 15) | |
165 | #define RX_BD_LEN(x) (((x) & 0xffff) << 16) | |
166 | ||
167 | #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ | |
168 | RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) | |
169 | ||
170 | #define ETHOC_BUFSIZ 1536 | |
171 | #define ETHOC_ZLEN 64 | |
172 | #define ETHOC_BD_BASE 0x400 | |
173 | #define ETHOC_TIMEOUT (HZ / 2) | |
174 | #define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) | |
175 | ||
176 | /** | |
177 | * struct ethoc - driver-private device structure | |
178 | * @iobase: pointer to I/O memory region | |
179 | * @membase: pointer to buffer memory region | |
d0ea5cbd | 180 | * @big_endian: just big or little (endian) |
bee7bacd | 181 | * @num_bd: number of buffer descriptors |
a1702857 TR |
182 | * @num_tx: number of send buffers |
183 | * @cur_tx: last send buffer written | |
184 | * @dty_tx: last buffer actually sent | |
185 | * @num_rx: number of receive buffers | |
186 | * @cur_rx: current receive buffer | |
f8555ad0 | 187 | * @vma: pointer to array of virtual memory addresses for buffers |
a1702857 TR |
188 | * @netdev: pointer to network device structure |
189 | * @napi: NAPI structure | |
a1702857 | 190 | * @msg_enable: device state flags |
a1702857 | 191 | * @lock: device lock |
a1702857 | 192 | * @mdio: MDIO bus for PHY access |
d0ea5cbd | 193 | * @clk: clock |
a1702857 | 194 | * @phy_id: address of attached PHY |
d0ea5cbd JB |
195 | * @old_link: previous link info |
196 | * @old_duplex: previous duplex info | |
a1702857 TR |
197 | */ |
198 | struct ethoc { | |
199 | void __iomem *iobase; | |
200 | void __iomem *membase; | |
06e60e59 | 201 | bool big_endian; |
a1702857 | 202 | |
bee7bacd | 203 | unsigned int num_bd; |
a1702857 TR |
204 | unsigned int num_tx; |
205 | unsigned int cur_tx; | |
206 | unsigned int dty_tx; | |
207 | ||
208 | unsigned int num_rx; | |
209 | unsigned int cur_rx; | |
210 | ||
72aa8e1b | 211 | void **vma; |
f8555ad0 | 212 | |
a1702857 TR |
213 | struct net_device *netdev; |
214 | struct napi_struct napi; | |
a1702857 TR |
215 | u32 msg_enable; |
216 | ||
a1702857 TR |
217 | spinlock_t lock; |
218 | ||
a1702857 | 219 | struct mii_bus *mdio; |
a13aff06 | 220 | struct clk *clk; |
a1702857 | 221 | s8 phy_id; |
abf7e53e FF |
222 | |
223 | int old_link; | |
224 | int old_duplex; | |
a1702857 TR |
225 | }; |
226 | ||
227 | /** | |
228 | * struct ethoc_bd - buffer descriptor | |
229 | * @stat: buffer statistics | |
230 | * @addr: physical memory address | |
231 | */ | |
232 | struct ethoc_bd { | |
233 | u32 stat; | |
234 | u32 addr; | |
235 | }; | |
236 | ||
16dd18b0 | 237 | static inline u32 ethoc_read(struct ethoc *dev, loff_t offset) |
a1702857 | 238 | { |
06e60e59 MF |
239 | if (dev->big_endian) |
240 | return ioread32be(dev->iobase + offset); | |
241 | else | |
242 | return ioread32(dev->iobase + offset); | |
a1702857 TR |
243 | } |
244 | ||
16dd18b0 | 245 | static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data) |
a1702857 | 246 | { |
06e60e59 MF |
247 | if (dev->big_endian) |
248 | iowrite32be(data, dev->iobase + offset); | |
249 | else | |
250 | iowrite32(data, dev->iobase + offset); | |
a1702857 TR |
251 | } |
252 | ||
16dd18b0 TC |
253 | static inline void ethoc_read_bd(struct ethoc *dev, int index, |
254 | struct ethoc_bd *bd) | |
a1702857 TR |
255 | { |
256 | loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); | |
257 | bd->stat = ethoc_read(dev, offset + 0); | |
258 | bd->addr = ethoc_read(dev, offset + 4); | |
259 | } | |
260 | ||
16dd18b0 | 261 | static inline void ethoc_write_bd(struct ethoc *dev, int index, |
a1702857 TR |
262 | const struct ethoc_bd *bd) |
263 | { | |
264 | loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); | |
265 | ethoc_write(dev, offset + 0, bd->stat); | |
266 | ethoc_write(dev, offset + 4, bd->addr); | |
267 | } | |
268 | ||
16dd18b0 | 269 | static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask) |
a1702857 TR |
270 | { |
271 | u32 imask = ethoc_read(dev, INT_MASK); | |
272 | imask |= mask; | |
273 | ethoc_write(dev, INT_MASK, imask); | |
274 | } | |
275 | ||
16dd18b0 | 276 | static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask) |
a1702857 TR |
277 | { |
278 | u32 imask = ethoc_read(dev, INT_MASK); | |
279 | imask &= ~mask; | |
280 | ethoc_write(dev, INT_MASK, imask); | |
281 | } | |
282 | ||
16dd18b0 | 283 | static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask) |
a1702857 TR |
284 | { |
285 | ethoc_write(dev, INT_SOURCE, mask); | |
286 | } | |
287 | ||
16dd18b0 | 288 | static inline void ethoc_enable_rx_and_tx(struct ethoc *dev) |
a1702857 TR |
289 | { |
290 | u32 mode = ethoc_read(dev, MODER); | |
291 | mode |= MODER_RXEN | MODER_TXEN; | |
292 | ethoc_write(dev, MODER, mode); | |
293 | } | |
294 | ||
16dd18b0 | 295 | static inline void ethoc_disable_rx_and_tx(struct ethoc *dev) |
a1702857 TR |
296 | { |
297 | u32 mode = ethoc_read(dev, MODER); | |
298 | mode &= ~(MODER_RXEN | MODER_TXEN); | |
299 | ethoc_write(dev, MODER, mode); | |
300 | } | |
301 | ||
5cf3e034 | 302 | static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start) |
a1702857 TR |
303 | { |
304 | struct ethoc_bd bd; | |
305 | int i; | |
72aa8e1b | 306 | void *vma; |
a1702857 TR |
307 | |
308 | dev->cur_tx = 0; | |
309 | dev->dty_tx = 0; | |
310 | dev->cur_rx = 0; | |
311 | ||
ee4f56b9 JB |
312 | ethoc_write(dev, TX_BD_NUM, dev->num_tx); |
313 | ||
a1702857 | 314 | /* setup transmission buffers */ |
f8555ad0 | 315 | bd.addr = mem_start; |
a1702857 | 316 | bd.stat = TX_BD_IRQ | TX_BD_CRC; |
f8555ad0 | 317 | vma = dev->membase; |
a1702857 TR |
318 | |
319 | for (i = 0; i < dev->num_tx; i++) { | |
320 | if (i == dev->num_tx - 1) | |
321 | bd.stat |= TX_BD_WRAP; | |
322 | ||
323 | ethoc_write_bd(dev, i, &bd); | |
324 | bd.addr += ETHOC_BUFSIZ; | |
f8555ad0 JB |
325 | |
326 | dev->vma[i] = vma; | |
327 | vma += ETHOC_BUFSIZ; | |
a1702857 TR |
328 | } |
329 | ||
a1702857 TR |
330 | bd.stat = RX_BD_EMPTY | RX_BD_IRQ; |
331 | ||
332 | for (i = 0; i < dev->num_rx; i++) { | |
333 | if (i == dev->num_rx - 1) | |
334 | bd.stat |= RX_BD_WRAP; | |
335 | ||
336 | ethoc_write_bd(dev, dev->num_tx + i, &bd); | |
337 | bd.addr += ETHOC_BUFSIZ; | |
f8555ad0 JB |
338 | |
339 | dev->vma[dev->num_tx + i] = vma; | |
340 | vma += ETHOC_BUFSIZ; | |
a1702857 TR |
341 | } |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static int ethoc_reset(struct ethoc *dev) | |
347 | { | |
348 | u32 mode; | |
349 | ||
350 | /* TODO: reset controller? */ | |
351 | ||
352 | ethoc_disable_rx_and_tx(dev); | |
353 | ||
354 | /* TODO: setup registers */ | |
355 | ||
356 | /* enable FCS generation and automatic padding */ | |
357 | mode = ethoc_read(dev, MODER); | |
358 | mode |= MODER_CRC | MODER_PAD; | |
359 | ethoc_write(dev, MODER, mode); | |
360 | ||
361 | /* set full-duplex mode */ | |
362 | mode = ethoc_read(dev, MODER); | |
363 | mode |= MODER_FULLD; | |
364 | ethoc_write(dev, MODER, mode); | |
365 | ethoc_write(dev, IPGT, 0x15); | |
366 | ||
367 | ethoc_ack_irq(dev, INT_MASK_ALL); | |
368 | ethoc_enable_irq(dev, INT_MASK_ALL); | |
369 | ethoc_enable_rx_and_tx(dev); | |
370 | return 0; | |
371 | } | |
372 | ||
373 | static unsigned int ethoc_update_rx_stats(struct ethoc *dev, | |
374 | struct ethoc_bd *bd) | |
375 | { | |
376 | struct net_device *netdev = dev->netdev; | |
377 | unsigned int ret = 0; | |
378 | ||
379 | if (bd->stat & RX_BD_TL) { | |
380 | dev_err(&netdev->dev, "RX: frame too long\n"); | |
57616ee4 | 381 | netdev->stats.rx_length_errors++; |
a1702857 TR |
382 | ret++; |
383 | } | |
384 | ||
385 | if (bd->stat & RX_BD_SF) { | |
386 | dev_err(&netdev->dev, "RX: frame too short\n"); | |
57616ee4 | 387 | netdev->stats.rx_length_errors++; |
a1702857 TR |
388 | ret++; |
389 | } | |
390 | ||
391 | if (bd->stat & RX_BD_DN) { | |
392 | dev_err(&netdev->dev, "RX: dribble nibble\n"); | |
57616ee4 | 393 | netdev->stats.rx_frame_errors++; |
a1702857 TR |
394 | } |
395 | ||
396 | if (bd->stat & RX_BD_CRC) { | |
397 | dev_err(&netdev->dev, "RX: wrong CRC\n"); | |
57616ee4 | 398 | netdev->stats.rx_crc_errors++; |
a1702857 TR |
399 | ret++; |
400 | } | |
401 | ||
402 | if (bd->stat & RX_BD_OR) { | |
403 | dev_err(&netdev->dev, "RX: overrun\n"); | |
57616ee4 | 404 | netdev->stats.rx_over_errors++; |
a1702857 TR |
405 | ret++; |
406 | } | |
407 | ||
408 | if (bd->stat & RX_BD_MISS) | |
57616ee4 | 409 | netdev->stats.rx_missed_errors++; |
a1702857 TR |
410 | |
411 | if (bd->stat & RX_BD_LC) { | |
412 | dev_err(&netdev->dev, "RX: late collision\n"); | |
57616ee4 | 413 | netdev->stats.collisions++; |
a1702857 TR |
414 | ret++; |
415 | } | |
416 | ||
417 | return ret; | |
418 | } | |
419 | ||
420 | static int ethoc_rx(struct net_device *dev, int limit) | |
421 | { | |
422 | struct ethoc *priv = netdev_priv(dev); | |
423 | int count; | |
424 | ||
425 | for (count = 0; count < limit; ++count) { | |
426 | unsigned int entry; | |
427 | struct ethoc_bd bd; | |
428 | ||
6a632625 | 429 | entry = priv->num_tx + priv->cur_rx; |
a1702857 | 430 | ethoc_read_bd(priv, entry, &bd); |
20f70ddd JB |
431 | if (bd.stat & RX_BD_EMPTY) { |
432 | ethoc_ack_irq(priv, INT_MASK_RX); | |
433 | /* If packet (interrupt) came in between checking | |
434 | * BD_EMTPY and clearing the interrupt source, then we | |
435 | * risk missing the packet as the RX interrupt won't | |
436 | * trigger right away when we reenable it; hence, check | |
437 | * BD_EMTPY here again to make sure there isn't such a | |
438 | * packet waiting for us... | |
439 | */ | |
440 | ethoc_read_bd(priv, entry, &bd); | |
441 | if (bd.stat & RX_BD_EMPTY) | |
442 | break; | |
443 | } | |
a1702857 TR |
444 | |
445 | if (ethoc_update_rx_stats(priv, &bd) == 0) { | |
446 | int size = bd.stat >> 16; | |
89d71a66 | 447 | struct sk_buff *skb; |
050f91dc TC |
448 | |
449 | size -= 4; /* strip the CRC */ | |
89d71a66 | 450 | skb = netdev_alloc_skb_ip_align(dev, size); |
050f91dc | 451 | |
a1702857 | 452 | if (likely(skb)) { |
f8555ad0 | 453 | void *src = priv->vma[entry]; |
a1702857 TR |
454 | memcpy_fromio(skb_put(skb, size), src, size); |
455 | skb->protocol = eth_type_trans(skb, dev); | |
57616ee4 KV |
456 | dev->stats.rx_packets++; |
457 | dev->stats.rx_bytes += size; | |
a1702857 TR |
458 | netif_receive_skb(skb); |
459 | } else { | |
460 | if (net_ratelimit()) | |
72aa8e1b BG |
461 | dev_warn(&dev->dev, |
462 | "low on memory - packet dropped\n"); | |
a1702857 | 463 | |
57616ee4 | 464 | dev->stats.rx_dropped++; |
a1702857 TR |
465 | break; |
466 | } | |
467 | } | |
468 | ||
469 | /* clear the buffer descriptor so it can be reused */ | |
470 | bd.stat &= ~RX_BD_STATS; | |
471 | bd.stat |= RX_BD_EMPTY; | |
472 | ethoc_write_bd(priv, entry, &bd); | |
6a632625 JB |
473 | if (++priv->cur_rx == priv->num_rx) |
474 | priv->cur_rx = 0; | |
a1702857 TR |
475 | } |
476 | ||
477 | return count; | |
478 | } | |
479 | ||
4f64bcb2 | 480 | static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd) |
a1702857 TR |
481 | { |
482 | struct net_device *netdev = dev->netdev; | |
483 | ||
484 | if (bd->stat & TX_BD_LC) { | |
485 | dev_err(&netdev->dev, "TX: late collision\n"); | |
57616ee4 | 486 | netdev->stats.tx_window_errors++; |
a1702857 TR |
487 | } |
488 | ||
489 | if (bd->stat & TX_BD_RL) { | |
490 | dev_err(&netdev->dev, "TX: retransmit limit\n"); | |
57616ee4 | 491 | netdev->stats.tx_aborted_errors++; |
a1702857 TR |
492 | } |
493 | ||
494 | if (bd->stat & TX_BD_UR) { | |
495 | dev_err(&netdev->dev, "TX: underrun\n"); | |
57616ee4 | 496 | netdev->stats.tx_fifo_errors++; |
a1702857 TR |
497 | } |
498 | ||
499 | if (bd->stat & TX_BD_CS) { | |
500 | dev_err(&netdev->dev, "TX: carrier sense lost\n"); | |
57616ee4 | 501 | netdev->stats.tx_carrier_errors++; |
a1702857 TR |
502 | } |
503 | ||
504 | if (bd->stat & TX_BD_STATS) | |
57616ee4 | 505 | netdev->stats.tx_errors++; |
a1702857 | 506 | |
57616ee4 KV |
507 | netdev->stats.collisions += (bd->stat >> 4) & 0xf; |
508 | netdev->stats.tx_bytes += bd->stat >> 16; | |
509 | netdev->stats.tx_packets++; | |
a1702857 TR |
510 | } |
511 | ||
fa98eb0e | 512 | static int ethoc_tx(struct net_device *dev, int limit) |
a1702857 TR |
513 | { |
514 | struct ethoc *priv = netdev_priv(dev); | |
fa98eb0e JB |
515 | int count; |
516 | struct ethoc_bd bd; | |
a1702857 | 517 | |
fa98eb0e JB |
518 | for (count = 0; count < limit; ++count) { |
519 | unsigned int entry; | |
a1702857 | 520 | |
6a632625 | 521 | entry = priv->dty_tx & (priv->num_tx-1); |
a1702857 TR |
522 | |
523 | ethoc_read_bd(priv, entry, &bd); | |
a1702857 | 524 | |
fa98eb0e JB |
525 | if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) { |
526 | ethoc_ack_irq(priv, INT_MASK_TX); | |
527 | /* If interrupt came in between reading in the BD | |
528 | * and clearing the interrupt source, then we risk | |
529 | * missing the event as the TX interrupt won't trigger | |
530 | * right away when we reenable it; hence, check | |
531 | * BD_EMPTY here again to make sure there isn't such an | |
532 | * event pending... | |
533 | */ | |
534 | ethoc_read_bd(priv, entry, &bd); | |
535 | if (bd.stat & TX_BD_READY || | |
536 | (priv->dty_tx == priv->cur_tx)) | |
537 | break; | |
538 | } | |
539 | ||
4f64bcb2 | 540 | ethoc_update_tx_stats(priv, &bd); |
fa98eb0e | 541 | priv->dty_tx++; |
a1702857 TR |
542 | } |
543 | ||
544 | if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2)) | |
545 | netif_wake_queue(dev); | |
546 | ||
fa98eb0e | 547 | return count; |
a1702857 TR |
548 | } |
549 | ||
550 | static irqreturn_t ethoc_interrupt(int irq, void *dev_id) | |
551 | { | |
57616ee4 | 552 | struct net_device *dev = dev_id; |
a1702857 TR |
553 | struct ethoc *priv = netdev_priv(dev); |
554 | u32 pending; | |
fa98eb0e JB |
555 | u32 mask; |
556 | ||
557 | /* Figure out what triggered the interrupt... | |
558 | * The tricky bit here is that the interrupt source bits get | |
25985edc | 559 | * set in INT_SOURCE for an event regardless of whether that |
fa98eb0e JB |
560 | * event is masked or not. Thus, in order to figure out what |
561 | * triggered the interrupt, we need to remove the sources | |
562 | * for all events that are currently masked. This behaviour | |
563 | * is not particularly well documented but reasonable... | |
564 | */ | |
565 | mask = ethoc_read(priv, INT_MASK); | |
a1702857 | 566 | pending = ethoc_read(priv, INT_SOURCE); |
fa98eb0e JB |
567 | pending &= mask; |
568 | ||
72aa8e1b | 569 | if (unlikely(pending == 0)) |
a1702857 | 570 | return IRQ_NONE; |
a1702857 | 571 | |
50c54a57 | 572 | ethoc_ack_irq(priv, pending); |
a1702857 | 573 | |
fa98eb0e | 574 | /* We always handle the dropped packet interrupt */ |
a1702857 | 575 | if (pending & INT_MASK_BUSY) { |
38b4bc20 | 576 | dev_dbg(&dev->dev, "packet dropped\n"); |
57616ee4 | 577 | dev->stats.rx_dropped++; |
a1702857 TR |
578 | } |
579 | ||
fa98eb0e JB |
580 | /* Handle receive/transmit event by switching to polling */ |
581 | if (pending & (INT_MASK_TX | INT_MASK_RX)) { | |
582 | ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX); | |
583 | napi_schedule(&priv->napi); | |
a1702857 TR |
584 | } |
585 | ||
a1702857 TR |
586 | return IRQ_HANDLED; |
587 | } | |
588 | ||
589 | static int ethoc_get_mac_address(struct net_device *dev, void *addr) | |
590 | { | |
591 | struct ethoc *priv = netdev_priv(dev); | |
592 | u8 *mac = (u8 *)addr; | |
593 | u32 reg; | |
594 | ||
595 | reg = ethoc_read(priv, MAC_ADDR0); | |
596 | mac[2] = (reg >> 24) & 0xff; | |
597 | mac[3] = (reg >> 16) & 0xff; | |
598 | mac[4] = (reg >> 8) & 0xff; | |
599 | mac[5] = (reg >> 0) & 0xff; | |
600 | ||
601 | reg = ethoc_read(priv, MAC_ADDR1); | |
602 | mac[0] = (reg >> 8) & 0xff; | |
603 | mac[1] = (reg >> 0) & 0xff; | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | static int ethoc_poll(struct napi_struct *napi, int budget) | |
609 | { | |
610 | struct ethoc *priv = container_of(napi, struct ethoc, napi); | |
fa98eb0e JB |
611 | int rx_work_done = 0; |
612 | int tx_work_done = 0; | |
613 | ||
614 | rx_work_done = ethoc_rx(priv->netdev, budget); | |
615 | tx_work_done = ethoc_tx(priv->netdev, budget); | |
a1702857 | 616 | |
fa98eb0e | 617 | if (rx_work_done < budget && tx_work_done < budget) { |
6ad20165 | 618 | napi_complete_done(napi, rx_work_done); |
fa98eb0e | 619 | ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX); |
a1702857 TR |
620 | } |
621 | ||
fa98eb0e | 622 | return rx_work_done; |
a1702857 TR |
623 | } |
624 | ||
625 | static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg) | |
626 | { | |
a1702857 | 627 | struct ethoc *priv = bus->priv; |
8dac428a | 628 | int i; |
a1702857 TR |
629 | |
630 | ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); | |
631 | ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ); | |
632 | ||
72aa8e1b | 633 | for (i = 0; i < 5; i++) { |
a1702857 TR |
634 | u32 status = ethoc_read(priv, MIISTATUS); |
635 | if (!(status & MIISTATUS_BUSY)) { | |
636 | u32 data = ethoc_read(priv, MIIRX_DATA); | |
637 | /* reset MII command register */ | |
638 | ethoc_write(priv, MIICOMMAND, 0); | |
639 | return data; | |
640 | } | |
72aa8e1b | 641 | usleep_range(100, 200); |
a1702857 TR |
642 | } |
643 | ||
644 | return -EBUSY; | |
645 | } | |
646 | ||
647 | static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) | |
648 | { | |
a1702857 | 649 | struct ethoc *priv = bus->priv; |
8dac428a | 650 | int i; |
a1702857 TR |
651 | |
652 | ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); | |
653 | ethoc_write(priv, MIITX_DATA, val); | |
654 | ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE); | |
655 | ||
72aa8e1b | 656 | for (i = 0; i < 5; i++) { |
a1702857 | 657 | u32 stat = ethoc_read(priv, MIISTATUS); |
b46773db JB |
658 | if (!(stat & MIISTATUS_BUSY)) { |
659 | /* reset MII command register */ | |
660 | ethoc_write(priv, MIICOMMAND, 0); | |
a1702857 | 661 | return 0; |
b46773db | 662 | } |
72aa8e1b | 663 | usleep_range(100, 200); |
a1702857 TR |
664 | } |
665 | ||
666 | return -EBUSY; | |
667 | } | |
668 | ||
a1702857 TR |
669 | static void ethoc_mdio_poll(struct net_device *dev) |
670 | { | |
abf7e53e FF |
671 | struct ethoc *priv = netdev_priv(dev); |
672 | struct phy_device *phydev = dev->phydev; | |
673 | bool changed = false; | |
674 | u32 mode; | |
675 | ||
676 | if (priv->old_link != phydev->link) { | |
677 | changed = true; | |
678 | priv->old_link = phydev->link; | |
679 | } | |
680 | ||
681 | if (priv->old_duplex != phydev->duplex) { | |
682 | changed = true; | |
683 | priv->old_duplex = phydev->duplex; | |
684 | } | |
685 | ||
686 | if (!changed) | |
687 | return; | |
688 | ||
689 | mode = ethoc_read(priv, MODER); | |
690 | if (phydev->duplex == DUPLEX_FULL) | |
691 | mode |= MODER_FULLD; | |
692 | else | |
693 | mode &= ~MODER_FULLD; | |
694 | ethoc_write(priv, MODER, mode); | |
695 | ||
696 | phy_print_status(phydev); | |
a1702857 TR |
697 | } |
698 | ||
a0a4efed | 699 | static int ethoc_mdio_probe(struct net_device *dev) |
a1702857 TR |
700 | { |
701 | struct ethoc *priv = netdev_priv(dev); | |
702 | struct phy_device *phy; | |
637f33b8 | 703 | int err; |
a1702857 | 704 | |
72aa8e1b | 705 | if (priv->phy_id != -1) |
7f854420 | 706 | phy = mdiobus_get_phy(priv->mdio, priv->phy_id); |
72aa8e1b | 707 | else |
637f33b8 | 708 | phy = phy_find_first(priv->mdio); |
a1702857 TR |
709 | |
710 | if (!phy) { | |
711 | dev_err(&dev->dev, "no PHY found\n"); | |
712 | return -ENXIO; | |
713 | } | |
714 | ||
abf7e53e FF |
715 | priv->old_duplex = -1; |
716 | priv->old_link = -1; | |
717 | ||
f9a8f83b FF |
718 | err = phy_connect_direct(dev, phy, ethoc_mdio_poll, |
719 | PHY_INTERFACE_MODE_GMII); | |
637f33b8 | 720 | if (err) { |
a1702857 | 721 | dev_err(&dev->dev, "could not attach to PHY\n"); |
637f33b8 | 722 | return err; |
a1702857 TR |
723 | } |
724 | ||
58056c1e | 725 | phy_set_max_speed(phy, SPEED_100); |
445a48cc | 726 | |
a1702857 TR |
727 | return 0; |
728 | } | |
729 | ||
730 | static int ethoc_open(struct net_device *dev) | |
731 | { | |
732 | struct ethoc *priv = netdev_priv(dev); | |
a1702857 TR |
733 | int ret; |
734 | ||
735 | ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED, | |
736 | dev->name, dev); | |
737 | if (ret) | |
738 | return ret; | |
739 | ||
d220b942 MF |
740 | napi_enable(&priv->napi); |
741 | ||
5cf3e034 | 742 | ethoc_init_ring(priv, dev->mem_start); |
a1702857 TR |
743 | ethoc_reset(priv); |
744 | ||
745 | if (netif_queue_stopped(dev)) { | |
746 | dev_dbg(&dev->dev, " resuming queue\n"); | |
747 | netif_wake_queue(dev); | |
748 | } else { | |
749 | dev_dbg(&dev->dev, " starting queue\n"); | |
750 | netif_start_queue(dev); | |
751 | } | |
752 | ||
abf7e53e FF |
753 | priv->old_link = -1; |
754 | priv->old_duplex = -1; | |
755 | ||
11331fc2 | 756 | phy_start(dev->phydev); |
a1702857 TR |
757 | |
758 | if (netif_msg_ifup(priv)) { | |
759 | dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n", | |
760 | dev->base_addr, dev->mem_start, dev->mem_end); | |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | static int ethoc_stop(struct net_device *dev) | |
767 | { | |
768 | struct ethoc *priv = netdev_priv(dev); | |
769 | ||
770 | napi_disable(&priv->napi); | |
771 | ||
11331fc2 PR |
772 | if (dev->phydev) |
773 | phy_stop(dev->phydev); | |
a1702857 TR |
774 | |
775 | ethoc_disable_rx_and_tx(priv); | |
776 | free_irq(dev->irq, dev); | |
777 | ||
778 | if (!netif_queue_stopped(dev)) | |
779 | netif_stop_queue(dev); | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
784 | static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
785 | { | |
786 | struct ethoc *priv = netdev_priv(dev); | |
787 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
788 | struct phy_device *phy = NULL; | |
789 | ||
790 | if (!netif_running(dev)) | |
791 | return -EINVAL; | |
792 | ||
793 | if (cmd != SIOCGMIIPHY) { | |
794 | if (mdio->phy_id >= PHY_MAX_ADDR) | |
795 | return -ERANGE; | |
796 | ||
7f854420 | 797 | phy = mdiobus_get_phy(priv->mdio, mdio->phy_id); |
a1702857 TR |
798 | if (!phy) |
799 | return -ENODEV; | |
800 | } else { | |
11331fc2 | 801 | phy = dev->phydev; |
a1702857 TR |
802 | } |
803 | ||
28b04113 | 804 | return phy_mii_ioctl(phy, ifr, cmd); |
a1702857 TR |
805 | } |
806 | ||
efc61a34 | 807 | static void ethoc_do_set_mac_address(struct net_device *dev) |
a1702857 TR |
808 | { |
809 | struct ethoc *priv = netdev_priv(dev); | |
efc61a34 | 810 | unsigned char *mac = dev->dev_addr; |
939d2254 | 811 | |
a1702857 TR |
812 | ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | |
813 | (mac[4] << 8) | (mac[5] << 0)); | |
814 | ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); | |
efc61a34 | 815 | } |
a1702857 | 816 | |
efc61a34 JP |
817 | static int ethoc_set_mac_address(struct net_device *dev, void *p) |
818 | { | |
819 | const struct sockaddr *addr = p; | |
939d2254 | 820 | |
efc61a34 JP |
821 | if (!is_valid_ether_addr(addr->sa_data)) |
822 | return -EADDRNOTAVAIL; | |
823 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
824 | ethoc_do_set_mac_address(dev); | |
a1702857 TR |
825 | return 0; |
826 | } | |
827 | ||
828 | static void ethoc_set_multicast_list(struct net_device *dev) | |
829 | { | |
830 | struct ethoc *priv = netdev_priv(dev); | |
831 | u32 mode = ethoc_read(priv, MODER); | |
22bedad3 | 832 | struct netdev_hw_addr *ha; |
a1702857 TR |
833 | u32 hash[2] = { 0, 0 }; |
834 | ||
835 | /* set loopback mode if requested */ | |
836 | if (dev->flags & IFF_LOOPBACK) | |
837 | mode |= MODER_LOOP; | |
838 | else | |
839 | mode &= ~MODER_LOOP; | |
840 | ||
841 | /* receive broadcast frames if requested */ | |
842 | if (dev->flags & IFF_BROADCAST) | |
843 | mode &= ~MODER_BRO; | |
844 | else | |
845 | mode |= MODER_BRO; | |
846 | ||
847 | /* enable promiscuous mode if requested */ | |
848 | if (dev->flags & IFF_PROMISC) | |
849 | mode |= MODER_PRO; | |
850 | else | |
851 | mode &= ~MODER_PRO; | |
852 | ||
853 | ethoc_write(priv, MODER, mode); | |
854 | ||
855 | /* receive multicast frames */ | |
856 | if (dev->flags & IFF_ALLMULTI) { | |
857 | hash[0] = 0xffffffff; | |
858 | hash[1] = 0xffffffff; | |
859 | } else { | |
22bedad3 JP |
860 | netdev_for_each_mc_addr(ha, dev) { |
861 | u32 crc = ether_crc(ETH_ALEN, ha->addr); | |
a1702857 TR |
862 | int bit = (crc >> 26) & 0x3f; |
863 | hash[bit >> 5] |= 1 << (bit & 0x1f); | |
864 | } | |
865 | } | |
866 | ||
867 | ethoc_write(priv, ETH_HASH0, hash[0]); | |
868 | ethoc_write(priv, ETH_HASH1, hash[1]); | |
869 | } | |
870 | ||
871 | static int ethoc_change_mtu(struct net_device *dev, int new_mtu) | |
872 | { | |
873 | return -ENOSYS; | |
874 | } | |
875 | ||
0290bd29 | 876 | static void ethoc_tx_timeout(struct net_device *dev, unsigned int txqueue) |
a1702857 TR |
877 | { |
878 | struct ethoc *priv = netdev_priv(dev); | |
879 | u32 pending = ethoc_read(priv, INT_SOURCE); | |
880 | if (likely(pending)) | |
881 | ethoc_interrupt(dev->irq, dev); | |
882 | } | |
883 | ||
61357325 | 884 | static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev) |
a1702857 TR |
885 | { |
886 | struct ethoc *priv = netdev_priv(dev); | |
887 | struct ethoc_bd bd; | |
888 | unsigned int entry; | |
889 | void *dest; | |
890 | ||
ee6c21b9 FF |
891 | if (skb_put_padto(skb, ETHOC_ZLEN)) { |
892 | dev->stats.tx_errors++; | |
893 | goto out_no_free; | |
894 | } | |
895 | ||
a1702857 | 896 | if (unlikely(skb->len > ETHOC_BUFSIZ)) { |
57616ee4 | 897 | dev->stats.tx_errors++; |
3790c8cd | 898 | goto out; |
a1702857 TR |
899 | } |
900 | ||
901 | entry = priv->cur_tx % priv->num_tx; | |
902 | spin_lock_irq(&priv->lock); | |
903 | priv->cur_tx++; | |
904 | ||
905 | ethoc_read_bd(priv, entry, &bd); | |
906 | if (unlikely(skb->len < ETHOC_ZLEN)) | |
907 | bd.stat |= TX_BD_PAD; | |
908 | else | |
909 | bd.stat &= ~TX_BD_PAD; | |
910 | ||
f8555ad0 | 911 | dest = priv->vma[entry]; |
a1702857 TR |
912 | memcpy_toio(dest, skb->data, skb->len); |
913 | ||
914 | bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); | |
915 | bd.stat |= TX_BD_LEN(skb->len); | |
916 | ethoc_write_bd(priv, entry, &bd); | |
917 | ||
918 | bd.stat |= TX_BD_READY; | |
919 | ethoc_write_bd(priv, entry, &bd); | |
920 | ||
921 | if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) { | |
922 | dev_dbg(&dev->dev, "stopping queue\n"); | |
923 | netif_stop_queue(dev); | |
924 | } | |
925 | ||
a1702857 | 926 | spin_unlock_irq(&priv->lock); |
68f51394 | 927 | skb_tx_timestamp(skb); |
3790c8cd PM |
928 | out: |
929 | dev_kfree_skb(skb); | |
ee6c21b9 | 930 | out_no_free: |
a1702857 TR |
931 | return NETDEV_TX_OK; |
932 | } | |
933 | ||
1112909f MF |
934 | static int ethoc_get_regs_len(struct net_device *netdev) |
935 | { | |
936 | return ETH_END; | |
937 | } | |
938 | ||
939 | static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
940 | void *p) | |
941 | { | |
942 | struct ethoc *priv = netdev_priv(dev); | |
943 | u32 *regs_buff = p; | |
944 | unsigned i; | |
945 | ||
946 | regs->version = 0; | |
947 | for (i = 0; i < ETH_END / sizeof(u32); ++i) | |
948 | regs_buff[i] = ethoc_read(priv, i * sizeof(u32)); | |
949 | } | |
950 | ||
bee7bacd MF |
951 | static void ethoc_get_ringparam(struct net_device *dev, |
952 | struct ethtool_ringparam *ring) | |
953 | { | |
954 | struct ethoc *priv = netdev_priv(dev); | |
955 | ||
956 | ring->rx_max_pending = priv->num_bd - 1; | |
957 | ring->rx_mini_max_pending = 0; | |
958 | ring->rx_jumbo_max_pending = 0; | |
959 | ring->tx_max_pending = priv->num_bd - 1; | |
960 | ||
961 | ring->rx_pending = priv->num_rx; | |
962 | ring->rx_mini_pending = 0; | |
963 | ring->rx_jumbo_pending = 0; | |
964 | ring->tx_pending = priv->num_tx; | |
965 | } | |
966 | ||
967 | static int ethoc_set_ringparam(struct net_device *dev, | |
968 | struct ethtool_ringparam *ring) | |
969 | { | |
970 | struct ethoc *priv = netdev_priv(dev); | |
971 | ||
972 | if (ring->tx_pending < 1 || ring->rx_pending < 1 || | |
973 | ring->tx_pending + ring->rx_pending > priv->num_bd) | |
974 | return -EINVAL; | |
975 | if (ring->rx_mini_pending || ring->rx_jumbo_pending) | |
976 | return -EINVAL; | |
977 | ||
978 | if (netif_running(dev)) { | |
979 | netif_tx_disable(dev); | |
980 | ethoc_disable_rx_and_tx(priv); | |
981 | ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX); | |
982 | synchronize_irq(dev->irq); | |
983 | } | |
984 | ||
985 | priv->num_tx = rounddown_pow_of_two(ring->tx_pending); | |
986 | priv->num_rx = ring->rx_pending; | |
987 | ethoc_init_ring(priv, dev->mem_start); | |
988 | ||
989 | if (netif_running(dev)) { | |
990 | ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX); | |
991 | ethoc_enable_rx_and_tx(priv); | |
992 | netif_wake_queue(dev); | |
993 | } | |
994 | return 0; | |
995 | } | |
996 | ||
a870a977 | 997 | static const struct ethtool_ops ethoc_ethtool_ops = { |
1112909f MF |
998 | .get_regs_len = ethoc_get_regs_len, |
999 | .get_regs = ethoc_get_regs, | |
3d3ba568 | 1000 | .nway_reset = phy_ethtool_nway_reset, |
fba9110c | 1001 | .get_link = ethtool_op_get_link, |
bee7bacd MF |
1002 | .get_ringparam = ethoc_get_ringparam, |
1003 | .set_ringparam = ethoc_set_ringparam, | |
fba9110c | 1004 | .get_ts_info = ethtool_op_get_ts_info, |
87e544bf PR |
1005 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
1006 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
fba9110c MF |
1007 | }; |
1008 | ||
a1702857 TR |
1009 | static const struct net_device_ops ethoc_netdev_ops = { |
1010 | .ndo_open = ethoc_open, | |
1011 | .ndo_stop = ethoc_stop, | |
1012 | .ndo_do_ioctl = ethoc_ioctl, | |
a1702857 | 1013 | .ndo_set_mac_address = ethoc_set_mac_address, |
afc4b13d | 1014 | .ndo_set_rx_mode = ethoc_set_multicast_list, |
a1702857 TR |
1015 | .ndo_change_mtu = ethoc_change_mtu, |
1016 | .ndo_tx_timeout = ethoc_tx_timeout, | |
a1702857 TR |
1017 | .ndo_start_xmit = ethoc_start_xmit, |
1018 | }; | |
1019 | ||
1020 | /** | |
49ce9c2c | 1021 | * ethoc_probe - initialize OpenCores ethernet MAC |
d0ea5cbd | 1022 | * @pdev: platform device |
a1702857 | 1023 | */ |
a0a4efed | 1024 | static int ethoc_probe(struct platform_device *pdev) |
a1702857 TR |
1025 | { |
1026 | struct net_device *netdev = NULL; | |
1027 | struct resource *res = NULL; | |
1028 | struct resource *mmio = NULL; | |
1029 | struct resource *mem = NULL; | |
1030 | struct ethoc *priv = NULL; | |
c527f814 | 1031 | int num_bd; |
a1702857 | 1032 | int ret = 0; |
a13aff06 MF |
1033 | struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
1034 | u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0; | |
a1702857 TR |
1035 | |
1036 | /* allocate networking device */ | |
1037 | netdev = alloc_etherdev(sizeof(struct ethoc)); | |
1038 | if (!netdev) { | |
a1702857 TR |
1039 | ret = -ENOMEM; |
1040 | goto out; | |
1041 | } | |
1042 | ||
1043 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1044 | platform_set_drvdata(pdev, netdev); | |
1045 | ||
1046 | /* obtain I/O memory space */ | |
1047 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1048 | if (!res) { | |
1049 | dev_err(&pdev->dev, "cannot obtain I/O memory space\n"); | |
1050 | ret = -ENXIO; | |
1051 | goto free; | |
1052 | } | |
1053 | ||
1054 | mmio = devm_request_mem_region(&pdev->dev, res->start, | |
d8645847 | 1055 | resource_size(res), res->name); |
463889e2 | 1056 | if (!mmio) { |
a1702857 TR |
1057 | dev_err(&pdev->dev, "cannot request I/O memory space\n"); |
1058 | ret = -ENXIO; | |
1059 | goto free; | |
1060 | } | |
1061 | ||
1062 | netdev->base_addr = mmio->start; | |
1063 | ||
1064 | /* obtain buffer memory space */ | |
1065 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
0baa080c TC |
1066 | if (res) { |
1067 | mem = devm_request_mem_region(&pdev->dev, res->start, | |
d8645847 | 1068 | resource_size(res), res->name); |
0baa080c TC |
1069 | if (!mem) { |
1070 | dev_err(&pdev->dev, "cannot request memory space\n"); | |
1071 | ret = -ENXIO; | |
1072 | goto free; | |
1073 | } | |
1074 | ||
1075 | netdev->mem_start = mem->start; | |
1076 | netdev->mem_end = mem->end; | |
a1702857 TR |
1077 | } |
1078 | ||
a1702857 TR |
1079 | |
1080 | /* obtain device IRQ number */ | |
1081 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1082 | if (!res) { | |
1083 | dev_err(&pdev->dev, "cannot obtain IRQ\n"); | |
1084 | ret = -ENXIO; | |
1085 | goto free; | |
1086 | } | |
1087 | ||
1088 | netdev->irq = res->start; | |
1089 | ||
1090 | /* setup driver-private data */ | |
1091 | priv = netdev_priv(netdev); | |
1092 | priv->netdev = netdev; | |
1093 | ||
4bdc0d67 | 1094 | priv->iobase = devm_ioremap(&pdev->dev, netdev->base_addr, |
d8645847 | 1095 | resource_size(mmio)); |
a1702857 TR |
1096 | if (!priv->iobase) { |
1097 | dev_err(&pdev->dev, "cannot remap I/O memory space\n"); | |
1098 | ret = -ENXIO; | |
386512d1 | 1099 | goto free; |
a1702857 TR |
1100 | } |
1101 | ||
0baa080c | 1102 | if (netdev->mem_end) { |
4bdc0d67 | 1103 | priv->membase = devm_ioremap(&pdev->dev, |
d8645847 | 1104 | netdev->mem_start, resource_size(mem)); |
0baa080c TC |
1105 | if (!priv->membase) { |
1106 | dev_err(&pdev->dev, "cannot remap memory space\n"); | |
1107 | ret = -ENXIO; | |
386512d1 | 1108 | goto free; |
0baa080c TC |
1109 | } |
1110 | } else { | |
1111 | /* Allocate buffer memory */ | |
a71fba97 | 1112 | priv->membase = dmam_alloc_coherent(&pdev->dev, |
0baa080c TC |
1113 | buffer_size, (void *)&netdev->mem_start, |
1114 | GFP_KERNEL); | |
1115 | if (!priv->membase) { | |
1116 | dev_err(&pdev->dev, "cannot allocate %dB buffer\n", | |
1117 | buffer_size); | |
1118 | ret = -ENOMEM; | |
386512d1 | 1119 | goto free; |
0baa080c TC |
1120 | } |
1121 | netdev->mem_end = netdev->mem_start + buffer_size; | |
a1702857 TR |
1122 | } |
1123 | ||
06e60e59 MF |
1124 | priv->big_endian = pdata ? pdata->big_endian : |
1125 | of_device_is_big_endian(pdev->dev.of_node); | |
1126 | ||
c527f814 JB |
1127 | /* calculate the number of TX/RX buffers, maximum 128 supported */ |
1128 | num_bd = min_t(unsigned int, | |
1129 | 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ); | |
6a632625 JB |
1130 | if (num_bd < 4) { |
1131 | ret = -ENODEV; | |
386512d1 | 1132 | goto free; |
6a632625 | 1133 | } |
bee7bacd | 1134 | priv->num_bd = num_bd; |
6a632625 JB |
1135 | /* num_tx must be a power of two */ |
1136 | priv->num_tx = rounddown_pow_of_two(num_bd >> 1); | |
c527f814 JB |
1137 | priv->num_rx = num_bd - priv->num_tx; |
1138 | ||
6a632625 JB |
1139 | dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n", |
1140 | priv->num_tx, priv->num_rx); | |
1141 | ||
a86854d0 KC |
1142 | priv->vma = devm_kcalloc(&pdev->dev, num_bd, sizeof(void *), |
1143 | GFP_KERNEL); | |
f8555ad0 JB |
1144 | if (!priv->vma) { |
1145 | ret = -ENOMEM; | |
386512d1 | 1146 | goto free; |
f8555ad0 JB |
1147 | } |
1148 | ||
a1702857 | 1149 | /* Allow the platform setup code to pass in a MAC address. */ |
a13aff06 | 1150 | if (pdata) { |
de6b08fd | 1151 | ether_addr_copy(netdev->dev_addr, pdata->hwaddr); |
a1702857 | 1152 | priv->phy_id = pdata->phy_id; |
e0f4258b | 1153 | } else { |
83216e39 | 1154 | of_get_mac_address(pdev->dev.of_node, netdev->dev_addr); |
444c5f92 | 1155 | priv->phy_id = -1; |
a1702857 TR |
1156 | } |
1157 | ||
1158 | /* Check that the given MAC address is valid. If it isn't, read the | |
72aa8e1b BG |
1159 | * current MAC from the controller. |
1160 | */ | |
a1702857 TR |
1161 | if (!is_valid_ether_addr(netdev->dev_addr)) |
1162 | ethoc_get_mac_address(netdev, netdev->dev_addr); | |
1163 | ||
1164 | /* Check the MAC again for validity, if it still isn't choose and | |
72aa8e1b BG |
1165 | * program a random one. |
1166 | */ | |
6d6a505a TK |
1167 | if (!is_valid_ether_addr(netdev->dev_addr)) |
1168 | eth_hw_addr_random(netdev); | |
939d2254 | 1169 | |
efc61a34 | 1170 | ethoc_do_set_mac_address(netdev); |
a1702857 | 1171 | |
a13aff06 MF |
1172 | /* Allow the platform setup code to adjust MII management bus clock. */ |
1173 | if (!eth_clkfreq) { | |
1174 | struct clk *clk = devm_clk_get(&pdev->dev, NULL); | |
1175 | ||
1176 | if (!IS_ERR(clk)) { | |
1177 | priv->clk = clk; | |
1178 | clk_prepare_enable(clk); | |
1179 | eth_clkfreq = clk_get_rate(clk); | |
1180 | } | |
1181 | } | |
1182 | if (eth_clkfreq) { | |
1183 | u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1); | |
1184 | ||
1185 | if (!clkdiv) | |
1186 | clkdiv = 2; | |
1187 | dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv); | |
1188 | ethoc_write(priv, MIIMODER, | |
1189 | (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) | | |
1190 | clkdiv); | |
1191 | } | |
1192 | ||
a1702857 TR |
1193 | /* register MII bus */ |
1194 | priv->mdio = mdiobus_alloc(); | |
1195 | if (!priv->mdio) { | |
1196 | ret = -ENOMEM; | |
bfa49cfc | 1197 | goto free2; |
a1702857 TR |
1198 | } |
1199 | ||
1200 | priv->mdio->name = "ethoc-mdio"; | |
1201 | snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d", | |
1202 | priv->mdio->name, pdev->id); | |
1203 | priv->mdio->read = ethoc_mdio_read; | |
1204 | priv->mdio->write = ethoc_mdio_write; | |
a1702857 TR |
1205 | priv->mdio->priv = priv; |
1206 | ||
a1702857 TR |
1207 | ret = mdiobus_register(priv->mdio); |
1208 | if (ret) { | |
1209 | dev_err(&netdev->dev, "failed to register MDIO bus\n"); | |
5d41f9b7 | 1210 | goto free3; |
a1702857 TR |
1211 | } |
1212 | ||
1213 | ret = ethoc_mdio_probe(netdev); | |
1214 | if (ret) { | |
1215 | dev_err(&netdev->dev, "failed to probe MDIO bus\n"); | |
1216 | goto error; | |
1217 | } | |
1218 | ||
a1702857 TR |
1219 | /* setup the net_device structure */ |
1220 | netdev->netdev_ops = ðoc_netdev_ops; | |
1221 | netdev->watchdog_timeo = ETHOC_TIMEOUT; | |
1222 | netdev->features |= 0; | |
fba9110c | 1223 | netdev->ethtool_ops = ðoc_ethtool_ops; |
a1702857 TR |
1224 | |
1225 | /* setup NAPI */ | |
a1702857 TR |
1226 | netif_napi_add(netdev, &priv->napi, ethoc_poll, 64); |
1227 | ||
a1702857 TR |
1228 | spin_lock_init(&priv->lock); |
1229 | ||
1230 | ret = register_netdev(netdev); | |
1231 | if (ret < 0) { | |
1232 | dev_err(&netdev->dev, "failed to register interface\n"); | |
ee02a4ef | 1233 | goto error2; |
a1702857 TR |
1234 | } |
1235 | ||
1236 | goto out; | |
1237 | ||
ee02a4ef TC |
1238 | error2: |
1239 | netif_napi_del(&priv->napi); | |
a1702857 TR |
1240 | error: |
1241 | mdiobus_unregister(priv->mdio); | |
5d41f9b7 | 1242 | free3: |
a1702857 | 1243 | mdiobus_free(priv->mdio); |
bfa49cfc | 1244 | free2: |
76e597eb | 1245 | clk_disable_unprepare(priv->clk); |
bfa49cfc | 1246 | free: |
a1702857 TR |
1247 | free_netdev(netdev); |
1248 | out: | |
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | /** | |
49ce9c2c | 1253 | * ethoc_remove - shutdown OpenCores ethernet MAC |
a1702857 TR |
1254 | * @pdev: platform device |
1255 | */ | |
a0a4efed | 1256 | static int ethoc_remove(struct platform_device *pdev) |
a1702857 TR |
1257 | { |
1258 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1259 | struct ethoc *priv = netdev_priv(netdev); | |
1260 | ||
a1702857 | 1261 | if (netdev) { |
ee02a4ef | 1262 | netif_napi_del(&priv->napi); |
11331fc2 | 1263 | phy_disconnect(netdev->phydev); |
a1702857 TR |
1264 | |
1265 | if (priv->mdio) { | |
1266 | mdiobus_unregister(priv->mdio); | |
a1702857 TR |
1267 | mdiobus_free(priv->mdio); |
1268 | } | |
76e597eb | 1269 | clk_disable_unprepare(priv->clk); |
a1702857 TR |
1270 | unregister_netdev(netdev); |
1271 | free_netdev(netdev); | |
1272 | } | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | #ifdef CONFIG_PM | |
1278 | static int ethoc_suspend(struct platform_device *pdev, pm_message_t state) | |
1279 | { | |
1280 | return -ENOSYS; | |
1281 | } | |
1282 | ||
1283 | static int ethoc_resume(struct platform_device *pdev) | |
1284 | { | |
1285 | return -ENOSYS; | |
1286 | } | |
1287 | #else | |
1288 | # define ethoc_suspend NULL | |
1289 | # define ethoc_resume NULL | |
1290 | #endif | |
1291 | ||
fa2b1837 | 1292 | static const struct of_device_id ethoc_match[] = { |
c9e358df | 1293 | { .compatible = "opencores,ethoc", }, |
e0f4258b JB |
1294 | {}, |
1295 | }; | |
1296 | MODULE_DEVICE_TABLE(of, ethoc_match); | |
e0f4258b | 1297 | |
a1702857 TR |
1298 | static struct platform_driver ethoc_driver = { |
1299 | .probe = ethoc_probe, | |
a0a4efed | 1300 | .remove = ethoc_remove, |
a1702857 TR |
1301 | .suspend = ethoc_suspend, |
1302 | .resume = ethoc_resume, | |
1303 | .driver = { | |
1304 | .name = "ethoc", | |
e0f4258b | 1305 | .of_match_table = ethoc_match, |
a1702857 TR |
1306 | }, |
1307 | }; | |
1308 | ||
db62f684 | 1309 | module_platform_driver(ethoc_driver); |
a1702857 TR |
1310 | |
1311 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); | |
1312 | MODULE_DESCRIPTION("OpenCores Ethernet MAC driver"); | |
1313 | MODULE_LICENSE("GPL v2"); | |
1314 |