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69785b79 PYC |
1 | /* |
2 | * Faraday FTGMAC100 Gigabit Ethernet | |
3 | * | |
4 | * (C) Copyright 2009-2011 Faraday Technology | |
5 | * Po-Yu Chuang <ratbert@faraday-tech.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
23 | ||
4b70c62b | 24 | #include <linux/clk.h> |
69785b79 PYC |
25 | #include <linux/dma-mapping.h> |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/ethtool.h> | |
17f1bbca | 28 | #include <linux/interrupt.h> |
69785b79 PYC |
29 | #include <linux/io.h> |
30 | #include <linux/module.h> | |
31 | #include <linux/netdevice.h> | |
3af887c3 | 32 | #include <linux/of.h> |
69785b79 PYC |
33 | #include <linux/phy.h> |
34 | #include <linux/platform_device.h> | |
3af887c3 | 35 | #include <linux/property.h> |
f48b3c0d | 36 | #include <linux/crc32.h> |
0fb99688 | 37 | #include <linux/if_vlan.h> |
abcc3eb0 | 38 | #include <linux/of_net.h> |
69785b79 | 39 | #include <net/ip.h> |
bd466c3f | 40 | #include <net/ncsi.h> |
69785b79 PYC |
41 | |
42 | #include "ftgmac100.h" | |
43 | ||
44 | #define DRV_NAME "ftgmac100" | |
45 | #define DRV_VERSION "0.7" | |
46 | ||
52d9138f BH |
47 | /* Arbitrary values, I am not sure the HW has limits */ |
48 | #define MAX_RX_QUEUE_ENTRIES 1024 | |
49 | #define MAX_TX_QUEUE_ENTRIES 1024 | |
50 | #define MIN_RX_QUEUE_ENTRIES 32 | |
51 | #define MIN_TX_QUEUE_ENTRIES 32 | |
52 | ||
53 | /* Defaults */ | |
bd3e4fde BH |
54 | #define DEF_RX_QUEUE_ENTRIES 128 |
55 | #define DEF_TX_QUEUE_ENTRIES 128 | |
69785b79 | 56 | |
7b49cd1c BH |
57 | #define MAX_PKT_SIZE 1536 |
58 | #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */ | |
69785b79 | 59 | |
6ad3d7ed | 60 | /* Min number of tx ring entries before stopping queue */ |
6db74704 | 61 | #define TX_THRESHOLD (MAX_SKB_FRAGS + 1) |
6ad3d7ed | 62 | |
4b70c62b JS |
63 | #define FTGMAC_100MHZ 100000000 |
64 | #define FTGMAC_25MHZ 25000000 | |
65 | ||
69785b79 | 66 | struct ftgmac100 { |
831fb338 | 67 | /* Registers */ |
69785b79 PYC |
68 | struct resource *res; |
69 | void __iomem *base; | |
69785b79 | 70 | |
831fb338 | 71 | /* Rx ring */ |
52d9138f BH |
72 | unsigned int rx_q_entries; |
73 | struct ftgmac100_rxdes *rxdes; | |
74 | dma_addr_t rxdes_dma; | |
75 | struct sk_buff **rx_skbs; | |
69785b79 | 76 | unsigned int rx_pointer; |
831fb338 BH |
77 | u32 rxdes0_edorr_mask; |
78 | ||
79 | /* Tx ring */ | |
52d9138f BH |
80 | unsigned int tx_q_entries; |
81 | struct ftgmac100_txdes *txdes; | |
82 | dma_addr_t txdes_dma; | |
83 | struct sk_buff **tx_skbs; | |
69785b79 PYC |
84 | unsigned int tx_clean_pointer; |
85 | unsigned int tx_pointer; | |
831fb338 | 86 | u32 txdes0_edotr_mask; |
69785b79 | 87 | |
52d9138f BH |
88 | /* Used to signal the reset task of ring change request */ |
89 | unsigned int new_rx_q_entries; | |
90 | unsigned int new_tx_q_entries; | |
91 | ||
d72e01a0 BH |
92 | /* Scratch page to use when rx skb alloc fails */ |
93 | void *rx_scratch; | |
94 | dma_addr_t rx_scratch_dma; | |
95 | ||
831fb338 | 96 | /* Component structures */ |
69785b79 PYC |
97 | struct net_device *netdev; |
98 | struct device *dev; | |
bd466c3f | 99 | struct ncsi_dev *ndev; |
69785b79 | 100 | struct napi_struct napi; |
855944ce | 101 | struct work_struct reset_task; |
69785b79 | 102 | struct mii_bus *mii_bus; |
4b70c62b | 103 | struct clk *clk; |
831fb338 BH |
104 | |
105 | /* Link management */ | |
51764777 BH |
106 | int cur_speed; |
107 | int cur_duplex; | |
bd466c3f | 108 | bool use_ncsi; |
7906a4da | 109 | |
f48b3c0d BH |
110 | /* Multicast filter settings */ |
111 | u32 maht0; | |
112 | u32 maht1; | |
113 | ||
7c8e5141 BH |
114 | /* Flow control settings */ |
115 | bool tx_pause; | |
116 | bool rx_pause; | |
117 | bool aneg_pause; | |
118 | ||
831fb338 | 119 | /* Misc */ |
10cbd640 | 120 | bool need_mac_restart; |
78d28543 | 121 | bool is_aspeed; |
69785b79 PYC |
122 | }; |
123 | ||
874b55bf | 124 | static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr) |
69785b79 PYC |
125 | { |
126 | struct net_device *netdev = priv->netdev; | |
127 | int i; | |
128 | ||
129 | /* NOTE: reset clears all registers */ | |
874b55bf BH |
130 | iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); |
131 | iowrite32(maccr | FTGMAC100_MACCR_SW_RST, | |
132 | priv->base + FTGMAC100_OFFSET_MACCR); | |
c7472ec4 | 133 | for (i = 0; i < 200; i++) { |
69785b79 PYC |
134 | unsigned int maccr; |
135 | ||
136 | maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); | |
137 | if (!(maccr & FTGMAC100_MACCR_SW_RST)) | |
138 | return 0; | |
139 | ||
874b55bf | 140 | udelay(1); |
69785b79 PYC |
141 | } |
142 | ||
874b55bf | 143 | netdev_err(netdev, "Hardware reset failed\n"); |
69785b79 PYC |
144 | return -EIO; |
145 | } | |
146 | ||
874b55bf BH |
147 | static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) |
148 | { | |
149 | u32 maccr = 0; | |
150 | ||
151 | switch (priv->cur_speed) { | |
152 | case SPEED_10: | |
153 | case 0: /* no link */ | |
154 | break; | |
155 | ||
156 | case SPEED_100: | |
157 | maccr |= FTGMAC100_MACCR_FAST_MODE; | |
158 | break; | |
159 | ||
160 | case SPEED_1000: | |
161 | maccr |= FTGMAC100_MACCR_GIGA_MODE; | |
162 | break; | |
163 | default: | |
164 | netdev_err(priv->netdev, "Unknown speed %d !\n", | |
165 | priv->cur_speed); | |
166 | break; | |
167 | } | |
168 | ||
169 | /* (Re)initialize the queue pointers */ | |
170 | priv->rx_pointer = 0; | |
171 | priv->tx_clean_pointer = 0; | |
172 | priv->tx_pointer = 0; | |
874b55bf BH |
173 | |
174 | /* The doc says reset twice with 10us interval */ | |
175 | if (ftgmac100_reset_mac(priv, maccr)) | |
176 | return -EIO; | |
177 | usleep_range(10, 1000); | |
178 | return ftgmac100_reset_mac(priv, maccr); | |
179 | } | |
180 | ||
f39c71b0 | 181 | static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac) |
69785b79 PYC |
182 | { |
183 | unsigned int maddr = mac[0] << 8 | mac[1]; | |
184 | unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; | |
185 | ||
186 | iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); | |
187 | iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); | |
188 | } | |
189 | ||
ba1b1234 | 190 | static void ftgmac100_initial_mac(struct ftgmac100 *priv) |
113ce107 GS |
191 | { |
192 | u8 mac[ETH_ALEN]; | |
193 | unsigned int m; | |
194 | unsigned int l; | |
195 | void *addr; | |
196 | ||
197 | addr = device_get_mac_address(priv->dev, mac, ETH_ALEN); | |
198 | if (addr) { | |
199 | ether_addr_copy(priv->netdev->dev_addr, mac); | |
200 | dev_info(priv->dev, "Read MAC address %pM from device tree\n", | |
201 | mac); | |
202 | return; | |
203 | } | |
204 | ||
205 | m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); | |
206 | l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); | |
207 | ||
208 | mac[0] = (m >> 8) & 0xff; | |
209 | mac[1] = m & 0xff; | |
210 | mac[2] = (l >> 24) & 0xff; | |
211 | mac[3] = (l >> 16) & 0xff; | |
212 | mac[4] = (l >> 8) & 0xff; | |
213 | mac[5] = l & 0xff; | |
214 | ||
113ce107 GS |
215 | if (is_valid_ether_addr(mac)) { |
216 | ether_addr_copy(priv->netdev->dev_addr, mac); | |
217 | dev_info(priv->dev, "Read MAC address %pM from chip\n", mac); | |
218 | } else { | |
219 | eth_hw_addr_random(priv->netdev); | |
220 | dev_info(priv->dev, "Generated random MAC address %pM\n", | |
221 | priv->netdev->dev_addr); | |
222 | } | |
223 | } | |
224 | ||
225 | static int ftgmac100_set_mac_addr(struct net_device *dev, void *p) | |
226 | { | |
227 | int ret; | |
228 | ||
229 | ret = eth_prepare_mac_addr_change(dev, p); | |
230 | if (ret < 0) | |
231 | return ret; | |
232 | ||
233 | eth_commit_mac_addr_change(dev, p); | |
f39c71b0 | 234 | ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr); |
113ce107 GS |
235 | |
236 | return 0; | |
237 | } | |
238 | ||
7c8e5141 BH |
239 | static void ftgmac100_config_pause(struct ftgmac100 *priv) |
240 | { | |
241 | u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16); | |
242 | ||
243 | /* Throttle tx queue when receiving pause frames */ | |
244 | if (priv->rx_pause) | |
245 | fcr |= FTGMAC100_FCR_FC_EN; | |
246 | ||
247 | /* Enables sending pause frames when the RX queue is past a | |
248 | * certain threshold. | |
249 | */ | |
250 | if (priv->tx_pause) | |
251 | fcr |= FTGMAC100_FCR_FCTHR_EN; | |
252 | ||
253 | iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR); | |
254 | } | |
255 | ||
69785b79 PYC |
256 | static void ftgmac100_init_hw(struct ftgmac100 *priv) |
257 | { | |
3833dc6c | 258 | u32 reg, rfifo_sz, tfifo_sz; |
69785b79 | 259 | |
3833dc6c BH |
260 | /* Clear stale interrupts */ |
261 | reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); | |
262 | iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); | |
69785b79 | 263 | |
8eecf7ca | 264 | /* Setup RX ring buffer base */ |
52d9138f | 265 | iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR); |
69785b79 | 266 | |
8eecf7ca | 267 | /* Setup TX ring buffer base */ |
52d9138f | 268 | iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); |
8eecf7ca BH |
269 | |
270 | /* Configure RX buffer size */ | |
271 | iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE), | |
272 | priv->base + FTGMAC100_OFFSET_RBSR); | |
273 | ||
274 | /* Set RX descriptor autopoll */ | |
275 | iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), | |
276 | priv->base + FTGMAC100_OFFSET_APTC); | |
277 | ||
278 | /* Write MAC address */ | |
f39c71b0 | 279 | ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr); |
3833dc6c | 280 | |
f48b3c0d BH |
281 | /* Write multicast filter */ |
282 | iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); | |
283 | iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); | |
284 | ||
3833dc6c BH |
285 | /* Configure descriptor sizes and increase burst sizes according |
286 | * to values in Aspeed SDK. The FIFO arbitration is enabled and | |
287 | * the thresholds set based on the recommended values in the | |
288 | * AST2400 specification. | |
289 | */ | |
290 | iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */ | |
291 | FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */ | |
292 | FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */ | |
293 | FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */ | |
294 | FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */ | |
295 | FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */ | |
296 | FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */ | |
297 | priv->base + FTGMAC100_OFFSET_DBLAC); | |
298 | ||
299 | /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt | |
300 | * mitigation doesn't seem to provide any benefit with NAPI so leave | |
301 | * it at that. | |
302 | */ | |
303 | iowrite32(FTGMAC100_ITC_RXINT_THR(1) | | |
304 | FTGMAC100_ITC_TXINT_THR(1), | |
305 | priv->base + FTGMAC100_OFFSET_ITC); | |
306 | ||
307 | /* Configure FIFO sizes in the TPAFCR register */ | |
308 | reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); | |
309 | rfifo_sz = reg & 0x00000007; | |
310 | tfifo_sz = (reg >> 3) & 0x00000007; | |
311 | reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); | |
312 | reg &= ~0x3f000000; | |
313 | reg |= (tfifo_sz << 27); | |
314 | reg |= (rfifo_sz << 24); | |
315 | iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); | |
69785b79 PYC |
316 | } |
317 | ||
51764777 | 318 | static void ftgmac100_start_hw(struct ftgmac100 *priv) |
69785b79 | 319 | { |
874b55bf | 320 | u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); |
69785b79 | 321 | |
874b55bf BH |
322 | /* Keep the original GMAC and FAST bits */ |
323 | maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE); | |
69785b79 | 324 | |
874b55bf BH |
325 | /* Add all the main enable bits */ |
326 | maccr |= FTGMAC100_MACCR_TXDMA_EN | | |
327 | FTGMAC100_MACCR_RXDMA_EN | | |
328 | FTGMAC100_MACCR_TXMAC_EN | | |
329 | FTGMAC100_MACCR_RXMAC_EN | | |
330 | FTGMAC100_MACCR_CRC_APD | | |
331 | FTGMAC100_MACCR_PHY_LINK_LEVEL | | |
332 | FTGMAC100_MACCR_RX_RUNT | | |
333 | FTGMAC100_MACCR_RX_BROADPKT; | |
69785b79 | 334 | |
874b55bf | 335 | /* Add other bits as needed */ |
51764777 BH |
336 | if (priv->cur_duplex == DUPLEX_FULL) |
337 | maccr |= FTGMAC100_MACCR_FULLDUP; | |
f48b3c0d BH |
338 | if (priv->netdev->flags & IFF_PROMISC) |
339 | maccr |= FTGMAC100_MACCR_RX_ALL; | |
340 | if (priv->netdev->flags & IFF_ALLMULTI) | |
341 | maccr |= FTGMAC100_MACCR_RX_MULTIPKT; | |
342 | else if (netdev_mc_count(priv->netdev)) | |
343 | maccr |= FTGMAC100_MACCR_HT_MULTI_EN; | |
51764777 | 344 | |
0fb99688 BH |
345 | /* Vlan filtering enabled */ |
346 | if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) | |
347 | maccr |= FTGMAC100_MACCR_RM_VLAN; | |
348 | ||
874b55bf | 349 | /* Hit the HW */ |
69785b79 PYC |
350 | iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); |
351 | } | |
352 | ||
353 | static void ftgmac100_stop_hw(struct ftgmac100 *priv) | |
354 | { | |
355 | iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); | |
356 | } | |
357 | ||
f48b3c0d BH |
358 | static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv) |
359 | { | |
360 | struct netdev_hw_addr *ha; | |
361 | ||
362 | priv->maht1 = 0; | |
363 | priv->maht0 = 0; | |
364 | netdev_for_each_mc_addr(ha, priv->netdev) { | |
365 | u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr); | |
366 | ||
367 | crc_val = (~(crc_val >> 2)) & 0x3f; | |
368 | if (crc_val >= 32) | |
369 | priv->maht1 |= 1ul << (crc_val - 32); | |
370 | else | |
371 | priv->maht0 |= 1ul << (crc_val); | |
372 | } | |
373 | } | |
374 | ||
375 | static void ftgmac100_set_rx_mode(struct net_device *netdev) | |
376 | { | |
377 | struct ftgmac100 *priv = netdev_priv(netdev); | |
378 | ||
379 | /* Setup the hash filter */ | |
380 | ftgmac100_calc_mc_hash(priv); | |
381 | ||
382 | /* Interface down ? that's all there is to do */ | |
383 | if (!netif_running(netdev)) | |
384 | return; | |
385 | ||
386 | /* Update the HW */ | |
387 | iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); | |
388 | iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); | |
389 | ||
390 | /* Reconfigure MACCR */ | |
391 | ftgmac100_start_hw(priv); | |
392 | } | |
393 | ||
7b49cd1c BH |
394 | static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry, |
395 | struct ftgmac100_rxdes *rxdes, gfp_t gfp) | |
c06f73fb BH |
396 | { |
397 | struct net_device *netdev = priv->netdev; | |
7b49cd1c | 398 | struct sk_buff *skb; |
c06f73fb | 399 | dma_addr_t map; |
6cee9d64 | 400 | int err = 0; |
c06f73fb | 401 | |
7b49cd1c BH |
402 | skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE); |
403 | if (unlikely(!skb)) { | |
c06f73fb | 404 | if (net_ratelimit()) |
7b49cd1c | 405 | netdev_warn(netdev, "failed to allocate rx skb\n"); |
d72e01a0 BH |
406 | err = -ENOMEM; |
407 | map = priv->rx_scratch_dma; | |
7b49cd1c BH |
408 | } else { |
409 | map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE, | |
410 | DMA_FROM_DEVICE); | |
411 | if (unlikely(dma_mapping_error(priv->dev, map))) { | |
412 | if (net_ratelimit()) | |
413 | netdev_err(netdev, "failed to map rx page\n"); | |
414 | dev_kfree_skb_any(skb); | |
415 | map = priv->rx_scratch_dma; | |
416 | skb = NULL; | |
417 | err = -ENOMEM; | |
418 | } | |
c06f73fb BH |
419 | } |
420 | ||
7b49cd1c BH |
421 | /* Store skb */ |
422 | priv->rx_skbs[entry] = skb; | |
c06f73fb | 423 | |
7b49cd1c | 424 | /* Store DMA address into RX desc */ |
4ca24152 | 425 | rxdes->rxdes3 = cpu_to_le32(map); |
7b49cd1c BH |
426 | |
427 | /* Ensure the above is ordered vs clearing the OWN bit */ | |
428 | dma_wmb(); | |
429 | ||
4ca24152 | 430 | /* Clean status (which resets own bit) */ |
52d9138f | 431 | if (entry == (priv->rx_q_entries - 1)) |
4ca24152 BH |
432 | rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask); |
433 | else | |
434 | rxdes->rxdes0 = 0; | |
7b49cd1c | 435 | |
6cee9d64 | 436 | return err; |
c06f73fb BH |
437 | } |
438 | ||
52d9138f BH |
439 | static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv, |
440 | unsigned int pointer) | |
69785b79 | 441 | { |
52d9138f | 442 | return (pointer + 1) & (priv->rx_q_entries - 1); |
69785b79 PYC |
443 | } |
444 | ||
4ca24152 | 445 | static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status) |
69785b79 PYC |
446 | { |
447 | struct net_device *netdev = priv->netdev; | |
69785b79 | 448 | |
4ca24152 | 449 | if (status & FTGMAC100_RXDES0_RX_ERR) |
69785b79 | 450 | netdev->stats.rx_errors++; |
69785b79 | 451 | |
4ca24152 | 452 | if (status & FTGMAC100_RXDES0_CRC_ERR) |
69785b79 | 453 | netdev->stats.rx_crc_errors++; |
69785b79 | 454 | |
4ca24152 BH |
455 | if (status & (FTGMAC100_RXDES0_FTL | |
456 | FTGMAC100_RXDES0_RUNT | | |
457 | FTGMAC100_RXDES0_RX_ODD_NB)) | |
69785b79 | 458 | netdev->stats.rx_length_errors++; |
69785b79 PYC |
459 | } |
460 | ||
69785b79 PYC |
461 | static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) |
462 | { | |
463 | struct net_device *netdev = priv->netdev; | |
464 | struct ftgmac100_rxdes *rxdes; | |
465 | struct sk_buff *skb; | |
01dd70b5 | 466 | unsigned int pointer, size; |
d930655d | 467 | u32 status, csum_vlan; |
b1977bfb | 468 | dma_addr_t map; |
69785b79 | 469 | |
01dd70b5 BH |
470 | /* Grab next RX descriptor */ |
471 | pointer = priv->rx_pointer; | |
52d9138f | 472 | rxdes = &priv->rxdes[pointer]; |
01dd70b5 | 473 | |
4ca24152 BH |
474 | /* Grab descriptor status */ |
475 | status = le32_to_cpu(rxdes->rxdes0); | |
476 | ||
01dd70b5 | 477 | /* Do we have a packet ? */ |
4ca24152 | 478 | if (!(status & FTGMAC100_RXDES0_RXPKT_RDY)) |
69785b79 PYC |
479 | return false; |
480 | ||
027f426d BH |
481 | /* Order subsequent reads with the test for the ready bit */ |
482 | dma_rmb(); | |
483 | ||
01dd70b5 | 484 | /* We don't cope with fragmented RX packets */ |
4ca24152 BH |
485 | if (unlikely(!(status & FTGMAC100_RXDES0_FRS) || |
486 | !(status & FTGMAC100_RXDES0_LRS))) | |
01dd70b5 BH |
487 | goto drop; |
488 | ||
d930655d BH |
489 | /* Grab received size and csum vlan field in the descriptor */ |
490 | size = status & FTGMAC100_RXDES0_VDBC; | |
491 | csum_vlan = le32_to_cpu(rxdes->rxdes1); | |
492 | ||
01dd70b5 | 493 | /* Any error (other than csum offload) flagged ? */ |
4ca24152 | 494 | if (unlikely(status & RXDES0_ANY_ERROR)) { |
d930655d BH |
495 | /* Correct for incorrect flagging of runt packets |
496 | * with vlan tags... Just accept a runt packet that | |
497 | * has been flagged as vlan and whose size is at | |
498 | * least 60 bytes. | |
499 | */ | |
500 | if ((status & FTGMAC100_RXDES0_RUNT) && | |
501 | (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) && | |
502 | (size >= 60)) | |
503 | status &= ~FTGMAC100_RXDES0_RUNT; | |
504 | ||
505 | /* Any error still in there ? */ | |
506 | if (status & RXDES0_ANY_ERROR) { | |
507 | ftgmac100_rx_packet_error(priv, status); | |
508 | goto drop; | |
509 | } | |
69785b79 PYC |
510 | } |
511 | ||
7b49cd1c | 512 | /* If the packet had no skb (failed to allocate earlier) |
d72e01a0 BH |
513 | * then try to allocate one and skip |
514 | */ | |
7b49cd1c BH |
515 | skb = priv->rx_skbs[pointer]; |
516 | if (!unlikely(skb)) { | |
517 | ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); | |
01dd70b5 | 518 | goto drop; |
69785b79 PYC |
519 | } |
520 | ||
4ca24152 | 521 | if (unlikely(status & FTGMAC100_RXDES0_MULTICAST)) |
69785b79 PYC |
522 | netdev->stats.multicast++; |
523 | ||
67202194 BH |
524 | /* If the HW found checksum errors, bounce it to software. |
525 | * | |
526 | * If we didn't, we need to see if the packet was recognized | |
527 | * by HW as one of the supported checksummed protocols before | |
528 | * we accept the HW test results. | |
69785b79 | 529 | */ |
67202194 | 530 | if (netdev->features & NETIF_F_RXCSUM) { |
d930655d BH |
531 | u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR | |
532 | FTGMAC100_RXDES1_UDP_CHKSUM_ERR | | |
533 | FTGMAC100_RXDES1_IP_CHKSUM_ERR; | |
67202194 | 534 | if ((csum_vlan & err_bits) || |
d930655d | 535 | !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK)) |
67202194 BH |
536 | skb->ip_summed = CHECKSUM_NONE; |
537 | else | |
538 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
539 | } | |
69785b79 | 540 | |
d930655d | 541 | /* Transfer received size to skb */ |
7b49cd1c | 542 | skb_put(skb, size); |
69785b79 | 543 | |
0fb99688 BH |
544 | /* Extract vlan tag */ |
545 | if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
546 | (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL)) | |
547 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
548 | csum_vlan & 0xffff); | |
549 | ||
7b49cd1c | 550 | /* Tear down DMA mapping, do necessary cache management */ |
4ca24152 BH |
551 | map = le32_to_cpu(rxdes->rxdes3); |
552 | ||
7b49cd1c BH |
553 | #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU) |
554 | /* When we don't have an iommu, we can save cycles by not | |
555 | * invalidating the cache for the part of the packet that | |
556 | * wasn't received. | |
557 | */ | |
558 | dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE); | |
559 | #else | |
560 | dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); | |
561 | #endif | |
69785b79 | 562 | |
69785b79 | 563 | |
7b49cd1c BH |
564 | /* Resplenish rx ring */ |
565 | ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); | |
52d9138f | 566 | priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); |
69785b79 | 567 | |
69785b79 PYC |
568 | skb->protocol = eth_type_trans(skb, netdev); |
569 | ||
570 | netdev->stats.rx_packets++; | |
7b49cd1c | 571 | netdev->stats.rx_bytes += size; |
69785b79 PYC |
572 | |
573 | /* push packet to protocol stack */ | |
67202194 BH |
574 | if (skb->ip_summed == CHECKSUM_NONE) |
575 | netif_receive_skb(skb); | |
576 | else | |
577 | napi_gro_receive(&priv->napi, skb); | |
69785b79 PYC |
578 | |
579 | (*processed)++; | |
580 | return true; | |
01dd70b5 BH |
581 | |
582 | drop: | |
583 | /* Clean rxdes0 (which resets own bit) */ | |
4ca24152 | 584 | rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask); |
52d9138f | 585 | priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); |
01dd70b5 BH |
586 | netdev->stats.rx_dropped++; |
587 | return true; | |
69785b79 PYC |
588 | } |
589 | ||
52c0cae8 BH |
590 | static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv, |
591 | unsigned int index) | |
69785b79 | 592 | { |
52d9138f | 593 | if (index == (priv->tx_q_entries - 1)) |
52c0cae8 BH |
594 | return priv->txdes0_edotr_mask; |
595 | else | |
596 | return 0; | |
69785b79 PYC |
597 | } |
598 | ||
52d9138f BH |
599 | static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv, |
600 | unsigned int pointer) | |
69785b79 | 601 | { |
52d9138f | 602 | return (pointer + 1) & (priv->tx_q_entries - 1); |
69785b79 PYC |
603 | } |
604 | ||
6ad3d7ed BH |
605 | static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv) |
606 | { | |
607 | /* Returns the number of available slots in the TX queue | |
608 | * | |
609 | * This always leaves one free slot so we don't have to | |
610 | * worry about empty vs. full, and this simplifies the | |
611 | * test for ftgmac100_tx_buf_cleanable() below | |
612 | */ | |
613 | return (priv->tx_clean_pointer - priv->tx_pointer - 1) & | |
52d9138f | 614 | (priv->tx_q_entries - 1); |
6ad3d7ed BH |
615 | } |
616 | ||
617 | static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv) | |
618 | { | |
619 | return priv->tx_pointer != priv->tx_clean_pointer; | |
620 | } | |
621 | ||
42c2d197 BH |
622 | static void ftgmac100_free_tx_packet(struct ftgmac100 *priv, |
623 | unsigned int pointer, | |
624 | struct sk_buff *skb, | |
52c0cae8 BH |
625 | struct ftgmac100_txdes *txdes, |
626 | u32 ctl_stat) | |
42c2d197 | 627 | { |
52c0cae8 BH |
628 | dma_addr_t map = le32_to_cpu(txdes->txdes3); |
629 | size_t len; | |
42c2d197 | 630 | |
52c0cae8 BH |
631 | if (ctl_stat & FTGMAC100_TXDES0_FTS) { |
632 | len = skb_headlen(skb); | |
633 | dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE); | |
6db74704 | 634 | } else { |
52c0cae8 BH |
635 | len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat); |
636 | dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE); | |
6db74704 | 637 | } |
42c2d197 | 638 | |
52c0cae8 BH |
639 | /* Free SKB on last segment */ |
640 | if (ctl_stat & FTGMAC100_TXDES0_LTS) | |
6db74704 | 641 | dev_kfree_skb(skb); |
42c2d197 | 642 | priv->tx_skbs[pointer] = NULL; |
42c2d197 BH |
643 | } |
644 | ||
69785b79 PYC |
645 | static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) |
646 | { | |
647 | struct net_device *netdev = priv->netdev; | |
648 | struct ftgmac100_txdes *txdes; | |
649 | struct sk_buff *skb; | |
42c2d197 | 650 | unsigned int pointer; |
52c0cae8 | 651 | u32 ctl_stat; |
69785b79 | 652 | |
83617317 | 653 | pointer = priv->tx_clean_pointer; |
52d9138f | 654 | txdes = &priv->txdes[pointer]; |
69785b79 | 655 | |
52c0cae8 BH |
656 | ctl_stat = le32_to_cpu(txdes->txdes0); |
657 | if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN) | |
69785b79 PYC |
658 | return false; |
659 | ||
83617317 | 660 | skb = priv->tx_skbs[pointer]; |
69785b79 PYC |
661 | netdev->stats.tx_packets++; |
662 | netdev->stats.tx_bytes += skb->len; | |
52c0cae8 BH |
663 | ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); |
664 | txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); | |
69785b79 | 665 | |
52d9138f | 666 | priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer); |
69785b79 | 667 | |
69785b79 PYC |
668 | return true; |
669 | } | |
670 | ||
671 | static void ftgmac100_tx_complete(struct ftgmac100 *priv) | |
672 | { | |
6ad3d7ed BH |
673 | struct net_device *netdev = priv->netdev; |
674 | ||
675 | /* Process all completed packets */ | |
676 | while (ftgmac100_tx_buf_cleanable(priv) && | |
677 | ftgmac100_tx_complete_packet(priv)) | |
69785b79 | 678 | ; |
6ad3d7ed BH |
679 | |
680 | /* Restart queue if needed */ | |
681 | smp_mb(); | |
682 | if (unlikely(netif_queue_stopped(netdev) && | |
683 | ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) { | |
684 | struct netdev_queue *txq; | |
685 | ||
686 | txq = netdev_get_tx_queue(netdev, 0); | |
687 | __netif_tx_lock(txq, smp_processor_id()); | |
688 | if (netif_queue_stopped(netdev) && | |
689 | ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) | |
690 | netif_wake_queue(netdev); | |
691 | __netif_tx_unlock(txq); | |
692 | } | |
69785b79 PYC |
693 | } |
694 | ||
05690d63 BH |
695 | static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan) |
696 | { | |
697 | if (skb->protocol == cpu_to_be16(ETH_P_IP)) { | |
698 | u8 ip_proto = ip_hdr(skb)->protocol; | |
699 | ||
700 | *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM; | |
701 | switch(ip_proto) { | |
702 | case IPPROTO_TCP: | |
703 | *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM; | |
704 | return true; | |
705 | case IPPROTO_UDP: | |
706 | *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM; | |
707 | return true; | |
708 | case IPPROTO_IP: | |
709 | return true; | |
710 | } | |
711 | } | |
712 | return skb_checksum_help(skb) == 0; | |
713 | } | |
714 | ||
0a715156 Y |
715 | static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb, |
716 | struct net_device *netdev) | |
69785b79 | 717 | { |
43b25ee7 | 718 | struct ftgmac100 *priv = netdev_priv(netdev); |
6db74704 BH |
719 | struct ftgmac100_txdes *txdes, *first; |
720 | unsigned int pointer, nfrags, len, i, j; | |
52c0cae8 | 721 | u32 f_ctl_stat, ctl_stat, csum_vlan; |
43b25ee7 BH |
722 | dma_addr_t map; |
723 | ||
9b0f7711 BH |
724 | /* The HW doesn't pad small frames */ |
725 | if (eth_skb_pad(skb)) { | |
726 | netdev->stats.tx_dropped++; | |
727 | return NETDEV_TX_OK; | |
728 | } | |
729 | ||
730 | /* Reject oversize packets */ | |
43b25ee7 BH |
731 | if (unlikely(skb->len > MAX_PKT_SIZE)) { |
732 | if (net_ratelimit()) | |
733 | netdev_dbg(netdev, "tx packet too big\n"); | |
3e427a33 | 734 | goto drop; |
43b25ee7 BH |
735 | } |
736 | ||
6db74704 BH |
737 | /* Do we have a limit on #fragments ? I yet have to get a reply |
738 | * from Aspeed. If there's one I haven't hit it. | |
739 | */ | |
740 | nfrags = skb_shinfo(skb)->nr_frags; | |
741 | ||
742 | /* Get header len */ | |
743 | len = skb_headlen(skb); | |
744 | ||
745 | /* Map the packet head */ | |
746 | map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); | |
747 | if (dma_mapping_error(priv->dev, map)) { | |
43b25ee7 | 748 | if (net_ratelimit()) |
6db74704 | 749 | netdev_err(netdev, "map tx packet head failed\n"); |
3e427a33 | 750 | goto drop; |
43b25ee7 | 751 | } |
69785b79 | 752 | |
83617317 BH |
753 | /* Grab the next free tx descriptor */ |
754 | pointer = priv->tx_pointer; | |
52d9138f | 755 | txdes = first = &priv->txdes[pointer]; |
69785b79 | 756 | |
52c0cae8 BH |
757 | /* Setup it up with the packet head. Don't write the head to the |
758 | * ring just yet | |
759 | */ | |
83617317 | 760 | priv->tx_skbs[pointer] = skb; |
52c0cae8 BH |
761 | f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); |
762 | f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; | |
763 | f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); | |
764 | f_ctl_stat |= FTGMAC100_TXDES0_FTS; | |
765 | if (nfrags == 0) | |
766 | f_ctl_stat |= FTGMAC100_TXDES0_LTS; | |
767 | txdes->txdes3 = cpu_to_le32(map); | |
6db74704 BH |
768 | |
769 | /* Setup HW checksumming */ | |
52c0cae8 | 770 | csum_vlan = 0; |
05690d63 BH |
771 | if (skb->ip_summed == CHECKSUM_PARTIAL && |
772 | !ftgmac100_prep_tx_csum(skb, &csum_vlan)) | |
773 | goto drop; | |
0fb99688 BH |
774 | |
775 | /* Add VLAN tag */ | |
776 | if (skb_vlan_tag_present(skb)) { | |
777 | csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG; | |
778 | csum_vlan |= skb_vlan_tag_get(skb) & 0xffff; | |
779 | } | |
780 | ||
52c0cae8 | 781 | txdes->txdes1 = cpu_to_le32(csum_vlan); |
69785b79 | 782 | |
6db74704 | 783 | /* Next descriptor */ |
52d9138f | 784 | pointer = ftgmac100_next_tx_pointer(priv, pointer); |
6db74704 BH |
785 | |
786 | /* Add the fragments */ | |
787 | for (i = 0; i < nfrags; i++) { | |
788 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
789 | ||
790 | len = frag->size; | |
791 | ||
792 | /* Map it */ | |
793 | map = skb_frag_dma_map(priv->dev, frag, 0, len, | |
794 | DMA_TO_DEVICE); | |
795 | if (dma_mapping_error(priv->dev, map)) | |
796 | goto dma_err; | |
797 | ||
798 | /* Setup descriptor */ | |
799 | priv->tx_skbs[pointer] = skb; | |
52d9138f | 800 | txdes = &priv->txdes[pointer]; |
52c0cae8 BH |
801 | ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer); |
802 | ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN; | |
803 | ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len); | |
804 | if (i == (nfrags - 1)) | |
805 | ctl_stat |= FTGMAC100_TXDES0_LTS; | |
806 | txdes->txdes0 = cpu_to_le32(ctl_stat); | |
807 | txdes->txdes1 = 0; | |
808 | txdes->txdes3 = cpu_to_le32(map); | |
809 | ||
810 | /* Next one */ | |
52d9138f | 811 | pointer = ftgmac100_next_tx_pointer(priv, pointer); |
6db74704 BH |
812 | } |
813 | ||
4a2712b2 | 814 | /* Order the previous packet and descriptor udpates |
52c0cae8 | 815 | * before setting the OWN bit on the first descriptor. |
4a2712b2 BH |
816 | */ |
817 | dma_wmb(); | |
52c0cae8 | 818 | first->txdes0 = cpu_to_le32(f_ctl_stat); |
6ad3d7ed | 819 | |
83617317 | 820 | /* Update next TX pointer */ |
6db74704 | 821 | priv->tx_pointer = pointer; |
83617317 | 822 | |
6ad3d7ed BH |
823 | /* If there isn't enough room for all the fragments of a new packet |
824 | * in the TX ring, stop the queue. The sequence below is race free | |
825 | * vs. a concurrent restart in ftgmac100_poll() | |
826 | */ | |
827 | if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) { | |
69785b79 | 828 | netif_stop_queue(netdev); |
6ad3d7ed BH |
829 | /* Order the queue stop with the test below */ |
830 | smp_mb(); | |
831 | if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD) | |
832 | netif_wake_queue(netdev); | |
833 | } | |
69785b79 | 834 | |
8eecf7ca BH |
835 | /* Poke transmitter to read the updated TX descriptors */ |
836 | iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); | |
69785b79 | 837 | |
3e427a33 BH |
838 | return NETDEV_TX_OK; |
839 | ||
6db74704 BH |
840 | dma_err: |
841 | if (net_ratelimit()) | |
842 | netdev_err(netdev, "map tx fragment failed\n"); | |
843 | ||
844 | /* Free head */ | |
845 | pointer = priv->tx_pointer; | |
52c0cae8 BH |
846 | ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat); |
847 | first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask); | |
6db74704 BH |
848 | |
849 | /* Then all fragments */ | |
850 | for (j = 0; j < i; j++) { | |
52d9138f BH |
851 | pointer = ftgmac100_next_tx_pointer(priv, pointer); |
852 | txdes = &priv->txdes[pointer]; | |
52c0cae8 BH |
853 | ctl_stat = le32_to_cpu(txdes->txdes0); |
854 | ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat); | |
855 | txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask); | |
6db74704 BH |
856 | } |
857 | ||
858 | /* This cannot be reached if we successfully mapped the | |
859 | * last fragment, so we know ftgmac100_free_tx_packet() | |
860 | * hasn't freed the skb yet. | |
861 | */ | |
3e427a33 BH |
862 | drop: |
863 | /* Drop the packet */ | |
864 | dev_kfree_skb_any(skb); | |
865 | netdev->stats.tx_dropped++; | |
866 | ||
69785b79 PYC |
867 | return NETDEV_TX_OK; |
868 | } | |
869 | ||
69785b79 PYC |
870 | static void ftgmac100_free_buffers(struct ftgmac100 *priv) |
871 | { | |
872 | int i; | |
873 | ||
87d18757 | 874 | /* Free all RX buffers */ |
52d9138f BH |
875 | for (i = 0; i < priv->rx_q_entries; i++) { |
876 | struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; | |
7b49cd1c | 877 | struct sk_buff *skb = priv->rx_skbs[i]; |
4ca24152 | 878 | dma_addr_t map = le32_to_cpu(rxdes->rxdes3); |
69785b79 | 879 | |
7b49cd1c | 880 | if (!skb) |
69785b79 PYC |
881 | continue; |
882 | ||
7b49cd1c BH |
883 | priv->rx_skbs[i] = NULL; |
884 | dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); | |
885 | dev_kfree_skb_any(skb); | |
69785b79 PYC |
886 | } |
887 | ||
87d18757 | 888 | /* Free all TX buffers */ |
52d9138f BH |
889 | for (i = 0; i < priv->tx_q_entries; i++) { |
890 | struct ftgmac100_txdes *txdes = &priv->txdes[i]; | |
83617317 | 891 | struct sk_buff *skb = priv->tx_skbs[i]; |
69785b79 | 892 | |
52c0cae8 BH |
893 | if (!skb) |
894 | continue; | |
895 | ftgmac100_free_tx_packet(priv, i, skb, txdes, | |
896 | le32_to_cpu(txdes->txdes0)); | |
69785b79 | 897 | } |
69785b79 PYC |
898 | } |
899 | ||
87d18757 | 900 | static void ftgmac100_free_rings(struct ftgmac100 *priv) |
69785b79 | 901 | { |
52d9138f BH |
902 | /* Free skb arrays */ |
903 | kfree(priv->rx_skbs); | |
904 | kfree(priv->tx_skbs); | |
905 | ||
87d18757 | 906 | /* Free descriptors */ |
52d9138f BH |
907 | if (priv->rxdes) |
908 | dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES * | |
909 | sizeof(struct ftgmac100_rxdes), | |
910 | priv->rxdes, priv->rxdes_dma); | |
911 | priv->rxdes = NULL; | |
912 | ||
913 | if (priv->txdes) | |
914 | dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES * | |
915 | sizeof(struct ftgmac100_txdes), | |
916 | priv->txdes, priv->txdes_dma); | |
917 | priv->txdes = NULL; | |
d72e01a0 BH |
918 | |
919 | /* Free scratch packet buffer */ | |
920 | if (priv->rx_scratch) | |
921 | dma_free_coherent(priv->dev, RX_BUF_SIZE, | |
922 | priv->rx_scratch, priv->rx_scratch_dma); | |
87d18757 | 923 | } |
69785b79 | 924 | |
87d18757 BH |
925 | static int ftgmac100_alloc_rings(struct ftgmac100 *priv) |
926 | { | |
52d9138f BH |
927 | /* Allocate skb arrays */ |
928 | priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *), | |
929 | GFP_KERNEL); | |
930 | if (!priv->rx_skbs) | |
931 | return -ENOMEM; | |
932 | priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *), | |
933 | GFP_KERNEL); | |
934 | if (!priv->tx_skbs) | |
935 | return -ENOMEM; | |
936 | ||
87d18757 | 937 | /* Allocate descriptors */ |
750afb08 LC |
938 | priv->rxdes = dma_alloc_coherent(priv->dev, |
939 | MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes), | |
940 | &priv->rxdes_dma, GFP_KERNEL); | |
52d9138f BH |
941 | if (!priv->rxdes) |
942 | return -ENOMEM; | |
750afb08 LC |
943 | priv->txdes = dma_alloc_coherent(priv->dev, |
944 | MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes), | |
945 | &priv->txdes_dma, GFP_KERNEL); | |
52d9138f | 946 | if (!priv->txdes) |
69785b79 PYC |
947 | return -ENOMEM; |
948 | ||
d72e01a0 BH |
949 | /* Allocate scratch packet buffer */ |
950 | priv->rx_scratch = dma_alloc_coherent(priv->dev, | |
951 | RX_BUF_SIZE, | |
952 | &priv->rx_scratch_dma, | |
953 | GFP_KERNEL); | |
954 | if (!priv->rx_scratch) | |
955 | return -ENOMEM; | |
956 | ||
87d18757 BH |
957 | return 0; |
958 | } | |
959 | ||
960 | static void ftgmac100_init_rings(struct ftgmac100 *priv) | |
961 | { | |
52d9138f BH |
962 | struct ftgmac100_rxdes *rxdes = NULL; |
963 | struct ftgmac100_txdes *txdes = NULL; | |
87d18757 BH |
964 | int i; |
965 | ||
52d9138f BH |
966 | /* Update entries counts */ |
967 | priv->rx_q_entries = priv->new_rx_q_entries; | |
968 | priv->tx_q_entries = priv->new_tx_q_entries; | |
969 | ||
970 | if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES)) | |
971 | return; | |
972 | ||
87d18757 | 973 | /* Initialize RX ring */ |
52d9138f BH |
974 | for (i = 0; i < priv->rx_q_entries; i++) { |
975 | rxdes = &priv->rxdes[i]; | |
d72e01a0 | 976 | rxdes->rxdes0 = 0; |
4ca24152 | 977 | rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma); |
d72e01a0 | 978 | } |
4ca24152 BH |
979 | /* Mark the end of the ring */ |
980 | rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); | |
87d18757 | 981 | |
52d9138f BH |
982 | if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES)) |
983 | return; | |
984 | ||
87d18757 | 985 | /* Initialize TX ring */ |
52d9138f BH |
986 | for (i = 0; i < priv->tx_q_entries; i++) { |
987 | txdes = &priv->txdes[i]; | |
52c0cae8 BH |
988 | txdes->txdes0 = 0; |
989 | } | |
990 | txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask); | |
87d18757 BH |
991 | } |
992 | ||
993 | static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv) | |
994 | { | |
995 | int i; | |
69785b79 | 996 | |
52d9138f BH |
997 | for (i = 0; i < priv->rx_q_entries; i++) { |
998 | struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; | |
69785b79 | 999 | |
7b49cd1c | 1000 | if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL)) |
87d18757 | 1001 | return -ENOMEM; |
69785b79 | 1002 | } |
69785b79 | 1003 | return 0; |
69785b79 PYC |
1004 | } |
1005 | ||
69785b79 PYC |
1006 | static void ftgmac100_adjust_link(struct net_device *netdev) |
1007 | { | |
1008 | struct ftgmac100 *priv = netdev_priv(netdev); | |
b3c40adc | 1009 | struct phy_device *phydev = netdev->phydev; |
7c8e5141 | 1010 | bool tx_pause, rx_pause; |
51764777 | 1011 | int new_speed; |
69785b79 | 1012 | |
51764777 BH |
1013 | /* We store "no link" as speed 0 */ |
1014 | if (!phydev->link) | |
1015 | new_speed = 0; | |
1016 | else | |
1017 | new_speed = phydev->speed; | |
1018 | ||
7c8e5141 BH |
1019 | /* Grab pause settings from PHY if configured to do so */ |
1020 | if (priv->aneg_pause) { | |
1021 | rx_pause = tx_pause = phydev->pause; | |
1022 | if (phydev->asym_pause) | |
1023 | tx_pause = !rx_pause; | |
1024 | } else { | |
1025 | rx_pause = priv->rx_pause; | |
1026 | tx_pause = priv->tx_pause; | |
1027 | } | |
1028 | ||
1029 | /* Link hasn't changed, do nothing */ | |
51764777 | 1030 | if (phydev->speed == priv->cur_speed && |
7c8e5141 BH |
1031 | phydev->duplex == priv->cur_duplex && |
1032 | rx_pause == priv->rx_pause && | |
1033 | tx_pause == priv->tx_pause) | |
69785b79 PYC |
1034 | return; |
1035 | ||
51764777 BH |
1036 | /* Print status if we have a link or we had one and just lost it, |
1037 | * don't print otherwise. | |
1038 | */ | |
1039 | if (new_speed || priv->cur_speed) | |
1040 | phy_print_status(phydev); | |
1041 | ||
1042 | priv->cur_speed = new_speed; | |
1043 | priv->cur_duplex = phydev->duplex; | |
7c8e5141 BH |
1044 | priv->rx_pause = rx_pause; |
1045 | priv->tx_pause = tx_pause; | |
51764777 BH |
1046 | |
1047 | /* Link is down, do nothing else */ | |
1048 | if (!new_speed) | |
1049 | return; | |
69785b79 | 1050 | |
855944ce | 1051 | /* Disable all interrupts */ |
69785b79 PYC |
1052 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); |
1053 | ||
855944ce BH |
1054 | /* Reset the adapter asynchronously */ |
1055 | schedule_work(&priv->reset_task); | |
69785b79 PYC |
1056 | } |
1057 | ||
abcc3eb0 | 1058 | static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf) |
69785b79 PYC |
1059 | { |
1060 | struct net_device *netdev = priv->netdev; | |
e574f398 | 1061 | struct phy_device *phydev; |
69785b79 | 1062 | |
e574f398 | 1063 | phydev = phy_find_first(priv->mii_bus); |
69785b79 PYC |
1064 | if (!phydev) { |
1065 | netdev_info(netdev, "%s: no PHY found\n", netdev->name); | |
1066 | return -ENODEV; | |
1067 | } | |
1068 | ||
84eff6d1 | 1069 | phydev = phy_connect(netdev, phydev_name(phydev), |
abcc3eb0 | 1070 | &ftgmac100_adjust_link, intf); |
69785b79 PYC |
1071 | |
1072 | if (IS_ERR(phydev)) { | |
1073 | netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); | |
1074 | return PTR_ERR(phydev); | |
1075 | } | |
1076 | ||
7c8e5141 BH |
1077 | /* Indicate that we support PAUSE frames (see comment in |
1078 | * Documentation/networking/phy.txt) | |
1079 | */ | |
af8d9bb2 | 1080 | phy_support_asym_pause(phydev); |
7c8e5141 | 1081 | |
33de6932 BH |
1082 | /* Display what we found */ |
1083 | phy_attached_info(phydev); | |
1084 | ||
69785b79 PYC |
1085 | return 0; |
1086 | } | |
1087 | ||
69785b79 PYC |
1088 | static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
1089 | { | |
1090 | struct net_device *netdev = bus->priv; | |
1091 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1092 | unsigned int phycr; | |
1093 | int i; | |
1094 | ||
1095 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
1096 | ||
1097 | /* preserve MDC cycle threshold */ | |
1098 | phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; | |
1099 | ||
1100 | phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | | |
1101 | FTGMAC100_PHYCR_REGAD(regnum) | | |
1102 | FTGMAC100_PHYCR_MIIRD; | |
1103 | ||
1104 | iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); | |
1105 | ||
1106 | for (i = 0; i < 10; i++) { | |
1107 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
1108 | ||
1109 | if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { | |
1110 | int data; | |
1111 | ||
1112 | data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); | |
1113 | return FTGMAC100_PHYDATA_MIIRDATA(data); | |
1114 | } | |
1115 | ||
1116 | udelay(100); | |
1117 | } | |
1118 | ||
1119 | netdev_err(netdev, "mdio read timed out\n"); | |
1120 | return -EIO; | |
1121 | } | |
1122 | ||
1123 | static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, | |
1124 | int regnum, u16 value) | |
1125 | { | |
1126 | struct net_device *netdev = bus->priv; | |
1127 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1128 | unsigned int phycr; | |
1129 | int data; | |
1130 | int i; | |
1131 | ||
1132 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
1133 | ||
1134 | /* preserve MDC cycle threshold */ | |
1135 | phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; | |
1136 | ||
1137 | phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | | |
1138 | FTGMAC100_PHYCR_REGAD(regnum) | | |
1139 | FTGMAC100_PHYCR_MIIWR; | |
1140 | ||
1141 | data = FTGMAC100_PHYDATA_MIIWDATA(value); | |
1142 | ||
1143 | iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); | |
1144 | iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); | |
1145 | ||
1146 | for (i = 0; i < 10; i++) { | |
1147 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
1148 | ||
1149 | if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) | |
1150 | return 0; | |
1151 | ||
1152 | udelay(100); | |
1153 | } | |
1154 | ||
1155 | netdev_err(netdev, "mdio write timed out\n"); | |
1156 | return -EIO; | |
1157 | } | |
1158 | ||
69785b79 PYC |
1159 | static void ftgmac100_get_drvinfo(struct net_device *netdev, |
1160 | struct ethtool_drvinfo *info) | |
1161 | { | |
7826d43f JP |
1162 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
1163 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1164 | strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); | |
69785b79 PYC |
1165 | } |
1166 | ||
52d9138f BH |
1167 | static void ftgmac100_get_ringparam(struct net_device *netdev, |
1168 | struct ethtool_ringparam *ering) | |
1169 | { | |
1170 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1171 | ||
1172 | memset(ering, 0, sizeof(*ering)); | |
1173 | ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES; | |
1174 | ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES; | |
1175 | ering->rx_pending = priv->rx_q_entries; | |
1176 | ering->tx_pending = priv->tx_q_entries; | |
1177 | } | |
1178 | ||
1179 | static int ftgmac100_set_ringparam(struct net_device *netdev, | |
1180 | struct ethtool_ringparam *ering) | |
1181 | { | |
1182 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1183 | ||
1184 | if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES || | |
1185 | ering->tx_pending > MAX_TX_QUEUE_ENTRIES || | |
1186 | ering->rx_pending < MIN_RX_QUEUE_ENTRIES || | |
1187 | ering->tx_pending < MIN_TX_QUEUE_ENTRIES || | |
1188 | !is_power_of_2(ering->rx_pending) || | |
1189 | !is_power_of_2(ering->tx_pending)) | |
1190 | return -EINVAL; | |
1191 | ||
1192 | priv->new_rx_q_entries = ering->rx_pending; | |
1193 | priv->new_tx_q_entries = ering->tx_pending; | |
1194 | if (netif_running(netdev)) | |
1195 | schedule_work(&priv->reset_task); | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
7c8e5141 BH |
1200 | static void ftgmac100_get_pauseparam(struct net_device *netdev, |
1201 | struct ethtool_pauseparam *pause) | |
1202 | { | |
1203 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1204 | ||
1205 | pause->autoneg = priv->aneg_pause; | |
1206 | pause->tx_pause = priv->tx_pause; | |
1207 | pause->rx_pause = priv->rx_pause; | |
1208 | } | |
1209 | ||
1210 | static int ftgmac100_set_pauseparam(struct net_device *netdev, | |
1211 | struct ethtool_pauseparam *pause) | |
1212 | { | |
1213 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1214 | struct phy_device *phydev = netdev->phydev; | |
1215 | ||
1216 | priv->aneg_pause = pause->autoneg; | |
1217 | priv->tx_pause = pause->tx_pause; | |
1218 | priv->rx_pause = pause->rx_pause; | |
1219 | ||
70814e81 AL |
1220 | if (phydev) |
1221 | phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause); | |
7c8e5141 | 1222 | |
7c8e5141 | 1223 | if (netif_running(netdev)) { |
70814e81 | 1224 | if (!(phydev && priv->aneg_pause)) |
7c8e5141 BH |
1225 | ftgmac100_config_pause(priv); |
1226 | } | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
69785b79 | 1231 | static const struct ethtool_ops ftgmac100_ethtool_ops = { |
69785b79 PYC |
1232 | .get_drvinfo = ftgmac100_get_drvinfo, |
1233 | .get_link = ethtool_op_get_link, | |
fd24d72c PR |
1234 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
1235 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
e98233a6 | 1236 | .nway_reset = phy_ethtool_nway_reset, |
52d9138f BH |
1237 | .get_ringparam = ftgmac100_get_ringparam, |
1238 | .set_ringparam = ftgmac100_set_ringparam, | |
7c8e5141 BH |
1239 | .get_pauseparam = ftgmac100_get_pauseparam, |
1240 | .set_pauseparam = ftgmac100_set_pauseparam, | |
69785b79 PYC |
1241 | }; |
1242 | ||
69785b79 PYC |
1243 | static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) |
1244 | { | |
1245 | struct net_device *netdev = dev_id; | |
1246 | struct ftgmac100 *priv = netdev_priv(netdev); | |
10cbd640 | 1247 | unsigned int status, new_mask = FTGMAC100_INT_BAD; |
69785b79 | 1248 | |
10cbd640 BH |
1249 | /* Fetch and clear interrupt bits, process abnormal ones */ |
1250 | status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); | |
1251 | iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); | |
1252 | if (unlikely(status & FTGMAC100_INT_BAD)) { | |
1253 | ||
1254 | /* RX buffer unavailable */ | |
1255 | if (status & FTGMAC100_INT_NO_RXBUF) | |
1256 | netdev->stats.rx_over_errors++; | |
1257 | ||
1258 | /* received packet lost due to RX FIFO full */ | |
1259 | if (status & FTGMAC100_INT_RPKT_LOST) | |
1260 | netdev->stats.rx_fifo_errors++; | |
1261 | ||
1262 | /* sent packet lost due to excessive TX collision */ | |
1263 | if (status & FTGMAC100_INT_XPKT_LOST) | |
1264 | netdev->stats.tx_fifo_errors++; | |
1265 | ||
1266 | /* AHB error -> Reset the chip */ | |
1267 | if (status & FTGMAC100_INT_AHB_ERR) { | |
1268 | if (net_ratelimit()) | |
1269 | netdev_warn(netdev, | |
1270 | "AHB bus error ! Resetting chip.\n"); | |
1271 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
1272 | schedule_work(&priv->reset_task); | |
1273 | return IRQ_HANDLED; | |
1274 | } | |
1275 | ||
1276 | /* We may need to restart the MAC after such errors, delay | |
1277 | * this until after we have freed some Rx buffers though | |
1278 | */ | |
1279 | priv->need_mac_restart = true; | |
1280 | ||
1281 | /* Disable those errors until we restart */ | |
1282 | new_mask &= ~status; | |
1283 | } | |
1284 | ||
1285 | /* Only enable "bad" interrupts while NAPI is on */ | |
1286 | iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER); | |
1287 | ||
1288 | /* Schedule NAPI bh */ | |
1289 | napi_schedule_irqoff(&priv->napi); | |
69785b79 PYC |
1290 | |
1291 | return IRQ_HANDLED; | |
1292 | } | |
1293 | ||
4ca24152 BH |
1294 | static bool ftgmac100_check_rx(struct ftgmac100 *priv) |
1295 | { | |
52d9138f | 1296 | struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer]; |
4ca24152 BH |
1297 | |
1298 | /* Do we have a packet ? */ | |
1299 | return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY)); | |
1300 | } | |
1301 | ||
69785b79 PYC |
1302 | static int ftgmac100_poll(struct napi_struct *napi, int budget) |
1303 | { | |
1304 | struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); | |
6ad3d7ed BH |
1305 | int work_done = 0; |
1306 | bool more; | |
69785b79 | 1307 | |
6ad3d7ed BH |
1308 | /* Handle TX completions */ |
1309 | if (ftgmac100_tx_buf_cleanable(priv)) | |
1310 | ftgmac100_tx_complete(priv); | |
69785b79 | 1311 | |
6ad3d7ed | 1312 | /* Handle RX packets */ |
10cbd640 | 1313 | do { |
6ad3d7ed BH |
1314 | more = ftgmac100_rx_packet(priv, &work_done); |
1315 | } while (more && work_done < budget); | |
69785b79 | 1316 | |
69785b79 | 1317 | |
10cbd640 BH |
1318 | /* The interrupt is telling us to kick the MAC back to life |
1319 | * after an RX overflow | |
1320 | */ | |
1321 | if (unlikely(priv->need_mac_restart)) { | |
1322 | ftgmac100_start_hw(priv); | |
69785b79 | 1323 | |
10cbd640 BH |
1324 | /* Re-enable "bad" interrupts */ |
1325 | iowrite32(FTGMAC100_INT_BAD, | |
1326 | priv->base + FTGMAC100_OFFSET_IER); | |
69785b79 PYC |
1327 | } |
1328 | ||
6ad3d7ed BH |
1329 | /* As long as we are waiting for transmit packets to be |
1330 | * completed we keep NAPI going | |
1331 | */ | |
1332 | if (ftgmac100_tx_buf_cleanable(priv)) | |
1333 | work_done = budget; | |
10cbd640 | 1334 | |
6ad3d7ed | 1335 | if (work_done < budget) { |
10cbd640 BH |
1336 | /* We are about to re-enable all interrupts. However |
1337 | * the HW has been latching RX/TX packet interrupts while | |
1338 | * they were masked. So we clear them first, then we need | |
1339 | * to re-check if there's something to process | |
1340 | */ | |
1341 | iowrite32(FTGMAC100_INT_RXTX, | |
1342 | priv->base + FTGMAC100_OFFSET_ISR); | |
ccaf725a BH |
1343 | |
1344 | /* Push the above (and provides a barrier vs. subsequent | |
1345 | * reads of the descriptor). | |
1346 | */ | |
1347 | ioread32(priv->base + FTGMAC100_OFFSET_ISR); | |
1348 | ||
1349 | /* Check RX and TX descriptors for more work to do */ | |
6ad3d7ed BH |
1350 | if (ftgmac100_check_rx(priv) || |
1351 | ftgmac100_tx_buf_cleanable(priv)) | |
10cbd640 BH |
1352 | return budget; |
1353 | ||
1354 | /* deschedule NAPI */ | |
69785b79 PYC |
1355 | napi_complete(napi); |
1356 | ||
1357 | /* enable all interrupts */ | |
10cbd640 | 1358 | iowrite32(FTGMAC100_INT_ALL, |
fc6061cf | 1359 | priv->base + FTGMAC100_OFFSET_IER); |
69785b79 PYC |
1360 | } |
1361 | ||
6ad3d7ed | 1362 | return work_done; |
69785b79 PYC |
1363 | } |
1364 | ||
da40d9d4 BH |
1365 | static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err) |
1366 | { | |
1367 | int err = 0; | |
1368 | ||
1369 | /* Re-init descriptors (adjust queue sizes) */ | |
1370 | ftgmac100_init_rings(priv); | |
1371 | ||
1372 | /* Realloc rx descriptors */ | |
1373 | err = ftgmac100_alloc_rx_buffers(priv); | |
1374 | if (err && !ignore_alloc_err) | |
1375 | return err; | |
1376 | ||
1377 | /* Reinit and restart HW */ | |
1378 | ftgmac100_init_hw(priv); | |
7c8e5141 | 1379 | ftgmac100_config_pause(priv); |
da40d9d4 BH |
1380 | ftgmac100_start_hw(priv); |
1381 | ||
1382 | /* Re-enable the device */ | |
1383 | napi_enable(&priv->napi); | |
1384 | netif_start_queue(priv->netdev); | |
1385 | ||
1386 | /* Enable all interrupts */ | |
10cbd640 | 1387 | iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER); |
da40d9d4 BH |
1388 | |
1389 | return err; | |
1390 | } | |
1391 | ||
855944ce BH |
1392 | static void ftgmac100_reset_task(struct work_struct *work) |
1393 | { | |
1394 | struct ftgmac100 *priv = container_of(work, struct ftgmac100, | |
1395 | reset_task); | |
1396 | struct net_device *netdev = priv->netdev; | |
1397 | int err; | |
1398 | ||
1399 | netdev_dbg(netdev, "Resetting NIC...\n"); | |
1400 | ||
1401 | /* Lock the world */ | |
1402 | rtnl_lock(); | |
1403 | if (netdev->phydev) | |
1404 | mutex_lock(&netdev->phydev->lock); | |
1405 | if (priv->mii_bus) | |
1406 | mutex_lock(&priv->mii_bus->mdio_lock); | |
1407 | ||
1408 | ||
1409 | /* Check if the interface is still up */ | |
1410 | if (!netif_running(netdev)) | |
1411 | goto bail; | |
1412 | ||
1413 | /* Stop the network stack */ | |
1414 | netif_trans_update(netdev); | |
1415 | napi_disable(&priv->napi); | |
1416 | netif_tx_disable(netdev); | |
1417 | ||
1418 | /* Stop and reset the MAC */ | |
1419 | ftgmac100_stop_hw(priv); | |
874b55bf | 1420 | err = ftgmac100_reset_and_config_mac(priv); |
855944ce BH |
1421 | if (err) { |
1422 | /* Not much we can do ... it might come back... */ | |
1423 | netdev_err(netdev, "attempting to continue...\n"); | |
1424 | } | |
1425 | ||
1426 | /* Free all rx and tx buffers */ | |
1427 | ftgmac100_free_buffers(priv); | |
1428 | ||
855944ce BH |
1429 | /* Setup everything again and restart chip */ |
1430 | ftgmac100_init_all(priv, true); | |
1431 | ||
1432 | netdev_dbg(netdev, "Reset done !\n"); | |
1433 | bail: | |
1434 | if (priv->mii_bus) | |
1435 | mutex_unlock(&priv->mii_bus->mdio_lock); | |
1436 | if (netdev->phydev) | |
1437 | mutex_unlock(&netdev->phydev->lock); | |
1438 | rtnl_unlock(); | |
1439 | } | |
1440 | ||
69785b79 PYC |
1441 | static int ftgmac100_open(struct net_device *netdev) |
1442 | { | |
1443 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1444 | int err; | |
1445 | ||
87d18757 BH |
1446 | /* Allocate ring buffers */ |
1447 | err = ftgmac100_alloc_rings(priv); | |
69785b79 | 1448 | if (err) { |
87d18757 BH |
1449 | netdev_err(netdev, "Failed to allocate descriptors\n"); |
1450 | return err; | |
69785b79 PYC |
1451 | } |
1452 | ||
51764777 BH |
1453 | /* When using NC-SI we force the speed to 100Mbit/s full duplex, |
1454 | * | |
1455 | * Otherwise we leave it set to 0 (no link), the link | |
1456 | * message from the PHY layer will handle setting it up to | |
1457 | * something else if needed. | |
1458 | */ | |
1459 | if (priv->use_ncsi) { | |
1460 | priv->cur_duplex = DUPLEX_FULL; | |
1461 | priv->cur_speed = SPEED_100; | |
1462 | } else { | |
1463 | priv->cur_duplex = 0; | |
1464 | priv->cur_speed = 0; | |
1465 | } | |
1466 | ||
874b55bf BH |
1467 | /* Reset the hardware */ |
1468 | err = ftgmac100_reset_and_config_mac(priv); | |
69785b79 PYC |
1469 | if (err) |
1470 | goto err_hw; | |
1471 | ||
b8dbecff BH |
1472 | /* Initialize NAPI */ |
1473 | netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); | |
1474 | ||
81f1eca6 BH |
1475 | /* Grab our interrupt */ |
1476 | err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev); | |
1477 | if (err) { | |
1478 | netdev_err(netdev, "failed to request irq %d\n", netdev->irq); | |
1479 | goto err_irq; | |
1480 | } | |
1481 | ||
da40d9d4 BH |
1482 | /* Start things up */ |
1483 | err = ftgmac100_init_all(priv, false); | |
1484 | if (err) { | |
1485 | netdev_err(netdev, "Failed to allocate packet buffers\n"); | |
1486 | goto err_alloc; | |
1487 | } | |
08c9c126 | 1488 | |
da40d9d4 BH |
1489 | if (netdev->phydev) { |
1490 | /* If we have a PHY, start polling */ | |
bd466c3f | 1491 | phy_start(netdev->phydev); |
da40d9d4 BH |
1492 | } else if (priv->use_ncsi) { |
1493 | /* If using NC-SI, set our carrier on and start the stack */ | |
bd466c3f | 1494 | netif_carrier_on(netdev); |
69785b79 | 1495 | |
da40d9d4 | 1496 | /* Start the NCSI device */ |
bd466c3f GS |
1497 | err = ncsi_start_dev(priv->ndev); |
1498 | if (err) | |
1499 | goto err_ncsi; | |
1500 | } | |
1501 | ||
69785b79 PYC |
1502 | return 0; |
1503 | ||
da40d9d4 | 1504 | err_ncsi: |
bd466c3f GS |
1505 | napi_disable(&priv->napi); |
1506 | netif_stop_queue(netdev); | |
da40d9d4 BH |
1507 | err_alloc: |
1508 | ftgmac100_free_buffers(priv); | |
60b28a11 | 1509 | free_irq(netdev->irq, netdev); |
da40d9d4 | 1510 | err_irq: |
81f1eca6 | 1511 | netif_napi_del(&priv->napi); |
da40d9d4 | 1512 | err_hw: |
81f1eca6 | 1513 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); |
87d18757 | 1514 | ftgmac100_free_rings(priv); |
69785b79 PYC |
1515 | return err; |
1516 | } | |
1517 | ||
1518 | static int ftgmac100_stop(struct net_device *netdev) | |
1519 | { | |
1520 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1521 | ||
855944ce BH |
1522 | /* Note about the reset task: We are called with the rtnl lock |
1523 | * held, so we are synchronized against the core of the reset | |
1524 | * task. We must not try to synchronously cancel it otherwise | |
1525 | * we can deadlock. But since it will test for netif_running() | |
1526 | * which has already been cleared by the net core, we don't | |
1527 | * anything special to do. | |
1528 | */ | |
1529 | ||
69785b79 PYC |
1530 | /* disable all interrupts */ |
1531 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
1532 | ||
1533 | netif_stop_queue(netdev); | |
1534 | napi_disable(&priv->napi); | |
b8dbecff | 1535 | netif_napi_del(&priv->napi); |
bd466c3f GS |
1536 | if (netdev->phydev) |
1537 | phy_stop(netdev->phydev); | |
2c15f25b GS |
1538 | else if (priv->use_ncsi) |
1539 | ncsi_stop_dev(priv->ndev); | |
69785b79 PYC |
1540 | |
1541 | ftgmac100_stop_hw(priv); | |
60b28a11 | 1542 | free_irq(netdev->irq, netdev); |
69785b79 | 1543 | ftgmac100_free_buffers(priv); |
87d18757 | 1544 | ftgmac100_free_rings(priv); |
69785b79 PYC |
1545 | |
1546 | return 0; | |
1547 | } | |
1548 | ||
69785b79 PYC |
1549 | /* optional */ |
1550 | static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
1551 | { | |
bd466c3f GS |
1552 | if (!netdev->phydev) |
1553 | return -ENXIO; | |
1554 | ||
b3c40adc | 1555 | return phy_mii_ioctl(netdev->phydev, ifr, cmd); |
69785b79 PYC |
1556 | } |
1557 | ||
d3ca8fb1 BH |
1558 | static void ftgmac100_tx_timeout(struct net_device *netdev) |
1559 | { | |
1560 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1561 | ||
1562 | /* Disable all interrupts */ | |
1563 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
1564 | ||
1565 | /* Do the reset outside of interrupt context */ | |
1566 | schedule_work(&priv->reset_task); | |
1567 | } | |
1568 | ||
0fb99688 BH |
1569 | static int ftgmac100_set_features(struct net_device *netdev, |
1570 | netdev_features_t features) | |
1571 | { | |
1572 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1573 | netdev_features_t changed = netdev->features ^ features; | |
1574 | ||
1575 | if (!netif_running(netdev)) | |
1576 | return 0; | |
1577 | ||
1578 | /* Update the vlan filtering bit */ | |
1579 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { | |
1580 | u32 maccr; | |
1581 | ||
1582 | maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); | |
1583 | if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) | |
1584 | maccr |= FTGMAC100_MACCR_RM_VLAN; | |
1585 | else | |
1586 | maccr &= ~FTGMAC100_MACCR_RM_VLAN; | |
1587 | iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); | |
1588 | } | |
1589 | ||
1590 | return 0; | |
1591 | } | |
1592 | ||
030d9828 BH |
1593 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1594 | static void ftgmac100_poll_controller(struct net_device *netdev) | |
1595 | { | |
1596 | unsigned long flags; | |
1597 | ||
1598 | local_irq_save(flags); | |
1599 | ftgmac100_interrupt(netdev->irq, netdev); | |
1600 | local_irq_restore(flags); | |
1601 | } | |
1602 | #endif | |
1603 | ||
69785b79 PYC |
1604 | static const struct net_device_ops ftgmac100_netdev_ops = { |
1605 | .ndo_open = ftgmac100_open, | |
1606 | .ndo_stop = ftgmac100_stop, | |
1607 | .ndo_start_xmit = ftgmac100_hard_start_xmit, | |
113ce107 | 1608 | .ndo_set_mac_address = ftgmac100_set_mac_addr, |
69785b79 PYC |
1609 | .ndo_validate_addr = eth_validate_addr, |
1610 | .ndo_do_ioctl = ftgmac100_do_ioctl, | |
d3ca8fb1 | 1611 | .ndo_tx_timeout = ftgmac100_tx_timeout, |
f48b3c0d | 1612 | .ndo_set_rx_mode = ftgmac100_set_rx_mode, |
0fb99688 | 1613 | .ndo_set_features = ftgmac100_set_features, |
030d9828 BH |
1614 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1615 | .ndo_poll_controller = ftgmac100_poll_controller, | |
1616 | #endif | |
51564585 SMJ |
1617 | .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid, |
1618 | .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid, | |
69785b79 PYC |
1619 | }; |
1620 | ||
eb418184 GS |
1621 | static int ftgmac100_setup_mdio(struct net_device *netdev) |
1622 | { | |
1623 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1624 | struct platform_device *pdev = to_platform_device(priv->dev); | |
abcc3eb0 BH |
1625 | int phy_intf = PHY_INTERFACE_MODE_RGMII; |
1626 | struct device_node *np = pdev->dev.of_node; | |
eb418184 | 1627 | int i, err = 0; |
e07dc63b | 1628 | u32 reg; |
eb418184 GS |
1629 | |
1630 | /* initialize mdio bus */ | |
1631 | priv->mii_bus = mdiobus_alloc(); | |
1632 | if (!priv->mii_bus) | |
1633 | return -EIO; | |
1634 | ||
78d28543 | 1635 | if (priv->is_aspeed) { |
e07dc63b JS |
1636 | /* This driver supports the old MDIO interface */ |
1637 | reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); | |
1638 | reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; | |
1639 | iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); | |
1640 | }; | |
1641 | ||
abcc3eb0 BH |
1642 | /* Get PHY mode from device-tree */ |
1643 | if (np) { | |
1644 | /* Default to RGMII. It's a gigabit part after all */ | |
1645 | phy_intf = of_get_phy_mode(np); | |
1646 | if (phy_intf < 0) | |
1647 | phy_intf = PHY_INTERFACE_MODE_RGMII; | |
1648 | ||
1649 | /* Aspeed only supports these. I don't know about other IP | |
1650 | * block vendors so I'm going to just let them through for | |
1651 | * now. Note that this is only a warning if for some obscure | |
1652 | * reason the DT really means to lie about it or it's a newer | |
1653 | * part we don't know about. | |
1654 | * | |
1655 | * On the Aspeed SoC there are additionally straps and SCU | |
1656 | * control bits that could tell us what the interface is | |
1657 | * (or allow us to configure it while the IP block is held | |
1658 | * in reset). For now I chose to keep this driver away from | |
1659 | * those SoC specific bits and assume the device-tree is | |
1660 | * right and the SCU has been configured properly by pinmux | |
1661 | * or the firmware. | |
1662 | */ | |
1663 | if (priv->is_aspeed && | |
1664 | phy_intf != PHY_INTERFACE_MODE_RMII && | |
1665 | phy_intf != PHY_INTERFACE_MODE_RGMII && | |
1666 | phy_intf != PHY_INTERFACE_MODE_RGMII_ID && | |
1667 | phy_intf != PHY_INTERFACE_MODE_RGMII_RXID && | |
1668 | phy_intf != PHY_INTERFACE_MODE_RGMII_TXID) { | |
1669 | netdev_warn(netdev, | |
1670 | "Unsupported PHY mode %s !\n", | |
1671 | phy_modes(phy_intf)); | |
1672 | } | |
1673 | } | |
1674 | ||
eb418184 GS |
1675 | priv->mii_bus->name = "ftgmac100_mdio"; |
1676 | snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", | |
1677 | pdev->name, pdev->id); | |
d57b9db1 | 1678 | priv->mii_bus->parent = priv->dev; |
eb418184 GS |
1679 | priv->mii_bus->priv = priv->netdev; |
1680 | priv->mii_bus->read = ftgmac100_mdiobus_read; | |
1681 | priv->mii_bus->write = ftgmac100_mdiobus_write; | |
1682 | ||
1683 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
1684 | priv->mii_bus->irq[i] = PHY_POLL; | |
1685 | ||
1686 | err = mdiobus_register(priv->mii_bus); | |
1687 | if (err) { | |
1688 | dev_err(priv->dev, "Cannot register MDIO bus!\n"); | |
1689 | goto err_register_mdiobus; | |
1690 | } | |
1691 | ||
abcc3eb0 | 1692 | err = ftgmac100_mii_probe(priv, phy_intf); |
eb418184 GS |
1693 | if (err) { |
1694 | dev_err(priv->dev, "MII Probe failed!\n"); | |
1695 | goto err_mii_probe; | |
1696 | } | |
1697 | ||
1698 | return 0; | |
1699 | ||
1700 | err_mii_probe: | |
1701 | mdiobus_unregister(priv->mii_bus); | |
1702 | err_register_mdiobus: | |
1703 | mdiobus_free(priv->mii_bus); | |
1704 | return err; | |
1705 | } | |
1706 | ||
1707 | static void ftgmac100_destroy_mdio(struct net_device *netdev) | |
1708 | { | |
1709 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1710 | ||
1711 | if (!netdev->phydev) | |
1712 | return; | |
1713 | ||
1714 | phy_disconnect(netdev->phydev); | |
1715 | mdiobus_unregister(priv->mii_bus); | |
1716 | mdiobus_free(priv->mii_bus); | |
1717 | } | |
1718 | ||
bd466c3f GS |
1719 | static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) |
1720 | { | |
1721 | if (unlikely(nd->state != ncsi_dev_state_functional)) | |
1722 | return; | |
1723 | ||
87975a01 JS |
1724 | netdev_dbg(nd->dev, "NCSI interface %s\n", |
1725 | nd->link_up ? "up" : "down"); | |
bd466c3f GS |
1726 | } |
1727 | ||
4b70c62b JS |
1728 | static void ftgmac100_setup_clk(struct ftgmac100 *priv) |
1729 | { | |
1730 | priv->clk = devm_clk_get(priv->dev, NULL); | |
1731 | if (IS_ERR(priv->clk)) | |
1732 | return; | |
1733 | ||
1734 | clk_prepare_enable(priv->clk); | |
1735 | ||
1736 | /* Aspeed specifies a 100MHz clock is required for up to | |
1737 | * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz | |
1738 | * is sufficient | |
1739 | */ | |
1740 | clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ : | |
1741 | FTGMAC_100MHZ); | |
1742 | } | |
1743 | ||
69785b79 PYC |
1744 | static int ftgmac100_probe(struct platform_device *pdev) |
1745 | { | |
1746 | struct resource *res; | |
1747 | int irq; | |
1748 | struct net_device *netdev; | |
1749 | struct ftgmac100 *priv; | |
78d28543 | 1750 | struct device_node *np; |
bd466c3f | 1751 | int err = 0; |
69785b79 PYC |
1752 | |
1753 | if (!pdev) | |
1754 | return -ENODEV; | |
1755 | ||
1756 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1757 | if (!res) | |
1758 | return -ENXIO; | |
1759 | ||
1760 | irq = platform_get_irq(pdev, 0); | |
1761 | if (irq < 0) | |
1762 | return irq; | |
1763 | ||
1764 | /* setup net_device */ | |
1765 | netdev = alloc_etherdev(sizeof(*priv)); | |
1766 | if (!netdev) { | |
1767 | err = -ENOMEM; | |
1768 | goto err_alloc_etherdev; | |
1769 | } | |
1770 | ||
1771 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1772 | ||
7ad24ea4 | 1773 | netdev->ethtool_ops = &ftgmac100_ethtool_ops; |
69785b79 | 1774 | netdev->netdev_ops = &ftgmac100_netdev_ops; |
d3ca8fb1 | 1775 | netdev->watchdog_timeo = 5 * HZ; |
69785b79 PYC |
1776 | |
1777 | platform_set_drvdata(pdev, netdev); | |
1778 | ||
1779 | /* setup private data */ | |
1780 | priv = netdev_priv(netdev); | |
1781 | priv->netdev = netdev; | |
1782 | priv->dev = &pdev->dev; | |
855944ce | 1783 | INIT_WORK(&priv->reset_task, ftgmac100_reset_task); |
69785b79 | 1784 | |
69785b79 PYC |
1785 | /* map io memory */ |
1786 | priv->res = request_mem_region(res->start, resource_size(res), | |
1787 | dev_name(&pdev->dev)); | |
1788 | if (!priv->res) { | |
1789 | dev_err(&pdev->dev, "Could not reserve memory region\n"); | |
1790 | err = -ENOMEM; | |
1791 | goto err_req_mem; | |
1792 | } | |
1793 | ||
1794 | priv->base = ioremap(res->start, resource_size(res)); | |
1795 | if (!priv->base) { | |
1796 | dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); | |
1797 | err = -EIO; | |
1798 | goto err_ioremap; | |
1799 | } | |
1800 | ||
60b28a11 | 1801 | netdev->irq = irq; |
69785b79 | 1802 | |
7c8e5141 BH |
1803 | /* Enable pause */ |
1804 | priv->tx_pause = true; | |
1805 | priv->rx_pause = true; | |
1806 | priv->aneg_pause = true; | |
1807 | ||
113ce107 | 1808 | /* MAC address from chip or random one */ |
ba1b1234 | 1809 | ftgmac100_initial_mac(priv); |
113ce107 | 1810 | |
78d28543 BH |
1811 | np = pdev->dev.of_node; |
1812 | if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || | |
1813 | of_device_is_compatible(np, "aspeed,ast2500-mac"))) { | |
2a0ab8eb JS |
1814 | priv->rxdes0_edorr_mask = BIT(30); |
1815 | priv->txdes0_edotr_mask = BIT(30); | |
78d28543 | 1816 | priv->is_aspeed = true; |
2a0ab8eb JS |
1817 | } else { |
1818 | priv->rxdes0_edorr_mask = BIT(15); | |
1819 | priv->txdes0_edotr_mask = BIT(15); | |
1820 | } | |
1821 | ||
78d28543 | 1822 | if (np && of_get_property(np, "use-ncsi", NULL)) { |
bd466c3f GS |
1823 | if (!IS_ENABLED(CONFIG_NET_NCSI)) { |
1824 | dev_err(&pdev->dev, "NCSI stack not enabled\n"); | |
1825 | goto err_ncsi_dev; | |
1826 | } | |
1827 | ||
1828 | dev_info(&pdev->dev, "Using NCSI interface\n"); | |
1829 | priv->use_ncsi = true; | |
1830 | priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); | |
1831 | if (!priv->ndev) | |
1832 | goto err_ncsi_dev; | |
1833 | } else { | |
1834 | priv->use_ncsi = false; | |
1835 | err = ftgmac100_setup_mdio(netdev); | |
1836 | if (err) | |
1837 | goto err_setup_mdio; | |
1838 | } | |
1839 | ||
4b70c62b JS |
1840 | if (priv->is_aspeed) |
1841 | ftgmac100_setup_clk(priv); | |
1842 | ||
52d9138f BH |
1843 | /* Default ring sizes */ |
1844 | priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES; | |
1845 | priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES; | |
1846 | ||
6aff0bf6 | 1847 | /* Base feature set */ |
8c3ed131 | 1848 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM | |
0fb99688 BH |
1849 | NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX | |
1850 | NETIF_F_HW_VLAN_CTAG_TX; | |
6aff0bf6 | 1851 | |
51564585 SMJ |
1852 | if (priv->use_ncsi) |
1853 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
1854 | ||
6aff0bf6 BH |
1855 | /* AST2400 doesn't have working HW checksum generation */ |
1856 | if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac"))) | |
8c3ed131 | 1857 | netdev->hw_features &= ~NETIF_F_HW_CSUM; |
6aff0bf6 | 1858 | if (np && of_get_property(np, "no-hw-checksum", NULL)) |
8c3ed131 BH |
1859 | netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM); |
1860 | netdev->features |= netdev->hw_features; | |
bd466c3f | 1861 | |
69785b79 PYC |
1862 | /* register network device */ |
1863 | err = register_netdev(netdev); | |
1864 | if (err) { | |
1865 | dev_err(&pdev->dev, "Failed to register netdev\n"); | |
1866 | goto err_register_netdev; | |
1867 | } | |
1868 | ||
60b28a11 | 1869 | netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base); |
69785b79 | 1870 | |
69785b79 PYC |
1871 | return 0; |
1872 | ||
bd466c3f | 1873 | err_ncsi_dev: |
69785b79 | 1874 | err_register_netdev: |
eb418184 GS |
1875 | ftgmac100_destroy_mdio(netdev); |
1876 | err_setup_mdio: | |
69785b79 PYC |
1877 | iounmap(priv->base); |
1878 | err_ioremap: | |
1879 | release_resource(priv->res); | |
1880 | err_req_mem: | |
69785b79 PYC |
1881 | free_netdev(netdev); |
1882 | err_alloc_etherdev: | |
1883 | return err; | |
1884 | } | |
1885 | ||
be12502e | 1886 | static int ftgmac100_remove(struct platform_device *pdev) |
69785b79 PYC |
1887 | { |
1888 | struct net_device *netdev; | |
1889 | struct ftgmac100 *priv; | |
1890 | ||
1891 | netdev = platform_get_drvdata(pdev); | |
1892 | priv = netdev_priv(netdev); | |
1893 | ||
1894 | unregister_netdev(netdev); | |
855944ce | 1895 | |
4b70c62b JS |
1896 | clk_disable_unprepare(priv->clk); |
1897 | ||
855944ce BH |
1898 | /* There's a small chance the reset task will have been re-queued, |
1899 | * during stop, make sure it's gone before we free the structure. | |
1900 | */ | |
1901 | cancel_work_sync(&priv->reset_task); | |
1902 | ||
eb418184 | 1903 | ftgmac100_destroy_mdio(netdev); |
69785b79 PYC |
1904 | |
1905 | iounmap(priv->base); | |
1906 | release_resource(priv->res); | |
1907 | ||
1908 | netif_napi_del(&priv->napi); | |
69785b79 PYC |
1909 | free_netdev(netdev); |
1910 | return 0; | |
1911 | } | |
1912 | ||
bb168e2e GS |
1913 | static const struct of_device_id ftgmac100_of_match[] = { |
1914 | { .compatible = "faraday,ftgmac100" }, | |
1915 | { } | |
1916 | }; | |
1917 | MODULE_DEVICE_TABLE(of, ftgmac100_of_match); | |
1918 | ||
69785b79 | 1919 | static struct platform_driver ftgmac100_driver = { |
bb168e2e | 1920 | .probe = ftgmac100_probe, |
be12502e | 1921 | .remove = ftgmac100_remove, |
bb168e2e GS |
1922 | .driver = { |
1923 | .name = DRV_NAME, | |
1924 | .of_match_table = ftgmac100_of_match, | |
69785b79 PYC |
1925 | }, |
1926 | }; | |
14f645d0 | 1927 | module_platform_driver(ftgmac100_driver); |
69785b79 PYC |
1928 | |
1929 | MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); | |
1930 | MODULE_DESCRIPTION("FTGMAC100 driver"); | |
1931 | MODULE_LICENSE("GPL"); |