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sfc: Remove duplicate argument
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / freescale / enetc / enetc_pf.c
CommitLineData
d4fd0404
CM		 1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/* Copyright 2017-2019 NXP */
3
975d183e 4#include <linux/mdio.h>
d4fd0404 5#include <linux/module.h>
6517798d 6#include <linux/fsl/enetc_mdio.h>
d4fd0404
CM		 7#include <linux/of_mdio.h>
8#include <linux/of_net.h>
9#include "enetc_pf.h"
10
d4fd0404 11#define ENETC_DRV_NAME_STR "ENETC PF driver"
d4fd0404
CM		 12
13static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
14{
15 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
16 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
17
18 *(u32 *)addr = upper;
19 *(u16 *)(addr + 4) = lower;
20}
21
22static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
23 const u8 *addr)
24{
25 u32 upper = *(const u32 *)addr;
26 u16 lower = *(const u16 *)(addr + 4);
27
28 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
29 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
30}
31
32static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
33{
34 struct enetc_ndev_priv *priv = netdev_priv(ndev);
35 struct sockaddr *saddr = addr;
36
37 if (!is_valid_ether_addr(saddr->sa_data))
38 return -EADDRNOTAVAIL;
39
40 memcpy(ndev->dev_addr, saddr->sa_data, ndev->addr_len);
41 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
42
43 return 0;
44}
45
46static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
47{
48 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
49
50 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
51 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
52}
53
d4fd0404
CM		 54static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
55{
56 pf->vlan_promisc_simap |= BIT(si_idx);
57 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
58}
59
60static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
61{
62 pf->vlan_promisc_simap &= ~BIT(si_idx);
63 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
64}
65
66static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
67{
68 u32 val = 0;
69
70 if (vlan)
71 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
72
73 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
74}
75
76static int enetc_mac_addr_hash_idx(const u8 *addr)
77{
78 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
79 u64 mask = 0;
80 int res = 0;
81 int i;
82
83 for (i = 0; i < 8; i++)
84 mask |= BIT_ULL(i * 6);
85
86 for (i = 0; i < 6; i++)
87 res |= (hweight64(fold & (mask << i)) & 0x1) << i;
88
89 return res;
90}
91
92static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
93{
94 filter->mac_addr_cnt = 0;
95
96 bitmap_zero(filter->mac_hash_table,
97 ENETC_MADDR_HASH_TBL_SZ);
98}
99
100static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
101 const unsigned char *addr)
102{
103 /* add exact match addr */
104 ether_addr_copy(filter->mac_addr, addr);
105 filter->mac_addr_cnt++;
106}
107
108static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
109 const unsigned char *addr)
110{
111 int idx = enetc_mac_addr_hash_idx(addr);
112
113 /* add hash table entry */
114 __set_bit(idx, filter->mac_hash_table);
115 filter->mac_addr_cnt++;
116}
117
118static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
119{
120 bool err = si->errata & ENETC_ERR_UCMCSWP;
121
122 if (type == UC) {
123 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
124 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
125 } else { /* MC */
126 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
127 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
128 }
129}
130
131static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
e366a392 132 unsigned long hash)
d4fd0404
CM		 133{
134 bool err = si->errata & ENETC_ERR_UCMCSWP;
135
136 if (type == UC) {
e366a392
VO		 137 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
138 lower_32_bits(hash));
139 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
140 upper_32_bits(hash));
d4fd0404 141 } else { /* MC */
e366a392
VO		 142 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
143 lower_32_bits(hash));
144 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
145 upper_32_bits(hash));
d4fd0404
CM		 146 }
147}
148
149static void enetc_sync_mac_filters(struct enetc_pf *pf)
150{
151 struct enetc_mac_filter *f = pf->mac_filter;
152 struct enetc_si *si = pf->si;
153 int i, pos;
154
155 pos = EMETC_MAC_ADDR_FILT_RES;
156
157 for (i = 0; i < MADDR_TYPE; i++, f++) {
158 bool em = (f->mac_addr_cnt == 1) && (i == UC);
159 bool clear = !f->mac_addr_cnt;
160
161 if (clear) {
162 if (i == UC)
163 enetc_clear_mac_flt_entry(si, pos);
164
165 enetc_clear_mac_ht_flt(si, 0, i);
166 continue;
167 }
168
169 /* exact match filter */
170 if (em) {
171 int err;
172
173 enetc_clear_mac_ht_flt(si, 0, UC);
174
175 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
176 BIT(0));
177 if (!err)
178 continue;
179
180 /* fallback to HT filtering */
181 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
182 err);
183 }
184
185 /* hash table filter, clear EM filter for UC entries */
186 if (i == UC)
187 enetc_clear_mac_flt_entry(si, pos);
188
e366a392 189 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
d4fd0404
CM		 190 }
191}
192
193static void enetc_pf_set_rx_mode(struct net_device *ndev)
194{
195 struct enetc_ndev_priv *priv = netdev_priv(ndev);
196 struct enetc_pf *pf = enetc_si_priv(priv->si);
197 struct enetc_hw *hw = &priv->si->hw;
198 bool uprom = false, mprom = false;
199 struct enetc_mac_filter *filter;
200 struct netdev_hw_addr *ha;
201 u32 psipmr = 0;
202 bool em;
203
204 if (ndev->flags & IFF_PROMISC) {
205 /* enable promisc mode for SI0 (PF) */
206 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
207 uprom = true;
208 mprom = true;
d4fd0404
CM		 209 } else if (ndev->flags & IFF_ALLMULTI) {
210 /* enable multi cast promisc mode for SI0 (PF) */
211 psipmr = ENETC_PSIPMR_SET_MP(0);
212 mprom = true;
213 }
214
215 /* first 2 filter entries belong to PF */
216 if (!uprom) {
217 /* Update unicast filters */
218 filter = &pf->mac_filter[UC];
219 enetc_reset_mac_addr_filter(filter);
220
221 em = (netdev_uc_count(ndev) == 1);
222 netdev_for_each_uc_addr(ha, ndev) {
223 if (em) {
224 enetc_add_mac_addr_em_filter(filter, ha->addr);
225 break;
226 }
227
228 enetc_add_mac_addr_ht_filter(filter, ha->addr);
229 }
230 }
231
232 if (!mprom) {
233 /* Update multicast filters */
234 filter = &pf->mac_filter[MC];
235 enetc_reset_mac_addr_filter(filter);
236
237 netdev_for_each_mc_addr(ha, ndev) {
238 if (!is_multicast_ether_addr(ha->addr))
239 continue;
240
241 enetc_add_mac_addr_ht_filter(filter, ha->addr);
242 }
243 }
244
245 if (!uprom || !mprom)
246 /* update PF entries */
247 enetc_sync_mac_filters(pf);
248
249 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
250 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
251 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
252}
253
254static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
110eccdb 255 unsigned long hash)
d4fd0404 256{
110eccdb
VO		 257 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
258 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
d4fd0404
CM		 259}
260
261static int enetc_vid_hash_idx(unsigned int vid)
262{
263 int res = 0;
264 int i;
265
266 for (i = 0; i < 6; i++)
267 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
268
269 return res;
270}
271
272static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
273{
274 int i;
275
276 if (rehash) {
277 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
278
279 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
280 int hidx = enetc_vid_hash_idx(i);
281
282 __set_bit(hidx, pf->vlan_ht_filter);
283 }
284 }
285
110eccdb 286 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
d4fd0404
CM		 287}
288
289static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
290{
291 struct enetc_ndev_priv *priv = netdev_priv(ndev);
292 struct enetc_pf *pf = enetc_si_priv(priv->si);
293 int idx;
294
d4fd0404
CM		 295 __set_bit(vid, pf->active_vlans);
296
297 idx = enetc_vid_hash_idx(vid);
298 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
299 enetc_sync_vlan_ht_filter(pf, false);
300
301 return 0;
302}
303
304static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
305{
306 struct enetc_ndev_priv *priv = netdev_priv(ndev);
307 struct enetc_pf *pf = enetc_si_priv(priv->si);
308
309 __clear_bit(vid, pf->active_vlans);
310 enetc_sync_vlan_ht_filter(pf, true);
311
d4fd0404
CM		 312 return 0;
313}
314
315static void enetc_set_loopback(struct net_device *ndev, bool en)
316{
317 struct enetc_ndev_priv *priv = netdev_priv(ndev);
318 struct enetc_hw *hw = &priv->si->hw;
319 u32 reg;
320
321 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
c76a9721 322 if (reg & ENETC_PM0_IFM_RG) {
d4fd0404
CM		 323 /* RGMII mode */
324 reg = (reg & ~ENETC_PM0_IFM_RLP) |
325 (en ? ENETC_PM0_IFM_RLP : 0);
326 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
327 } else {
328 /* assume SGMII mode */
329 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
330 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
331 (en ? ENETC_PM0_CMD_XGLP : 0);
332 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
333 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
334 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
335 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
336 }
337}
338
339static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
340{
341 struct enetc_ndev_priv *priv = netdev_priv(ndev);
342 struct enetc_pf *pf = enetc_si_priv(priv->si);
beb74ac8 343 struct enetc_vf_state *vf_state;
d4fd0404
CM		 344
345 if (vf >= pf->total_vfs)
346 return -EINVAL;
347
348 if (!is_valid_ether_addr(mac))
349 return -EADDRNOTAVAIL;
350
beb74ac8
CM		 351 vf_state = &pf->vf_state[vf];
352 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
d4fd0404
CM		 353 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
354 return 0;
355}
356
357static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
358 u8 qos, __be16 proto)
359{
360 struct enetc_ndev_priv *priv = netdev_priv(ndev);
361 struct enetc_pf *pf = enetc_si_priv(priv->si);
362
363 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
364 return -EOPNOTSUPP;
365
366 if (vf >= pf->total_vfs)
367 return -EINVAL;
368
369 if (proto != htons(ETH_P_8021Q))
370 /* only C-tags supported for now */
371 return -EPROTONOSUPPORT;
372
373 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
374 return 0;
375}
376
377static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
378{
379 struct enetc_ndev_priv *priv = netdev_priv(ndev);
380 struct enetc_pf *pf = enetc_si_priv(priv->si);
381 u32 cfgr;
382
383 if (vf >= pf->total_vfs)
384 return -EINVAL;
385
386 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
387 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
388 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
389
390 return 0;
391}
392
393static void enetc_port_setup_primary_mac_address(struct enetc_si *si)
394{
395 unsigned char mac_addr[MAX_ADDR_LEN];
396 struct enetc_pf *pf = enetc_si_priv(si);
397 struct enetc_hw *hw = &si->hw;
398 int i;
399
400 /* check MAC addresses for PF and all VFs, if any is 0 set it ro rand */
401 for (i = 0; i < pf->total_vfs + 1; i++) {
402 enetc_pf_get_primary_mac_addr(hw, i, mac_addr);
403 if (!is_zero_ether_addr(mac_addr))
404 continue;
405 eth_random_addr(mac_addr);
406 dev_info(&si->pdev->dev, "no MAC address specified for SI%d, using %pM\n",
407 i, mac_addr);
408 enetc_pf_set_primary_mac_addr(hw, i, mac_addr);
409 }
410}
411
d382563f
CM		 412static void enetc_port_assign_rfs_entries(struct enetc_si *si)
413{
414 struct enetc_pf *pf = enetc_si_priv(si);
415 struct enetc_hw *hw = &si->hw;
416 int num_entries, vf_entries, i;
417 u32 val;
418
419 /* split RFS entries between functions */
420 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
421 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
422 vf_entries = num_entries / (pf->total_vfs + 1);
423
424 for (i = 0; i < pf->total_vfs; i++)
425 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
426 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
427 num_entries - vf_entries * pf->total_vfs);
428
429 /* enable RFS on port */
430 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
431}
432
d4fd0404
CM		 433static void enetc_port_si_configure(struct enetc_si *si)
434{
435 struct enetc_pf *pf = enetc_si_priv(si);
436 struct enetc_hw *hw = &si->hw;
437 int num_rings, i;
438 u32 val;
439
440 val = enetc_port_rd(hw, ENETC_PCAPR0);
441 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
442
443 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
444 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
445
446 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
447 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
448 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
449
450 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
451 num_rings, ENETC_PF_NUM_RINGS);
452
453 num_rings = 0;
454 }
455
456 /* Add default one-time settings for SI0 (PF) */
457 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
458
459 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
460
461 if (num_rings)
462 num_rings -= ENETC_PF_NUM_RINGS;
463
464 /* Configure the SIs for each available VF */
465 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
466 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
467
468 if (num_rings) {
469 num_rings /= pf->total_vfs;
470 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
471 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
472 }
473
474 for (i = 0; i < pf->total_vfs; i++)
475 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
476
477 /* Port level VLAN settings */
478 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
479 enetc_port_wr(hw, ENETC_PVCLCTR, val);
480 /* use outer tag for VLAN filtering */
481 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
482}
483
08f90fc9 484static void enetc_configure_port_mac(struct enetc_hw *hw)
d4fd0404
CM		 485{
486 enetc_port_wr(hw, ENETC_PM0_MAXFRM,
487 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
488
489 enetc_port_wr(hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
490 enetc_port_wr(hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE);
491
492 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
08f90fc9 493 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
d4fd0404
CM		 494
495 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
08f90fc9 496 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
1b2395df
AM		 497
498 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
499 * and may lead to RX lock-up under traffic. Set it to 1 instead,
500 * as recommended by the hardware team.
501 */
502 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
08f90fc9
CM		 503}
504
505static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
506{
c76a9721
VO		 507 u32 val;
508
509 if (phy_interface_mode_is_rgmii(phy_mode)) {
510 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
511 val &= ~ENETC_PM0_IFM_EN_AUTO;
512 val &= ENETC_PM0_IFM_IFMODE_MASK;
513 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
514 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
515 }
07095c02 516
c76a9721
VO		 517 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
518 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
519 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
520 }
71b77a7a
CM		 521}
522
523static void enetc_mac_enable(struct enetc_hw *hw, bool en)
524{
525 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
08f90fc9 526
71b77a7a
CM		 527 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
528 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
08f90fc9 529
71b77a7a
CM		 530 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
531 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
d4fd0404
CM		 532}
533
534static void enetc_configure_port_pmac(struct enetc_hw *hw)
535{
536 u32 temp;
537
538 /* Set pMAC step lock */
539 temp = enetc_port_rd(hw, ENETC_PFPMR);
540 enetc_port_wr(hw, ENETC_PFPMR,
541 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
542
543 temp = enetc_port_rd(hw, ENETC_MMCSR);
544 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
545}
546
547static void enetc_configure_port(struct enetc_pf *pf)
548{
d382563f 549 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
d4fd0404
CM		 550 struct enetc_hw *hw = &pf->si->hw;
551
552 enetc_configure_port_pmac(hw);
553
08f90fc9 554 enetc_configure_port_mac(hw);
d4fd0404
CM		 555
556 enetc_port_si_configure(pf->si);
557
d382563f
CM		 558 /* set up hash key */
559 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
560 enetc_set_rss_key(hw, hash_key);
561
562 /* split up RFS entries */
563 enetc_port_assign_rfs_entries(pf->si);
564
d4fd0404
CM		 565 /* fix-up primary MAC addresses, if not set already */
566 enetc_port_setup_primary_mac_address(pf->si);
567
568 /* enforce VLAN promisc mode for all SIs */
569 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
570 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
571
572 enetc_port_wr(hw, ENETC_PSIPMR, 0);
573
574 /* enable port */
575 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
576}
577
beb74ac8
CM		 578/* Messaging */
579static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
580 int vf_id)
581{
582 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
583 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
584 struct enetc_msg_cmd_set_primary_mac *cmd;
585 struct device *dev = &pf->si->pdev->dev;
586 u16 cmd_id;
587 char *addr;
588
589 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
590 cmd_id = cmd->header.id;
591 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
592 return ENETC_MSG_CMD_STATUS_FAIL;
593
594 addr = cmd->mac.sa_data;
595 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
596 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
597 vf_id);
598 else
599 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
600
601 return ENETC_MSG_CMD_STATUS_OK;
602}
603
604void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
605{
606 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
607 struct device *dev = &pf->si->pdev->dev;
608 struct enetc_msg_cmd_header *cmd_hdr;
609 u16 cmd_type;
610
611 *status = ENETC_MSG_CMD_STATUS_OK;
612 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
613 cmd_type = cmd_hdr->type;
614
615 switch (cmd_type) {
616 case ENETC_MSG_CMD_MNG_MAC:
617 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
618 break;
619 default:
620 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
621 cmd_type);
622 }
623}
624
d4fd0404
CM		 625#ifdef CONFIG_PCI_IOV
626static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
627{
628 struct enetc_si *si = pci_get_drvdata(pdev);
629 struct enetc_pf *pf = enetc_si_priv(si);
630 int err;
631
632 if (!num_vfs) {
beb74ac8
CM		 633 enetc_msg_psi_free(pf);
634 kfree(pf->vf_state);
d4fd0404
CM		 635 pf->num_vfs = 0;
636 pci_disable_sriov(pdev);
637 } else {
638 pf->num_vfs = num_vfs;
639
beb74ac8
CM		 640 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
641 GFP_KERNEL);
642 if (!pf->vf_state) {
643 pf->num_vfs = 0;
644 return -ENOMEM;
645 }
646
647 err = enetc_msg_psi_init(pf);
648 if (err) {
649 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
650 goto err_msg_psi;
651 }
652
d4fd0404
CM		 653 err = pci_enable_sriov(pdev, num_vfs);
654 if (err) {
655 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
656 goto err_en_sriov;
657 }
658 }
659
660 return num_vfs;
661
662err_en_sriov:
beb74ac8
CM		 663 enetc_msg_psi_free(pf);
664err_msg_psi:
665 kfree(pf->vf_state);
d4fd0404
CM		 666 pf->num_vfs = 0;
667
668 return err;
669}
670#else
671#define enetc_sriov_configure(pdev, num_vfs) (void)0
672#endif
673
674static int enetc_pf_set_features(struct net_device *ndev,
675 netdev_features_t features)
676{
677 netdev_features_t changed = ndev->features ^ features;
678 struct enetc_ndev_priv *priv = netdev_priv(ndev);
679
7070eea5
VO		 680 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
681 struct enetc_pf *pf = enetc_si_priv(priv->si);
682
683 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
684 enetc_disable_si_vlan_promisc(pf, 0);
685 else
686 enetc_enable_si_vlan_promisc(pf, 0);
687 }
688
d4fd0404
CM		 689 if (changed & NETIF_F_LOOPBACK)
690 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
691
d382563f 692 return enetc_set_features(ndev, features);
d4fd0404
CM		 693}
694
695static const struct net_device_ops enetc_ndev_ops = {
696 .ndo_open = enetc_open,
697 .ndo_stop = enetc_close,
698 .ndo_start_xmit = enetc_xmit,
699 .ndo_get_stats = enetc_get_stats,
700 .ndo_set_mac_address = enetc_pf_set_mac_addr,
701 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
702 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
703 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
704 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
705 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
706 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
707 .ndo_set_features = enetc_pf_set_features,
d3982312 708 .ndo_do_ioctl = enetc_ioctl,
cbe9e835 709 .ndo_setup_tc = enetc_setup_tc,
d1b15102 710 .ndo_bpf = enetc_setup_bpf,
9d2b68cc 711 .ndo_xdp_xmit = enetc_xdp_xmit,
d4fd0404
CM		 712};
713
714static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
715 const struct net_device_ops *ndev_ops)
716{
717 struct enetc_ndev_priv *priv = netdev_priv(ndev);
718
719 SET_NETDEV_DEV(ndev, &si->pdev->dev);
720 priv->ndev = ndev;
721 priv->si = si;
722 priv->dev = &si->pdev->dev;
723 si->ndev = ndev;
724
725 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
726 ndev->netdev_ops = ndev_ops;
727 enetc_set_ethtool_ops(ndev);
728 ndev->watchdog_timeo = 5 * HZ;
729 ndev->max_mtu = ENETC_MAX_MTU;
730
82728b91 731 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
d4fd0404 732 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
7070eea5 733 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK;
82728b91 734 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
d4fd0404 735 NETIF_F_HW_VLAN_CTAG_TX |
7070eea5 736 NETIF_F_HW_VLAN_CTAG_RX;
d4fd0404 737
d382563f
CM		 738 if (si->num_rss)
739 ndev->hw_features |= NETIF_F_RXHASH;
740
d4fd0404
CM		 741 ndev->priv_flags |= IFF_UNICAST_FLT;
742
2e47cb41
PL		 743 if (si->hw_features & ENETC_SI_F_QBV)
744 priv->active_offloads |= ENETC_F_QBV;
745
888ae5a3 746 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
79e49982
PL		 747 priv->active_offloads |= ENETC_F_QCI;
748 ndev->features |= NETIF_F_HW_TC;
749 ndev->hw_features |= NETIF_F_HW_TC;
79e49982
PL		 750 }
751
d4fd0404
CM		 752 /* pick up primary MAC address from SI */
753 enetc_get_primary_mac_addr(&si->hw, ndev->dev_addr);
754}
755
08f90fc9 756static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
6517798d
CM		 757{
758 struct device *dev = &pf->si->pdev->dev;
759 struct enetc_mdio_priv *mdio_priv;
6517798d
CM		 760 struct mii_bus *bus;
761 int err;
762
763 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
764 if (!bus)
765 return -ENOMEM;
766
767 bus->name = "Freescale ENETC MDIO Bus";
768 bus->read = enetc_mdio_read;
769 bus->write = enetc_mdio_write;
770 bus->parent = dev;
771 mdio_priv = bus->priv;
772 mdio_priv->hw = &pf->si->hw;
773 mdio_priv->mdio_base = ENETC_EMDIO_BASE;
774 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
775
6517798d
CM		 776 err = of_mdiobus_register(bus, np);
777 if (err) {
6517798d
CM		 778 dev_err(dev, "cannot register MDIO bus\n");
779 return err;
780 }
781
6517798d
CM		 782 pf->mdio = bus;
783
784 return 0;
785}
786
46456ccf 787static void enetc_mdio_remove(struct enetc_pf *pf)
6517798d
CM		 788{
789 if (pf->mdio)
790 mdiobus_unregister(pf->mdio);
791}
792
46456ccf 793static int enetc_imdio_create(struct enetc_pf *pf)
975d183e
MW		 794{
795 struct device *dev = &pf->si->pdev->dev;
796 struct enetc_mdio_priv *mdio_priv;
71b77a7a
CM		 797 struct lynx_pcs *pcs_lynx;
798 struct mdio_device *pcs;
975d183e
MW		 799 struct mii_bus *bus;
800 int err;
801
802 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
803 if (!bus)
804 return -ENOMEM;
805
806 bus->name = "Freescale ENETC internal MDIO Bus";
807 bus->read = enetc_mdio_read;
808 bus->write = enetc_mdio_write;
809 bus->parent = dev;
810 bus->phy_mask = ~0;
811 mdio_priv = bus->priv;
812 mdio_priv->hw = &pf->si->hw;
813 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
814 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
815
816 err = mdiobus_register(bus);
817 if (err) {
818 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
819 goto free_mdio_bus;
820 }
821
71b77a7a 822 pcs = mdio_device_create(bus, 0);
975d183e
MW		 823 if (IS_ERR(pcs)) {
824 err = PTR_ERR(pcs);
71b77a7a
CM		 825 dev_err(dev, "cannot create pcs (%d)\n", err);
826 goto unregister_mdiobus;
827 }
828
829 pcs_lynx = lynx_pcs_create(pcs);
830 if (!pcs_lynx) {
831 mdio_device_free(pcs);
832 err = -ENOMEM;
833 dev_err(dev, "cannot create lynx pcs (%d)\n", err);
975d183e
MW		 834 goto unregister_mdiobus;
835 }
836
837 pf->imdio = bus;
71b77a7a 838 pf->pcs = pcs_lynx;
975d183e
MW		 839
840 return 0;
841
842unregister_mdiobus:
843 mdiobus_unregister(bus);
844free_mdio_bus:
845 mdiobus_free(bus);
846 return err;
847}
848
849static void enetc_imdio_remove(struct enetc_pf *pf)
850{
71b77a7a
CM		 851 if (pf->pcs) {
852 mdio_device_free(pf->pcs->mdio);
853 lynx_pcs_destroy(pf->pcs);
854 }
975d183e
MW		 855 if (pf->imdio) {
856 mdiobus_unregister(pf->imdio);
857 mdiobus_free(pf->imdio);
858 }
859}
860
46456ccf
CM		 861static bool enetc_port_has_pcs(struct enetc_pf *pf)
862{
863 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
864 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
865 pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
866}
867
4560b2a3 868static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
46456ccf 869{
46456ccf
CM		 870 struct device_node *mdio_np;
871 int err;
872
4560b2a3 873 mdio_np = of_get_child_by_name(node, "mdio");
46456ccf
CM		 874 if (mdio_np) {
875 err = enetc_mdio_probe(pf, mdio_np);
876
877 of_node_put(mdio_np);
878 if (err)
879 return err;
880 }
881
882 if (enetc_port_has_pcs(pf)) {
883 err = enetc_imdio_create(pf);
884 if (err) {
885 enetc_mdio_remove(pf);
886 return err;
887 }
888 }
889
890 return 0;
891}
892
893static void enetc_mdiobus_destroy(struct enetc_pf *pf)
894{
895 enetc_mdio_remove(pf);
896 enetc_imdio_remove(pf);
897}
898
71b77a7a
CM		 899static void enetc_pl_mac_validate(struct phylink_config *config,
900 unsigned long *supported,
901 struct phylink_link_state *state)
975d183e 902{
71b77a7a
CM		 903 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
904
905 if (state->interface != PHY_INTERFACE_MODE_NA &&
906 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
907 state->interface != PHY_INTERFACE_MODE_SGMII &&
908 state->interface != PHY_INTERFACE_MODE_2500BASEX &&
909 state->interface != PHY_INTERFACE_MODE_USXGMII &&
910 !phy_interface_mode_is_rgmii(state->interface)) {
911 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
912 return;
913 }
975d183e 914
71b77a7a
CM		 915 phylink_set_port_modes(mask);
916 phylink_set(mask, Autoneg);
917 phylink_set(mask, Pause);
918 phylink_set(mask, Asym_Pause);
919 phylink_set(mask, 10baseT_Half);
920 phylink_set(mask, 10baseT_Full);
921 phylink_set(mask, 100baseT_Half);
922 phylink_set(mask, 100baseT_Full);
923 phylink_set(mask, 100baseT_Half);
924 phylink_set(mask, 1000baseT_Half);
925 phylink_set(mask, 1000baseT_Full);
926
927 if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
928 state->interface == PHY_INTERFACE_MODE_2500BASEX ||
929 state->interface == PHY_INTERFACE_MODE_USXGMII) {
930 phylink_set(mask, 2500baseT_Full);
931 phylink_set(mask, 2500baseX_Full);
932 }
933
934 bitmap_and(supported, supported, mask,
935 __ETHTOOL_LINK_MODE_MASK_NBITS);
936 bitmap_and(state->advertising, state->advertising, mask,
937 __ETHTOOL_LINK_MODE_MASK_NBITS);
938}
975d183e 939
71b77a7a
CM		 940static void enetc_pl_mac_config(struct phylink_config *config,
941 unsigned int mode,
942 const struct phylink_link_state *state)
943{
944 struct enetc_pf *pf = phylink_to_enetc_pf(config);
945 struct enetc_ndev_priv *priv;
975d183e 946
71b77a7a
CM		 947 enetc_mac_config(&pf->si->hw, state->interface);
948
949 priv = netdev_priv(pf->si->ndev);
950 if (pf->pcs)
951 phylink_set_pcs(priv->phylink, &pf->pcs->pcs);
975d183e
MW		 952}
953
c76a9721
VO		 954static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
955{
956 u32 old_val, val;
957
958 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
959
960 if (speed == SPEED_1000) {
961 val &= ~ENETC_PM0_IFM_SSP_MASK;
962 val |= ENETC_PM0_IFM_SSP_1000;
963 } else if (speed == SPEED_100) {
964 val &= ~ENETC_PM0_IFM_SSP_MASK;
965 val |= ENETC_PM0_IFM_SSP_100;
966 } else if (speed == SPEED_10) {
967 val &= ~ENETC_PM0_IFM_SSP_MASK;
968 val |= ENETC_PM0_IFM_SSP_10;
969 }
970
971 if (duplex == DUPLEX_FULL)
972 val |= ENETC_PM0_IFM_FULL_DPX;
973 else
974 val &= ~ENETC_PM0_IFM_FULL_DPX;
975
976 if (val == old_val)
977 return;
978
979 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
980}
981
71b77a7a
CM		 982static void enetc_pl_mac_link_up(struct phylink_config *config,
983 struct phy_device *phy, unsigned int mode,
984 phy_interface_t interface, int speed,
985 int duplex, bool tx_pause, bool rx_pause)
975d183e 986{
71b77a7a
CM		 987 struct enetc_pf *pf = phylink_to_enetc_pf(config);
988 struct enetc_ndev_priv *priv;
989
990 priv = netdev_priv(pf->si->ndev);
991 if (priv->active_offloads & ENETC_F_QBV)
992 enetc_sched_speed_set(priv, speed);
975d183e 993
c76a9721
VO		 994 if (!phylink_autoneg_inband(mode) &&
995 phy_interface_mode_is_rgmii(interface))
996 enetc_force_rgmii_mac(&pf->si->hw, speed, duplex);
997
71b77a7a 998 enetc_mac_enable(&pf->si->hw, true);
975d183e
MW		 999}
1000
71b77a7a
CM		 1001static void enetc_pl_mac_link_down(struct phylink_config *config,
1002 unsigned int mode,
1003 phy_interface_t interface)
975d183e 1004{
71b77a7a
CM		 1005 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1006
1007 enetc_mac_enable(&pf->si->hw, false);
975d183e
MW		 1008}
1009
71b77a7a
CM		 1010static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1011 .validate = enetc_pl_mac_validate,
1012 .mac_config = enetc_pl_mac_config,
1013 .mac_link_up = enetc_pl_mac_link_up,
1014 .mac_link_down = enetc_pl_mac_link_down,
1015};
1016
4560b2a3
AB		 1017static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1018 struct device_node *node)
975d183e 1019{
71b77a7a 1020 struct enetc_pf *pf = enetc_si_priv(priv->si);
71b77a7a
CM		 1021 struct phylink *phylink;
1022 int err;
1023
1024 pf->phylink_config.dev = &priv->ndev->dev;
1025 pf->phylink_config.type = PHYLINK_NETDEV;
1026
4560b2a3 1027 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
71b77a7a
CM		 1028 pf->if_mode, &enetc_mac_phylink_ops);
1029 if (IS_ERR(phylink)) {
1030 err = PTR_ERR(phylink);
1031 return err;
975d183e 1032 }
71b77a7a
CM		 1033
1034 priv->phylink = phylink;
1035
1036 return 0;
1037}
1038
1039static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1040{
1041 if (priv->phylink)
1042 phylink_destroy(priv->phylink);
c6dd6488
CM		 1043}
1044
07bf34a5
VO		 1045/* Initialize the entire shared memory for the flow steering entries
1046 * of this port (PF + VFs)
1047 */
1048static int enetc_init_port_rfs_memory(struct enetc_si *si)
1049{
1050 struct enetc_cmd_rfse rfse = {0};
1051 struct enetc_hw *hw = &si->hw;
1052 int num_rfs, i, err = 0;
1053 u32 val;
1054
1055 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1056 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1057
1058 for (i = 0; i < num_rfs; i++) {
1059 err = enetc_set_fs_entry(si, &rfse, i);
1060 if (err)
1061 break;
1062 }
1063
1064 return err;
1065}
1066
1067static int enetc_init_port_rss_memory(struct enetc_si *si)
1068{
1069 struct enetc_hw *hw = &si->hw;
1070 int num_rss, err;
1071 int *rss_table;
1072 u32 val;
1073
1074 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1075 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1076 if (!num_rss)
1077 return 0;
1078
1079 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1080 if (!rss_table)
1081 return -ENOMEM;
1082
1083 err = enetc_set_rss_table(si, rss_table, num_rss);
1084
1085 kfree(rss_table);
1086
1087 return err;
1088}
1089
d4fd0404
CM		 1090static int enetc_pf_probe(struct pci_dev *pdev,
1091 const struct pci_device_id *ent)
1092{
4560b2a3 1093 struct device_node *node = pdev->dev.of_node;
d4fd0404
CM		 1094 struct enetc_ndev_priv *priv;
1095 struct net_device *ndev;
1096 struct enetc_si *si;
1097 struct enetc_pf *pf;
1098 int err;
1099
d4fd0404
CM		 1100 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
1101 if (err) {
1102 dev_err(&pdev->dev, "PCI probing failed\n");
1103 return err;
1104 }
1105
1106 si = pci_get_drvdata(pdev);
1107 if (!si->hw.port || !si->hw.global) {
1108 err = -ENODEV;
1109 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1110 goto err_map_pf_space;
1111 }
1112
4b47c0b8
VO		 1113 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1114 &si->cbd_ring);
1115 if (err)
1116 goto err_setup_cbdr;
1117
1118 err = enetc_init_port_rfs_memory(si);
1119 if (err) {
1120 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1121 goto err_init_port_rfs;
1122 }
1123
1124 err = enetc_init_port_rss_memory(si);
1125 if (err) {
1126 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1127 goto err_init_port_rss;
1128 }
1129
3222b5b6 1130 if (node && !of_device_is_available(node)) {
3222b5b6
VO		 1131 dev_info(&pdev->dev, "device is disabled, skipping\n");
1132 err = -ENODEV;
1133 goto err_device_disabled;
1134 }
1135
d4fd0404
CM		 1136 pf = enetc_si_priv(si);
1137 pf->si = si;
1138 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1139
1140 enetc_configure_port(pf);
1141
1142 enetc_get_si_caps(si);
1143
1144 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1145 if (!ndev) {
1146 err = -ENOMEM;
1147 dev_err(&pdev->dev, "netdev creation failed\n");
1148 goto err_alloc_netdev;
1149 }
1150
1151 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1152
1153 priv = netdev_priv(ndev);
1154
1155 enetc_init_si_rings_params(priv);
1156
1157 err = enetc_alloc_si_resources(priv);
1158 if (err) {
1159 dev_err(&pdev->dev, "SI resource alloc failed\n");
1160 goto err_alloc_si_res;
1161 }
1162
c646d10d
VO		 1163 err = enetc_configure_si(priv);
1164 if (err) {
1165 dev_err(&pdev->dev, "Failed to configure SI\n");
1166 goto err_config_si;
1167 }
1168
d4fd0404
CM		 1169 err = enetc_alloc_msix(priv);
1170 if (err) {
1171 dev_err(&pdev->dev, "MSIX alloc failed\n");
1172 goto err_alloc_msix;
1173 }
1174
4560b2a3
AB		 1175 if (!of_get_phy_mode(node, &pf->if_mode)) {
1176 err = enetc_mdiobus_create(pf, node);
08f90fc9
CM		 1177 if (err)
1178 goto err_mdiobus_create;
1179
4560b2a3 1180 err = enetc_phylink_create(priv, node);
71b77a7a
CM		 1181 if (err)
1182 goto err_phylink_create;
08f90fc9 1183 }
975d183e 1184
d4fd0404
CM		 1185 err = register_netdev(ndev);
1186 if (err)
1187 goto err_reg_netdev;
1188
d4fd0404
CM		 1189 return 0;
1190
1191err_reg_netdev:
71b77a7a
CM		 1192 enetc_phylink_destroy(priv);
1193err_phylink_create:
08f90fc9
CM		 1194 enetc_mdiobus_destroy(pf);
1195err_mdiobus_create:
d4fd0404 1196 enetc_free_msix(priv);
c646d10d 1197err_config_si:
d4fd0404
CM		 1198err_alloc_msix:
1199 enetc_free_si_resources(priv);
1200err_alloc_si_res:
1201 si->ndev = NULL;
1202 free_netdev(ndev);
1203err_alloc_netdev:
4b47c0b8
VO		 1204err_init_port_rss:
1205err_init_port_rfs:
3222b5b6 1206err_device_disabled:
4b47c0b8
VO		 1207 enetc_teardown_cbdr(&si->cbd_ring);
1208err_setup_cbdr:
d4fd0404
CM		 1209err_map_pf_space:
1210 enetc_pci_remove(pdev);
1211
1212 return err;
1213}
1214
1215static void enetc_pf_remove(struct pci_dev *pdev)
1216{
1217 struct enetc_si *si = pci_get_drvdata(pdev);
1218 struct enetc_pf *pf = enetc_si_priv(si);
1219 struct enetc_ndev_priv *priv;
1220
08f90fc9 1221 priv = netdev_priv(si->ndev);
08f90fc9 1222
d4fd0404
CM		 1223 if (pf->num_vfs)
1224 enetc_sriov_configure(pdev, 0);
1225
d4fd0404
CM		 1226 unregister_netdev(si->ndev);
1227
3af409ca
VO		 1228 enetc_phylink_destroy(priv);
1229 enetc_mdiobus_destroy(pf);
1230
d4fd0404
CM		 1231 enetc_free_msix(priv);
1232
1233 enetc_free_si_resources(priv);
c54f042d 1234 enetc_teardown_cbdr(&si->cbd_ring);
d4fd0404
CM		 1235
1236 free_netdev(si->ndev);
1237
1238 enetc_pci_remove(pdev);
1239}
1240
1241static const struct pci_device_id enetc_pf_id_table[] = {
1242 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1243 { 0, } /* End of table. */
1244};
1245MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1246
1247static struct pci_driver enetc_pf_driver = {
1248 .name = KBUILD_MODNAME,
1249 .id_table = enetc_pf_id_table,
1250 .probe = enetc_pf_probe,
1251 .remove = enetc_pf_remove,
1252#ifdef CONFIG_PCI_IOV
1253 .sriov_configure = enetc_sriov_configure,
1254#endif
1255};
1256module_pci_driver(enetc_pf_driver);
1257
1258MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1259MODULE_LICENSE("Dual BSD/GPL");
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