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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/bitops.h> | |
6f501b17 SH |
41 | #include <linux/io.h> |
42 | #include <linux/irq.h> | |
196719ec | 43 | #include <linux/clk.h> |
ead73183 | 44 | #include <linux/platform_device.h> |
e6b043d5 | 45 | #include <linux/phy.h> |
5eb32bd0 | 46 | #include <linux/fec.h> |
ca2cc333 SG |
47 | #include <linux/of.h> |
48 | #include <linux/of_device.h> | |
49 | #include <linux/of_gpio.h> | |
50 | #include <linux/of_net.h> | |
b2bccee1 | 51 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 52 | |
080853af | 53 | #include <asm/cacheflush.h> |
196719ec | 54 | |
b5680e0b | 55 | #ifndef CONFIG_ARM |
1da177e4 LT |
56 | #include <asm/coldfire.h> |
57 | #include <asm/mcfsim.h> | |
196719ec | 58 | #endif |
6f501b17 | 59 | |
1da177e4 | 60 | #include "fec.h" |
1da177e4 | 61 | |
085e79ed | 62 | #if defined(CONFIG_ARM) |
196719ec SH |
63 | #define FEC_ALIGNMENT 0xf |
64 | #else | |
65 | #define FEC_ALIGNMENT 0x3 | |
66 | #endif | |
67 | ||
b5680e0b SG |
68 | #define DRIVER_NAME "fec" |
69 | ||
70 | /* Controller is ENET-MAC */ | |
71 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
72 | /* Controller needs driver to swap frame */ | |
73 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
74 | /* Controller uses gasket */ |
75 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
76 | /* Controller has GBIT support */ |
77 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
b5680e0b SG |
78 | |
79 | static struct platform_device_id fec_devtype[] = { | |
80 | { | |
0ca1e290 | 81 | /* keep it for coldfire */ |
b5680e0b SG |
82 | .name = DRIVER_NAME, |
83 | .driver_data = 0, | |
0ca1e290 SG |
84 | }, { |
85 | .name = "imx25-fec", | |
86 | .driver_data = FEC_QUIRK_USE_GASKET, | |
87 | }, { | |
88 | .name = "imx27-fec", | |
89 | .driver_data = 0, | |
b5680e0b SG |
90 | }, { |
91 | .name = "imx28-fec", | |
92 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
93 | }, { |
94 | .name = "imx6q-fec", | |
95 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT, | |
0ca1e290 SG |
96 | }, { |
97 | /* sentinel */ | |
98 | } | |
b5680e0b | 99 | }; |
0ca1e290 | 100 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 101 | |
ca2cc333 | 102 | enum imx_fec_type { |
a7dd3219 | 103 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
104 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
105 | IMX28_FEC, | |
230dec61 | 106 | IMX6Q_FEC, |
ca2cc333 SG |
107 | }; |
108 | ||
109 | static const struct of_device_id fec_dt_ids[] = { | |
110 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
111 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
112 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 113 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
ca2cc333 SG |
114 | { /* sentinel */ } |
115 | }; | |
116 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
117 | ||
49da97dc SG |
118 | static unsigned char macaddr[ETH_ALEN]; |
119 | module_param_array(macaddr, byte, NULL, 0); | |
120 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 121 | |
49da97dc | 122 | #if defined(CONFIG_M5272) |
1da177e4 LT |
123 | /* |
124 | * Some hardware gets it MAC address out of local flash memory. | |
125 | * if this is non-zero then assume it is the address to get MAC from. | |
126 | */ | |
127 | #if defined(CONFIG_NETtel) | |
128 | #define FEC_FLASHMAC 0xf0006006 | |
129 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
130 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
131 | #elif defined(CONFIG_CANCam) |
132 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
133 | #elif defined (CONFIG_M5272C3) |
134 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
135 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 136 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
137 | #else |
138 | #define FEC_FLASHMAC 0 | |
139 | #endif | |
43be6366 | 140 | #endif /* CONFIG_M5272 */ |
ead73183 | 141 | |
1da177e4 LT |
142 | /* The number of Tx and Rx buffers. These are allocated from the page |
143 | * pool. The code may assume these are power of two, so it it best | |
144 | * to keep them that size. | |
145 | * We don't need to allocate pages for the transmitter. We just use | |
146 | * the skbuffer directly. | |
147 | */ | |
148 | #define FEC_ENET_RX_PAGES 8 | |
149 | #define FEC_ENET_RX_FRSIZE 2048 | |
150 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
151 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
152 | #define FEC_ENET_TX_FRSIZE 2048 | |
153 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
154 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
155 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
156 | ||
562d2f8c | 157 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 158 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
159 | #endif |
160 | ||
22f6b860 | 161 | /* Interrupt events/masks. */ |
1da177e4 LT |
162 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
163 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
164 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
165 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
166 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
167 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
168 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
169 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
170 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
171 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
172 | ||
4bee1f9a WS |
173 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
174 | ||
1da177e4 LT |
175 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
176 | */ | |
177 | #define PKT_MAXBUF_SIZE 1518 | |
178 | #define PKT_MINBUF_SIZE 64 | |
179 | #define PKT_MAXBLR_SIZE 1520 | |
180 | ||
c7c83d1c XJ |
181 | /* This device has up to three irqs on some platforms */ |
182 | #define FEC_IRQ_NUM 3 | |
1da177e4 LT |
183 | |
184 | /* | |
6b265293 | 185 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
186 | * size bits. Other FEC hardware does not, so we need to take that into |
187 | * account when setting it. | |
188 | */ | |
562d2f8c | 189 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 190 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
191 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
192 | #else | |
193 | #define OPT_FRAME_SIZE 0 | |
194 | #endif | |
195 | ||
196 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
197 | * tx_bd_base always point to the base of the buffer descriptors. The | |
198 | * cur_rx and cur_tx point to the currently available buffer. | |
199 | * The dirty_tx tracks the current buffer that is being sent by the | |
200 | * controller. The cur_tx and dirty_tx are equal under both completely | |
201 | * empty and completely full conditions. The empty/ready indicator in | |
202 | * the buffer descriptor determines the actual condition. | |
203 | */ | |
204 | struct fec_enet_private { | |
205 | /* Hardware registers of the FEC device */ | |
f44d6305 | 206 | void __iomem *hwp; |
1da177e4 | 207 | |
cb84d6e7 GU |
208 | struct net_device *netdev; |
209 | ||
f4d40de3 SH |
210 | struct clk *clk_ipg; |
211 | struct clk *clk_ahb; | |
ead73183 | 212 | |
1da177e4 LT |
213 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
214 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
215 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
f0b3fbea | 216 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
1da177e4 LT |
217 | ushort skb_cur; |
218 | ushort skb_dirty; | |
219 | ||
22f6b860 | 220 | /* CPM dual port RAM relative addresses */ |
4661e75b | 221 | dma_addr_t bd_dma; |
22f6b860 | 222 | /* Address of Rx and Tx buffers */ |
2e28532f SH |
223 | struct bufdesc *rx_bd_base; |
224 | struct bufdesc *tx_bd_base; | |
225 | /* The next free ring entry */ | |
db8880bc | 226 | struct bufdesc *cur_rx, *cur_tx; |
22f6b860 | 227 | /* The ring entries to be free()ed */ |
2e28532f SH |
228 | struct bufdesc *dirty_tx; |
229 | ||
1da177e4 | 230 | uint tx_full; |
3b2b74ca SS |
231 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
232 | spinlock_t hw_lock; | |
1da177e4 | 233 | |
db8880bc | 234 | struct platform_device *pdev; |
1da177e4 | 235 | |
e6b043d5 | 236 | int opened; |
43af940c | 237 | int dev_id; |
1da177e4 | 238 | |
e6b043d5 | 239 | /* Phylib and MDIO interface */ |
db8880bc UKK |
240 | struct mii_bus *mii_bus; |
241 | struct phy_device *phy_dev; | |
242 | int mii_timeout; | |
243 | uint phy_speed; | |
5eb32bd0 | 244 | phy_interface_t phy_interface; |
1da177e4 | 245 | int link; |
1da177e4 | 246 | int full_duplex; |
97b72e43 | 247 | struct completion mdio_done; |
7f5c6add | 248 | int irq[FEC_IRQ_NUM]; |
1da177e4 LT |
249 | }; |
250 | ||
e6b043d5 BW |
251 | /* FEC MII MMFR bits definition */ |
252 | #define FEC_MMFR_ST (1 << 30) | |
253 | #define FEC_MMFR_OP_READ (2 << 28) | |
254 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
255 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
256 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
257 | #define FEC_MMFR_TA (2 << 16) | |
258 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 259 | |
c3b084c2 | 260 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 261 | |
22f6b860 SH |
262 | /* Transmitter timeout */ |
263 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 264 | |
e163cc97 LW |
265 | static int mii_cnt; |
266 | ||
b5680e0b SG |
267 | static void *swap_buffer(void *bufaddr, int len) |
268 | { | |
269 | int i; | |
270 | unsigned int *buf = bufaddr; | |
271 | ||
272 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
273 | *buf = cpu_to_be32(*buf); | |
274 | ||
275 | return bufaddr; | |
276 | } | |
277 | ||
c7621cb3 | 278 | static netdev_tx_t |
c556167f | 279 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 280 | { |
c556167f | 281 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
282 | const struct platform_device_id *id_entry = |
283 | platform_get_device_id(fep->pdev); | |
2e28532f | 284 | struct bufdesc *bdp; |
9555b31e | 285 | void *bufaddr; |
0e702ab3 | 286 | unsigned short status; |
3b2b74ca | 287 | unsigned long flags; |
1da177e4 | 288 | |
1da177e4 LT |
289 | if (!fep->link) { |
290 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 291 | return NETDEV_TX_BUSY; |
1da177e4 LT |
292 | } |
293 | ||
3b2b74ca | 294 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
295 | /* Fill in a Tx ring entry */ |
296 | bdp = fep->cur_tx; | |
297 | ||
0e702ab3 | 298 | status = bdp->cbd_sc; |
22f6b860 | 299 | |
0e702ab3 | 300 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 301 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 302 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 303 | */ |
c556167f | 304 | printk("%s: tx queue full!.\n", ndev->name); |
3b2b74ca | 305 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
5b548140 | 306 | return NETDEV_TX_BUSY; |
1da177e4 | 307 | } |
1da177e4 | 308 | |
22f6b860 | 309 | /* Clear all of the status flags */ |
0e702ab3 | 310 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 311 | |
22f6b860 | 312 | /* Set buffer length and buffer pointer */ |
9555b31e | 313 | bufaddr = skb->data; |
1da177e4 LT |
314 | bdp->cbd_datlen = skb->len; |
315 | ||
316 | /* | |
22f6b860 SH |
317 | * On some FEC implementations data must be aligned on |
318 | * 4-byte boundaries. Use bounce buffers to copy data | |
319 | * and get it aligned. Ugh. | |
1da177e4 | 320 | */ |
9555b31e | 321 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
1da177e4 LT |
322 | unsigned int index; |
323 | index = bdp - fep->tx_bd_base; | |
8a73b0bc | 324 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 325 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
326 | } |
327 | ||
b5680e0b SG |
328 | /* |
329 | * Some design made an incorrect assumption on endian mode of | |
330 | * the system that it's running on. As the result, driver has to | |
331 | * swap every frame going to and coming from the controller. | |
332 | */ | |
333 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
334 | swap_buffer(bufaddr, skb->len); | |
335 | ||
22f6b860 | 336 | /* Save skb pointer */ |
1da177e4 LT |
337 | fep->tx_skbuff[fep->skb_cur] = skb; |
338 | ||
c556167f | 339 | ndev->stats.tx_bytes += skb->len; |
1da177e4 | 340 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 341 | |
1da177e4 LT |
342 | /* Push the data cache so the CPM does not get stale memory |
343 | * data. | |
344 | */ | |
d1ab1f54 | 345 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 346 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 347 | |
0e702ab3 GU |
348 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
349 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 350 | */ |
0e702ab3 | 351 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 352 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 353 | bdp->cbd_sc = status; |
1da177e4 | 354 | |
1da177e4 | 355 | /* Trigger transmission start */ |
f44d6305 | 356 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 357 | |
22f6b860 SH |
358 | /* If this was the last BD in the ring, start at the beginning again. */ |
359 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 360 | bdp = fep->tx_bd_base; |
22f6b860 | 361 | else |
1da177e4 | 362 | bdp++; |
1da177e4 LT |
363 | |
364 | if (bdp == fep->dirty_tx) { | |
365 | fep->tx_full = 1; | |
c556167f | 366 | netif_stop_queue(ndev); |
1da177e4 LT |
367 | } |
368 | ||
2e28532f | 369 | fep->cur_tx = bdp; |
1da177e4 | 370 | |
18a03b97 RC |
371 | skb_tx_timestamp(skb); |
372 | ||
a0087a36 RC |
373 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
374 | ||
6ed10654 | 375 | return NETDEV_TX_OK; |
1da177e4 LT |
376 | } |
377 | ||
45993653 UKK |
378 | /* This function is called to start or restart the FEC during a link |
379 | * change. This only happens when switching between half and full | |
380 | * duplex. | |
381 | */ | |
1da177e4 | 382 | static void |
45993653 | 383 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 384 | { |
c556167f | 385 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
386 | const struct platform_device_id *id_entry = |
387 | platform_get_device_id(fep->pdev); | |
388 | int i; | |
cd1f402c UKK |
389 | u32 temp_mac[2]; |
390 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 391 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 392 | |
45993653 UKK |
393 | /* Whack a reset. We should wait for this. */ |
394 | writel(1, fep->hwp + FEC_ECNTRL); | |
395 | udelay(10); | |
1da177e4 | 396 | |
45993653 UKK |
397 | /* |
398 | * enet-mac reset will reset mac address registers too, | |
399 | * so need to reconfigure it. | |
400 | */ | |
401 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
402 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
403 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
404 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
405 | } | |
1da177e4 | 406 | |
45993653 UKK |
407 | /* Clear any outstanding interrupt. */ |
408 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 409 | |
45993653 UKK |
410 | /* Reset all multicast. */ |
411 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
412 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
413 | #ifndef CONFIG_M5272 | |
414 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
415 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
416 | #endif | |
1da177e4 | 417 | |
45993653 UKK |
418 | /* Set maximum receive buffer size. */ |
419 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 420 | |
45993653 UKK |
421 | /* Set receive and transmit descriptor base. */ |
422 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
423 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, | |
424 | fep->hwp + FEC_X_DES_START); | |
425 | ||
426 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
427 | fep->cur_rx = fep->rx_bd_base; | |
428 | ||
429 | /* Reset SKB transmit buffers. */ | |
430 | fep->skb_cur = fep->skb_dirty = 0; | |
431 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { | |
432 | if (fep->tx_skbuff[i]) { | |
433 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
434 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 435 | } |
45993653 | 436 | } |
97b72e43 | 437 | |
45993653 UKK |
438 | /* Enable MII mode */ |
439 | if (duplex) { | |
cd1f402c | 440 | /* FD enable */ |
45993653 UKK |
441 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
442 | } else { | |
cd1f402c UKK |
443 | /* No Rcv on Xmit */ |
444 | rcntl |= 0x02; | |
45993653 UKK |
445 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
446 | } | |
cd1f402c | 447 | |
45993653 UKK |
448 | fep->full_duplex = duplex; |
449 | ||
450 | /* Set MII speed */ | |
451 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
452 | ||
453 | /* | |
454 | * The phy interface and speed need to get configured | |
455 | * differently on enet-mac. | |
456 | */ | |
457 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
458 | /* Enable flow control and length check */ |
459 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 460 | |
230dec61 SG |
461 | /* RGMII, RMII or MII */ |
462 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
463 | rcntl |= (1 << 6); | |
464 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 465 | rcntl |= (1 << 8); |
45993653 | 466 | else |
cd1f402c | 467 | rcntl &= ~(1 << 8); |
45993653 | 468 | |
230dec61 SG |
469 | /* 1G, 100M or 10M */ |
470 | if (fep->phy_dev) { | |
471 | if (fep->phy_dev->speed == SPEED_1000) | |
472 | ecntl |= (1 << 5); | |
473 | else if (fep->phy_dev->speed == SPEED_100) | |
474 | rcntl &= ~(1 << 9); | |
475 | else | |
476 | rcntl |= (1 << 9); | |
477 | } | |
45993653 UKK |
478 | } else { |
479 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 480 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 481 | u32 cfgr; |
45993653 UKK |
482 | /* disable the gasket and wait */ |
483 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
484 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
485 | udelay(1); | |
486 | ||
487 | /* | |
488 | * configure the gasket: | |
489 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 490 | * MII, 25 MHz, no loopback, no echo |
45993653 | 491 | */ |
8d82f219 EB |
492 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
493 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
494 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
495 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
496 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
497 | |
498 | /* re-enable the gasket */ | |
499 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 500 | } |
45993653 UKK |
501 | #endif |
502 | } | |
cd1f402c | 503 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 504 | |
230dec61 SG |
505 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
506 | /* enable ENET endian swap */ | |
507 | ecntl |= (1 << 8); | |
508 | /* enable ENET store and forward mode */ | |
509 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
510 | } | |
511 | ||
45993653 | 512 | /* And last, enable the transmit and receive processing */ |
230dec61 | 513 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
514 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
515 | ||
516 | /* Enable interrupts we wish to service */ | |
517 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
518 | } | |
519 | ||
520 | static void | |
521 | fec_stop(struct net_device *ndev) | |
522 | { | |
523 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
524 | const struct platform_device_id *id_entry = |
525 | platform_get_device_id(fep->pdev); | |
42431dc2 | 526 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
527 | |
528 | /* We cannot expect a graceful transmit stop without link !!! */ | |
529 | if (fep->link) { | |
530 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
531 | udelay(10); | |
532 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
533 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
534 | } | |
535 | ||
536 | /* Whack a reset. We should wait for this. */ | |
537 | writel(1, fep->hwp + FEC_ECNTRL); | |
538 | udelay(10); | |
539 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
540 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
541 | |
542 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 543 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 544 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
545 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
546 | } | |
1da177e4 LT |
547 | } |
548 | ||
549 | ||
45993653 UKK |
550 | static void |
551 | fec_timeout(struct net_device *ndev) | |
552 | { | |
553 | struct fec_enet_private *fep = netdev_priv(ndev); | |
554 | ||
555 | ndev->stats.tx_errors++; | |
556 | ||
557 | fec_restart(ndev, fep->full_duplex); | |
558 | netif_wake_queue(ndev); | |
559 | } | |
560 | ||
1da177e4 | 561 | static void |
c556167f | 562 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
563 | { |
564 | struct fec_enet_private *fep; | |
2e28532f | 565 | struct bufdesc *bdp; |
0e702ab3 | 566 | unsigned short status; |
1da177e4 LT |
567 | struct sk_buff *skb; |
568 | ||
c556167f | 569 | fep = netdev_priv(ndev); |
81538e74 | 570 | spin_lock(&fep->hw_lock); |
1da177e4 LT |
571 | bdp = fep->dirty_tx; |
572 | ||
0e702ab3 | 573 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
f0b3fbea SH |
574 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
575 | break; | |
576 | ||
d1ab1f54 UKK |
577 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
578 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 579 | bdp->cbd_bufaddr = 0; |
1da177e4 LT |
580 | |
581 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
582 | /* Check for errors. */ | |
0e702ab3 | 583 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
584 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
585 | BD_ENET_TX_CSL)) { | |
c556167f | 586 | ndev->stats.tx_errors++; |
0e702ab3 | 587 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 588 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 589 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 590 | ndev->stats.tx_window_errors++; |
0e702ab3 | 591 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 592 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 593 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 594 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 595 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 596 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 597 | } else { |
c556167f | 598 | ndev->stats.tx_packets++; |
1da177e4 LT |
599 | } |
600 | ||
0e702ab3 | 601 | if (status & BD_ENET_TX_READY) |
1da177e4 | 602 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 603 | |
1da177e4 LT |
604 | /* Deferred means some collisions occurred during transmit, |
605 | * but we eventually sent the packet OK. | |
606 | */ | |
0e702ab3 | 607 | if (status & BD_ENET_TX_DEF) |
c556167f | 608 | ndev->stats.collisions++; |
6aa20a22 | 609 | |
22f6b860 | 610 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
611 | dev_kfree_skb_any(skb); |
612 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
613 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 614 | |
22f6b860 | 615 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 616 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
617 | bdp = fep->tx_bd_base; |
618 | else | |
619 | bdp++; | |
6aa20a22 | 620 | |
22f6b860 | 621 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
622 | */ |
623 | if (fep->tx_full) { | |
624 | fep->tx_full = 0; | |
c556167f UKK |
625 | if (netif_queue_stopped(ndev)) |
626 | netif_wake_queue(ndev); | |
1da177e4 LT |
627 | } |
628 | } | |
2e28532f | 629 | fep->dirty_tx = bdp; |
81538e74 | 630 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
631 | } |
632 | ||
633 | ||
634 | /* During a receive, the cur_rx points to the current incoming buffer. | |
635 | * When we update through the ring, if the next incoming buffer has | |
636 | * not been given to the system, we just set the empty indicator, | |
637 | * effectively tossing the packet. | |
638 | */ | |
639 | static void | |
c556167f | 640 | fec_enet_rx(struct net_device *ndev) |
1da177e4 | 641 | { |
c556167f | 642 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
643 | const struct platform_device_id *id_entry = |
644 | platform_get_device_id(fep->pdev); | |
2e28532f | 645 | struct bufdesc *bdp; |
0e702ab3 | 646 | unsigned short status; |
1da177e4 LT |
647 | struct sk_buff *skb; |
648 | ushort pkt_len; | |
649 | __u8 *data; | |
6aa20a22 | 650 | |
0e702ab3 GU |
651 | #ifdef CONFIG_M532x |
652 | flush_cache_all(); | |
6aa20a22 | 653 | #endif |
1da177e4 | 654 | |
81538e74 | 655 | spin_lock(&fep->hw_lock); |
3b2b74ca | 656 | |
1da177e4 LT |
657 | /* First, grab all of the stats for the incoming packet. |
658 | * These get messed up if we get called due to a busy condition. | |
659 | */ | |
660 | bdp = fep->cur_rx; | |
661 | ||
22f6b860 | 662 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 663 | |
22f6b860 SH |
664 | /* Since we have allocated space to hold a complete frame, |
665 | * the last indicator should be set. | |
666 | */ | |
667 | if ((status & BD_ENET_RX_LAST) == 0) | |
668 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 669 | |
22f6b860 SH |
670 | if (!fep->opened) |
671 | goto rx_processing_done; | |
1da177e4 | 672 | |
22f6b860 SH |
673 | /* Check for errors. */ |
674 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 675 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 676 | ndev->stats.rx_errors++; |
22f6b860 SH |
677 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
678 | /* Frame too long or too short. */ | |
c556167f | 679 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
680 | } |
681 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 682 | ndev->stats.rx_frame_errors++; |
22f6b860 | 683 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 684 | ndev->stats.rx_crc_errors++; |
22f6b860 | 685 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 686 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 687 | } |
1da177e4 | 688 | |
22f6b860 SH |
689 | /* Report late collisions as a frame error. |
690 | * On this error, the BD is closed, but we don't know what we | |
691 | * have in the buffer. So, just drop this frame on the floor. | |
692 | */ | |
693 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
694 | ndev->stats.rx_errors++; |
695 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
696 | goto rx_processing_done; |
697 | } | |
1da177e4 | 698 | |
22f6b860 | 699 | /* Process the incoming frame. */ |
c556167f | 700 | ndev->stats.rx_packets++; |
22f6b860 | 701 | pkt_len = bdp->cbd_datlen; |
c556167f | 702 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 703 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 704 | |
d1ab1f54 UKK |
705 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
706 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 707 | |
b5680e0b SG |
708 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
709 | swap_buffer(data, pkt_len); | |
710 | ||
22f6b860 SH |
711 | /* This does 16 byte alignment, exactly what we need. |
712 | * The packet length includes FCS, but we don't want to | |
713 | * include that when passing upstream as it messes up | |
714 | * bridging applications. | |
715 | */ | |
b72061a3 | 716 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 717 | |
8549889c | 718 | if (unlikely(!skb)) { |
22f6b860 | 719 | printk("%s: Memory squeeze, dropping packet.\n", |
c556167f UKK |
720 | ndev->name); |
721 | ndev->stats.rx_dropped++; | |
22f6b860 | 722 | } else { |
8549889c | 723 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
724 | skb_put(skb, pkt_len - 4); /* Make room */ |
725 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 726 | skb->protocol = eth_type_trans(skb, ndev); |
18a03b97 RC |
727 | if (!skb_defer_rx_timestamp(skb)) |
728 | netif_rx(skb); | |
22f6b860 | 729 | } |
f0b3fbea | 730 | |
d1ab1f54 UKK |
731 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
732 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
733 | rx_processing_done: |
734 | /* Clear the status flags for this buffer */ | |
735 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 736 | |
22f6b860 SH |
737 | /* Mark the buffer empty */ |
738 | status |= BD_ENET_RX_EMPTY; | |
739 | bdp->cbd_sc = status; | |
6aa20a22 | 740 | |
22f6b860 SH |
741 | /* Update BD pointer to next entry */ |
742 | if (status & BD_ENET_RX_WRAP) | |
743 | bdp = fep->rx_bd_base; | |
744 | else | |
745 | bdp++; | |
746 | /* Doing this here will keep the FEC running while we process | |
747 | * incoming frames. On a heavily loaded network, we should be | |
748 | * able to keep up at the expense of system resources. | |
749 | */ | |
750 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
751 | } | |
2e28532f | 752 | fep->cur_rx = bdp; |
1da177e4 | 753 | |
81538e74 | 754 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
755 | } |
756 | ||
45993653 UKK |
757 | static irqreturn_t |
758 | fec_enet_interrupt(int irq, void *dev_id) | |
759 | { | |
760 | struct net_device *ndev = dev_id; | |
761 | struct fec_enet_private *fep = netdev_priv(ndev); | |
762 | uint int_events; | |
763 | irqreturn_t ret = IRQ_NONE; | |
764 | ||
765 | do { | |
766 | int_events = readl(fep->hwp + FEC_IEVENT); | |
767 | writel(int_events, fep->hwp + FEC_IEVENT); | |
768 | ||
769 | if (int_events & FEC_ENET_RXF) { | |
770 | ret = IRQ_HANDLED; | |
771 | fec_enet_rx(ndev); | |
772 | } | |
773 | ||
774 | /* Transmit OK, or non-fatal error. Update the buffer | |
775 | * descriptors. FEC handles all errors, we just discover | |
776 | * them as part of the transmit process. | |
777 | */ | |
778 | if (int_events & FEC_ENET_TXF) { | |
779 | ret = IRQ_HANDLED; | |
780 | fec_enet_tx(ndev); | |
781 | } | |
782 | ||
783 | if (int_events & FEC_ENET_MII) { | |
784 | ret = IRQ_HANDLED; | |
785 | complete(&fep->mdio_done); | |
786 | } | |
787 | } while (int_events); | |
788 | ||
789 | return ret; | |
790 | } | |
791 | ||
792 | ||
793 | ||
e6b043d5 | 794 | /* ------------------------------------------------------------------------- */ |
c556167f | 795 | static void __inline__ fec_get_mac(struct net_device *ndev) |
1da177e4 | 796 | { |
c556167f | 797 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 798 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 799 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 800 | |
49da97dc SG |
801 | /* |
802 | * try to get mac address in following order: | |
803 | * | |
804 | * 1) module parameter via kernel command line in form | |
805 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
806 | */ | |
807 | iap = macaddr; | |
808 | ||
ca2cc333 SG |
809 | #ifdef CONFIG_OF |
810 | /* | |
811 | * 2) from device tree data | |
812 | */ | |
813 | if (!is_valid_ether_addr(iap)) { | |
814 | struct device_node *np = fep->pdev->dev.of_node; | |
815 | if (np) { | |
816 | const char *mac = of_get_mac_address(np); | |
817 | if (mac) | |
818 | iap = (unsigned char *) mac; | |
819 | } | |
820 | } | |
821 | #endif | |
822 | ||
49da97dc | 823 | /* |
ca2cc333 | 824 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
825 | */ |
826 | if (!is_valid_ether_addr(iap)) { | |
827 | #ifdef CONFIG_M5272 | |
828 | if (FEC_FLASHMAC) | |
829 | iap = (unsigned char *)FEC_FLASHMAC; | |
830 | #else | |
831 | if (pdata) | |
589efdc7 | 832 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
833 | #endif |
834 | } | |
835 | ||
836 | /* | |
ca2cc333 | 837 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
838 | */ |
839 | if (!is_valid_ether_addr(iap)) { | |
840 | *((unsigned long *) &tmpaddr[0]) = | |
841 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
842 | *((unsigned short *) &tmpaddr[4]) = | |
843 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 844 | iap = &tmpaddr[0]; |
1da177e4 LT |
845 | } |
846 | ||
c556167f | 847 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 848 | |
49da97dc SG |
849 | /* Adjust MAC if using macaddr */ |
850 | if (iap == macaddr) | |
43af940c | 851 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
852 | } |
853 | ||
e6b043d5 | 854 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 855 | |
e6b043d5 BW |
856 | /* |
857 | * Phy section | |
858 | */ | |
c556167f | 859 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 860 | { |
c556167f | 861 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 BW |
862 | struct phy_device *phy_dev = fep->phy_dev; |
863 | unsigned long flags; | |
1da177e4 | 864 | |
e6b043d5 | 865 | int status_change = 0; |
1da177e4 | 866 | |
e6b043d5 | 867 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 868 | |
e6b043d5 BW |
869 | /* Prevent a state halted on mii error */ |
870 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
871 | phy_dev->state = PHY_RESUMING; | |
872 | goto spin_unlock; | |
873 | } | |
1da177e4 | 874 | |
e6b043d5 BW |
875 | /* Duplex link change */ |
876 | if (phy_dev->link) { | |
877 | if (fep->full_duplex != phy_dev->duplex) { | |
c556167f | 878 | fec_restart(ndev, phy_dev->duplex); |
6ea0722f LW |
879 | /* prevent unnecessary second fec_restart() below */ |
880 | fep->link = phy_dev->link; | |
e6b043d5 BW |
881 | status_change = 1; |
882 | } | |
883 | } | |
1da177e4 | 884 | |
e6b043d5 BW |
885 | /* Link on or off change */ |
886 | if (phy_dev->link != fep->link) { | |
887 | fep->link = phy_dev->link; | |
888 | if (phy_dev->link) | |
c556167f | 889 | fec_restart(ndev, phy_dev->duplex); |
1da177e4 | 890 | else |
c556167f | 891 | fec_stop(ndev); |
e6b043d5 | 892 | status_change = 1; |
1da177e4 | 893 | } |
6aa20a22 | 894 | |
e6b043d5 BW |
895 | spin_unlock: |
896 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 897 | |
e6b043d5 BW |
898 | if (status_change) |
899 | phy_print_status(phy_dev); | |
900 | } | |
1da177e4 | 901 | |
e6b043d5 | 902 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 903 | { |
e6b043d5 | 904 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 905 | unsigned long time_left; |
1da177e4 | 906 | |
e6b043d5 | 907 | fep->mii_timeout = 0; |
97b72e43 | 908 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
909 | |
910 | /* start a read op */ | |
911 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
912 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
913 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
914 | ||
915 | /* wait for end of transfer */ | |
97b72e43 BS |
916 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
917 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
918 | if (time_left == 0) { | |
919 | fep->mii_timeout = 1; | |
920 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
921 | return -ETIMEDOUT; | |
1da177e4 | 922 | } |
1da177e4 | 923 | |
e6b043d5 BW |
924 | /* return value */ |
925 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 926 | } |
6aa20a22 | 927 | |
e6b043d5 BW |
928 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
929 | u16 value) | |
1da177e4 | 930 | { |
e6b043d5 | 931 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 932 | unsigned long time_left; |
1da177e4 | 933 | |
e6b043d5 | 934 | fep->mii_timeout = 0; |
97b72e43 | 935 | init_completion(&fep->mdio_done); |
1da177e4 | 936 | |
862f0982 SG |
937 | /* start a write op */ |
938 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
939 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
940 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
941 | fep->hwp + FEC_MII_DATA); | |
942 | ||
943 | /* wait for end of transfer */ | |
97b72e43 BS |
944 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
945 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
946 | if (time_left == 0) { | |
947 | fep->mii_timeout = 1; | |
948 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
949 | return -ETIMEDOUT; | |
e6b043d5 | 950 | } |
1da177e4 | 951 | |
e6b043d5 BW |
952 | return 0; |
953 | } | |
1da177e4 | 954 | |
e6b043d5 | 955 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 956 | { |
e6b043d5 | 957 | return 0; |
1da177e4 LT |
958 | } |
959 | ||
c556167f | 960 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 961 | { |
c556167f | 962 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
963 | const struct platform_device_id *id_entry = |
964 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 965 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
966 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
967 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
968 | int phy_id; | |
43af940c | 969 | int dev_id = fep->dev_id; |
562d2f8c | 970 | |
418bd0d4 BW |
971 | fep->phy_dev = NULL; |
972 | ||
6fcc040f GU |
973 | /* check for attached phy */ |
974 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
975 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
976 | continue; | |
977 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
978 | continue; | |
979 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
980 | continue; | |
b5680e0b SG |
981 | if (dev_id--) |
982 | continue; | |
6fcc040f GU |
983 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
984 | break; | |
e6b043d5 | 985 | } |
1da177e4 | 986 | |
6fcc040f | 987 | if (phy_id >= PHY_MAX_ADDR) { |
a7dd3219 LW |
988 | printk(KERN_INFO |
989 | "%s: no PHY, assuming direct connection to switch\n", | |
990 | ndev->name); | |
ea51ade9 | 991 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
992 | phy_id = 0; |
993 | } | |
994 | ||
a7ed07d5 | 995 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
c556167f | 996 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0, |
230dec61 | 997 | fep->phy_interface); |
6fcc040f | 998 | if (IS_ERR(phy_dev)) { |
c556167f | 999 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); |
6fcc040f | 1000 | return PTR_ERR(phy_dev); |
e6b043d5 | 1001 | } |
1da177e4 | 1002 | |
e6b043d5 | 1003 | /* mask with MAC supported features */ |
230dec61 SG |
1004 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) |
1005 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
1006 | else | |
1007 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1008 | ||
e6b043d5 | 1009 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1010 | |
e6b043d5 BW |
1011 | fep->phy_dev = phy_dev; |
1012 | fep->link = 0; | |
1013 | fep->full_duplex = 0; | |
1da177e4 | 1014 | |
a7dd3219 LW |
1015 | printk(KERN_INFO |
1016 | "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
1017 | ndev->name, | |
418bd0d4 BW |
1018 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
1019 | fep->phy_dev->irq); | |
1020 | ||
e6b043d5 | 1021 | return 0; |
1da177e4 LT |
1022 | } |
1023 | ||
e6b043d5 | 1024 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1025 | { |
b5680e0b | 1026 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1027 | struct net_device *ndev = platform_get_drvdata(pdev); |
1028 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1029 | const struct platform_device_id *id_entry = |
1030 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1031 | int err = -ENXIO, i; |
6b265293 | 1032 | |
b5680e0b SG |
1033 | /* |
1034 | * The dual fec interfaces are not equivalent with enet-mac. | |
1035 | * Here are the differences: | |
1036 | * | |
1037 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1038 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1039 | * - external phys can only be configured by fec0 | |
1040 | * | |
1041 | * That is to say fec1 can not work independently. It only works | |
1042 | * when fec0 is working. The reason behind this design is that the | |
1043 | * second interface is added primarily for Switch mode. | |
1044 | * | |
1045 | * Because of the last point above, both phys are attached on fec0 | |
1046 | * mdio interface in board design, and need to be configured by | |
1047 | * fec0 mii_bus. | |
1048 | */ | |
43af940c | 1049 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1050 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1051 | if (mii_cnt && fec0_mii_bus) { |
1052 | fep->mii_bus = fec0_mii_bus; | |
1053 | mii_cnt++; | |
1054 | return 0; | |
1055 | } | |
1056 | return -ENOENT; | |
b5680e0b SG |
1057 | } |
1058 | ||
e6b043d5 | 1059 | fep->mii_timeout = 0; |
1da177e4 | 1060 | |
e6b043d5 BW |
1061 | /* |
1062 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1063 | * |
1064 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1065 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1066 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1067 | * document. | |
e6b043d5 | 1068 | */ |
f4d40de3 | 1069 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1070 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1071 | fep->phy_speed--; | |
1072 | fep->phy_speed <<= 1; | |
e6b043d5 | 1073 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1074 | |
e6b043d5 BW |
1075 | fep->mii_bus = mdiobus_alloc(); |
1076 | if (fep->mii_bus == NULL) { | |
1077 | err = -ENOMEM; | |
1078 | goto err_out; | |
1da177e4 LT |
1079 | } |
1080 | ||
e6b043d5 BW |
1081 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1082 | fep->mii_bus->read = fec_enet_mdio_read; | |
1083 | fep->mii_bus->write = fec_enet_mdio_write; | |
1084 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1085 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1086 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1087 | fep->mii_bus->priv = fep; |
1088 | fep->mii_bus->parent = &pdev->dev; | |
1089 | ||
1090 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1091 | if (!fep->mii_bus->irq) { | |
1092 | err = -ENOMEM; | |
1093 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1094 | } |
1095 | ||
e6b043d5 BW |
1096 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1097 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1098 | |
e6b043d5 BW |
1099 | if (mdiobus_register(fep->mii_bus)) |
1100 | goto err_out_free_mdio_irq; | |
1da177e4 | 1101 | |
e163cc97 LW |
1102 | mii_cnt++; |
1103 | ||
b5680e0b SG |
1104 | /* save fec0 mii_bus */ |
1105 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1106 | fec0_mii_bus = fep->mii_bus; | |
1107 | ||
e6b043d5 | 1108 | return 0; |
1da177e4 | 1109 | |
e6b043d5 BW |
1110 | err_out_free_mdio_irq: |
1111 | kfree(fep->mii_bus->irq); | |
1112 | err_out_free_mdiobus: | |
1113 | mdiobus_free(fep->mii_bus); | |
1114 | err_out: | |
1115 | return err; | |
1da177e4 LT |
1116 | } |
1117 | ||
e6b043d5 | 1118 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1119 | { |
e163cc97 LW |
1120 | if (--mii_cnt == 0) { |
1121 | mdiobus_unregister(fep->mii_bus); | |
1122 | kfree(fep->mii_bus->irq); | |
1123 | mdiobus_free(fep->mii_bus); | |
1124 | } | |
1da177e4 LT |
1125 | } |
1126 | ||
c556167f | 1127 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1128 | struct ethtool_cmd *cmd) |
1da177e4 | 1129 | { |
c556167f | 1130 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1131 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1132 | |
e6b043d5 BW |
1133 | if (!phydev) |
1134 | return -ENODEV; | |
1da177e4 | 1135 | |
e6b043d5 | 1136 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1137 | } |
1138 | ||
c556167f | 1139 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1140 | struct ethtool_cmd *cmd) |
1da177e4 | 1141 | { |
c556167f | 1142 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1143 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1144 | |
e6b043d5 BW |
1145 | if (!phydev) |
1146 | return -ENODEV; | |
1da177e4 | 1147 | |
e6b043d5 | 1148 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1149 | } |
1150 | ||
c556167f | 1151 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1152 | struct ethtool_drvinfo *info) |
1da177e4 | 1153 | { |
c556167f | 1154 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1155 | |
e6b043d5 BW |
1156 | strcpy(info->driver, fep->pdev->dev.driver->name); |
1157 | strcpy(info->version, "Revision: 1.0"); | |
c556167f | 1158 | strcpy(info->bus_info, dev_name(&ndev->dev)); |
1da177e4 LT |
1159 | } |
1160 | ||
9b07be4b | 1161 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
e6b043d5 BW |
1162 | .get_settings = fec_enet_get_settings, |
1163 | .set_settings = fec_enet_set_settings, | |
1164 | .get_drvinfo = fec_enet_get_drvinfo, | |
1165 | .get_link = ethtool_op_get_link, | |
ec567bca | 1166 | .get_ts_info = ethtool_op_get_ts_info, |
e6b043d5 | 1167 | }; |
1da177e4 | 1168 | |
c556167f | 1169 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1170 | { |
c556167f | 1171 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1172 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1173 | |
c556167f | 1174 | if (!netif_running(ndev)) |
e6b043d5 | 1175 | return -EINVAL; |
1da177e4 | 1176 | |
e6b043d5 BW |
1177 | if (!phydev) |
1178 | return -ENODEV; | |
1179 | ||
28b04113 | 1180 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1181 | } |
1182 | ||
c556167f | 1183 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1184 | { |
c556167f | 1185 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1186 | int i; |
1187 | struct sk_buff *skb; | |
1188 | struct bufdesc *bdp; | |
1189 | ||
1190 | bdp = fep->rx_bd_base; | |
1191 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1192 | skb = fep->rx_skbuff[i]; | |
1193 | ||
1194 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1195 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1196 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1197 | if (skb) | |
1198 | dev_kfree_skb(skb); | |
1199 | bdp++; | |
1200 | } | |
1201 | ||
1202 | bdp = fep->tx_bd_base; | |
1203 | for (i = 0; i < TX_RING_SIZE; i++) | |
1204 | kfree(fep->tx_bounce[i]); | |
1205 | } | |
1206 | ||
c556167f | 1207 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1208 | { |
c556167f | 1209 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1210 | int i; |
1211 | struct sk_buff *skb; | |
1212 | struct bufdesc *bdp; | |
1213 | ||
1214 | bdp = fep->rx_bd_base; | |
1215 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1216 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1217 | if (!skb) { |
c556167f | 1218 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1219 | return -ENOMEM; |
1220 | } | |
1221 | fep->rx_skbuff[i] = skb; | |
1222 | ||
d1ab1f54 | 1223 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1224 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1225 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
1226 | bdp++; | |
1227 | } | |
1228 | ||
1229 | /* Set the last buffer to wrap. */ | |
1230 | bdp--; | |
1231 | bdp->cbd_sc |= BD_SC_WRAP; | |
1232 | ||
1233 | bdp = fep->tx_bd_base; | |
1234 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1235 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1236 | ||
1237 | bdp->cbd_sc = 0; | |
1238 | bdp->cbd_bufaddr = 0; | |
1239 | bdp++; | |
1240 | } | |
1241 | ||
1242 | /* Set the last buffer to wrap. */ | |
1243 | bdp--; | |
1244 | bdp->cbd_sc |= BD_SC_WRAP; | |
1245 | ||
1246 | return 0; | |
1247 | } | |
1248 | ||
1da177e4 | 1249 | static int |
c556167f | 1250 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1251 | { |
c556167f | 1252 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1253 | int ret; |
1da177e4 LT |
1254 | |
1255 | /* I should reset the ring buffers here, but I don't yet know | |
1256 | * a simple way to do that. | |
1257 | */ | |
1da177e4 | 1258 | |
c556167f | 1259 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1260 | if (ret) |
1261 | return ret; | |
1262 | ||
418bd0d4 | 1263 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1264 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1265 | if (ret) { |
c556167f | 1266 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1267 | return ret; |
1268 | } | |
e6b043d5 | 1269 | phy_start(fep->phy_dev); |
c556167f | 1270 | netif_start_queue(ndev); |
1da177e4 | 1271 | fep->opened = 1; |
22f6b860 | 1272 | return 0; |
1da177e4 LT |
1273 | } |
1274 | ||
1275 | static int | |
c556167f | 1276 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1277 | { |
c556167f | 1278 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1279 | |
22f6b860 | 1280 | /* Don't know what to do yet. */ |
1da177e4 | 1281 | fep->opened = 0; |
c556167f UKK |
1282 | netif_stop_queue(ndev); |
1283 | fec_stop(ndev); | |
1da177e4 | 1284 | |
e497ba82 UKK |
1285 | if (fep->phy_dev) { |
1286 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1287 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1288 | } |
418bd0d4 | 1289 | |
db8880bc | 1290 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1291 | |
1da177e4 LT |
1292 | return 0; |
1293 | } | |
1294 | ||
1da177e4 LT |
1295 | /* Set or clear the multicast filter for this adaptor. |
1296 | * Skeleton taken from sunlance driver. | |
1297 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1298 | * MAC address filtering. Some of the drivers check to make sure it is | |
1299 | * a group multicast address, and discard those that are not. I guess I | |
1300 | * will do the same for now, but just remove the test if you want | |
1301 | * individual filtering as well (do the upper net layers want or support | |
1302 | * this kind of feature?). | |
1303 | */ | |
1304 | ||
1305 | #define HASH_BITS 6 /* #bits in hash */ | |
1306 | #define CRC32_POLY 0xEDB88320 | |
1307 | ||
c556167f | 1308 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1309 | { |
c556167f | 1310 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1311 | struct netdev_hw_addr *ha; |
48e2f183 | 1312 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1313 | unsigned char hash; |
1314 | ||
c556167f | 1315 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1316 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1317 | tmp |= 0x8; | |
1318 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1319 | return; |
1320 | } | |
1da177e4 | 1321 | |
4e831836 SH |
1322 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1323 | tmp &= ~0x8; | |
1324 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1325 | ||
c556167f | 1326 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1327 | /* Catch all multicast addresses, so set the |
1328 | * filter to all 1's | |
1329 | */ | |
1330 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1331 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1332 | ||
1333 | return; | |
1334 | } | |
1335 | ||
1336 | /* Clear filter and add the addresses in hash register | |
1337 | */ | |
1338 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1339 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1340 | ||
c556167f | 1341 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1342 | /* calculate crc32 value of mac address */ |
1343 | crc = 0xffffffff; | |
1344 | ||
c556167f | 1345 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1346 | data = ha->addr[i]; |
4e831836 SH |
1347 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1348 | crc = (crc >> 1) ^ | |
1349 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1350 | } |
1351 | } | |
4e831836 SH |
1352 | |
1353 | /* only upper 6 bits (HASH_BITS) are used | |
1354 | * which point to specific bit in he hash registers | |
1355 | */ | |
1356 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1357 | ||
1358 | if (hash > 31) { | |
1359 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1360 | tmp |= 1 << (hash - 32); | |
1361 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1362 | } else { | |
1363 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1364 | tmp |= 1 << hash; | |
1365 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1366 | } | |
1da177e4 LT |
1367 | } |
1368 | } | |
1369 | ||
22f6b860 | 1370 | /* Set a MAC change in hardware. */ |
009fda83 | 1371 | static int |
c556167f | 1372 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1373 | { |
c556167f | 1374 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1375 | struct sockaddr *addr = p; |
1376 | ||
1377 | if (!is_valid_ether_addr(addr->sa_data)) | |
1378 | return -EADDRNOTAVAIL; | |
1379 | ||
c556167f | 1380 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1381 | |
c556167f UKK |
1382 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1383 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1384 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1385 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1386 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1387 | return 0; |
1da177e4 LT |
1388 | } |
1389 | ||
7f5c6add XJ |
1390 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1391 | /* | |
1392 | * fec_poll_controller: FEC Poll controller function | |
1393 | * @dev: The FEC network adapter | |
1394 | * | |
1395 | * Polled functionality used by netconsole and others in non interrupt mode | |
1396 | * | |
1397 | */ | |
1398 | void fec_poll_controller(struct net_device *dev) | |
1399 | { | |
1400 | int i; | |
1401 | struct fec_enet_private *fep = netdev_priv(dev); | |
1402 | ||
1403 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1404 | if (fep->irq[i] > 0) { | |
1405 | disable_irq(fep->irq[i]); | |
1406 | fec_enet_interrupt(fep->irq[i], dev); | |
1407 | enable_irq(fep->irq[i]); | |
1408 | } | |
1409 | } | |
1410 | } | |
1411 | #endif | |
1412 | ||
009fda83 SH |
1413 | static const struct net_device_ops fec_netdev_ops = { |
1414 | .ndo_open = fec_enet_open, | |
1415 | .ndo_stop = fec_enet_close, | |
1416 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1417 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1418 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1419 | .ndo_validate_addr = eth_validate_addr, |
1420 | .ndo_tx_timeout = fec_timeout, | |
1421 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1422 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1423 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1424 | .ndo_poll_controller = fec_poll_controller, | |
1425 | #endif | |
009fda83 SH |
1426 | }; |
1427 | ||
1da177e4 LT |
1428 | /* |
1429 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1430 | * |
1da177e4 | 1431 | */ |
c556167f | 1432 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1433 | { |
c556167f | 1434 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1435 | struct bufdesc *cbd_base; |
633e7533 | 1436 | struct bufdesc *bdp; |
f0b3fbea | 1437 | int i; |
1da177e4 | 1438 | |
8d4dd5cf SH |
1439 | /* Allocate memory for buffer descriptors. */ |
1440 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1441 | GFP_KERNEL); | |
1442 | if (!cbd_base) { | |
562d2f8c GU |
1443 | printk("FEC: allocate descriptor memory failed?\n"); |
1444 | return -ENOMEM; | |
1445 | } | |
1446 | ||
3b2b74ca | 1447 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1448 | |
c556167f | 1449 | fep->netdev = ndev; |
1da177e4 | 1450 | |
49da97dc | 1451 | /* Get the Ethernet address */ |
c556167f | 1452 | fec_get_mac(ndev); |
1da177e4 | 1453 | |
8d4dd5cf | 1454 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1455 | fep->rx_bd_base = cbd_base; |
1456 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1457 | ||
22f6b860 | 1458 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1459 | ndev->watchdog_timeo = TX_TIMEOUT; |
1460 | ndev->netdev_ops = &fec_netdev_ops; | |
1461 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 RH |
1462 | |
1463 | /* Initialize the receive buffer descriptors. */ | |
1464 | bdp = fep->rx_bd_base; | |
1465 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1466 | ||
1467 | /* Initialize the BD for every fragment in the page. */ | |
1468 | bdp->cbd_sc = 0; | |
1469 | bdp++; | |
1470 | } | |
1471 | ||
1472 | /* Set the last buffer to wrap */ | |
1473 | bdp--; | |
1474 | bdp->cbd_sc |= BD_SC_WRAP; | |
1475 | ||
1476 | /* ...and the same for transmit */ | |
1477 | bdp = fep->tx_bd_base; | |
1478 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1479 | ||
1480 | /* Initialize the BD for every fragment in the page. */ | |
1481 | bdp->cbd_sc = 0; | |
1482 | bdp->cbd_bufaddr = 0; | |
1483 | bdp++; | |
1484 | } | |
1485 | ||
1486 | /* Set the last buffer to wrap */ | |
1487 | bdp--; | |
1488 | bdp->cbd_sc |= BD_SC_WRAP; | |
1489 | ||
c556167f | 1490 | fec_restart(ndev, 0); |
1da177e4 | 1491 | |
1da177e4 LT |
1492 | return 0; |
1493 | } | |
1494 | ||
ca2cc333 SG |
1495 | #ifdef CONFIG_OF |
1496 | static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev) | |
1497 | { | |
1498 | struct device_node *np = pdev->dev.of_node; | |
1499 | ||
1500 | if (np) | |
1501 | return of_get_phy_mode(np); | |
1502 | ||
1503 | return -ENODEV; | |
1504 | } | |
1505 | ||
a9b2c8ef | 1506 | static void __devinit fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1507 | { |
1508 | int err, phy_reset; | |
1509 | struct device_node *np = pdev->dev.of_node; | |
1510 | ||
1511 | if (!np) | |
a9b2c8ef | 1512 | return; |
ca2cc333 SG |
1513 | |
1514 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); | |
1515 | err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset"); | |
1516 | if (err) { | |
a9b2c8ef SG |
1517 | pr_debug("FEC: failed to get gpio phy-reset: %d\n", err); |
1518 | return; | |
ca2cc333 SG |
1519 | } |
1520 | msleep(1); | |
1521 | gpio_set_value(phy_reset, 1); | |
ca2cc333 SG |
1522 | } |
1523 | #else /* CONFIG_OF */ | |
1524 | static inline int fec_get_phy_mode_dt(struct platform_device *pdev) | |
1525 | { | |
1526 | return -ENODEV; | |
1527 | } | |
1528 | ||
a9b2c8ef | 1529 | static inline void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1530 | { |
1531 | /* | |
1532 | * In case of platform probe, the reset has been done | |
1533 | * by machine code. | |
1534 | */ | |
ca2cc333 SG |
1535 | } |
1536 | #endif /* CONFIG_OF */ | |
1537 | ||
ead73183 SH |
1538 | static int __devinit |
1539 | fec_probe(struct platform_device *pdev) | |
1540 | { | |
1541 | struct fec_enet_private *fep; | |
5eb32bd0 | 1542 | struct fec_platform_data *pdata; |
ead73183 SH |
1543 | struct net_device *ndev; |
1544 | int i, irq, ret = 0; | |
1545 | struct resource *r; | |
ca2cc333 | 1546 | const struct of_device_id *of_id; |
43af940c | 1547 | static int dev_id; |
b2bccee1 | 1548 | struct pinctrl *pinctrl; |
ca2cc333 SG |
1549 | |
1550 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
1551 | if (of_id) | |
1552 | pdev->id_entry = of_id->data; | |
ead73183 SH |
1553 | |
1554 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1555 | if (!r) | |
1556 | return -ENXIO; | |
1557 | ||
1558 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1559 | if (!r) | |
1560 | return -EBUSY; | |
1561 | ||
1562 | /* Init network device */ | |
1563 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
28e2188e UKK |
1564 | if (!ndev) { |
1565 | ret = -ENOMEM; | |
1566 | goto failed_alloc_etherdev; | |
1567 | } | |
ead73183 SH |
1568 | |
1569 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1570 | ||
1571 | /* setup board info structure */ | |
1572 | fep = netdev_priv(ndev); | |
ead73183 | 1573 | |
24e531b4 | 1574 | fep->hwp = ioremap(r->start, resource_size(r)); |
e6b043d5 | 1575 | fep->pdev = pdev; |
43af940c | 1576 | fep->dev_id = dev_id++; |
ead73183 | 1577 | |
24e531b4 | 1578 | if (!fep->hwp) { |
ead73183 SH |
1579 | ret = -ENOMEM; |
1580 | goto failed_ioremap; | |
1581 | } | |
1582 | ||
1583 | platform_set_drvdata(pdev, ndev); | |
1584 | ||
ca2cc333 SG |
1585 | ret = fec_get_phy_mode_dt(pdev); |
1586 | if (ret < 0) { | |
1587 | pdata = pdev->dev.platform_data; | |
1588 | if (pdata) | |
1589 | fep->phy_interface = pdata->phy; | |
1590 | else | |
1591 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
1592 | } else { | |
1593 | fep->phy_interface = ret; | |
1594 | } | |
1595 | ||
c7c83d1c | 1596 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
ead73183 | 1597 | irq = platform_get_irq(pdev, i); |
86f9f2c8 LW |
1598 | if (irq < 0) { |
1599 | if (i) | |
1600 | break; | |
1601 | ret = irq; | |
1602 | goto failed_irq; | |
1603 | } | |
ead73183 SH |
1604 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); |
1605 | if (ret) { | |
b2b09ad6 | 1606 | while (--i >= 0) { |
ead73183 SH |
1607 | irq = platform_get_irq(pdev, i); |
1608 | free_irq(irq, ndev); | |
ead73183 SH |
1609 | } |
1610 | goto failed_irq; | |
1611 | } | |
1612 | } | |
1613 | ||
b2bccee1 SG |
1614 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1615 | if (IS_ERR(pinctrl)) { | |
1616 | ret = PTR_ERR(pinctrl); | |
1617 | goto failed_pin; | |
1618 | } | |
1619 | ||
f4d40de3 SH |
1620 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1621 | if (IS_ERR(fep->clk_ipg)) { | |
1622 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
1623 | goto failed_clk; |
1624 | } | |
f4d40de3 SH |
1625 | |
1626 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1627 | if (IS_ERR(fep->clk_ahb)) { | |
1628 | ret = PTR_ERR(fep->clk_ahb); | |
1629 | goto failed_clk; | |
1630 | } | |
1631 | ||
1632 | clk_prepare_enable(fep->clk_ahb); | |
1633 | clk_prepare_enable(fep->clk_ipg); | |
ead73183 | 1634 | |
2ca9b2aa SG |
1635 | fec_reset_phy(pdev); |
1636 | ||
8649a230 | 1637 | ret = fec_enet_init(ndev); |
ead73183 SH |
1638 | if (ret) |
1639 | goto failed_init; | |
1640 | ||
e6b043d5 BW |
1641 | ret = fec_enet_mii_init(pdev); |
1642 | if (ret) | |
1643 | goto failed_mii_init; | |
1644 | ||
03c698c9 OS |
1645 | /* Carrier starts down, phylib will bring it up */ |
1646 | netif_carrier_off(ndev); | |
1647 | ||
ead73183 SH |
1648 | ret = register_netdev(ndev); |
1649 | if (ret) | |
1650 | goto failed_register; | |
1651 | ||
1652 | return 0; | |
1653 | ||
1654 | failed_register: | |
e6b043d5 BW |
1655 | fec_enet_mii_remove(fep); |
1656 | failed_mii_init: | |
ead73183 | 1657 | failed_init: |
f4d40de3 SH |
1658 | clk_disable_unprepare(fep->clk_ahb); |
1659 | clk_disable_unprepare(fep->clk_ipg); | |
b2bccee1 | 1660 | failed_pin: |
ead73183 | 1661 | failed_clk: |
c7c83d1c | 1662 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
ead73183 SH |
1663 | irq = platform_get_irq(pdev, i); |
1664 | if (irq > 0) | |
1665 | free_irq(irq, ndev); | |
1666 | } | |
1667 | failed_irq: | |
24e531b4 | 1668 | iounmap(fep->hwp); |
ead73183 SH |
1669 | failed_ioremap: |
1670 | free_netdev(ndev); | |
28e2188e UKK |
1671 | failed_alloc_etherdev: |
1672 | release_mem_region(r->start, resource_size(r)); | |
ead73183 SH |
1673 | |
1674 | return ret; | |
1675 | } | |
1676 | ||
1677 | static int __devexit | |
1678 | fec_drv_remove(struct platform_device *pdev) | |
1679 | { | |
1680 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1681 | struct fec_enet_private *fep = netdev_priv(ndev); | |
28e2188e | 1682 | struct resource *r; |
e163cc97 | 1683 | int i; |
ead73183 | 1684 | |
e163cc97 | 1685 | unregister_netdev(ndev); |
e6b043d5 | 1686 | fec_enet_mii_remove(fep); |
e163cc97 LW |
1687 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
1688 | int irq = platform_get_irq(pdev, i); | |
1689 | if (irq > 0) | |
1690 | free_irq(irq, ndev); | |
1691 | } | |
f4d40de3 SH |
1692 | clk_disable_unprepare(fep->clk_ahb); |
1693 | clk_disable_unprepare(fep->clk_ipg); | |
24e531b4 | 1694 | iounmap(fep->hwp); |
ead73183 | 1695 | free_netdev(ndev); |
28e2188e UKK |
1696 | |
1697 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1698 | BUG_ON(!r); | |
1699 | release_mem_region(r->start, resource_size(r)); | |
1700 | ||
b3cde36c UKK |
1701 | platform_set_drvdata(pdev, NULL); |
1702 | ||
ead73183 SH |
1703 | return 0; |
1704 | } | |
1705 | ||
59d4289b | 1706 | #ifdef CONFIG_PM |
ead73183 | 1707 | static int |
87cad5c3 | 1708 | fec_suspend(struct device *dev) |
ead73183 | 1709 | { |
87cad5c3 | 1710 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1711 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1712 | |
04e5216d UKK |
1713 | if (netif_running(ndev)) { |
1714 | fec_stop(ndev); | |
1715 | netif_device_detach(ndev); | |
ead73183 | 1716 | } |
f4d40de3 SH |
1717 | clk_disable_unprepare(fep->clk_ahb); |
1718 | clk_disable_unprepare(fep->clk_ipg); | |
04e5216d | 1719 | |
ead73183 SH |
1720 | return 0; |
1721 | } | |
1722 | ||
1723 | static int | |
87cad5c3 | 1724 | fec_resume(struct device *dev) |
ead73183 | 1725 | { |
87cad5c3 | 1726 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1727 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1728 | |
f4d40de3 SH |
1729 | clk_prepare_enable(fep->clk_ahb); |
1730 | clk_prepare_enable(fep->clk_ipg); | |
04e5216d UKK |
1731 | if (netif_running(ndev)) { |
1732 | fec_restart(ndev, fep->full_duplex); | |
1733 | netif_device_attach(ndev); | |
ead73183 | 1734 | } |
04e5216d | 1735 | |
ead73183 SH |
1736 | return 0; |
1737 | } | |
1738 | ||
59d4289b DK |
1739 | static const struct dev_pm_ops fec_pm_ops = { |
1740 | .suspend = fec_suspend, | |
1741 | .resume = fec_resume, | |
1742 | .freeze = fec_suspend, | |
1743 | .thaw = fec_resume, | |
1744 | .poweroff = fec_suspend, | |
1745 | .restore = fec_resume, | |
1746 | }; | |
87cad5c3 | 1747 | #endif |
59d4289b | 1748 | |
ead73183 SH |
1749 | static struct platform_driver fec_driver = { |
1750 | .driver = { | |
b5680e0b | 1751 | .name = DRIVER_NAME, |
87cad5c3 EB |
1752 | .owner = THIS_MODULE, |
1753 | #ifdef CONFIG_PM | |
1754 | .pm = &fec_pm_ops, | |
1755 | #endif | |
ca2cc333 | 1756 | .of_match_table = fec_dt_ids, |
ead73183 | 1757 | }, |
b5680e0b | 1758 | .id_table = fec_devtype, |
87cad5c3 EB |
1759 | .probe = fec_probe, |
1760 | .remove = __devexit_p(fec_drv_remove), | |
ead73183 SH |
1761 | }; |
1762 | ||
aaca2377 | 1763 | module_platform_driver(fec_driver); |
1da177e4 LT |
1764 | |
1765 | MODULE_LICENSE("GPL"); |