]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/bitops.h> | |
6f501b17 SH |
41 | #include <linux/io.h> |
42 | #include <linux/irq.h> | |
196719ec | 43 | #include <linux/clk.h> |
ead73183 | 44 | #include <linux/platform_device.h> |
e6b043d5 | 45 | #include <linux/phy.h> |
5eb32bd0 | 46 | #include <linux/fec.h> |
ca2cc333 SG |
47 | #include <linux/of.h> |
48 | #include <linux/of_device.h> | |
49 | #include <linux/of_gpio.h> | |
50 | #include <linux/of_net.h> | |
b2bccee1 | 51 | #include <linux/pinctrl/consumer.h> |
5fa9c0fe | 52 | #include <linux/regulator/consumer.h> |
1da177e4 | 53 | |
080853af | 54 | #include <asm/cacheflush.h> |
196719ec | 55 | |
b5680e0b | 56 | #ifndef CONFIG_ARM |
1da177e4 LT |
57 | #include <asm/coldfire.h> |
58 | #include <asm/mcfsim.h> | |
196719ec | 59 | #endif |
6f501b17 | 60 | |
1da177e4 | 61 | #include "fec.h" |
1da177e4 | 62 | |
085e79ed | 63 | #if defined(CONFIG_ARM) |
196719ec SH |
64 | #define FEC_ALIGNMENT 0xf |
65 | #else | |
66 | #define FEC_ALIGNMENT 0x3 | |
67 | #endif | |
68 | ||
b5680e0b | 69 | #define DRIVER_NAME "fec" |
dc975382 | 70 | #define FEC_NAPI_WEIGHT 64 |
b5680e0b | 71 | |
baa70a5c FL |
72 | /* Pause frame feild and FIFO threshold */ |
73 | #define FEC_ENET_FCE (1 << 5) | |
74 | #define FEC_ENET_RSEM_V 0x84 | |
75 | #define FEC_ENET_RSFL_V 16 | |
76 | #define FEC_ENET_RAEM_V 0x8 | |
77 | #define FEC_ENET_RAFL_V 0x8 | |
78 | #define FEC_ENET_OPD_V 0xFFF0 | |
79 | ||
b5680e0b SG |
80 | /* Controller is ENET-MAC */ |
81 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
82 | /* Controller needs driver to swap frame */ | |
83 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
84 | /* Controller uses gasket */ |
85 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
86 | /* Controller has GBIT support */ |
87 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
ff43da86 FL |
88 | /* Controller has extend desc buffer */ |
89 | #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) | |
b5680e0b SG |
90 | |
91 | static struct platform_device_id fec_devtype[] = { | |
92 | { | |
0ca1e290 | 93 | /* keep it for coldfire */ |
b5680e0b SG |
94 | .name = DRIVER_NAME, |
95 | .driver_data = 0, | |
0ca1e290 SG |
96 | }, { |
97 | .name = "imx25-fec", | |
98 | .driver_data = FEC_QUIRK_USE_GASKET, | |
99 | }, { | |
100 | .name = "imx27-fec", | |
101 | .driver_data = 0, | |
b5680e0b SG |
102 | }, { |
103 | .name = "imx28-fec", | |
104 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
105 | }, { |
106 | .name = "imx6q-fec", | |
ff43da86 FL |
107 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
108 | FEC_QUIRK_HAS_BUFDESC_EX, | |
0ca1e290 SG |
109 | }, { |
110 | /* sentinel */ | |
111 | } | |
b5680e0b | 112 | }; |
0ca1e290 | 113 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 114 | |
ca2cc333 | 115 | enum imx_fec_type { |
a7dd3219 | 116 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
117 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
118 | IMX28_FEC, | |
230dec61 | 119 | IMX6Q_FEC, |
ca2cc333 SG |
120 | }; |
121 | ||
122 | static const struct of_device_id fec_dt_ids[] = { | |
123 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
124 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
125 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 126 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
ca2cc333 SG |
127 | { /* sentinel */ } |
128 | }; | |
129 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
130 | ||
49da97dc SG |
131 | static unsigned char macaddr[ETH_ALEN]; |
132 | module_param_array(macaddr, byte, NULL, 0); | |
133 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 134 | |
49da97dc | 135 | #if defined(CONFIG_M5272) |
1da177e4 LT |
136 | /* |
137 | * Some hardware gets it MAC address out of local flash memory. | |
138 | * if this is non-zero then assume it is the address to get MAC from. | |
139 | */ | |
140 | #if defined(CONFIG_NETtel) | |
141 | #define FEC_FLASHMAC 0xf0006006 | |
142 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
143 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
144 | #elif defined(CONFIG_CANCam) |
145 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
146 | #elif defined (CONFIG_M5272C3) |
147 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
148 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 149 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
150 | #else |
151 | #define FEC_FLASHMAC 0 | |
152 | #endif | |
43be6366 | 153 | #endif /* CONFIG_M5272 */ |
ead73183 | 154 | |
ff43da86 | 155 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) |
6b265293 | 156 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
157 | #endif |
158 | ||
22f6b860 | 159 | /* Interrupt events/masks. */ |
1da177e4 LT |
160 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
161 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
162 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
163 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
164 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
165 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
166 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
167 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
168 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
169 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
170 | ||
4bee1f9a | 171 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
dc975382 | 172 | #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) |
4bee1f9a | 173 | |
1da177e4 LT |
174 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
175 | */ | |
176 | #define PKT_MAXBUF_SIZE 1518 | |
177 | #define PKT_MINBUF_SIZE 64 | |
178 | #define PKT_MAXBLR_SIZE 1520 | |
179 | ||
1da177e4 | 180 | /* |
6b265293 | 181 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
182 | * size bits. Other FEC hardware does not, so we need to take that into |
183 | * account when setting it. | |
184 | */ | |
562d2f8c | 185 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 186 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
187 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
188 | #else | |
189 | #define OPT_FRAME_SIZE 0 | |
190 | #endif | |
191 | ||
e6b043d5 BW |
192 | /* FEC MII MMFR bits definition */ |
193 | #define FEC_MMFR_ST (1 << 30) | |
194 | #define FEC_MMFR_OP_READ (2 << 28) | |
195 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
196 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
197 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
198 | #define FEC_MMFR_TA (2 << 16) | |
199 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 200 | |
c3b084c2 | 201 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 202 | |
22f6b860 SH |
203 | /* Transmitter timeout */ |
204 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 205 | |
baa70a5c FL |
206 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
207 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
208 | ||
e163cc97 LW |
209 | static int mii_cnt; |
210 | ||
ff43da86 FL |
211 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) |
212 | { | |
213 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
214 | if (is_ex) | |
215 | return (struct bufdesc *)(ex + 1); | |
216 | else | |
217 | return bdp + 1; | |
218 | } | |
219 | ||
220 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) | |
221 | { | |
222 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
223 | if (is_ex) | |
224 | return (struct bufdesc *)(ex - 1); | |
225 | else | |
226 | return bdp - 1; | |
227 | } | |
228 | ||
b5680e0b SG |
229 | static void *swap_buffer(void *bufaddr, int len) |
230 | { | |
231 | int i; | |
232 | unsigned int *buf = bufaddr; | |
233 | ||
234 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
235 | *buf = cpu_to_be32(*buf); | |
236 | ||
237 | return bufaddr; | |
238 | } | |
239 | ||
c7621cb3 | 240 | static netdev_tx_t |
c556167f | 241 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 242 | { |
c556167f | 243 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
244 | const struct platform_device_id *id_entry = |
245 | platform_get_device_id(fep->pdev); | |
2e28532f | 246 | struct bufdesc *bdp; |
9555b31e | 247 | void *bufaddr; |
0e702ab3 | 248 | unsigned short status; |
de5fb0a0 | 249 | unsigned int index; |
1da177e4 | 250 | |
1da177e4 LT |
251 | if (!fep->link) { |
252 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 253 | return NETDEV_TX_BUSY; |
1da177e4 LT |
254 | } |
255 | ||
256 | /* Fill in a Tx ring entry */ | |
257 | bdp = fep->cur_tx; | |
258 | ||
0e702ab3 | 259 | status = bdp->cbd_sc; |
22f6b860 | 260 | |
0e702ab3 | 261 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 262 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 263 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 264 | */ |
c556167f | 265 | printk("%s: tx queue full!.\n", ndev->name); |
5b548140 | 266 | return NETDEV_TX_BUSY; |
1da177e4 | 267 | } |
1da177e4 | 268 | |
22f6b860 | 269 | /* Clear all of the status flags */ |
0e702ab3 | 270 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 271 | |
22f6b860 | 272 | /* Set buffer length and buffer pointer */ |
9555b31e | 273 | bufaddr = skb->data; |
1da177e4 LT |
274 | bdp->cbd_datlen = skb->len; |
275 | ||
276 | /* | |
22f6b860 SH |
277 | * On some FEC implementations data must be aligned on |
278 | * 4-byte boundaries. Use bounce buffers to copy data | |
279 | * and get it aligned. Ugh. | |
1da177e4 | 280 | */ |
de5fb0a0 FL |
281 | if (fep->bufdesc_ex) |
282 | index = (struct bufdesc_ex *)bdp - | |
283 | (struct bufdesc_ex *)fep->tx_bd_base; | |
284 | else | |
285 | index = bdp - fep->tx_bd_base; | |
286 | ||
9555b31e | 287 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
8a73b0bc | 288 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 289 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
290 | } |
291 | ||
b5680e0b SG |
292 | /* |
293 | * Some design made an incorrect assumption on endian mode of | |
294 | * the system that it's running on. As the result, driver has to | |
295 | * swap every frame going to and coming from the controller. | |
296 | */ | |
297 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
298 | swap_buffer(bufaddr, skb->len); | |
299 | ||
22f6b860 | 300 | /* Save skb pointer */ |
de5fb0a0 | 301 | fep->tx_skbuff[index] = skb; |
6aa20a22 | 302 | |
1da177e4 LT |
303 | /* Push the data cache so the CPM does not get stale memory |
304 | * data. | |
305 | */ | |
d1ab1f54 | 306 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 307 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 308 | |
0e702ab3 GU |
309 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
310 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 311 | */ |
0e702ab3 | 312 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 313 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 314 | bdp->cbd_sc = status; |
1da177e4 | 315 | |
ff43da86 FL |
316 | if (fep->bufdesc_ex) { |
317 | ||
318 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
319 | ebdp->cbd_bdu = 0; | |
320 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
6605b730 | 321 | fep->hwts_tx_en)) { |
ff43da86 | 322 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
6605b730 | 323 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
ff43da86 | 324 | } else { |
6605b730 | 325 | |
ff43da86 FL |
326 | ebdp->cbd_esc = BD_ENET_TX_INT; |
327 | } | |
6605b730 | 328 | } |
22f6b860 SH |
329 | /* If this was the last BD in the ring, start at the beginning again. */ |
330 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 331 | bdp = fep->tx_bd_base; |
22f6b860 | 332 | else |
ff43da86 | 333 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
1da177e4 | 334 | |
de5fb0a0 FL |
335 | fep->cur_tx = bdp; |
336 | ||
337 | if (fep->cur_tx == fep->dirty_tx) | |
c556167f | 338 | netif_stop_queue(ndev); |
1da177e4 | 339 | |
de5fb0a0 FL |
340 | /* Trigger transmission start */ |
341 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
1da177e4 | 342 | |
18a03b97 RC |
343 | skb_tx_timestamp(skb); |
344 | ||
6ed10654 | 345 | return NETDEV_TX_OK; |
1da177e4 LT |
346 | } |
347 | ||
14109a59 FL |
348 | /* Init RX & TX buffer descriptors |
349 | */ | |
350 | static void fec_enet_bd_init(struct net_device *dev) | |
351 | { | |
352 | struct fec_enet_private *fep = netdev_priv(dev); | |
353 | struct bufdesc *bdp; | |
354 | unsigned int i; | |
355 | ||
356 | /* Initialize the receive buffer descriptors. */ | |
357 | bdp = fep->rx_bd_base; | |
358 | for (i = 0; i < RX_RING_SIZE; i++) { | |
359 | ||
360 | /* Initialize the BD for every fragment in the page. */ | |
361 | if (bdp->cbd_bufaddr) | |
362 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
363 | else | |
364 | bdp->cbd_sc = 0; | |
365 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
366 | } | |
367 | ||
368 | /* Set the last buffer to wrap */ | |
369 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
370 | bdp->cbd_sc |= BD_SC_WRAP; | |
371 | ||
372 | fep->cur_rx = fep->rx_bd_base; | |
373 | ||
374 | /* ...and the same for transmit */ | |
375 | bdp = fep->tx_bd_base; | |
376 | fep->cur_tx = bdp; | |
377 | for (i = 0; i < TX_RING_SIZE; i++) { | |
378 | ||
379 | /* Initialize the BD for every fragment in the page. */ | |
380 | bdp->cbd_sc = 0; | |
381 | if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { | |
382 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
383 | fep->tx_skbuff[i] = NULL; | |
384 | } | |
385 | bdp->cbd_bufaddr = 0; | |
386 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
387 | } | |
388 | ||
389 | /* Set the last buffer to wrap */ | |
390 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
391 | bdp->cbd_sc |= BD_SC_WRAP; | |
392 | fep->dirty_tx = bdp; | |
393 | } | |
394 | ||
45993653 UKK |
395 | /* This function is called to start or restart the FEC during a link |
396 | * change. This only happens when switching between half and full | |
397 | * duplex. | |
398 | */ | |
1da177e4 | 399 | static void |
45993653 | 400 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 401 | { |
c556167f | 402 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
403 | const struct platform_device_id *id_entry = |
404 | platform_get_device_id(fep->pdev); | |
405 | int i; | |
cd1f402c UKK |
406 | u32 temp_mac[2]; |
407 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 408 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 409 | |
45993653 UKK |
410 | /* Whack a reset. We should wait for this. */ |
411 | writel(1, fep->hwp + FEC_ECNTRL); | |
412 | udelay(10); | |
1da177e4 | 413 | |
45993653 UKK |
414 | /* |
415 | * enet-mac reset will reset mac address registers too, | |
416 | * so need to reconfigure it. | |
417 | */ | |
418 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
419 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
420 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
421 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
422 | } | |
1da177e4 | 423 | |
45993653 UKK |
424 | /* Clear any outstanding interrupt. */ |
425 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 426 | |
45993653 UKK |
427 | /* Reset all multicast. */ |
428 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
429 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
430 | #ifndef CONFIG_M5272 | |
431 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
432 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
433 | #endif | |
1da177e4 | 434 | |
45993653 UKK |
435 | /* Set maximum receive buffer size. */ |
436 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 437 | |
14109a59 FL |
438 | fec_enet_bd_init(ndev); |
439 | ||
45993653 UKK |
440 | /* Set receive and transmit descriptor base. */ |
441 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
ff43da86 FL |
442 | if (fep->bufdesc_ex) |
443 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) | |
444 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
445 | else | |
446 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) | |
447 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
45993653 | 448 | |
45993653 | 449 | |
45993653 UKK |
450 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
451 | if (fep->tx_skbuff[i]) { | |
452 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
453 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 454 | } |
45993653 | 455 | } |
97b72e43 | 456 | |
45993653 UKK |
457 | /* Enable MII mode */ |
458 | if (duplex) { | |
cd1f402c | 459 | /* FD enable */ |
45993653 UKK |
460 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
461 | } else { | |
cd1f402c UKK |
462 | /* No Rcv on Xmit */ |
463 | rcntl |= 0x02; | |
45993653 UKK |
464 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
465 | } | |
cd1f402c | 466 | |
45993653 UKK |
467 | fep->full_duplex = duplex; |
468 | ||
469 | /* Set MII speed */ | |
470 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
471 | ||
472 | /* | |
473 | * The phy interface and speed need to get configured | |
474 | * differently on enet-mac. | |
475 | */ | |
476 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
477 | /* Enable flow control and length check */ |
478 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 479 | |
230dec61 SG |
480 | /* RGMII, RMII or MII */ |
481 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
482 | rcntl |= (1 << 6); | |
483 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 484 | rcntl |= (1 << 8); |
45993653 | 485 | else |
cd1f402c | 486 | rcntl &= ~(1 << 8); |
45993653 | 487 | |
230dec61 SG |
488 | /* 1G, 100M or 10M */ |
489 | if (fep->phy_dev) { | |
490 | if (fep->phy_dev->speed == SPEED_1000) | |
491 | ecntl |= (1 << 5); | |
492 | else if (fep->phy_dev->speed == SPEED_100) | |
493 | rcntl &= ~(1 << 9); | |
494 | else | |
495 | rcntl |= (1 << 9); | |
496 | } | |
45993653 UKK |
497 | } else { |
498 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 499 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 500 | u32 cfgr; |
45993653 UKK |
501 | /* disable the gasket and wait */ |
502 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
503 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
504 | udelay(1); | |
505 | ||
506 | /* | |
507 | * configure the gasket: | |
508 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 509 | * MII, 25 MHz, no loopback, no echo |
45993653 | 510 | */ |
8d82f219 EB |
511 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
512 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
513 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
514 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
515 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
516 | |
517 | /* re-enable the gasket */ | |
518 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 519 | } |
45993653 UKK |
520 | #endif |
521 | } | |
baa70a5c FL |
522 | |
523 | /* enable pause frame*/ | |
524 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
525 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
526 | fep->phy_dev && fep->phy_dev->pause)) { | |
527 | rcntl |= FEC_ENET_FCE; | |
528 | ||
529 | /* set FIFO thresh hold parameter to reduce overrun */ | |
530 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); | |
531 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
532 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
533 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
534 | ||
535 | /* OPD */ | |
536 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
537 | } else { | |
538 | rcntl &= ~FEC_ENET_FCE; | |
539 | } | |
540 | ||
cd1f402c | 541 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 542 | |
230dec61 SG |
543 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
544 | /* enable ENET endian swap */ | |
545 | ecntl |= (1 << 8); | |
546 | /* enable ENET store and forward mode */ | |
547 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
548 | } | |
549 | ||
ff43da86 FL |
550 | if (fep->bufdesc_ex) |
551 | ecntl |= (1 << 4); | |
6605b730 | 552 | |
45993653 | 553 | /* And last, enable the transmit and receive processing */ |
230dec61 | 554 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
555 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
556 | ||
ff43da86 FL |
557 | if (fep->bufdesc_ex) |
558 | fec_ptp_start_cyclecounter(ndev); | |
559 | ||
45993653 UKK |
560 | /* Enable interrupts we wish to service */ |
561 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
562 | } | |
563 | ||
564 | static void | |
565 | fec_stop(struct net_device *ndev) | |
566 | { | |
567 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
568 | const struct platform_device_id *id_entry = |
569 | platform_get_device_id(fep->pdev); | |
42431dc2 | 570 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
571 | |
572 | /* We cannot expect a graceful transmit stop without link !!! */ | |
573 | if (fep->link) { | |
574 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
575 | udelay(10); | |
576 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
577 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
578 | } | |
579 | ||
580 | /* Whack a reset. We should wait for this. */ | |
581 | writel(1, fep->hwp + FEC_ECNTRL); | |
582 | udelay(10); | |
583 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
584 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
585 | |
586 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 587 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 588 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
589 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
590 | } | |
1da177e4 LT |
591 | } |
592 | ||
593 | ||
45993653 UKK |
594 | static void |
595 | fec_timeout(struct net_device *ndev) | |
596 | { | |
597 | struct fec_enet_private *fep = netdev_priv(ndev); | |
598 | ||
599 | ndev->stats.tx_errors++; | |
600 | ||
601 | fec_restart(ndev, fep->full_duplex); | |
602 | netif_wake_queue(ndev); | |
603 | } | |
604 | ||
1da177e4 | 605 | static void |
c556167f | 606 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
607 | { |
608 | struct fec_enet_private *fep; | |
2e28532f | 609 | struct bufdesc *bdp; |
0e702ab3 | 610 | unsigned short status; |
1da177e4 | 611 | struct sk_buff *skb; |
de5fb0a0 | 612 | int index = 0; |
1da177e4 | 613 | |
c556167f | 614 | fep = netdev_priv(ndev); |
1da177e4 LT |
615 | bdp = fep->dirty_tx; |
616 | ||
de5fb0a0 FL |
617 | /* get next bdp of dirty_tx */ |
618 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
619 | bdp = fep->tx_bd_base; | |
620 | else | |
621 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
622 | ||
0e702ab3 | 623 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
de5fb0a0 FL |
624 | |
625 | /* current queue is empty */ | |
626 | if (bdp == fep->cur_tx) | |
f0b3fbea SH |
627 | break; |
628 | ||
de5fb0a0 FL |
629 | if (fep->bufdesc_ex) |
630 | index = (struct bufdesc_ex *)bdp - | |
631 | (struct bufdesc_ex *)fep->tx_bd_base; | |
632 | else | |
633 | index = bdp - fep->tx_bd_base; | |
634 | ||
d1ab1f54 UKK |
635 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
636 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 637 | bdp->cbd_bufaddr = 0; |
1da177e4 | 638 | |
de5fb0a0 FL |
639 | skb = fep->tx_skbuff[index]; |
640 | ||
1da177e4 | 641 | /* Check for errors. */ |
0e702ab3 | 642 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
643 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
644 | BD_ENET_TX_CSL)) { | |
c556167f | 645 | ndev->stats.tx_errors++; |
0e702ab3 | 646 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 647 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 648 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 649 | ndev->stats.tx_window_errors++; |
0e702ab3 | 650 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 651 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 652 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 653 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 654 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 655 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 656 | } else { |
c556167f | 657 | ndev->stats.tx_packets++; |
1da177e4 LT |
658 | } |
659 | ||
ff43da86 FL |
660 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
661 | fep->bufdesc_ex) { | |
6605b730 FL |
662 | struct skb_shared_hwtstamps shhwtstamps; |
663 | unsigned long flags; | |
ff43da86 | 664 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 FL |
665 | |
666 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
667 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
668 | shhwtstamps.hwtstamp = ns_to_ktime( | |
ff43da86 | 669 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
670 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
671 | skb_tstamp_tx(skb, &shhwtstamps); | |
672 | } | |
ff43da86 | 673 | |
0e702ab3 | 674 | if (status & BD_ENET_TX_READY) |
1da177e4 | 675 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 676 | |
1da177e4 LT |
677 | /* Deferred means some collisions occurred during transmit, |
678 | * but we eventually sent the packet OK. | |
679 | */ | |
0e702ab3 | 680 | if (status & BD_ENET_TX_DEF) |
c556167f | 681 | ndev->stats.collisions++; |
6aa20a22 | 682 | |
22f6b860 | 683 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 684 | dev_kfree_skb_any(skb); |
de5fb0a0 FL |
685 | fep->tx_skbuff[index] = NULL; |
686 | ||
687 | fep->dirty_tx = bdp; | |
6aa20a22 | 688 | |
22f6b860 | 689 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 690 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
691 | bdp = fep->tx_bd_base; |
692 | else | |
ff43da86 | 693 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
6aa20a22 | 694 | |
22f6b860 | 695 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 696 | */ |
de5fb0a0 | 697 | if (fep->dirty_tx != fep->cur_tx) { |
c556167f UKK |
698 | if (netif_queue_stopped(ndev)) |
699 | netif_wake_queue(ndev); | |
1da177e4 LT |
700 | } |
701 | } | |
de5fb0a0 | 702 | return; |
1da177e4 LT |
703 | } |
704 | ||
705 | ||
706 | /* During a receive, the cur_rx points to the current incoming buffer. | |
707 | * When we update through the ring, if the next incoming buffer has | |
708 | * not been given to the system, we just set the empty indicator, | |
709 | * effectively tossing the packet. | |
710 | */ | |
dc975382 FL |
711 | static int |
712 | fec_enet_rx(struct net_device *ndev, int budget) | |
1da177e4 | 713 | { |
c556167f | 714 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
715 | const struct platform_device_id *id_entry = |
716 | platform_get_device_id(fep->pdev); | |
2e28532f | 717 | struct bufdesc *bdp; |
0e702ab3 | 718 | unsigned short status; |
1da177e4 LT |
719 | struct sk_buff *skb; |
720 | ushort pkt_len; | |
721 | __u8 *data; | |
dc975382 | 722 | int pkt_received = 0; |
6aa20a22 | 723 | |
0e702ab3 GU |
724 | #ifdef CONFIG_M532x |
725 | flush_cache_all(); | |
6aa20a22 | 726 | #endif |
1da177e4 | 727 | |
1da177e4 LT |
728 | /* First, grab all of the stats for the incoming packet. |
729 | * These get messed up if we get called due to a busy condition. | |
730 | */ | |
731 | bdp = fep->cur_rx; | |
732 | ||
22f6b860 | 733 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 734 | |
dc975382 FL |
735 | if (pkt_received >= budget) |
736 | break; | |
737 | pkt_received++; | |
738 | ||
22f6b860 SH |
739 | /* Since we have allocated space to hold a complete frame, |
740 | * the last indicator should be set. | |
741 | */ | |
742 | if ((status & BD_ENET_RX_LAST) == 0) | |
743 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 744 | |
22f6b860 SH |
745 | if (!fep->opened) |
746 | goto rx_processing_done; | |
1da177e4 | 747 | |
22f6b860 SH |
748 | /* Check for errors. */ |
749 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 750 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 751 | ndev->stats.rx_errors++; |
22f6b860 SH |
752 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
753 | /* Frame too long or too short. */ | |
c556167f | 754 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
755 | } |
756 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 757 | ndev->stats.rx_frame_errors++; |
22f6b860 | 758 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 759 | ndev->stats.rx_crc_errors++; |
22f6b860 | 760 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 761 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 762 | } |
1da177e4 | 763 | |
22f6b860 SH |
764 | /* Report late collisions as a frame error. |
765 | * On this error, the BD is closed, but we don't know what we | |
766 | * have in the buffer. So, just drop this frame on the floor. | |
767 | */ | |
768 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
769 | ndev->stats.rx_errors++; |
770 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
771 | goto rx_processing_done; |
772 | } | |
1da177e4 | 773 | |
22f6b860 | 774 | /* Process the incoming frame. */ |
c556167f | 775 | ndev->stats.rx_packets++; |
22f6b860 | 776 | pkt_len = bdp->cbd_datlen; |
c556167f | 777 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 778 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 779 | |
d1ab1f54 UKK |
780 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
781 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 782 | |
b5680e0b SG |
783 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
784 | swap_buffer(data, pkt_len); | |
785 | ||
22f6b860 SH |
786 | /* This does 16 byte alignment, exactly what we need. |
787 | * The packet length includes FCS, but we don't want to | |
788 | * include that when passing upstream as it messes up | |
789 | * bridging applications. | |
790 | */ | |
b72061a3 | 791 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 792 | |
8549889c | 793 | if (unlikely(!skb)) { |
22f6b860 | 794 | printk("%s: Memory squeeze, dropping packet.\n", |
c556167f UKK |
795 | ndev->name); |
796 | ndev->stats.rx_dropped++; | |
22f6b860 | 797 | } else { |
8549889c | 798 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
799 | skb_put(skb, pkt_len - 4); /* Make room */ |
800 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 801 | skb->protocol = eth_type_trans(skb, ndev); |
ff43da86 | 802 | |
6605b730 | 803 | /* Get receive timestamp from the skb */ |
ff43da86 | 804 | if (fep->hwts_rx_en && fep->bufdesc_ex) { |
6605b730 FL |
805 | struct skb_shared_hwtstamps *shhwtstamps = |
806 | skb_hwtstamps(skb); | |
807 | unsigned long flags; | |
ff43da86 FL |
808 | struct bufdesc_ex *ebdp = |
809 | (struct bufdesc_ex *)bdp; | |
6605b730 FL |
810 | |
811 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
812 | ||
813 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
814 | shhwtstamps->hwtstamp = ns_to_ktime( | |
ff43da86 | 815 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
816 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
817 | } | |
ff43da86 | 818 | |
18a03b97 | 819 | if (!skb_defer_rx_timestamp(skb)) |
dc975382 | 820 | napi_gro_receive(&fep->napi, skb); |
22f6b860 | 821 | } |
f0b3fbea | 822 | |
d1ab1f54 UKK |
823 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
824 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
825 | rx_processing_done: |
826 | /* Clear the status flags for this buffer */ | |
827 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 828 | |
22f6b860 SH |
829 | /* Mark the buffer empty */ |
830 | status |= BD_ENET_RX_EMPTY; | |
831 | bdp->cbd_sc = status; | |
6aa20a22 | 832 | |
ff43da86 FL |
833 | if (fep->bufdesc_ex) { |
834 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
835 | ||
836 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
837 | ebdp->cbd_prot = 0; | |
838 | ebdp->cbd_bdu = 0; | |
839 | } | |
6605b730 | 840 | |
22f6b860 SH |
841 | /* Update BD pointer to next entry */ |
842 | if (status & BD_ENET_RX_WRAP) | |
843 | bdp = fep->rx_bd_base; | |
844 | else | |
ff43da86 | 845 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
22f6b860 SH |
846 | /* Doing this here will keep the FEC running while we process |
847 | * incoming frames. On a heavily loaded network, we should be | |
848 | * able to keep up at the expense of system resources. | |
849 | */ | |
850 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
851 | } | |
2e28532f | 852 | fep->cur_rx = bdp; |
1da177e4 | 853 | |
dc975382 | 854 | return pkt_received; |
1da177e4 LT |
855 | } |
856 | ||
45993653 UKK |
857 | static irqreturn_t |
858 | fec_enet_interrupt(int irq, void *dev_id) | |
859 | { | |
860 | struct net_device *ndev = dev_id; | |
861 | struct fec_enet_private *fep = netdev_priv(ndev); | |
862 | uint int_events; | |
863 | irqreturn_t ret = IRQ_NONE; | |
864 | ||
865 | do { | |
866 | int_events = readl(fep->hwp + FEC_IEVENT); | |
867 | writel(int_events, fep->hwp + FEC_IEVENT); | |
868 | ||
de5fb0a0 | 869 | if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { |
45993653 | 870 | ret = IRQ_HANDLED; |
dc975382 FL |
871 | |
872 | /* Disable the RX interrupt */ | |
873 | if (napi_schedule_prep(&fep->napi)) { | |
874 | writel(FEC_RX_DISABLED_IMASK, | |
875 | fep->hwp + FEC_IMASK); | |
876 | __napi_schedule(&fep->napi); | |
877 | } | |
45993653 UKK |
878 | } |
879 | ||
45993653 UKK |
880 | if (int_events & FEC_ENET_MII) { |
881 | ret = IRQ_HANDLED; | |
882 | complete(&fep->mdio_done); | |
883 | } | |
884 | } while (int_events); | |
885 | ||
886 | return ret; | |
887 | } | |
888 | ||
dc975382 FL |
889 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
890 | { | |
891 | struct net_device *ndev = napi->dev; | |
892 | int pkts = fec_enet_rx(ndev, budget); | |
893 | struct fec_enet_private *fep = netdev_priv(ndev); | |
45993653 | 894 | |
de5fb0a0 FL |
895 | fec_enet_tx(ndev); |
896 | ||
dc975382 FL |
897 | if (pkts < budget) { |
898 | napi_complete(napi); | |
899 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
900 | } | |
901 | return pkts; | |
902 | } | |
45993653 | 903 | |
e6b043d5 | 904 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 905 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 906 | { |
c556167f | 907 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 908 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 909 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 910 | |
49da97dc SG |
911 | /* |
912 | * try to get mac address in following order: | |
913 | * | |
914 | * 1) module parameter via kernel command line in form | |
915 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
916 | */ | |
917 | iap = macaddr; | |
918 | ||
ca2cc333 SG |
919 | #ifdef CONFIG_OF |
920 | /* | |
921 | * 2) from device tree data | |
922 | */ | |
923 | if (!is_valid_ether_addr(iap)) { | |
924 | struct device_node *np = fep->pdev->dev.of_node; | |
925 | if (np) { | |
926 | const char *mac = of_get_mac_address(np); | |
927 | if (mac) | |
928 | iap = (unsigned char *) mac; | |
929 | } | |
930 | } | |
931 | #endif | |
932 | ||
49da97dc | 933 | /* |
ca2cc333 | 934 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
935 | */ |
936 | if (!is_valid_ether_addr(iap)) { | |
937 | #ifdef CONFIG_M5272 | |
938 | if (FEC_FLASHMAC) | |
939 | iap = (unsigned char *)FEC_FLASHMAC; | |
940 | #else | |
941 | if (pdata) | |
589efdc7 | 942 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
943 | #endif |
944 | } | |
945 | ||
946 | /* | |
ca2cc333 | 947 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
948 | */ |
949 | if (!is_valid_ether_addr(iap)) { | |
950 | *((unsigned long *) &tmpaddr[0]) = | |
951 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
952 | *((unsigned short *) &tmpaddr[4]) = | |
953 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 954 | iap = &tmpaddr[0]; |
1da177e4 LT |
955 | } |
956 | ||
c556167f | 957 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 958 | |
49da97dc SG |
959 | /* Adjust MAC if using macaddr */ |
960 | if (iap == macaddr) | |
43af940c | 961 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
962 | } |
963 | ||
e6b043d5 | 964 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 965 | |
e6b043d5 BW |
966 | /* |
967 | * Phy section | |
968 | */ | |
c556167f | 969 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 970 | { |
c556167f | 971 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 BW |
972 | struct phy_device *phy_dev = fep->phy_dev; |
973 | unsigned long flags; | |
1da177e4 | 974 | |
e6b043d5 | 975 | int status_change = 0; |
1da177e4 | 976 | |
e6b043d5 | 977 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 978 | |
e6b043d5 BW |
979 | /* Prevent a state halted on mii error */ |
980 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
981 | phy_dev->state = PHY_RESUMING; | |
982 | goto spin_unlock; | |
983 | } | |
1da177e4 | 984 | |
e6b043d5 | 985 | if (phy_dev->link) { |
d97e7497 | 986 | if (!fep->link) { |
6ea0722f | 987 | fep->link = phy_dev->link; |
e6b043d5 BW |
988 | status_change = 1; |
989 | } | |
1da177e4 | 990 | |
d97e7497 LS |
991 | if (fep->full_duplex != phy_dev->duplex) |
992 | status_change = 1; | |
993 | ||
994 | if (phy_dev->speed != fep->speed) { | |
995 | fep->speed = phy_dev->speed; | |
996 | status_change = 1; | |
997 | } | |
998 | ||
999 | /* if any of the above changed restart the FEC */ | |
1000 | if (status_change) | |
c556167f | 1001 | fec_restart(ndev, phy_dev->duplex); |
d97e7497 LS |
1002 | } else { |
1003 | if (fep->link) { | |
c556167f | 1004 | fec_stop(ndev); |
d97e7497 LS |
1005 | status_change = 1; |
1006 | } | |
1da177e4 | 1007 | } |
6aa20a22 | 1008 | |
e6b043d5 BW |
1009 | spin_unlock: |
1010 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 1011 | |
e6b043d5 BW |
1012 | if (status_change) |
1013 | phy_print_status(phy_dev); | |
1014 | } | |
1da177e4 | 1015 | |
e6b043d5 | 1016 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 1017 | { |
e6b043d5 | 1018 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1019 | unsigned long time_left; |
1da177e4 | 1020 | |
e6b043d5 | 1021 | fep->mii_timeout = 0; |
97b72e43 | 1022 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
1023 | |
1024 | /* start a read op */ | |
1025 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
1026 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
1027 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
1028 | ||
1029 | /* wait for end of transfer */ | |
97b72e43 BS |
1030 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1031 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1032 | if (time_left == 0) { | |
1033 | fep->mii_timeout = 1; | |
1034 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
1035 | return -ETIMEDOUT; | |
1da177e4 | 1036 | } |
1da177e4 | 1037 | |
e6b043d5 BW |
1038 | /* return value */ |
1039 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 1040 | } |
6aa20a22 | 1041 | |
e6b043d5 BW |
1042 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
1043 | u16 value) | |
1da177e4 | 1044 | { |
e6b043d5 | 1045 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1046 | unsigned long time_left; |
1da177e4 | 1047 | |
e6b043d5 | 1048 | fep->mii_timeout = 0; |
97b72e43 | 1049 | init_completion(&fep->mdio_done); |
1da177e4 | 1050 | |
862f0982 SG |
1051 | /* start a write op */ |
1052 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1053 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1054 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1055 | fep->hwp + FEC_MII_DATA); | |
1056 | ||
1057 | /* wait for end of transfer */ | |
97b72e43 BS |
1058 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1059 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1060 | if (time_left == 0) { | |
1061 | fep->mii_timeout = 1; | |
1062 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
1063 | return -ETIMEDOUT; | |
e6b043d5 | 1064 | } |
1da177e4 | 1065 | |
e6b043d5 BW |
1066 | return 0; |
1067 | } | |
1da177e4 | 1068 | |
e6b043d5 | 1069 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 1070 | { |
e6b043d5 | 1071 | return 0; |
1da177e4 LT |
1072 | } |
1073 | ||
c556167f | 1074 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1075 | { |
c556167f | 1076 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
1077 | const struct platform_device_id *id_entry = |
1078 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1079 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1080 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1081 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1082 | int phy_id; | |
43af940c | 1083 | int dev_id = fep->dev_id; |
562d2f8c | 1084 | |
418bd0d4 BW |
1085 | fep->phy_dev = NULL; |
1086 | ||
6fcc040f GU |
1087 | /* check for attached phy */ |
1088 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
1089 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
1090 | continue; | |
1091 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
1092 | continue; | |
1093 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
1094 | continue; | |
b5680e0b SG |
1095 | if (dev_id--) |
1096 | continue; | |
6fcc040f GU |
1097 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
1098 | break; | |
e6b043d5 | 1099 | } |
1da177e4 | 1100 | |
6fcc040f | 1101 | if (phy_id >= PHY_MAX_ADDR) { |
a7dd3219 LW |
1102 | printk(KERN_INFO |
1103 | "%s: no PHY, assuming direct connection to switch\n", | |
1104 | ndev->name); | |
ea51ade9 | 1105 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
1106 | phy_id = 0; |
1107 | } | |
1108 | ||
a7ed07d5 | 1109 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
f9a8f83b | 1110 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
230dec61 | 1111 | fep->phy_interface); |
6fcc040f | 1112 | if (IS_ERR(phy_dev)) { |
c556167f | 1113 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); |
6fcc040f | 1114 | return PTR_ERR(phy_dev); |
e6b043d5 | 1115 | } |
1da177e4 | 1116 | |
e6b043d5 | 1117 | /* mask with MAC supported features */ |
baa70a5c | 1118 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1119 | phy_dev->supported &= PHY_GBIT_FEATURES; |
baa70a5c FL |
1120 | phy_dev->supported |= SUPPORTED_Pause; |
1121 | } | |
230dec61 SG |
1122 | else |
1123 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1124 | ||
e6b043d5 | 1125 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1126 | |
e6b043d5 BW |
1127 | fep->phy_dev = phy_dev; |
1128 | fep->link = 0; | |
1129 | fep->full_duplex = 0; | |
1da177e4 | 1130 | |
a7dd3219 LW |
1131 | printk(KERN_INFO |
1132 | "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
1133 | ndev->name, | |
418bd0d4 BW |
1134 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
1135 | fep->phy_dev->irq); | |
1136 | ||
e6b043d5 | 1137 | return 0; |
1da177e4 LT |
1138 | } |
1139 | ||
e6b043d5 | 1140 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1141 | { |
b5680e0b | 1142 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1143 | struct net_device *ndev = platform_get_drvdata(pdev); |
1144 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1145 | const struct platform_device_id *id_entry = |
1146 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1147 | int err = -ENXIO, i; |
6b265293 | 1148 | |
b5680e0b SG |
1149 | /* |
1150 | * The dual fec interfaces are not equivalent with enet-mac. | |
1151 | * Here are the differences: | |
1152 | * | |
1153 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1154 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1155 | * - external phys can only be configured by fec0 | |
1156 | * | |
1157 | * That is to say fec1 can not work independently. It only works | |
1158 | * when fec0 is working. The reason behind this design is that the | |
1159 | * second interface is added primarily for Switch mode. | |
1160 | * | |
1161 | * Because of the last point above, both phys are attached on fec0 | |
1162 | * mdio interface in board design, and need to be configured by | |
1163 | * fec0 mii_bus. | |
1164 | */ | |
43af940c | 1165 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1166 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1167 | if (mii_cnt && fec0_mii_bus) { |
1168 | fep->mii_bus = fec0_mii_bus; | |
1169 | mii_cnt++; | |
1170 | return 0; | |
1171 | } | |
1172 | return -ENOENT; | |
b5680e0b SG |
1173 | } |
1174 | ||
e6b043d5 | 1175 | fep->mii_timeout = 0; |
1da177e4 | 1176 | |
e6b043d5 BW |
1177 | /* |
1178 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1179 | * |
1180 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1181 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1182 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1183 | * document. | |
e6b043d5 | 1184 | */ |
f4d40de3 | 1185 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1186 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1187 | fep->phy_speed--; | |
1188 | fep->phy_speed <<= 1; | |
e6b043d5 | 1189 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1190 | |
e6b043d5 BW |
1191 | fep->mii_bus = mdiobus_alloc(); |
1192 | if (fep->mii_bus == NULL) { | |
1193 | err = -ENOMEM; | |
1194 | goto err_out; | |
1da177e4 LT |
1195 | } |
1196 | ||
e6b043d5 BW |
1197 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1198 | fep->mii_bus->read = fec_enet_mdio_read; | |
1199 | fep->mii_bus->write = fec_enet_mdio_write; | |
1200 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1201 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1202 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1203 | fep->mii_bus->priv = fep; |
1204 | fep->mii_bus->parent = &pdev->dev; | |
1205 | ||
1206 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1207 | if (!fep->mii_bus->irq) { | |
1208 | err = -ENOMEM; | |
1209 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1210 | } |
1211 | ||
e6b043d5 BW |
1212 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1213 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1214 | |
e6b043d5 BW |
1215 | if (mdiobus_register(fep->mii_bus)) |
1216 | goto err_out_free_mdio_irq; | |
1da177e4 | 1217 | |
e163cc97 LW |
1218 | mii_cnt++; |
1219 | ||
b5680e0b SG |
1220 | /* save fec0 mii_bus */ |
1221 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1222 | fec0_mii_bus = fep->mii_bus; | |
1223 | ||
e6b043d5 | 1224 | return 0; |
1da177e4 | 1225 | |
e6b043d5 BW |
1226 | err_out_free_mdio_irq: |
1227 | kfree(fep->mii_bus->irq); | |
1228 | err_out_free_mdiobus: | |
1229 | mdiobus_free(fep->mii_bus); | |
1230 | err_out: | |
1231 | return err; | |
1da177e4 LT |
1232 | } |
1233 | ||
e6b043d5 | 1234 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1235 | { |
e163cc97 LW |
1236 | if (--mii_cnt == 0) { |
1237 | mdiobus_unregister(fep->mii_bus); | |
1238 | kfree(fep->mii_bus->irq); | |
1239 | mdiobus_free(fep->mii_bus); | |
1240 | } | |
1da177e4 LT |
1241 | } |
1242 | ||
c556167f | 1243 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1244 | struct ethtool_cmd *cmd) |
1da177e4 | 1245 | { |
c556167f | 1246 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1247 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1248 | |
e6b043d5 BW |
1249 | if (!phydev) |
1250 | return -ENODEV; | |
1da177e4 | 1251 | |
e6b043d5 | 1252 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1253 | } |
1254 | ||
c556167f | 1255 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1256 | struct ethtool_cmd *cmd) |
1da177e4 | 1257 | { |
c556167f | 1258 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1259 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1260 | |
e6b043d5 BW |
1261 | if (!phydev) |
1262 | return -ENODEV; | |
1da177e4 | 1263 | |
e6b043d5 | 1264 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1265 | } |
1266 | ||
c556167f | 1267 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1268 | struct ethtool_drvinfo *info) |
1da177e4 | 1269 | { |
c556167f | 1270 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1271 | |
7826d43f JP |
1272 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
1273 | sizeof(info->driver)); | |
1274 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
1275 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1276 | } |
1277 | ||
5ebae489 FL |
1278 | static int fec_enet_get_ts_info(struct net_device *ndev, |
1279 | struct ethtool_ts_info *info) | |
1280 | { | |
1281 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1282 | ||
1283 | if (fep->bufdesc_ex) { | |
1284 | ||
1285 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1286 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1287 | SOF_TIMESTAMPING_SOFTWARE | | |
1288 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1289 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1290 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1291 | if (fep->ptp_clock) | |
1292 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
1293 | else | |
1294 | info->phc_index = -1; | |
1295 | ||
1296 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
1297 | (1 << HWTSTAMP_TX_ON); | |
1298 | ||
1299 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
1300 | (1 << HWTSTAMP_FILTER_ALL); | |
1301 | return 0; | |
1302 | } else { | |
1303 | return ethtool_op_get_ts_info(ndev, info); | |
1304 | } | |
1305 | } | |
1306 | ||
baa70a5c FL |
1307 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
1308 | struct ethtool_pauseparam *pause) | |
1309 | { | |
1310 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1311 | ||
1312 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
1313 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
1314 | pause->rx_pause = pause->tx_pause; | |
1315 | } | |
1316 | ||
1317 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
1318 | struct ethtool_pauseparam *pause) | |
1319 | { | |
1320 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1321 | ||
1322 | if (pause->tx_pause != pause->rx_pause) { | |
1323 | netdev_info(ndev, | |
1324 | "hardware only support enable/disable both tx and rx"); | |
1325 | return -EINVAL; | |
1326 | } | |
1327 | ||
1328 | fep->pause_flag = 0; | |
1329 | ||
1330 | /* tx pause must be same as rx pause */ | |
1331 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
1332 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
1333 | ||
1334 | if (pause->rx_pause || pause->autoneg) { | |
1335 | fep->phy_dev->supported |= ADVERTISED_Pause; | |
1336 | fep->phy_dev->advertising |= ADVERTISED_Pause; | |
1337 | } else { | |
1338 | fep->phy_dev->supported &= ~ADVERTISED_Pause; | |
1339 | fep->phy_dev->advertising &= ~ADVERTISED_Pause; | |
1340 | } | |
1341 | ||
1342 | if (pause->autoneg) { | |
1343 | if (netif_running(ndev)) | |
1344 | fec_stop(ndev); | |
1345 | phy_start_aneg(fep->phy_dev); | |
1346 | } | |
1347 | if (netif_running(ndev)) | |
1348 | fec_restart(ndev, 0); | |
1349 | ||
1350 | return 0; | |
1351 | } | |
1352 | ||
9b07be4b | 1353 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
baa70a5c FL |
1354 | .get_pauseparam = fec_enet_get_pauseparam, |
1355 | .set_pauseparam = fec_enet_set_pauseparam, | |
e6b043d5 BW |
1356 | .get_settings = fec_enet_get_settings, |
1357 | .set_settings = fec_enet_set_settings, | |
1358 | .get_drvinfo = fec_enet_get_drvinfo, | |
1359 | .get_link = ethtool_op_get_link, | |
5ebae489 | 1360 | .get_ts_info = fec_enet_get_ts_info, |
e6b043d5 | 1361 | }; |
1da177e4 | 1362 | |
c556167f | 1363 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1364 | { |
c556167f | 1365 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1366 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1367 | |
c556167f | 1368 | if (!netif_running(ndev)) |
e6b043d5 | 1369 | return -EINVAL; |
1da177e4 | 1370 | |
e6b043d5 BW |
1371 | if (!phydev) |
1372 | return -ENODEV; | |
1373 | ||
ff43da86 | 1374 | if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) |
6605b730 | 1375 | return fec_ptp_ioctl(ndev, rq, cmd); |
ff43da86 | 1376 | |
28b04113 | 1377 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1378 | } |
1379 | ||
c556167f | 1380 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1381 | { |
c556167f | 1382 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1383 | unsigned int i; |
f0b3fbea SH |
1384 | struct sk_buff *skb; |
1385 | struct bufdesc *bdp; | |
1386 | ||
1387 | bdp = fep->rx_bd_base; | |
1388 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1389 | skb = fep->rx_skbuff[i]; | |
1390 | ||
1391 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1392 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1393 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1394 | if (skb) | |
1395 | dev_kfree_skb(skb); | |
ff43da86 | 1396 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1397 | } |
1398 | ||
1399 | bdp = fep->tx_bd_base; | |
1400 | for (i = 0; i < TX_RING_SIZE; i++) | |
1401 | kfree(fep->tx_bounce[i]); | |
1402 | } | |
1403 | ||
c556167f | 1404 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1405 | { |
c556167f | 1406 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1407 | unsigned int i; |
f0b3fbea SH |
1408 | struct sk_buff *skb; |
1409 | struct bufdesc *bdp; | |
1410 | ||
1411 | bdp = fep->rx_bd_base; | |
1412 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1413 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1414 | if (!skb) { |
c556167f | 1415 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1416 | return -ENOMEM; |
1417 | } | |
1418 | fep->rx_skbuff[i] = skb; | |
1419 | ||
d1ab1f54 | 1420 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1421 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1422 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
ff43da86 FL |
1423 | |
1424 | if (fep->bufdesc_ex) { | |
1425 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1426 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1427 | } | |
1428 | ||
1429 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1430 | } |
1431 | ||
1432 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1433 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1434 | bdp->cbd_sc |= BD_SC_WRAP; |
1435 | ||
1436 | bdp = fep->tx_bd_base; | |
1437 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1438 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1439 | ||
1440 | bdp->cbd_sc = 0; | |
1441 | bdp->cbd_bufaddr = 0; | |
6605b730 | 1442 | |
ff43da86 FL |
1443 | if (fep->bufdesc_ex) { |
1444 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1445 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1446 | } | |
1447 | ||
1448 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1449 | } |
1450 | ||
1451 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1452 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1453 | bdp->cbd_sc |= BD_SC_WRAP; |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
1da177e4 | 1458 | static int |
c556167f | 1459 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1460 | { |
c556167f | 1461 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1462 | int ret; |
1da177e4 | 1463 | |
dc975382 FL |
1464 | napi_enable(&fep->napi); |
1465 | ||
1da177e4 LT |
1466 | /* I should reset the ring buffers here, but I don't yet know |
1467 | * a simple way to do that. | |
1468 | */ | |
1da177e4 | 1469 | |
c556167f | 1470 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1471 | if (ret) |
1472 | return ret; | |
1473 | ||
418bd0d4 | 1474 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1475 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1476 | if (ret) { |
c556167f | 1477 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1478 | return ret; |
1479 | } | |
e6b043d5 | 1480 | phy_start(fep->phy_dev); |
c556167f | 1481 | netif_start_queue(ndev); |
1da177e4 | 1482 | fep->opened = 1; |
22f6b860 | 1483 | return 0; |
1da177e4 LT |
1484 | } |
1485 | ||
1486 | static int | |
c556167f | 1487 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1488 | { |
c556167f | 1489 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1490 | |
22f6b860 | 1491 | /* Don't know what to do yet. */ |
3f104c38 | 1492 | napi_disable(&fep->napi); |
1da177e4 | 1493 | fep->opened = 0; |
c556167f UKK |
1494 | netif_stop_queue(ndev); |
1495 | fec_stop(ndev); | |
1da177e4 | 1496 | |
e497ba82 UKK |
1497 | if (fep->phy_dev) { |
1498 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1499 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1500 | } |
418bd0d4 | 1501 | |
db8880bc | 1502 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1503 | |
1da177e4 LT |
1504 | return 0; |
1505 | } | |
1506 | ||
1da177e4 LT |
1507 | /* Set or clear the multicast filter for this adaptor. |
1508 | * Skeleton taken from sunlance driver. | |
1509 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1510 | * MAC address filtering. Some of the drivers check to make sure it is | |
1511 | * a group multicast address, and discard those that are not. I guess I | |
1512 | * will do the same for now, but just remove the test if you want | |
1513 | * individual filtering as well (do the upper net layers want or support | |
1514 | * this kind of feature?). | |
1515 | */ | |
1516 | ||
1517 | #define HASH_BITS 6 /* #bits in hash */ | |
1518 | #define CRC32_POLY 0xEDB88320 | |
1519 | ||
c556167f | 1520 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1521 | { |
c556167f | 1522 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1523 | struct netdev_hw_addr *ha; |
48e2f183 | 1524 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1525 | unsigned char hash; |
1526 | ||
c556167f | 1527 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1528 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1529 | tmp |= 0x8; | |
1530 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1531 | return; |
1532 | } | |
1da177e4 | 1533 | |
4e831836 SH |
1534 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1535 | tmp &= ~0x8; | |
1536 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1537 | ||
c556167f | 1538 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1539 | /* Catch all multicast addresses, so set the |
1540 | * filter to all 1's | |
1541 | */ | |
1542 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1543 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1544 | ||
1545 | return; | |
1546 | } | |
1547 | ||
1548 | /* Clear filter and add the addresses in hash register | |
1549 | */ | |
1550 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1551 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1552 | ||
c556167f | 1553 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1554 | /* calculate crc32 value of mac address */ |
1555 | crc = 0xffffffff; | |
1556 | ||
c556167f | 1557 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1558 | data = ha->addr[i]; |
4e831836 SH |
1559 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1560 | crc = (crc >> 1) ^ | |
1561 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1562 | } |
1563 | } | |
4e831836 SH |
1564 | |
1565 | /* only upper 6 bits (HASH_BITS) are used | |
1566 | * which point to specific bit in he hash registers | |
1567 | */ | |
1568 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1569 | ||
1570 | if (hash > 31) { | |
1571 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1572 | tmp |= 1 << (hash - 32); | |
1573 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1574 | } else { | |
1575 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1576 | tmp |= 1 << hash; | |
1577 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1578 | } | |
1da177e4 LT |
1579 | } |
1580 | } | |
1581 | ||
22f6b860 | 1582 | /* Set a MAC change in hardware. */ |
009fda83 | 1583 | static int |
c556167f | 1584 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1585 | { |
c556167f | 1586 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1587 | struct sockaddr *addr = p; |
1588 | ||
1589 | if (!is_valid_ether_addr(addr->sa_data)) | |
1590 | return -EADDRNOTAVAIL; | |
1591 | ||
c556167f | 1592 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1593 | |
c556167f UKK |
1594 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1595 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1596 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1597 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1598 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1599 | return 0; |
1da177e4 LT |
1600 | } |
1601 | ||
7f5c6add | 1602 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1603 | /** |
1604 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1605 | * @dev: The FEC network adapter |
1606 | * | |
1607 | * Polled functionality used by netconsole and others in non interrupt mode | |
1608 | * | |
1609 | */ | |
1610 | void fec_poll_controller(struct net_device *dev) | |
1611 | { | |
1612 | int i; | |
1613 | struct fec_enet_private *fep = netdev_priv(dev); | |
1614 | ||
1615 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1616 | if (fep->irq[i] > 0) { | |
1617 | disable_irq(fep->irq[i]); | |
1618 | fec_enet_interrupt(fep->irq[i], dev); | |
1619 | enable_irq(fep->irq[i]); | |
1620 | } | |
1621 | } | |
1622 | } | |
1623 | #endif | |
1624 | ||
009fda83 SH |
1625 | static const struct net_device_ops fec_netdev_ops = { |
1626 | .ndo_open = fec_enet_open, | |
1627 | .ndo_stop = fec_enet_close, | |
1628 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1629 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1630 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1631 | .ndo_validate_addr = eth_validate_addr, |
1632 | .ndo_tx_timeout = fec_timeout, | |
1633 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1634 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1635 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1636 | .ndo_poll_controller = fec_poll_controller, | |
1637 | #endif | |
009fda83 SH |
1638 | }; |
1639 | ||
1da177e4 LT |
1640 | /* |
1641 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1642 | * |
1da177e4 | 1643 | */ |
c556167f | 1644 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1645 | { |
c556167f | 1646 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1647 | struct bufdesc *cbd_base; |
1da177e4 | 1648 | |
8d4dd5cf SH |
1649 | /* Allocate memory for buffer descriptors. */ |
1650 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1651 | GFP_KERNEL); | |
1652 | if (!cbd_base) { | |
562d2f8c GU |
1653 | printk("FEC: allocate descriptor memory failed?\n"); |
1654 | return -ENOMEM; | |
1655 | } | |
1656 | ||
14109a59 | 1657 | memset(cbd_base, 0, PAGE_SIZE); |
3b2b74ca | 1658 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1659 | |
c556167f | 1660 | fep->netdev = ndev; |
1da177e4 | 1661 | |
49da97dc | 1662 | /* Get the Ethernet address */ |
c556167f | 1663 | fec_get_mac(ndev); |
1da177e4 | 1664 | |
8d4dd5cf | 1665 | /* Set receive and transmit descriptor base. */ |
1da177e4 | 1666 | fep->rx_bd_base = cbd_base; |
ff43da86 FL |
1667 | if (fep->bufdesc_ex) |
1668 | fep->tx_bd_base = (struct bufdesc *) | |
1669 | (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); | |
1670 | else | |
1671 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1da177e4 | 1672 | |
22f6b860 | 1673 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1674 | ndev->watchdog_timeo = TX_TIMEOUT; |
1675 | ndev->netdev_ops = &fec_netdev_ops; | |
1676 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 1677 | |
dc975382 FL |
1678 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
1679 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); | |
1680 | ||
c556167f | 1681 | fec_restart(ndev, 0); |
1da177e4 | 1682 | |
1da177e4 LT |
1683 | return 0; |
1684 | } | |
1685 | ||
ca2cc333 | 1686 | #ifdef CONFIG_OF |
33897cc8 | 1687 | static int fec_get_phy_mode_dt(struct platform_device *pdev) |
ca2cc333 SG |
1688 | { |
1689 | struct device_node *np = pdev->dev.of_node; | |
1690 | ||
1691 | if (np) | |
1692 | return of_get_phy_mode(np); | |
1693 | ||
1694 | return -ENODEV; | |
1695 | } | |
1696 | ||
33897cc8 | 1697 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1698 | { |
1699 | int err, phy_reset; | |
a3caad0a | 1700 | int msec = 1; |
ca2cc333 SG |
1701 | struct device_node *np = pdev->dev.of_node; |
1702 | ||
1703 | if (!np) | |
a9b2c8ef | 1704 | return; |
ca2cc333 | 1705 | |
a3caad0a SG |
1706 | of_property_read_u32(np, "phy-reset-duration", &msec); |
1707 | /* A sane reset duration should not be longer than 1s */ | |
1708 | if (msec > 1000) | |
1709 | msec = 1; | |
1710 | ||
ca2cc333 | 1711 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
1712 | if (!gpio_is_valid(phy_reset)) |
1713 | return; | |
1714 | ||
119fc007 SG |
1715 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
1716 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 1717 | if (err) { |
07dcf8e9 | 1718 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 1719 | return; |
ca2cc333 | 1720 | } |
a3caad0a | 1721 | msleep(msec); |
ca2cc333 | 1722 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
1723 | } |
1724 | #else /* CONFIG_OF */ | |
0c7768a0 | 1725 | static int fec_get_phy_mode_dt(struct platform_device *pdev) |
ca2cc333 SG |
1726 | { |
1727 | return -ENODEV; | |
1728 | } | |
1729 | ||
0c7768a0 | 1730 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1731 | { |
1732 | /* | |
1733 | * In case of platform probe, the reset has been done | |
1734 | * by machine code. | |
1735 | */ | |
ca2cc333 SG |
1736 | } |
1737 | #endif /* CONFIG_OF */ | |
1738 | ||
33897cc8 | 1739 | static int |
ead73183 SH |
1740 | fec_probe(struct platform_device *pdev) |
1741 | { | |
1742 | struct fec_enet_private *fep; | |
5eb32bd0 | 1743 | struct fec_platform_data *pdata; |
ead73183 SH |
1744 | struct net_device *ndev; |
1745 | int i, irq, ret = 0; | |
1746 | struct resource *r; | |
ca2cc333 | 1747 | const struct of_device_id *of_id; |
43af940c | 1748 | static int dev_id; |
b2bccee1 | 1749 | struct pinctrl *pinctrl; |
5fa9c0fe | 1750 | struct regulator *reg_phy; |
ca2cc333 SG |
1751 | |
1752 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
1753 | if (of_id) | |
1754 | pdev->id_entry = of_id->data; | |
ead73183 SH |
1755 | |
1756 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1757 | if (!r) | |
1758 | return -ENXIO; | |
1759 | ||
1760 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1761 | if (!r) | |
1762 | return -EBUSY; | |
1763 | ||
1764 | /* Init network device */ | |
1765 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
28e2188e UKK |
1766 | if (!ndev) { |
1767 | ret = -ENOMEM; | |
1768 | goto failed_alloc_etherdev; | |
1769 | } | |
ead73183 SH |
1770 | |
1771 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1772 | ||
1773 | /* setup board info structure */ | |
1774 | fep = netdev_priv(ndev); | |
ead73183 | 1775 | |
baa70a5c FL |
1776 | /* default enable pause frame auto negotiation */ |
1777 | if (pdev->id_entry && | |
1778 | (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) | |
1779 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; | |
1780 | ||
24e531b4 | 1781 | fep->hwp = ioremap(r->start, resource_size(r)); |
e6b043d5 | 1782 | fep->pdev = pdev; |
43af940c | 1783 | fep->dev_id = dev_id++; |
ead73183 | 1784 | |
ff43da86 FL |
1785 | fep->bufdesc_ex = 0; |
1786 | ||
24e531b4 | 1787 | if (!fep->hwp) { |
ead73183 SH |
1788 | ret = -ENOMEM; |
1789 | goto failed_ioremap; | |
1790 | } | |
1791 | ||
1792 | platform_set_drvdata(pdev, ndev); | |
1793 | ||
ca2cc333 SG |
1794 | ret = fec_get_phy_mode_dt(pdev); |
1795 | if (ret < 0) { | |
1796 | pdata = pdev->dev.platform_data; | |
1797 | if (pdata) | |
1798 | fep->phy_interface = pdata->phy; | |
1799 | else | |
1800 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
1801 | } else { | |
1802 | fep->phy_interface = ret; | |
1803 | } | |
1804 | ||
b2bccee1 SG |
1805 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1806 | if (IS_ERR(pinctrl)) { | |
1807 | ret = PTR_ERR(pinctrl); | |
1808 | goto failed_pin; | |
1809 | } | |
1810 | ||
f4d40de3 SH |
1811 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1812 | if (IS_ERR(fep->clk_ipg)) { | |
1813 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
1814 | goto failed_clk; |
1815 | } | |
f4d40de3 SH |
1816 | |
1817 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1818 | if (IS_ERR(fep->clk_ahb)) { | |
1819 | ret = PTR_ERR(fep->clk_ahb); | |
1820 | goto failed_clk; | |
1821 | } | |
1822 | ||
6605b730 | 1823 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
e2f8d555 FE |
1824 | fep->bufdesc_ex = |
1825 | pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; | |
6605b730 FL |
1826 | if (IS_ERR(fep->clk_ptp)) { |
1827 | ret = PTR_ERR(fep->clk_ptp); | |
ff43da86 | 1828 | fep->bufdesc_ex = 0; |
6605b730 | 1829 | } |
6605b730 | 1830 | |
f4d40de3 SH |
1831 | clk_prepare_enable(fep->clk_ahb); |
1832 | clk_prepare_enable(fep->clk_ipg); | |
ff43da86 FL |
1833 | if (!IS_ERR(fep->clk_ptp)) |
1834 | clk_prepare_enable(fep->clk_ptp); | |
1835 | ||
5fa9c0fe SG |
1836 | reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
1837 | if (!IS_ERR(reg_phy)) { | |
1838 | ret = regulator_enable(reg_phy); | |
1839 | if (ret) { | |
1840 | dev_err(&pdev->dev, | |
1841 | "Failed to enable phy regulator: %d\n", ret); | |
1842 | goto failed_regulator; | |
1843 | } | |
1844 | } | |
1845 | ||
2ca9b2aa SG |
1846 | fec_reset_phy(pdev); |
1847 | ||
e2f8d555 FE |
1848 | if (fep->bufdesc_ex) |
1849 | fec_ptp_init(ndev, pdev); | |
1850 | ||
1851 | ret = fec_enet_init(ndev); | |
1852 | if (ret) | |
1853 | goto failed_init; | |
1854 | ||
1855 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1856 | irq = platform_get_irq(pdev, i); | |
1857 | if (irq < 0) { | |
1858 | if (i) | |
1859 | break; | |
1860 | ret = irq; | |
1861 | goto failed_irq; | |
1862 | } | |
1863 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1864 | if (ret) { | |
1865 | while (--i >= 0) { | |
1866 | irq = platform_get_irq(pdev, i); | |
1867 | free_irq(irq, ndev); | |
1868 | } | |
1869 | goto failed_irq; | |
1870 | } | |
1871 | } | |
1872 | ||
e6b043d5 BW |
1873 | ret = fec_enet_mii_init(pdev); |
1874 | if (ret) | |
1875 | goto failed_mii_init; | |
1876 | ||
03c698c9 OS |
1877 | /* Carrier starts down, phylib will bring it up */ |
1878 | netif_carrier_off(ndev); | |
1879 | ||
ead73183 SH |
1880 | ret = register_netdev(ndev); |
1881 | if (ret) | |
1882 | goto failed_register; | |
1883 | ||
1884 | return 0; | |
1885 | ||
1886 | failed_register: | |
e6b043d5 BW |
1887 | fec_enet_mii_remove(fep); |
1888 | failed_mii_init: | |
e2f8d555 FE |
1889 | failed_init: |
1890 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1891 | irq = platform_get_irq(pdev, i); | |
1892 | if (irq > 0) | |
1893 | free_irq(irq, ndev); | |
1894 | } | |
1895 | failed_irq: | |
5fa9c0fe | 1896 | failed_regulator: |
f4d40de3 SH |
1897 | clk_disable_unprepare(fep->clk_ahb); |
1898 | clk_disable_unprepare(fep->clk_ipg); | |
ff43da86 FL |
1899 | if (!IS_ERR(fep->clk_ptp)) |
1900 | clk_disable_unprepare(fep->clk_ptp); | |
b2bccee1 | 1901 | failed_pin: |
ead73183 | 1902 | failed_clk: |
24e531b4 | 1903 | iounmap(fep->hwp); |
ead73183 SH |
1904 | failed_ioremap: |
1905 | free_netdev(ndev); | |
28e2188e UKK |
1906 | failed_alloc_etherdev: |
1907 | release_mem_region(r->start, resource_size(r)); | |
ead73183 SH |
1908 | |
1909 | return ret; | |
1910 | } | |
1911 | ||
33897cc8 | 1912 | static int |
ead73183 SH |
1913 | fec_drv_remove(struct platform_device *pdev) |
1914 | { | |
1915 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1916 | struct fec_enet_private *fep = netdev_priv(ndev); | |
28e2188e | 1917 | struct resource *r; |
e163cc97 | 1918 | int i; |
ead73183 | 1919 | |
e163cc97 | 1920 | unregister_netdev(ndev); |
e6b043d5 | 1921 | fec_enet_mii_remove(fep); |
6605b730 FL |
1922 | del_timer_sync(&fep->time_keep); |
1923 | clk_disable_unprepare(fep->clk_ptp); | |
1924 | if (fep->ptp_clock) | |
1925 | ptp_clock_unregister(fep->ptp_clock); | |
f4d40de3 SH |
1926 | clk_disable_unprepare(fep->clk_ahb); |
1927 | clk_disable_unprepare(fep->clk_ipg); | |
7f7d6c28 FE |
1928 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
1929 | int irq = platform_get_irq(pdev, i); | |
1930 | if (irq > 0) | |
1931 | free_irq(irq, ndev); | |
1932 | } | |
24e531b4 | 1933 | iounmap(fep->hwp); |
ead73183 | 1934 | free_netdev(ndev); |
28e2188e UKK |
1935 | |
1936 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1937 | BUG_ON(!r); | |
1938 | release_mem_region(r->start, resource_size(r)); | |
1939 | ||
b3cde36c UKK |
1940 | platform_set_drvdata(pdev, NULL); |
1941 | ||
ead73183 SH |
1942 | return 0; |
1943 | } | |
1944 | ||
59d4289b | 1945 | #ifdef CONFIG_PM |
ead73183 | 1946 | static int |
87cad5c3 | 1947 | fec_suspend(struct device *dev) |
ead73183 | 1948 | { |
87cad5c3 | 1949 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1950 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1951 | |
04e5216d UKK |
1952 | if (netif_running(ndev)) { |
1953 | fec_stop(ndev); | |
1954 | netif_device_detach(ndev); | |
ead73183 | 1955 | } |
f4d40de3 SH |
1956 | clk_disable_unprepare(fep->clk_ahb); |
1957 | clk_disable_unprepare(fep->clk_ipg); | |
04e5216d | 1958 | |
ead73183 SH |
1959 | return 0; |
1960 | } | |
1961 | ||
1962 | static int | |
87cad5c3 | 1963 | fec_resume(struct device *dev) |
ead73183 | 1964 | { |
87cad5c3 | 1965 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1966 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1967 | |
f4d40de3 SH |
1968 | clk_prepare_enable(fep->clk_ahb); |
1969 | clk_prepare_enable(fep->clk_ipg); | |
04e5216d UKK |
1970 | if (netif_running(ndev)) { |
1971 | fec_restart(ndev, fep->full_duplex); | |
1972 | netif_device_attach(ndev); | |
ead73183 | 1973 | } |
04e5216d | 1974 | |
ead73183 SH |
1975 | return 0; |
1976 | } | |
1977 | ||
59d4289b DK |
1978 | static const struct dev_pm_ops fec_pm_ops = { |
1979 | .suspend = fec_suspend, | |
1980 | .resume = fec_resume, | |
1981 | .freeze = fec_suspend, | |
1982 | .thaw = fec_resume, | |
1983 | .poweroff = fec_suspend, | |
1984 | .restore = fec_resume, | |
1985 | }; | |
87cad5c3 | 1986 | #endif |
59d4289b | 1987 | |
ead73183 SH |
1988 | static struct platform_driver fec_driver = { |
1989 | .driver = { | |
b5680e0b | 1990 | .name = DRIVER_NAME, |
87cad5c3 EB |
1991 | .owner = THIS_MODULE, |
1992 | #ifdef CONFIG_PM | |
1993 | .pm = &fec_pm_ops, | |
1994 | #endif | |
ca2cc333 | 1995 | .of_match_table = fec_dt_ids, |
ead73183 | 1996 | }, |
b5680e0b | 1997 | .id_table = fec_devtype, |
87cad5c3 | 1998 | .probe = fec_probe, |
33897cc8 | 1999 | .remove = fec_drv_remove, |
ead73183 SH |
2000 | }; |
2001 | ||
aaca2377 | 2002 | module_platform_driver(fec_driver); |
1da177e4 LT |
2003 | |
2004 | MODULE_LICENSE("GPL"); |