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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/bitops.h> | |
6f501b17 SH |
41 | #include <linux/io.h> |
42 | #include <linux/irq.h> | |
196719ec | 43 | #include <linux/clk.h> |
ead73183 | 44 | #include <linux/platform_device.h> |
e6b043d5 | 45 | #include <linux/phy.h> |
5eb32bd0 | 46 | #include <linux/fec.h> |
ca2cc333 SG |
47 | #include <linux/of.h> |
48 | #include <linux/of_device.h> | |
49 | #include <linux/of_gpio.h> | |
50 | #include <linux/of_net.h> | |
b2bccee1 | 51 | #include <linux/pinctrl/consumer.h> |
5fa9c0fe | 52 | #include <linux/regulator/consumer.h> |
1da177e4 | 53 | |
080853af | 54 | #include <asm/cacheflush.h> |
196719ec | 55 | |
b5680e0b | 56 | #ifndef CONFIG_ARM |
1da177e4 LT |
57 | #include <asm/coldfire.h> |
58 | #include <asm/mcfsim.h> | |
196719ec | 59 | #endif |
6f501b17 | 60 | |
1da177e4 | 61 | #include "fec.h" |
1da177e4 | 62 | |
085e79ed | 63 | #if defined(CONFIG_ARM) |
196719ec SH |
64 | #define FEC_ALIGNMENT 0xf |
65 | #else | |
66 | #define FEC_ALIGNMENT 0x3 | |
67 | #endif | |
68 | ||
b5680e0b SG |
69 | #define DRIVER_NAME "fec" |
70 | ||
71 | /* Controller is ENET-MAC */ | |
72 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
73 | /* Controller needs driver to swap frame */ | |
74 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
75 | /* Controller uses gasket */ |
76 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
77 | /* Controller has GBIT support */ |
78 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
b5680e0b SG |
79 | |
80 | static struct platform_device_id fec_devtype[] = { | |
81 | { | |
0ca1e290 | 82 | /* keep it for coldfire */ |
b5680e0b SG |
83 | .name = DRIVER_NAME, |
84 | .driver_data = 0, | |
0ca1e290 SG |
85 | }, { |
86 | .name = "imx25-fec", | |
87 | .driver_data = FEC_QUIRK_USE_GASKET, | |
88 | }, { | |
89 | .name = "imx27-fec", | |
90 | .driver_data = 0, | |
b5680e0b SG |
91 | }, { |
92 | .name = "imx28-fec", | |
93 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
94 | }, { |
95 | .name = "imx6q-fec", | |
96 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT, | |
0ca1e290 SG |
97 | }, { |
98 | /* sentinel */ | |
99 | } | |
b5680e0b | 100 | }; |
0ca1e290 | 101 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 102 | |
ca2cc333 | 103 | enum imx_fec_type { |
a7dd3219 | 104 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
105 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
106 | IMX28_FEC, | |
230dec61 | 107 | IMX6Q_FEC, |
ca2cc333 SG |
108 | }; |
109 | ||
110 | static const struct of_device_id fec_dt_ids[] = { | |
111 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
112 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
113 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 114 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
ca2cc333 SG |
115 | { /* sentinel */ } |
116 | }; | |
117 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
118 | ||
49da97dc SG |
119 | static unsigned char macaddr[ETH_ALEN]; |
120 | module_param_array(macaddr, byte, NULL, 0); | |
121 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 122 | |
49da97dc | 123 | #if defined(CONFIG_M5272) |
1da177e4 LT |
124 | /* |
125 | * Some hardware gets it MAC address out of local flash memory. | |
126 | * if this is non-zero then assume it is the address to get MAC from. | |
127 | */ | |
128 | #if defined(CONFIG_NETtel) | |
129 | #define FEC_FLASHMAC 0xf0006006 | |
130 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
131 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
132 | #elif defined(CONFIG_CANCam) |
133 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
134 | #elif defined (CONFIG_M5272C3) |
135 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
136 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 137 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
138 | #else |
139 | #define FEC_FLASHMAC 0 | |
140 | #endif | |
43be6366 | 141 | #endif /* CONFIG_M5272 */ |
ead73183 | 142 | |
562d2f8c | 143 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 144 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
145 | #endif |
146 | ||
22f6b860 | 147 | /* Interrupt events/masks. */ |
1da177e4 LT |
148 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
149 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
150 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
151 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
152 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
153 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
154 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
155 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
156 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
157 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
158 | ||
4bee1f9a WS |
159 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
160 | ||
1da177e4 LT |
161 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
162 | */ | |
163 | #define PKT_MAXBUF_SIZE 1518 | |
164 | #define PKT_MINBUF_SIZE 64 | |
165 | #define PKT_MAXBLR_SIZE 1520 | |
166 | ||
1da177e4 | 167 | /* |
6b265293 | 168 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
169 | * size bits. Other FEC hardware does not, so we need to take that into |
170 | * account when setting it. | |
171 | */ | |
562d2f8c | 172 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 173 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
174 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
175 | #else | |
176 | #define OPT_FRAME_SIZE 0 | |
177 | #endif | |
178 | ||
e6b043d5 BW |
179 | /* FEC MII MMFR bits definition */ |
180 | #define FEC_MMFR_ST (1 << 30) | |
181 | #define FEC_MMFR_OP_READ (2 << 28) | |
182 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
183 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
184 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
185 | #define FEC_MMFR_TA (2 << 16) | |
186 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 187 | |
c3b084c2 | 188 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 189 | |
22f6b860 SH |
190 | /* Transmitter timeout */ |
191 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 192 | |
e163cc97 LW |
193 | static int mii_cnt; |
194 | ||
b5680e0b SG |
195 | static void *swap_buffer(void *bufaddr, int len) |
196 | { | |
197 | int i; | |
198 | unsigned int *buf = bufaddr; | |
199 | ||
200 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
201 | *buf = cpu_to_be32(*buf); | |
202 | ||
203 | return bufaddr; | |
204 | } | |
205 | ||
c7621cb3 | 206 | static netdev_tx_t |
c556167f | 207 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 208 | { |
c556167f | 209 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
210 | const struct platform_device_id *id_entry = |
211 | platform_get_device_id(fep->pdev); | |
2e28532f | 212 | struct bufdesc *bdp; |
9555b31e | 213 | void *bufaddr; |
0e702ab3 | 214 | unsigned short status; |
3b2b74ca | 215 | unsigned long flags; |
1da177e4 | 216 | |
1da177e4 LT |
217 | if (!fep->link) { |
218 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 219 | return NETDEV_TX_BUSY; |
1da177e4 LT |
220 | } |
221 | ||
3b2b74ca | 222 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
223 | /* Fill in a Tx ring entry */ |
224 | bdp = fep->cur_tx; | |
225 | ||
0e702ab3 | 226 | status = bdp->cbd_sc; |
22f6b860 | 227 | |
0e702ab3 | 228 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 229 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 230 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 231 | */ |
c556167f | 232 | printk("%s: tx queue full!.\n", ndev->name); |
3b2b74ca | 233 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
5b548140 | 234 | return NETDEV_TX_BUSY; |
1da177e4 | 235 | } |
1da177e4 | 236 | |
22f6b860 | 237 | /* Clear all of the status flags */ |
0e702ab3 | 238 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 239 | |
22f6b860 | 240 | /* Set buffer length and buffer pointer */ |
9555b31e | 241 | bufaddr = skb->data; |
1da177e4 LT |
242 | bdp->cbd_datlen = skb->len; |
243 | ||
244 | /* | |
22f6b860 SH |
245 | * On some FEC implementations data must be aligned on |
246 | * 4-byte boundaries. Use bounce buffers to copy data | |
247 | * and get it aligned. Ugh. | |
1da177e4 | 248 | */ |
9555b31e | 249 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
1da177e4 LT |
250 | unsigned int index; |
251 | index = bdp - fep->tx_bd_base; | |
8a73b0bc | 252 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 253 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
254 | } |
255 | ||
b5680e0b SG |
256 | /* |
257 | * Some design made an incorrect assumption on endian mode of | |
258 | * the system that it's running on. As the result, driver has to | |
259 | * swap every frame going to and coming from the controller. | |
260 | */ | |
261 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
262 | swap_buffer(bufaddr, skb->len); | |
263 | ||
22f6b860 | 264 | /* Save skb pointer */ |
1da177e4 LT |
265 | fep->tx_skbuff[fep->skb_cur] = skb; |
266 | ||
c556167f | 267 | ndev->stats.tx_bytes += skb->len; |
1da177e4 | 268 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 269 | |
1da177e4 LT |
270 | /* Push the data cache so the CPM does not get stale memory |
271 | * data. | |
272 | */ | |
d1ab1f54 | 273 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 274 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 275 | |
0e702ab3 GU |
276 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
277 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 278 | */ |
0e702ab3 | 279 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 280 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 281 | bdp->cbd_sc = status; |
1da177e4 | 282 | |
6605b730 FL |
283 | #ifdef CONFIG_FEC_PTP |
284 | bdp->cbd_bdu = 0; | |
285 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
286 | fep->hwts_tx_en)) { | |
287 | bdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); | |
288 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
289 | } else { | |
290 | ||
291 | bdp->cbd_esc = BD_ENET_TX_INT; | |
292 | } | |
293 | #endif | |
1da177e4 | 294 | /* Trigger transmission start */ |
f44d6305 | 295 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 296 | |
22f6b860 SH |
297 | /* If this was the last BD in the ring, start at the beginning again. */ |
298 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 299 | bdp = fep->tx_bd_base; |
22f6b860 | 300 | else |
1da177e4 | 301 | bdp++; |
1da177e4 LT |
302 | |
303 | if (bdp == fep->dirty_tx) { | |
304 | fep->tx_full = 1; | |
c556167f | 305 | netif_stop_queue(ndev); |
1da177e4 LT |
306 | } |
307 | ||
2e28532f | 308 | fep->cur_tx = bdp; |
1da177e4 | 309 | |
18a03b97 RC |
310 | skb_tx_timestamp(skb); |
311 | ||
a0087a36 RC |
312 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
313 | ||
6ed10654 | 314 | return NETDEV_TX_OK; |
1da177e4 LT |
315 | } |
316 | ||
45993653 UKK |
317 | /* This function is called to start or restart the FEC during a link |
318 | * change. This only happens when switching between half and full | |
319 | * duplex. | |
320 | */ | |
1da177e4 | 321 | static void |
45993653 | 322 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 323 | { |
c556167f | 324 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
325 | const struct platform_device_id *id_entry = |
326 | platform_get_device_id(fep->pdev); | |
327 | int i; | |
cd1f402c UKK |
328 | u32 temp_mac[2]; |
329 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 330 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 331 | |
45993653 UKK |
332 | /* Whack a reset. We should wait for this. */ |
333 | writel(1, fep->hwp + FEC_ECNTRL); | |
334 | udelay(10); | |
1da177e4 | 335 | |
45993653 UKK |
336 | /* |
337 | * enet-mac reset will reset mac address registers too, | |
338 | * so need to reconfigure it. | |
339 | */ | |
340 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
341 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
342 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
343 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
344 | } | |
1da177e4 | 345 | |
45993653 UKK |
346 | /* Clear any outstanding interrupt. */ |
347 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 348 | |
45993653 UKK |
349 | /* Reset all multicast. */ |
350 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
351 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
352 | #ifndef CONFIG_M5272 | |
353 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
354 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
355 | #endif | |
1da177e4 | 356 | |
45993653 UKK |
357 | /* Set maximum receive buffer size. */ |
358 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 359 | |
45993653 UKK |
360 | /* Set receive and transmit descriptor base. */ |
361 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
362 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, | |
363 | fep->hwp + FEC_X_DES_START); | |
364 | ||
365 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
366 | fep->cur_rx = fep->rx_bd_base; | |
367 | ||
368 | /* Reset SKB transmit buffers. */ | |
369 | fep->skb_cur = fep->skb_dirty = 0; | |
370 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { | |
371 | if (fep->tx_skbuff[i]) { | |
372 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
373 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 374 | } |
45993653 | 375 | } |
97b72e43 | 376 | |
45993653 UKK |
377 | /* Enable MII mode */ |
378 | if (duplex) { | |
cd1f402c | 379 | /* FD enable */ |
45993653 UKK |
380 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
381 | } else { | |
cd1f402c UKK |
382 | /* No Rcv on Xmit */ |
383 | rcntl |= 0x02; | |
45993653 UKK |
384 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
385 | } | |
cd1f402c | 386 | |
45993653 UKK |
387 | fep->full_duplex = duplex; |
388 | ||
389 | /* Set MII speed */ | |
390 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
391 | ||
392 | /* | |
393 | * The phy interface and speed need to get configured | |
394 | * differently on enet-mac. | |
395 | */ | |
396 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
397 | /* Enable flow control and length check */ |
398 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 399 | |
230dec61 SG |
400 | /* RGMII, RMII or MII */ |
401 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
402 | rcntl |= (1 << 6); | |
403 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 404 | rcntl |= (1 << 8); |
45993653 | 405 | else |
cd1f402c | 406 | rcntl &= ~(1 << 8); |
45993653 | 407 | |
230dec61 SG |
408 | /* 1G, 100M or 10M */ |
409 | if (fep->phy_dev) { | |
410 | if (fep->phy_dev->speed == SPEED_1000) | |
411 | ecntl |= (1 << 5); | |
412 | else if (fep->phy_dev->speed == SPEED_100) | |
413 | rcntl &= ~(1 << 9); | |
414 | else | |
415 | rcntl |= (1 << 9); | |
416 | } | |
45993653 UKK |
417 | } else { |
418 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 419 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 420 | u32 cfgr; |
45993653 UKK |
421 | /* disable the gasket and wait */ |
422 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
423 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
424 | udelay(1); | |
425 | ||
426 | /* | |
427 | * configure the gasket: | |
428 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 429 | * MII, 25 MHz, no loopback, no echo |
45993653 | 430 | */ |
8d82f219 EB |
431 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
432 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
433 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
434 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
435 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
436 | |
437 | /* re-enable the gasket */ | |
438 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 439 | } |
45993653 UKK |
440 | #endif |
441 | } | |
cd1f402c | 442 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 443 | |
230dec61 SG |
444 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
445 | /* enable ENET endian swap */ | |
446 | ecntl |= (1 << 8); | |
447 | /* enable ENET store and forward mode */ | |
448 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
449 | } | |
450 | ||
6605b730 FL |
451 | #ifdef CONFIG_FEC_PTP |
452 | ecntl |= (1 << 4); | |
453 | #endif | |
454 | ||
45993653 | 455 | /* And last, enable the transmit and receive processing */ |
230dec61 | 456 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
457 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
458 | ||
6605b730 FL |
459 | #ifdef CONFIG_FEC_PTP |
460 | fec_ptp_start_cyclecounter(ndev); | |
461 | #endif | |
45993653 UKK |
462 | /* Enable interrupts we wish to service */ |
463 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
464 | } | |
465 | ||
466 | static void | |
467 | fec_stop(struct net_device *ndev) | |
468 | { | |
469 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
470 | const struct platform_device_id *id_entry = |
471 | platform_get_device_id(fep->pdev); | |
42431dc2 | 472 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
473 | |
474 | /* We cannot expect a graceful transmit stop without link !!! */ | |
475 | if (fep->link) { | |
476 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
477 | udelay(10); | |
478 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
479 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
480 | } | |
481 | ||
482 | /* Whack a reset. We should wait for this. */ | |
483 | writel(1, fep->hwp + FEC_ECNTRL); | |
484 | udelay(10); | |
485 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
486 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
487 | |
488 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 489 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 490 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
491 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
492 | } | |
1da177e4 LT |
493 | } |
494 | ||
495 | ||
45993653 UKK |
496 | static void |
497 | fec_timeout(struct net_device *ndev) | |
498 | { | |
499 | struct fec_enet_private *fep = netdev_priv(ndev); | |
500 | ||
501 | ndev->stats.tx_errors++; | |
502 | ||
503 | fec_restart(ndev, fep->full_duplex); | |
504 | netif_wake_queue(ndev); | |
505 | } | |
506 | ||
1da177e4 | 507 | static void |
c556167f | 508 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
509 | { |
510 | struct fec_enet_private *fep; | |
2e28532f | 511 | struct bufdesc *bdp; |
0e702ab3 | 512 | unsigned short status; |
1da177e4 LT |
513 | struct sk_buff *skb; |
514 | ||
c556167f | 515 | fep = netdev_priv(ndev); |
81538e74 | 516 | spin_lock(&fep->hw_lock); |
1da177e4 LT |
517 | bdp = fep->dirty_tx; |
518 | ||
0e702ab3 | 519 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
f0b3fbea SH |
520 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
521 | break; | |
522 | ||
d1ab1f54 UKK |
523 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
524 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 525 | bdp->cbd_bufaddr = 0; |
1da177e4 LT |
526 | |
527 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
528 | /* Check for errors. */ | |
0e702ab3 | 529 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
530 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
531 | BD_ENET_TX_CSL)) { | |
c556167f | 532 | ndev->stats.tx_errors++; |
0e702ab3 | 533 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 534 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 535 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 536 | ndev->stats.tx_window_errors++; |
0e702ab3 | 537 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 538 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 539 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 540 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 541 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 542 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 543 | } else { |
c556167f | 544 | ndev->stats.tx_packets++; |
1da177e4 LT |
545 | } |
546 | ||
6605b730 FL |
547 | #ifdef CONFIG_FEC_PTP |
548 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { | |
549 | struct skb_shared_hwtstamps shhwtstamps; | |
550 | unsigned long flags; | |
551 | ||
552 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
553 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
554 | shhwtstamps.hwtstamp = ns_to_ktime( | |
555 | timecounter_cyc2time(&fep->tc, bdp->ts)); | |
556 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); | |
557 | skb_tstamp_tx(skb, &shhwtstamps); | |
558 | } | |
559 | #endif | |
0e702ab3 | 560 | if (status & BD_ENET_TX_READY) |
1da177e4 | 561 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 562 | |
1da177e4 LT |
563 | /* Deferred means some collisions occurred during transmit, |
564 | * but we eventually sent the packet OK. | |
565 | */ | |
0e702ab3 | 566 | if (status & BD_ENET_TX_DEF) |
c556167f | 567 | ndev->stats.collisions++; |
6aa20a22 | 568 | |
22f6b860 | 569 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
570 | dev_kfree_skb_any(skb); |
571 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
572 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 573 | |
22f6b860 | 574 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 575 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
576 | bdp = fep->tx_bd_base; |
577 | else | |
578 | bdp++; | |
6aa20a22 | 579 | |
22f6b860 | 580 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
581 | */ |
582 | if (fep->tx_full) { | |
583 | fep->tx_full = 0; | |
c556167f UKK |
584 | if (netif_queue_stopped(ndev)) |
585 | netif_wake_queue(ndev); | |
1da177e4 LT |
586 | } |
587 | } | |
2e28532f | 588 | fep->dirty_tx = bdp; |
81538e74 | 589 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
590 | } |
591 | ||
592 | ||
593 | /* During a receive, the cur_rx points to the current incoming buffer. | |
594 | * When we update through the ring, if the next incoming buffer has | |
595 | * not been given to the system, we just set the empty indicator, | |
596 | * effectively tossing the packet. | |
597 | */ | |
598 | static void | |
c556167f | 599 | fec_enet_rx(struct net_device *ndev) |
1da177e4 | 600 | { |
c556167f | 601 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
602 | const struct platform_device_id *id_entry = |
603 | platform_get_device_id(fep->pdev); | |
2e28532f | 604 | struct bufdesc *bdp; |
0e702ab3 | 605 | unsigned short status; |
1da177e4 LT |
606 | struct sk_buff *skb; |
607 | ushort pkt_len; | |
608 | __u8 *data; | |
6aa20a22 | 609 | |
0e702ab3 GU |
610 | #ifdef CONFIG_M532x |
611 | flush_cache_all(); | |
6aa20a22 | 612 | #endif |
1da177e4 | 613 | |
81538e74 | 614 | spin_lock(&fep->hw_lock); |
3b2b74ca | 615 | |
1da177e4 LT |
616 | /* First, grab all of the stats for the incoming packet. |
617 | * These get messed up if we get called due to a busy condition. | |
618 | */ | |
619 | bdp = fep->cur_rx; | |
620 | ||
22f6b860 | 621 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 622 | |
22f6b860 SH |
623 | /* Since we have allocated space to hold a complete frame, |
624 | * the last indicator should be set. | |
625 | */ | |
626 | if ((status & BD_ENET_RX_LAST) == 0) | |
627 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 628 | |
22f6b860 SH |
629 | if (!fep->opened) |
630 | goto rx_processing_done; | |
1da177e4 | 631 | |
22f6b860 SH |
632 | /* Check for errors. */ |
633 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 634 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 635 | ndev->stats.rx_errors++; |
22f6b860 SH |
636 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
637 | /* Frame too long or too short. */ | |
c556167f | 638 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
639 | } |
640 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 641 | ndev->stats.rx_frame_errors++; |
22f6b860 | 642 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 643 | ndev->stats.rx_crc_errors++; |
22f6b860 | 644 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 645 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 646 | } |
1da177e4 | 647 | |
22f6b860 SH |
648 | /* Report late collisions as a frame error. |
649 | * On this error, the BD is closed, but we don't know what we | |
650 | * have in the buffer. So, just drop this frame on the floor. | |
651 | */ | |
652 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
653 | ndev->stats.rx_errors++; |
654 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
655 | goto rx_processing_done; |
656 | } | |
1da177e4 | 657 | |
22f6b860 | 658 | /* Process the incoming frame. */ |
c556167f | 659 | ndev->stats.rx_packets++; |
22f6b860 | 660 | pkt_len = bdp->cbd_datlen; |
c556167f | 661 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 662 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 663 | |
d1ab1f54 UKK |
664 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
665 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 666 | |
b5680e0b SG |
667 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
668 | swap_buffer(data, pkt_len); | |
669 | ||
22f6b860 SH |
670 | /* This does 16 byte alignment, exactly what we need. |
671 | * The packet length includes FCS, but we don't want to | |
672 | * include that when passing upstream as it messes up | |
673 | * bridging applications. | |
674 | */ | |
b72061a3 | 675 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 676 | |
8549889c | 677 | if (unlikely(!skb)) { |
22f6b860 | 678 | printk("%s: Memory squeeze, dropping packet.\n", |
c556167f UKK |
679 | ndev->name); |
680 | ndev->stats.rx_dropped++; | |
22f6b860 | 681 | } else { |
8549889c | 682 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
683 | skb_put(skb, pkt_len - 4); /* Make room */ |
684 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 685 | skb->protocol = eth_type_trans(skb, ndev); |
6605b730 FL |
686 | #ifdef CONFIG_FEC_PTP |
687 | /* Get receive timestamp from the skb */ | |
688 | if (fep->hwts_rx_en) { | |
689 | struct skb_shared_hwtstamps *shhwtstamps = | |
690 | skb_hwtstamps(skb); | |
691 | unsigned long flags; | |
692 | ||
693 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
694 | ||
695 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
696 | shhwtstamps->hwtstamp = ns_to_ktime( | |
697 | timecounter_cyc2time(&fep->tc, bdp->ts)); | |
698 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); | |
699 | } | |
700 | #endif | |
18a03b97 RC |
701 | if (!skb_defer_rx_timestamp(skb)) |
702 | netif_rx(skb); | |
22f6b860 | 703 | } |
f0b3fbea | 704 | |
d1ab1f54 UKK |
705 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
706 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
707 | rx_processing_done: |
708 | /* Clear the status flags for this buffer */ | |
709 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 710 | |
22f6b860 SH |
711 | /* Mark the buffer empty */ |
712 | status |= BD_ENET_RX_EMPTY; | |
713 | bdp->cbd_sc = status; | |
6aa20a22 | 714 | |
6605b730 FL |
715 | #ifdef CONFIG_FEC_PTP |
716 | bdp->cbd_esc = BD_ENET_RX_INT; | |
717 | bdp->cbd_prot = 0; | |
718 | bdp->cbd_bdu = 0; | |
719 | #endif | |
720 | ||
22f6b860 SH |
721 | /* Update BD pointer to next entry */ |
722 | if (status & BD_ENET_RX_WRAP) | |
723 | bdp = fep->rx_bd_base; | |
724 | else | |
725 | bdp++; | |
726 | /* Doing this here will keep the FEC running while we process | |
727 | * incoming frames. On a heavily loaded network, we should be | |
728 | * able to keep up at the expense of system resources. | |
729 | */ | |
730 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
731 | } | |
2e28532f | 732 | fep->cur_rx = bdp; |
1da177e4 | 733 | |
81538e74 | 734 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
735 | } |
736 | ||
45993653 UKK |
737 | static irqreturn_t |
738 | fec_enet_interrupt(int irq, void *dev_id) | |
739 | { | |
740 | struct net_device *ndev = dev_id; | |
741 | struct fec_enet_private *fep = netdev_priv(ndev); | |
742 | uint int_events; | |
743 | irqreturn_t ret = IRQ_NONE; | |
744 | ||
745 | do { | |
746 | int_events = readl(fep->hwp + FEC_IEVENT); | |
747 | writel(int_events, fep->hwp + FEC_IEVENT); | |
748 | ||
749 | if (int_events & FEC_ENET_RXF) { | |
750 | ret = IRQ_HANDLED; | |
751 | fec_enet_rx(ndev); | |
752 | } | |
753 | ||
754 | /* Transmit OK, or non-fatal error. Update the buffer | |
755 | * descriptors. FEC handles all errors, we just discover | |
756 | * them as part of the transmit process. | |
757 | */ | |
758 | if (int_events & FEC_ENET_TXF) { | |
759 | ret = IRQ_HANDLED; | |
760 | fec_enet_tx(ndev); | |
761 | } | |
762 | ||
763 | if (int_events & FEC_ENET_MII) { | |
764 | ret = IRQ_HANDLED; | |
765 | complete(&fep->mdio_done); | |
766 | } | |
767 | } while (int_events); | |
768 | ||
769 | return ret; | |
770 | } | |
771 | ||
772 | ||
773 | ||
e6b043d5 | 774 | /* ------------------------------------------------------------------------- */ |
c556167f | 775 | static void __inline__ fec_get_mac(struct net_device *ndev) |
1da177e4 | 776 | { |
c556167f | 777 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 778 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 779 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 780 | |
49da97dc SG |
781 | /* |
782 | * try to get mac address in following order: | |
783 | * | |
784 | * 1) module parameter via kernel command line in form | |
785 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
786 | */ | |
787 | iap = macaddr; | |
788 | ||
ca2cc333 SG |
789 | #ifdef CONFIG_OF |
790 | /* | |
791 | * 2) from device tree data | |
792 | */ | |
793 | if (!is_valid_ether_addr(iap)) { | |
794 | struct device_node *np = fep->pdev->dev.of_node; | |
795 | if (np) { | |
796 | const char *mac = of_get_mac_address(np); | |
797 | if (mac) | |
798 | iap = (unsigned char *) mac; | |
799 | } | |
800 | } | |
801 | #endif | |
802 | ||
49da97dc | 803 | /* |
ca2cc333 | 804 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
805 | */ |
806 | if (!is_valid_ether_addr(iap)) { | |
807 | #ifdef CONFIG_M5272 | |
808 | if (FEC_FLASHMAC) | |
809 | iap = (unsigned char *)FEC_FLASHMAC; | |
810 | #else | |
811 | if (pdata) | |
589efdc7 | 812 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
813 | #endif |
814 | } | |
815 | ||
816 | /* | |
ca2cc333 | 817 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
818 | */ |
819 | if (!is_valid_ether_addr(iap)) { | |
820 | *((unsigned long *) &tmpaddr[0]) = | |
821 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
822 | *((unsigned short *) &tmpaddr[4]) = | |
823 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 824 | iap = &tmpaddr[0]; |
1da177e4 LT |
825 | } |
826 | ||
c556167f | 827 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 828 | |
49da97dc SG |
829 | /* Adjust MAC if using macaddr */ |
830 | if (iap == macaddr) | |
43af940c | 831 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
832 | } |
833 | ||
e6b043d5 | 834 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 835 | |
e6b043d5 BW |
836 | /* |
837 | * Phy section | |
838 | */ | |
c556167f | 839 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 840 | { |
c556167f | 841 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 BW |
842 | struct phy_device *phy_dev = fep->phy_dev; |
843 | unsigned long flags; | |
1da177e4 | 844 | |
e6b043d5 | 845 | int status_change = 0; |
1da177e4 | 846 | |
e6b043d5 | 847 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 848 | |
e6b043d5 BW |
849 | /* Prevent a state halted on mii error */ |
850 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
851 | phy_dev->state = PHY_RESUMING; | |
852 | goto spin_unlock; | |
853 | } | |
1da177e4 | 854 | |
e6b043d5 BW |
855 | /* Duplex link change */ |
856 | if (phy_dev->link) { | |
857 | if (fep->full_duplex != phy_dev->duplex) { | |
c556167f | 858 | fec_restart(ndev, phy_dev->duplex); |
6ea0722f LW |
859 | /* prevent unnecessary second fec_restart() below */ |
860 | fep->link = phy_dev->link; | |
e6b043d5 BW |
861 | status_change = 1; |
862 | } | |
863 | } | |
1da177e4 | 864 | |
e6b043d5 BW |
865 | /* Link on or off change */ |
866 | if (phy_dev->link != fep->link) { | |
867 | fep->link = phy_dev->link; | |
868 | if (phy_dev->link) | |
c556167f | 869 | fec_restart(ndev, phy_dev->duplex); |
1da177e4 | 870 | else |
c556167f | 871 | fec_stop(ndev); |
e6b043d5 | 872 | status_change = 1; |
1da177e4 | 873 | } |
6aa20a22 | 874 | |
e6b043d5 BW |
875 | spin_unlock: |
876 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 877 | |
e6b043d5 BW |
878 | if (status_change) |
879 | phy_print_status(phy_dev); | |
880 | } | |
1da177e4 | 881 | |
e6b043d5 | 882 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 883 | { |
e6b043d5 | 884 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 885 | unsigned long time_left; |
1da177e4 | 886 | |
e6b043d5 | 887 | fep->mii_timeout = 0; |
97b72e43 | 888 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
889 | |
890 | /* start a read op */ | |
891 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
892 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
893 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
894 | ||
895 | /* wait for end of transfer */ | |
97b72e43 BS |
896 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
897 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
898 | if (time_left == 0) { | |
899 | fep->mii_timeout = 1; | |
900 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
901 | return -ETIMEDOUT; | |
1da177e4 | 902 | } |
1da177e4 | 903 | |
e6b043d5 BW |
904 | /* return value */ |
905 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 906 | } |
6aa20a22 | 907 | |
e6b043d5 BW |
908 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
909 | u16 value) | |
1da177e4 | 910 | { |
e6b043d5 | 911 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 912 | unsigned long time_left; |
1da177e4 | 913 | |
e6b043d5 | 914 | fep->mii_timeout = 0; |
97b72e43 | 915 | init_completion(&fep->mdio_done); |
1da177e4 | 916 | |
862f0982 SG |
917 | /* start a write op */ |
918 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
919 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
920 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
921 | fep->hwp + FEC_MII_DATA); | |
922 | ||
923 | /* wait for end of transfer */ | |
97b72e43 BS |
924 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
925 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
926 | if (time_left == 0) { | |
927 | fep->mii_timeout = 1; | |
928 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
929 | return -ETIMEDOUT; | |
e6b043d5 | 930 | } |
1da177e4 | 931 | |
e6b043d5 BW |
932 | return 0; |
933 | } | |
1da177e4 | 934 | |
e6b043d5 | 935 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 936 | { |
e6b043d5 | 937 | return 0; |
1da177e4 LT |
938 | } |
939 | ||
c556167f | 940 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 941 | { |
c556167f | 942 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
943 | const struct platform_device_id *id_entry = |
944 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 945 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
946 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
947 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
948 | int phy_id; | |
43af940c | 949 | int dev_id = fep->dev_id; |
562d2f8c | 950 | |
418bd0d4 BW |
951 | fep->phy_dev = NULL; |
952 | ||
6fcc040f GU |
953 | /* check for attached phy */ |
954 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
955 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
956 | continue; | |
957 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
958 | continue; | |
959 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
960 | continue; | |
b5680e0b SG |
961 | if (dev_id--) |
962 | continue; | |
6fcc040f GU |
963 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
964 | break; | |
e6b043d5 | 965 | } |
1da177e4 | 966 | |
6fcc040f | 967 | if (phy_id >= PHY_MAX_ADDR) { |
a7dd3219 LW |
968 | printk(KERN_INFO |
969 | "%s: no PHY, assuming direct connection to switch\n", | |
970 | ndev->name); | |
ea51ade9 | 971 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
972 | phy_id = 0; |
973 | } | |
974 | ||
a7ed07d5 | 975 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
c556167f | 976 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0, |
230dec61 | 977 | fep->phy_interface); |
6fcc040f | 978 | if (IS_ERR(phy_dev)) { |
c556167f | 979 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); |
6fcc040f | 980 | return PTR_ERR(phy_dev); |
e6b043d5 | 981 | } |
1da177e4 | 982 | |
e6b043d5 | 983 | /* mask with MAC supported features */ |
230dec61 SG |
984 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) |
985 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
986 | else | |
987 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
988 | ||
e6b043d5 | 989 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 990 | |
e6b043d5 BW |
991 | fep->phy_dev = phy_dev; |
992 | fep->link = 0; | |
993 | fep->full_duplex = 0; | |
1da177e4 | 994 | |
a7dd3219 LW |
995 | printk(KERN_INFO |
996 | "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
997 | ndev->name, | |
418bd0d4 BW |
998 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
999 | fep->phy_dev->irq); | |
1000 | ||
e6b043d5 | 1001 | return 0; |
1da177e4 LT |
1002 | } |
1003 | ||
e6b043d5 | 1004 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1005 | { |
b5680e0b | 1006 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1007 | struct net_device *ndev = platform_get_drvdata(pdev); |
1008 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1009 | const struct platform_device_id *id_entry = |
1010 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1011 | int err = -ENXIO, i; |
6b265293 | 1012 | |
b5680e0b SG |
1013 | /* |
1014 | * The dual fec interfaces are not equivalent with enet-mac. | |
1015 | * Here are the differences: | |
1016 | * | |
1017 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1018 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1019 | * - external phys can only be configured by fec0 | |
1020 | * | |
1021 | * That is to say fec1 can not work independently. It only works | |
1022 | * when fec0 is working. The reason behind this design is that the | |
1023 | * second interface is added primarily for Switch mode. | |
1024 | * | |
1025 | * Because of the last point above, both phys are attached on fec0 | |
1026 | * mdio interface in board design, and need to be configured by | |
1027 | * fec0 mii_bus. | |
1028 | */ | |
43af940c | 1029 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1030 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1031 | if (mii_cnt && fec0_mii_bus) { |
1032 | fep->mii_bus = fec0_mii_bus; | |
1033 | mii_cnt++; | |
1034 | return 0; | |
1035 | } | |
1036 | return -ENOENT; | |
b5680e0b SG |
1037 | } |
1038 | ||
e6b043d5 | 1039 | fep->mii_timeout = 0; |
1da177e4 | 1040 | |
e6b043d5 BW |
1041 | /* |
1042 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1043 | * |
1044 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1045 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1046 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1047 | * document. | |
e6b043d5 | 1048 | */ |
f4d40de3 | 1049 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1050 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1051 | fep->phy_speed--; | |
1052 | fep->phy_speed <<= 1; | |
e6b043d5 | 1053 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1054 | |
e6b043d5 BW |
1055 | fep->mii_bus = mdiobus_alloc(); |
1056 | if (fep->mii_bus == NULL) { | |
1057 | err = -ENOMEM; | |
1058 | goto err_out; | |
1da177e4 LT |
1059 | } |
1060 | ||
e6b043d5 BW |
1061 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1062 | fep->mii_bus->read = fec_enet_mdio_read; | |
1063 | fep->mii_bus->write = fec_enet_mdio_write; | |
1064 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1065 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1066 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1067 | fep->mii_bus->priv = fep; |
1068 | fep->mii_bus->parent = &pdev->dev; | |
1069 | ||
1070 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1071 | if (!fep->mii_bus->irq) { | |
1072 | err = -ENOMEM; | |
1073 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1074 | } |
1075 | ||
e6b043d5 BW |
1076 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1077 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1078 | |
e6b043d5 BW |
1079 | if (mdiobus_register(fep->mii_bus)) |
1080 | goto err_out_free_mdio_irq; | |
1da177e4 | 1081 | |
e163cc97 LW |
1082 | mii_cnt++; |
1083 | ||
b5680e0b SG |
1084 | /* save fec0 mii_bus */ |
1085 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1086 | fec0_mii_bus = fep->mii_bus; | |
1087 | ||
e6b043d5 | 1088 | return 0; |
1da177e4 | 1089 | |
e6b043d5 BW |
1090 | err_out_free_mdio_irq: |
1091 | kfree(fep->mii_bus->irq); | |
1092 | err_out_free_mdiobus: | |
1093 | mdiobus_free(fep->mii_bus); | |
1094 | err_out: | |
1095 | return err; | |
1da177e4 LT |
1096 | } |
1097 | ||
e6b043d5 | 1098 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1099 | { |
e163cc97 LW |
1100 | if (--mii_cnt == 0) { |
1101 | mdiobus_unregister(fep->mii_bus); | |
1102 | kfree(fep->mii_bus->irq); | |
1103 | mdiobus_free(fep->mii_bus); | |
1104 | } | |
1da177e4 LT |
1105 | } |
1106 | ||
c556167f | 1107 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1108 | struct ethtool_cmd *cmd) |
1da177e4 | 1109 | { |
c556167f | 1110 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1111 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1112 | |
e6b043d5 BW |
1113 | if (!phydev) |
1114 | return -ENODEV; | |
1da177e4 | 1115 | |
e6b043d5 | 1116 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1117 | } |
1118 | ||
c556167f | 1119 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1120 | struct ethtool_cmd *cmd) |
1da177e4 | 1121 | { |
c556167f | 1122 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1123 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1124 | |
e6b043d5 BW |
1125 | if (!phydev) |
1126 | return -ENODEV; | |
1da177e4 | 1127 | |
e6b043d5 | 1128 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1129 | } |
1130 | ||
c556167f | 1131 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1132 | struct ethtool_drvinfo *info) |
1da177e4 | 1133 | { |
c556167f | 1134 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1135 | |
e6b043d5 BW |
1136 | strcpy(info->driver, fep->pdev->dev.driver->name); |
1137 | strcpy(info->version, "Revision: 1.0"); | |
c556167f | 1138 | strcpy(info->bus_info, dev_name(&ndev->dev)); |
1da177e4 LT |
1139 | } |
1140 | ||
9b07be4b | 1141 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
e6b043d5 BW |
1142 | .get_settings = fec_enet_get_settings, |
1143 | .set_settings = fec_enet_set_settings, | |
1144 | .get_drvinfo = fec_enet_get_drvinfo, | |
1145 | .get_link = ethtool_op_get_link, | |
ec567bca | 1146 | .get_ts_info = ethtool_op_get_ts_info, |
e6b043d5 | 1147 | }; |
1da177e4 | 1148 | |
c556167f | 1149 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1150 | { |
c556167f | 1151 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1152 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1153 | |
c556167f | 1154 | if (!netif_running(ndev)) |
e6b043d5 | 1155 | return -EINVAL; |
1da177e4 | 1156 | |
e6b043d5 BW |
1157 | if (!phydev) |
1158 | return -ENODEV; | |
1159 | ||
6605b730 FL |
1160 | #ifdef CONFIG_FEC_PTP |
1161 | if (cmd == SIOCSHWTSTAMP) | |
1162 | return fec_ptp_ioctl(ndev, rq, cmd); | |
1163 | #endif | |
28b04113 | 1164 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1165 | } |
1166 | ||
c556167f | 1167 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1168 | { |
c556167f | 1169 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1170 | int i; |
1171 | struct sk_buff *skb; | |
1172 | struct bufdesc *bdp; | |
1173 | ||
1174 | bdp = fep->rx_bd_base; | |
1175 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1176 | skb = fep->rx_skbuff[i]; | |
1177 | ||
1178 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1179 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1180 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1181 | if (skb) | |
1182 | dev_kfree_skb(skb); | |
1183 | bdp++; | |
1184 | } | |
1185 | ||
1186 | bdp = fep->tx_bd_base; | |
1187 | for (i = 0; i < TX_RING_SIZE; i++) | |
1188 | kfree(fep->tx_bounce[i]); | |
1189 | } | |
1190 | ||
c556167f | 1191 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1192 | { |
c556167f | 1193 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1194 | int i; |
1195 | struct sk_buff *skb; | |
1196 | struct bufdesc *bdp; | |
1197 | ||
1198 | bdp = fep->rx_bd_base; | |
1199 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1200 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1201 | if (!skb) { |
c556167f | 1202 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1203 | return -ENOMEM; |
1204 | } | |
1205 | fep->rx_skbuff[i] = skb; | |
1206 | ||
d1ab1f54 | 1207 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1208 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1209 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
6605b730 FL |
1210 | #ifdef CONFIG_FEC_PTP |
1211 | bdp->cbd_esc = BD_ENET_RX_INT; | |
1212 | #endif | |
f0b3fbea SH |
1213 | bdp++; |
1214 | } | |
1215 | ||
1216 | /* Set the last buffer to wrap. */ | |
1217 | bdp--; | |
1218 | bdp->cbd_sc |= BD_SC_WRAP; | |
1219 | ||
1220 | bdp = fep->tx_bd_base; | |
1221 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1222 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1223 | ||
1224 | bdp->cbd_sc = 0; | |
1225 | bdp->cbd_bufaddr = 0; | |
6605b730 FL |
1226 | |
1227 | #ifdef CONFIG_FEC_PTP | |
1228 | bdp->cbd_esc = BD_ENET_RX_INT; | |
1229 | #endif | |
f0b3fbea SH |
1230 | bdp++; |
1231 | } | |
1232 | ||
1233 | /* Set the last buffer to wrap. */ | |
1234 | bdp--; | |
1235 | bdp->cbd_sc |= BD_SC_WRAP; | |
1236 | ||
1237 | return 0; | |
1238 | } | |
1239 | ||
1da177e4 | 1240 | static int |
c556167f | 1241 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1242 | { |
c556167f | 1243 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1244 | int ret; |
1da177e4 LT |
1245 | |
1246 | /* I should reset the ring buffers here, but I don't yet know | |
1247 | * a simple way to do that. | |
1248 | */ | |
1da177e4 | 1249 | |
c556167f | 1250 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1251 | if (ret) |
1252 | return ret; | |
1253 | ||
418bd0d4 | 1254 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1255 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1256 | if (ret) { |
c556167f | 1257 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1258 | return ret; |
1259 | } | |
e6b043d5 | 1260 | phy_start(fep->phy_dev); |
c556167f | 1261 | netif_start_queue(ndev); |
1da177e4 | 1262 | fep->opened = 1; |
22f6b860 | 1263 | return 0; |
1da177e4 LT |
1264 | } |
1265 | ||
1266 | static int | |
c556167f | 1267 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1268 | { |
c556167f | 1269 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1270 | |
22f6b860 | 1271 | /* Don't know what to do yet. */ |
1da177e4 | 1272 | fep->opened = 0; |
c556167f UKK |
1273 | netif_stop_queue(ndev); |
1274 | fec_stop(ndev); | |
1da177e4 | 1275 | |
e497ba82 UKK |
1276 | if (fep->phy_dev) { |
1277 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1278 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1279 | } |
418bd0d4 | 1280 | |
db8880bc | 1281 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1282 | |
1da177e4 LT |
1283 | return 0; |
1284 | } | |
1285 | ||
1da177e4 LT |
1286 | /* Set or clear the multicast filter for this adaptor. |
1287 | * Skeleton taken from sunlance driver. | |
1288 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1289 | * MAC address filtering. Some of the drivers check to make sure it is | |
1290 | * a group multicast address, and discard those that are not. I guess I | |
1291 | * will do the same for now, but just remove the test if you want | |
1292 | * individual filtering as well (do the upper net layers want or support | |
1293 | * this kind of feature?). | |
1294 | */ | |
1295 | ||
1296 | #define HASH_BITS 6 /* #bits in hash */ | |
1297 | #define CRC32_POLY 0xEDB88320 | |
1298 | ||
c556167f | 1299 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1300 | { |
c556167f | 1301 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1302 | struct netdev_hw_addr *ha; |
48e2f183 | 1303 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1304 | unsigned char hash; |
1305 | ||
c556167f | 1306 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1307 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1308 | tmp |= 0x8; | |
1309 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1310 | return; |
1311 | } | |
1da177e4 | 1312 | |
4e831836 SH |
1313 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1314 | tmp &= ~0x8; | |
1315 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1316 | ||
c556167f | 1317 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1318 | /* Catch all multicast addresses, so set the |
1319 | * filter to all 1's | |
1320 | */ | |
1321 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1322 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1323 | ||
1324 | return; | |
1325 | } | |
1326 | ||
1327 | /* Clear filter and add the addresses in hash register | |
1328 | */ | |
1329 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1330 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1331 | ||
c556167f | 1332 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1333 | /* calculate crc32 value of mac address */ |
1334 | crc = 0xffffffff; | |
1335 | ||
c556167f | 1336 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1337 | data = ha->addr[i]; |
4e831836 SH |
1338 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1339 | crc = (crc >> 1) ^ | |
1340 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1341 | } |
1342 | } | |
4e831836 SH |
1343 | |
1344 | /* only upper 6 bits (HASH_BITS) are used | |
1345 | * which point to specific bit in he hash registers | |
1346 | */ | |
1347 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1348 | ||
1349 | if (hash > 31) { | |
1350 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1351 | tmp |= 1 << (hash - 32); | |
1352 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1353 | } else { | |
1354 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1355 | tmp |= 1 << hash; | |
1356 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1357 | } | |
1da177e4 LT |
1358 | } |
1359 | } | |
1360 | ||
22f6b860 | 1361 | /* Set a MAC change in hardware. */ |
009fda83 | 1362 | static int |
c556167f | 1363 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1364 | { |
c556167f | 1365 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1366 | struct sockaddr *addr = p; |
1367 | ||
1368 | if (!is_valid_ether_addr(addr->sa_data)) | |
1369 | return -EADDRNOTAVAIL; | |
1370 | ||
c556167f | 1371 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1372 | |
c556167f UKK |
1373 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1374 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1375 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1376 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1377 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1378 | return 0; |
1da177e4 LT |
1379 | } |
1380 | ||
7f5c6add | 1381 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1382 | /** |
1383 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1384 | * @dev: The FEC network adapter |
1385 | * | |
1386 | * Polled functionality used by netconsole and others in non interrupt mode | |
1387 | * | |
1388 | */ | |
1389 | void fec_poll_controller(struct net_device *dev) | |
1390 | { | |
1391 | int i; | |
1392 | struct fec_enet_private *fep = netdev_priv(dev); | |
1393 | ||
1394 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1395 | if (fep->irq[i] > 0) { | |
1396 | disable_irq(fep->irq[i]); | |
1397 | fec_enet_interrupt(fep->irq[i], dev); | |
1398 | enable_irq(fep->irq[i]); | |
1399 | } | |
1400 | } | |
1401 | } | |
1402 | #endif | |
1403 | ||
009fda83 SH |
1404 | static const struct net_device_ops fec_netdev_ops = { |
1405 | .ndo_open = fec_enet_open, | |
1406 | .ndo_stop = fec_enet_close, | |
1407 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1408 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1409 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1410 | .ndo_validate_addr = eth_validate_addr, |
1411 | .ndo_tx_timeout = fec_timeout, | |
1412 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1413 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1414 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1415 | .ndo_poll_controller = fec_poll_controller, | |
1416 | #endif | |
009fda83 SH |
1417 | }; |
1418 | ||
1da177e4 LT |
1419 | /* |
1420 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1421 | * |
1da177e4 | 1422 | */ |
c556167f | 1423 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1424 | { |
c556167f | 1425 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1426 | struct bufdesc *cbd_base; |
633e7533 | 1427 | struct bufdesc *bdp; |
f0b3fbea | 1428 | int i; |
1da177e4 | 1429 | |
8d4dd5cf SH |
1430 | /* Allocate memory for buffer descriptors. */ |
1431 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1432 | GFP_KERNEL); | |
1433 | if (!cbd_base) { | |
562d2f8c GU |
1434 | printk("FEC: allocate descriptor memory failed?\n"); |
1435 | return -ENOMEM; | |
1436 | } | |
1437 | ||
3b2b74ca | 1438 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1439 | |
c556167f | 1440 | fep->netdev = ndev; |
1da177e4 | 1441 | |
49da97dc | 1442 | /* Get the Ethernet address */ |
c556167f | 1443 | fec_get_mac(ndev); |
1da177e4 | 1444 | |
8d4dd5cf | 1445 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1446 | fep->rx_bd_base = cbd_base; |
1447 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1448 | ||
22f6b860 | 1449 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1450 | ndev->watchdog_timeo = TX_TIMEOUT; |
1451 | ndev->netdev_ops = &fec_netdev_ops; | |
1452 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 RH |
1453 | |
1454 | /* Initialize the receive buffer descriptors. */ | |
1455 | bdp = fep->rx_bd_base; | |
1456 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1457 | ||
1458 | /* Initialize the BD for every fragment in the page. */ | |
1459 | bdp->cbd_sc = 0; | |
1460 | bdp++; | |
1461 | } | |
1462 | ||
1463 | /* Set the last buffer to wrap */ | |
1464 | bdp--; | |
1465 | bdp->cbd_sc |= BD_SC_WRAP; | |
1466 | ||
1467 | /* ...and the same for transmit */ | |
1468 | bdp = fep->tx_bd_base; | |
1469 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1470 | ||
1471 | /* Initialize the BD for every fragment in the page. */ | |
1472 | bdp->cbd_sc = 0; | |
1473 | bdp->cbd_bufaddr = 0; | |
1474 | bdp++; | |
1475 | } | |
1476 | ||
1477 | /* Set the last buffer to wrap */ | |
1478 | bdp--; | |
1479 | bdp->cbd_sc |= BD_SC_WRAP; | |
1480 | ||
c556167f | 1481 | fec_restart(ndev, 0); |
1da177e4 | 1482 | |
1da177e4 LT |
1483 | return 0; |
1484 | } | |
1485 | ||
ca2cc333 SG |
1486 | #ifdef CONFIG_OF |
1487 | static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev) | |
1488 | { | |
1489 | struct device_node *np = pdev->dev.of_node; | |
1490 | ||
1491 | if (np) | |
1492 | return of_get_phy_mode(np); | |
1493 | ||
1494 | return -ENODEV; | |
1495 | } | |
1496 | ||
a9b2c8ef | 1497 | static void __devinit fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1498 | { |
1499 | int err, phy_reset; | |
a3caad0a | 1500 | int msec = 1; |
ca2cc333 SG |
1501 | struct device_node *np = pdev->dev.of_node; |
1502 | ||
1503 | if (!np) | |
a9b2c8ef | 1504 | return; |
ca2cc333 | 1505 | |
a3caad0a SG |
1506 | of_property_read_u32(np, "phy-reset-duration", &msec); |
1507 | /* A sane reset duration should not be longer than 1s */ | |
1508 | if (msec > 1000) | |
1509 | msec = 1; | |
1510 | ||
ca2cc333 | 1511 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
119fc007 SG |
1512 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
1513 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 1514 | if (err) { |
a9b2c8ef SG |
1515 | pr_debug("FEC: failed to get gpio phy-reset: %d\n", err); |
1516 | return; | |
ca2cc333 | 1517 | } |
a3caad0a | 1518 | msleep(msec); |
ca2cc333 | 1519 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
1520 | } |
1521 | #else /* CONFIG_OF */ | |
1522 | static inline int fec_get_phy_mode_dt(struct platform_device *pdev) | |
1523 | { | |
1524 | return -ENODEV; | |
1525 | } | |
1526 | ||
a9b2c8ef | 1527 | static inline void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1528 | { |
1529 | /* | |
1530 | * In case of platform probe, the reset has been done | |
1531 | * by machine code. | |
1532 | */ | |
ca2cc333 SG |
1533 | } |
1534 | #endif /* CONFIG_OF */ | |
1535 | ||
ead73183 SH |
1536 | static int __devinit |
1537 | fec_probe(struct platform_device *pdev) | |
1538 | { | |
1539 | struct fec_enet_private *fep; | |
5eb32bd0 | 1540 | struct fec_platform_data *pdata; |
ead73183 SH |
1541 | struct net_device *ndev; |
1542 | int i, irq, ret = 0; | |
1543 | struct resource *r; | |
ca2cc333 | 1544 | const struct of_device_id *of_id; |
43af940c | 1545 | static int dev_id; |
b2bccee1 | 1546 | struct pinctrl *pinctrl; |
5fa9c0fe | 1547 | struct regulator *reg_phy; |
ca2cc333 SG |
1548 | |
1549 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
1550 | if (of_id) | |
1551 | pdev->id_entry = of_id->data; | |
ead73183 SH |
1552 | |
1553 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1554 | if (!r) | |
1555 | return -ENXIO; | |
1556 | ||
1557 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1558 | if (!r) | |
1559 | return -EBUSY; | |
1560 | ||
1561 | /* Init network device */ | |
1562 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
28e2188e UKK |
1563 | if (!ndev) { |
1564 | ret = -ENOMEM; | |
1565 | goto failed_alloc_etherdev; | |
1566 | } | |
ead73183 SH |
1567 | |
1568 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1569 | ||
1570 | /* setup board info structure */ | |
1571 | fep = netdev_priv(ndev); | |
ead73183 | 1572 | |
24e531b4 | 1573 | fep->hwp = ioremap(r->start, resource_size(r)); |
e6b043d5 | 1574 | fep->pdev = pdev; |
43af940c | 1575 | fep->dev_id = dev_id++; |
ead73183 | 1576 | |
24e531b4 | 1577 | if (!fep->hwp) { |
ead73183 SH |
1578 | ret = -ENOMEM; |
1579 | goto failed_ioremap; | |
1580 | } | |
1581 | ||
1582 | platform_set_drvdata(pdev, ndev); | |
1583 | ||
ca2cc333 SG |
1584 | ret = fec_get_phy_mode_dt(pdev); |
1585 | if (ret < 0) { | |
1586 | pdata = pdev->dev.platform_data; | |
1587 | if (pdata) | |
1588 | fep->phy_interface = pdata->phy; | |
1589 | else | |
1590 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
1591 | } else { | |
1592 | fep->phy_interface = ret; | |
1593 | } | |
1594 | ||
c7c83d1c | 1595 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
ead73183 | 1596 | irq = platform_get_irq(pdev, i); |
86f9f2c8 LW |
1597 | if (irq < 0) { |
1598 | if (i) | |
1599 | break; | |
1600 | ret = irq; | |
1601 | goto failed_irq; | |
1602 | } | |
ead73183 SH |
1603 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); |
1604 | if (ret) { | |
b2b09ad6 | 1605 | while (--i >= 0) { |
ead73183 SH |
1606 | irq = platform_get_irq(pdev, i); |
1607 | free_irq(irq, ndev); | |
ead73183 SH |
1608 | } |
1609 | goto failed_irq; | |
1610 | } | |
1611 | } | |
1612 | ||
b2bccee1 SG |
1613 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1614 | if (IS_ERR(pinctrl)) { | |
1615 | ret = PTR_ERR(pinctrl); | |
1616 | goto failed_pin; | |
1617 | } | |
1618 | ||
f4d40de3 SH |
1619 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1620 | if (IS_ERR(fep->clk_ipg)) { | |
1621 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
1622 | goto failed_clk; |
1623 | } | |
f4d40de3 SH |
1624 | |
1625 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1626 | if (IS_ERR(fep->clk_ahb)) { | |
1627 | ret = PTR_ERR(fep->clk_ahb); | |
1628 | goto failed_clk; | |
1629 | } | |
1630 | ||
6605b730 FL |
1631 | #ifdef CONFIG_FEC_PTP |
1632 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); | |
1633 | if (IS_ERR(fep->clk_ptp)) { | |
1634 | ret = PTR_ERR(fep->clk_ptp); | |
1635 | goto failed_clk; | |
1636 | } | |
1637 | #endif | |
1638 | ||
f4d40de3 SH |
1639 | clk_prepare_enable(fep->clk_ahb); |
1640 | clk_prepare_enable(fep->clk_ipg); | |
6605b730 FL |
1641 | #ifdef CONFIG_FEC_PTP |
1642 | clk_prepare_enable(fep->clk_ptp); | |
1643 | #endif | |
5fa9c0fe SG |
1644 | reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
1645 | if (!IS_ERR(reg_phy)) { | |
1646 | ret = regulator_enable(reg_phy); | |
1647 | if (ret) { | |
1648 | dev_err(&pdev->dev, | |
1649 | "Failed to enable phy regulator: %d\n", ret); | |
1650 | goto failed_regulator; | |
1651 | } | |
1652 | } | |
1653 | ||
2ca9b2aa SG |
1654 | fec_reset_phy(pdev); |
1655 | ||
8649a230 | 1656 | ret = fec_enet_init(ndev); |
ead73183 SH |
1657 | if (ret) |
1658 | goto failed_init; | |
1659 | ||
e6b043d5 BW |
1660 | ret = fec_enet_mii_init(pdev); |
1661 | if (ret) | |
1662 | goto failed_mii_init; | |
1663 | ||
03c698c9 OS |
1664 | /* Carrier starts down, phylib will bring it up */ |
1665 | netif_carrier_off(ndev); | |
1666 | ||
ead73183 SH |
1667 | ret = register_netdev(ndev); |
1668 | if (ret) | |
1669 | goto failed_register; | |
1670 | ||
6605b730 FL |
1671 | #ifdef CONFIG_FEC_PTP |
1672 | fec_ptp_init(ndev, pdev); | |
1673 | #endif | |
1674 | ||
ead73183 SH |
1675 | return 0; |
1676 | ||
1677 | failed_register: | |
e6b043d5 BW |
1678 | fec_enet_mii_remove(fep); |
1679 | failed_mii_init: | |
ead73183 | 1680 | failed_init: |
5fa9c0fe | 1681 | failed_regulator: |
f4d40de3 SH |
1682 | clk_disable_unprepare(fep->clk_ahb); |
1683 | clk_disable_unprepare(fep->clk_ipg); | |
6605b730 FL |
1684 | #ifdef CONFIG_FEC_PTP |
1685 | clk_disable_unprepare(fep->clk_ptp); | |
1686 | #endif | |
b2bccee1 | 1687 | failed_pin: |
ead73183 | 1688 | failed_clk: |
c7c83d1c | 1689 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
ead73183 SH |
1690 | irq = platform_get_irq(pdev, i); |
1691 | if (irq > 0) | |
1692 | free_irq(irq, ndev); | |
1693 | } | |
1694 | failed_irq: | |
24e531b4 | 1695 | iounmap(fep->hwp); |
ead73183 SH |
1696 | failed_ioremap: |
1697 | free_netdev(ndev); | |
28e2188e UKK |
1698 | failed_alloc_etherdev: |
1699 | release_mem_region(r->start, resource_size(r)); | |
ead73183 SH |
1700 | |
1701 | return ret; | |
1702 | } | |
1703 | ||
1704 | static int __devexit | |
1705 | fec_drv_remove(struct platform_device *pdev) | |
1706 | { | |
1707 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1708 | struct fec_enet_private *fep = netdev_priv(ndev); | |
28e2188e | 1709 | struct resource *r; |
e163cc97 | 1710 | int i; |
ead73183 | 1711 | |
e163cc97 | 1712 | unregister_netdev(ndev); |
e6b043d5 | 1713 | fec_enet_mii_remove(fep); |
e163cc97 LW |
1714 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
1715 | int irq = platform_get_irq(pdev, i); | |
1716 | if (irq > 0) | |
1717 | free_irq(irq, ndev); | |
1718 | } | |
6605b730 FL |
1719 | #ifdef CONFIG_FEC_PTP |
1720 | del_timer_sync(&fep->time_keep); | |
1721 | clk_disable_unprepare(fep->clk_ptp); | |
1722 | if (fep->ptp_clock) | |
1723 | ptp_clock_unregister(fep->ptp_clock); | |
1724 | #endif | |
f4d40de3 SH |
1725 | clk_disable_unprepare(fep->clk_ahb); |
1726 | clk_disable_unprepare(fep->clk_ipg); | |
24e531b4 | 1727 | iounmap(fep->hwp); |
ead73183 | 1728 | free_netdev(ndev); |
28e2188e UKK |
1729 | |
1730 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1731 | BUG_ON(!r); | |
1732 | release_mem_region(r->start, resource_size(r)); | |
1733 | ||
b3cde36c UKK |
1734 | platform_set_drvdata(pdev, NULL); |
1735 | ||
ead73183 SH |
1736 | return 0; |
1737 | } | |
1738 | ||
59d4289b | 1739 | #ifdef CONFIG_PM |
ead73183 | 1740 | static int |
87cad5c3 | 1741 | fec_suspend(struct device *dev) |
ead73183 | 1742 | { |
87cad5c3 | 1743 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1744 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1745 | |
04e5216d UKK |
1746 | if (netif_running(ndev)) { |
1747 | fec_stop(ndev); | |
1748 | netif_device_detach(ndev); | |
ead73183 | 1749 | } |
f4d40de3 SH |
1750 | clk_disable_unprepare(fep->clk_ahb); |
1751 | clk_disable_unprepare(fep->clk_ipg); | |
04e5216d | 1752 | |
ead73183 SH |
1753 | return 0; |
1754 | } | |
1755 | ||
1756 | static int | |
87cad5c3 | 1757 | fec_resume(struct device *dev) |
ead73183 | 1758 | { |
87cad5c3 | 1759 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1760 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1761 | |
f4d40de3 SH |
1762 | clk_prepare_enable(fep->clk_ahb); |
1763 | clk_prepare_enable(fep->clk_ipg); | |
04e5216d UKK |
1764 | if (netif_running(ndev)) { |
1765 | fec_restart(ndev, fep->full_duplex); | |
1766 | netif_device_attach(ndev); | |
ead73183 | 1767 | } |
04e5216d | 1768 | |
ead73183 SH |
1769 | return 0; |
1770 | } | |
1771 | ||
59d4289b DK |
1772 | static const struct dev_pm_ops fec_pm_ops = { |
1773 | .suspend = fec_suspend, | |
1774 | .resume = fec_resume, | |
1775 | .freeze = fec_suspend, | |
1776 | .thaw = fec_resume, | |
1777 | .poweroff = fec_suspend, | |
1778 | .restore = fec_resume, | |
1779 | }; | |
87cad5c3 | 1780 | #endif |
59d4289b | 1781 | |
ead73183 SH |
1782 | static struct platform_driver fec_driver = { |
1783 | .driver = { | |
b5680e0b | 1784 | .name = DRIVER_NAME, |
87cad5c3 EB |
1785 | .owner = THIS_MODULE, |
1786 | #ifdef CONFIG_PM | |
1787 | .pm = &fec_pm_ops, | |
1788 | #endif | |
ca2cc333 | 1789 | .of_match_table = fec_dt_ids, |
ead73183 | 1790 | }, |
b5680e0b | 1791 | .id_table = fec_devtype, |
87cad5c3 EB |
1792 | .probe = fec_probe, |
1793 | .remove = __devexit_p(fec_drv_remove), | |
ead73183 SH |
1794 | }; |
1795 | ||
aaca2377 | 1796 | module_platform_driver(fec_driver); |
1da177e4 LT |
1797 | |
1798 | MODULE_LICENSE("GPL"); |