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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/bitops.h> | |
6f501b17 SH |
41 | #include <linux/io.h> |
42 | #include <linux/irq.h> | |
196719ec | 43 | #include <linux/clk.h> |
ead73183 | 44 | #include <linux/platform_device.h> |
e6b043d5 | 45 | #include <linux/phy.h> |
5eb32bd0 | 46 | #include <linux/fec.h> |
ca2cc333 SG |
47 | #include <linux/of.h> |
48 | #include <linux/of_device.h> | |
49 | #include <linux/of_gpio.h> | |
50 | #include <linux/of_net.h> | |
1da177e4 | 51 | |
080853af | 52 | #include <asm/cacheflush.h> |
196719ec | 53 | |
b5680e0b | 54 | #ifndef CONFIG_ARM |
1da177e4 LT |
55 | #include <asm/coldfire.h> |
56 | #include <asm/mcfsim.h> | |
196719ec | 57 | #endif |
6f501b17 | 58 | |
1da177e4 | 59 | #include "fec.h" |
1da177e4 | 60 | |
085e79ed | 61 | #if defined(CONFIG_ARM) |
196719ec SH |
62 | #define FEC_ALIGNMENT 0xf |
63 | #else | |
64 | #define FEC_ALIGNMENT 0x3 | |
65 | #endif | |
66 | ||
b5680e0b SG |
67 | #define DRIVER_NAME "fec" |
68 | ||
69 | /* Controller is ENET-MAC */ | |
70 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
71 | /* Controller needs driver to swap frame */ | |
72 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
73 | /* Controller uses gasket */ |
74 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
75 | /* Controller has GBIT support */ |
76 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
b5680e0b SG |
77 | |
78 | static struct platform_device_id fec_devtype[] = { | |
79 | { | |
0ca1e290 | 80 | /* keep it for coldfire */ |
b5680e0b SG |
81 | .name = DRIVER_NAME, |
82 | .driver_data = 0, | |
0ca1e290 SG |
83 | }, { |
84 | .name = "imx25-fec", | |
85 | .driver_data = FEC_QUIRK_USE_GASKET, | |
86 | }, { | |
87 | .name = "imx27-fec", | |
88 | .driver_data = 0, | |
b5680e0b SG |
89 | }, { |
90 | .name = "imx28-fec", | |
91 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
92 | }, { |
93 | .name = "imx6q-fec", | |
94 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT, | |
0ca1e290 SG |
95 | }, { |
96 | /* sentinel */ | |
97 | } | |
b5680e0b | 98 | }; |
0ca1e290 | 99 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 100 | |
ca2cc333 SG |
101 | enum imx_fec_type { |
102 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ | |
103 | IMX27_FEC, /* runs on i.mx27/35/51 */ | |
104 | IMX28_FEC, | |
230dec61 | 105 | IMX6Q_FEC, |
ca2cc333 SG |
106 | }; |
107 | ||
108 | static const struct of_device_id fec_dt_ids[] = { | |
109 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
110 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
111 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 112 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
ca2cc333 SG |
113 | { /* sentinel */ } |
114 | }; | |
115 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
116 | ||
49da97dc SG |
117 | static unsigned char macaddr[ETH_ALEN]; |
118 | module_param_array(macaddr, byte, NULL, 0); | |
119 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 120 | |
49da97dc | 121 | #if defined(CONFIG_M5272) |
1da177e4 LT |
122 | /* |
123 | * Some hardware gets it MAC address out of local flash memory. | |
124 | * if this is non-zero then assume it is the address to get MAC from. | |
125 | */ | |
126 | #if defined(CONFIG_NETtel) | |
127 | #define FEC_FLASHMAC 0xf0006006 | |
128 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
129 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
130 | #elif defined(CONFIG_CANCam) |
131 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
132 | #elif defined (CONFIG_M5272C3) |
133 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
134 | #elif defined(CONFIG_MOD5272) | |
135 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
136 | #else |
137 | #define FEC_FLASHMAC 0 | |
138 | #endif | |
43be6366 | 139 | #endif /* CONFIG_M5272 */ |
ead73183 | 140 | |
1da177e4 LT |
141 | /* The number of Tx and Rx buffers. These are allocated from the page |
142 | * pool. The code may assume these are power of two, so it it best | |
143 | * to keep them that size. | |
144 | * We don't need to allocate pages for the transmitter. We just use | |
145 | * the skbuffer directly. | |
146 | */ | |
147 | #define FEC_ENET_RX_PAGES 8 | |
148 | #define FEC_ENET_RX_FRSIZE 2048 | |
149 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
150 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
151 | #define FEC_ENET_TX_FRSIZE 2048 | |
152 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
153 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
154 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
155 | ||
562d2f8c | 156 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 157 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
158 | #endif |
159 | ||
22f6b860 | 160 | /* Interrupt events/masks. */ |
1da177e4 LT |
161 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
162 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
163 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
164 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
165 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
166 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
167 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
168 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
169 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
170 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
171 | ||
4bee1f9a WS |
172 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
173 | ||
1da177e4 LT |
174 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
175 | */ | |
176 | #define PKT_MAXBUF_SIZE 1518 | |
177 | #define PKT_MINBUF_SIZE 64 | |
178 | #define PKT_MAXBLR_SIZE 1520 | |
179 | ||
c7c83d1c XJ |
180 | /* This device has up to three irqs on some platforms */ |
181 | #define FEC_IRQ_NUM 3 | |
1da177e4 LT |
182 | |
183 | /* | |
6b265293 | 184 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
185 | * size bits. Other FEC hardware does not, so we need to take that into |
186 | * account when setting it. | |
187 | */ | |
562d2f8c | 188 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 189 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
190 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
191 | #else | |
192 | #define OPT_FRAME_SIZE 0 | |
193 | #endif | |
194 | ||
195 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
196 | * tx_bd_base always point to the base of the buffer descriptors. The | |
197 | * cur_rx and cur_tx point to the currently available buffer. | |
198 | * The dirty_tx tracks the current buffer that is being sent by the | |
199 | * controller. The cur_tx and dirty_tx are equal under both completely | |
200 | * empty and completely full conditions. The empty/ready indicator in | |
201 | * the buffer descriptor determines the actual condition. | |
202 | */ | |
203 | struct fec_enet_private { | |
204 | /* Hardware registers of the FEC device */ | |
f44d6305 | 205 | void __iomem *hwp; |
1da177e4 | 206 | |
cb84d6e7 GU |
207 | struct net_device *netdev; |
208 | ||
ead73183 SH |
209 | struct clk *clk; |
210 | ||
1da177e4 LT |
211 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
212 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
213 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
f0b3fbea | 214 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
1da177e4 LT |
215 | ushort skb_cur; |
216 | ushort skb_dirty; | |
217 | ||
22f6b860 | 218 | /* CPM dual port RAM relative addresses */ |
4661e75b | 219 | dma_addr_t bd_dma; |
22f6b860 | 220 | /* Address of Rx and Tx buffers */ |
2e28532f SH |
221 | struct bufdesc *rx_bd_base; |
222 | struct bufdesc *tx_bd_base; | |
223 | /* The next free ring entry */ | |
db8880bc | 224 | struct bufdesc *cur_rx, *cur_tx; |
22f6b860 | 225 | /* The ring entries to be free()ed */ |
2e28532f SH |
226 | struct bufdesc *dirty_tx; |
227 | ||
1da177e4 | 228 | uint tx_full; |
3b2b74ca SS |
229 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
230 | spinlock_t hw_lock; | |
1da177e4 | 231 | |
db8880bc | 232 | struct platform_device *pdev; |
1da177e4 | 233 | |
e6b043d5 | 234 | int opened; |
43af940c | 235 | int dev_id; |
1da177e4 | 236 | |
e6b043d5 | 237 | /* Phylib and MDIO interface */ |
db8880bc UKK |
238 | struct mii_bus *mii_bus; |
239 | struct phy_device *phy_dev; | |
240 | int mii_timeout; | |
241 | uint phy_speed; | |
5eb32bd0 | 242 | phy_interface_t phy_interface; |
1da177e4 | 243 | int link; |
1da177e4 | 244 | int full_duplex; |
97b72e43 | 245 | struct completion mdio_done; |
7f5c6add | 246 | int irq[FEC_IRQ_NUM]; |
1da177e4 LT |
247 | }; |
248 | ||
e6b043d5 BW |
249 | /* FEC MII MMFR bits definition */ |
250 | #define FEC_MMFR_ST (1 << 30) | |
251 | #define FEC_MMFR_OP_READ (2 << 28) | |
252 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
253 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
254 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
255 | #define FEC_MMFR_TA (2 << 16) | |
256 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 257 | |
97b72e43 | 258 | #define FEC_MII_TIMEOUT 1000 /* us */ |
1da177e4 | 259 | |
22f6b860 SH |
260 | /* Transmitter timeout */ |
261 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 262 | |
b5680e0b SG |
263 | static void *swap_buffer(void *bufaddr, int len) |
264 | { | |
265 | int i; | |
266 | unsigned int *buf = bufaddr; | |
267 | ||
268 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
269 | *buf = cpu_to_be32(*buf); | |
270 | ||
271 | return bufaddr; | |
272 | } | |
273 | ||
c7621cb3 | 274 | static netdev_tx_t |
c556167f | 275 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 276 | { |
c556167f | 277 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
278 | const struct platform_device_id *id_entry = |
279 | platform_get_device_id(fep->pdev); | |
2e28532f | 280 | struct bufdesc *bdp; |
9555b31e | 281 | void *bufaddr; |
0e702ab3 | 282 | unsigned short status; |
3b2b74ca | 283 | unsigned long flags; |
1da177e4 | 284 | |
1da177e4 LT |
285 | if (!fep->link) { |
286 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 287 | return NETDEV_TX_BUSY; |
1da177e4 LT |
288 | } |
289 | ||
3b2b74ca | 290 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
291 | /* Fill in a Tx ring entry */ |
292 | bdp = fep->cur_tx; | |
293 | ||
0e702ab3 | 294 | status = bdp->cbd_sc; |
22f6b860 | 295 | |
0e702ab3 | 296 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 297 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 298 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 299 | */ |
c556167f | 300 | printk("%s: tx queue full!.\n", ndev->name); |
3b2b74ca | 301 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
5b548140 | 302 | return NETDEV_TX_BUSY; |
1da177e4 | 303 | } |
1da177e4 | 304 | |
22f6b860 | 305 | /* Clear all of the status flags */ |
0e702ab3 | 306 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 307 | |
22f6b860 | 308 | /* Set buffer length and buffer pointer */ |
9555b31e | 309 | bufaddr = skb->data; |
1da177e4 LT |
310 | bdp->cbd_datlen = skb->len; |
311 | ||
312 | /* | |
22f6b860 SH |
313 | * On some FEC implementations data must be aligned on |
314 | * 4-byte boundaries. Use bounce buffers to copy data | |
315 | * and get it aligned. Ugh. | |
1da177e4 | 316 | */ |
9555b31e | 317 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
1da177e4 LT |
318 | unsigned int index; |
319 | index = bdp - fep->tx_bd_base; | |
8a73b0bc | 320 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 321 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
322 | } |
323 | ||
b5680e0b SG |
324 | /* |
325 | * Some design made an incorrect assumption on endian mode of | |
326 | * the system that it's running on. As the result, driver has to | |
327 | * swap every frame going to and coming from the controller. | |
328 | */ | |
329 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
330 | swap_buffer(bufaddr, skb->len); | |
331 | ||
22f6b860 | 332 | /* Save skb pointer */ |
1da177e4 LT |
333 | fep->tx_skbuff[fep->skb_cur] = skb; |
334 | ||
c556167f | 335 | ndev->stats.tx_bytes += skb->len; |
1da177e4 | 336 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 337 | |
1da177e4 LT |
338 | /* Push the data cache so the CPM does not get stale memory |
339 | * data. | |
340 | */ | |
d1ab1f54 | 341 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 342 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 343 | |
0e702ab3 GU |
344 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
345 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 346 | */ |
0e702ab3 | 347 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 348 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 349 | bdp->cbd_sc = status; |
1da177e4 | 350 | |
1da177e4 | 351 | /* Trigger transmission start */ |
f44d6305 | 352 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 353 | |
22f6b860 SH |
354 | /* If this was the last BD in the ring, start at the beginning again. */ |
355 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 356 | bdp = fep->tx_bd_base; |
22f6b860 | 357 | else |
1da177e4 | 358 | bdp++; |
1da177e4 LT |
359 | |
360 | if (bdp == fep->dirty_tx) { | |
361 | fep->tx_full = 1; | |
c556167f | 362 | netif_stop_queue(ndev); |
1da177e4 LT |
363 | } |
364 | ||
2e28532f | 365 | fep->cur_tx = bdp; |
1da177e4 | 366 | |
18a03b97 RC |
367 | skb_tx_timestamp(skb); |
368 | ||
a0087a36 RC |
369 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
370 | ||
6ed10654 | 371 | return NETDEV_TX_OK; |
1da177e4 LT |
372 | } |
373 | ||
45993653 UKK |
374 | /* This function is called to start or restart the FEC during a link |
375 | * change. This only happens when switching between half and full | |
376 | * duplex. | |
377 | */ | |
1da177e4 | 378 | static void |
45993653 | 379 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 380 | { |
c556167f | 381 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
382 | const struct platform_device_id *id_entry = |
383 | platform_get_device_id(fep->pdev); | |
384 | int i; | |
cd1f402c UKK |
385 | u32 temp_mac[2]; |
386 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 387 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 388 | |
45993653 UKK |
389 | /* Whack a reset. We should wait for this. */ |
390 | writel(1, fep->hwp + FEC_ECNTRL); | |
391 | udelay(10); | |
1da177e4 | 392 | |
45993653 UKK |
393 | /* |
394 | * enet-mac reset will reset mac address registers too, | |
395 | * so need to reconfigure it. | |
396 | */ | |
397 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
398 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
399 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
400 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
401 | } | |
1da177e4 | 402 | |
45993653 UKK |
403 | /* Clear any outstanding interrupt. */ |
404 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 405 | |
45993653 UKK |
406 | /* Reset all multicast. */ |
407 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
408 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
409 | #ifndef CONFIG_M5272 | |
410 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
411 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
412 | #endif | |
1da177e4 | 413 | |
45993653 UKK |
414 | /* Set maximum receive buffer size. */ |
415 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 416 | |
45993653 UKK |
417 | /* Set receive and transmit descriptor base. */ |
418 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
419 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, | |
420 | fep->hwp + FEC_X_DES_START); | |
421 | ||
422 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
423 | fep->cur_rx = fep->rx_bd_base; | |
424 | ||
425 | /* Reset SKB transmit buffers. */ | |
426 | fep->skb_cur = fep->skb_dirty = 0; | |
427 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { | |
428 | if (fep->tx_skbuff[i]) { | |
429 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
430 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 431 | } |
45993653 | 432 | } |
97b72e43 | 433 | |
45993653 UKK |
434 | /* Enable MII mode */ |
435 | if (duplex) { | |
cd1f402c | 436 | /* FD enable */ |
45993653 UKK |
437 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
438 | } else { | |
cd1f402c UKK |
439 | /* No Rcv on Xmit */ |
440 | rcntl |= 0x02; | |
45993653 UKK |
441 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
442 | } | |
cd1f402c | 443 | |
45993653 UKK |
444 | fep->full_duplex = duplex; |
445 | ||
446 | /* Set MII speed */ | |
447 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
448 | ||
449 | /* | |
450 | * The phy interface and speed need to get configured | |
451 | * differently on enet-mac. | |
452 | */ | |
453 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
454 | /* Enable flow control and length check */ |
455 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 456 | |
230dec61 SG |
457 | /* RGMII, RMII or MII */ |
458 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
459 | rcntl |= (1 << 6); | |
460 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 461 | rcntl |= (1 << 8); |
45993653 | 462 | else |
cd1f402c | 463 | rcntl &= ~(1 << 8); |
45993653 | 464 | |
230dec61 SG |
465 | /* 1G, 100M or 10M */ |
466 | if (fep->phy_dev) { | |
467 | if (fep->phy_dev->speed == SPEED_1000) | |
468 | ecntl |= (1 << 5); | |
469 | else if (fep->phy_dev->speed == SPEED_100) | |
470 | rcntl &= ~(1 << 9); | |
471 | else | |
472 | rcntl |= (1 << 9); | |
473 | } | |
45993653 UKK |
474 | } else { |
475 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 476 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
45993653 UKK |
477 | /* disable the gasket and wait */ |
478 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
479 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
480 | udelay(1); | |
481 | ||
482 | /* | |
483 | * configure the gasket: | |
484 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 485 | * MII, 25 MHz, no loopback, no echo |
45993653 | 486 | */ |
0ca1e290 SG |
487 | writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ? |
488 | 1 : 0, fep->hwp + FEC_MIIGSK_CFGR); | |
489 | ||
45993653 UKK |
490 | |
491 | /* re-enable the gasket */ | |
492 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 493 | } |
45993653 UKK |
494 | #endif |
495 | } | |
cd1f402c | 496 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 497 | |
230dec61 SG |
498 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
499 | /* enable ENET endian swap */ | |
500 | ecntl |= (1 << 8); | |
501 | /* enable ENET store and forward mode */ | |
502 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
503 | } | |
504 | ||
45993653 | 505 | /* And last, enable the transmit and receive processing */ |
230dec61 | 506 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
507 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
508 | ||
509 | /* Enable interrupts we wish to service */ | |
510 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
511 | } | |
512 | ||
513 | static void | |
514 | fec_stop(struct net_device *ndev) | |
515 | { | |
516 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
517 | const struct platform_device_id *id_entry = |
518 | platform_get_device_id(fep->pdev); | |
45993653 UKK |
519 | |
520 | /* We cannot expect a graceful transmit stop without link !!! */ | |
521 | if (fep->link) { | |
522 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
523 | udelay(10); | |
524 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
525 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
526 | } | |
527 | ||
528 | /* Whack a reset. We should wait for this. */ | |
529 | writel(1, fep->hwp + FEC_ECNTRL); | |
530 | udelay(10); | |
531 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
532 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
533 | |
534 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
535 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
536 | writel(2, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
537 | } |
538 | ||
539 | ||
45993653 UKK |
540 | static void |
541 | fec_timeout(struct net_device *ndev) | |
542 | { | |
543 | struct fec_enet_private *fep = netdev_priv(ndev); | |
544 | ||
545 | ndev->stats.tx_errors++; | |
546 | ||
547 | fec_restart(ndev, fep->full_duplex); | |
548 | netif_wake_queue(ndev); | |
549 | } | |
550 | ||
1da177e4 | 551 | static void |
c556167f | 552 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
553 | { |
554 | struct fec_enet_private *fep; | |
2e28532f | 555 | struct bufdesc *bdp; |
0e702ab3 | 556 | unsigned short status; |
1da177e4 LT |
557 | struct sk_buff *skb; |
558 | ||
c556167f | 559 | fep = netdev_priv(ndev); |
81538e74 | 560 | spin_lock(&fep->hw_lock); |
1da177e4 LT |
561 | bdp = fep->dirty_tx; |
562 | ||
0e702ab3 | 563 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
f0b3fbea SH |
564 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
565 | break; | |
566 | ||
d1ab1f54 UKK |
567 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
568 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 569 | bdp->cbd_bufaddr = 0; |
1da177e4 LT |
570 | |
571 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
572 | /* Check for errors. */ | |
0e702ab3 | 573 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
574 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
575 | BD_ENET_TX_CSL)) { | |
c556167f | 576 | ndev->stats.tx_errors++; |
0e702ab3 | 577 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 578 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 579 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 580 | ndev->stats.tx_window_errors++; |
0e702ab3 | 581 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 582 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 583 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 584 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 585 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 586 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 587 | } else { |
c556167f | 588 | ndev->stats.tx_packets++; |
1da177e4 LT |
589 | } |
590 | ||
0e702ab3 | 591 | if (status & BD_ENET_TX_READY) |
1da177e4 | 592 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 593 | |
1da177e4 LT |
594 | /* Deferred means some collisions occurred during transmit, |
595 | * but we eventually sent the packet OK. | |
596 | */ | |
0e702ab3 | 597 | if (status & BD_ENET_TX_DEF) |
c556167f | 598 | ndev->stats.collisions++; |
6aa20a22 | 599 | |
22f6b860 | 600 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
601 | dev_kfree_skb_any(skb); |
602 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
603 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 604 | |
22f6b860 | 605 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 606 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
607 | bdp = fep->tx_bd_base; |
608 | else | |
609 | bdp++; | |
6aa20a22 | 610 | |
22f6b860 | 611 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
612 | */ |
613 | if (fep->tx_full) { | |
614 | fep->tx_full = 0; | |
c556167f UKK |
615 | if (netif_queue_stopped(ndev)) |
616 | netif_wake_queue(ndev); | |
1da177e4 LT |
617 | } |
618 | } | |
2e28532f | 619 | fep->dirty_tx = bdp; |
81538e74 | 620 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
621 | } |
622 | ||
623 | ||
624 | /* During a receive, the cur_rx points to the current incoming buffer. | |
625 | * When we update through the ring, if the next incoming buffer has | |
626 | * not been given to the system, we just set the empty indicator, | |
627 | * effectively tossing the packet. | |
628 | */ | |
629 | static void | |
c556167f | 630 | fec_enet_rx(struct net_device *ndev) |
1da177e4 | 631 | { |
c556167f | 632 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
633 | const struct platform_device_id *id_entry = |
634 | platform_get_device_id(fep->pdev); | |
2e28532f | 635 | struct bufdesc *bdp; |
0e702ab3 | 636 | unsigned short status; |
1da177e4 LT |
637 | struct sk_buff *skb; |
638 | ushort pkt_len; | |
639 | __u8 *data; | |
6aa20a22 | 640 | |
0e702ab3 GU |
641 | #ifdef CONFIG_M532x |
642 | flush_cache_all(); | |
6aa20a22 | 643 | #endif |
1da177e4 | 644 | |
81538e74 | 645 | spin_lock(&fep->hw_lock); |
3b2b74ca | 646 | |
1da177e4 LT |
647 | /* First, grab all of the stats for the incoming packet. |
648 | * These get messed up if we get called due to a busy condition. | |
649 | */ | |
650 | bdp = fep->cur_rx; | |
651 | ||
22f6b860 | 652 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 653 | |
22f6b860 SH |
654 | /* Since we have allocated space to hold a complete frame, |
655 | * the last indicator should be set. | |
656 | */ | |
657 | if ((status & BD_ENET_RX_LAST) == 0) | |
658 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 659 | |
22f6b860 SH |
660 | if (!fep->opened) |
661 | goto rx_processing_done; | |
1da177e4 | 662 | |
22f6b860 SH |
663 | /* Check for errors. */ |
664 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 665 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 666 | ndev->stats.rx_errors++; |
22f6b860 SH |
667 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
668 | /* Frame too long or too short. */ | |
c556167f | 669 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
670 | } |
671 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 672 | ndev->stats.rx_frame_errors++; |
22f6b860 | 673 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 674 | ndev->stats.rx_crc_errors++; |
22f6b860 | 675 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 676 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 677 | } |
1da177e4 | 678 | |
22f6b860 SH |
679 | /* Report late collisions as a frame error. |
680 | * On this error, the BD is closed, but we don't know what we | |
681 | * have in the buffer. So, just drop this frame on the floor. | |
682 | */ | |
683 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
684 | ndev->stats.rx_errors++; |
685 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
686 | goto rx_processing_done; |
687 | } | |
1da177e4 | 688 | |
22f6b860 | 689 | /* Process the incoming frame. */ |
c556167f | 690 | ndev->stats.rx_packets++; |
22f6b860 | 691 | pkt_len = bdp->cbd_datlen; |
c556167f | 692 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 693 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 694 | |
d1ab1f54 UKK |
695 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
696 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 697 | |
b5680e0b SG |
698 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
699 | swap_buffer(data, pkt_len); | |
700 | ||
22f6b860 SH |
701 | /* This does 16 byte alignment, exactly what we need. |
702 | * The packet length includes FCS, but we don't want to | |
703 | * include that when passing upstream as it messes up | |
704 | * bridging applications. | |
705 | */ | |
8549889c | 706 | skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 707 | |
8549889c | 708 | if (unlikely(!skb)) { |
22f6b860 | 709 | printk("%s: Memory squeeze, dropping packet.\n", |
c556167f UKK |
710 | ndev->name); |
711 | ndev->stats.rx_dropped++; | |
22f6b860 | 712 | } else { |
8549889c | 713 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
714 | skb_put(skb, pkt_len - 4); /* Make room */ |
715 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 716 | skb->protocol = eth_type_trans(skb, ndev); |
18a03b97 RC |
717 | if (!skb_defer_rx_timestamp(skb)) |
718 | netif_rx(skb); | |
22f6b860 | 719 | } |
f0b3fbea | 720 | |
d1ab1f54 UKK |
721 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
722 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
723 | rx_processing_done: |
724 | /* Clear the status flags for this buffer */ | |
725 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 726 | |
22f6b860 SH |
727 | /* Mark the buffer empty */ |
728 | status |= BD_ENET_RX_EMPTY; | |
729 | bdp->cbd_sc = status; | |
6aa20a22 | 730 | |
22f6b860 SH |
731 | /* Update BD pointer to next entry */ |
732 | if (status & BD_ENET_RX_WRAP) | |
733 | bdp = fep->rx_bd_base; | |
734 | else | |
735 | bdp++; | |
736 | /* Doing this here will keep the FEC running while we process | |
737 | * incoming frames. On a heavily loaded network, we should be | |
738 | * able to keep up at the expense of system resources. | |
739 | */ | |
740 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
741 | } | |
2e28532f | 742 | fep->cur_rx = bdp; |
1da177e4 | 743 | |
81538e74 | 744 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
745 | } |
746 | ||
45993653 UKK |
747 | static irqreturn_t |
748 | fec_enet_interrupt(int irq, void *dev_id) | |
749 | { | |
750 | struct net_device *ndev = dev_id; | |
751 | struct fec_enet_private *fep = netdev_priv(ndev); | |
752 | uint int_events; | |
753 | irqreturn_t ret = IRQ_NONE; | |
754 | ||
755 | do { | |
756 | int_events = readl(fep->hwp + FEC_IEVENT); | |
757 | writel(int_events, fep->hwp + FEC_IEVENT); | |
758 | ||
759 | if (int_events & FEC_ENET_RXF) { | |
760 | ret = IRQ_HANDLED; | |
761 | fec_enet_rx(ndev); | |
762 | } | |
763 | ||
764 | /* Transmit OK, or non-fatal error. Update the buffer | |
765 | * descriptors. FEC handles all errors, we just discover | |
766 | * them as part of the transmit process. | |
767 | */ | |
768 | if (int_events & FEC_ENET_TXF) { | |
769 | ret = IRQ_HANDLED; | |
770 | fec_enet_tx(ndev); | |
771 | } | |
772 | ||
773 | if (int_events & FEC_ENET_MII) { | |
774 | ret = IRQ_HANDLED; | |
775 | complete(&fep->mdio_done); | |
776 | } | |
777 | } while (int_events); | |
778 | ||
779 | return ret; | |
780 | } | |
781 | ||
782 | ||
783 | ||
e6b043d5 | 784 | /* ------------------------------------------------------------------------- */ |
c556167f | 785 | static void __inline__ fec_get_mac(struct net_device *ndev) |
1da177e4 | 786 | { |
c556167f | 787 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 788 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 789 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 790 | |
49da97dc SG |
791 | /* |
792 | * try to get mac address in following order: | |
793 | * | |
794 | * 1) module parameter via kernel command line in form | |
795 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
796 | */ | |
797 | iap = macaddr; | |
798 | ||
ca2cc333 SG |
799 | #ifdef CONFIG_OF |
800 | /* | |
801 | * 2) from device tree data | |
802 | */ | |
803 | if (!is_valid_ether_addr(iap)) { | |
804 | struct device_node *np = fep->pdev->dev.of_node; | |
805 | if (np) { | |
806 | const char *mac = of_get_mac_address(np); | |
807 | if (mac) | |
808 | iap = (unsigned char *) mac; | |
809 | } | |
810 | } | |
811 | #endif | |
812 | ||
49da97dc | 813 | /* |
ca2cc333 | 814 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
815 | */ |
816 | if (!is_valid_ether_addr(iap)) { | |
817 | #ifdef CONFIG_M5272 | |
818 | if (FEC_FLASHMAC) | |
819 | iap = (unsigned char *)FEC_FLASHMAC; | |
820 | #else | |
821 | if (pdata) | |
822 | memcpy(iap, pdata->mac, ETH_ALEN); | |
823 | #endif | |
824 | } | |
825 | ||
826 | /* | |
ca2cc333 | 827 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
828 | */ |
829 | if (!is_valid_ether_addr(iap)) { | |
830 | *((unsigned long *) &tmpaddr[0]) = | |
831 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
832 | *((unsigned short *) &tmpaddr[4]) = | |
833 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 834 | iap = &tmpaddr[0]; |
1da177e4 LT |
835 | } |
836 | ||
c556167f | 837 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 838 | |
49da97dc SG |
839 | /* Adjust MAC if using macaddr */ |
840 | if (iap == macaddr) | |
43af940c | 841 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
842 | } |
843 | ||
e6b043d5 | 844 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 845 | |
e6b043d5 BW |
846 | /* |
847 | * Phy section | |
848 | */ | |
c556167f | 849 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 850 | { |
c556167f | 851 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 BW |
852 | struct phy_device *phy_dev = fep->phy_dev; |
853 | unsigned long flags; | |
1da177e4 | 854 | |
e6b043d5 | 855 | int status_change = 0; |
1da177e4 | 856 | |
e6b043d5 | 857 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 858 | |
e6b043d5 BW |
859 | /* Prevent a state halted on mii error */ |
860 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
861 | phy_dev->state = PHY_RESUMING; | |
862 | goto spin_unlock; | |
863 | } | |
1da177e4 | 864 | |
e6b043d5 BW |
865 | /* Duplex link change */ |
866 | if (phy_dev->link) { | |
867 | if (fep->full_duplex != phy_dev->duplex) { | |
c556167f | 868 | fec_restart(ndev, phy_dev->duplex); |
e6b043d5 BW |
869 | status_change = 1; |
870 | } | |
871 | } | |
1da177e4 | 872 | |
e6b043d5 BW |
873 | /* Link on or off change */ |
874 | if (phy_dev->link != fep->link) { | |
875 | fep->link = phy_dev->link; | |
876 | if (phy_dev->link) | |
c556167f | 877 | fec_restart(ndev, phy_dev->duplex); |
1da177e4 | 878 | else |
c556167f | 879 | fec_stop(ndev); |
e6b043d5 | 880 | status_change = 1; |
1da177e4 | 881 | } |
6aa20a22 | 882 | |
e6b043d5 BW |
883 | spin_unlock: |
884 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 885 | |
e6b043d5 BW |
886 | if (status_change) |
887 | phy_print_status(phy_dev); | |
888 | } | |
1da177e4 | 889 | |
e6b043d5 | 890 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 891 | { |
e6b043d5 | 892 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 893 | unsigned long time_left; |
1da177e4 | 894 | |
e6b043d5 | 895 | fep->mii_timeout = 0; |
97b72e43 | 896 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
897 | |
898 | /* start a read op */ | |
899 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
900 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
901 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
902 | ||
903 | /* wait for end of transfer */ | |
97b72e43 BS |
904 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
905 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
906 | if (time_left == 0) { | |
907 | fep->mii_timeout = 1; | |
908 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
909 | return -ETIMEDOUT; | |
1da177e4 | 910 | } |
1da177e4 | 911 | |
e6b043d5 BW |
912 | /* return value */ |
913 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 914 | } |
6aa20a22 | 915 | |
e6b043d5 BW |
916 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
917 | u16 value) | |
1da177e4 | 918 | { |
e6b043d5 | 919 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 920 | unsigned long time_left; |
1da177e4 | 921 | |
e6b043d5 | 922 | fep->mii_timeout = 0; |
97b72e43 | 923 | init_completion(&fep->mdio_done); |
1da177e4 | 924 | |
862f0982 SG |
925 | /* start a write op */ |
926 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
927 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
928 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
929 | fep->hwp + FEC_MII_DATA); | |
930 | ||
931 | /* wait for end of transfer */ | |
97b72e43 BS |
932 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
933 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
934 | if (time_left == 0) { | |
935 | fep->mii_timeout = 1; | |
936 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
937 | return -ETIMEDOUT; | |
e6b043d5 | 938 | } |
1da177e4 | 939 | |
e6b043d5 BW |
940 | return 0; |
941 | } | |
1da177e4 | 942 | |
e6b043d5 | 943 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 944 | { |
e6b043d5 | 945 | return 0; |
1da177e4 LT |
946 | } |
947 | ||
c556167f | 948 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 949 | { |
c556167f | 950 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
951 | const struct platform_device_id *id_entry = |
952 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 953 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
954 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
955 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
956 | int phy_id; | |
43af940c | 957 | int dev_id = fep->dev_id; |
562d2f8c | 958 | |
418bd0d4 BW |
959 | fep->phy_dev = NULL; |
960 | ||
6fcc040f GU |
961 | /* check for attached phy */ |
962 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
963 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
964 | continue; | |
965 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
966 | continue; | |
967 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
968 | continue; | |
b5680e0b SG |
969 | if (dev_id--) |
970 | continue; | |
6fcc040f GU |
971 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
972 | break; | |
e6b043d5 | 973 | } |
1da177e4 | 974 | |
6fcc040f GU |
975 | if (phy_id >= PHY_MAX_ADDR) { |
976 | printk(KERN_INFO "%s: no PHY, assuming direct connection " | |
c556167f | 977 | "to switch\n", ndev->name); |
6fcc040f GU |
978 | strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); |
979 | phy_id = 0; | |
980 | } | |
981 | ||
982 | snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); | |
c556167f | 983 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0, |
230dec61 | 984 | fep->phy_interface); |
6fcc040f | 985 | if (IS_ERR(phy_dev)) { |
c556167f | 986 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); |
6fcc040f | 987 | return PTR_ERR(phy_dev); |
e6b043d5 | 988 | } |
1da177e4 | 989 | |
e6b043d5 | 990 | /* mask with MAC supported features */ |
230dec61 SG |
991 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) |
992 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
993 | else | |
994 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
995 | ||
e6b043d5 | 996 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 997 | |
e6b043d5 BW |
998 | fep->phy_dev = phy_dev; |
999 | fep->link = 0; | |
1000 | fep->full_duplex = 0; | |
1da177e4 | 1001 | |
418bd0d4 | 1002 | printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] " |
c556167f | 1003 | "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name, |
418bd0d4 BW |
1004 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
1005 | fep->phy_dev->irq); | |
1006 | ||
e6b043d5 | 1007 | return 0; |
1da177e4 LT |
1008 | } |
1009 | ||
e6b043d5 | 1010 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1011 | { |
b5680e0b | 1012 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1013 | struct net_device *ndev = platform_get_drvdata(pdev); |
1014 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1015 | const struct platform_device_id *id_entry = |
1016 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1017 | int err = -ENXIO, i; |
6b265293 | 1018 | |
b5680e0b SG |
1019 | /* |
1020 | * The dual fec interfaces are not equivalent with enet-mac. | |
1021 | * Here are the differences: | |
1022 | * | |
1023 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1024 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1025 | * - external phys can only be configured by fec0 | |
1026 | * | |
1027 | * That is to say fec1 can not work independently. It only works | |
1028 | * when fec0 is working. The reason behind this design is that the | |
1029 | * second interface is added primarily for Switch mode. | |
1030 | * | |
1031 | * Because of the last point above, both phys are attached on fec0 | |
1032 | * mdio interface in board design, and need to be configured by | |
1033 | * fec0 mii_bus. | |
1034 | */ | |
43af940c | 1035 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b SG |
1036 | /* fec1 uses fec0 mii_bus */ |
1037 | fep->mii_bus = fec0_mii_bus; | |
1038 | return 0; | |
1039 | } | |
1040 | ||
e6b043d5 | 1041 | fep->mii_timeout = 0; |
1da177e4 | 1042 | |
e6b043d5 BW |
1043 | /* |
1044 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1045 | * |
1046 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1047 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1048 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1049 | * document. | |
e6b043d5 | 1050 | */ |
230dec61 SG |
1051 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000); |
1052 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1053 | fep->phy_speed--; | |
1054 | fep->phy_speed <<= 1; | |
e6b043d5 | 1055 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1056 | |
e6b043d5 BW |
1057 | fep->mii_bus = mdiobus_alloc(); |
1058 | if (fep->mii_bus == NULL) { | |
1059 | err = -ENOMEM; | |
1060 | goto err_out; | |
1da177e4 LT |
1061 | } |
1062 | ||
e6b043d5 BW |
1063 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1064 | fep->mii_bus->read = fec_enet_mdio_read; | |
1065 | fep->mii_bus->write = fec_enet_mdio_write; | |
1066 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
43af940c | 1067 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", fep->dev_id + 1); |
e6b043d5 BW |
1068 | fep->mii_bus->priv = fep; |
1069 | fep->mii_bus->parent = &pdev->dev; | |
1070 | ||
1071 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1072 | if (!fep->mii_bus->irq) { | |
1073 | err = -ENOMEM; | |
1074 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1075 | } |
1076 | ||
e6b043d5 BW |
1077 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1078 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1079 | |
e6b043d5 BW |
1080 | if (mdiobus_register(fep->mii_bus)) |
1081 | goto err_out_free_mdio_irq; | |
1da177e4 | 1082 | |
b5680e0b SG |
1083 | /* save fec0 mii_bus */ |
1084 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1085 | fec0_mii_bus = fep->mii_bus; | |
1086 | ||
e6b043d5 | 1087 | return 0; |
1da177e4 | 1088 | |
e6b043d5 BW |
1089 | err_out_free_mdio_irq: |
1090 | kfree(fep->mii_bus->irq); | |
1091 | err_out_free_mdiobus: | |
1092 | mdiobus_free(fep->mii_bus); | |
1093 | err_out: | |
1094 | return err; | |
1da177e4 LT |
1095 | } |
1096 | ||
e6b043d5 | 1097 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1098 | { |
e6b043d5 BW |
1099 | if (fep->phy_dev) |
1100 | phy_disconnect(fep->phy_dev); | |
1101 | mdiobus_unregister(fep->mii_bus); | |
1102 | kfree(fep->mii_bus->irq); | |
1103 | mdiobus_free(fep->mii_bus); | |
1da177e4 LT |
1104 | } |
1105 | ||
c556167f | 1106 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1107 | struct ethtool_cmd *cmd) |
1da177e4 | 1108 | { |
c556167f | 1109 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1110 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1111 | |
e6b043d5 BW |
1112 | if (!phydev) |
1113 | return -ENODEV; | |
1da177e4 | 1114 | |
e6b043d5 | 1115 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1116 | } |
1117 | ||
c556167f | 1118 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1119 | struct ethtool_cmd *cmd) |
1da177e4 | 1120 | { |
c556167f | 1121 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1122 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1123 | |
e6b043d5 BW |
1124 | if (!phydev) |
1125 | return -ENODEV; | |
1da177e4 | 1126 | |
e6b043d5 | 1127 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1128 | } |
1129 | ||
c556167f | 1130 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1131 | struct ethtool_drvinfo *info) |
1da177e4 | 1132 | { |
c556167f | 1133 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1134 | |
e6b043d5 BW |
1135 | strcpy(info->driver, fep->pdev->dev.driver->name); |
1136 | strcpy(info->version, "Revision: 1.0"); | |
c556167f | 1137 | strcpy(info->bus_info, dev_name(&ndev->dev)); |
1da177e4 LT |
1138 | } |
1139 | ||
e6b043d5 BW |
1140 | static struct ethtool_ops fec_enet_ethtool_ops = { |
1141 | .get_settings = fec_enet_get_settings, | |
1142 | .set_settings = fec_enet_set_settings, | |
1143 | .get_drvinfo = fec_enet_get_drvinfo, | |
1144 | .get_link = ethtool_op_get_link, | |
1145 | }; | |
1da177e4 | 1146 | |
c556167f | 1147 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1148 | { |
c556167f | 1149 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1150 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1151 | |
c556167f | 1152 | if (!netif_running(ndev)) |
e6b043d5 | 1153 | return -EINVAL; |
1da177e4 | 1154 | |
e6b043d5 BW |
1155 | if (!phydev) |
1156 | return -ENODEV; | |
1157 | ||
28b04113 | 1158 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1159 | } |
1160 | ||
c556167f | 1161 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1162 | { |
c556167f | 1163 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1164 | int i; |
1165 | struct sk_buff *skb; | |
1166 | struct bufdesc *bdp; | |
1167 | ||
1168 | bdp = fep->rx_bd_base; | |
1169 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1170 | skb = fep->rx_skbuff[i]; | |
1171 | ||
1172 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1173 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1174 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1175 | if (skb) | |
1176 | dev_kfree_skb(skb); | |
1177 | bdp++; | |
1178 | } | |
1179 | ||
1180 | bdp = fep->tx_bd_base; | |
1181 | for (i = 0; i < TX_RING_SIZE; i++) | |
1182 | kfree(fep->tx_bounce[i]); | |
1183 | } | |
1184 | ||
c556167f | 1185 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1186 | { |
c556167f | 1187 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea SH |
1188 | int i; |
1189 | struct sk_buff *skb; | |
1190 | struct bufdesc *bdp; | |
1191 | ||
1192 | bdp = fep->rx_bd_base; | |
1193 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1194 | skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); | |
1195 | if (!skb) { | |
c556167f | 1196 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1197 | return -ENOMEM; |
1198 | } | |
1199 | fep->rx_skbuff[i] = skb; | |
1200 | ||
d1ab1f54 | 1201 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1202 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1203 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
1204 | bdp++; | |
1205 | } | |
1206 | ||
1207 | /* Set the last buffer to wrap. */ | |
1208 | bdp--; | |
1209 | bdp->cbd_sc |= BD_SC_WRAP; | |
1210 | ||
1211 | bdp = fep->tx_bd_base; | |
1212 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1213 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1214 | ||
1215 | bdp->cbd_sc = 0; | |
1216 | bdp->cbd_bufaddr = 0; | |
1217 | bdp++; | |
1218 | } | |
1219 | ||
1220 | /* Set the last buffer to wrap. */ | |
1221 | bdp--; | |
1222 | bdp->cbd_sc |= BD_SC_WRAP; | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
1da177e4 | 1227 | static int |
c556167f | 1228 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1229 | { |
c556167f | 1230 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1231 | int ret; |
1da177e4 LT |
1232 | |
1233 | /* I should reset the ring buffers here, but I don't yet know | |
1234 | * a simple way to do that. | |
1235 | */ | |
1da177e4 | 1236 | |
c556167f | 1237 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1238 | if (ret) |
1239 | return ret; | |
1240 | ||
418bd0d4 | 1241 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1242 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1243 | if (ret) { |
c556167f | 1244 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1245 | return ret; |
1246 | } | |
e6b043d5 | 1247 | phy_start(fep->phy_dev); |
c556167f | 1248 | netif_start_queue(ndev); |
1da177e4 | 1249 | fep->opened = 1; |
22f6b860 | 1250 | return 0; |
1da177e4 LT |
1251 | } |
1252 | ||
1253 | static int | |
c556167f | 1254 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1255 | { |
c556167f | 1256 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1257 | |
22f6b860 | 1258 | /* Don't know what to do yet. */ |
1da177e4 | 1259 | fep->opened = 0; |
c556167f UKK |
1260 | netif_stop_queue(ndev); |
1261 | fec_stop(ndev); | |
1da177e4 | 1262 | |
e497ba82 UKK |
1263 | if (fep->phy_dev) { |
1264 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1265 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1266 | } |
418bd0d4 | 1267 | |
db8880bc | 1268 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1269 | |
1da177e4 LT |
1270 | return 0; |
1271 | } | |
1272 | ||
1da177e4 LT |
1273 | /* Set or clear the multicast filter for this adaptor. |
1274 | * Skeleton taken from sunlance driver. | |
1275 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1276 | * MAC address filtering. Some of the drivers check to make sure it is | |
1277 | * a group multicast address, and discard those that are not. I guess I | |
1278 | * will do the same for now, but just remove the test if you want | |
1279 | * individual filtering as well (do the upper net layers want or support | |
1280 | * this kind of feature?). | |
1281 | */ | |
1282 | ||
1283 | #define HASH_BITS 6 /* #bits in hash */ | |
1284 | #define CRC32_POLY 0xEDB88320 | |
1285 | ||
c556167f | 1286 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1287 | { |
c556167f | 1288 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1289 | struct netdev_hw_addr *ha; |
48e2f183 | 1290 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1291 | unsigned char hash; |
1292 | ||
c556167f | 1293 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1294 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1295 | tmp |= 0x8; | |
1296 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1297 | return; |
1298 | } | |
1da177e4 | 1299 | |
4e831836 SH |
1300 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1301 | tmp &= ~0x8; | |
1302 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1303 | ||
c556167f | 1304 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1305 | /* Catch all multicast addresses, so set the |
1306 | * filter to all 1's | |
1307 | */ | |
1308 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1309 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1310 | ||
1311 | return; | |
1312 | } | |
1313 | ||
1314 | /* Clear filter and add the addresses in hash register | |
1315 | */ | |
1316 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1317 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1318 | ||
c556167f | 1319 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1320 | /* calculate crc32 value of mac address */ |
1321 | crc = 0xffffffff; | |
1322 | ||
c556167f | 1323 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1324 | data = ha->addr[i]; |
4e831836 SH |
1325 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1326 | crc = (crc >> 1) ^ | |
1327 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1328 | } |
1329 | } | |
4e831836 SH |
1330 | |
1331 | /* only upper 6 bits (HASH_BITS) are used | |
1332 | * which point to specific bit in he hash registers | |
1333 | */ | |
1334 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1335 | ||
1336 | if (hash > 31) { | |
1337 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1338 | tmp |= 1 << (hash - 32); | |
1339 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1340 | } else { | |
1341 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1342 | tmp |= 1 << hash; | |
1343 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1344 | } | |
1da177e4 LT |
1345 | } |
1346 | } | |
1347 | ||
22f6b860 | 1348 | /* Set a MAC change in hardware. */ |
009fda83 | 1349 | static int |
c556167f | 1350 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1351 | { |
c556167f | 1352 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1353 | struct sockaddr *addr = p; |
1354 | ||
1355 | if (!is_valid_ether_addr(addr->sa_data)) | |
1356 | return -EADDRNOTAVAIL; | |
1357 | ||
c556167f | 1358 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1359 | |
c556167f UKK |
1360 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1361 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1362 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1363 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1364 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1365 | return 0; |
1da177e4 LT |
1366 | } |
1367 | ||
7f5c6add XJ |
1368 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1369 | /* | |
1370 | * fec_poll_controller: FEC Poll controller function | |
1371 | * @dev: The FEC network adapter | |
1372 | * | |
1373 | * Polled functionality used by netconsole and others in non interrupt mode | |
1374 | * | |
1375 | */ | |
1376 | void fec_poll_controller(struct net_device *dev) | |
1377 | { | |
1378 | int i; | |
1379 | struct fec_enet_private *fep = netdev_priv(dev); | |
1380 | ||
1381 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1382 | if (fep->irq[i] > 0) { | |
1383 | disable_irq(fep->irq[i]); | |
1384 | fec_enet_interrupt(fep->irq[i], dev); | |
1385 | enable_irq(fep->irq[i]); | |
1386 | } | |
1387 | } | |
1388 | } | |
1389 | #endif | |
1390 | ||
009fda83 SH |
1391 | static const struct net_device_ops fec_netdev_ops = { |
1392 | .ndo_open = fec_enet_open, | |
1393 | .ndo_stop = fec_enet_close, | |
1394 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1395 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1396 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1397 | .ndo_validate_addr = eth_validate_addr, |
1398 | .ndo_tx_timeout = fec_timeout, | |
1399 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1400 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1401 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1402 | .ndo_poll_controller = fec_poll_controller, | |
1403 | #endif | |
009fda83 SH |
1404 | }; |
1405 | ||
1da177e4 LT |
1406 | /* |
1407 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1408 | * |
1da177e4 | 1409 | */ |
c556167f | 1410 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1411 | { |
c556167f | 1412 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1413 | struct bufdesc *cbd_base; |
633e7533 | 1414 | struct bufdesc *bdp; |
f0b3fbea | 1415 | int i; |
1da177e4 | 1416 | |
8d4dd5cf SH |
1417 | /* Allocate memory for buffer descriptors. */ |
1418 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1419 | GFP_KERNEL); | |
1420 | if (!cbd_base) { | |
562d2f8c GU |
1421 | printk("FEC: allocate descriptor memory failed?\n"); |
1422 | return -ENOMEM; | |
1423 | } | |
1424 | ||
3b2b74ca | 1425 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1426 | |
c556167f | 1427 | fep->netdev = ndev; |
1da177e4 | 1428 | |
49da97dc | 1429 | /* Get the Ethernet address */ |
c556167f | 1430 | fec_get_mac(ndev); |
1da177e4 | 1431 | |
8d4dd5cf | 1432 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1433 | fep->rx_bd_base = cbd_base; |
1434 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1435 | ||
22f6b860 | 1436 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1437 | ndev->watchdog_timeo = TX_TIMEOUT; |
1438 | ndev->netdev_ops = &fec_netdev_ops; | |
1439 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 RH |
1440 | |
1441 | /* Initialize the receive buffer descriptors. */ | |
1442 | bdp = fep->rx_bd_base; | |
1443 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1444 | ||
1445 | /* Initialize the BD for every fragment in the page. */ | |
1446 | bdp->cbd_sc = 0; | |
1447 | bdp++; | |
1448 | } | |
1449 | ||
1450 | /* Set the last buffer to wrap */ | |
1451 | bdp--; | |
1452 | bdp->cbd_sc |= BD_SC_WRAP; | |
1453 | ||
1454 | /* ...and the same for transmit */ | |
1455 | bdp = fep->tx_bd_base; | |
1456 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1457 | ||
1458 | /* Initialize the BD for every fragment in the page. */ | |
1459 | bdp->cbd_sc = 0; | |
1460 | bdp->cbd_bufaddr = 0; | |
1461 | bdp++; | |
1462 | } | |
1463 | ||
1464 | /* Set the last buffer to wrap */ | |
1465 | bdp--; | |
1466 | bdp->cbd_sc |= BD_SC_WRAP; | |
1467 | ||
c556167f | 1468 | fec_restart(ndev, 0); |
1da177e4 | 1469 | |
1da177e4 LT |
1470 | return 0; |
1471 | } | |
1472 | ||
ca2cc333 SG |
1473 | #ifdef CONFIG_OF |
1474 | static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev) | |
1475 | { | |
1476 | struct device_node *np = pdev->dev.of_node; | |
1477 | ||
1478 | if (np) | |
1479 | return of_get_phy_mode(np); | |
1480 | ||
1481 | return -ENODEV; | |
1482 | } | |
1483 | ||
a9b2c8ef | 1484 | static void __devinit fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1485 | { |
1486 | int err, phy_reset; | |
1487 | struct device_node *np = pdev->dev.of_node; | |
1488 | ||
1489 | if (!np) | |
a9b2c8ef | 1490 | return; |
ca2cc333 SG |
1491 | |
1492 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); | |
1493 | err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset"); | |
1494 | if (err) { | |
a9b2c8ef SG |
1495 | pr_debug("FEC: failed to get gpio phy-reset: %d\n", err); |
1496 | return; | |
ca2cc333 SG |
1497 | } |
1498 | msleep(1); | |
1499 | gpio_set_value(phy_reset, 1); | |
ca2cc333 SG |
1500 | } |
1501 | #else /* CONFIG_OF */ | |
1502 | static inline int fec_get_phy_mode_dt(struct platform_device *pdev) | |
1503 | { | |
1504 | return -ENODEV; | |
1505 | } | |
1506 | ||
a9b2c8ef | 1507 | static inline void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1508 | { |
1509 | /* | |
1510 | * In case of platform probe, the reset has been done | |
1511 | * by machine code. | |
1512 | */ | |
ca2cc333 SG |
1513 | } |
1514 | #endif /* CONFIG_OF */ | |
1515 | ||
ead73183 SH |
1516 | static int __devinit |
1517 | fec_probe(struct platform_device *pdev) | |
1518 | { | |
1519 | struct fec_enet_private *fep; | |
5eb32bd0 | 1520 | struct fec_platform_data *pdata; |
ead73183 SH |
1521 | struct net_device *ndev; |
1522 | int i, irq, ret = 0; | |
1523 | struct resource *r; | |
ca2cc333 | 1524 | const struct of_device_id *of_id; |
43af940c | 1525 | static int dev_id; |
ca2cc333 SG |
1526 | |
1527 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
1528 | if (of_id) | |
1529 | pdev->id_entry = of_id->data; | |
ead73183 SH |
1530 | |
1531 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1532 | if (!r) | |
1533 | return -ENXIO; | |
1534 | ||
1535 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1536 | if (!r) | |
1537 | return -EBUSY; | |
1538 | ||
1539 | /* Init network device */ | |
1540 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
28e2188e UKK |
1541 | if (!ndev) { |
1542 | ret = -ENOMEM; | |
1543 | goto failed_alloc_etherdev; | |
1544 | } | |
ead73183 SH |
1545 | |
1546 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1547 | ||
1548 | /* setup board info structure */ | |
1549 | fep = netdev_priv(ndev); | |
ead73183 | 1550 | |
24e531b4 | 1551 | fep->hwp = ioremap(r->start, resource_size(r)); |
e6b043d5 | 1552 | fep->pdev = pdev; |
43af940c | 1553 | fep->dev_id = dev_id++; |
ead73183 | 1554 | |
24e531b4 | 1555 | if (!fep->hwp) { |
ead73183 SH |
1556 | ret = -ENOMEM; |
1557 | goto failed_ioremap; | |
1558 | } | |
1559 | ||
1560 | platform_set_drvdata(pdev, ndev); | |
1561 | ||
ca2cc333 SG |
1562 | ret = fec_get_phy_mode_dt(pdev); |
1563 | if (ret < 0) { | |
1564 | pdata = pdev->dev.platform_data; | |
1565 | if (pdata) | |
1566 | fep->phy_interface = pdata->phy; | |
1567 | else | |
1568 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
1569 | } else { | |
1570 | fep->phy_interface = ret; | |
1571 | } | |
1572 | ||
1573 | fec_reset_phy(pdev); | |
5eb32bd0 | 1574 | |
c7c83d1c | 1575 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
ead73183 SH |
1576 | irq = platform_get_irq(pdev, i); |
1577 | if (i && irq < 0) | |
1578 | break; | |
1579 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1580 | if (ret) { | |
b2b09ad6 | 1581 | while (--i >= 0) { |
ead73183 SH |
1582 | irq = platform_get_irq(pdev, i); |
1583 | free_irq(irq, ndev); | |
ead73183 SH |
1584 | } |
1585 | goto failed_irq; | |
1586 | } | |
1587 | } | |
1588 | ||
1589 | fep->clk = clk_get(&pdev->dev, "fec_clk"); | |
1590 | if (IS_ERR(fep->clk)) { | |
1591 | ret = PTR_ERR(fep->clk); | |
1592 | goto failed_clk; | |
1593 | } | |
1594 | clk_enable(fep->clk); | |
1595 | ||
8649a230 | 1596 | ret = fec_enet_init(ndev); |
ead73183 SH |
1597 | if (ret) |
1598 | goto failed_init; | |
1599 | ||
e6b043d5 BW |
1600 | ret = fec_enet_mii_init(pdev); |
1601 | if (ret) | |
1602 | goto failed_mii_init; | |
1603 | ||
03c698c9 OS |
1604 | /* Carrier starts down, phylib will bring it up */ |
1605 | netif_carrier_off(ndev); | |
1606 | ||
ead73183 SH |
1607 | ret = register_netdev(ndev); |
1608 | if (ret) | |
1609 | goto failed_register; | |
1610 | ||
1611 | return 0; | |
1612 | ||
1613 | failed_register: | |
e6b043d5 BW |
1614 | fec_enet_mii_remove(fep); |
1615 | failed_mii_init: | |
ead73183 SH |
1616 | failed_init: |
1617 | clk_disable(fep->clk); | |
1618 | clk_put(fep->clk); | |
1619 | failed_clk: | |
c7c83d1c | 1620 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
ead73183 SH |
1621 | irq = platform_get_irq(pdev, i); |
1622 | if (irq > 0) | |
1623 | free_irq(irq, ndev); | |
1624 | } | |
1625 | failed_irq: | |
24e531b4 | 1626 | iounmap(fep->hwp); |
ead73183 SH |
1627 | failed_ioremap: |
1628 | free_netdev(ndev); | |
28e2188e UKK |
1629 | failed_alloc_etherdev: |
1630 | release_mem_region(r->start, resource_size(r)); | |
ead73183 SH |
1631 | |
1632 | return ret; | |
1633 | } | |
1634 | ||
1635 | static int __devexit | |
1636 | fec_drv_remove(struct platform_device *pdev) | |
1637 | { | |
1638 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1639 | struct fec_enet_private *fep = netdev_priv(ndev); | |
28e2188e | 1640 | struct resource *r; |
ead73183 | 1641 | |
ead73183 | 1642 | fec_stop(ndev); |
e6b043d5 | 1643 | fec_enet_mii_remove(fep); |
ead73183 SH |
1644 | clk_disable(fep->clk); |
1645 | clk_put(fep->clk); | |
24e531b4 | 1646 | iounmap(fep->hwp); |
ead73183 SH |
1647 | unregister_netdev(ndev); |
1648 | free_netdev(ndev); | |
28e2188e UKK |
1649 | |
1650 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1651 | BUG_ON(!r); | |
1652 | release_mem_region(r->start, resource_size(r)); | |
1653 | ||
b3cde36c UKK |
1654 | platform_set_drvdata(pdev, NULL); |
1655 | ||
ead73183 SH |
1656 | return 0; |
1657 | } | |
1658 | ||
59d4289b | 1659 | #ifdef CONFIG_PM |
ead73183 | 1660 | static int |
87cad5c3 | 1661 | fec_suspend(struct device *dev) |
ead73183 | 1662 | { |
87cad5c3 | 1663 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1664 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1665 | |
04e5216d UKK |
1666 | if (netif_running(ndev)) { |
1667 | fec_stop(ndev); | |
1668 | netif_device_detach(ndev); | |
ead73183 | 1669 | } |
04e5216d UKK |
1670 | clk_disable(fep->clk); |
1671 | ||
ead73183 SH |
1672 | return 0; |
1673 | } | |
1674 | ||
1675 | static int | |
87cad5c3 | 1676 | fec_resume(struct device *dev) |
ead73183 | 1677 | { |
87cad5c3 | 1678 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1679 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1680 | |
04e5216d UKK |
1681 | clk_enable(fep->clk); |
1682 | if (netif_running(ndev)) { | |
1683 | fec_restart(ndev, fep->full_duplex); | |
1684 | netif_device_attach(ndev); | |
ead73183 | 1685 | } |
04e5216d | 1686 | |
ead73183 SH |
1687 | return 0; |
1688 | } | |
1689 | ||
59d4289b DK |
1690 | static const struct dev_pm_ops fec_pm_ops = { |
1691 | .suspend = fec_suspend, | |
1692 | .resume = fec_resume, | |
1693 | .freeze = fec_suspend, | |
1694 | .thaw = fec_resume, | |
1695 | .poweroff = fec_suspend, | |
1696 | .restore = fec_resume, | |
1697 | }; | |
87cad5c3 | 1698 | #endif |
59d4289b | 1699 | |
ead73183 SH |
1700 | static struct platform_driver fec_driver = { |
1701 | .driver = { | |
b5680e0b | 1702 | .name = DRIVER_NAME, |
87cad5c3 EB |
1703 | .owner = THIS_MODULE, |
1704 | #ifdef CONFIG_PM | |
1705 | .pm = &fec_pm_ops, | |
1706 | #endif | |
ca2cc333 | 1707 | .of_match_table = fec_dt_ids, |
ead73183 | 1708 | }, |
b5680e0b | 1709 | .id_table = fec_devtype, |
87cad5c3 EB |
1710 | .probe = fec_probe, |
1711 | .remove = __devexit_p(fec_drv_remove), | |
ead73183 SH |
1712 | }; |
1713 | ||
1714 | static int __init | |
1715 | fec_enet_module_init(void) | |
1716 | { | |
1717 | printk(KERN_INFO "FEC Ethernet Driver\n"); | |
1718 | ||
1719 | return platform_driver_register(&fec_driver); | |
1720 | } | |
1721 | ||
1722 | static void __exit | |
1723 | fec_enet_cleanup(void) | |
1724 | { | |
1725 | platform_driver_unregister(&fec_driver); | |
1726 | } | |
1727 | ||
1728 | module_exit(fec_enet_cleanup); | |
1da177e4 LT |
1729 | module_init(fec_enet_module_init); |
1730 | ||
1731 | MODULE_LICENSE("GPL"); |