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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
1da177e4 LT |
32 | #include <linux/init.h> |
33 | #include <linux/delay.h> | |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/spinlock.h> | |
38 | #include <linux/workqueue.h> | |
39 | #include <linux/bitops.h> | |
6f501b17 SH |
40 | #include <linux/io.h> |
41 | #include <linux/irq.h> | |
196719ec | 42 | #include <linux/clk.h> |
ead73183 | 43 | #include <linux/platform_device.h> |
e6b043d5 | 44 | #include <linux/phy.h> |
5eb32bd0 | 45 | #include <linux/fec.h> |
ca2cc333 SG |
46 | #include <linux/of.h> |
47 | #include <linux/of_device.h> | |
48 | #include <linux/of_gpio.h> | |
49 | #include <linux/of_net.h> | |
b2bccee1 | 50 | #include <linux/pinctrl/consumer.h> |
5fa9c0fe | 51 | #include <linux/regulator/consumer.h> |
1da177e4 | 52 | |
080853af | 53 | #include <asm/cacheflush.h> |
196719ec | 54 | |
b5680e0b | 55 | #ifndef CONFIG_ARM |
1da177e4 LT |
56 | #include <asm/coldfire.h> |
57 | #include <asm/mcfsim.h> | |
196719ec | 58 | #endif |
6f501b17 | 59 | |
1da177e4 | 60 | #include "fec.h" |
1da177e4 | 61 | |
085e79ed | 62 | #if defined(CONFIG_ARM) |
196719ec SH |
63 | #define FEC_ALIGNMENT 0xf |
64 | #else | |
65 | #define FEC_ALIGNMENT 0x3 | |
66 | #endif | |
67 | ||
b5680e0b | 68 | #define DRIVER_NAME "fec" |
dc975382 | 69 | #define FEC_NAPI_WEIGHT 64 |
b5680e0b | 70 | |
baa70a5c FL |
71 | /* Pause frame feild and FIFO threshold */ |
72 | #define FEC_ENET_FCE (1 << 5) | |
73 | #define FEC_ENET_RSEM_V 0x84 | |
74 | #define FEC_ENET_RSFL_V 16 | |
75 | #define FEC_ENET_RAEM_V 0x8 | |
76 | #define FEC_ENET_RAFL_V 0x8 | |
77 | #define FEC_ENET_OPD_V 0xFFF0 | |
78 | ||
b5680e0b SG |
79 | /* Controller is ENET-MAC */ |
80 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
81 | /* Controller needs driver to swap frame */ | |
82 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
83 | /* Controller uses gasket */ |
84 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
85 | /* Controller has GBIT support */ |
86 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
ff43da86 FL |
87 | /* Controller has extend desc buffer */ |
88 | #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) | |
b5680e0b SG |
89 | |
90 | static struct platform_device_id fec_devtype[] = { | |
91 | { | |
0ca1e290 | 92 | /* keep it for coldfire */ |
b5680e0b SG |
93 | .name = DRIVER_NAME, |
94 | .driver_data = 0, | |
0ca1e290 SG |
95 | }, { |
96 | .name = "imx25-fec", | |
97 | .driver_data = FEC_QUIRK_USE_GASKET, | |
98 | }, { | |
99 | .name = "imx27-fec", | |
100 | .driver_data = 0, | |
b5680e0b SG |
101 | }, { |
102 | .name = "imx28-fec", | |
103 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
104 | }, { |
105 | .name = "imx6q-fec", | |
ff43da86 FL |
106 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
107 | FEC_QUIRK_HAS_BUFDESC_EX, | |
0ca1e290 SG |
108 | }, { |
109 | /* sentinel */ | |
110 | } | |
b5680e0b | 111 | }; |
0ca1e290 | 112 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 113 | |
ca2cc333 | 114 | enum imx_fec_type { |
a7dd3219 | 115 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
116 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
117 | IMX28_FEC, | |
230dec61 | 118 | IMX6Q_FEC, |
ca2cc333 SG |
119 | }; |
120 | ||
121 | static const struct of_device_id fec_dt_ids[] = { | |
122 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
123 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
124 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 125 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
ca2cc333 SG |
126 | { /* sentinel */ } |
127 | }; | |
128 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
129 | ||
49da97dc SG |
130 | static unsigned char macaddr[ETH_ALEN]; |
131 | module_param_array(macaddr, byte, NULL, 0); | |
132 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 133 | |
49da97dc | 134 | #if defined(CONFIG_M5272) |
1da177e4 LT |
135 | /* |
136 | * Some hardware gets it MAC address out of local flash memory. | |
137 | * if this is non-zero then assume it is the address to get MAC from. | |
138 | */ | |
139 | #if defined(CONFIG_NETtel) | |
140 | #define FEC_FLASHMAC 0xf0006006 | |
141 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
142 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
143 | #elif defined(CONFIG_CANCam) |
144 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
145 | #elif defined (CONFIG_M5272C3) |
146 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
147 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 148 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
149 | #else |
150 | #define FEC_FLASHMAC 0 | |
151 | #endif | |
43be6366 | 152 | #endif /* CONFIG_M5272 */ |
ead73183 | 153 | |
ff43da86 | 154 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) |
6b265293 | 155 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
156 | #endif |
157 | ||
22f6b860 | 158 | /* Interrupt events/masks. */ |
1da177e4 LT |
159 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
160 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
161 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
162 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
163 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
164 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
165 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
166 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
167 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
168 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
169 | ||
4bee1f9a | 170 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
dc975382 | 171 | #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) |
4bee1f9a | 172 | |
1da177e4 LT |
173 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
174 | */ | |
175 | #define PKT_MAXBUF_SIZE 1518 | |
176 | #define PKT_MINBUF_SIZE 64 | |
177 | #define PKT_MAXBLR_SIZE 1520 | |
178 | ||
1da177e4 | 179 | /* |
6b265293 | 180 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
181 | * size bits. Other FEC hardware does not, so we need to take that into |
182 | * account when setting it. | |
183 | */ | |
562d2f8c | 184 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 185 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
186 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
187 | #else | |
188 | #define OPT_FRAME_SIZE 0 | |
189 | #endif | |
190 | ||
e6b043d5 BW |
191 | /* FEC MII MMFR bits definition */ |
192 | #define FEC_MMFR_ST (1 << 30) | |
193 | #define FEC_MMFR_OP_READ (2 << 28) | |
194 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
195 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
196 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
197 | #define FEC_MMFR_TA (2 << 16) | |
198 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 199 | |
c3b084c2 | 200 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 201 | |
22f6b860 SH |
202 | /* Transmitter timeout */ |
203 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 204 | |
baa70a5c FL |
205 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
206 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
207 | ||
e163cc97 LW |
208 | static int mii_cnt; |
209 | ||
ff43da86 FL |
210 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) |
211 | { | |
212 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
213 | if (is_ex) | |
214 | return (struct bufdesc *)(ex + 1); | |
215 | else | |
216 | return bdp + 1; | |
217 | } | |
218 | ||
219 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) | |
220 | { | |
221 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
222 | if (is_ex) | |
223 | return (struct bufdesc *)(ex - 1); | |
224 | else | |
225 | return bdp - 1; | |
226 | } | |
227 | ||
b5680e0b SG |
228 | static void *swap_buffer(void *bufaddr, int len) |
229 | { | |
230 | int i; | |
231 | unsigned int *buf = bufaddr; | |
232 | ||
233 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
234 | *buf = cpu_to_be32(*buf); | |
235 | ||
236 | return bufaddr; | |
237 | } | |
238 | ||
c7621cb3 | 239 | static netdev_tx_t |
c556167f | 240 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 241 | { |
c556167f | 242 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
243 | const struct platform_device_id *id_entry = |
244 | platform_get_device_id(fep->pdev); | |
2e28532f | 245 | struct bufdesc *bdp; |
9555b31e | 246 | void *bufaddr; |
0e702ab3 | 247 | unsigned short status; |
de5fb0a0 | 248 | unsigned int index; |
1da177e4 | 249 | |
1da177e4 LT |
250 | if (!fep->link) { |
251 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 252 | return NETDEV_TX_BUSY; |
1da177e4 LT |
253 | } |
254 | ||
255 | /* Fill in a Tx ring entry */ | |
256 | bdp = fep->cur_tx; | |
257 | ||
0e702ab3 | 258 | status = bdp->cbd_sc; |
22f6b860 | 259 | |
0e702ab3 | 260 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 261 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 262 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 263 | */ |
c556167f | 264 | printk("%s: tx queue full!.\n", ndev->name); |
5b548140 | 265 | return NETDEV_TX_BUSY; |
1da177e4 | 266 | } |
1da177e4 | 267 | |
22f6b860 | 268 | /* Clear all of the status flags */ |
0e702ab3 | 269 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 270 | |
22f6b860 | 271 | /* Set buffer length and buffer pointer */ |
9555b31e | 272 | bufaddr = skb->data; |
1da177e4 LT |
273 | bdp->cbd_datlen = skb->len; |
274 | ||
275 | /* | |
22f6b860 SH |
276 | * On some FEC implementations data must be aligned on |
277 | * 4-byte boundaries. Use bounce buffers to copy data | |
278 | * and get it aligned. Ugh. | |
1da177e4 | 279 | */ |
de5fb0a0 FL |
280 | if (fep->bufdesc_ex) |
281 | index = (struct bufdesc_ex *)bdp - | |
282 | (struct bufdesc_ex *)fep->tx_bd_base; | |
283 | else | |
284 | index = bdp - fep->tx_bd_base; | |
285 | ||
9555b31e | 286 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
8a73b0bc | 287 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 288 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
289 | } |
290 | ||
b5680e0b SG |
291 | /* |
292 | * Some design made an incorrect assumption on endian mode of | |
293 | * the system that it's running on. As the result, driver has to | |
294 | * swap every frame going to and coming from the controller. | |
295 | */ | |
296 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
297 | swap_buffer(bufaddr, skb->len); | |
298 | ||
22f6b860 | 299 | /* Save skb pointer */ |
de5fb0a0 | 300 | fep->tx_skbuff[index] = skb; |
6aa20a22 | 301 | |
1da177e4 LT |
302 | /* Push the data cache so the CPM does not get stale memory |
303 | * data. | |
304 | */ | |
d1ab1f54 | 305 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 306 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 307 | |
0e702ab3 GU |
308 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
309 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 310 | */ |
0e702ab3 | 311 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 312 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 313 | bdp->cbd_sc = status; |
1da177e4 | 314 | |
ff43da86 FL |
315 | if (fep->bufdesc_ex) { |
316 | ||
317 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
318 | ebdp->cbd_bdu = 0; | |
319 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
6605b730 | 320 | fep->hwts_tx_en)) { |
ff43da86 | 321 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
6605b730 | 322 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
ff43da86 | 323 | } else { |
6605b730 | 324 | |
ff43da86 FL |
325 | ebdp->cbd_esc = BD_ENET_TX_INT; |
326 | } | |
6605b730 | 327 | } |
22f6b860 SH |
328 | /* If this was the last BD in the ring, start at the beginning again. */ |
329 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 330 | bdp = fep->tx_bd_base; |
22f6b860 | 331 | else |
ff43da86 | 332 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
1da177e4 | 333 | |
de5fb0a0 FL |
334 | fep->cur_tx = bdp; |
335 | ||
336 | if (fep->cur_tx == fep->dirty_tx) | |
c556167f | 337 | netif_stop_queue(ndev); |
1da177e4 | 338 | |
de5fb0a0 FL |
339 | /* Trigger transmission start */ |
340 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
1da177e4 | 341 | |
18a03b97 RC |
342 | skb_tx_timestamp(skb); |
343 | ||
6ed10654 | 344 | return NETDEV_TX_OK; |
1da177e4 LT |
345 | } |
346 | ||
45993653 UKK |
347 | /* This function is called to start or restart the FEC during a link |
348 | * change. This only happens when switching between half and full | |
349 | * duplex. | |
350 | */ | |
1da177e4 | 351 | static void |
45993653 | 352 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 353 | { |
c556167f | 354 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
355 | const struct platform_device_id *id_entry = |
356 | platform_get_device_id(fep->pdev); | |
357 | int i; | |
cd1f402c UKK |
358 | u32 temp_mac[2]; |
359 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 360 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 361 | |
45993653 UKK |
362 | /* Whack a reset. We should wait for this. */ |
363 | writel(1, fep->hwp + FEC_ECNTRL); | |
364 | udelay(10); | |
1da177e4 | 365 | |
45993653 UKK |
366 | /* |
367 | * enet-mac reset will reset mac address registers too, | |
368 | * so need to reconfigure it. | |
369 | */ | |
370 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
371 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
372 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
373 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
374 | } | |
1da177e4 | 375 | |
45993653 UKK |
376 | /* Clear any outstanding interrupt. */ |
377 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 378 | |
45993653 UKK |
379 | /* Reset all multicast. */ |
380 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
381 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
382 | #ifndef CONFIG_M5272 | |
383 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
384 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
385 | #endif | |
1da177e4 | 386 | |
45993653 UKK |
387 | /* Set maximum receive buffer size. */ |
388 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 389 | |
45993653 UKK |
390 | /* Set receive and transmit descriptor base. */ |
391 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
ff43da86 FL |
392 | if (fep->bufdesc_ex) |
393 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) | |
394 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
395 | else | |
396 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) | |
397 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
45993653 | 398 | |
45993653 UKK |
399 | fep->cur_rx = fep->rx_bd_base; |
400 | ||
45993653 UKK |
401 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
402 | if (fep->tx_skbuff[i]) { | |
403 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
404 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 405 | } |
45993653 | 406 | } |
97b72e43 | 407 | |
45993653 UKK |
408 | /* Enable MII mode */ |
409 | if (duplex) { | |
cd1f402c | 410 | /* FD enable */ |
45993653 UKK |
411 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
412 | } else { | |
cd1f402c UKK |
413 | /* No Rcv on Xmit */ |
414 | rcntl |= 0x02; | |
45993653 UKK |
415 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
416 | } | |
cd1f402c | 417 | |
45993653 UKK |
418 | fep->full_duplex = duplex; |
419 | ||
420 | /* Set MII speed */ | |
421 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
422 | ||
423 | /* | |
424 | * The phy interface and speed need to get configured | |
425 | * differently on enet-mac. | |
426 | */ | |
427 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
428 | /* Enable flow control and length check */ |
429 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 430 | |
230dec61 SG |
431 | /* RGMII, RMII or MII */ |
432 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
433 | rcntl |= (1 << 6); | |
434 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 435 | rcntl |= (1 << 8); |
45993653 | 436 | else |
cd1f402c | 437 | rcntl &= ~(1 << 8); |
45993653 | 438 | |
230dec61 SG |
439 | /* 1G, 100M or 10M */ |
440 | if (fep->phy_dev) { | |
441 | if (fep->phy_dev->speed == SPEED_1000) | |
442 | ecntl |= (1 << 5); | |
443 | else if (fep->phy_dev->speed == SPEED_100) | |
444 | rcntl &= ~(1 << 9); | |
445 | else | |
446 | rcntl |= (1 << 9); | |
447 | } | |
45993653 UKK |
448 | } else { |
449 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 450 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 451 | u32 cfgr; |
45993653 UKK |
452 | /* disable the gasket and wait */ |
453 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
454 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
455 | udelay(1); | |
456 | ||
457 | /* | |
458 | * configure the gasket: | |
459 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 460 | * MII, 25 MHz, no loopback, no echo |
45993653 | 461 | */ |
8d82f219 EB |
462 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
463 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
464 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
465 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
466 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
467 | |
468 | /* re-enable the gasket */ | |
469 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 470 | } |
45993653 UKK |
471 | #endif |
472 | } | |
baa70a5c FL |
473 | |
474 | /* enable pause frame*/ | |
475 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
476 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
477 | fep->phy_dev && fep->phy_dev->pause)) { | |
478 | rcntl |= FEC_ENET_FCE; | |
479 | ||
480 | /* set FIFO thresh hold parameter to reduce overrun */ | |
481 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); | |
482 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
483 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
484 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
485 | ||
486 | /* OPD */ | |
487 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
488 | } else { | |
489 | rcntl &= ~FEC_ENET_FCE; | |
490 | } | |
491 | ||
cd1f402c | 492 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 493 | |
230dec61 SG |
494 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
495 | /* enable ENET endian swap */ | |
496 | ecntl |= (1 << 8); | |
497 | /* enable ENET store and forward mode */ | |
498 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
499 | } | |
500 | ||
ff43da86 FL |
501 | if (fep->bufdesc_ex) |
502 | ecntl |= (1 << 4); | |
6605b730 | 503 | |
45993653 | 504 | /* And last, enable the transmit and receive processing */ |
230dec61 | 505 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
506 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
507 | ||
ff43da86 FL |
508 | if (fep->bufdesc_ex) |
509 | fec_ptp_start_cyclecounter(ndev); | |
510 | ||
45993653 UKK |
511 | /* Enable interrupts we wish to service */ |
512 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
513 | } | |
514 | ||
515 | static void | |
516 | fec_stop(struct net_device *ndev) | |
517 | { | |
518 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
519 | const struct platform_device_id *id_entry = |
520 | platform_get_device_id(fep->pdev); | |
42431dc2 | 521 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
522 | |
523 | /* We cannot expect a graceful transmit stop without link !!! */ | |
524 | if (fep->link) { | |
525 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
526 | udelay(10); | |
527 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
528 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
529 | } | |
530 | ||
531 | /* Whack a reset. We should wait for this. */ | |
532 | writel(1, fep->hwp + FEC_ECNTRL); | |
533 | udelay(10); | |
534 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
535 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
536 | |
537 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 538 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 539 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
540 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
541 | } | |
1da177e4 LT |
542 | } |
543 | ||
544 | ||
45993653 UKK |
545 | static void |
546 | fec_timeout(struct net_device *ndev) | |
547 | { | |
548 | struct fec_enet_private *fep = netdev_priv(ndev); | |
549 | ||
550 | ndev->stats.tx_errors++; | |
551 | ||
552 | fec_restart(ndev, fep->full_duplex); | |
553 | netif_wake_queue(ndev); | |
554 | } | |
555 | ||
1da177e4 | 556 | static void |
c556167f | 557 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
558 | { |
559 | struct fec_enet_private *fep; | |
2e28532f | 560 | struct bufdesc *bdp; |
0e702ab3 | 561 | unsigned short status; |
1da177e4 | 562 | struct sk_buff *skb; |
de5fb0a0 | 563 | int index = 0; |
1da177e4 | 564 | |
c556167f | 565 | fep = netdev_priv(ndev); |
1da177e4 LT |
566 | bdp = fep->dirty_tx; |
567 | ||
de5fb0a0 FL |
568 | /* get next bdp of dirty_tx */ |
569 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
570 | bdp = fep->tx_bd_base; | |
571 | else | |
572 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
573 | ||
0e702ab3 | 574 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
de5fb0a0 FL |
575 | |
576 | /* current queue is empty */ | |
577 | if (bdp == fep->cur_tx) | |
f0b3fbea SH |
578 | break; |
579 | ||
de5fb0a0 FL |
580 | if (fep->bufdesc_ex) |
581 | index = (struct bufdesc_ex *)bdp - | |
582 | (struct bufdesc_ex *)fep->tx_bd_base; | |
583 | else | |
584 | index = bdp - fep->tx_bd_base; | |
585 | ||
d1ab1f54 UKK |
586 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
587 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 588 | bdp->cbd_bufaddr = 0; |
1da177e4 | 589 | |
de5fb0a0 FL |
590 | skb = fep->tx_skbuff[index]; |
591 | ||
1da177e4 | 592 | /* Check for errors. */ |
0e702ab3 | 593 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
594 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
595 | BD_ENET_TX_CSL)) { | |
c556167f | 596 | ndev->stats.tx_errors++; |
0e702ab3 | 597 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 598 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 599 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 600 | ndev->stats.tx_window_errors++; |
0e702ab3 | 601 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 602 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 603 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 604 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 605 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 606 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 607 | } else { |
c556167f | 608 | ndev->stats.tx_packets++; |
1da177e4 LT |
609 | } |
610 | ||
ff43da86 FL |
611 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
612 | fep->bufdesc_ex) { | |
6605b730 FL |
613 | struct skb_shared_hwtstamps shhwtstamps; |
614 | unsigned long flags; | |
ff43da86 | 615 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 FL |
616 | |
617 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
618 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
619 | shhwtstamps.hwtstamp = ns_to_ktime( | |
ff43da86 | 620 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
621 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
622 | skb_tstamp_tx(skb, &shhwtstamps); | |
623 | } | |
ff43da86 | 624 | |
0e702ab3 | 625 | if (status & BD_ENET_TX_READY) |
1da177e4 | 626 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 627 | |
1da177e4 LT |
628 | /* Deferred means some collisions occurred during transmit, |
629 | * but we eventually sent the packet OK. | |
630 | */ | |
0e702ab3 | 631 | if (status & BD_ENET_TX_DEF) |
c556167f | 632 | ndev->stats.collisions++; |
6aa20a22 | 633 | |
22f6b860 | 634 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 635 | dev_kfree_skb_any(skb); |
de5fb0a0 FL |
636 | fep->tx_skbuff[index] = NULL; |
637 | ||
638 | fep->dirty_tx = bdp; | |
6aa20a22 | 639 | |
22f6b860 | 640 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 641 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
642 | bdp = fep->tx_bd_base; |
643 | else | |
ff43da86 | 644 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
6aa20a22 | 645 | |
22f6b860 | 646 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 647 | */ |
de5fb0a0 | 648 | if (fep->dirty_tx != fep->cur_tx) { |
c556167f UKK |
649 | if (netif_queue_stopped(ndev)) |
650 | netif_wake_queue(ndev); | |
1da177e4 LT |
651 | } |
652 | } | |
de5fb0a0 | 653 | return; |
1da177e4 LT |
654 | } |
655 | ||
656 | ||
657 | /* During a receive, the cur_rx points to the current incoming buffer. | |
658 | * When we update through the ring, if the next incoming buffer has | |
659 | * not been given to the system, we just set the empty indicator, | |
660 | * effectively tossing the packet. | |
661 | */ | |
dc975382 FL |
662 | static int |
663 | fec_enet_rx(struct net_device *ndev, int budget) | |
1da177e4 | 664 | { |
c556167f | 665 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
666 | const struct platform_device_id *id_entry = |
667 | platform_get_device_id(fep->pdev); | |
2e28532f | 668 | struct bufdesc *bdp; |
0e702ab3 | 669 | unsigned short status; |
1da177e4 LT |
670 | struct sk_buff *skb; |
671 | ushort pkt_len; | |
672 | __u8 *data; | |
dc975382 | 673 | int pkt_received = 0; |
6aa20a22 | 674 | |
0e702ab3 GU |
675 | #ifdef CONFIG_M532x |
676 | flush_cache_all(); | |
6aa20a22 | 677 | #endif |
1da177e4 | 678 | |
1da177e4 LT |
679 | /* First, grab all of the stats for the incoming packet. |
680 | * These get messed up if we get called due to a busy condition. | |
681 | */ | |
682 | bdp = fep->cur_rx; | |
683 | ||
22f6b860 | 684 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 685 | |
dc975382 FL |
686 | if (pkt_received >= budget) |
687 | break; | |
688 | pkt_received++; | |
689 | ||
22f6b860 SH |
690 | /* Since we have allocated space to hold a complete frame, |
691 | * the last indicator should be set. | |
692 | */ | |
693 | if ((status & BD_ENET_RX_LAST) == 0) | |
694 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 695 | |
22f6b860 SH |
696 | if (!fep->opened) |
697 | goto rx_processing_done; | |
1da177e4 | 698 | |
22f6b860 SH |
699 | /* Check for errors. */ |
700 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 701 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 702 | ndev->stats.rx_errors++; |
22f6b860 SH |
703 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
704 | /* Frame too long or too short. */ | |
c556167f | 705 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
706 | } |
707 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 708 | ndev->stats.rx_frame_errors++; |
22f6b860 | 709 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 710 | ndev->stats.rx_crc_errors++; |
22f6b860 | 711 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 712 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 713 | } |
1da177e4 | 714 | |
22f6b860 SH |
715 | /* Report late collisions as a frame error. |
716 | * On this error, the BD is closed, but we don't know what we | |
717 | * have in the buffer. So, just drop this frame on the floor. | |
718 | */ | |
719 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
720 | ndev->stats.rx_errors++; |
721 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
722 | goto rx_processing_done; |
723 | } | |
1da177e4 | 724 | |
22f6b860 | 725 | /* Process the incoming frame. */ |
c556167f | 726 | ndev->stats.rx_packets++; |
22f6b860 | 727 | pkt_len = bdp->cbd_datlen; |
c556167f | 728 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 729 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 730 | |
d1ab1f54 UKK |
731 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
732 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 733 | |
b5680e0b SG |
734 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
735 | swap_buffer(data, pkt_len); | |
736 | ||
22f6b860 SH |
737 | /* This does 16 byte alignment, exactly what we need. |
738 | * The packet length includes FCS, but we don't want to | |
739 | * include that when passing upstream as it messes up | |
740 | * bridging applications. | |
741 | */ | |
b72061a3 | 742 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 743 | |
8549889c | 744 | if (unlikely(!skb)) { |
c556167f | 745 | ndev->stats.rx_dropped++; |
22f6b860 | 746 | } else { |
8549889c | 747 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
748 | skb_put(skb, pkt_len - 4); /* Make room */ |
749 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
c556167f | 750 | skb->protocol = eth_type_trans(skb, ndev); |
ff43da86 | 751 | |
6605b730 | 752 | /* Get receive timestamp from the skb */ |
ff43da86 | 753 | if (fep->hwts_rx_en && fep->bufdesc_ex) { |
6605b730 FL |
754 | struct skb_shared_hwtstamps *shhwtstamps = |
755 | skb_hwtstamps(skb); | |
756 | unsigned long flags; | |
ff43da86 FL |
757 | struct bufdesc_ex *ebdp = |
758 | (struct bufdesc_ex *)bdp; | |
6605b730 FL |
759 | |
760 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
761 | ||
762 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
763 | shhwtstamps->hwtstamp = ns_to_ktime( | |
ff43da86 | 764 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
765 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
766 | } | |
ff43da86 | 767 | |
18a03b97 | 768 | if (!skb_defer_rx_timestamp(skb)) |
dc975382 | 769 | napi_gro_receive(&fep->napi, skb); |
22f6b860 | 770 | } |
f0b3fbea | 771 | |
d1ab1f54 UKK |
772 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
773 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
774 | rx_processing_done: |
775 | /* Clear the status flags for this buffer */ | |
776 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 777 | |
22f6b860 SH |
778 | /* Mark the buffer empty */ |
779 | status |= BD_ENET_RX_EMPTY; | |
780 | bdp->cbd_sc = status; | |
6aa20a22 | 781 | |
ff43da86 FL |
782 | if (fep->bufdesc_ex) { |
783 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
784 | ||
785 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
786 | ebdp->cbd_prot = 0; | |
787 | ebdp->cbd_bdu = 0; | |
788 | } | |
6605b730 | 789 | |
22f6b860 SH |
790 | /* Update BD pointer to next entry */ |
791 | if (status & BD_ENET_RX_WRAP) | |
792 | bdp = fep->rx_bd_base; | |
793 | else | |
ff43da86 | 794 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
22f6b860 SH |
795 | /* Doing this here will keep the FEC running while we process |
796 | * incoming frames. On a heavily loaded network, we should be | |
797 | * able to keep up at the expense of system resources. | |
798 | */ | |
799 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
800 | } | |
2e28532f | 801 | fep->cur_rx = bdp; |
1da177e4 | 802 | |
dc975382 | 803 | return pkt_received; |
1da177e4 LT |
804 | } |
805 | ||
45993653 UKK |
806 | static irqreturn_t |
807 | fec_enet_interrupt(int irq, void *dev_id) | |
808 | { | |
809 | struct net_device *ndev = dev_id; | |
810 | struct fec_enet_private *fep = netdev_priv(ndev); | |
811 | uint int_events; | |
812 | irqreturn_t ret = IRQ_NONE; | |
813 | ||
814 | do { | |
815 | int_events = readl(fep->hwp + FEC_IEVENT); | |
816 | writel(int_events, fep->hwp + FEC_IEVENT); | |
817 | ||
de5fb0a0 | 818 | if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { |
45993653 | 819 | ret = IRQ_HANDLED; |
dc975382 FL |
820 | |
821 | /* Disable the RX interrupt */ | |
822 | if (napi_schedule_prep(&fep->napi)) { | |
823 | writel(FEC_RX_DISABLED_IMASK, | |
824 | fep->hwp + FEC_IMASK); | |
825 | __napi_schedule(&fep->napi); | |
826 | } | |
45993653 UKK |
827 | } |
828 | ||
45993653 UKK |
829 | if (int_events & FEC_ENET_MII) { |
830 | ret = IRQ_HANDLED; | |
831 | complete(&fep->mdio_done); | |
832 | } | |
833 | } while (int_events); | |
834 | ||
835 | return ret; | |
836 | } | |
837 | ||
dc975382 FL |
838 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
839 | { | |
840 | struct net_device *ndev = napi->dev; | |
841 | int pkts = fec_enet_rx(ndev, budget); | |
842 | struct fec_enet_private *fep = netdev_priv(ndev); | |
45993653 | 843 | |
de5fb0a0 FL |
844 | fec_enet_tx(ndev); |
845 | ||
dc975382 FL |
846 | if (pkts < budget) { |
847 | napi_complete(napi); | |
848 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
849 | } | |
850 | return pkts; | |
851 | } | |
45993653 | 852 | |
e6b043d5 | 853 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 854 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 855 | { |
c556167f | 856 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 857 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 858 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 859 | |
49da97dc SG |
860 | /* |
861 | * try to get mac address in following order: | |
862 | * | |
863 | * 1) module parameter via kernel command line in form | |
864 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
865 | */ | |
866 | iap = macaddr; | |
867 | ||
ca2cc333 SG |
868 | #ifdef CONFIG_OF |
869 | /* | |
870 | * 2) from device tree data | |
871 | */ | |
872 | if (!is_valid_ether_addr(iap)) { | |
873 | struct device_node *np = fep->pdev->dev.of_node; | |
874 | if (np) { | |
875 | const char *mac = of_get_mac_address(np); | |
876 | if (mac) | |
877 | iap = (unsigned char *) mac; | |
878 | } | |
879 | } | |
880 | #endif | |
881 | ||
49da97dc | 882 | /* |
ca2cc333 | 883 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
884 | */ |
885 | if (!is_valid_ether_addr(iap)) { | |
886 | #ifdef CONFIG_M5272 | |
887 | if (FEC_FLASHMAC) | |
888 | iap = (unsigned char *)FEC_FLASHMAC; | |
889 | #else | |
890 | if (pdata) | |
589efdc7 | 891 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
892 | #endif |
893 | } | |
894 | ||
895 | /* | |
ca2cc333 | 896 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
897 | */ |
898 | if (!is_valid_ether_addr(iap)) { | |
899 | *((unsigned long *) &tmpaddr[0]) = | |
900 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
901 | *((unsigned short *) &tmpaddr[4]) = | |
902 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 903 | iap = &tmpaddr[0]; |
1da177e4 LT |
904 | } |
905 | ||
c556167f | 906 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 907 | |
49da97dc SG |
908 | /* Adjust MAC if using macaddr */ |
909 | if (iap == macaddr) | |
43af940c | 910 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
911 | } |
912 | ||
e6b043d5 | 913 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 914 | |
e6b043d5 BW |
915 | /* |
916 | * Phy section | |
917 | */ | |
c556167f | 918 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 919 | { |
c556167f | 920 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 BW |
921 | struct phy_device *phy_dev = fep->phy_dev; |
922 | unsigned long flags; | |
1da177e4 | 923 | |
e6b043d5 | 924 | int status_change = 0; |
1da177e4 | 925 | |
e6b043d5 | 926 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 927 | |
e6b043d5 BW |
928 | /* Prevent a state halted on mii error */ |
929 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
930 | phy_dev->state = PHY_RESUMING; | |
931 | goto spin_unlock; | |
932 | } | |
1da177e4 | 933 | |
e6b043d5 | 934 | if (phy_dev->link) { |
d97e7497 | 935 | if (!fep->link) { |
6ea0722f | 936 | fep->link = phy_dev->link; |
e6b043d5 BW |
937 | status_change = 1; |
938 | } | |
1da177e4 | 939 | |
d97e7497 LS |
940 | if (fep->full_duplex != phy_dev->duplex) |
941 | status_change = 1; | |
942 | ||
943 | if (phy_dev->speed != fep->speed) { | |
944 | fep->speed = phy_dev->speed; | |
945 | status_change = 1; | |
946 | } | |
947 | ||
948 | /* if any of the above changed restart the FEC */ | |
949 | if (status_change) | |
c556167f | 950 | fec_restart(ndev, phy_dev->duplex); |
d97e7497 LS |
951 | } else { |
952 | if (fep->link) { | |
c556167f | 953 | fec_stop(ndev); |
d97e7497 LS |
954 | status_change = 1; |
955 | } | |
1da177e4 | 956 | } |
6aa20a22 | 957 | |
e6b043d5 BW |
958 | spin_unlock: |
959 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 960 | |
e6b043d5 BW |
961 | if (status_change) |
962 | phy_print_status(phy_dev); | |
963 | } | |
1da177e4 | 964 | |
e6b043d5 | 965 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 966 | { |
e6b043d5 | 967 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 968 | unsigned long time_left; |
1da177e4 | 969 | |
e6b043d5 | 970 | fep->mii_timeout = 0; |
97b72e43 | 971 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
972 | |
973 | /* start a read op */ | |
974 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
975 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
976 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
977 | ||
978 | /* wait for end of transfer */ | |
97b72e43 BS |
979 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
980 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
981 | if (time_left == 0) { | |
982 | fep->mii_timeout = 1; | |
983 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
984 | return -ETIMEDOUT; | |
1da177e4 | 985 | } |
1da177e4 | 986 | |
e6b043d5 BW |
987 | /* return value */ |
988 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 989 | } |
6aa20a22 | 990 | |
e6b043d5 BW |
991 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
992 | u16 value) | |
1da177e4 | 993 | { |
e6b043d5 | 994 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 995 | unsigned long time_left; |
1da177e4 | 996 | |
e6b043d5 | 997 | fep->mii_timeout = 0; |
97b72e43 | 998 | init_completion(&fep->mdio_done); |
1da177e4 | 999 | |
862f0982 SG |
1000 | /* start a write op */ |
1001 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1002 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1003 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1004 | fep->hwp + FEC_MII_DATA); | |
1005 | ||
1006 | /* wait for end of transfer */ | |
97b72e43 BS |
1007 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1008 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1009 | if (time_left == 0) { | |
1010 | fep->mii_timeout = 1; | |
1011 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
1012 | return -ETIMEDOUT; | |
e6b043d5 | 1013 | } |
1da177e4 | 1014 | |
e6b043d5 BW |
1015 | return 0; |
1016 | } | |
1da177e4 | 1017 | |
e6b043d5 | 1018 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 1019 | { |
e6b043d5 | 1020 | return 0; |
1da177e4 LT |
1021 | } |
1022 | ||
c556167f | 1023 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1024 | { |
c556167f | 1025 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
1026 | const struct platform_device_id *id_entry = |
1027 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1028 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1029 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1030 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1031 | int phy_id; | |
43af940c | 1032 | int dev_id = fep->dev_id; |
562d2f8c | 1033 | |
418bd0d4 BW |
1034 | fep->phy_dev = NULL; |
1035 | ||
6fcc040f GU |
1036 | /* check for attached phy */ |
1037 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
1038 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
1039 | continue; | |
1040 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
1041 | continue; | |
1042 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
1043 | continue; | |
b5680e0b SG |
1044 | if (dev_id--) |
1045 | continue; | |
6fcc040f GU |
1046 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
1047 | break; | |
e6b043d5 | 1048 | } |
1da177e4 | 1049 | |
6fcc040f | 1050 | if (phy_id >= PHY_MAX_ADDR) { |
a7dd3219 LW |
1051 | printk(KERN_INFO |
1052 | "%s: no PHY, assuming direct connection to switch\n", | |
1053 | ndev->name); | |
ea51ade9 | 1054 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
1055 | phy_id = 0; |
1056 | } | |
1057 | ||
a7ed07d5 | 1058 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
f9a8f83b | 1059 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
230dec61 | 1060 | fep->phy_interface); |
6fcc040f | 1061 | if (IS_ERR(phy_dev)) { |
c556167f | 1062 | printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); |
6fcc040f | 1063 | return PTR_ERR(phy_dev); |
e6b043d5 | 1064 | } |
1da177e4 | 1065 | |
e6b043d5 | 1066 | /* mask with MAC supported features */ |
baa70a5c | 1067 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1068 | phy_dev->supported &= PHY_GBIT_FEATURES; |
baa70a5c FL |
1069 | phy_dev->supported |= SUPPORTED_Pause; |
1070 | } | |
230dec61 SG |
1071 | else |
1072 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1073 | ||
e6b043d5 | 1074 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1075 | |
e6b043d5 BW |
1076 | fep->phy_dev = phy_dev; |
1077 | fep->link = 0; | |
1078 | fep->full_duplex = 0; | |
1da177e4 | 1079 | |
a7dd3219 LW |
1080 | printk(KERN_INFO |
1081 | "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
1082 | ndev->name, | |
418bd0d4 BW |
1083 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), |
1084 | fep->phy_dev->irq); | |
1085 | ||
e6b043d5 | 1086 | return 0; |
1da177e4 LT |
1087 | } |
1088 | ||
e6b043d5 | 1089 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1090 | { |
b5680e0b | 1091 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1092 | struct net_device *ndev = platform_get_drvdata(pdev); |
1093 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1094 | const struct platform_device_id *id_entry = |
1095 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1096 | int err = -ENXIO, i; |
6b265293 | 1097 | |
b5680e0b SG |
1098 | /* |
1099 | * The dual fec interfaces are not equivalent with enet-mac. | |
1100 | * Here are the differences: | |
1101 | * | |
1102 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1103 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1104 | * - external phys can only be configured by fec0 | |
1105 | * | |
1106 | * That is to say fec1 can not work independently. It only works | |
1107 | * when fec0 is working. The reason behind this design is that the | |
1108 | * second interface is added primarily for Switch mode. | |
1109 | * | |
1110 | * Because of the last point above, both phys are attached on fec0 | |
1111 | * mdio interface in board design, and need to be configured by | |
1112 | * fec0 mii_bus. | |
1113 | */ | |
43af940c | 1114 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1115 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1116 | if (mii_cnt && fec0_mii_bus) { |
1117 | fep->mii_bus = fec0_mii_bus; | |
1118 | mii_cnt++; | |
1119 | return 0; | |
1120 | } | |
1121 | return -ENOENT; | |
b5680e0b SG |
1122 | } |
1123 | ||
e6b043d5 | 1124 | fep->mii_timeout = 0; |
1da177e4 | 1125 | |
e6b043d5 BW |
1126 | /* |
1127 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1128 | * |
1129 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1130 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1131 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1132 | * document. | |
e6b043d5 | 1133 | */ |
f4d40de3 | 1134 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1135 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1136 | fep->phy_speed--; | |
1137 | fep->phy_speed <<= 1; | |
e6b043d5 | 1138 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1139 | |
e6b043d5 BW |
1140 | fep->mii_bus = mdiobus_alloc(); |
1141 | if (fep->mii_bus == NULL) { | |
1142 | err = -ENOMEM; | |
1143 | goto err_out; | |
1da177e4 LT |
1144 | } |
1145 | ||
e6b043d5 BW |
1146 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1147 | fep->mii_bus->read = fec_enet_mdio_read; | |
1148 | fep->mii_bus->write = fec_enet_mdio_write; | |
1149 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1150 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1151 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1152 | fep->mii_bus->priv = fep; |
1153 | fep->mii_bus->parent = &pdev->dev; | |
1154 | ||
1155 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1156 | if (!fep->mii_bus->irq) { | |
1157 | err = -ENOMEM; | |
1158 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1159 | } |
1160 | ||
e6b043d5 BW |
1161 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1162 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1163 | |
e6b043d5 BW |
1164 | if (mdiobus_register(fep->mii_bus)) |
1165 | goto err_out_free_mdio_irq; | |
1da177e4 | 1166 | |
e163cc97 LW |
1167 | mii_cnt++; |
1168 | ||
b5680e0b SG |
1169 | /* save fec0 mii_bus */ |
1170 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1171 | fec0_mii_bus = fep->mii_bus; | |
1172 | ||
e6b043d5 | 1173 | return 0; |
1da177e4 | 1174 | |
e6b043d5 BW |
1175 | err_out_free_mdio_irq: |
1176 | kfree(fep->mii_bus->irq); | |
1177 | err_out_free_mdiobus: | |
1178 | mdiobus_free(fep->mii_bus); | |
1179 | err_out: | |
1180 | return err; | |
1da177e4 LT |
1181 | } |
1182 | ||
e6b043d5 | 1183 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1184 | { |
e163cc97 LW |
1185 | if (--mii_cnt == 0) { |
1186 | mdiobus_unregister(fep->mii_bus); | |
1187 | kfree(fep->mii_bus->irq); | |
1188 | mdiobus_free(fep->mii_bus); | |
1189 | } | |
1da177e4 LT |
1190 | } |
1191 | ||
c556167f | 1192 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1193 | struct ethtool_cmd *cmd) |
1da177e4 | 1194 | { |
c556167f | 1195 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1196 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1197 | |
e6b043d5 BW |
1198 | if (!phydev) |
1199 | return -ENODEV; | |
1da177e4 | 1200 | |
e6b043d5 | 1201 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1202 | } |
1203 | ||
c556167f | 1204 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1205 | struct ethtool_cmd *cmd) |
1da177e4 | 1206 | { |
c556167f | 1207 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1208 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1209 | |
e6b043d5 BW |
1210 | if (!phydev) |
1211 | return -ENODEV; | |
1da177e4 | 1212 | |
e6b043d5 | 1213 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1214 | } |
1215 | ||
c556167f | 1216 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1217 | struct ethtool_drvinfo *info) |
1da177e4 | 1218 | { |
c556167f | 1219 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1220 | |
7826d43f JP |
1221 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
1222 | sizeof(info->driver)); | |
1223 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
1224 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1225 | } |
1226 | ||
5ebae489 FL |
1227 | static int fec_enet_get_ts_info(struct net_device *ndev, |
1228 | struct ethtool_ts_info *info) | |
1229 | { | |
1230 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1231 | ||
1232 | if (fep->bufdesc_ex) { | |
1233 | ||
1234 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1235 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1236 | SOF_TIMESTAMPING_SOFTWARE | | |
1237 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1238 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1239 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1240 | if (fep->ptp_clock) | |
1241 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
1242 | else | |
1243 | info->phc_index = -1; | |
1244 | ||
1245 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
1246 | (1 << HWTSTAMP_TX_ON); | |
1247 | ||
1248 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
1249 | (1 << HWTSTAMP_FILTER_ALL); | |
1250 | return 0; | |
1251 | } else { | |
1252 | return ethtool_op_get_ts_info(ndev, info); | |
1253 | } | |
1254 | } | |
1255 | ||
baa70a5c FL |
1256 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
1257 | struct ethtool_pauseparam *pause) | |
1258 | { | |
1259 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1260 | ||
1261 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
1262 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
1263 | pause->rx_pause = pause->tx_pause; | |
1264 | } | |
1265 | ||
1266 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
1267 | struct ethtool_pauseparam *pause) | |
1268 | { | |
1269 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1270 | ||
1271 | if (pause->tx_pause != pause->rx_pause) { | |
1272 | netdev_info(ndev, | |
1273 | "hardware only support enable/disable both tx and rx"); | |
1274 | return -EINVAL; | |
1275 | } | |
1276 | ||
1277 | fep->pause_flag = 0; | |
1278 | ||
1279 | /* tx pause must be same as rx pause */ | |
1280 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
1281 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
1282 | ||
1283 | if (pause->rx_pause || pause->autoneg) { | |
1284 | fep->phy_dev->supported |= ADVERTISED_Pause; | |
1285 | fep->phy_dev->advertising |= ADVERTISED_Pause; | |
1286 | } else { | |
1287 | fep->phy_dev->supported &= ~ADVERTISED_Pause; | |
1288 | fep->phy_dev->advertising &= ~ADVERTISED_Pause; | |
1289 | } | |
1290 | ||
1291 | if (pause->autoneg) { | |
1292 | if (netif_running(ndev)) | |
1293 | fec_stop(ndev); | |
1294 | phy_start_aneg(fep->phy_dev); | |
1295 | } | |
1296 | if (netif_running(ndev)) | |
1297 | fec_restart(ndev, 0); | |
1298 | ||
1299 | return 0; | |
1300 | } | |
1301 | ||
9b07be4b | 1302 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
baa70a5c FL |
1303 | .get_pauseparam = fec_enet_get_pauseparam, |
1304 | .set_pauseparam = fec_enet_set_pauseparam, | |
e6b043d5 BW |
1305 | .get_settings = fec_enet_get_settings, |
1306 | .set_settings = fec_enet_set_settings, | |
1307 | .get_drvinfo = fec_enet_get_drvinfo, | |
1308 | .get_link = ethtool_op_get_link, | |
5ebae489 | 1309 | .get_ts_info = fec_enet_get_ts_info, |
e6b043d5 | 1310 | }; |
1da177e4 | 1311 | |
c556167f | 1312 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1313 | { |
c556167f | 1314 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1315 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1316 | |
c556167f | 1317 | if (!netif_running(ndev)) |
e6b043d5 | 1318 | return -EINVAL; |
1da177e4 | 1319 | |
e6b043d5 BW |
1320 | if (!phydev) |
1321 | return -ENODEV; | |
1322 | ||
ff43da86 | 1323 | if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) |
6605b730 | 1324 | return fec_ptp_ioctl(ndev, rq, cmd); |
ff43da86 | 1325 | |
28b04113 | 1326 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1327 | } |
1328 | ||
c556167f | 1329 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1330 | { |
c556167f | 1331 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1332 | unsigned int i; |
f0b3fbea SH |
1333 | struct sk_buff *skb; |
1334 | struct bufdesc *bdp; | |
1335 | ||
1336 | bdp = fep->rx_bd_base; | |
1337 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1338 | skb = fep->rx_skbuff[i]; | |
1339 | ||
1340 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1341 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1342 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1343 | if (skb) | |
1344 | dev_kfree_skb(skb); | |
ff43da86 | 1345 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1346 | } |
1347 | ||
1348 | bdp = fep->tx_bd_base; | |
1349 | for (i = 0; i < TX_RING_SIZE; i++) | |
1350 | kfree(fep->tx_bounce[i]); | |
1351 | } | |
1352 | ||
c556167f | 1353 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1354 | { |
c556167f | 1355 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1356 | unsigned int i; |
f0b3fbea SH |
1357 | struct sk_buff *skb; |
1358 | struct bufdesc *bdp; | |
1359 | ||
1360 | bdp = fep->rx_bd_base; | |
1361 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1362 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1363 | if (!skb) { |
c556167f | 1364 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1365 | return -ENOMEM; |
1366 | } | |
1367 | fep->rx_skbuff[i] = skb; | |
1368 | ||
d1ab1f54 | 1369 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1370 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1371 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
ff43da86 FL |
1372 | |
1373 | if (fep->bufdesc_ex) { | |
1374 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1375 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1376 | } | |
1377 | ||
1378 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1379 | } |
1380 | ||
1381 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1382 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1383 | bdp->cbd_sc |= BD_SC_WRAP; |
1384 | ||
1385 | bdp = fep->tx_bd_base; | |
1386 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1387 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1388 | ||
1389 | bdp->cbd_sc = 0; | |
1390 | bdp->cbd_bufaddr = 0; | |
6605b730 | 1391 | |
ff43da86 FL |
1392 | if (fep->bufdesc_ex) { |
1393 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1394 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1395 | } | |
1396 | ||
1397 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1398 | } |
1399 | ||
1400 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1401 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1402 | bdp->cbd_sc |= BD_SC_WRAP; |
1403 | ||
1404 | return 0; | |
1405 | } | |
1406 | ||
1da177e4 | 1407 | static int |
c556167f | 1408 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1409 | { |
c556167f | 1410 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1411 | int ret; |
1da177e4 | 1412 | |
dc975382 FL |
1413 | napi_enable(&fep->napi); |
1414 | ||
1da177e4 LT |
1415 | /* I should reset the ring buffers here, but I don't yet know |
1416 | * a simple way to do that. | |
1417 | */ | |
1da177e4 | 1418 | |
c556167f | 1419 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1420 | if (ret) |
1421 | return ret; | |
1422 | ||
418bd0d4 | 1423 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1424 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1425 | if (ret) { |
c556167f | 1426 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1427 | return ret; |
1428 | } | |
e6b043d5 | 1429 | phy_start(fep->phy_dev); |
c556167f | 1430 | netif_start_queue(ndev); |
1da177e4 | 1431 | fep->opened = 1; |
22f6b860 | 1432 | return 0; |
1da177e4 LT |
1433 | } |
1434 | ||
1435 | static int | |
c556167f | 1436 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1437 | { |
c556167f | 1438 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1439 | |
22f6b860 | 1440 | /* Don't know what to do yet. */ |
3f104c38 | 1441 | napi_disable(&fep->napi); |
1da177e4 | 1442 | fep->opened = 0; |
c556167f UKK |
1443 | netif_stop_queue(ndev); |
1444 | fec_stop(ndev); | |
1da177e4 | 1445 | |
e497ba82 UKK |
1446 | if (fep->phy_dev) { |
1447 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1448 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1449 | } |
418bd0d4 | 1450 | |
db8880bc | 1451 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1452 | |
1da177e4 LT |
1453 | return 0; |
1454 | } | |
1455 | ||
1da177e4 LT |
1456 | /* Set or clear the multicast filter for this adaptor. |
1457 | * Skeleton taken from sunlance driver. | |
1458 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1459 | * MAC address filtering. Some of the drivers check to make sure it is | |
1460 | * a group multicast address, and discard those that are not. I guess I | |
1461 | * will do the same for now, but just remove the test if you want | |
1462 | * individual filtering as well (do the upper net layers want or support | |
1463 | * this kind of feature?). | |
1464 | */ | |
1465 | ||
1466 | #define HASH_BITS 6 /* #bits in hash */ | |
1467 | #define CRC32_POLY 0xEDB88320 | |
1468 | ||
c556167f | 1469 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1470 | { |
c556167f | 1471 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1472 | struct netdev_hw_addr *ha; |
48e2f183 | 1473 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1474 | unsigned char hash; |
1475 | ||
c556167f | 1476 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1477 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1478 | tmp |= 0x8; | |
1479 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1480 | return; |
1481 | } | |
1da177e4 | 1482 | |
4e831836 SH |
1483 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1484 | tmp &= ~0x8; | |
1485 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1486 | ||
c556167f | 1487 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1488 | /* Catch all multicast addresses, so set the |
1489 | * filter to all 1's | |
1490 | */ | |
1491 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1492 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1493 | ||
1494 | return; | |
1495 | } | |
1496 | ||
1497 | /* Clear filter and add the addresses in hash register | |
1498 | */ | |
1499 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1500 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1501 | ||
c556167f | 1502 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1503 | /* calculate crc32 value of mac address */ |
1504 | crc = 0xffffffff; | |
1505 | ||
c556167f | 1506 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1507 | data = ha->addr[i]; |
4e831836 SH |
1508 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1509 | crc = (crc >> 1) ^ | |
1510 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1511 | } |
1512 | } | |
4e831836 SH |
1513 | |
1514 | /* only upper 6 bits (HASH_BITS) are used | |
1515 | * which point to specific bit in he hash registers | |
1516 | */ | |
1517 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1518 | ||
1519 | if (hash > 31) { | |
1520 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1521 | tmp |= 1 << (hash - 32); | |
1522 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1523 | } else { | |
1524 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1525 | tmp |= 1 << hash; | |
1526 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1527 | } | |
1da177e4 LT |
1528 | } |
1529 | } | |
1530 | ||
22f6b860 | 1531 | /* Set a MAC change in hardware. */ |
009fda83 | 1532 | static int |
c556167f | 1533 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1534 | { |
c556167f | 1535 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1536 | struct sockaddr *addr = p; |
1537 | ||
1538 | if (!is_valid_ether_addr(addr->sa_data)) | |
1539 | return -EADDRNOTAVAIL; | |
1540 | ||
c556167f | 1541 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1542 | |
c556167f UKK |
1543 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1544 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1545 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1546 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1547 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1548 | return 0; |
1da177e4 LT |
1549 | } |
1550 | ||
7f5c6add | 1551 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1552 | /** |
1553 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1554 | * @dev: The FEC network adapter |
1555 | * | |
1556 | * Polled functionality used by netconsole and others in non interrupt mode | |
1557 | * | |
1558 | */ | |
1559 | void fec_poll_controller(struct net_device *dev) | |
1560 | { | |
1561 | int i; | |
1562 | struct fec_enet_private *fep = netdev_priv(dev); | |
1563 | ||
1564 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1565 | if (fep->irq[i] > 0) { | |
1566 | disable_irq(fep->irq[i]); | |
1567 | fec_enet_interrupt(fep->irq[i], dev); | |
1568 | enable_irq(fep->irq[i]); | |
1569 | } | |
1570 | } | |
1571 | } | |
1572 | #endif | |
1573 | ||
009fda83 SH |
1574 | static const struct net_device_ops fec_netdev_ops = { |
1575 | .ndo_open = fec_enet_open, | |
1576 | .ndo_stop = fec_enet_close, | |
1577 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1578 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1579 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1580 | .ndo_validate_addr = eth_validate_addr, |
1581 | .ndo_tx_timeout = fec_timeout, | |
1582 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1583 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1584 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1585 | .ndo_poll_controller = fec_poll_controller, | |
1586 | #endif | |
009fda83 SH |
1587 | }; |
1588 | ||
1da177e4 LT |
1589 | /* |
1590 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1591 | * |
1da177e4 | 1592 | */ |
c556167f | 1593 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1594 | { |
c556167f | 1595 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1596 | struct bufdesc *cbd_base; |
633e7533 | 1597 | struct bufdesc *bdp; |
da2191e3 | 1598 | unsigned int i; |
1da177e4 | 1599 | |
8d4dd5cf SH |
1600 | /* Allocate memory for buffer descriptors. */ |
1601 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
d0320f75 JP |
1602 | GFP_KERNEL); |
1603 | if (!cbd_base) | |
562d2f8c | 1604 | return -ENOMEM; |
562d2f8c | 1605 | |
3b2b74ca | 1606 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1607 | |
c556167f | 1608 | fep->netdev = ndev; |
1da177e4 | 1609 | |
49da97dc | 1610 | /* Get the Ethernet address */ |
c556167f | 1611 | fec_get_mac(ndev); |
1da177e4 | 1612 | |
8d4dd5cf | 1613 | /* Set receive and transmit descriptor base. */ |
1da177e4 | 1614 | fep->rx_bd_base = cbd_base; |
ff43da86 FL |
1615 | if (fep->bufdesc_ex) |
1616 | fep->tx_bd_base = (struct bufdesc *) | |
1617 | (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); | |
1618 | else | |
1619 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1da177e4 | 1620 | |
22f6b860 | 1621 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1622 | ndev->watchdog_timeo = TX_TIMEOUT; |
1623 | ndev->netdev_ops = &fec_netdev_ops; | |
1624 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 1625 | |
dc975382 FL |
1626 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
1627 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); | |
1628 | ||
633e7533 RH |
1629 | /* Initialize the receive buffer descriptors. */ |
1630 | bdp = fep->rx_bd_base; | |
1631 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1632 | ||
1633 | /* Initialize the BD for every fragment in the page. */ | |
1634 | bdp->cbd_sc = 0; | |
ff43da86 | 1635 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
633e7533 RH |
1636 | } |
1637 | ||
1638 | /* Set the last buffer to wrap */ | |
ff43da86 | 1639 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
633e7533 RH |
1640 | bdp->cbd_sc |= BD_SC_WRAP; |
1641 | ||
1642 | /* ...and the same for transmit */ | |
1643 | bdp = fep->tx_bd_base; | |
de5fb0a0 | 1644 | fep->cur_tx = bdp; |
633e7533 RH |
1645 | for (i = 0; i < TX_RING_SIZE; i++) { |
1646 | ||
1647 | /* Initialize the BD for every fragment in the page. */ | |
1648 | bdp->cbd_sc = 0; | |
1649 | bdp->cbd_bufaddr = 0; | |
ff43da86 | 1650 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
633e7533 RH |
1651 | } |
1652 | ||
1653 | /* Set the last buffer to wrap */ | |
ff43da86 | 1654 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
633e7533 | 1655 | bdp->cbd_sc |= BD_SC_WRAP; |
de5fb0a0 | 1656 | fep->dirty_tx = bdp; |
633e7533 | 1657 | |
c556167f | 1658 | fec_restart(ndev, 0); |
1da177e4 | 1659 | |
1da177e4 LT |
1660 | return 0; |
1661 | } | |
1662 | ||
ca2cc333 | 1663 | #ifdef CONFIG_OF |
33897cc8 | 1664 | static int fec_get_phy_mode_dt(struct platform_device *pdev) |
ca2cc333 SG |
1665 | { |
1666 | struct device_node *np = pdev->dev.of_node; | |
1667 | ||
1668 | if (np) | |
1669 | return of_get_phy_mode(np); | |
1670 | ||
1671 | return -ENODEV; | |
1672 | } | |
1673 | ||
33897cc8 | 1674 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1675 | { |
1676 | int err, phy_reset; | |
a3caad0a | 1677 | int msec = 1; |
ca2cc333 SG |
1678 | struct device_node *np = pdev->dev.of_node; |
1679 | ||
1680 | if (!np) | |
a9b2c8ef | 1681 | return; |
ca2cc333 | 1682 | |
a3caad0a SG |
1683 | of_property_read_u32(np, "phy-reset-duration", &msec); |
1684 | /* A sane reset duration should not be longer than 1s */ | |
1685 | if (msec > 1000) | |
1686 | msec = 1; | |
1687 | ||
ca2cc333 | 1688 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
1689 | if (!gpio_is_valid(phy_reset)) |
1690 | return; | |
1691 | ||
119fc007 SG |
1692 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
1693 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 1694 | if (err) { |
07dcf8e9 | 1695 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 1696 | return; |
ca2cc333 | 1697 | } |
a3caad0a | 1698 | msleep(msec); |
ca2cc333 | 1699 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
1700 | } |
1701 | #else /* CONFIG_OF */ | |
0c7768a0 | 1702 | static int fec_get_phy_mode_dt(struct platform_device *pdev) |
ca2cc333 SG |
1703 | { |
1704 | return -ENODEV; | |
1705 | } | |
1706 | ||
0c7768a0 | 1707 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
1708 | { |
1709 | /* | |
1710 | * In case of platform probe, the reset has been done | |
1711 | * by machine code. | |
1712 | */ | |
ca2cc333 SG |
1713 | } |
1714 | #endif /* CONFIG_OF */ | |
1715 | ||
33897cc8 | 1716 | static int |
ead73183 SH |
1717 | fec_probe(struct platform_device *pdev) |
1718 | { | |
1719 | struct fec_enet_private *fep; | |
5eb32bd0 | 1720 | struct fec_platform_data *pdata; |
ead73183 SH |
1721 | struct net_device *ndev; |
1722 | int i, irq, ret = 0; | |
1723 | struct resource *r; | |
ca2cc333 | 1724 | const struct of_device_id *of_id; |
43af940c | 1725 | static int dev_id; |
b2bccee1 | 1726 | struct pinctrl *pinctrl; |
5fa9c0fe | 1727 | struct regulator *reg_phy; |
ca2cc333 SG |
1728 | |
1729 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
1730 | if (of_id) | |
1731 | pdev->id_entry = of_id->data; | |
ead73183 SH |
1732 | |
1733 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1734 | if (!r) | |
1735 | return -ENXIO; | |
1736 | ||
ead73183 SH |
1737 | /* Init network device */ |
1738 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
83e519b6 FE |
1739 | if (!ndev) |
1740 | return -ENOMEM; | |
ead73183 SH |
1741 | |
1742 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1743 | ||
1744 | /* setup board info structure */ | |
1745 | fep = netdev_priv(ndev); | |
ead73183 | 1746 | |
baa70a5c FL |
1747 | /* default enable pause frame auto negotiation */ |
1748 | if (pdev->id_entry && | |
1749 | (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) | |
1750 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; | |
1751 | ||
83e519b6 | 1752 | fep->hwp = devm_request_and_ioremap(&pdev->dev, r); |
e6b043d5 | 1753 | fep->pdev = pdev; |
43af940c | 1754 | fep->dev_id = dev_id++; |
ead73183 | 1755 | |
ff43da86 FL |
1756 | fep->bufdesc_ex = 0; |
1757 | ||
24e531b4 | 1758 | if (!fep->hwp) { |
ead73183 SH |
1759 | ret = -ENOMEM; |
1760 | goto failed_ioremap; | |
1761 | } | |
1762 | ||
1763 | platform_set_drvdata(pdev, ndev); | |
1764 | ||
ca2cc333 SG |
1765 | ret = fec_get_phy_mode_dt(pdev); |
1766 | if (ret < 0) { | |
1767 | pdata = pdev->dev.platform_data; | |
1768 | if (pdata) | |
1769 | fep->phy_interface = pdata->phy; | |
1770 | else | |
1771 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
1772 | } else { | |
1773 | fep->phy_interface = ret; | |
1774 | } | |
1775 | ||
b2bccee1 SG |
1776 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1777 | if (IS_ERR(pinctrl)) { | |
1778 | ret = PTR_ERR(pinctrl); | |
1779 | goto failed_pin; | |
1780 | } | |
1781 | ||
f4d40de3 SH |
1782 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1783 | if (IS_ERR(fep->clk_ipg)) { | |
1784 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
1785 | goto failed_clk; |
1786 | } | |
f4d40de3 SH |
1787 | |
1788 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1789 | if (IS_ERR(fep->clk_ahb)) { | |
1790 | ret = PTR_ERR(fep->clk_ahb); | |
1791 | goto failed_clk; | |
1792 | } | |
1793 | ||
6605b730 | 1794 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
e2f8d555 FE |
1795 | fep->bufdesc_ex = |
1796 | pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; | |
6605b730 FL |
1797 | if (IS_ERR(fep->clk_ptp)) { |
1798 | ret = PTR_ERR(fep->clk_ptp); | |
ff43da86 | 1799 | fep->bufdesc_ex = 0; |
6605b730 | 1800 | } |
6605b730 | 1801 | |
f4d40de3 SH |
1802 | clk_prepare_enable(fep->clk_ahb); |
1803 | clk_prepare_enable(fep->clk_ipg); | |
ff43da86 FL |
1804 | if (!IS_ERR(fep->clk_ptp)) |
1805 | clk_prepare_enable(fep->clk_ptp); | |
1806 | ||
5fa9c0fe SG |
1807 | reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
1808 | if (!IS_ERR(reg_phy)) { | |
1809 | ret = regulator_enable(reg_phy); | |
1810 | if (ret) { | |
1811 | dev_err(&pdev->dev, | |
1812 | "Failed to enable phy regulator: %d\n", ret); | |
1813 | goto failed_regulator; | |
1814 | } | |
1815 | } | |
1816 | ||
2ca9b2aa SG |
1817 | fec_reset_phy(pdev); |
1818 | ||
e2f8d555 FE |
1819 | if (fep->bufdesc_ex) |
1820 | fec_ptp_init(ndev, pdev); | |
1821 | ||
1822 | ret = fec_enet_init(ndev); | |
1823 | if (ret) | |
1824 | goto failed_init; | |
1825 | ||
1826 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1827 | irq = platform_get_irq(pdev, i); | |
1828 | if (irq < 0) { | |
1829 | if (i) | |
1830 | break; | |
1831 | ret = irq; | |
1832 | goto failed_irq; | |
1833 | } | |
1834 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1835 | if (ret) { | |
1836 | while (--i >= 0) { | |
1837 | irq = platform_get_irq(pdev, i); | |
1838 | free_irq(irq, ndev); | |
1839 | } | |
1840 | goto failed_irq; | |
1841 | } | |
1842 | } | |
1843 | ||
e6b043d5 BW |
1844 | ret = fec_enet_mii_init(pdev); |
1845 | if (ret) | |
1846 | goto failed_mii_init; | |
1847 | ||
03c698c9 OS |
1848 | /* Carrier starts down, phylib will bring it up */ |
1849 | netif_carrier_off(ndev); | |
1850 | ||
ead73183 SH |
1851 | ret = register_netdev(ndev); |
1852 | if (ret) | |
1853 | goto failed_register; | |
1854 | ||
1855 | return 0; | |
1856 | ||
1857 | failed_register: | |
e6b043d5 BW |
1858 | fec_enet_mii_remove(fep); |
1859 | failed_mii_init: | |
e2f8d555 FE |
1860 | failed_init: |
1861 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1862 | irq = platform_get_irq(pdev, i); | |
1863 | if (irq > 0) | |
1864 | free_irq(irq, ndev); | |
1865 | } | |
1866 | failed_irq: | |
5fa9c0fe | 1867 | failed_regulator: |
f4d40de3 SH |
1868 | clk_disable_unprepare(fep->clk_ahb); |
1869 | clk_disable_unprepare(fep->clk_ipg); | |
ff43da86 FL |
1870 | if (!IS_ERR(fep->clk_ptp)) |
1871 | clk_disable_unprepare(fep->clk_ptp); | |
b2bccee1 | 1872 | failed_pin: |
ead73183 | 1873 | failed_clk: |
ead73183 SH |
1874 | failed_ioremap: |
1875 | free_netdev(ndev); | |
1876 | ||
1877 | return ret; | |
1878 | } | |
1879 | ||
33897cc8 | 1880 | static int |
ead73183 SH |
1881 | fec_drv_remove(struct platform_device *pdev) |
1882 | { | |
1883 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1884 | struct fec_enet_private *fep = netdev_priv(ndev); | |
e163cc97 | 1885 | int i; |
ead73183 | 1886 | |
e163cc97 | 1887 | unregister_netdev(ndev); |
e6b043d5 | 1888 | fec_enet_mii_remove(fep); |
6605b730 FL |
1889 | del_timer_sync(&fep->time_keep); |
1890 | clk_disable_unprepare(fep->clk_ptp); | |
1891 | if (fep->ptp_clock) | |
1892 | ptp_clock_unregister(fep->ptp_clock); | |
f4d40de3 SH |
1893 | clk_disable_unprepare(fep->clk_ahb); |
1894 | clk_disable_unprepare(fep->clk_ipg); | |
7f7d6c28 FE |
1895 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
1896 | int irq = platform_get_irq(pdev, i); | |
1897 | if (irq > 0) | |
1898 | free_irq(irq, ndev); | |
1899 | } | |
ead73183 | 1900 | free_netdev(ndev); |
28e2188e | 1901 | |
b3cde36c UKK |
1902 | platform_set_drvdata(pdev, NULL); |
1903 | ||
ead73183 SH |
1904 | return 0; |
1905 | } | |
1906 | ||
59d4289b | 1907 | #ifdef CONFIG_PM |
ead73183 | 1908 | static int |
87cad5c3 | 1909 | fec_suspend(struct device *dev) |
ead73183 | 1910 | { |
87cad5c3 | 1911 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1912 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1913 | |
04e5216d UKK |
1914 | if (netif_running(ndev)) { |
1915 | fec_stop(ndev); | |
1916 | netif_device_detach(ndev); | |
ead73183 | 1917 | } |
f4d40de3 SH |
1918 | clk_disable_unprepare(fep->clk_ahb); |
1919 | clk_disable_unprepare(fep->clk_ipg); | |
04e5216d | 1920 | |
ead73183 SH |
1921 | return 0; |
1922 | } | |
1923 | ||
1924 | static int | |
87cad5c3 | 1925 | fec_resume(struct device *dev) |
ead73183 | 1926 | { |
87cad5c3 | 1927 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1928 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1929 | |
f4d40de3 SH |
1930 | clk_prepare_enable(fep->clk_ahb); |
1931 | clk_prepare_enable(fep->clk_ipg); | |
04e5216d UKK |
1932 | if (netif_running(ndev)) { |
1933 | fec_restart(ndev, fep->full_duplex); | |
1934 | netif_device_attach(ndev); | |
ead73183 | 1935 | } |
04e5216d | 1936 | |
ead73183 SH |
1937 | return 0; |
1938 | } | |
1939 | ||
59d4289b DK |
1940 | static const struct dev_pm_ops fec_pm_ops = { |
1941 | .suspend = fec_suspend, | |
1942 | .resume = fec_resume, | |
1943 | .freeze = fec_suspend, | |
1944 | .thaw = fec_resume, | |
1945 | .poweroff = fec_suspend, | |
1946 | .restore = fec_resume, | |
1947 | }; | |
87cad5c3 | 1948 | #endif |
59d4289b | 1949 | |
ead73183 SH |
1950 | static struct platform_driver fec_driver = { |
1951 | .driver = { | |
b5680e0b | 1952 | .name = DRIVER_NAME, |
87cad5c3 EB |
1953 | .owner = THIS_MODULE, |
1954 | #ifdef CONFIG_PM | |
1955 | .pm = &fec_pm_ops, | |
1956 | #endif | |
ca2cc333 | 1957 | .of_match_table = fec_dt_ids, |
ead73183 | 1958 | }, |
b5680e0b | 1959 | .id_table = fec_devtype, |
87cad5c3 | 1960 | .probe = fec_probe, |
33897cc8 | 1961 | .remove = fec_drv_remove, |
ead73183 SH |
1962 | }; |
1963 | ||
aaca2377 | 1964 | module_platform_driver(fec_driver); |
1da177e4 LT |
1965 | |
1966 | MODULE_LICENSE("GPL"); |