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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
1da177e4 LT |
32 | #include <linux/init.h> |
33 | #include <linux/delay.h> | |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
4c09eed9 JB |
37 | #include <linux/in.h> |
38 | #include <linux/ip.h> | |
39 | #include <net/ip.h> | |
40 | #include <linux/tcp.h> | |
41 | #include <linux/udp.h> | |
42 | #include <linux/icmp.h> | |
1da177e4 LT |
43 | #include <linux/spinlock.h> |
44 | #include <linux/workqueue.h> | |
45 | #include <linux/bitops.h> | |
6f501b17 SH |
46 | #include <linux/io.h> |
47 | #include <linux/irq.h> | |
196719ec | 48 | #include <linux/clk.h> |
ead73183 | 49 | #include <linux/platform_device.h> |
e6b043d5 | 50 | #include <linux/phy.h> |
5eb32bd0 | 51 | #include <linux/fec.h> |
ca2cc333 SG |
52 | #include <linux/of.h> |
53 | #include <linux/of_device.h> | |
54 | #include <linux/of_gpio.h> | |
55 | #include <linux/of_net.h> | |
5fa9c0fe | 56 | #include <linux/regulator/consumer.h> |
cdffcf1b | 57 | #include <linux/if_vlan.h> |
1da177e4 | 58 | |
080853af | 59 | #include <asm/cacheflush.h> |
196719ec | 60 | |
1da177e4 | 61 | #include "fec.h" |
1da177e4 | 62 | |
772e42b0 CM |
63 | static void set_multicast_list(struct net_device *ndev); |
64 | ||
085e79ed | 65 | #if defined(CONFIG_ARM) |
196719ec SH |
66 | #define FEC_ALIGNMENT 0xf |
67 | #else | |
68 | #define FEC_ALIGNMENT 0x3 | |
69 | #endif | |
70 | ||
b5680e0b SG |
71 | #define DRIVER_NAME "fec" |
72 | ||
baa70a5c FL |
73 | /* Pause frame feild and FIFO threshold */ |
74 | #define FEC_ENET_FCE (1 << 5) | |
75 | #define FEC_ENET_RSEM_V 0x84 | |
76 | #define FEC_ENET_RSFL_V 16 | |
77 | #define FEC_ENET_RAEM_V 0x8 | |
78 | #define FEC_ENET_RAFL_V 0x8 | |
79 | #define FEC_ENET_OPD_V 0xFFF0 | |
80 | ||
b5680e0b SG |
81 | /* Controller is ENET-MAC */ |
82 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
83 | /* Controller needs driver to swap frame */ | |
84 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
85 | /* Controller uses gasket */ |
86 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
87 | /* Controller has GBIT support */ |
88 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
ff43da86 FL |
89 | /* Controller has extend desc buffer */ |
90 | #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) | |
48496255 SG |
91 | /* Controller has hardware checksum support */ |
92 | #define FEC_QUIRK_HAS_CSUM (1 << 5) | |
cdffcf1b JB |
93 | /* Controller has hardware vlan support */ |
94 | #define FEC_QUIRK_HAS_VLAN (1 << 6) | |
03191656 FL |
95 | /* ENET IP errata ERR006358 |
96 | * | |
97 | * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously | |
98 | * detected as not set during a prior frame transmission, then the | |
99 | * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs | |
100 | * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in | |
101 | * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously | |
102 | * detected as not set during a prior frame transmission, then the | |
103 | * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs | |
104 | * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in | |
105 | * frames not being transmitted until there is a 0-to-1 transition on | |
106 | * ENET_TDAR[TDAR]. | |
107 | */ | |
108 | #define FEC_QUIRK_ERR006358 (1 << 7) | |
b5680e0b SG |
109 | |
110 | static struct platform_device_id fec_devtype[] = { | |
111 | { | |
0ca1e290 | 112 | /* keep it for coldfire */ |
b5680e0b SG |
113 | .name = DRIVER_NAME, |
114 | .driver_data = 0, | |
0ca1e290 SG |
115 | }, { |
116 | .name = "imx25-fec", | |
117 | .driver_data = FEC_QUIRK_USE_GASKET, | |
118 | }, { | |
119 | .name = "imx27-fec", | |
120 | .driver_data = 0, | |
b5680e0b SG |
121 | }, { |
122 | .name = "imx28-fec", | |
123 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
124 | }, { |
125 | .name = "imx6q-fec", | |
ff43da86 | 126 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
cdffcf1b | 127 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | |
03191656 | 128 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, |
ca7c4a45 | 129 | }, { |
36803542 | 130 | .name = "mvf600-fec", |
ca7c4a45 | 131 | .driver_data = FEC_QUIRK_ENET_MAC, |
0ca1e290 SG |
132 | }, { |
133 | /* sentinel */ | |
134 | } | |
b5680e0b | 135 | }; |
0ca1e290 | 136 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 137 | |
ca2cc333 | 138 | enum imx_fec_type { |
a7dd3219 | 139 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
140 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
141 | IMX28_FEC, | |
230dec61 | 142 | IMX6Q_FEC, |
36803542 | 143 | MVF600_FEC, |
ca2cc333 SG |
144 | }; |
145 | ||
146 | static const struct of_device_id fec_dt_ids[] = { | |
147 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
148 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
149 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 150 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
36803542 | 151 | { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, |
ca2cc333 SG |
152 | { /* sentinel */ } |
153 | }; | |
154 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
155 | ||
49da97dc SG |
156 | static unsigned char macaddr[ETH_ALEN]; |
157 | module_param_array(macaddr, byte, NULL, 0); | |
158 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 159 | |
49da97dc | 160 | #if defined(CONFIG_M5272) |
1da177e4 LT |
161 | /* |
162 | * Some hardware gets it MAC address out of local flash memory. | |
163 | * if this is non-zero then assume it is the address to get MAC from. | |
164 | */ | |
165 | #if defined(CONFIG_NETtel) | |
166 | #define FEC_FLASHMAC 0xf0006006 | |
167 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
168 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
169 | #elif defined(CONFIG_CANCam) |
170 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
171 | #elif defined (CONFIG_M5272C3) |
172 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
173 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 174 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
175 | #else |
176 | #define FEC_FLASHMAC 0 | |
177 | #endif | |
43be6366 | 178 | #endif /* CONFIG_M5272 */ |
ead73183 | 179 | |
ff43da86 | 180 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) |
6b265293 | 181 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
182 | #endif |
183 | ||
22f6b860 | 184 | /* Interrupt events/masks. */ |
1da177e4 LT |
185 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
186 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
187 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
188 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
189 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
190 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
191 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
192 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
193 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
194 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
195 | ||
4bee1f9a | 196 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
dc975382 | 197 | #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) |
4bee1f9a | 198 | |
cdffcf1b | 199 | /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. |
1da177e4 | 200 | */ |
cdffcf1b | 201 | #define PKT_MAXBUF_SIZE 1522 |
1da177e4 | 202 | #define PKT_MINBUF_SIZE 64 |
cdffcf1b | 203 | #define PKT_MAXBLR_SIZE 1536 |
1da177e4 | 204 | |
4c09eed9 JB |
205 | /* FEC receive acceleration */ |
206 | #define FEC_RACC_IPDIS (1 << 1) | |
207 | #define FEC_RACC_PRODIS (1 << 2) | |
208 | #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) | |
209 | ||
1da177e4 | 210 | /* |
6b265293 | 211 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
212 | * size bits. Other FEC hardware does not, so we need to take that into |
213 | * account when setting it. | |
214 | */ | |
562d2f8c | 215 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 216 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
217 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
218 | #else | |
219 | #define OPT_FRAME_SIZE 0 | |
220 | #endif | |
221 | ||
e6b043d5 BW |
222 | /* FEC MII MMFR bits definition */ |
223 | #define FEC_MMFR_ST (1 << 30) | |
224 | #define FEC_MMFR_OP_READ (2 << 28) | |
225 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
226 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
227 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
228 | #define FEC_MMFR_TA (2 << 16) | |
229 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 230 | |
c3b084c2 | 231 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 232 | |
22f6b860 SH |
233 | /* Transmitter timeout */ |
234 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 235 | |
baa70a5c FL |
236 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
237 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
238 | ||
e163cc97 LW |
239 | static int mii_cnt; |
240 | ||
ff43da86 FL |
241 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) |
242 | { | |
243 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
244 | if (is_ex) | |
245 | return (struct bufdesc *)(ex + 1); | |
246 | else | |
247 | return bdp + 1; | |
248 | } | |
249 | ||
250 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) | |
251 | { | |
252 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
253 | if (is_ex) | |
254 | return (struct bufdesc *)(ex - 1); | |
255 | else | |
256 | return bdp - 1; | |
257 | } | |
258 | ||
b5680e0b SG |
259 | static void *swap_buffer(void *bufaddr, int len) |
260 | { | |
261 | int i; | |
262 | unsigned int *buf = bufaddr; | |
263 | ||
ffed61e6 | 264 | for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) |
b5680e0b SG |
265 | *buf = cpu_to_be32(*buf); |
266 | ||
267 | return bufaddr; | |
268 | } | |
269 | ||
4c09eed9 JB |
270 | static int |
271 | fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) | |
272 | { | |
273 | /* Only run for packets requiring a checksum. */ | |
274 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
275 | return 0; | |
276 | ||
277 | if (unlikely(skb_cow_head(skb, 0))) | |
278 | return -1; | |
279 | ||
280 | *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
c7621cb3 | 285 | static netdev_tx_t |
c556167f | 286 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 287 | { |
c556167f | 288 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
289 | const struct platform_device_id *id_entry = |
290 | platform_get_device_id(fep->pdev); | |
03191656 | 291 | struct bufdesc *bdp, *bdp_pre; |
9555b31e | 292 | void *bufaddr; |
0e702ab3 | 293 | unsigned short status; |
de5fb0a0 | 294 | unsigned int index; |
1da177e4 | 295 | |
1da177e4 LT |
296 | /* Fill in a Tx ring entry */ |
297 | bdp = fep->cur_tx; | |
298 | ||
0e702ab3 | 299 | status = bdp->cbd_sc; |
22f6b860 | 300 | |
0e702ab3 | 301 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 302 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 303 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 304 | */ |
31b7720c | 305 | netdev_err(ndev, "tx queue full!\n"); |
5b548140 | 306 | return NETDEV_TX_BUSY; |
1da177e4 | 307 | } |
1da177e4 | 308 | |
4c09eed9 JB |
309 | /* Protocol checksum off-load for TCP and UDP. */ |
310 | if (fec_enet_clear_csum(skb, ndev)) { | |
311 | kfree_skb(skb); | |
312 | return NETDEV_TX_OK; | |
313 | } | |
314 | ||
22f6b860 | 315 | /* Clear all of the status flags */ |
0e702ab3 | 316 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 317 | |
22f6b860 | 318 | /* Set buffer length and buffer pointer */ |
9555b31e | 319 | bufaddr = skb->data; |
1da177e4 LT |
320 | bdp->cbd_datlen = skb->len; |
321 | ||
322 | /* | |
22f6b860 SH |
323 | * On some FEC implementations data must be aligned on |
324 | * 4-byte boundaries. Use bounce buffers to copy data | |
325 | * and get it aligned. Ugh. | |
1da177e4 | 326 | */ |
de5fb0a0 FL |
327 | if (fep->bufdesc_ex) |
328 | index = (struct bufdesc_ex *)bdp - | |
329 | (struct bufdesc_ex *)fep->tx_bd_base; | |
330 | else | |
331 | index = bdp - fep->tx_bd_base; | |
332 | ||
9555b31e | 333 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
8a73b0bc | 334 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 335 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
336 | } |
337 | ||
b5680e0b SG |
338 | /* |
339 | * Some design made an incorrect assumption on endian mode of | |
340 | * the system that it's running on. As the result, driver has to | |
341 | * swap every frame going to and coming from the controller. | |
342 | */ | |
343 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
344 | swap_buffer(bufaddr, skb->len); | |
345 | ||
22f6b860 | 346 | /* Save skb pointer */ |
de5fb0a0 | 347 | fep->tx_skbuff[index] = skb; |
6aa20a22 | 348 | |
1da177e4 LT |
349 | /* Push the data cache so the CPM does not get stale memory |
350 | * data. | |
351 | */ | |
d1ab1f54 | 352 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 353 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 354 | |
0e702ab3 GU |
355 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
356 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 357 | */ |
0e702ab3 | 358 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 359 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 360 | bdp->cbd_sc = status; |
1da177e4 | 361 | |
ff43da86 FL |
362 | if (fep->bufdesc_ex) { |
363 | ||
364 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
365 | ebdp->cbd_bdu = 0; | |
366 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
6605b730 | 367 | fep->hwts_tx_en)) { |
ff43da86 | 368 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
6605b730 | 369 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
ff43da86 | 370 | } else { |
ff43da86 | 371 | ebdp->cbd_esc = BD_ENET_TX_INT; |
4c09eed9 JB |
372 | |
373 | /* Enable protocol checksum flags | |
374 | * We do not bother with the IP Checksum bits as they | |
375 | * are done by the kernel | |
376 | */ | |
377 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
378 | ebdp->cbd_esc |= BD_ENET_TX_PINS; | |
ff43da86 | 379 | } |
6605b730 | 380 | } |
03191656 FL |
381 | |
382 | bdp_pre = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
383 | if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && | |
384 | !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { | |
385 | fep->delay_work.trig_tx = true; | |
386 | schedule_delayed_work(&(fep->delay_work.delay_work), | |
387 | msecs_to_jiffies(1)); | |
388 | } | |
389 | ||
22f6b860 SH |
390 | /* If this was the last BD in the ring, start at the beginning again. */ |
391 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 392 | bdp = fep->tx_bd_base; |
22f6b860 | 393 | else |
ff43da86 | 394 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
1da177e4 | 395 | |
de5fb0a0 FL |
396 | fep->cur_tx = bdp; |
397 | ||
398 | if (fep->cur_tx == fep->dirty_tx) | |
c556167f | 399 | netif_stop_queue(ndev); |
1da177e4 | 400 | |
de5fb0a0 FL |
401 | /* Trigger transmission start */ |
402 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
1da177e4 | 403 | |
18a03b97 RC |
404 | skb_tx_timestamp(skb); |
405 | ||
6ed10654 | 406 | return NETDEV_TX_OK; |
1da177e4 LT |
407 | } |
408 | ||
14109a59 FL |
409 | /* Init RX & TX buffer descriptors |
410 | */ | |
411 | static void fec_enet_bd_init(struct net_device *dev) | |
412 | { | |
413 | struct fec_enet_private *fep = netdev_priv(dev); | |
414 | struct bufdesc *bdp; | |
415 | unsigned int i; | |
416 | ||
417 | /* Initialize the receive buffer descriptors. */ | |
418 | bdp = fep->rx_bd_base; | |
419 | for (i = 0; i < RX_RING_SIZE; i++) { | |
420 | ||
421 | /* Initialize the BD for every fragment in the page. */ | |
422 | if (bdp->cbd_bufaddr) | |
423 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
424 | else | |
425 | bdp->cbd_sc = 0; | |
426 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
427 | } | |
428 | ||
429 | /* Set the last buffer to wrap */ | |
430 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
431 | bdp->cbd_sc |= BD_SC_WRAP; | |
432 | ||
433 | fep->cur_rx = fep->rx_bd_base; | |
434 | ||
435 | /* ...and the same for transmit */ | |
436 | bdp = fep->tx_bd_base; | |
437 | fep->cur_tx = bdp; | |
438 | for (i = 0; i < TX_RING_SIZE; i++) { | |
439 | ||
440 | /* Initialize the BD for every fragment in the page. */ | |
441 | bdp->cbd_sc = 0; | |
442 | if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { | |
443 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
444 | fep->tx_skbuff[i] = NULL; | |
445 | } | |
446 | bdp->cbd_bufaddr = 0; | |
447 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
448 | } | |
449 | ||
450 | /* Set the last buffer to wrap */ | |
451 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
452 | bdp->cbd_sc |= BD_SC_WRAP; | |
453 | fep->dirty_tx = bdp; | |
454 | } | |
455 | ||
45993653 UKK |
456 | /* This function is called to start or restart the FEC during a link |
457 | * change. This only happens when switching between half and full | |
458 | * duplex. | |
459 | */ | |
1da177e4 | 460 | static void |
45993653 | 461 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 462 | { |
c556167f | 463 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
464 | const struct platform_device_id *id_entry = |
465 | platform_get_device_id(fep->pdev); | |
466 | int i; | |
4c09eed9 | 467 | u32 val; |
cd1f402c UKK |
468 | u32 temp_mac[2]; |
469 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 470 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 471 | |
54309fa6 FL |
472 | if (netif_running(ndev)) { |
473 | netif_device_detach(ndev); | |
474 | napi_disable(&fep->napi); | |
475 | netif_stop_queue(ndev); | |
31691344 | 476 | netif_tx_lock_bh(ndev); |
54309fa6 FL |
477 | } |
478 | ||
45993653 UKK |
479 | /* Whack a reset. We should wait for this. */ |
480 | writel(1, fep->hwp + FEC_ECNTRL); | |
481 | udelay(10); | |
1da177e4 | 482 | |
45993653 UKK |
483 | /* |
484 | * enet-mac reset will reset mac address registers too, | |
485 | * so need to reconfigure it. | |
486 | */ | |
487 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
488 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
489 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
490 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
491 | } | |
1da177e4 | 492 | |
45993653 UKK |
493 | /* Clear any outstanding interrupt. */ |
494 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 495 | |
772e42b0 CM |
496 | /* Setup multicast filter. */ |
497 | set_multicast_list(ndev); | |
45993653 UKK |
498 | #ifndef CONFIG_M5272 |
499 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
500 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
501 | #endif | |
1da177e4 | 502 | |
45993653 UKK |
503 | /* Set maximum receive buffer size. */ |
504 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 505 | |
14109a59 FL |
506 | fec_enet_bd_init(ndev); |
507 | ||
45993653 UKK |
508 | /* Set receive and transmit descriptor base. */ |
509 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
ff43da86 FL |
510 | if (fep->bufdesc_ex) |
511 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) | |
512 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
513 | else | |
514 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) | |
515 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
45993653 | 516 | |
45993653 | 517 | |
45993653 UKK |
518 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
519 | if (fep->tx_skbuff[i]) { | |
520 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
521 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 522 | } |
45993653 | 523 | } |
97b72e43 | 524 | |
45993653 UKK |
525 | /* Enable MII mode */ |
526 | if (duplex) { | |
cd1f402c | 527 | /* FD enable */ |
45993653 UKK |
528 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
529 | } else { | |
cd1f402c UKK |
530 | /* No Rcv on Xmit */ |
531 | rcntl |= 0x02; | |
45993653 UKK |
532 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
533 | } | |
cd1f402c | 534 | |
45993653 UKK |
535 | fep->full_duplex = duplex; |
536 | ||
537 | /* Set MII speed */ | |
538 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
539 | ||
d1391930 | 540 | #if !defined(CONFIG_M5272) |
4c09eed9 JB |
541 | /* set RX checksum */ |
542 | val = readl(fep->hwp + FEC_RACC); | |
543 | if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) | |
544 | val |= FEC_RACC_OPTIONS; | |
545 | else | |
546 | val &= ~FEC_RACC_OPTIONS; | |
547 | writel(val, fep->hwp + FEC_RACC); | |
d1391930 | 548 | #endif |
4c09eed9 | 549 | |
45993653 UKK |
550 | /* |
551 | * The phy interface and speed need to get configured | |
552 | * differently on enet-mac. | |
553 | */ | |
554 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
555 | /* Enable flow control and length check */ |
556 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 557 | |
230dec61 SG |
558 | /* RGMII, RMII or MII */ |
559 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
560 | rcntl |= (1 << 6); | |
561 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 562 | rcntl |= (1 << 8); |
45993653 | 563 | else |
cd1f402c | 564 | rcntl &= ~(1 << 8); |
45993653 | 565 | |
230dec61 SG |
566 | /* 1G, 100M or 10M */ |
567 | if (fep->phy_dev) { | |
568 | if (fep->phy_dev->speed == SPEED_1000) | |
569 | ecntl |= (1 << 5); | |
570 | else if (fep->phy_dev->speed == SPEED_100) | |
571 | rcntl &= ~(1 << 9); | |
572 | else | |
573 | rcntl |= (1 << 9); | |
574 | } | |
45993653 UKK |
575 | } else { |
576 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 577 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 578 | u32 cfgr; |
45993653 UKK |
579 | /* disable the gasket and wait */ |
580 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
581 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
582 | udelay(1); | |
583 | ||
584 | /* | |
585 | * configure the gasket: | |
586 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 587 | * MII, 25 MHz, no loopback, no echo |
45993653 | 588 | */ |
8d82f219 EB |
589 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
590 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
591 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
592 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
593 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
594 | |
595 | /* re-enable the gasket */ | |
596 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 597 | } |
45993653 UKK |
598 | #endif |
599 | } | |
baa70a5c | 600 | |
d1391930 | 601 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
602 | /* enable pause frame*/ |
603 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
604 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
605 | fep->phy_dev && fep->phy_dev->pause)) { | |
606 | rcntl |= FEC_ENET_FCE; | |
607 | ||
4c09eed9 | 608 | /* set FIFO threshold parameter to reduce overrun */ |
baa70a5c FL |
609 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); |
610 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
611 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
612 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
613 | ||
614 | /* OPD */ | |
615 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
616 | } else { | |
617 | rcntl &= ~FEC_ENET_FCE; | |
618 | } | |
d1391930 | 619 | #endif /* !defined(CONFIG_M5272) */ |
baa70a5c | 620 | |
cd1f402c | 621 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 622 | |
230dec61 SG |
623 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
624 | /* enable ENET endian swap */ | |
625 | ecntl |= (1 << 8); | |
626 | /* enable ENET store and forward mode */ | |
627 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
628 | } | |
629 | ||
ff43da86 FL |
630 | if (fep->bufdesc_ex) |
631 | ecntl |= (1 << 4); | |
6605b730 | 632 | |
38ae92dc | 633 | #ifndef CONFIG_M5272 |
b9eef55c JB |
634 | /* Enable the MIB statistic event counters */ |
635 | writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); | |
38ae92dc CH |
636 | #endif |
637 | ||
45993653 | 638 | /* And last, enable the transmit and receive processing */ |
230dec61 | 639 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
640 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
641 | ||
ff43da86 FL |
642 | if (fep->bufdesc_ex) |
643 | fec_ptp_start_cyclecounter(ndev); | |
644 | ||
45993653 UKK |
645 | /* Enable interrupts we wish to service */ |
646 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
54309fa6 FL |
647 | |
648 | if (netif_running(ndev)) { | |
31691344 | 649 | netif_tx_unlock_bh(ndev); |
54309fa6 | 650 | netif_wake_queue(ndev); |
1ed0d56c FE |
651 | napi_enable(&fep->napi); |
652 | netif_device_attach(ndev); | |
54309fa6 | 653 | } |
45993653 UKK |
654 | } |
655 | ||
656 | static void | |
657 | fec_stop(struct net_device *ndev) | |
658 | { | |
659 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
660 | const struct platform_device_id *id_entry = |
661 | platform_get_device_id(fep->pdev); | |
42431dc2 | 662 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
663 | |
664 | /* We cannot expect a graceful transmit stop without link !!! */ | |
665 | if (fep->link) { | |
666 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
667 | udelay(10); | |
668 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
31b7720c | 669 | netdev_err(ndev, "Graceful transmit stop did not complete!\n"); |
45993653 UKK |
670 | } |
671 | ||
672 | /* Whack a reset. We should wait for this. */ | |
673 | writel(1, fep->hwp + FEC_ECNTRL); | |
674 | udelay(10); | |
675 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
676 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
677 | |
678 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 679 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 680 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
681 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
682 | } | |
1da177e4 LT |
683 | } |
684 | ||
685 | ||
45993653 UKK |
686 | static void |
687 | fec_timeout(struct net_device *ndev) | |
688 | { | |
689 | struct fec_enet_private *fep = netdev_priv(ndev); | |
690 | ||
691 | ndev->stats.tx_errors++; | |
692 | ||
54309fa6 FL |
693 | fep->delay_work.timeout = true; |
694 | schedule_delayed_work(&(fep->delay_work.delay_work), 0); | |
695 | } | |
696 | ||
697 | static void fec_enet_work(struct work_struct *work) | |
698 | { | |
699 | struct fec_enet_private *fep = | |
700 | container_of(work, | |
701 | struct fec_enet_private, | |
702 | delay_work.delay_work.work); | |
703 | ||
704 | if (fep->delay_work.timeout) { | |
705 | fep->delay_work.timeout = false; | |
706 | fec_restart(fep->netdev, fep->full_duplex); | |
707 | netif_wake_queue(fep->netdev); | |
708 | } | |
03191656 FL |
709 | |
710 | if (fep->delay_work.trig_tx) { | |
711 | fep->delay_work.trig_tx = false; | |
712 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
713 | } | |
45993653 UKK |
714 | } |
715 | ||
1da177e4 | 716 | static void |
c556167f | 717 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
718 | { |
719 | struct fec_enet_private *fep; | |
2e28532f | 720 | struct bufdesc *bdp; |
0e702ab3 | 721 | unsigned short status; |
1da177e4 | 722 | struct sk_buff *skb; |
de5fb0a0 | 723 | int index = 0; |
1da177e4 | 724 | |
c556167f | 725 | fep = netdev_priv(ndev); |
1da177e4 LT |
726 | bdp = fep->dirty_tx; |
727 | ||
de5fb0a0 FL |
728 | /* get next bdp of dirty_tx */ |
729 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
730 | bdp = fep->tx_bd_base; | |
731 | else | |
732 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
733 | ||
0e702ab3 | 734 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
de5fb0a0 FL |
735 | |
736 | /* current queue is empty */ | |
737 | if (bdp == fep->cur_tx) | |
f0b3fbea SH |
738 | break; |
739 | ||
de5fb0a0 FL |
740 | if (fep->bufdesc_ex) |
741 | index = (struct bufdesc_ex *)bdp - | |
742 | (struct bufdesc_ex *)fep->tx_bd_base; | |
743 | else | |
744 | index = bdp - fep->tx_bd_base; | |
745 | ||
d1ab1f54 UKK |
746 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
747 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 748 | bdp->cbd_bufaddr = 0; |
1da177e4 | 749 | |
de5fb0a0 FL |
750 | skb = fep->tx_skbuff[index]; |
751 | ||
1da177e4 | 752 | /* Check for errors. */ |
0e702ab3 | 753 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
754 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
755 | BD_ENET_TX_CSL)) { | |
c556167f | 756 | ndev->stats.tx_errors++; |
0e702ab3 | 757 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 758 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 759 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 760 | ndev->stats.tx_window_errors++; |
0e702ab3 | 761 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 762 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 763 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 764 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 765 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 766 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 767 | } else { |
c556167f | 768 | ndev->stats.tx_packets++; |
06efce71 | 769 | ndev->stats.tx_bytes += bdp->cbd_datlen; |
1da177e4 LT |
770 | } |
771 | ||
ff43da86 FL |
772 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
773 | fep->bufdesc_ex) { | |
6605b730 FL |
774 | struct skb_shared_hwtstamps shhwtstamps; |
775 | unsigned long flags; | |
ff43da86 | 776 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 FL |
777 | |
778 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
779 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
780 | shhwtstamps.hwtstamp = ns_to_ktime( | |
ff43da86 | 781 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
782 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
783 | skb_tstamp_tx(skb, &shhwtstamps); | |
784 | } | |
ff43da86 | 785 | |
0e702ab3 | 786 | if (status & BD_ENET_TX_READY) |
31b7720c | 787 | netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); |
22f6b860 | 788 | |
1da177e4 LT |
789 | /* Deferred means some collisions occurred during transmit, |
790 | * but we eventually sent the packet OK. | |
791 | */ | |
0e702ab3 | 792 | if (status & BD_ENET_TX_DEF) |
c556167f | 793 | ndev->stats.collisions++; |
6aa20a22 | 794 | |
22f6b860 | 795 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 796 | dev_kfree_skb_any(skb); |
de5fb0a0 FL |
797 | fep->tx_skbuff[index] = NULL; |
798 | ||
799 | fep->dirty_tx = bdp; | |
6aa20a22 | 800 | |
22f6b860 | 801 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 802 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
803 | bdp = fep->tx_bd_base; |
804 | else | |
ff43da86 | 805 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
6aa20a22 | 806 | |
22f6b860 | 807 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 808 | */ |
de5fb0a0 | 809 | if (fep->dirty_tx != fep->cur_tx) { |
c556167f UKK |
810 | if (netif_queue_stopped(ndev)) |
811 | netif_wake_queue(ndev); | |
1da177e4 LT |
812 | } |
813 | } | |
de5fb0a0 | 814 | return; |
1da177e4 LT |
815 | } |
816 | ||
817 | ||
818 | /* During a receive, the cur_rx points to the current incoming buffer. | |
819 | * When we update through the ring, if the next incoming buffer has | |
820 | * not been given to the system, we just set the empty indicator, | |
821 | * effectively tossing the packet. | |
822 | */ | |
dc975382 FL |
823 | static int |
824 | fec_enet_rx(struct net_device *ndev, int budget) | |
1da177e4 | 825 | { |
c556167f | 826 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
827 | const struct platform_device_id *id_entry = |
828 | platform_get_device_id(fep->pdev); | |
2e28532f | 829 | struct bufdesc *bdp; |
0e702ab3 | 830 | unsigned short status; |
1da177e4 LT |
831 | struct sk_buff *skb; |
832 | ushort pkt_len; | |
833 | __u8 *data; | |
dc975382 | 834 | int pkt_received = 0; |
cdffcf1b JB |
835 | struct bufdesc_ex *ebdp = NULL; |
836 | bool vlan_packet_rcvd = false; | |
837 | u16 vlan_tag; | |
6aa20a22 | 838 | |
0e702ab3 GU |
839 | #ifdef CONFIG_M532x |
840 | flush_cache_all(); | |
6aa20a22 | 841 | #endif |
1da177e4 | 842 | |
1da177e4 LT |
843 | /* First, grab all of the stats for the incoming packet. |
844 | * These get messed up if we get called due to a busy condition. | |
845 | */ | |
846 | bdp = fep->cur_rx; | |
847 | ||
22f6b860 | 848 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 849 | |
dc975382 FL |
850 | if (pkt_received >= budget) |
851 | break; | |
852 | pkt_received++; | |
853 | ||
22f6b860 SH |
854 | /* Since we have allocated space to hold a complete frame, |
855 | * the last indicator should be set. | |
856 | */ | |
857 | if ((status & BD_ENET_RX_LAST) == 0) | |
31b7720c | 858 | netdev_err(ndev, "rcv is not +last\n"); |
1da177e4 | 859 | |
22f6b860 SH |
860 | if (!fep->opened) |
861 | goto rx_processing_done; | |
1da177e4 | 862 | |
22f6b860 SH |
863 | /* Check for errors. */ |
864 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 865 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 866 | ndev->stats.rx_errors++; |
22f6b860 SH |
867 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
868 | /* Frame too long or too short. */ | |
c556167f | 869 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
870 | } |
871 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 872 | ndev->stats.rx_frame_errors++; |
22f6b860 | 873 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 874 | ndev->stats.rx_crc_errors++; |
22f6b860 | 875 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 876 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 877 | } |
1da177e4 | 878 | |
22f6b860 SH |
879 | /* Report late collisions as a frame error. |
880 | * On this error, the BD is closed, but we don't know what we | |
881 | * have in the buffer. So, just drop this frame on the floor. | |
882 | */ | |
883 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
884 | ndev->stats.rx_errors++; |
885 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
886 | goto rx_processing_done; |
887 | } | |
1da177e4 | 888 | |
22f6b860 | 889 | /* Process the incoming frame. */ |
c556167f | 890 | ndev->stats.rx_packets++; |
22f6b860 | 891 | pkt_len = bdp->cbd_datlen; |
c556167f | 892 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 893 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 894 | |
d1ab1f54 UKK |
895 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
896 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 897 | |
b5680e0b SG |
898 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
899 | swap_buffer(data, pkt_len); | |
900 | ||
cdffcf1b JB |
901 | /* Extract the enhanced buffer descriptor */ |
902 | ebdp = NULL; | |
903 | if (fep->bufdesc_ex) | |
904 | ebdp = (struct bufdesc_ex *)bdp; | |
905 | ||
906 | /* If this is a VLAN packet remove the VLAN Tag */ | |
907 | vlan_packet_rcvd = false; | |
908 | if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
909 | fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { | |
910 | /* Push and remove the vlan tag */ | |
911 | struct vlan_hdr *vlan_header = | |
912 | (struct vlan_hdr *) (data + ETH_HLEN); | |
913 | vlan_tag = ntohs(vlan_header->h_vlan_TCI); | |
914 | pkt_len -= VLAN_HLEN; | |
915 | ||
916 | vlan_packet_rcvd = true; | |
917 | } | |
918 | ||
22f6b860 SH |
919 | /* This does 16 byte alignment, exactly what we need. |
920 | * The packet length includes FCS, but we don't want to | |
921 | * include that when passing upstream as it messes up | |
922 | * bridging applications. | |
923 | */ | |
b72061a3 | 924 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 925 | |
8549889c | 926 | if (unlikely(!skb)) { |
c556167f | 927 | ndev->stats.rx_dropped++; |
22f6b860 | 928 | } else { |
cdffcf1b | 929 | int payload_offset = (2 * ETH_ALEN); |
8549889c | 930 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 | 931 | skb_put(skb, pkt_len - 4); /* Make room */ |
cdffcf1b JB |
932 | |
933 | /* Extract the frame data without the VLAN header. */ | |
934 | skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); | |
935 | if (vlan_packet_rcvd) | |
936 | payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; | |
937 | skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), | |
938 | data + payload_offset, | |
939 | pkt_len - 4 - (2 * ETH_ALEN)); | |
940 | ||
c556167f | 941 | skb->protocol = eth_type_trans(skb, ndev); |
ff43da86 | 942 | |
6605b730 | 943 | /* Get receive timestamp from the skb */ |
ff43da86 | 944 | if (fep->hwts_rx_en && fep->bufdesc_ex) { |
6605b730 FL |
945 | struct skb_shared_hwtstamps *shhwtstamps = |
946 | skb_hwtstamps(skb); | |
947 | unsigned long flags; | |
948 | ||
949 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
950 | ||
951 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
952 | shhwtstamps->hwtstamp = ns_to_ktime( | |
ff43da86 | 953 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
954 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
955 | } | |
ff43da86 | 956 | |
4c09eed9 | 957 | if (fep->bufdesc_ex && |
cdffcf1b | 958 | (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { |
4c09eed9 JB |
959 | if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { |
960 | /* don't check it */ | |
961 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
962 | } else { | |
963 | skb_checksum_none_assert(skb); | |
964 | } | |
965 | } | |
966 | ||
cdffcf1b JB |
967 | /* Handle received VLAN packets */ |
968 | if (vlan_packet_rcvd) | |
969 | __vlan_hwaccel_put_tag(skb, | |
970 | htons(ETH_P_8021Q), | |
971 | vlan_tag); | |
972 | ||
18a03b97 | 973 | if (!skb_defer_rx_timestamp(skb)) |
dc975382 | 974 | napi_gro_receive(&fep->napi, skb); |
22f6b860 | 975 | } |
f0b3fbea | 976 | |
d1ab1f54 UKK |
977 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
978 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
979 | rx_processing_done: |
980 | /* Clear the status flags for this buffer */ | |
981 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 982 | |
22f6b860 SH |
983 | /* Mark the buffer empty */ |
984 | status |= BD_ENET_RX_EMPTY; | |
985 | bdp->cbd_sc = status; | |
6aa20a22 | 986 | |
ff43da86 FL |
987 | if (fep->bufdesc_ex) { |
988 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
989 | ||
990 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
991 | ebdp->cbd_prot = 0; | |
992 | ebdp->cbd_bdu = 0; | |
993 | } | |
6605b730 | 994 | |
22f6b860 SH |
995 | /* Update BD pointer to next entry */ |
996 | if (status & BD_ENET_RX_WRAP) | |
997 | bdp = fep->rx_bd_base; | |
998 | else | |
ff43da86 | 999 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
22f6b860 SH |
1000 | /* Doing this here will keep the FEC running while we process |
1001 | * incoming frames. On a heavily loaded network, we should be | |
1002 | * able to keep up at the expense of system resources. | |
1003 | */ | |
1004 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
1005 | } | |
2e28532f | 1006 | fep->cur_rx = bdp; |
1da177e4 | 1007 | |
dc975382 | 1008 | return pkt_received; |
1da177e4 LT |
1009 | } |
1010 | ||
45993653 UKK |
1011 | static irqreturn_t |
1012 | fec_enet_interrupt(int irq, void *dev_id) | |
1013 | { | |
1014 | struct net_device *ndev = dev_id; | |
1015 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1016 | uint int_events; | |
1017 | irqreturn_t ret = IRQ_NONE; | |
1018 | ||
1019 | do { | |
1020 | int_events = readl(fep->hwp + FEC_IEVENT); | |
1021 | writel(int_events, fep->hwp + FEC_IEVENT); | |
1022 | ||
de5fb0a0 | 1023 | if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { |
45993653 | 1024 | ret = IRQ_HANDLED; |
dc975382 FL |
1025 | |
1026 | /* Disable the RX interrupt */ | |
1027 | if (napi_schedule_prep(&fep->napi)) { | |
1028 | writel(FEC_RX_DISABLED_IMASK, | |
1029 | fep->hwp + FEC_IMASK); | |
1030 | __napi_schedule(&fep->napi); | |
1031 | } | |
45993653 UKK |
1032 | } |
1033 | ||
45993653 UKK |
1034 | if (int_events & FEC_ENET_MII) { |
1035 | ret = IRQ_HANDLED; | |
1036 | complete(&fep->mdio_done); | |
1037 | } | |
1038 | } while (int_events); | |
1039 | ||
1040 | return ret; | |
1041 | } | |
1042 | ||
dc975382 FL |
1043 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
1044 | { | |
1045 | struct net_device *ndev = napi->dev; | |
1046 | int pkts = fec_enet_rx(ndev, budget); | |
1047 | struct fec_enet_private *fep = netdev_priv(ndev); | |
45993653 | 1048 | |
de5fb0a0 FL |
1049 | fec_enet_tx(ndev); |
1050 | ||
dc975382 FL |
1051 | if (pkts < budget) { |
1052 | napi_complete(napi); | |
1053 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
1054 | } | |
1055 | return pkts; | |
1056 | } | |
45993653 | 1057 | |
e6b043d5 | 1058 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 1059 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 1060 | { |
c556167f | 1061 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 1062 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 1063 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 1064 | |
49da97dc SG |
1065 | /* |
1066 | * try to get mac address in following order: | |
1067 | * | |
1068 | * 1) module parameter via kernel command line in form | |
1069 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
1070 | */ | |
1071 | iap = macaddr; | |
1072 | ||
ca2cc333 SG |
1073 | /* |
1074 | * 2) from device tree data | |
1075 | */ | |
1076 | if (!is_valid_ether_addr(iap)) { | |
1077 | struct device_node *np = fep->pdev->dev.of_node; | |
1078 | if (np) { | |
1079 | const char *mac = of_get_mac_address(np); | |
1080 | if (mac) | |
1081 | iap = (unsigned char *) mac; | |
1082 | } | |
1083 | } | |
ca2cc333 | 1084 | |
49da97dc | 1085 | /* |
ca2cc333 | 1086 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
1087 | */ |
1088 | if (!is_valid_ether_addr(iap)) { | |
1089 | #ifdef CONFIG_M5272 | |
1090 | if (FEC_FLASHMAC) | |
1091 | iap = (unsigned char *)FEC_FLASHMAC; | |
1092 | #else | |
1093 | if (pdata) | |
589efdc7 | 1094 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
1095 | #endif |
1096 | } | |
1097 | ||
1098 | /* | |
ca2cc333 | 1099 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
1100 | */ |
1101 | if (!is_valid_ether_addr(iap)) { | |
1102 | *((unsigned long *) &tmpaddr[0]) = | |
1103 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
1104 | *((unsigned short *) &tmpaddr[4]) = | |
1105 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 1106 | iap = &tmpaddr[0]; |
1da177e4 LT |
1107 | } |
1108 | ||
ff5b2fab LS |
1109 | /* |
1110 | * 5) random mac address | |
1111 | */ | |
1112 | if (!is_valid_ether_addr(iap)) { | |
1113 | /* Report it and use a random ethernet address instead */ | |
1114 | netdev_err(ndev, "Invalid MAC address: %pM\n", iap); | |
1115 | eth_hw_addr_random(ndev); | |
1116 | netdev_info(ndev, "Using random MAC address: %pM\n", | |
1117 | ndev->dev_addr); | |
1118 | return; | |
1119 | } | |
1120 | ||
c556167f | 1121 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 1122 | |
49da97dc SG |
1123 | /* Adjust MAC if using macaddr */ |
1124 | if (iap == macaddr) | |
43af940c | 1125 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
1126 | } |
1127 | ||
e6b043d5 | 1128 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 1129 | |
e6b043d5 BW |
1130 | /* |
1131 | * Phy section | |
1132 | */ | |
c556167f | 1133 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 1134 | { |
c556167f | 1135 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1136 | struct phy_device *phy_dev = fep->phy_dev; |
e6b043d5 | 1137 | int status_change = 0; |
1da177e4 | 1138 | |
e6b043d5 BW |
1139 | /* Prevent a state halted on mii error */ |
1140 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
1141 | phy_dev->state = PHY_RESUMING; | |
54309fa6 | 1142 | return; |
e6b043d5 | 1143 | } |
1da177e4 | 1144 | |
e6b043d5 | 1145 | if (phy_dev->link) { |
d97e7497 | 1146 | if (!fep->link) { |
6ea0722f | 1147 | fep->link = phy_dev->link; |
e6b043d5 BW |
1148 | status_change = 1; |
1149 | } | |
1da177e4 | 1150 | |
d97e7497 LS |
1151 | if (fep->full_duplex != phy_dev->duplex) |
1152 | status_change = 1; | |
1153 | ||
1154 | if (phy_dev->speed != fep->speed) { | |
1155 | fep->speed = phy_dev->speed; | |
1156 | status_change = 1; | |
1157 | } | |
1158 | ||
1159 | /* if any of the above changed restart the FEC */ | |
1160 | if (status_change) | |
c556167f | 1161 | fec_restart(ndev, phy_dev->duplex); |
d97e7497 LS |
1162 | } else { |
1163 | if (fep->link) { | |
c556167f | 1164 | fec_stop(ndev); |
8d7ed0f0 | 1165 | fep->link = phy_dev->link; |
d97e7497 LS |
1166 | status_change = 1; |
1167 | } | |
1da177e4 | 1168 | } |
6aa20a22 | 1169 | |
e6b043d5 BW |
1170 | if (status_change) |
1171 | phy_print_status(phy_dev); | |
1172 | } | |
1da177e4 | 1173 | |
e6b043d5 | 1174 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 1175 | { |
e6b043d5 | 1176 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1177 | unsigned long time_left; |
1da177e4 | 1178 | |
e6b043d5 | 1179 | fep->mii_timeout = 0; |
97b72e43 | 1180 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
1181 | |
1182 | /* start a read op */ | |
1183 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
1184 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
1185 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
1186 | ||
1187 | /* wait for end of transfer */ | |
97b72e43 BS |
1188 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1189 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1190 | if (time_left == 0) { | |
1191 | fep->mii_timeout = 1; | |
31b7720c | 1192 | netdev_err(fep->netdev, "MDIO read timeout\n"); |
97b72e43 | 1193 | return -ETIMEDOUT; |
1da177e4 | 1194 | } |
1da177e4 | 1195 | |
e6b043d5 BW |
1196 | /* return value */ |
1197 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 1198 | } |
6aa20a22 | 1199 | |
e6b043d5 BW |
1200 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
1201 | u16 value) | |
1da177e4 | 1202 | { |
e6b043d5 | 1203 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1204 | unsigned long time_left; |
1da177e4 | 1205 | |
e6b043d5 | 1206 | fep->mii_timeout = 0; |
97b72e43 | 1207 | init_completion(&fep->mdio_done); |
1da177e4 | 1208 | |
862f0982 SG |
1209 | /* start a write op */ |
1210 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1211 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1212 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1213 | fep->hwp + FEC_MII_DATA); | |
1214 | ||
1215 | /* wait for end of transfer */ | |
97b72e43 BS |
1216 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1217 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1218 | if (time_left == 0) { | |
1219 | fep->mii_timeout = 1; | |
31b7720c | 1220 | netdev_err(fep->netdev, "MDIO write timeout\n"); |
97b72e43 | 1221 | return -ETIMEDOUT; |
e6b043d5 | 1222 | } |
1da177e4 | 1223 | |
e6b043d5 BW |
1224 | return 0; |
1225 | } | |
1da177e4 | 1226 | |
e6b043d5 | 1227 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 1228 | { |
e6b043d5 | 1229 | return 0; |
1da177e4 LT |
1230 | } |
1231 | ||
c556167f | 1232 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1233 | { |
c556167f | 1234 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
1235 | const struct platform_device_id *id_entry = |
1236 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1237 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1238 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1239 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1240 | int phy_id; | |
43af940c | 1241 | int dev_id = fep->dev_id; |
562d2f8c | 1242 | |
418bd0d4 BW |
1243 | fep->phy_dev = NULL; |
1244 | ||
6fcc040f GU |
1245 | /* check for attached phy */ |
1246 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
1247 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
1248 | continue; | |
1249 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
1250 | continue; | |
1251 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
1252 | continue; | |
b5680e0b SG |
1253 | if (dev_id--) |
1254 | continue; | |
6fcc040f GU |
1255 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
1256 | break; | |
e6b043d5 | 1257 | } |
1da177e4 | 1258 | |
6fcc040f | 1259 | if (phy_id >= PHY_MAX_ADDR) { |
31b7720c | 1260 | netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); |
ea51ade9 | 1261 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
1262 | phy_id = 0; |
1263 | } | |
1264 | ||
a7ed07d5 | 1265 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
f9a8f83b | 1266 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
230dec61 | 1267 | fep->phy_interface); |
6fcc040f | 1268 | if (IS_ERR(phy_dev)) { |
31b7720c | 1269 | netdev_err(ndev, "could not attach to PHY\n"); |
6fcc040f | 1270 | return PTR_ERR(phy_dev); |
e6b043d5 | 1271 | } |
1da177e4 | 1272 | |
e6b043d5 | 1273 | /* mask with MAC supported features */ |
baa70a5c | 1274 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1275 | phy_dev->supported &= PHY_GBIT_FEATURES; |
d1391930 | 1276 | #if !defined(CONFIG_M5272) |
baa70a5c | 1277 | phy_dev->supported |= SUPPORTED_Pause; |
d1391930 | 1278 | #endif |
baa70a5c | 1279 | } |
230dec61 SG |
1280 | else |
1281 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1282 | ||
e6b043d5 | 1283 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1284 | |
e6b043d5 BW |
1285 | fep->phy_dev = phy_dev; |
1286 | fep->link = 0; | |
1287 | fep->full_duplex = 0; | |
1da177e4 | 1288 | |
31b7720c JP |
1289 | netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1290 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
1291 | fep->phy_dev->irq); | |
418bd0d4 | 1292 | |
e6b043d5 | 1293 | return 0; |
1da177e4 LT |
1294 | } |
1295 | ||
e6b043d5 | 1296 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1297 | { |
b5680e0b | 1298 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1299 | struct net_device *ndev = platform_get_drvdata(pdev); |
1300 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1301 | const struct platform_device_id *id_entry = |
1302 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1303 | int err = -ENXIO, i; |
6b265293 | 1304 | |
b5680e0b SG |
1305 | /* |
1306 | * The dual fec interfaces are not equivalent with enet-mac. | |
1307 | * Here are the differences: | |
1308 | * | |
1309 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1310 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1311 | * - external phys can only be configured by fec0 | |
1312 | * | |
1313 | * That is to say fec1 can not work independently. It only works | |
1314 | * when fec0 is working. The reason behind this design is that the | |
1315 | * second interface is added primarily for Switch mode. | |
1316 | * | |
1317 | * Because of the last point above, both phys are attached on fec0 | |
1318 | * mdio interface in board design, and need to be configured by | |
1319 | * fec0 mii_bus. | |
1320 | */ | |
43af940c | 1321 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1322 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1323 | if (mii_cnt && fec0_mii_bus) { |
1324 | fep->mii_bus = fec0_mii_bus; | |
1325 | mii_cnt++; | |
1326 | return 0; | |
1327 | } | |
1328 | return -ENOENT; | |
b5680e0b SG |
1329 | } |
1330 | ||
e6b043d5 | 1331 | fep->mii_timeout = 0; |
1da177e4 | 1332 | |
e6b043d5 BW |
1333 | /* |
1334 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1335 | * |
1336 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1337 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1338 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1339 | * document. | |
e6b043d5 | 1340 | */ |
f4d40de3 | 1341 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1342 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1343 | fep->phy_speed--; | |
1344 | fep->phy_speed <<= 1; | |
e6b043d5 | 1345 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1346 | |
e6b043d5 BW |
1347 | fep->mii_bus = mdiobus_alloc(); |
1348 | if (fep->mii_bus == NULL) { | |
1349 | err = -ENOMEM; | |
1350 | goto err_out; | |
1da177e4 LT |
1351 | } |
1352 | ||
e6b043d5 BW |
1353 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1354 | fep->mii_bus->read = fec_enet_mdio_read; | |
1355 | fep->mii_bus->write = fec_enet_mdio_write; | |
1356 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1357 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1358 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1359 | fep->mii_bus->priv = fep; |
1360 | fep->mii_bus->parent = &pdev->dev; | |
1361 | ||
1362 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1363 | if (!fep->mii_bus->irq) { | |
1364 | err = -ENOMEM; | |
1365 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1366 | } |
1367 | ||
e6b043d5 BW |
1368 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1369 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1370 | |
e6b043d5 BW |
1371 | if (mdiobus_register(fep->mii_bus)) |
1372 | goto err_out_free_mdio_irq; | |
1da177e4 | 1373 | |
e163cc97 LW |
1374 | mii_cnt++; |
1375 | ||
b5680e0b SG |
1376 | /* save fec0 mii_bus */ |
1377 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1378 | fec0_mii_bus = fep->mii_bus; | |
1379 | ||
e6b043d5 | 1380 | return 0; |
1da177e4 | 1381 | |
e6b043d5 BW |
1382 | err_out_free_mdio_irq: |
1383 | kfree(fep->mii_bus->irq); | |
1384 | err_out_free_mdiobus: | |
1385 | mdiobus_free(fep->mii_bus); | |
1386 | err_out: | |
1387 | return err; | |
1da177e4 LT |
1388 | } |
1389 | ||
e6b043d5 | 1390 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1391 | { |
e163cc97 LW |
1392 | if (--mii_cnt == 0) { |
1393 | mdiobus_unregister(fep->mii_bus); | |
1394 | kfree(fep->mii_bus->irq); | |
1395 | mdiobus_free(fep->mii_bus); | |
1396 | } | |
1da177e4 LT |
1397 | } |
1398 | ||
c556167f | 1399 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1400 | struct ethtool_cmd *cmd) |
1da177e4 | 1401 | { |
c556167f | 1402 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1403 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1404 | |
e6b043d5 BW |
1405 | if (!phydev) |
1406 | return -ENODEV; | |
1da177e4 | 1407 | |
e6b043d5 | 1408 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1409 | } |
1410 | ||
c556167f | 1411 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1412 | struct ethtool_cmd *cmd) |
1da177e4 | 1413 | { |
c556167f | 1414 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1415 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1416 | |
e6b043d5 BW |
1417 | if (!phydev) |
1418 | return -ENODEV; | |
1da177e4 | 1419 | |
e6b043d5 | 1420 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1421 | } |
1422 | ||
c556167f | 1423 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1424 | struct ethtool_drvinfo *info) |
1da177e4 | 1425 | { |
c556167f | 1426 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1427 | |
7826d43f JP |
1428 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
1429 | sizeof(info->driver)); | |
1430 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
1431 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1432 | } |
1433 | ||
5ebae489 FL |
1434 | static int fec_enet_get_ts_info(struct net_device *ndev, |
1435 | struct ethtool_ts_info *info) | |
1436 | { | |
1437 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1438 | ||
1439 | if (fep->bufdesc_ex) { | |
1440 | ||
1441 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1442 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1443 | SOF_TIMESTAMPING_SOFTWARE | | |
1444 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1445 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1446 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1447 | if (fep->ptp_clock) | |
1448 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
1449 | else | |
1450 | info->phc_index = -1; | |
1451 | ||
1452 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
1453 | (1 << HWTSTAMP_TX_ON); | |
1454 | ||
1455 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
1456 | (1 << HWTSTAMP_FILTER_ALL); | |
1457 | return 0; | |
1458 | } else { | |
1459 | return ethtool_op_get_ts_info(ndev, info); | |
1460 | } | |
1461 | } | |
1462 | ||
d1391930 GR |
1463 | #if !defined(CONFIG_M5272) |
1464 | ||
baa70a5c FL |
1465 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
1466 | struct ethtool_pauseparam *pause) | |
1467 | { | |
1468 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1469 | ||
1470 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
1471 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
1472 | pause->rx_pause = pause->tx_pause; | |
1473 | } | |
1474 | ||
1475 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
1476 | struct ethtool_pauseparam *pause) | |
1477 | { | |
1478 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1479 | ||
1480 | if (pause->tx_pause != pause->rx_pause) { | |
1481 | netdev_info(ndev, | |
1482 | "hardware only support enable/disable both tx and rx"); | |
1483 | return -EINVAL; | |
1484 | } | |
1485 | ||
1486 | fep->pause_flag = 0; | |
1487 | ||
1488 | /* tx pause must be same as rx pause */ | |
1489 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
1490 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
1491 | ||
1492 | if (pause->rx_pause || pause->autoneg) { | |
1493 | fep->phy_dev->supported |= ADVERTISED_Pause; | |
1494 | fep->phy_dev->advertising |= ADVERTISED_Pause; | |
1495 | } else { | |
1496 | fep->phy_dev->supported &= ~ADVERTISED_Pause; | |
1497 | fep->phy_dev->advertising &= ~ADVERTISED_Pause; | |
1498 | } | |
1499 | ||
1500 | if (pause->autoneg) { | |
1501 | if (netif_running(ndev)) | |
1502 | fec_stop(ndev); | |
1503 | phy_start_aneg(fep->phy_dev); | |
1504 | } | |
1505 | if (netif_running(ndev)) | |
1506 | fec_restart(ndev, 0); | |
1507 | ||
1508 | return 0; | |
1509 | } | |
1510 | ||
38ae92dc CH |
1511 | static const struct fec_stat { |
1512 | char name[ETH_GSTRING_LEN]; | |
1513 | u16 offset; | |
1514 | } fec_stats[] = { | |
1515 | /* RMON TX */ | |
1516 | { "tx_dropped", RMON_T_DROP }, | |
1517 | { "tx_packets", RMON_T_PACKETS }, | |
1518 | { "tx_broadcast", RMON_T_BC_PKT }, | |
1519 | { "tx_multicast", RMON_T_MC_PKT }, | |
1520 | { "tx_crc_errors", RMON_T_CRC_ALIGN }, | |
1521 | { "tx_undersize", RMON_T_UNDERSIZE }, | |
1522 | { "tx_oversize", RMON_T_OVERSIZE }, | |
1523 | { "tx_fragment", RMON_T_FRAG }, | |
1524 | { "tx_jabber", RMON_T_JAB }, | |
1525 | { "tx_collision", RMON_T_COL }, | |
1526 | { "tx_64byte", RMON_T_P64 }, | |
1527 | { "tx_65to127byte", RMON_T_P65TO127 }, | |
1528 | { "tx_128to255byte", RMON_T_P128TO255 }, | |
1529 | { "tx_256to511byte", RMON_T_P256TO511 }, | |
1530 | { "tx_512to1023byte", RMON_T_P512TO1023 }, | |
1531 | { "tx_1024to2047byte", RMON_T_P1024TO2047 }, | |
1532 | { "tx_GTE2048byte", RMON_T_P_GTE2048 }, | |
1533 | { "tx_octets", RMON_T_OCTETS }, | |
1534 | ||
1535 | /* IEEE TX */ | |
1536 | { "IEEE_tx_drop", IEEE_T_DROP }, | |
1537 | { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, | |
1538 | { "IEEE_tx_1col", IEEE_T_1COL }, | |
1539 | { "IEEE_tx_mcol", IEEE_T_MCOL }, | |
1540 | { "IEEE_tx_def", IEEE_T_DEF }, | |
1541 | { "IEEE_tx_lcol", IEEE_T_LCOL }, | |
1542 | { "IEEE_tx_excol", IEEE_T_EXCOL }, | |
1543 | { "IEEE_tx_macerr", IEEE_T_MACERR }, | |
1544 | { "IEEE_tx_cserr", IEEE_T_CSERR }, | |
1545 | { "IEEE_tx_sqe", IEEE_T_SQE }, | |
1546 | { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, | |
1547 | { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, | |
1548 | ||
1549 | /* RMON RX */ | |
1550 | { "rx_packets", RMON_R_PACKETS }, | |
1551 | { "rx_broadcast", RMON_R_BC_PKT }, | |
1552 | { "rx_multicast", RMON_R_MC_PKT }, | |
1553 | { "rx_crc_errors", RMON_R_CRC_ALIGN }, | |
1554 | { "rx_undersize", RMON_R_UNDERSIZE }, | |
1555 | { "rx_oversize", RMON_R_OVERSIZE }, | |
1556 | { "rx_fragment", RMON_R_FRAG }, | |
1557 | { "rx_jabber", RMON_R_JAB }, | |
1558 | { "rx_64byte", RMON_R_P64 }, | |
1559 | { "rx_65to127byte", RMON_R_P65TO127 }, | |
1560 | { "rx_128to255byte", RMON_R_P128TO255 }, | |
1561 | { "rx_256to511byte", RMON_R_P256TO511 }, | |
1562 | { "rx_512to1023byte", RMON_R_P512TO1023 }, | |
1563 | { "rx_1024to2047byte", RMON_R_P1024TO2047 }, | |
1564 | { "rx_GTE2048byte", RMON_R_P_GTE2048 }, | |
1565 | { "rx_octets", RMON_R_OCTETS }, | |
1566 | ||
1567 | /* IEEE RX */ | |
1568 | { "IEEE_rx_drop", IEEE_R_DROP }, | |
1569 | { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, | |
1570 | { "IEEE_rx_crc", IEEE_R_CRC }, | |
1571 | { "IEEE_rx_align", IEEE_R_ALIGN }, | |
1572 | { "IEEE_rx_macerr", IEEE_R_MACERR }, | |
1573 | { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, | |
1574 | { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, | |
1575 | }; | |
1576 | ||
1577 | static void fec_enet_get_ethtool_stats(struct net_device *dev, | |
1578 | struct ethtool_stats *stats, u64 *data) | |
1579 | { | |
1580 | struct fec_enet_private *fep = netdev_priv(dev); | |
1581 | int i; | |
1582 | ||
1583 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
1584 | data[i] = readl(fep->hwp + fec_stats[i].offset); | |
1585 | } | |
1586 | ||
1587 | static void fec_enet_get_strings(struct net_device *netdev, | |
1588 | u32 stringset, u8 *data) | |
1589 | { | |
1590 | int i; | |
1591 | switch (stringset) { | |
1592 | case ETH_SS_STATS: | |
1593 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
1594 | memcpy(data + i * ETH_GSTRING_LEN, | |
1595 | fec_stats[i].name, ETH_GSTRING_LEN); | |
1596 | break; | |
1597 | } | |
1598 | } | |
1599 | ||
1600 | static int fec_enet_get_sset_count(struct net_device *dev, int sset) | |
1601 | { | |
1602 | switch (sset) { | |
1603 | case ETH_SS_STATS: | |
1604 | return ARRAY_SIZE(fec_stats); | |
1605 | default: | |
1606 | return -EOPNOTSUPP; | |
1607 | } | |
1608 | } | |
d1391930 | 1609 | #endif /* !defined(CONFIG_M5272) */ |
38ae92dc | 1610 | |
32bc9b46 CH |
1611 | static int fec_enet_nway_reset(struct net_device *dev) |
1612 | { | |
1613 | struct fec_enet_private *fep = netdev_priv(dev); | |
1614 | struct phy_device *phydev = fep->phy_dev; | |
1615 | ||
1616 | if (!phydev) | |
1617 | return -ENODEV; | |
1618 | ||
1619 | return genphy_restart_aneg(phydev); | |
1620 | } | |
1621 | ||
9b07be4b | 1622 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
d1391930 | 1623 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
1624 | .get_pauseparam = fec_enet_get_pauseparam, |
1625 | .set_pauseparam = fec_enet_set_pauseparam, | |
d1391930 | 1626 | #endif |
e6b043d5 BW |
1627 | .get_settings = fec_enet_get_settings, |
1628 | .set_settings = fec_enet_set_settings, | |
1629 | .get_drvinfo = fec_enet_get_drvinfo, | |
1630 | .get_link = ethtool_op_get_link, | |
5ebae489 | 1631 | .get_ts_info = fec_enet_get_ts_info, |
32bc9b46 | 1632 | .nway_reset = fec_enet_nway_reset, |
38ae92dc CH |
1633 | #ifndef CONFIG_M5272 |
1634 | .get_ethtool_stats = fec_enet_get_ethtool_stats, | |
1635 | .get_strings = fec_enet_get_strings, | |
1636 | .get_sset_count = fec_enet_get_sset_count, | |
1637 | #endif | |
e6b043d5 | 1638 | }; |
1da177e4 | 1639 | |
c556167f | 1640 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1641 | { |
c556167f | 1642 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1643 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1644 | |
c556167f | 1645 | if (!netif_running(ndev)) |
e6b043d5 | 1646 | return -EINVAL; |
1da177e4 | 1647 | |
e6b043d5 BW |
1648 | if (!phydev) |
1649 | return -ENODEV; | |
1650 | ||
ff43da86 | 1651 | if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) |
6605b730 | 1652 | return fec_ptp_ioctl(ndev, rq, cmd); |
ff43da86 | 1653 | |
28b04113 | 1654 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1655 | } |
1656 | ||
c556167f | 1657 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1658 | { |
c556167f | 1659 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1660 | unsigned int i; |
f0b3fbea SH |
1661 | struct sk_buff *skb; |
1662 | struct bufdesc *bdp; | |
1663 | ||
1664 | bdp = fep->rx_bd_base; | |
1665 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1666 | skb = fep->rx_skbuff[i]; | |
1667 | ||
1668 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1669 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1670 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1671 | if (skb) | |
1672 | dev_kfree_skb(skb); | |
ff43da86 | 1673 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1674 | } |
1675 | ||
1676 | bdp = fep->tx_bd_base; | |
1677 | for (i = 0; i < TX_RING_SIZE; i++) | |
1678 | kfree(fep->tx_bounce[i]); | |
1679 | } | |
1680 | ||
c556167f | 1681 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1682 | { |
c556167f | 1683 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1684 | unsigned int i; |
f0b3fbea SH |
1685 | struct sk_buff *skb; |
1686 | struct bufdesc *bdp; | |
1687 | ||
1688 | bdp = fep->rx_bd_base; | |
1689 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1690 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1691 | if (!skb) { |
c556167f | 1692 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1693 | return -ENOMEM; |
1694 | } | |
1695 | fep->rx_skbuff[i] = skb; | |
1696 | ||
d1ab1f54 | 1697 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1698 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1699 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
ff43da86 FL |
1700 | |
1701 | if (fep->bufdesc_ex) { | |
1702 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1703 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1704 | } | |
1705 | ||
1706 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1707 | } |
1708 | ||
1709 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1710 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1711 | bdp->cbd_sc |= BD_SC_WRAP; |
1712 | ||
1713 | bdp = fep->tx_bd_base; | |
1714 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1715 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1716 | ||
1717 | bdp->cbd_sc = 0; | |
1718 | bdp->cbd_bufaddr = 0; | |
6605b730 | 1719 | |
ff43da86 FL |
1720 | if (fep->bufdesc_ex) { |
1721 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
96d2222b | 1722 | ebdp->cbd_esc = BD_ENET_TX_INT; |
ff43da86 FL |
1723 | } |
1724 | ||
1725 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1726 | } |
1727 | ||
1728 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1729 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1730 | bdp->cbd_sc |= BD_SC_WRAP; |
1731 | ||
1732 | return 0; | |
1733 | } | |
1734 | ||
1da177e4 | 1735 | static int |
c556167f | 1736 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1737 | { |
c556167f | 1738 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1739 | int ret; |
1da177e4 | 1740 | |
dc975382 FL |
1741 | napi_enable(&fep->napi); |
1742 | ||
1da177e4 LT |
1743 | /* I should reset the ring buffers here, but I don't yet know |
1744 | * a simple way to do that. | |
1745 | */ | |
1da177e4 | 1746 | |
c556167f | 1747 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1748 | if (ret) |
1749 | return ret; | |
1750 | ||
418bd0d4 | 1751 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1752 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1753 | if (ret) { |
c556167f | 1754 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1755 | return ret; |
1756 | } | |
e6b043d5 | 1757 | phy_start(fep->phy_dev); |
c556167f | 1758 | netif_start_queue(ndev); |
1da177e4 | 1759 | fep->opened = 1; |
22f6b860 | 1760 | return 0; |
1da177e4 LT |
1761 | } |
1762 | ||
1763 | static int | |
c556167f | 1764 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1765 | { |
c556167f | 1766 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1767 | |
22f6b860 | 1768 | /* Don't know what to do yet. */ |
3f104c38 | 1769 | napi_disable(&fep->napi); |
1da177e4 | 1770 | fep->opened = 0; |
c556167f UKK |
1771 | netif_stop_queue(ndev); |
1772 | fec_stop(ndev); | |
1da177e4 | 1773 | |
e497ba82 UKK |
1774 | if (fep->phy_dev) { |
1775 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1776 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1777 | } |
418bd0d4 | 1778 | |
db8880bc | 1779 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1780 | |
1da177e4 LT |
1781 | return 0; |
1782 | } | |
1783 | ||
1da177e4 LT |
1784 | /* Set or clear the multicast filter for this adaptor. |
1785 | * Skeleton taken from sunlance driver. | |
1786 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1787 | * MAC address filtering. Some of the drivers check to make sure it is | |
1788 | * a group multicast address, and discard those that are not. I guess I | |
1789 | * will do the same for now, but just remove the test if you want | |
1790 | * individual filtering as well (do the upper net layers want or support | |
1791 | * this kind of feature?). | |
1792 | */ | |
1793 | ||
1794 | #define HASH_BITS 6 /* #bits in hash */ | |
1795 | #define CRC32_POLY 0xEDB88320 | |
1796 | ||
c556167f | 1797 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1798 | { |
c556167f | 1799 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1800 | struct netdev_hw_addr *ha; |
48e2f183 | 1801 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1802 | unsigned char hash; |
1803 | ||
c556167f | 1804 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1805 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1806 | tmp |= 0x8; | |
1807 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1808 | return; |
1809 | } | |
1da177e4 | 1810 | |
4e831836 SH |
1811 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1812 | tmp &= ~0x8; | |
1813 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1814 | ||
c556167f | 1815 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1816 | /* Catch all multicast addresses, so set the |
1817 | * filter to all 1's | |
1818 | */ | |
1819 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1820 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1821 | ||
1822 | return; | |
1823 | } | |
1824 | ||
1825 | /* Clear filter and add the addresses in hash register | |
1826 | */ | |
1827 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1828 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1829 | ||
c556167f | 1830 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1831 | /* calculate crc32 value of mac address */ |
1832 | crc = 0xffffffff; | |
1833 | ||
c556167f | 1834 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1835 | data = ha->addr[i]; |
4e831836 SH |
1836 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1837 | crc = (crc >> 1) ^ | |
1838 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1839 | } |
1840 | } | |
4e831836 SH |
1841 | |
1842 | /* only upper 6 bits (HASH_BITS) are used | |
1843 | * which point to specific bit in he hash registers | |
1844 | */ | |
1845 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1846 | ||
1847 | if (hash > 31) { | |
1848 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1849 | tmp |= 1 << (hash - 32); | |
1850 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1851 | } else { | |
1852 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1853 | tmp |= 1 << hash; | |
1854 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1855 | } | |
1da177e4 LT |
1856 | } |
1857 | } | |
1858 | ||
22f6b860 | 1859 | /* Set a MAC change in hardware. */ |
009fda83 | 1860 | static int |
c556167f | 1861 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1862 | { |
c556167f | 1863 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1864 | struct sockaddr *addr = p; |
1865 | ||
1866 | if (!is_valid_ether_addr(addr->sa_data)) | |
1867 | return -EADDRNOTAVAIL; | |
1868 | ||
c556167f | 1869 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1870 | |
c556167f UKK |
1871 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1872 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1873 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1874 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1875 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1876 | return 0; |
1da177e4 LT |
1877 | } |
1878 | ||
7f5c6add | 1879 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1880 | /** |
1881 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1882 | * @dev: The FEC network adapter |
1883 | * | |
1884 | * Polled functionality used by netconsole and others in non interrupt mode | |
1885 | * | |
1886 | */ | |
47a5247f | 1887 | static void fec_poll_controller(struct net_device *dev) |
7f5c6add XJ |
1888 | { |
1889 | int i; | |
1890 | struct fec_enet_private *fep = netdev_priv(dev); | |
1891 | ||
1892 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1893 | if (fep->irq[i] > 0) { | |
1894 | disable_irq(fep->irq[i]); | |
1895 | fec_enet_interrupt(fep->irq[i], dev); | |
1896 | enable_irq(fep->irq[i]); | |
1897 | } | |
1898 | } | |
1899 | } | |
1900 | #endif | |
1901 | ||
4c09eed9 JB |
1902 | static int fec_set_features(struct net_device *netdev, |
1903 | netdev_features_t features) | |
1904 | { | |
1905 | struct fec_enet_private *fep = netdev_priv(netdev); | |
1906 | netdev_features_t changed = features ^ netdev->features; | |
1907 | ||
1908 | netdev->features = features; | |
1909 | ||
1910 | /* Receive checksum has been changed */ | |
1911 | if (changed & NETIF_F_RXCSUM) { | |
1912 | if (features & NETIF_F_RXCSUM) | |
1913 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
1914 | else | |
1915 | fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; | |
1916 | ||
1917 | if (netif_running(netdev)) { | |
1918 | fec_stop(netdev); | |
1919 | fec_restart(netdev, fep->phy_dev->duplex); | |
1920 | netif_wake_queue(netdev); | |
1921 | } else { | |
1922 | fec_restart(netdev, fep->phy_dev->duplex); | |
1923 | } | |
1924 | } | |
1925 | ||
1926 | return 0; | |
1927 | } | |
1928 | ||
009fda83 SH |
1929 | static const struct net_device_ops fec_netdev_ops = { |
1930 | .ndo_open = fec_enet_open, | |
1931 | .ndo_stop = fec_enet_close, | |
1932 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1933 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1934 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1935 | .ndo_validate_addr = eth_validate_addr, |
1936 | .ndo_tx_timeout = fec_timeout, | |
1937 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1938 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1939 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1940 | .ndo_poll_controller = fec_poll_controller, | |
1941 | #endif | |
4c09eed9 | 1942 | .ndo_set_features = fec_set_features, |
009fda83 SH |
1943 | }; |
1944 | ||
1da177e4 LT |
1945 | /* |
1946 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1947 | * |
1da177e4 | 1948 | */ |
c556167f | 1949 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1950 | { |
c556167f | 1951 | struct fec_enet_private *fep = netdev_priv(ndev); |
48496255 SG |
1952 | const struct platform_device_id *id_entry = |
1953 | platform_get_device_id(fep->pdev); | |
f0b3fbea | 1954 | struct bufdesc *cbd_base; |
1da177e4 | 1955 | |
8d4dd5cf SH |
1956 | /* Allocate memory for buffer descriptors. */ |
1957 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
d0320f75 JP |
1958 | GFP_KERNEL); |
1959 | if (!cbd_base) | |
562d2f8c | 1960 | return -ENOMEM; |
562d2f8c | 1961 | |
14109a59 | 1962 | memset(cbd_base, 0, PAGE_SIZE); |
3b2b74ca | 1963 | |
c556167f | 1964 | fep->netdev = ndev; |
1da177e4 | 1965 | |
49da97dc | 1966 | /* Get the Ethernet address */ |
c556167f | 1967 | fec_get_mac(ndev); |
1da177e4 | 1968 | |
8d4dd5cf | 1969 | /* Set receive and transmit descriptor base. */ |
1da177e4 | 1970 | fep->rx_bd_base = cbd_base; |
ff43da86 FL |
1971 | if (fep->bufdesc_ex) |
1972 | fep->tx_bd_base = (struct bufdesc *) | |
1973 | (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); | |
1974 | else | |
1975 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1da177e4 | 1976 | |
22f6b860 | 1977 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1978 | ndev->watchdog_timeo = TX_TIMEOUT; |
1979 | ndev->netdev_ops = &fec_netdev_ops; | |
1980 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 1981 | |
dc975382 | 1982 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
322555f5 | 1983 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); |
dc975382 | 1984 | |
cdffcf1b JB |
1985 | if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) { |
1986 | /* enable hw VLAN support */ | |
1987 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
1988 | ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; | |
1989 | } | |
1990 | ||
48496255 SG |
1991 | if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { |
1992 | /* enable hw accelerator */ | |
1993 | ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1994 | | NETIF_F_RXCSUM); | |
1995 | ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1996 | | NETIF_F_RXCSUM); | |
1997 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
1998 | } | |
4c09eed9 | 1999 | |
c556167f | 2000 | fec_restart(ndev, 0); |
1da177e4 | 2001 | |
1da177e4 LT |
2002 | return 0; |
2003 | } | |
2004 | ||
ca2cc333 | 2005 | #ifdef CONFIG_OF |
33897cc8 | 2006 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
2007 | { |
2008 | int err, phy_reset; | |
a3caad0a | 2009 | int msec = 1; |
ca2cc333 SG |
2010 | struct device_node *np = pdev->dev.of_node; |
2011 | ||
2012 | if (!np) | |
a9b2c8ef | 2013 | return; |
ca2cc333 | 2014 | |
a3caad0a SG |
2015 | of_property_read_u32(np, "phy-reset-duration", &msec); |
2016 | /* A sane reset duration should not be longer than 1s */ | |
2017 | if (msec > 1000) | |
2018 | msec = 1; | |
2019 | ||
ca2cc333 | 2020 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
2021 | if (!gpio_is_valid(phy_reset)) |
2022 | return; | |
2023 | ||
119fc007 SG |
2024 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
2025 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 2026 | if (err) { |
07dcf8e9 | 2027 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 2028 | return; |
ca2cc333 | 2029 | } |
a3caad0a | 2030 | msleep(msec); |
ca2cc333 | 2031 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
2032 | } |
2033 | #else /* CONFIG_OF */ | |
0c7768a0 | 2034 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
2035 | { |
2036 | /* | |
2037 | * In case of platform probe, the reset has been done | |
2038 | * by machine code. | |
2039 | */ | |
ca2cc333 SG |
2040 | } |
2041 | #endif /* CONFIG_OF */ | |
2042 | ||
33897cc8 | 2043 | static int |
ead73183 SH |
2044 | fec_probe(struct platform_device *pdev) |
2045 | { | |
2046 | struct fec_enet_private *fep; | |
5eb32bd0 | 2047 | struct fec_platform_data *pdata; |
ead73183 SH |
2048 | struct net_device *ndev; |
2049 | int i, irq, ret = 0; | |
2050 | struct resource *r; | |
ca2cc333 | 2051 | const struct of_device_id *of_id; |
43af940c | 2052 | static int dev_id; |
ca2cc333 SG |
2053 | |
2054 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
2055 | if (of_id) | |
2056 | pdev->id_entry = of_id->data; | |
ead73183 | 2057 | |
ead73183 SH |
2058 | /* Init network device */ |
2059 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
83e519b6 FE |
2060 | if (!ndev) |
2061 | return -ENOMEM; | |
ead73183 SH |
2062 | |
2063 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
2064 | ||
2065 | /* setup board info structure */ | |
2066 | fep = netdev_priv(ndev); | |
ead73183 | 2067 | |
d1391930 | 2068 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
2069 | /* default enable pause frame auto negotiation */ |
2070 | if (pdev->id_entry && | |
2071 | (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) | |
2072 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; | |
d1391930 | 2073 | #endif |
baa70a5c | 2074 | |
399db75b | 2075 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
941e173a TB |
2076 | fep->hwp = devm_ioremap_resource(&pdev->dev, r); |
2077 | if (IS_ERR(fep->hwp)) { | |
2078 | ret = PTR_ERR(fep->hwp); | |
2079 | goto failed_ioremap; | |
2080 | } | |
2081 | ||
e6b043d5 | 2082 | fep->pdev = pdev; |
43af940c | 2083 | fep->dev_id = dev_id++; |
ead73183 | 2084 | |
ff43da86 FL |
2085 | fep->bufdesc_ex = 0; |
2086 | ||
ead73183 SH |
2087 | platform_set_drvdata(pdev, ndev); |
2088 | ||
6c5f7808 | 2089 | ret = of_get_phy_mode(pdev->dev.of_node); |
ca2cc333 SG |
2090 | if (ret < 0) { |
2091 | pdata = pdev->dev.platform_data; | |
2092 | if (pdata) | |
2093 | fep->phy_interface = pdata->phy; | |
2094 | else | |
2095 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
2096 | } else { | |
2097 | fep->phy_interface = ret; | |
2098 | } | |
2099 | ||
f4d40de3 SH |
2100 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
2101 | if (IS_ERR(fep->clk_ipg)) { | |
2102 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
2103 | goto failed_clk; |
2104 | } | |
f4d40de3 SH |
2105 | |
2106 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
2107 | if (IS_ERR(fep->clk_ahb)) { | |
2108 | ret = PTR_ERR(fep->clk_ahb); | |
2109 | goto failed_clk; | |
2110 | } | |
2111 | ||
daa7d392 WS |
2112 | /* enet_out is optional, depends on board */ |
2113 | fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); | |
2114 | if (IS_ERR(fep->clk_enet_out)) | |
2115 | fep->clk_enet_out = NULL; | |
2116 | ||
6605b730 | 2117 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
e2f8d555 FE |
2118 | fep->bufdesc_ex = |
2119 | pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; | |
6605b730 | 2120 | if (IS_ERR(fep->clk_ptp)) { |
c29dc2d7 | 2121 | fep->clk_ptp = NULL; |
ff43da86 | 2122 | fep->bufdesc_ex = 0; |
6605b730 | 2123 | } |
6605b730 | 2124 | |
13a097bd FE |
2125 | ret = clk_prepare_enable(fep->clk_ahb); |
2126 | if (ret) | |
2127 | goto failed_clk; | |
2128 | ||
2129 | ret = clk_prepare_enable(fep->clk_ipg); | |
2130 | if (ret) | |
2131 | goto failed_clk_ipg; | |
2132 | ||
2133 | if (fep->clk_enet_out) { | |
2134 | ret = clk_prepare_enable(fep->clk_enet_out); | |
2135 | if (ret) | |
2136 | goto failed_clk_enet_out; | |
2137 | } | |
2138 | ||
2139 | if (fep->clk_ptp) { | |
2140 | ret = clk_prepare_enable(fep->clk_ptp); | |
2141 | if (ret) | |
2142 | goto failed_clk_ptp; | |
2143 | } | |
ff43da86 | 2144 | |
f4e9f3d2 FE |
2145 | fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
2146 | if (!IS_ERR(fep->reg_phy)) { | |
2147 | ret = regulator_enable(fep->reg_phy); | |
5fa9c0fe SG |
2148 | if (ret) { |
2149 | dev_err(&pdev->dev, | |
2150 | "Failed to enable phy regulator: %d\n", ret); | |
2151 | goto failed_regulator; | |
2152 | } | |
f6a4d607 FE |
2153 | } else { |
2154 | fep->reg_phy = NULL; | |
5fa9c0fe SG |
2155 | } |
2156 | ||
2ca9b2aa SG |
2157 | fec_reset_phy(pdev); |
2158 | ||
e2f8d555 | 2159 | if (fep->bufdesc_ex) |
ca162a82 | 2160 | fec_ptp_init(pdev); |
e2f8d555 FE |
2161 | |
2162 | ret = fec_enet_init(ndev); | |
2163 | if (ret) | |
2164 | goto failed_init; | |
2165 | ||
2166 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
2167 | irq = platform_get_irq(pdev, i); | |
2168 | if (irq < 0) { | |
2169 | if (i) | |
2170 | break; | |
2171 | ret = irq; | |
2172 | goto failed_irq; | |
2173 | } | |
0d9b2ab1 FE |
2174 | ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, |
2175 | IRQF_DISABLED, pdev->name, ndev); | |
2176 | if (ret) | |
e2f8d555 | 2177 | goto failed_irq; |
e2f8d555 FE |
2178 | } |
2179 | ||
e6b043d5 BW |
2180 | ret = fec_enet_mii_init(pdev); |
2181 | if (ret) | |
2182 | goto failed_mii_init; | |
2183 | ||
03c698c9 OS |
2184 | /* Carrier starts down, phylib will bring it up */ |
2185 | netif_carrier_off(ndev); | |
2186 | ||
ead73183 SH |
2187 | ret = register_netdev(ndev); |
2188 | if (ret) | |
2189 | goto failed_register; | |
2190 | ||
eb1d0640 FE |
2191 | if (fep->bufdesc_ex && fep->ptp_clock) |
2192 | netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); | |
2193 | ||
54309fa6 | 2194 | INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); |
ead73183 SH |
2195 | return 0; |
2196 | ||
2197 | failed_register: | |
e6b043d5 BW |
2198 | fec_enet_mii_remove(fep); |
2199 | failed_mii_init: | |
7a2bbd8d | 2200 | failed_irq: |
7a2bbd8d | 2201 | failed_init: |
f6a4d607 FE |
2202 | if (fep->reg_phy) |
2203 | regulator_disable(fep->reg_phy); | |
5fa9c0fe | 2204 | failed_regulator: |
9514fe7a FE |
2205 | if (fep->clk_ptp) |
2206 | clk_disable_unprepare(fep->clk_ptp); | |
13a097bd | 2207 | failed_clk_ptp: |
d265cf48 FE |
2208 | if (fep->clk_enet_out) |
2209 | clk_disable_unprepare(fep->clk_enet_out); | |
13a097bd | 2210 | failed_clk_enet_out: |
d265cf48 | 2211 | clk_disable_unprepare(fep->clk_ipg); |
13a097bd | 2212 | failed_clk_ipg: |
d265cf48 | 2213 | clk_disable_unprepare(fep->clk_ahb); |
ead73183 | 2214 | failed_clk: |
ead73183 SH |
2215 | failed_ioremap: |
2216 | free_netdev(ndev); | |
2217 | ||
2218 | return ret; | |
2219 | } | |
2220 | ||
33897cc8 | 2221 | static int |
ead73183 SH |
2222 | fec_drv_remove(struct platform_device *pdev) |
2223 | { | |
2224 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2225 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2226 | ||
54309fa6 | 2227 | cancel_delayed_work_sync(&(fep->delay_work.delay_work)); |
e163cc97 | 2228 | unregister_netdev(ndev); |
e6b043d5 | 2229 | fec_enet_mii_remove(fep); |
6605b730 | 2230 | del_timer_sync(&fep->time_keep); |
f6a4d607 FE |
2231 | if (fep->reg_phy) |
2232 | regulator_disable(fep->reg_phy); | |
9514fe7a FE |
2233 | if (fep->clk_ptp) |
2234 | clk_disable_unprepare(fep->clk_ptp); | |
6605b730 FL |
2235 | if (fep->ptp_clock) |
2236 | ptp_clock_unregister(fep->ptp_clock); | |
9514fe7a FE |
2237 | if (fep->clk_enet_out) |
2238 | clk_disable_unprepare(fep->clk_enet_out); | |
f4d40de3 | 2239 | clk_disable_unprepare(fep->clk_ipg); |
d265cf48 | 2240 | clk_disable_unprepare(fep->clk_ahb); |
ead73183 | 2241 | free_netdev(ndev); |
28e2188e | 2242 | |
ead73183 SH |
2243 | return 0; |
2244 | } | |
2245 | ||
bf7bfd7f | 2246 | #ifdef CONFIG_PM_SLEEP |
ead73183 | 2247 | static int |
87cad5c3 | 2248 | fec_suspend(struct device *dev) |
ead73183 | 2249 | { |
87cad5c3 | 2250 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2251 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 2252 | |
04e5216d UKK |
2253 | if (netif_running(ndev)) { |
2254 | fec_stop(ndev); | |
2255 | netif_device_detach(ndev); | |
ead73183 | 2256 | } |
79820e72 FE |
2257 | if (fep->clk_ptp) |
2258 | clk_disable_unprepare(fep->clk_ptp); | |
9514fe7a FE |
2259 | if (fep->clk_enet_out) |
2260 | clk_disable_unprepare(fep->clk_enet_out); | |
f4d40de3 | 2261 | clk_disable_unprepare(fep->clk_ipg); |
d265cf48 | 2262 | clk_disable_unprepare(fep->clk_ahb); |
04e5216d | 2263 | |
238f7bc7 FE |
2264 | if (fep->reg_phy) |
2265 | regulator_disable(fep->reg_phy); | |
2266 | ||
ead73183 SH |
2267 | return 0; |
2268 | } | |
2269 | ||
2270 | static int | |
87cad5c3 | 2271 | fec_resume(struct device *dev) |
ead73183 | 2272 | { |
87cad5c3 | 2273 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2274 | struct fec_enet_private *fep = netdev_priv(ndev); |
238f7bc7 FE |
2275 | int ret; |
2276 | ||
2277 | if (fep->reg_phy) { | |
2278 | ret = regulator_enable(fep->reg_phy); | |
2279 | if (ret) | |
2280 | return ret; | |
2281 | } | |
ead73183 | 2282 | |
13a097bd FE |
2283 | ret = clk_prepare_enable(fep->clk_ahb); |
2284 | if (ret) | |
2285 | goto failed_clk_ahb; | |
2286 | ||
2287 | ret = clk_prepare_enable(fep->clk_ipg); | |
2288 | if (ret) | |
2289 | goto failed_clk_ipg; | |
2290 | ||
2291 | if (fep->clk_enet_out) { | |
2292 | ret = clk_prepare_enable(fep->clk_enet_out); | |
2293 | if (ret) | |
2294 | goto failed_clk_enet_out; | |
2295 | } | |
2296 | ||
2297 | if (fep->clk_ptp) { | |
2298 | ret = clk_prepare_enable(fep->clk_ptp); | |
2299 | if (ret) | |
2300 | goto failed_clk_ptp; | |
2301 | } | |
2302 | ||
04e5216d UKK |
2303 | if (netif_running(ndev)) { |
2304 | fec_restart(ndev, fep->full_duplex); | |
2305 | netif_device_attach(ndev); | |
ead73183 | 2306 | } |
04e5216d | 2307 | |
ead73183 | 2308 | return 0; |
13a097bd FE |
2309 | |
2310 | failed_clk_ptp: | |
2311 | if (fep->clk_enet_out) | |
2312 | clk_disable_unprepare(fep->clk_enet_out); | |
2313 | failed_clk_enet_out: | |
2314 | clk_disable_unprepare(fep->clk_ipg); | |
2315 | failed_clk_ipg: | |
2316 | clk_disable_unprepare(fep->clk_ahb); | |
2317 | failed_clk_ahb: | |
2318 | if (fep->reg_phy) | |
2319 | regulator_disable(fep->reg_phy); | |
2320 | return ret; | |
ead73183 | 2321 | } |
bf7bfd7f | 2322 | #endif /* CONFIG_PM_SLEEP */ |
ead73183 | 2323 | |
bf7bfd7f | 2324 | static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); |
59d4289b | 2325 | |
ead73183 SH |
2326 | static struct platform_driver fec_driver = { |
2327 | .driver = { | |
b5680e0b | 2328 | .name = DRIVER_NAME, |
87cad5c3 | 2329 | .owner = THIS_MODULE, |
87cad5c3 | 2330 | .pm = &fec_pm_ops, |
ca2cc333 | 2331 | .of_match_table = fec_dt_ids, |
ead73183 | 2332 | }, |
b5680e0b | 2333 | .id_table = fec_devtype, |
87cad5c3 | 2334 | .probe = fec_probe, |
33897cc8 | 2335 | .remove = fec_drv_remove, |
ead73183 SH |
2336 | }; |
2337 | ||
aaca2377 | 2338 | module_platform_driver(fec_driver); |
1da177e4 | 2339 | |
f8c0aca9 | 2340 | MODULE_ALIAS("platform:"DRIVER_NAME); |
1da177e4 | 2341 | MODULE_LICENSE("GPL"); |