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Merge tag 'omap-for-v5.0/fixes-rc7-signed' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1f508124 1// SPDX-License-Identifier: GPL-2.0+
1da177e4
LT		 2/*
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
7dd6a2aa 6 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
11 * small packets.
12 *
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 *
562d2f8c
GU		 16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 18 *
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 20 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 21 *
230dec61 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
8fff755e 28#include <linux/pm_runtime.h>
1da177e4
LT		 29#include <linux/ptrace.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
1da177e4
LT		 34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
4c09eed9
JB		 38#include <linux/in.h>
39#include <linux/ip.h>
40#include <net/ip.h>
79f33912 41#include <net/tso.h>
4c09eed9
JB		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/icmp.h>
1da177e4
LT		 45#include <linux/spinlock.h>
46#include <linux/workqueue.h>
47#include <linux/bitops.h>
6f501b17
SH		 48#include <linux/io.h>
49#include <linux/irq.h>
196719ec 50#include <linux/clk.h>
16f6e983 51#include <linux/crc32.h>
ead73183 52#include <linux/platform_device.h>
7f854420 53#include <linux/mdio.h>
e6b043d5 54#include <linux/phy.h>
5eb32bd0 55#include <linux/fec.h>
ca2cc333
SG		 56#include <linux/of.h>
57#include <linux/of_device.h>
58#include <linux/of_gpio.h>
407066f8 59#include <linux/of_mdio.h>
ca2cc333 60#include <linux/of_net.h>
5fa9c0fe 61#include <linux/regulator/consumer.h>
cdffcf1b 62#include <linux/if_vlan.h>
a68ab98e 63#include <linux/pinctrl/consumer.h>
c259c132 64#include <linux/prefetch.h>
29380905 65#include <soc/imx/cpuidle.h>
1da177e4 66
080853af 67#include <asm/cacheflush.h>
196719ec 68
1da177e4 69#include "fec.h"
1da177e4 70
772e42b0 71static void set_multicast_list(struct net_device *ndev);
d851b47b 72static void fec_enet_itr_coal_init(struct net_device *ndev);
772e42b0 73
b5680e0b
SG		 74#define DRIVER_NAME "fec"
75
4d494cdc
FD		 76#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
77
baa70a5c
FL		 78/* Pause frame feild and FIFO threshold */
79#define FEC_ENET_FCE (1 << 5)
80#define FEC_ENET_RSEM_V 0x84
81#define FEC_ENET_RSFL_V 16
82#define FEC_ENET_RAEM_V 0x8
83#define FEC_ENET_RAFL_V 0x8
84#define FEC_ENET_OPD_V 0xFFF0
8fff755e 85#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
baa70a5c 86
b5680e0b
SG		 87static struct platform_device_id fec_devtype[] = {
88 {
0ca1e290 89 /* keep it for coldfire */
b5680e0b
SG		 90 .name = DRIVER_NAME,
91 .driver_data = 0,
0ca1e290
SG		 92 }, {
93 .name = "imx25-fec",
ec20a63a
FD		 94 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
95 FEC_QUIRK_HAS_FRREG,
0ca1e290
SG		 96 }, {
97 .name = "imx27-fec",
ec20a63a 98 .driver_data = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
b5680e0b
SG		 99 }, {
100 .name = "imx28-fec",
3d125f9c 101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
ec20a63a
FD		 102 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
103 FEC_QUIRK_HAS_FRREG,
230dec61
SG		 104 }, {
105 .name = "imx6q-fec",
ff43da86 106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 107 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
18803495
GU		 108 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
109 FEC_QUIRK_HAS_RACC,
ca7c4a45 110 }, {
36803542 111 .name = "mvf600-fec",
18803495 112 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
95a77470
FD		 113 }, {
114 .name = "imx6sx-fec",
115 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
116 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
f88c7ede 117 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
18803495 118 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
ff7566b8 119 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
a51d3ab5
FD		 120 }, {
121 .name = "imx6ul-fec",
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
99492ad4
FD		 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
125 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
126 FEC_QUIRK_HAS_COALESCE,
0ca1e290
SG		 127 }, {
128 /* sentinel */
129 }
b5680e0b 130};
0ca1e290 131MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 132
ca2cc333 133enum imx_fec_type {
a7dd3219 134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 135 IMX27_FEC, /* runs on i.mx27/35/51 */
136 IMX28_FEC,
230dec61 137 IMX6Q_FEC,
36803542 138 MVF600_FEC,
ba593e00 139 IMX6SX_FEC,
a51d3ab5 140 IMX6UL_FEC,
ca2cc333
SG		 141};
142
143static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ba593e00 149 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
a51d3ab5 150 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
ca2cc333
SG		 151 { /* sentinel */ }
152};
153MODULE_DEVICE_TABLE(of, fec_dt_ids);
154
49da97dc
SG		 155static unsigned char macaddr[ETH_ALEN];
156module_param_array(macaddr, byte, NULL, 0);
157MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 158
49da97dc 159#if defined(CONFIG_M5272)
1da177e4
LT		 160/*
161 * Some hardware gets it MAC address out of local flash memory.
162 * if this is non-zero then assume it is the address to get MAC from.
163 */
164#if defined(CONFIG_NETtel)
165#define FEC_FLASHMAC 0xf0006006
166#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
167#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 168#elif defined(CONFIG_CANCam)
169#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 170#elif defined (CONFIG_M5272C3)
171#define FEC_FLASHMAC (0xffe04000 + 4)
172#elif defined(CONFIG_MOD5272)
a7dd3219 173#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 174#else
175#define FEC_FLASHMAC 0
176#endif
43be6366 177#endif /* CONFIG_M5272 */
ead73183 178
cdffcf1b 179/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
fbbeefdd
AL		 180 *
181 * 2048 byte skbufs are allocated. However, alignment requirements
182 * varies between FEC variants. Worst case is 64, so round down by 64.
1da177e4 183 */
fbbeefdd 184#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
1da177e4 185#define PKT_MINBUF_SIZE 64
1da177e4 186
4c09eed9
JB		 187/* FEC receive acceleration */
188#define FEC_RACC_IPDIS (1 << 1)
189#define FEC_RACC_PRODIS (1 << 2)
3ac72b7b 190#define FEC_RACC_SHIFT16 BIT(7)
4c09eed9
JB		 191#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
192
2b30842b
AL		 193/* MIB Control Register */
194#define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
195
1da177e4 196/*
6b265293 197 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 198 * size bits. Other FEC hardware does not, so we need to take that into
199 * account when setting it.
200 */
562d2f8c 201#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
3f1dcc6a
LS		 202 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
203 defined(CONFIG_ARM64)
1da177e4
LT		 204#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
205#else
206#define OPT_FRAME_SIZE 0
207#endif
208
e6b043d5
BW		 209/* FEC MII MMFR bits definition */
210#define FEC_MMFR_ST (1 << 30)
211#define FEC_MMFR_OP_READ (2 << 28)
212#define FEC_MMFR_OP_WRITE (1 << 28)
213#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
214#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
215#define FEC_MMFR_TA (2 << 16)
216#define FEC_MMFR_DATA(v) (v & 0xffff)
de40ed31
NA		 217/* FEC ECR bits definition */
218#define FEC_ECR_MAGICEN (1 << 2)
219#define FEC_ECR_SLEEP (1 << 3)
1da177e4 220
c3b084c2 221#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 222
22f6b860
SH		 223/* Transmitter timeout */
224#define TX_TIMEOUT (2 * HZ)
1da177e4 225
baa70a5c
FL		 226#define FEC_PAUSE_FLAG_AUTONEG 0x1
227#define FEC_PAUSE_FLAG_ENABLE 0x2
de40ed31
NA		 228#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
229#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
230#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
baa70a5c 231
1b7bde6d
NA		 232#define COPYBREAK_DEFAULT 256
233
79f33912
NA		 234/* Max number of allowed TCP segments for software TSO */
235#define FEC_MAX_TSO_SEGS 100
236#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
237
238#define IS_TSO_HEADER(txq, addr) \
239 ((addr >= txq->tso_hdrs_dma) && \
7355f276 240 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
79f33912 241
e163cc97
LW		 242static int mii_cnt;
243
7355f276
TK		 244static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
245 struct bufdesc_prop *bd)
246{
247 return (bdp >= bd->last) ? bd->base
145d6e29 248 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
7355f276 249}
36e24e2e 250
7355f276
TK		 251static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
252 struct bufdesc_prop *bd)
253{
254 return (bdp <= bd->base) ? bd->last
145d6e29 255 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
ff43da86
FL		 256}
257
7355f276
TK		 258static int fec_enet_get_bd_index(struct bufdesc *bdp,
259 struct bufdesc_prop *bd)
61a4427b 260{
7355f276 261 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
61a4427b
NA		 262}
263
7355f276 264static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
6e909283
NA		 265{
266 int entries;
267
7355f276
TK		 268 entries = (((const char *)txq->dirty_tx -
269 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
6e909283 270
7355f276 271 return entries >= 0 ? entries : entries + txq->bd.ring_size;
6e909283
NA		 272}
273
c20e599b 274static void swap_buffer(void *bufaddr, int len)
b5680e0b
SG		 275{
276 int i;
277 unsigned int *buf = bufaddr;
278
7b487d07 279 for (i = 0; i < len; i += 4, buf++)
e453789a 280 swab32s(buf);
b5680e0b
SG		 281}
282
1310b544
LW		 283static void swap_buffer2(void *dst_buf, void *src_buf, int len)
284{
285 int i;
286 unsigned int *src = src_buf;
287 unsigned int *dst = dst_buf;
288
289 for (i = 0; i < len; i += 4, src++, dst++)
290 *dst = swab32p(src);
291}
292
344756f6
RK		 293static void fec_dump(struct net_device *ndev)
294{
295 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 296 struct bufdesc *bdp;
297 struct fec_enet_priv_tx_q *txq;
298 int index = 0;
344756f6
RK		 299
300 netdev_info(ndev, "TX ring dump\n");
301 pr_info("Nr SC addr len SKB\n");
302
4d494cdc 303 txq = fep->tx_queue[0];
7355f276 304 bdp = txq->bd.base;
4d494cdc 305
344756f6 306 do {
5cfa3039 307 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
344756f6 308 index,
7355f276 309 bdp == txq->bd.cur ? 'S' : ' ',
4d494cdc 310 bdp == txq->dirty_tx ? 'H' : ' ',
5cfa3039
JB		 311 fec16_to_cpu(bdp->cbd_sc),
312 fec32_to_cpu(bdp->cbd_bufaddr),
313 fec16_to_cpu(bdp->cbd_datlen),
4d494cdc 314 txq->tx_skbuff[index]);
7355f276 315 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
344756f6 316 index++;
7355f276 317 } while (bdp != txq->bd.base);
344756f6
RK		 318}
319
62a02c98
FD		 320static inline bool is_ipv4_pkt(struct sk_buff *skb)
321{
322 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
323}
324
4c09eed9
JB		 325static int
326fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
327{
328 /* Only run for packets requiring a checksum. */
329 if (skb->ip_summed != CHECKSUM_PARTIAL)
330 return 0;
331
332 if (unlikely(skb_cow_head(skb, 0)))
333 return -1;
334
62a02c98
FD		 335 if (is_ipv4_pkt(skb))
336 ip_hdr(skb)->check = 0;
4c09eed9
JB		 337 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
338
339 return 0;
340}
341
c4bc44c6 342static struct bufdesc *
4d494cdc
FD		 343fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
344 struct sk_buff *skb,
345 struct net_device *ndev)
1da177e4 346{
c556167f 347 struct fec_enet_private *fep = netdev_priv(ndev);
7355f276 348 struct bufdesc *bdp = txq->bd.cur;
6e909283
NA		 349 struct bufdesc_ex *ebdp;
350 int nr_frags = skb_shinfo(skb)->nr_frags;
351 int frag, frag_len;
352 unsigned short status;
353 unsigned int estatus = 0;
354 skb_frag_t *this_frag;
de5fb0a0 355 unsigned int index;
6e909283 356 void *bufaddr;
d6bf3143 357 dma_addr_t addr;
6e909283 358 int i;
1da177e4 359
6e909283
NA		 360 for (frag = 0; frag < nr_frags; frag++) {
361 this_frag = &skb_shinfo(skb)->frags[frag];
7355f276 362 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
6e909283
NA		 363 ebdp = (struct bufdesc_ex *)bdp;
364
5cfa3039 365 status = fec16_to_cpu(bdp->cbd_sc);
6e909283
NA		 366 status &= ~BD_ENET_TX_STATS;
367 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
368 frag_len = skb_shinfo(skb)->frags[frag].size;
369
370 /* Handle the last BD specially */
371 if (frag == nr_frags - 1) {
372 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
373 if (fep->bufdesc_ex) {
374 estatus |= BD_ENET_TX_INT;
375 if (unlikely(skb_shinfo(skb)->tx_flags &
376 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
377 estatus |= BD_ENET_TX_TS;
378 }
379 }
380
381 if (fep->bufdesc_ex) {
6b7e4008 382 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 383 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
6e909283
NA		 384 if (skb->ip_summed == CHECKSUM_PARTIAL)
385 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
386 ebdp->cbd_bdu = 0;
5cfa3039 387 ebdp->cbd_esc = cpu_to_fec32(estatus);
6e909283
NA		 388 }
389
390 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
391
7355f276 392 index = fec_enet_get_bd_index(bdp, &txq->bd);
41ef84ce 393 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 394 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 395 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
396 bufaddr = txq->tx_bounce[index];
6e909283 397
6b7e4008 398 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 399 swap_buffer(bufaddr, frag_len);
400 }
401
d6bf3143
RK		 402 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
403 DMA_TO_DEVICE);
404 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 405 if (net_ratelimit())
406 netdev_err(ndev, "Tx DMA memory map failed\n");
407 goto dma_mapping_error;
408 }
409
5cfa3039
JB		 410 bdp->cbd_bufaddr = cpu_to_fec32(addr);
411 bdp->cbd_datlen = cpu_to_fec16(frag_len);
be293467
TK		 412 /* Make sure the updates to rest of the descriptor are
413 * performed before transferring ownership.
414 */
415 wmb();
5cfa3039 416 bdp->cbd_sc = cpu_to_fec16(status);
6e909283
NA		 417 }
418
c4bc44c6 419 return bdp;
6e909283 420dma_mapping_error:
7355f276 421 bdp = txq->bd.cur;
6e909283 422 for (i = 0; i < frag; i++) {
7355f276 423 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
5cfa3039
JB		 424 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
425 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
6e909283 426 }
c4bc44c6 427 return ERR_PTR(-ENOMEM);
6e909283 428}
1da177e4 429
4d494cdc
FD		 430static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
431 struct sk_buff *skb, struct net_device *ndev)
6e909283
NA		 432{
433 struct fec_enet_private *fep = netdev_priv(ndev);
6e909283
NA		 434 int nr_frags = skb_shinfo(skb)->nr_frags;
435 struct bufdesc *bdp, *last_bdp;
436 void *bufaddr;
d6bf3143 437 dma_addr_t addr;
6e909283
NA		 438 unsigned short status;
439 unsigned short buflen;
440 unsigned int estatus = 0;
441 unsigned int index;
79f33912 442 int entries_free;
22f6b860 443
7355f276 444 entries_free = fec_enet_get_free_txdesc_num(txq);
79f33912
NA		 445 if (entries_free < MAX_SKB_FRAGS + 1) {
446 dev_kfree_skb_any(skb);
447 if (net_ratelimit())
448 netdev_err(ndev, "NOT enough BD for SG!\n");
449 return NETDEV_TX_OK;
450 }
451
4c09eed9
JB		 452 /* Protocol checksum off-load for TCP and UDP. */
453 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 454 dev_kfree_skb_any(skb);
4c09eed9
JB		 455 return NETDEV_TX_OK;
456 }
457
6e909283 458 /* Fill in a Tx ring entry */
7355f276 459 bdp = txq->bd.cur;
c4bc44c6 460 last_bdp = bdp;
5cfa3039 461 status = fec16_to_cpu(bdp->cbd_sc);
0e702ab3 462 status &= ~BD_ENET_TX_STATS;
1da177e4 463
22f6b860 464 /* Set buffer length and buffer pointer */
9555b31e 465 bufaddr = skb->data;
6e909283 466 buflen = skb_headlen(skb);
1da177e4 467
7355f276 468 index = fec_enet_get_bd_index(bdp, &txq->bd);
41ef84ce 469 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 470 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 471 memcpy(txq->tx_bounce[index], skb->data, buflen);
472 bufaddr = txq->tx_bounce[index];
1da177e4 473
6b7e4008 474 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 475 swap_buffer(bufaddr, buflen);
476 }
6aa20a22 477
d6bf3143
RK		 478 /* Push the data cache so the CPM does not get stale memory data. */
479 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
480 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 481 dev_kfree_skb_any(skb);
482 if (net_ratelimit())
483 netdev_err(ndev, "Tx DMA memory map failed\n");
484 return NETDEV_TX_OK;
485 }
1da177e4 486
6e909283 487 if (nr_frags) {
c4bc44c6 488 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
fc75ba51
TK		 489 if (IS_ERR(last_bdp)) {
490 dma_unmap_single(&fep->pdev->dev, addr,
491 buflen, DMA_TO_DEVICE);
492 dev_kfree_skb_any(skb);
c4bc44c6 493 return NETDEV_TX_OK;
fc75ba51 494 }
6e909283
NA		 495 } else {
496 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
497 if (fep->bufdesc_ex) {
498 estatus = BD_ENET_TX_INT;
499 if (unlikely(skb_shinfo(skb)->tx_flags &
500 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
501 estatus |= BD_ENET_TX_TS;
502 }
503 }
fc75ba51
TK		 504 bdp->cbd_bufaddr = cpu_to_fec32(addr);
505 bdp->cbd_datlen = cpu_to_fec16(buflen);
6e909283 506
ff43da86
FL		 507 if (fep->bufdesc_ex) {
508
509 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 510
ff43da86 511 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 512 fep->hwts_tx_en))
6605b730 513 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 514
6b7e4008 515 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 516 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
befe8213 517
6e909283
NA		 518 if (skb->ip_summed == CHECKSUM_PARTIAL)
519 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
520
521 ebdp->cbd_bdu = 0;
5cfa3039 522 ebdp->cbd_esc = cpu_to_fec32(estatus);
6605b730 523 }
03191656 524
7355f276 525 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
6e909283 526 /* Save skb pointer */
4d494cdc 527 txq->tx_skbuff[index] = skb;
6e909283 528
be293467
TK		 529 /* Make sure the updates to rest of the descriptor are performed before
530 * transferring ownership.
531 */
532 wmb();
6e909283 533
fb8ef788
DFB		 534 /* Send it on its way. Tell FEC it's ready, interrupt when done,
535 * it's the last BD of the frame, and to put the CRC on the end.
536 */
6e909283 537 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
5cfa3039 538 bdp->cbd_sc = cpu_to_fec16(status);
fb8ef788 539
22f6b860 540 /* If this was the last BD in the ring, start at the beginning again. */
7355f276 541 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
1da177e4 542
7a2a8451
ED		 543 skb_tx_timestamp(skb);
544
c4bc44c6 545 /* Make sure the update to bdp and tx_skbuff are performed before
7355f276 546 * txq->bd.cur.
c4bc44c6
KH		 547 */
548 wmb();
7355f276 549 txq->bd.cur = bdp;
de5fb0a0 550
de5fb0a0 551 /* Trigger transmission start */
53bb20d1 552 writel(0, txq->bd.reg_desc_active);
1da177e4 553
6e909283 554 return 0;
1da177e4
LT		 555}
556
79f33912 557static int
4d494cdc
FD		 558fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
559 struct net_device *ndev,
560 struct bufdesc *bdp, int index, char *data,
561 int size, bool last_tcp, bool is_last)
61a4427b
NA		 562{
563 struct fec_enet_private *fep = netdev_priv(ndev);
61cd2ebb 564 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
79f33912
NA		 565 unsigned short status;
566 unsigned int estatus = 0;
d6bf3143 567 dma_addr_t addr;
61a4427b 568
5cfa3039 569 status = fec16_to_cpu(bdp->cbd_sc);
79f33912 570 status &= ~BD_ENET_TX_STATS;
61a4427b 571
79f33912 572 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912 573
41ef84ce 574 if (((unsigned long) data) & fep->tx_align ||
6b7e4008 575 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 576 memcpy(txq->tx_bounce[index], data, size);
577 data = txq->tx_bounce[index];
79f33912 578
6b7e4008 579 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 580 swap_buffer(data, size);
581 }
582
d6bf3143
RK		 583 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
584 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 585 dev_kfree_skb_any(skb);
6e909283 586 if (net_ratelimit())
79f33912 587 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 588 return NETDEV_TX_BUSY;
589 }
590
5cfa3039
JB		 591 bdp->cbd_datlen = cpu_to_fec16(size);
592 bdp->cbd_bufaddr = cpu_to_fec32(addr);
d6bf3143 593
79f33912 594 if (fep->bufdesc_ex) {
6b7e4008 595 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 596 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
79f33912
NA		 597 if (skb->ip_summed == CHECKSUM_PARTIAL)
598 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
599 ebdp->cbd_bdu = 0;
5cfa3039 600 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 601 }
602
603 /* Handle the last BD specially */
604 if (last_tcp)
605 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
606 if (is_last) {
607 status |= BD_ENET_TX_INTR;
608 if (fep->bufdesc_ex)
5cfa3039 609 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
79f33912
NA		 610 }
611
5cfa3039 612 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 613
614 return 0;
615}
616
617static int
4d494cdc
FD		 618fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
619 struct sk_buff *skb, struct net_device *ndev,
620 struct bufdesc *bdp, int index)
79f33912
NA		 621{
622 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912 623 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
61cd2ebb 624 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
79f33912
NA		 625 void *bufaddr;
626 unsigned long dmabuf;
627 unsigned short status;
628 unsigned int estatus = 0;
629
5cfa3039 630 status = fec16_to_cpu(bdp->cbd_sc);
79f33912
NA		 631 status &= ~BD_ENET_TX_STATS;
632 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
633
4d494cdc
FD		 634 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
635 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
41ef84ce 636 if (((unsigned long)bufaddr) & fep->tx_align ||
6b7e4008 637 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 638 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
639 bufaddr = txq->tx_bounce[index];
79f33912 640
6b7e4008 641 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 642 swap_buffer(bufaddr, hdr_len);
643
644 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
645 hdr_len, DMA_TO_DEVICE);
646 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
647 dev_kfree_skb_any(skb);
648 if (net_ratelimit())
649 netdev_err(ndev, "Tx DMA memory map failed\n");
650 return NETDEV_TX_BUSY;
651 }
652 }
653
5cfa3039
JB		 654 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
655 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
79f33912
NA		 656
657 if (fep->bufdesc_ex) {
6b7e4008 658 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 659 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
79f33912
NA		 660 if (skb->ip_summed == CHECKSUM_PARTIAL)
661 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
662 ebdp->cbd_bdu = 0;
5cfa3039 663 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 664 }
665
5cfa3039 666 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 667
668 return 0;
669}
670
4d494cdc
FD		 671static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
672 struct sk_buff *skb,
673 struct net_device *ndev)
79f33912
NA		 674{
675 struct fec_enet_private *fep = netdev_priv(ndev);
676 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
677 int total_len, data_left;
7355f276 678 struct bufdesc *bdp = txq->bd.cur;
79f33912
NA		 679 struct tso_t tso;
680 unsigned int index = 0;
681 int ret;
682
7355f276 683 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
79f33912
NA		 684 dev_kfree_skb_any(skb);
685 if (net_ratelimit())
686 netdev_err(ndev, "NOT enough BD for TSO!\n");
687 return NETDEV_TX_OK;
688 }
689
690 /* Protocol checksum off-load for TCP and UDP. */
691 if (fec_enet_clear_csum(skb, ndev)) {
692 dev_kfree_skb_any(skb);
693 return NETDEV_TX_OK;
694 }
695
696 /* Initialize the TSO handler, and prepare the first payload */
697 tso_start(skb, &tso);
698
699 total_len = skb->len - hdr_len;
700 while (total_len > 0) {
701 char *hdr;
702
7355f276 703 index = fec_enet_get_bd_index(bdp, &txq->bd);
79f33912
NA		 704 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
705 total_len -= data_left;
706
707 /* prepare packet headers: MAC + IP + TCP */
4d494cdc 708 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
79f33912 709 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
4d494cdc 710 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
79f33912
NA		 711 if (ret)
712 goto err_release;
713
714 while (data_left > 0) {
715 int size;
716
717 size = min_t(int, tso.size, data_left);
7355f276
TK		 718 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
719 index = fec_enet_get_bd_index(bdp, &txq->bd);
4d494cdc
FD		 720 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
721 bdp, index,
722 tso.data, size,
723 size == data_left,
79f33912
NA		 724 total_len == 0);
725 if (ret)
726 goto err_release;
727
728 data_left -= size;
729 tso_build_data(skb, &tso, size);
730 }
731
7355f276 732 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
79f33912
NA		 733 }
734
735 /* Save skb pointer */
4d494cdc 736 txq->tx_skbuff[index] = skb;
79f33912 737
79f33912 738 skb_tx_timestamp(skb);
7355f276 739 txq->bd.cur = bdp;
79f33912
NA		 740
741 /* Trigger transmission start */
6b7e4008 742 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
53bb20d1
TK		 743 !readl(txq->bd.reg_desc_active) ||
744 !readl(txq->bd.reg_desc_active) ||
745 !readl(txq->bd.reg_desc_active) ||
746 !readl(txq->bd.reg_desc_active))
747 writel(0, txq->bd.reg_desc_active);
79f33912
NA		 748
749 return 0;
750
751err_release:
752 /* TODO: Release all used data descriptors for TSO */
753 return ret;
754}
755
756static netdev_tx_t
757fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
758{
759 struct fec_enet_private *fep = netdev_priv(ndev);
760 int entries_free;
4d494cdc
FD		 761 unsigned short queue;
762 struct fec_enet_priv_tx_q *txq;
763 struct netdev_queue *nq;
79f33912
NA		 764 int ret;
765
4d494cdc
FD		 766 queue = skb_get_queue_mapping(skb);
767 txq = fep->tx_queue[queue];
768 nq = netdev_get_tx_queue(ndev, queue);
769
79f33912 770 if (skb_is_gso(skb))
4d494cdc 771 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
79f33912 772 else
4d494cdc 773 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
6e909283
NA		 774 if (ret)
775 return ret;
61a4427b 776
7355f276 777 entries_free = fec_enet_get_free_txdesc_num(txq);
4d494cdc
FD		 778 if (entries_free <= txq->tx_stop_threshold)
779 netif_tx_stop_queue(nq);
61a4427b
NA		 780
781 return NETDEV_TX_OK;
782}
783
14109a59
FL		 784/* Init RX & TX buffer descriptors
785 */
786static void fec_enet_bd_init(struct net_device *dev)
787{
788 struct fec_enet_private *fep = netdev_priv(dev);
4d494cdc
FD		 789 struct fec_enet_priv_tx_q *txq;
790 struct fec_enet_priv_rx_q *rxq;
14109a59
FL		 791 struct bufdesc *bdp;
792 unsigned int i;
59d0f746 793 unsigned int q;
14109a59 794
59d0f746
FL		 795 for (q = 0; q < fep->num_rx_queues; q++) {
796 /* Initialize the receive buffer descriptors. */
797 rxq = fep->rx_queue[q];
7355f276 798 bdp = rxq->bd.base;
4d494cdc 799
7355f276 800 for (i = 0; i < rxq->bd.ring_size; i++) {
14109a59 801
59d0f746
FL		 802 /* Initialize the BD for every fragment in the page. */
803 if (bdp->cbd_bufaddr)
5cfa3039 804 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
59d0f746 805 else
5cfa3039 806 bdp->cbd_sc = cpu_to_fec16(0);
7355f276 807 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
59d0f746
FL		 808 }
809
810 /* Set the last buffer to wrap */
7355f276 811 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
5cfa3039 812 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 813
7355f276 814 rxq->bd.cur = rxq->bd.base;
59d0f746
FL		 815 }
816
817 for (q = 0; q < fep->num_tx_queues; q++) {
818 /* ...and the same for transmit */
819 txq = fep->tx_queue[q];
7355f276
TK		 820 bdp = txq->bd.base;
821 txq->bd.cur = bdp;
59d0f746 822
7355f276 823 for (i = 0; i < txq->bd.ring_size; i++) {
59d0f746 824 /* Initialize the BD for every fragment in the page. */
5cfa3039 825 bdp->cbd_sc = cpu_to_fec16(0);
178e5f57
FD		 826 if (bdp->cbd_bufaddr &&
827 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
828 dma_unmap_single(&fep->pdev->dev,
829 fec32_to_cpu(bdp->cbd_bufaddr),
830 fec16_to_cpu(bdp->cbd_datlen),
831 DMA_TO_DEVICE);
59d0f746
FL		 832 if (txq->tx_skbuff[i]) {
833 dev_kfree_skb_any(txq->tx_skbuff[i]);
834 txq->tx_skbuff[i] = NULL;
835 }
5cfa3039 836 bdp->cbd_bufaddr = cpu_to_fec32(0);
7355f276 837 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
59d0f746
FL		 838 }
839
840 /* Set the last buffer to wrap */
7355f276 841 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
5cfa3039 842 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 843 txq->dirty_tx = bdp;
14109a59 844 }
59d0f746 845}
14109a59 846
ce99d0d3
FL		 847static void fec_enet_active_rxring(struct net_device *ndev)
848{
849 struct fec_enet_private *fep = netdev_priv(ndev);
850 int i;
851
852 for (i = 0; i < fep->num_rx_queues; i++)
53bb20d1 853 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
ce99d0d3
FL		 854}
855
59d0f746
FL		 856static void fec_enet_enable_ring(struct net_device *ndev)
857{
858 struct fec_enet_private *fep = netdev_priv(ndev);
859 struct fec_enet_priv_tx_q *txq;
860 struct fec_enet_priv_rx_q *rxq;
861 int i;
14109a59 862
59d0f746
FL		 863 for (i = 0; i < fep->num_rx_queues; i++) {
864 rxq = fep->rx_queue[i];
7355f276 865 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
fbbeefdd 866 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
14109a59 867
59d0f746
FL		 868 /* enable DMA1/2 */
869 if (i)
870 writel(RCMR_MATCHEN | RCMR_CMP(i),
871 fep->hwp + FEC_RCMR(i));
872 }
14109a59 873
59d0f746
FL		 874 for (i = 0; i < fep->num_tx_queues; i++) {
875 txq = fep->tx_queue[i];
7355f276 876 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
59d0f746
FL		 877
878 /* enable DMA1/2 */
879 if (i)
880 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
881 fep->hwp + FEC_DMA_CFG(i));
14109a59 882 }
59d0f746 883}
14109a59 884
59d0f746
FL		 885static void fec_enet_reset_skb(struct net_device *ndev)
886{
887 struct fec_enet_private *fep = netdev_priv(ndev);
888 struct fec_enet_priv_tx_q *txq;
889 int i, j;
890
891 for (i = 0; i < fep->num_tx_queues; i++) {
892 txq = fep->tx_queue[i];
893
7355f276 894 for (j = 0; j < txq->bd.ring_size; j++) {
59d0f746
FL		 895 if (txq->tx_skbuff[j]) {
896 dev_kfree_skb_any(txq->tx_skbuff[j]);
897 txq->tx_skbuff[j] = NULL;
898 }
899 }
900 }
14109a59
FL		 901}
902
dbc64a8e
RK		 903/*
904 * This function is called to start or restart the FEC during a link
905 * change, transmit timeout, or to reconfigure the FEC. The network
906 * packet processing for this device must be stopped before this call.
45993653 907 */
1da177e4 908static void
ef83337d 909fec_restart(struct net_device *ndev)
1da177e4 910{
c556167f 911 struct fec_enet_private *fep = netdev_priv(ndev);
4c09eed9 912 u32 val;
cd1f402c
UKK		 913 u32 temp_mac[2];
914 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 915 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 916
106c314c
FD		 917 /* Whack a reset. We should wait for this.
918 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
919 * instead of reset MAC itself.
920 */
6b7e4008 921 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 922 writel(0, fep->hwp + FEC_ECNTRL);
923 } else {
924 writel(1, fep->hwp + FEC_ECNTRL);
925 udelay(10);
926 }
1da177e4 927
45993653
UKK		 928 /*
929 * enet-mac reset will reset mac address registers too,
930 * so need to reconfigure it.
931 */
b82d44d7
GS		 932 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
933 writel((__force u32)cpu_to_be32(temp_mac[0]),
934 fep->hwp + FEC_ADDR_LOW);
935 writel((__force u32)cpu_to_be32(temp_mac[1]),
936 fep->hwp + FEC_ADDR_HIGH);
1da177e4 937
45993653 938 /* Clear any outstanding interrupt. */
e17f7fec 939 writel(0xffffffff, fep->hwp + FEC_IEVENT);
1da177e4 940
14109a59
FL		 941 fec_enet_bd_init(ndev);
942
59d0f746 943 fec_enet_enable_ring(ndev);
45993653 944
59d0f746
FL		 945 /* Reset tx SKB buffers. */
946 fec_enet_reset_skb(ndev);
97b72e43 947
45993653 948 /* Enable MII mode */
ef83337d 949 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 950 /* FD enable */
45993653
UKK		 951 writel(0x04, fep->hwp + FEC_X_CNTRL);
952 } else {
cd1f402c
UKK		 953 /* No Rcv on Xmit */
954 rcntl |= 0x02;
45993653
UKK		 955 writel(0x0, fep->hwp + FEC_X_CNTRL);
956 }
cd1f402c 957
45993653
UKK		 958 /* Set MII speed */
959 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
960
d1391930 961#if !defined(CONFIG_M5272)
18803495 962 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
18803495 963 val = readl(fep->hwp + FEC_RACC);
3ac72b7b
EN		 964 /* align IP header */
965 val |= FEC_RACC_SHIFT16;
18803495 966 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
3ac72b7b 967 /* set RX checksum */
18803495
GU		 968 val |= FEC_RACC_OPTIONS;
969 else
970 val &= ~FEC_RACC_OPTIONS;
971 writel(val, fep->hwp + FEC_RACC);
32867fcc 972 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
18803495 973 }
d1391930 974#endif
4c09eed9 975
45993653
UKK		 976 /*
977 * The phy interface and speed need to get configured
978 * differently on enet-mac.
979 */
6b7e4008 980 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 981 /* Enable flow control and length check */
982 rcntl |= 0x40000000 | 0x00000020;
45993653 983
230dec61 984 /* RGMII, RMII or MII */
e813bb2b
MP		 985 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
986 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
987 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
988 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
230dec61
SG		 989 rcntl |= (1 << 6);
990 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 991 rcntl |= (1 << 8);
45993653 992 else
cd1f402c 993 rcntl &= ~(1 << 8);
45993653 994
230dec61 995 /* 1G, 100M or 10M */
45f5c327
PR		 996 if (ndev->phydev) {
997 if (ndev->phydev->speed == SPEED_1000)
230dec61 998 ecntl |= (1 << 5);
45f5c327 999 else if (ndev->phydev->speed == SPEED_100)
230dec61
SG		 1000 rcntl &= ~(1 << 9);
1001 else
1002 rcntl |= (1 << 9);
1003 }
45993653
UKK		 1004 } else {
1005#ifdef FEC_MIIGSK_ENR
6b7e4008 1006 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
8d82f219 1007 u32 cfgr;
45993653
UKK		 1008 /* disable the gasket and wait */
1009 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1010 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1011 udelay(1);
1012
1013 /*
1014 * configure the gasket:
1015 * RMII, 50 MHz, no loopback, no echo
0ca1e290 1016 * MII, 25 MHz, no loopback, no echo
45993653 1017 */
8d82f219
EB		 1018 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1019 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
45f5c327 1020 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
8d82f219
EB		 1021 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1022 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 1023
1024 /* re-enable the gasket */
1025 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 1026 }
45993653
UKK		 1027#endif
1028 }
baa70a5c 1029
d1391930 1030#if !defined(CONFIG_M5272)
baa70a5c
FL		 1031 /* enable pause frame*/
1032 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1033 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
45f5c327 1034 ndev->phydev && ndev->phydev->pause)) {
baa70a5c
FL		 1035 rcntl |= FEC_ENET_FCE;
1036
4c09eed9 1037 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 1038 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1039 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1040 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1041 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1042
1043 /* OPD */
1044 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1045 } else {
1046 rcntl &= ~FEC_ENET_FCE;
1047 }
d1391930 1048#endif /* !defined(CONFIG_M5272) */
baa70a5c 1049
cd1f402c 1050 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 1051
84fe6182
SW		 1052 /* Setup multicast filter. */
1053 set_multicast_list(ndev);
1054#ifndef CONFIG_M5272
1055 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1056 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1057#endif
1058
6b7e4008 1059 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61
SG		 1060 /* enable ENET endian swap */
1061 ecntl |= (1 << 8);
1062 /* enable ENET store and forward mode */
1063 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1064 }
1065
ff43da86
FL		 1066 if (fep->bufdesc_ex)
1067 ecntl |= (1 << 4);
6605b730 1068
38ae92dc 1069#ifndef CONFIG_M5272
b9eef55c
JB		 1070 /* Enable the MIB statistic event counters */
1071 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1072#endif
1073
45993653 1074 /* And last, enable the transmit and receive processing */
230dec61 1075 writel(ecntl, fep->hwp + FEC_ECNTRL);
ce99d0d3 1076 fec_enet_active_rxring(ndev);
45993653 1077
ff43da86
FL		 1078 if (fep->bufdesc_ex)
1079 fec_ptp_start_cyclecounter(ndev);
1080
45993653 1081 /* Enable interrupts we wish to service */
0c5a3aef
NA		 1082 if (fep->link)
1083 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1084 else
1085 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
d851b47b
FD		 1086
1087 /* Init the interrupt coalescing */
1088 fec_enet_itr_coal_init(ndev);
1089
45993653
UKK		 1090}
1091
1092static void
1093fec_stop(struct net_device *ndev)
1094{
1095 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 1096 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
42431dc2 1097 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
de40ed31 1098 u32 val;
45993653
UKK		 1099
1100 /* We cannot expect a graceful transmit stop without link !!! */
1101 if (fep->link) {
1102 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1103 udelay(10);
1104 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1105 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1106 }
1107
106c314c
FD		 1108 /* Whack a reset. We should wait for this.
1109 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1110 * instead of reset MAC itself.
1111 */
de40ed31
NA		 1112 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1113 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1114 writel(0, fep->hwp + FEC_ECNTRL);
1115 } else {
1116 writel(1, fep->hwp + FEC_ECNTRL);
1117 udelay(10);
1118 }
1119 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
106c314c 1120 } else {
de40ed31
NA		 1121 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1122 val = readl(fep->hwp + FEC_ECNTRL);
1123 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1124 writel(val, fep->hwp + FEC_ECNTRL);
1125
1126 if (pdata && pdata->sleep_mode_enable)
1127 pdata->sleep_mode_enable(true);
106c314c 1128 }
45993653 1129 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
230dec61
SG		 1130
1131 /* We have to keep ENET enabled to have MII interrupt stay working */
de40ed31
NA		 1132 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1133 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
230dec61 1134 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1135 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1136 }
1da177e4
LT		 1137}
1138
1139
45993653
UKK		 1140static void
1141fec_timeout(struct net_device *ndev)
1142{
1143 struct fec_enet_private *fep = netdev_priv(ndev);
1144
344756f6
RK		 1145 fec_dump(ndev);
1146
45993653
UKK		 1147 ndev->stats.tx_errors++;
1148
36cdc743 1149 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1150}
1151
36cdc743 1152static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1153{
1154 struct fec_enet_private *fep =
36cdc743 1155 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1156 struct net_device *ndev = fep->netdev;
54309fa6 1157
36cdc743
RK		 1158 rtnl_lock();
1159 if (netif_device_present(ndev) || netif_running(ndev)) {
1160 napi_disable(&fep->napi);
1161 netif_tx_lock_bh(ndev);
1162 fec_restart(ndev);
657ade07 1163 netif_tx_wake_all_queues(ndev);
36cdc743
RK		 1164 netif_tx_unlock_bh(ndev);
1165 napi_enable(&fep->napi);
54309fa6 1166 }
36cdc743 1167 rtnl_unlock();
45993653
UKK		 1168}
1169
bfd4ecdd
RK		 1170static void
1171fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1172 struct skb_shared_hwtstamps *hwtstamps)
1173{
1174 unsigned long flags;
1175 u64 ns;
1176
1177 spin_lock_irqsave(&fep->tmreg_lock, flags);
1178 ns = timecounter_cyc2time(&fep->tc, ts);
1179 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1180
1181 memset(hwtstamps, 0, sizeof(*hwtstamps));
1182 hwtstamps->hwtstamp = ns_to_ktime(ns);
1183}
1184
1da177e4 1185static void
4d494cdc 1186fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1da177e4
LT		 1187{
1188 struct fec_enet_private *fep;
a2fe37b6 1189 struct bufdesc *bdp;
0e702ab3 1190 unsigned short status;
1da177e4 1191 struct sk_buff *skb;
4d494cdc
FD		 1192 struct fec_enet_priv_tx_q *txq;
1193 struct netdev_queue *nq;
de5fb0a0 1194 int index = 0;
79f33912 1195 int entries_free;
1da177e4 1196
c556167f 1197 fep = netdev_priv(ndev);
4d494cdc
FD		 1198
1199 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1200
1201 txq = fep->tx_queue[queue_id];
1202 /* get next bdp of dirty_tx */
1203 nq = netdev_get_tx_queue(ndev, queue_id);
1204 bdp = txq->dirty_tx;
1da177e4 1205
de5fb0a0 1206 /* get next bdp of dirty_tx */
7355f276 1207 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
de5fb0a0 1208
7355f276
TK		 1209 while (bdp != READ_ONCE(txq->bd.cur)) {
1210 /* Order the load of bd.cur and cbd_sc */
c4bc44c6 1211 rmb();
5cfa3039 1212 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
c4bc44c6 1213 if (status & BD_ENET_TX_READY)
f0b3fbea
SH		 1214 break;
1215
7355f276 1216 index = fec_enet_get_bd_index(bdp, &txq->bd);
2b995f63 1217
a2fe37b6 1218 skb = txq->tx_skbuff[index];
2b995f63 1219 txq->tx_skbuff[index] = NULL;
5cfa3039
JB		 1220 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1221 dma_unmap_single(&fep->pdev->dev,
1222 fec32_to_cpu(bdp->cbd_bufaddr),
1223 fec16_to_cpu(bdp->cbd_datlen),
1224 DMA_TO_DEVICE);
1225 bdp->cbd_bufaddr = cpu_to_fec32(0);
7fafe803
TK		 1226 if (!skb)
1227 goto skb_done;
de5fb0a0 1228
1da177e4 1229 /* Check for errors. */
0e702ab3 1230 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1231 BD_ENET_TX_RL | BD_ENET_TX_UN |
1232 BD_ENET_TX_CSL)) {
c556167f 1233 ndev->stats.tx_errors++;
0e702ab3 1234 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1235 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1236 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1237 ndev->stats.tx_window_errors++;
0e702ab3 1238 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1239 ndev->stats.tx_aborted_errors++;
0e702ab3 1240 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1241 ndev->stats.tx_fifo_errors++;
0e702ab3 1242 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1243 ndev->stats.tx_carrier_errors++;
1da177e4 1244 } else {
c556167f 1245 ndev->stats.tx_packets++;
6e909283 1246 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1247 }
1248
ff43da86
FL		 1249 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1250 fep->bufdesc_ex) {
6605b730 1251 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1252 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1253
5cfa3039 1254 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
6605b730
FL		 1255 skb_tstamp_tx(skb, &shhwtstamps);
1256 }
ff43da86 1257
1da177e4
LT		 1258 /* Deferred means some collisions occurred during transmit,
1259 * but we eventually sent the packet OK.
1260 */
0e702ab3 1261 if (status & BD_ENET_TX_DEF)
c556167f 1262 ndev->stats.collisions++;
6aa20a22 1263
22f6b860 1264 /* Free the sk buffer associated with this last transmit */
1da177e4 1265 dev_kfree_skb_any(skb);
7fafe803 1266skb_done:
c4bc44c6
KH		 1267 /* Make sure the update to bdp and tx_skbuff are performed
1268 * before dirty_tx
1269 */
1270 wmb();
4d494cdc 1271 txq->dirty_tx = bdp;
6aa20a22 1272
22f6b860 1273 /* Update pointer to next buffer descriptor to be transmitted */
7355f276 1274 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
6aa20a22 1275
22f6b860 1276 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1277 */
657ade07 1278 if (netif_tx_queue_stopped(nq)) {
7355f276 1279 entries_free = fec_enet_get_free_txdesc_num(txq);
4d494cdc
FD		 1280 if (entries_free >= txq->tx_wake_threshold)
1281 netif_tx_wake_queue(nq);
79f33912 1282 }
1da177e4 1283 }
ccea2968 1284
c10bc0e7 1285 /* ERR006358: Keep the transmitter going */
7355f276 1286 if (bdp != txq->bd.cur &&
53bb20d1
TK		 1287 readl(txq->bd.reg_desc_active) == 0)
1288 writel(0, txq->bd.reg_desc_active);
4d494cdc
FD		 1289}
1290
1291static void
1292fec_enet_tx(struct net_device *ndev)
1293{
1294 struct fec_enet_private *fep = netdev_priv(ndev);
1295 u16 queue_id;
1296 /* First process class A queue, then Class B and Best Effort queue */
1297 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1298 clear_bit(queue_id, &fep->work_tx);
1299 fec_enet_tx_queue(ndev, queue_id);
1300 }
1301 return;
1da177e4
LT		 1302}
1303
1b7bde6d
NA		 1304static int
1305fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1306{
1307 struct fec_enet_private *fep = netdev_priv(ndev);
1308 int off;
1309
1310 off = ((unsigned long)skb->data) & fep->rx_align;
1311 if (off)
1312 skb_reserve(skb, fep->rx_align + 1 - off);
1313
5cfa3039
JB		 1314 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1315 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1b7bde6d
NA		 1316 if (net_ratelimit())
1317 netdev_err(ndev, "Rx DMA memory map failed\n");
1318 return -ENOMEM;
1319 }
1320
1321 return 0;
1322}
1323
1324static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310b544 1325 struct bufdesc *bdp, u32 length, bool swap)
1b7bde6d
NA		 1326{
1327 struct fec_enet_private *fep = netdev_priv(ndev);
1328 struct sk_buff *new_skb;
1329
1330 if (length > fep->rx_copybreak)
1331 return false;
1332
1333 new_skb = netdev_alloc_skb(ndev, length);
1334 if (!new_skb)
1335 return false;
1336
5cfa3039
JB		 1337 dma_sync_single_for_cpu(&fep->pdev->dev,
1338 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1339 FEC_ENET_RX_FRSIZE - fep->rx_align,
1340 DMA_FROM_DEVICE);
1310b544
LW		 1341 if (!swap)
1342 memcpy(new_skb->data, (*skb)->data, length);
1343 else
1344 swap_buffer2(new_skb->data, (*skb)->data, length);
1b7bde6d
NA		 1345 *skb = new_skb;
1346
1347 return true;
1348}
1349
7355f276 1350/* During a receive, the bd_rx.cur points to the current incoming buffer.
1da177e4
LT		 1351 * When we update through the ring, if the next incoming buffer has
1352 * not been given to the system, we just set the empty indicator,
1353 * effectively tossing the packet.
1354 */
dc975382 1355static int
4d494cdc 1356fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1da177e4 1357{
c556167f 1358 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 1359 struct fec_enet_priv_rx_q *rxq;
2e28532f 1360 struct bufdesc *bdp;
0e702ab3 1361 unsigned short status;
1b7bde6d
NA		 1362 struct sk_buff *skb_new = NULL;
1363 struct sk_buff *skb;
1da177e4
LT		 1364 ushort pkt_len;
1365 __u8 *data;
dc975382 1366 int pkt_received = 0;
cdffcf1b
JB		 1367 struct bufdesc_ex *ebdp = NULL;
1368 bool vlan_packet_rcvd = false;
1369 u16 vlan_tag;
d842a31f 1370 int index = 0;
1b7bde6d 1371 bool is_copybreak;
6b7e4008 1372 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
6aa20a22 1373
0e702ab3
GU		 1374#ifdef CONFIG_M532x
1375 flush_cache_all();
6aa20a22 1376#endif
4d494cdc
FD		 1377 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1378 rxq = fep->rx_queue[queue_id];
1da177e4 1379
1da177e4
LT		 1380 /* First, grab all of the stats for the incoming packet.
1381 * These get messed up if we get called due to a busy condition.
1382 */
7355f276 1383 bdp = rxq->bd.cur;
1da177e4 1384
5cfa3039 1385 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1da177e4 1386
dc975382
FL		 1387 if (pkt_received >= budget)
1388 break;
1389 pkt_received++;
1390
ed63f1dc 1391 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
db3421c1 1392
22f6b860 1393 /* Check for errors. */
095098e1 1394 status ^= BD_ENET_RX_LAST;
22f6b860 1395 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
095098e1
TK		 1396 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1397 BD_ENET_RX_CL)) {
c556167f 1398 ndev->stats.rx_errors++;
095098e1
TK		 1399 if (status & BD_ENET_RX_OV) {
1400 /* FIFO overrun */
1401 ndev->stats.rx_fifo_errors++;
1402 goto rx_processing_done;
1403 }
1404 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1405 | BD_ENET_RX_LAST)) {
22f6b860 1406 /* Frame too long or too short. */
c556167f 1407 ndev->stats.rx_length_errors++;
095098e1
TK		 1408 if (status & BD_ENET_RX_LAST)
1409 netdev_err(ndev, "rcv is not +last\n");
22f6b860 1410 }
22f6b860 1411 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1412 ndev->stats.rx_crc_errors++;
095098e1
TK		 1413 /* Report late collisions as a frame error. */
1414 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1415 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1416 goto rx_processing_done;
1417 }
1da177e4 1418
22f6b860 1419 /* Process the incoming frame. */
c556167f 1420 ndev->stats.rx_packets++;
5cfa3039 1421 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
c556167f 1422 ndev->stats.rx_bytes += pkt_len;
1da177e4 1423
7355f276 1424 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1b7bde6d 1425 skb = rxq->rx_skbuff[index];
ccdc4f19 1426
1b7bde6d
NA		 1427 /* The packet length includes FCS, but we don't want to
1428 * include that when passing upstream as it messes up
1429 * bridging applications.
1430 */
1310b544
LW		 1431 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1432 need_swap);
1b7bde6d
NA		 1433 if (!is_copybreak) {
1434 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1435 if (unlikely(!skb_new)) {
1436 ndev->stats.rx_dropped++;
1437 goto rx_processing_done;
1438 }
5cfa3039
JB		 1439 dma_unmap_single(&fep->pdev->dev,
1440 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1441 FEC_ENET_RX_FRSIZE - fep->rx_align,
1442 DMA_FROM_DEVICE);
1443 }
1444
1445 prefetch(skb->data - NET_IP_ALIGN);
1446 skb_put(skb, pkt_len - 4);
1447 data = skb->data;
3ac72b7b 1448
235bde1e
FE		 1449 if (!is_copybreak && need_swap)
1450 swap_buffer(data, pkt_len);
1451
3ac72b7b
EN		 1452#if !defined(CONFIG_M5272)
1453 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1454 data = skb_pull_inline(skb, 2);
1455#endif
1456
cdffcf1b
JB		 1457 /* Extract the enhanced buffer descriptor */
1458 ebdp = NULL;
1459 if (fep->bufdesc_ex)
1460 ebdp = (struct bufdesc_ex *)bdp;
1461
1462 /* If this is a VLAN packet remove the VLAN Tag */
1463 vlan_packet_rcvd = false;
1464 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
5cfa3039
JB		 1465 fep->bufdesc_ex &&
1466 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
cdffcf1b
JB		 1467 /* Push and remove the vlan tag */
1468 struct vlan_hdr *vlan_header =
1469 (struct vlan_hdr *) (data + ETH_HLEN);
1470 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
cdffcf1b
JB		 1471
1472 vlan_packet_rcvd = true;
1b7bde6d 1473
af5cbc98 1474 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1b7bde6d 1475 skb_pull(skb, VLAN_HLEN);
cdffcf1b
JB		 1476 }
1477
1b7bde6d 1478 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 1479
1b7bde6d
NA		 1480 /* Get receive timestamp from the skb */
1481 if (fep->hwts_rx_en && fep->bufdesc_ex)
5cfa3039 1482 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1b7bde6d
NA		 1483 skb_hwtstamps(skb));
1484
1485 if (fep->bufdesc_ex &&
1486 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
5cfa3039 1487 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1b7bde6d
NA		 1488 /* don't check it */
1489 skb->ip_summed = CHECKSUM_UNNECESSARY;
1490 } else {
1491 skb_checksum_none_assert(skb);
4c09eed9 1492 }
1b7bde6d 1493 }
4c09eed9 1494
1b7bde6d
NA		 1495 /* Handle received VLAN packets */
1496 if (vlan_packet_rcvd)
1497 __vlan_hwaccel_put_tag(skb,
1498 htons(ETH_P_8021Q),
1499 vlan_tag);
cdffcf1b 1500
1b7bde6d
NA		 1501 napi_gro_receive(&fep->napi, skb);
1502
1503 if (is_copybreak) {
5cfa3039
JB		 1504 dma_sync_single_for_device(&fep->pdev->dev,
1505 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1506 FEC_ENET_RX_FRSIZE - fep->rx_align,
1507 DMA_FROM_DEVICE);
1508 } else {
1509 rxq->rx_skbuff[index] = skb_new;
1510 fec_enet_new_rxbdp(ndev, bdp, skb_new);
22f6b860 1511 }
f0b3fbea 1512
22f6b860
SH		 1513rx_processing_done:
1514 /* Clear the status flags for this buffer */
1515 status &= ~BD_ENET_RX_STATS;
1da177e4 1516
22f6b860
SH		 1517 /* Mark the buffer empty */
1518 status |= BD_ENET_RX_EMPTY;
6aa20a22 1519
ff43da86
FL		 1520 if (fep->bufdesc_ex) {
1521 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1522
5cfa3039 1523 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 1524 ebdp->cbd_prot = 0;
1525 ebdp->cbd_bdu = 0;
1526 }
be293467
TK		 1527 /* Make sure the updates to rest of the descriptor are
1528 * performed before transferring ownership.
1529 */
1530 wmb();
1531 bdp->cbd_sc = cpu_to_fec16(status);
6605b730 1532
22f6b860 1533 /* Update BD pointer to next entry */
7355f276 1534 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
36e24e2e 1535
22f6b860
SH		 1536 /* Doing this here will keep the FEC running while we process
1537 * incoming frames. On a heavily loaded network, we should be
1538 * able to keep up at the expense of system resources.
1539 */
53bb20d1 1540 writel(0, rxq->bd.reg_desc_active);
22f6b860 1541 }
7355f276 1542 rxq->bd.cur = bdp;
4d494cdc
FD		 1543 return pkt_received;
1544}
1da177e4 1545
4d494cdc
FD		 1546static int
1547fec_enet_rx(struct net_device *ndev, int budget)
1548{
1549 int pkt_received = 0;
1550 u16 queue_id;
1551 struct fec_enet_private *fep = netdev_priv(ndev);
1552
1553 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1c021bb7
UKK		 1554 int ret;
1555
1556 ret = fec_enet_rx_queue(ndev,
4d494cdc 1557 budget - pkt_received, queue_id);
1c021bb7
UKK		 1558
1559 if (ret < budget - pkt_received)
1560 clear_bit(queue_id, &fep->work_rx);
1561
1562 pkt_received += ret;
4d494cdc 1563 }
dc975382 1564 return pkt_received;
1da177e4
LT		 1565}
1566
4d494cdc
FD		 1567static bool
1568fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1569{
1570 if (int_events == 0)
1571 return false;
1572
5e62d98c 1573 if (int_events & FEC_ENET_RXF_0)
4d494cdc 1574 fep->work_rx |= (1 << 2);
ce99d0d3
FL		 1575 if (int_events & FEC_ENET_RXF_1)
1576 fep->work_rx |= (1 << 0);
1577 if (int_events & FEC_ENET_RXF_2)
1578 fep->work_rx |= (1 << 1);
4d494cdc 1579
5e62d98c 1580 if (int_events & FEC_ENET_TXF_0)
4d494cdc 1581 fep->work_tx |= (1 << 2);
ce99d0d3
FL		 1582 if (int_events & FEC_ENET_TXF_1)
1583 fep->work_tx |= (1 << 0);
1584 if (int_events & FEC_ENET_TXF_2)
1585 fep->work_tx |= (1 << 1);
4d494cdc
FD		 1586
1587 return true;
1588}
1589
45993653
UKK		 1590static irqreturn_t
1591fec_enet_interrupt(int irq, void *dev_id)
1592{
1593 struct net_device *ndev = dev_id;
1594 struct fec_enet_private *fep = netdev_priv(ndev);
1595 uint int_events;
1596 irqreturn_t ret = IRQ_NONE;
1597
7a16807c 1598 int_events = readl(fep->hwp + FEC_IEVENT);
94191fd6 1599 writel(int_events, fep->hwp + FEC_IEVENT);
4d494cdc 1600 fec_enet_collect_events(fep, int_events);
45993653 1601
61615cd2 1602 if ((fep->work_tx || fep->work_rx) && fep->link) {
7a16807c 1603 ret = IRQ_HANDLED;
dc975382 1604
94191fd6
NA		 1605 if (napi_schedule_prep(&fep->napi)) {
1606 /* Disable the NAPI interrupts */
80dc6a9f 1607 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
94191fd6
NA		 1608 __napi_schedule(&fep->napi);
1609 }
7a16807c 1610 }
45993653 1611
7a16807c
RK		 1612 if (int_events & FEC_ENET_MII) {
1613 ret = IRQ_HANDLED;
1614 complete(&fep->mdio_done);
1615 }
45993653
UKK		 1616 return ret;
1617}
1618
dc975382
FL		 1619static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1620{
1621 struct net_device *ndev = napi->dev;
dc975382 1622 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1623 int pkts;
1624
7a16807c 1625 pkts = fec_enet_rx(ndev, budget);
45993653 1626
de5fb0a0
FL		 1627 fec_enet_tx(ndev);
1628
dc975382 1629 if (pkts < budget) {
6ad20165 1630 napi_complete_done(napi, pkts);
dc975382
FL		 1631 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1632 }
1633 return pkts;
1634}
45993653 1635
e6b043d5 1636/* ------------------------------------------------------------------------- */
0c7768a0 1637static void fec_get_mac(struct net_device *ndev)
1da177e4 1638{
c556167f 1639 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1640 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1641 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1642
49da97dc
SG		 1643 /*
1644 * try to get mac address in following order:
1645 *
1646 * 1) module parameter via kernel command line in form
1647 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1648 */
1649 iap = macaddr;
1650
ca2cc333
SG		 1651 /*
1652 * 2) from device tree data
1653 */
1654 if (!is_valid_ether_addr(iap)) {
1655 struct device_node *np = fep->pdev->dev.of_node;
1656 if (np) {
1657 const char *mac = of_get_mac_address(np);
1658 if (mac)
1659 iap = (unsigned char *) mac;
1660 }
1661 }
ca2cc333 1662
49da97dc 1663 /*
ca2cc333 1664 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1665 */
1666 if (!is_valid_ether_addr(iap)) {
1667#ifdef CONFIG_M5272
1668 if (FEC_FLASHMAC)
1669 iap = (unsigned char *)FEC_FLASHMAC;
1670#else
1671 if (pdata)
589efdc7 1672 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1673#endif
1674 }
1675
1676 /*
ca2cc333 1677 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1678 */
1679 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1680 *((__be32 *) &tmpaddr[0]) =
1681 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1682 *((__be16 *) &tmpaddr[4]) =
1683 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1684 iap = &tmpaddr[0];
1da177e4
LT		 1685 }
1686
ff5b2fab
LS		 1687 /*
1688 * 5) random mac address
1689 */
1690 if (!is_valid_ether_addr(iap)) {
1691 /* Report it and use a random ethernet address instead */
1692 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1693 eth_hw_addr_random(ndev);
1694 netdev_info(ndev, "Using random MAC address: %pM\n",
1695 ndev->dev_addr);
1696 return;
1697 }
1698
c556167f 1699 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1700
49da97dc
SG		 1701 /* Adjust MAC if using macaddr */
1702 if (iap == macaddr)
43af940c 1703 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1704}
1705
e6b043d5 1706/* ------------------------------------------------------------------------- */
1da177e4 1707
e6b043d5
BW		 1708/*
1709 * Phy section
1710 */
c556167f 1711static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1712{
c556167f 1713 struct fec_enet_private *fep = netdev_priv(ndev);
45f5c327 1714 struct phy_device *phy_dev = ndev->phydev;
e6b043d5 1715 int status_change = 0;
1da177e4 1716
8ce5624f
RK		 1717 /*
1718 * If the netdev is down, or is going down, we're not interested
1719 * in link state events, so just mark our idea of the link as down
1720 * and ignore the event.
1721 */
1722 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1723 fep->link = 0;
1724 } else if (phy_dev->link) {
d97e7497 1725 if (!fep->link) {
6ea0722f 1726 fep->link = phy_dev->link;
e6b043d5
BW		 1727 status_change = 1;
1728 }
1da177e4 1729
ef83337d
RK		 1730 if (fep->full_duplex != phy_dev->duplex) {
1731 fep->full_duplex = phy_dev->duplex;
d97e7497 1732 status_change = 1;
ef83337d 1733 }
d97e7497
LS		 1734
1735 if (phy_dev->speed != fep->speed) {
1736 fep->speed = phy_dev->speed;
1737 status_change = 1;
1738 }
1739
1740 /* if any of the above changed restart the FEC */
dbc64a8e 1741 if (status_change) {
dbc64a8e 1742 napi_disable(&fep->napi);
dbc64a8e 1743 netif_tx_lock_bh(ndev);
ef83337d 1744 fec_restart(ndev);
657ade07 1745 netif_tx_wake_all_queues(ndev);
6af42d42 1746 netif_tx_unlock_bh(ndev);
dbc64a8e 1747 napi_enable(&fep->napi);
dbc64a8e 1748 }
d97e7497
LS		 1749 } else {
1750 if (fep->link) {
f208ce10
RK		 1751 napi_disable(&fep->napi);
1752 netif_tx_lock_bh(ndev);
c556167f 1753 fec_stop(ndev);
f208ce10
RK		 1754 netif_tx_unlock_bh(ndev);
1755 napi_enable(&fep->napi);
8d7ed0f0 1756 fep->link = phy_dev->link;
d97e7497
LS		 1757 status_change = 1;
1758 }
1da177e4 1759 }
6aa20a22 1760
e6b043d5
BW		 1761 if (status_change)
1762 phy_print_status(phy_dev);
1763}
1da177e4 1764
e6b043d5 1765static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1766{
e6b043d5 1767 struct fec_enet_private *fep = bus->priv;
8fff755e 1768 struct device *dev = &fep->pdev->dev;
97b72e43 1769 unsigned long time_left;
8fff755e
AL		 1770 int ret = 0;
1771
1772 ret = pm_runtime_get_sync(dev);
b0c6ce24 1773 if (ret < 0)
8fff755e 1774 return ret;
1da177e4 1775
aac27c7a 1776 reinit_completion(&fep->mdio_done);
e6b043d5
BW		 1777
1778 /* start a read op */
1779 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1780 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1781 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1782
1783 /* wait for end of transfer */
97b72e43
BS		 1784 time_left = wait_for_completion_timeout(&fep->mdio_done,
1785 usecs_to_jiffies(FEC_MII_TIMEOUT));
1786 if (time_left == 0) {
31b7720c 1787 netdev_err(fep->netdev, "MDIO read timeout\n");
8fff755e
AL		 1788 ret = -ETIMEDOUT;
1789 goto out;
1da177e4 1790 }
1da177e4 1791
8fff755e
AL		 1792 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1793
1794out:
1795 pm_runtime_mark_last_busy(dev);
1796 pm_runtime_put_autosuspend(dev);
1797
1798 return ret;
7dd6a2aa 1799}
6aa20a22 1800
e6b043d5
BW		 1801static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1802 u16 value)
1da177e4 1803{
e6b043d5 1804 struct fec_enet_private *fep = bus->priv;
8fff755e 1805 struct device *dev = &fep->pdev->dev;
97b72e43 1806 unsigned long time_left;
42ea4457 1807 int ret;
8fff755e
AL		 1808
1809 ret = pm_runtime_get_sync(dev);
b0c6ce24 1810 if (ret < 0)
8fff755e 1811 return ret;
42ea4457
MS		 1812 else
1813 ret = 0;
1da177e4 1814
aac27c7a 1815 reinit_completion(&fep->mdio_done);
1da177e4 1816
862f0982
SG		 1817 /* start a write op */
1818 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1819 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1820 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1821 fep->hwp + FEC_MII_DATA);
1822
1823 /* wait for end of transfer */
97b72e43
BS		 1824 time_left = wait_for_completion_timeout(&fep->mdio_done,
1825 usecs_to_jiffies(FEC_MII_TIMEOUT));
1826 if (time_left == 0) {
31b7720c 1827 netdev_err(fep->netdev, "MDIO write timeout\n");
8fff755e 1828 ret = -ETIMEDOUT;
e6b043d5 1829 }
1da177e4 1830
8fff755e
AL		 1831 pm_runtime_mark_last_busy(dev);
1832 pm_runtime_put_autosuspend(dev);
1833
1834 return ret;
e6b043d5 1835}
1da177e4 1836
e8fcfcd5
NA		 1837static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1838{
1839 struct fec_enet_private *fep = netdev_priv(ndev);
1840 int ret;
1841
1842 if (enable) {
1843 ret = clk_prepare_enable(fep->clk_ahb);
1844 if (ret)
1845 return ret;
01e5943a
UKK		 1846
1847 ret = clk_prepare_enable(fep->clk_enet_out);
1848 if (ret)
1849 goto failed_clk_enet_out;
1850
e8fcfcd5 1851 if (fep->clk_ptp) {
91c0d987 1852 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1853 ret = clk_prepare_enable(fep->clk_ptp);
91c0d987
NA		 1854 if (ret) {
1855 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1856 goto failed_clk_ptp;
91c0d987
NA		 1857 } else {
1858 fep->ptp_clk_on = true;
1859 }
1860 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1861 }
01e5943a
UKK		 1862
1863 ret = clk_prepare_enable(fep->clk_ref);
1864 if (ret)
1865 goto failed_clk_ref;
1b0a83ac
RL		 1866
1867 phy_reset_after_clk_enable(ndev->phydev);
e8fcfcd5
NA		 1868 } else {
1869 clk_disable_unprepare(fep->clk_ahb);
01e5943a 1870 clk_disable_unprepare(fep->clk_enet_out);
91c0d987
NA		 1871 if (fep->clk_ptp) {
1872 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1873 clk_disable_unprepare(fep->clk_ptp);
91c0d987
NA		 1874 fep->ptp_clk_on = false;
1875 mutex_unlock(&fep->ptp_clk_mutex);
1876 }
01e5943a 1877 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1878 }
1879
1880 return 0;
9b5330ed
FD		 1881
1882failed_clk_ref:
1883 if (fep->clk_ref)
1884 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1885failed_clk_ptp:
1886 if (fep->clk_enet_out)
1887 clk_disable_unprepare(fep->clk_enet_out);
1888failed_clk_enet_out:
e8fcfcd5
NA		 1889 clk_disable_unprepare(fep->clk_ahb);
1890
1891 return ret;
1892}
1893
c556167f 1894static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1895{
c556167f 1896 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1897 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1898 char mdio_bus_id[MII_BUS_ID_SIZE];
1899 char phy_name[MII_BUS_ID_SIZE + 3];
1900 int phy_id;
43af940c 1901 int dev_id = fep->dev_id;
562d2f8c 1902
407066f8
UKK		 1903 if (fep->phy_node) {
1904 phy_dev = of_phy_connect(ndev, fep->phy_node,
1905 &fec_enet_adjust_link, 0,
1906 fep->phy_interface);
9558df3a
AL		 1907 if (!phy_dev) {
1908 netdev_err(ndev, "Unable to connect to phy\n");
213a9922 1909 return -ENODEV;
9558df3a 1910 }
407066f8
UKK		 1911 } else {
1912 /* check for attached phy */
1913 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
7f854420 1914 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
407066f8
UKK		 1915 continue;
1916 if (dev_id--)
1917 continue;
949bdd20 1918 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
407066f8
UKK		 1919 break;
1920 }
1da177e4 1921
407066f8
UKK		 1922 if (phy_id >= PHY_MAX_ADDR) {
1923 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
949bdd20 1924 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
407066f8
UKK		 1925 phy_id = 0;
1926 }
1927
1928 snprintf(phy_name, sizeof(phy_name),
1929 PHY_ID_FMT, mdio_bus_id, phy_id);
1930 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1931 fep->phy_interface);
6fcc040f
GU		 1932 }
1933
6fcc040f 1934 if (IS_ERR(phy_dev)) {
31b7720c 1935 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1936 return PTR_ERR(phy_dev);
e6b043d5 1937 }
1da177e4 1938
e6b043d5 1939 /* mask with MAC supported features */
6b7e4008 1940 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
58056c1e 1941 phy_set_max_speed(phy_dev, 1000);
41124fa6
AL		 1942 phy_remove_link_mode(phy_dev,
1943 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
d1391930 1944#if !defined(CONFIG_M5272)
c306ad36 1945 phy_support_sym_pause(phy_dev);
d1391930 1946#endif
baa70a5c 1947 }
230dec61 1948 else
58056c1e 1949 phy_set_max_speed(phy_dev, 100);
230dec61 1950
e6b043d5
BW		 1951 fep->link = 0;
1952 fep->full_duplex = 0;
1da177e4 1953
2220943a 1954 phy_attached_info(phy_dev);
418bd0d4 1955
e6b043d5 1956 return 0;
1da177e4
LT		 1957}
1958
e6b043d5 1959static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1960{
b5680e0b 1961 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1962 struct net_device *ndev = platform_get_drvdata(pdev);
1963 struct fec_enet_private *fep = netdev_priv(ndev);
407066f8 1964 struct device_node *node;
e7f4dc35 1965 int err = -ENXIO;
63c60732 1966 u32 mii_speed, holdtime;
6b265293 1967
b5680e0b 1968 /*
3d125f9c 1969 * The i.MX28 dual fec interfaces are not equal.
b5680e0b
SG		 1970 * Here are the differences:
1971 *
1972 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1973 * - fec0 acts as the 1588 time master while fec1 is slave
1974 * - external phys can only be configured by fec0
1975 *
1976 * That is to say fec1 can not work independently. It only works
1977 * when fec0 is working. The reason behind this design is that the
1978 * second interface is added primarily for Switch mode.
1979 *
1980 * Because of the last point above, both phys are attached on fec0
1981 * mdio interface in board design, and need to be configured by
1982 * fec0 mii_bus.
1983 */
3d125f9c 1984 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
b5680e0b 1985 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 1986 if (mii_cnt && fec0_mii_bus) {
1987 fep->mii_bus = fec0_mii_bus;
1988 mii_cnt++;
1989 return 0;
1990 }
1991 return -ENOENT;
b5680e0b
SG		 1992 }
1993
e6b043d5
BW		 1994 /*
1995 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 1996 *
1997 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1998 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1999 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2000 * document.
e6b043d5 2001 */
63c60732 2002 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
6b7e4008 2003 if (fep->quirks & FEC_QUIRK_ENET_MAC)
63c60732
UKK		 2004 mii_speed--;
2005 if (mii_speed > 63) {
2006 dev_err(&pdev->dev,
981a0547 2007 "fec clock (%lu) too fast to get right mii speed\n",
63c60732
UKK		 2008 clk_get_rate(fep->clk_ipg));
2009 err = -EINVAL;
2010 goto err_out;
2011 }
2012
2013 /*
2014 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2015 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2016 * versions are RAZ there, so just ignore the difference and write the
2017 * register always.
2018 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2019 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2020 * output.
2021 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2022 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2023 * holdtime cannot result in a value greater than 3.
2024 */
2025 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2026
2027 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2028
e6b043d5 2029 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 2030
e6b043d5
BW		 2031 fep->mii_bus = mdiobus_alloc();
2032 if (fep->mii_bus == NULL) {
2033 err = -ENOMEM;
2034 goto err_out;
1da177e4
LT		 2035 }
2036
e6b043d5
BW		 2037 fep->mii_bus->name = "fec_enet_mii_bus";
2038 fep->mii_bus->read = fec_enet_mdio_read;
2039 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 2040 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2041 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 2042 fep->mii_bus->priv = fep;
2043 fep->mii_bus->parent = &pdev->dev;
2044
407066f8 2045 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
00e798c7 2046 err = of_mdiobus_register(fep->mii_bus, node);
a4ebec03 2047 of_node_put(node);
407066f8 2048 if (err)
e7f4dc35 2049 goto err_out_free_mdiobus;
1da177e4 2050
e163cc97
LW		 2051 mii_cnt++;
2052
b5680e0b 2053 /* save fec0 mii_bus */
3d125f9c 2054 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
b5680e0b
SG		 2055 fec0_mii_bus = fep->mii_bus;
2056
e6b043d5 2057 return 0;
1da177e4 2058
e6b043d5
BW		 2059err_out_free_mdiobus:
2060 mdiobus_free(fep->mii_bus);
2061err_out:
2062 return err;
1da177e4
LT		 2063}
2064
e6b043d5 2065static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 2066{
e163cc97
LW		 2067 if (--mii_cnt == 0) {
2068 mdiobus_unregister(fep->mii_bus);
e163cc97
LW		 2069 mdiobus_free(fep->mii_bus);
2070 }
1da177e4
LT		 2071}
2072
c556167f 2073static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 2074 struct ethtool_drvinfo *info)
1da177e4 2075{
c556167f 2076 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 2077
7826d43f
JP		 2078 strlcpy(info->driver, fep->pdev->dev.driver->name,
2079 sizeof(info->driver));
2080 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2081 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 2082}
2083
db65f35f
PR		 2084static int fec_enet_get_regs_len(struct net_device *ndev)
2085{
2086 struct fec_enet_private *fep = netdev_priv(ndev);
2087 struct resource *r;
2088 int s = 0;
2089
2090 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2091 if (r)
2092 s = resource_size(r);
2093
2094 return s;
2095}
2096
2097/* List of registers that can be safety be read to dump them with ethtool */
2098#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
3f1dcc6a 2099 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
78cc6e7e 2100 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
f9bcc9f3 2101static __u32 fec_enet_register_version = 2;
db65f35f
PR		 2102static u32 fec_enet_register_offset[] = {
2103 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2104 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2105 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2106 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2107 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2108 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2109 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2110 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2111 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2112 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2113 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2114 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2115 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2116 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2117 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2118 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2119 RMON_T_P_GTE2048, RMON_T_OCTETS,
2120 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2121 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2122 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2123 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2124 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2125 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2126 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2127 RMON_R_P_GTE2048, RMON_R_OCTETS,
2128 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2129 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2130};
2131#else
f9bcc9f3 2132static __u32 fec_enet_register_version = 1;
db65f35f
PR		 2133static u32 fec_enet_register_offset[] = {
2134 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2135 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2136 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2137 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2138 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2139 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2140 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2141 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2142 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2143};
2144#endif
2145
2146static void fec_enet_get_regs(struct net_device *ndev,
2147 struct ethtool_regs *regs, void *regbuf)
2148{
2149 struct fec_enet_private *fep = netdev_priv(ndev);
2150 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2151 u32 *buf = (u32 *)regbuf;
2152 u32 i, off;
2153
f9bcc9f3
VD		 2154 regs->version = fec_enet_register_version;
2155
db65f35f
PR		 2156 memset(buf, 0, regs->len);
2157
2158 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
ec20a63a
FD		 2159 off = fec_enet_register_offset[i];
2160
2161 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2162 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2163 continue;
2164
2165 off >>= 2;
db65f35f
PR		 2166 buf[off] = readl(&theregs[off]);
2167 }
2168}
2169
5ebae489
FL		 2170static int fec_enet_get_ts_info(struct net_device *ndev,
2171 struct ethtool_ts_info *info)
2172{
2173 struct fec_enet_private *fep = netdev_priv(ndev);
2174
2175 if (fep->bufdesc_ex) {
2176
2177 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2178 SOF_TIMESTAMPING_RX_SOFTWARE |
2179 SOF_TIMESTAMPING_SOFTWARE |
2180 SOF_TIMESTAMPING_TX_HARDWARE |
2181 SOF_TIMESTAMPING_RX_HARDWARE |
2182 SOF_TIMESTAMPING_RAW_HARDWARE;
2183 if (fep->ptp_clock)
2184 info->phc_index = ptp_clock_index(fep->ptp_clock);
2185 else
2186 info->phc_index = -1;
2187
2188 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2189 (1 << HWTSTAMP_TX_ON);
2190
2191 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2192 (1 << HWTSTAMP_FILTER_ALL);
2193 return 0;
2194 } else {
2195 return ethtool_op_get_ts_info(ndev, info);
2196 }
2197}
2198
d1391930
GR		 2199#if !defined(CONFIG_M5272)
2200
baa70a5c
FL		 2201static void fec_enet_get_pauseparam(struct net_device *ndev,
2202 struct ethtool_pauseparam *pause)
2203{
2204 struct fec_enet_private *fep = netdev_priv(ndev);
2205
2206 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2207 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2208 pause->rx_pause = pause->tx_pause;
2209}
2210
2211static int fec_enet_set_pauseparam(struct net_device *ndev,
2212 struct ethtool_pauseparam *pause)
2213{
2214 struct fec_enet_private *fep = netdev_priv(ndev);
2215
45f5c327 2216 if (!ndev->phydev)
0b146ca8
RK		 2217 return -ENODEV;
2218
baa70a5c
FL		 2219 if (pause->tx_pause != pause->rx_pause) {
2220 netdev_info(ndev,
2221 "hardware only support enable/disable both tx and rx");
2222 return -EINVAL;
2223 }
2224
2225 fep->pause_flag = 0;
2226
2227 /* tx pause must be same as rx pause */
2228 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2229 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2230
0c122405
AL		 2231 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2232 pause->autoneg);
baa70a5c
FL		 2233
2234 if (pause->autoneg) {
2235 if (netif_running(ndev))
2236 fec_stop(ndev);
45f5c327 2237 phy_start_aneg(ndev->phydev);
baa70a5c 2238 }
dbc64a8e 2239 if (netif_running(ndev)) {
dbc64a8e 2240 napi_disable(&fep->napi);
dbc64a8e 2241 netif_tx_lock_bh(ndev);
ef83337d 2242 fec_restart(ndev);
657ade07 2243 netif_tx_wake_all_queues(ndev);
6af42d42 2244 netif_tx_unlock_bh(ndev);
dbc64a8e 2245 napi_enable(&fep->napi);
dbc64a8e 2246 }
baa70a5c
FL		 2247
2248 return 0;
2249}
2250
38ae92dc
CH		 2251static const struct fec_stat {
2252 char name[ETH_GSTRING_LEN];
2253 u16 offset;
2254} fec_stats[] = {
2255 /* RMON TX */
2256 { "tx_dropped", RMON_T_DROP },
2257 { "tx_packets", RMON_T_PACKETS },
2258 { "tx_broadcast", RMON_T_BC_PKT },
2259 { "tx_multicast", RMON_T_MC_PKT },
2260 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2261 { "tx_undersize", RMON_T_UNDERSIZE },
2262 { "tx_oversize", RMON_T_OVERSIZE },
2263 { "tx_fragment", RMON_T_FRAG },
2264 { "tx_jabber", RMON_T_JAB },
2265 { "tx_collision", RMON_T_COL },
2266 { "tx_64byte", RMON_T_P64 },
2267 { "tx_65to127byte", RMON_T_P65TO127 },
2268 { "tx_128to255byte", RMON_T_P128TO255 },
2269 { "tx_256to511byte", RMON_T_P256TO511 },
2270 { "tx_512to1023byte", RMON_T_P512TO1023 },
2271 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2272 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2273 { "tx_octets", RMON_T_OCTETS },
2274
2275 /* IEEE TX */
2276 { "IEEE_tx_drop", IEEE_T_DROP },
2277 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2278 { "IEEE_tx_1col", IEEE_T_1COL },
2279 { "IEEE_tx_mcol", IEEE_T_MCOL },
2280 { "IEEE_tx_def", IEEE_T_DEF },
2281 { "IEEE_tx_lcol", IEEE_T_LCOL },
2282 { "IEEE_tx_excol", IEEE_T_EXCOL },
2283 { "IEEE_tx_macerr", IEEE_T_MACERR },
2284 { "IEEE_tx_cserr", IEEE_T_CSERR },
2285 { "IEEE_tx_sqe", IEEE_T_SQE },
2286 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2287 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2288
2289 /* RMON RX */
2290 { "rx_packets", RMON_R_PACKETS },
2291 { "rx_broadcast", RMON_R_BC_PKT },
2292 { "rx_multicast", RMON_R_MC_PKT },
2293 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2294 { "rx_undersize", RMON_R_UNDERSIZE },
2295 { "rx_oversize", RMON_R_OVERSIZE },
2296 { "rx_fragment", RMON_R_FRAG },
2297 { "rx_jabber", RMON_R_JAB },
2298 { "rx_64byte", RMON_R_P64 },
2299 { "rx_65to127byte", RMON_R_P65TO127 },
2300 { "rx_128to255byte", RMON_R_P128TO255 },
2301 { "rx_256to511byte", RMON_R_P256TO511 },
2302 { "rx_512to1023byte", RMON_R_P512TO1023 },
2303 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2304 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2305 { "rx_octets", RMON_R_OCTETS },
2306
2307 /* IEEE RX */
2308 { "IEEE_rx_drop", IEEE_R_DROP },
2309 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2310 { "IEEE_rx_crc", IEEE_R_CRC },
2311 { "IEEE_rx_align", IEEE_R_ALIGN },
2312 { "IEEE_rx_macerr", IEEE_R_MACERR },
2313 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2314 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2315};
2316
f85de666
NY		 2317#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2318
80cca775 2319static void fec_enet_update_ethtool_stats(struct net_device *dev)
38ae92dc
CH		 2320{
2321 struct fec_enet_private *fep = netdev_priv(dev);
2322 int i;
2323
2324 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
80cca775
NY		 2325 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2326}
2327
2328static void fec_enet_get_ethtool_stats(struct net_device *dev,
2329 struct ethtool_stats *stats, u64 *data)
2330{
2331 struct fec_enet_private *fep = netdev_priv(dev);
2332
2333 if (netif_running(dev))
2334 fec_enet_update_ethtool_stats(dev);
2335
f85de666 2336 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
38ae92dc
CH		 2337}
2338
2339static void fec_enet_get_strings(struct net_device *netdev,
2340 u32 stringset, u8 *data)
2341{
2342 int i;
2343 switch (stringset) {
2344 case ETH_SS_STATS:
2345 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2346 memcpy(data + i * ETH_GSTRING_LEN,
2347 fec_stats[i].name, ETH_GSTRING_LEN);
2348 break;
2349 }
2350}
2351
2352static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2353{
2354 switch (sset) {
2355 case ETH_SS_STATS:
2356 return ARRAY_SIZE(fec_stats);
2357 default:
2358 return -EOPNOTSUPP;
2359 }
2360}
f85de666 2361
2b30842b
AL		 2362static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2363{
2364 struct fec_enet_private *fep = netdev_priv(dev);
2365 int i;
2366
2367 /* Disable MIB statistics counters */
2368 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2369
2370 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2371 writel(0, fep->hwp + fec_stats[i].offset);
2372
2373 /* Don't disable MIB statistics counters */
2374 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2375}
2376
f85de666
NY		 2377#else /* !defined(CONFIG_M5272) */
2378#define FEC_STATS_SIZE 0
2379static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2380{
2381}
41e8e404
FE		 2382
2383static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2384{
2385}
d1391930 2386#endif /* !defined(CONFIG_M5272) */
38ae92dc 2387
d851b47b
FD		 2388/* ITR clock source is enet system clock (clk_ahb).
2389 * TCTT unit is cycle_ns * 64 cycle
2390 * So, the ICTT value = X us / (cycle_ns * 64)
2391 */
2392static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2393{
2394 struct fec_enet_private *fep = netdev_priv(ndev);
2395
2396 return us * (fep->itr_clk_rate / 64000) / 1000;
2397}
2398
2399/* Set threshold for interrupt coalescing */
2400static void fec_enet_itr_coal_set(struct net_device *ndev)
2401{
2402 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2403 int rx_itr, tx_itr;
2404
d851b47b
FD		 2405 /* Must be greater than zero to avoid unpredictable behavior */
2406 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2407 !fep->tx_time_itr || !fep->tx_pkts_itr)
2408 return;
2409
2410 /* Select enet system clock as Interrupt Coalescing
2411 * timer Clock Source
2412 */
2413 rx_itr = FEC_ITR_CLK_SEL;
2414 tx_itr = FEC_ITR_CLK_SEL;
2415
2416 /* set ICFT and ICTT */
2417 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2418 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2419 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2420 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2421
2422 rx_itr |= FEC_ITR_EN;
2423 tx_itr |= FEC_ITR_EN;
2424
2425 writel(tx_itr, fep->hwp + FEC_TXIC0);
2426 writel(rx_itr, fep->hwp + FEC_RXIC0);
ff7566b8
FD		 2427 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2428 writel(tx_itr, fep->hwp + FEC_TXIC1);
2429 writel(rx_itr, fep->hwp + FEC_RXIC1);
2430 writel(tx_itr, fep->hwp + FEC_TXIC2);
2431 writel(rx_itr, fep->hwp + FEC_RXIC2);
2432 }
d851b47b
FD		 2433}
2434
2435static int
2436fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2437{
2438 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b 2439
ff7566b8 2440 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
d851b47b
FD		 2441 return -EOPNOTSUPP;
2442
2443 ec->rx_coalesce_usecs = fep->rx_time_itr;
2444 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2445
2446 ec->tx_coalesce_usecs = fep->tx_time_itr;
2447 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2448
2449 return 0;
2450}
2451
2452static int
2453fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2454{
2455 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2456 unsigned int cycle;
2457
ff7566b8 2458 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
d851b47b
FD		 2459 return -EOPNOTSUPP;
2460
2461 if (ec->rx_max_coalesced_frames > 255) {
9f647a6d 2462 pr_err("Rx coalesced frames exceed hardware limitation\n");
d851b47b
FD		 2463 return -EINVAL;
2464 }
2465
2466 if (ec->tx_max_coalesced_frames > 255) {
9f647a6d 2467 pr_err("Tx coalesced frame exceed hardware limitation\n");
d851b47b
FD		 2468 return -EINVAL;
2469 }
2470
2471 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2472 if (cycle > 0xFFFF) {
9f647a6d 2473 pr_err("Rx coalesced usec exceed hardware limitation\n");
d851b47b
FD		 2474 return -EINVAL;
2475 }
2476
2477 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2478 if (cycle > 0xFFFF) {
9f647a6d 2479 pr_err("Rx coalesced usec exceed hardware limitation\n");
d851b47b
FD		 2480 return -EINVAL;
2481 }
2482
2483 fep->rx_time_itr = ec->rx_coalesce_usecs;
2484 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2485
2486 fep->tx_time_itr = ec->tx_coalesce_usecs;
2487 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2488
2489 fec_enet_itr_coal_set(ndev);
2490
2491 return 0;
2492}
2493
2494static void fec_enet_itr_coal_init(struct net_device *ndev)
2495{
2496 struct ethtool_coalesce ec;
2497
2498 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2499 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2500
2501 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2502 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2503
2504 fec_enet_set_coalesce(ndev, &ec);
2505}
2506
1b7bde6d
NA		 2507static int fec_enet_get_tunable(struct net_device *netdev,
2508 const struct ethtool_tunable *tuna,
2509 void *data)
2510{
2511 struct fec_enet_private *fep = netdev_priv(netdev);
2512 int ret = 0;
2513
2514 switch (tuna->id) {
2515 case ETHTOOL_RX_COPYBREAK:
2516 *(u32 *)data = fep->rx_copybreak;
2517 break;
2518 default:
2519 ret = -EINVAL;
2520 break;
2521 }
2522
2523 return ret;
2524}
2525
2526static int fec_enet_set_tunable(struct net_device *netdev,
2527 const struct ethtool_tunable *tuna,
2528 const void *data)
2529{
2530 struct fec_enet_private *fep = netdev_priv(netdev);
2531 int ret = 0;
2532
2533 switch (tuna->id) {
2534 case ETHTOOL_RX_COPYBREAK:
2535 fep->rx_copybreak = *(u32 *)data;
2536 break;
2537 default:
2538 ret = -EINVAL;
2539 break;
2540 }
2541
2542 return ret;
2543}
2544
de40ed31
NA		 2545static void
2546fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2547{
2548 struct fec_enet_private *fep = netdev_priv(ndev);
2549
2550 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2551 wol->supported = WAKE_MAGIC;
2552 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2553 } else {
2554 wol->supported = wol->wolopts = 0;
2555 }
2556}
2557
2558static int
2559fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2560{
2561 struct fec_enet_private *fep = netdev_priv(ndev);
2562
2563 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2564 return -EINVAL;
2565
2566 if (wol->wolopts & ~WAKE_MAGIC)
2567 return -EINVAL;
2568
2569 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2570 if (device_may_wakeup(&ndev->dev)) {
2571 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2572 if (fep->irq[0] > 0)
2573 enable_irq_wake(fep->irq[0]);
2574 } else {
2575 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2576 if (fep->irq[0] > 0)
2577 disable_irq_wake(fep->irq[0]);
2578 }
2579
2580 return 0;
2581}
2582
9b07be4b 2583static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5 2584 .get_drvinfo = fec_enet_get_drvinfo,
db65f35f
PR		 2585 .get_regs_len = fec_enet_get_regs_len,
2586 .get_regs = fec_enet_get_regs,
11d59289 2587 .nway_reset = phy_ethtool_nway_reset,
c1d7c48f 2588 .get_link = ethtool_op_get_link,
d851b47b
FD		 2589 .get_coalesce = fec_enet_get_coalesce,
2590 .set_coalesce = fec_enet_set_coalesce,
38ae92dc 2591#ifndef CONFIG_M5272
c1d7c48f
RK		 2592 .get_pauseparam = fec_enet_get_pauseparam,
2593 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2594 .get_strings = fec_enet_get_strings,
c1d7c48f 2595 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2596 .get_sset_count = fec_enet_get_sset_count,
2597#endif
c1d7c48f 2598 .get_ts_info = fec_enet_get_ts_info,
1b7bde6d
NA		 2599 .get_tunable = fec_enet_get_tunable,
2600 .set_tunable = fec_enet_set_tunable,
de40ed31
NA		 2601 .get_wol = fec_enet_get_wol,
2602 .set_wol = fec_enet_set_wol,
9365fbf5
PR		 2603 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2604 .set_link_ksettings = phy_ethtool_set_link_ksettings,
e6b043d5 2605};
1da177e4 2606
c556167f 2607static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2608{
c556167f 2609 struct fec_enet_private *fep = netdev_priv(ndev);
45f5c327 2610 struct phy_device *phydev = ndev->phydev;
1da177e4 2611
c556167f 2612 if (!netif_running(ndev))
e6b043d5 2613 return -EINVAL;
1da177e4 2614
e6b043d5
BW		 2615 if (!phydev)
2616 return -ENODEV;
2617
1d5244d0
BH		 2618 if (fep->bufdesc_ex) {
2619 if (cmd == SIOCSHWTSTAMP)
2620 return fec_ptp_set(ndev, rq);
2621 if (cmd == SIOCGHWTSTAMP)
2622 return fec_ptp_get(ndev, rq);
2623 }
ff43da86 2624
28b04113 2625 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2626}
2627
c556167f 2628static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2629{
c556167f 2630 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2631 unsigned int i;
f0b3fbea
SH		 2632 struct sk_buff *skb;
2633 struct bufdesc *bdp;
4d494cdc
FD		 2634 struct fec_enet_priv_tx_q *txq;
2635 struct fec_enet_priv_rx_q *rxq;
59d0f746
FL		 2636 unsigned int q;
2637
2638 for (q = 0; q < fep->num_rx_queues; q++) {
2639 rxq = fep->rx_queue[q];
7355f276
TK		 2640 bdp = rxq->bd.base;
2641 for (i = 0; i < rxq->bd.ring_size; i++) {
59d0f746
FL		 2642 skb = rxq->rx_skbuff[i];
2643 rxq->rx_skbuff[i] = NULL;
2644 if (skb) {
2645 dma_unmap_single(&fep->pdev->dev,
5cfa3039 2646 fec32_to_cpu(bdp->cbd_bufaddr),
b64bf4b7 2647 FEC_ENET_RX_FRSIZE - fep->rx_align,
59d0f746
FL		 2648 DMA_FROM_DEVICE);
2649 dev_kfree_skb(skb);
2650 }
7355f276 2651 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
59d0f746
FL		 2652 }
2653 }
4d494cdc 2654
59d0f746
FL		 2655 for (q = 0; q < fep->num_tx_queues; q++) {
2656 txq = fep->tx_queue[q];
7355f276
TK		 2657 bdp = txq->bd.base;
2658 for (i = 0; i < txq->bd.ring_size; i++) {
59d0f746
FL		 2659 kfree(txq->tx_bounce[i]);
2660 txq->tx_bounce[i] = NULL;
2661 skb = txq->tx_skbuff[i];
2662 txq->tx_skbuff[i] = NULL;
f0b3fbea 2663 dev_kfree_skb(skb);
730ee360 2664 }
f0b3fbea 2665 }
59d0f746 2666}
f0b3fbea 2667
59d0f746
FL		 2668static void fec_enet_free_queue(struct net_device *ndev)
2669{
2670 struct fec_enet_private *fep = netdev_priv(ndev);
2671 int i;
2672 struct fec_enet_priv_tx_q *txq;
2673
2674 for (i = 0; i < fep->num_tx_queues; i++)
2675 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2676 txq = fep->tx_queue[i];
94920128 2677 dma_free_coherent(&fep->pdev->dev,
7355f276 2678 txq->bd.ring_size * TSO_HEADER_SIZE,
59d0f746
FL		 2679 txq->tso_hdrs,
2680 txq->tso_hdrs_dma);
2681 }
2682
2683 for (i = 0; i < fep->num_rx_queues; i++)
1b4b32c6 2684 kfree(fep->rx_queue[i]);
59d0f746 2685 for (i = 0; i < fep->num_tx_queues; i++)
1b4b32c6 2686 kfree(fep->tx_queue[i]);
59d0f746
FL		 2687}
2688
2689static int fec_enet_alloc_queue(struct net_device *ndev)
2690{
2691 struct fec_enet_private *fep = netdev_priv(ndev);
2692 int i;
2693 int ret = 0;
2694 struct fec_enet_priv_tx_q *txq;
2695
2696 for (i = 0; i < fep->num_tx_queues; i++) {
2697 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2698 if (!txq) {
2699 ret = -ENOMEM;
2700 goto alloc_failed;
2701 }
2702
2703 fep->tx_queue[i] = txq;
7355f276
TK		 2704 txq->bd.ring_size = TX_RING_SIZE;
2705 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
59d0f746
FL		 2706
2707 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2708 txq->tx_wake_threshold =
7355f276 2709 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
59d0f746 2710
94920128 2711 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
7355f276 2712 txq->bd.ring_size * TSO_HEADER_SIZE,
59d0f746
FL		 2713 &txq->tso_hdrs_dma,
2714 GFP_KERNEL);
2715 if (!txq->tso_hdrs) {
2716 ret = -ENOMEM;
2717 goto alloc_failed;
2718 }
8b7c9efa 2719 }
59d0f746
FL		 2720
2721 for (i = 0; i < fep->num_rx_queues; i++) {
2722 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2723 GFP_KERNEL);
2724 if (!fep->rx_queue[i]) {
2725 ret = -ENOMEM;
2726 goto alloc_failed;
2727 }
2728
7355f276
TK		 2729 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2730 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
59d0f746
FL		 2731 }
2732 return ret;
2733
2734alloc_failed:
2735 fec_enet_free_queue(ndev);
2736 return ret;
f0b3fbea
SH		 2737}
2738
59d0f746
FL		 2739static int
2740fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
f0b3fbea 2741{
c556167f 2742 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2743 unsigned int i;
f0b3fbea
SH		 2744 struct sk_buff *skb;
2745 struct bufdesc *bdp;
4d494cdc 2746 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2747
59d0f746 2748 rxq = fep->rx_queue[queue];
7355f276
TK		 2749 bdp = rxq->bd.base;
2750 for (i = 0; i < rxq->bd.ring_size; i++) {
b72061a3 2751 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2752 if (!skb)
2753 goto err_alloc;
f0b3fbea 2754
1b7bde6d 2755 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
730ee360 2756 dev_kfree_skb(skb);
ffdce2cc 2757 goto err_alloc;
d842a31f 2758 }
730ee360 2759
4d494cdc 2760 rxq->rx_skbuff[i] = skb;
5cfa3039 2761 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
ff43da86
FL		 2762
2763 if (fep->bufdesc_ex) {
2764 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2765 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 2766 }
2767
7355f276 2768 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
f0b3fbea
SH		 2769 }
2770
2771 /* Set the last buffer to wrap. */
7355f276 2772 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
5cfa3039 2773 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 2774 return 0;
f0b3fbea 2775
59d0f746
FL		 2776 err_alloc:
2777 fec_enet_free_buffers(ndev);
2778 return -ENOMEM;
2779}
2780
2781static int
2782fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2783{
2784 struct fec_enet_private *fep = netdev_priv(ndev);
2785 unsigned int i;
2786 struct bufdesc *bdp;
2787 struct fec_enet_priv_tx_q *txq;
2788
2789 txq = fep->tx_queue[queue];
7355f276
TK		 2790 bdp = txq->bd.base;
2791 for (i = 0; i < txq->bd.ring_size; i++) {
4d494cdc
FD		 2792 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2793 if (!txq->tx_bounce[i])
ffdce2cc 2794 goto err_alloc;
f0b3fbea 2795
5cfa3039
JB		 2796 bdp->cbd_sc = cpu_to_fec16(0);
2797 bdp->cbd_bufaddr = cpu_to_fec32(0);
6605b730 2798
ff43da86
FL		 2799 if (fep->bufdesc_ex) {
2800 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2801 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
ff43da86
FL		 2802 }
2803
7355f276 2804 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
f0b3fbea
SH		 2805 }
2806
2807 /* Set the last buffer to wrap. */
7355f276 2808 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
5cfa3039 2809 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
f0b3fbea
SH		 2810
2811 return 0;
ffdce2cc
RK		 2812
2813 err_alloc:
2814 fec_enet_free_buffers(ndev);
2815 return -ENOMEM;
f0b3fbea
SH		 2816}
2817
59d0f746
FL		 2818static int fec_enet_alloc_buffers(struct net_device *ndev)
2819{
2820 struct fec_enet_private *fep = netdev_priv(ndev);
2821 unsigned int i;
2822
2823 for (i = 0; i < fep->num_rx_queues; i++)
2824 if (fec_enet_alloc_rxq_buffers(ndev, i))
2825 return -ENOMEM;
2826
2827 for (i = 0; i < fep->num_tx_queues; i++)
2828 if (fec_enet_alloc_txq_buffers(ndev, i))
2829 return -ENOMEM;
2830 return 0;
2831}
2832
1da177e4 2833static int
c556167f 2834fec_enet_open(struct net_device *ndev)
1da177e4 2835{
c556167f 2836 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2837 int ret;
1b0a83ac 2838 bool reset_again;
1da177e4 2839
8fff755e 2840 ret = pm_runtime_get_sync(&fep->pdev->dev);
b0c6ce24 2841 if (ret < 0)
8fff755e
AL		 2842 return ret;
2843
5bbde4d2 2844 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2845 ret = fec_enet_clk_enable(ndev, true);
2846 if (ret)
8fff755e 2847 goto clk_enable;
e8fcfcd5 2848
1b0a83ac
RL		 2849 /* During the first fec_enet_open call the PHY isn't probed at this
2850 * point. Therefore the phy_reset_after_clk_enable() call within
2851 * fec_enet_clk_enable() fails. As we need this reset in order to be
2852 * sure the PHY is working correctly we check if we need to reset again
2853 * later when the PHY is probed
2854 */
2855 if (ndev->phydev && ndev->phydev->drv)
2856 reset_again = false;
2857 else
2858 reset_again = true;
2859
1da177e4
LT		 2860 /* I should reset the ring buffers here, but I don't yet know
2861 * a simple way to do that.
2862 */
1da177e4 2863
c556167f 2864 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea 2865 if (ret)
681d2421 2866 goto err_enet_alloc;
f0b3fbea 2867
55dd2753
NA		 2868 /* Init MAC prior to mii bus probe */
2869 fec_restart(ndev);
2870
418bd0d4 2871 /* Probe and connect to PHY when open the interface */
c556167f 2872 ret = fec_enet_mii_probe(ndev);
681d2421
FE		 2873 if (ret)
2874 goto err_enet_mii_probe;
ce5eaf02 2875
1b0a83ac
RL		 2876 /* Call phy_reset_after_clk_enable() again if it failed during
2877 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
2878 */
2879 if (reset_again)
2880 phy_reset_after_clk_enable(ndev->phydev);
2881
29380905
LS		 2882 if (fep->quirks & FEC_QUIRK_ERR006687)
2883 imx6q_cpuidle_fec_irqs_used();
2884
ce5eaf02 2885 napi_enable(&fep->napi);
45f5c327 2886 phy_start(ndev->phydev);
4d494cdc
FD		 2887 netif_tx_start_all_queues(ndev);
2888
de40ed31
NA		 2889 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2890 FEC_WOL_FLAG_ENABLE);
2891
22f6b860 2892 return 0;
681d2421
FE		 2893
2894err_enet_mii_probe:
2895 fec_enet_free_buffers(ndev);
2896err_enet_alloc:
2897 fec_enet_clk_enable(ndev, false);
8fff755e
AL		 2898clk_enable:
2899 pm_runtime_mark_last_busy(&fep->pdev->dev);
2900 pm_runtime_put_autosuspend(&fep->pdev->dev);
681d2421
FE		 2901 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2902 return ret;
1da177e4
LT		 2903}
2904
2905static int
c556167f 2906fec_enet_close(struct net_device *ndev)
1da177e4 2907{
c556167f 2908 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2909
45f5c327 2910 phy_stop(ndev->phydev);
d76cfae9 2911
31a6de34
RK		 2912 if (netif_device_present(ndev)) {
2913 napi_disable(&fep->napi);
2914 netif_tx_disable(ndev);
8bbbd3c1 2915 fec_stop(ndev);
31a6de34 2916 }
1da177e4 2917
45f5c327 2918 phy_disconnect(ndev->phydev);
418bd0d4 2919
29380905
LS		 2920 if (fep->quirks & FEC_QUIRK_ERR006687)
2921 imx6q_cpuidle_fec_irqs_unused();
2922
80cca775
NY		 2923 fec_enet_update_ethtool_stats(ndev);
2924
e8fcfcd5 2925 fec_enet_clk_enable(ndev, false);
5bbde4d2 2926 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
8fff755e
AL		 2927 pm_runtime_mark_last_busy(&fep->pdev->dev);
2928 pm_runtime_put_autosuspend(&fep->pdev->dev);
2929
db8880bc 2930 fec_enet_free_buffers(ndev);
f0b3fbea 2931
1da177e4
LT		 2932 return 0;
2933}
2934
1da177e4
LT		 2935/* Set or clear the multicast filter for this adaptor.
2936 * Skeleton taken from sunlance driver.
2937 * The CPM Ethernet implementation allows Multicast as well as individual
2938 * MAC address filtering. Some of the drivers check to make sure it is
2939 * a group multicast address, and discard those that are not. I guess I
2940 * will do the same for now, but just remove the test if you want
2941 * individual filtering as well (do the upper net layers want or support
2942 * this kind of feature?).
2943 */
2944
6176e89c 2945#define FEC_HASH_BITS 6 /* #bits in hash */
1da177e4 2946
c556167f 2947static void set_multicast_list(struct net_device *ndev)
1da177e4 2948{
c556167f 2949 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2950 struct netdev_hw_addr *ha;
16f6e983 2951 unsigned int crc, tmp;
1da177e4 2952 unsigned char hash;
01f8902b 2953 unsigned int hash_high = 0, hash_low = 0;
1da177e4 2954
c556167f 2955 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2956 tmp = readl(fep->hwp + FEC_R_CNTRL);
2957 tmp |= 0x8;
2958 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2959 return;
2960 }
1da177e4 2961
4e831836
SH		 2962 tmp = readl(fep->hwp + FEC_R_CNTRL);
2963 tmp &= ~0x8;
2964 writel(tmp, fep->hwp + FEC_R_CNTRL);
2965
c556167f 2966 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2967 /* Catch all multicast addresses, so set the
2968 * filter to all 1's
2969 */
2970 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2971 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2972
2973 return;
2974 }
2975
01f8902b 2976 /* Add the addresses in hash register */
c556167f 2977 netdev_for_each_mc_addr(ha, ndev) {
4e831836 2978 /* calculate crc32 value of mac address */
16f6e983 2979 crc = ether_crc_le(ndev->addr_len, ha->addr);
4e831836 2980
6176e89c 2981 /* only upper 6 bits (FEC_HASH_BITS) are used
981a0547 2982 * which point to specific bit in the hash registers
4e831836 2983 */
6176e89c 2984 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
4e831836 2985
01f8902b
RS		 2986 if (hash > 31)
2987 hash_high |= 1 << (hash - 32);
2988 else
2989 hash_low |= 1 << hash;
1da177e4 2990 }
01f8902b
RS		 2991
2992 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2993 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1da177e4
LT		 2994}
2995
22f6b860 2996/* Set a MAC change in hardware. */
009fda83 2997static int
c556167f 2998fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 2999{
c556167f 3000 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 3001 struct sockaddr *addr = p;
3002
44934fac
LS		 3003 if (addr) {
3004 if (!is_valid_ether_addr(addr->sa_data))
3005 return -EADDRNOTAVAIL;
3006 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3007 }
1da177e4 3008
9638d19e
NA		 3009 /* Add netif status check here to avoid system hang in below case:
3010 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3011 * After ethx down, fec all clocks are gated off and then register
3012 * access causes system hang.
3013 */
3014 if (!netif_running(ndev))
3015 return 0;
3016
c556167f
UKK		 3017 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3018 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 3019 fep->hwp + FEC_ADDR_LOW);
c556167f 3020 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 3021 fep->hwp + FEC_ADDR_HIGH);
009fda83 3022 return 0;
1da177e4
LT		 3023}
3024
7f5c6add 3025#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 3026/**
3027 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 3028 * @dev: The FEC network adapter
3029 *
3030 * Polled functionality used by netconsole and others in non interrupt mode
3031 *
3032 */
47a5247f 3033static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 3034{
3035 int i;
3036 struct fec_enet_private *fep = netdev_priv(dev);
3037
3038 for (i = 0; i < FEC_IRQ_NUM; i++) {
3039 if (fep->irq[i] > 0) {
3040 disable_irq(fep->irq[i]);
3041 fec_enet_interrupt(fep->irq[i], dev);
3042 enable_irq(fep->irq[i]);
3043 }
3044 }
3045}
3046#endif
3047
5bc26726 3048static inline void fec_enet_set_netdev_features(struct net_device *netdev,
4c09eed9
JB		 3049 netdev_features_t features)
3050{
3051 struct fec_enet_private *fep = netdev_priv(netdev);
3052 netdev_features_t changed = features ^ netdev->features;
3053
3054 netdev->features = features;
3055
3056 /* Receive checksum has been changed */
3057 if (changed & NETIF_F_RXCSUM) {
3058 if (features & NETIF_F_RXCSUM)
3059 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3060 else
3061 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 3062 }
5bc26726
NA		 3063}
3064
3065static int fec_set_features(struct net_device *netdev,
3066 netdev_features_t features)
3067{
3068 struct fec_enet_private *fep = netdev_priv(netdev);
3069 netdev_features_t changed = features ^ netdev->features;
4c09eed9 3070
5b40f709 3071 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
5bc26726
NA		 3072 napi_disable(&fep->napi);
3073 netif_tx_lock_bh(netdev);
3074 fec_stop(netdev);
3075 fec_enet_set_netdev_features(netdev, features);
ef83337d 3076 fec_restart(netdev);
4d494cdc 3077 netif_tx_wake_all_queues(netdev);
8506fa1d
RK		 3078 netif_tx_unlock_bh(netdev);
3079 napi_enable(&fep->napi);
5bc26726
NA		 3080 } else {
3081 fec_enet_set_netdev_features(netdev, features);
4c09eed9
JB		 3082 }
3083
3084 return 0;
3085}
3086
009fda83
SH		 3087static const struct net_device_ops fec_netdev_ops = {
3088 .ndo_open = fec_enet_open,
3089 .ndo_stop = fec_enet_close,
3090 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 3091 .ndo_set_rx_mode = set_multicast_list,
009fda83
SH		 3092 .ndo_validate_addr = eth_validate_addr,
3093 .ndo_tx_timeout = fec_timeout,
3094 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 3095 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 3096#ifdef CONFIG_NET_POLL_CONTROLLER
3097 .ndo_poll_controller = fec_poll_controller,
3098#endif
4c09eed9 3099 .ndo_set_features = fec_set_features,
009fda83
SH		 3100};
3101
53bb20d1
TK		 3102static const unsigned short offset_des_active_rxq[] = {
3103 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3104};
3105
3106static const unsigned short offset_des_active_txq[] = {
3107 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3108};
3109
1da177e4
LT		 3110 /*
3111 * XXX: We need to clean up on failure exits here.
ead73183 3112 *
1da177e4 3113 */
c556167f 3114static int fec_enet_init(struct net_device *ndev)
1da177e4 3115{
c556167f 3116 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 3117 struct bufdesc *cbd_base;
4d494cdc 3118 dma_addr_t bd_dma;
55d0218a 3119 int bd_size;
59d0f746 3120 unsigned int i;
7355f276
TK		 3121 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3122 sizeof(struct bufdesc);
3123 unsigned dsize_log2 = __fls(dsize);
453e9dc4 3124 int ret;
55d0218a 3125
7355f276 3126 WARN_ON(dsize != (1 << dsize_log2));
3f1dcc6a 3127#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
41ef84ce
FD		 3128 fep->rx_align = 0xf;
3129 fep->tx_align = 0xf;
3130#else
3131 fep->rx_align = 0x3;
3132 fep->tx_align = 0x3;
3133#endif
3134
453e9dc4
SA		 3135 /* Check mask of the streaming and coherent API */
3136 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3137 if (ret < 0) {
3138 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3139 return ret;
3140 }
3141
59d0f746 3142 fec_enet_alloc_queue(ndev);
79f33912 3143
7355f276 3144 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
1da177e4 3145
8d4dd5cf 3146 /* Allocate memory for buffer descriptors. */
c0a1a0a6
LS		 3147 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3148 GFP_KERNEL);
4d494cdc 3149 if (!cbd_base) {
79f33912
NA		 3150 return -ENOMEM;
3151 }
3152
4d494cdc 3153 memset(cbd_base, 0, bd_size);
1da177e4 3154
49da97dc 3155 /* Get the Ethernet address */
c556167f 3156 fec_get_mac(ndev);
44934fac
LS		 3157 /* make sure MAC we just acquired is programmed into the hw */
3158 fec_set_mac_address(ndev, NULL);
1da177e4 3159
8d4dd5cf 3160 /* Set receive and transmit descriptor base. */
59d0f746 3161 for (i = 0; i < fep->num_rx_queues; i++) {
7355f276
TK		 3162 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3163 unsigned size = dsize * rxq->bd.ring_size;
3164
3165 rxq->bd.qid = i;
3166 rxq->bd.base = cbd_base;
3167 rxq->bd.cur = cbd_base;
3168 rxq->bd.dma = bd_dma;
3169 rxq->bd.dsize = dsize;
3170 rxq->bd.dsize_log2 = dsize_log2;
53bb20d1 3171 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
7355f276
TK		 3172 bd_dma += size;
3173 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3174 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
59d0f746
FL		 3175 }
3176
3177 for (i = 0; i < fep->num_tx_queues; i++) {
7355f276
TK		 3178 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3179 unsigned size = dsize * txq->bd.ring_size;
3180
3181 txq->bd.qid = i;
3182 txq->bd.base = cbd_base;
3183 txq->bd.cur = cbd_base;
3184 txq->bd.dma = bd_dma;
3185 txq->bd.dsize = dsize;
3186 txq->bd.dsize_log2 = dsize_log2;
53bb20d1 3187 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
7355f276
TK		 3188 bd_dma += size;
3189 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3190 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
59d0f746 3191 }
4d494cdc 3192
1da177e4 3193
22f6b860 3194 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 3195 ndev->watchdog_timeo = TX_TIMEOUT;
3196 ndev->netdev_ops = &fec_netdev_ops;
3197 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 3198
dc975382 3199 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 3200 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 3201
6b7e4008 3202 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 3203 /* enable hw VLAN support */
3204 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 3205
6b7e4008 3206 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 3207 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3208
48496255
SG		 3209 /* enable hw accelerator */
3210 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 3211 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 3212 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3213 }
4c09eed9 3214
6b7e4008 3215 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
41ef84ce
FD		 3216 fep->tx_align = 0;
3217 fep->rx_align = 0x3f;
3218 }
3219
09d1e541
NA		 3220 ndev->hw_features = ndev->features;
3221
ef83337d 3222 fec_restart(ndev);
1da177e4 3223
2b30842b
AL		 3224 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3225 fec_enet_clear_ethtool_stats(ndev);
3226 else
3227 fec_enet_update_ethtool_stats(ndev);
80cca775 3228
1da177e4
LT		 3229 return 0;
3230}
3231
ca2cc333 3232#ifdef CONFIG_OF
9269e556 3233static int fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3234{
3235 int err, phy_reset;
962d8cdc 3236 bool active_high = false;
159a0760 3237 int msec = 1, phy_post_delay = 0;
ca2cc333
SG		 3238 struct device_node *np = pdev->dev.of_node;
3239
3240 if (!np)
9269e556 3241 return 0;
ca2cc333 3242
61e04ccb 3243 err = of_property_read_u32(np, "phy-reset-duration", &msec);
a3caad0a 3244 /* A sane reset duration should not be longer than 1s */
61e04ccb 3245 if (!err && msec > 1000)
a3caad0a
SG		 3246 msec = 1;
3247
ca2cc333 3248 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
9269e556
FD		 3249 if (phy_reset == -EPROBE_DEFER)
3250 return phy_reset;
3251 else if (!gpio_is_valid(phy_reset))
3252 return 0;
07dcf8e9 3253
159a0760
QS		 3254 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3255 /* valid reset duration should be less than 1s */
3256 if (!err && phy_post_delay > 1000)
3257 return -EINVAL;
3258
962d8cdc 3259 active_high = of_property_read_bool(np, "phy-reset-active-high");
64f10f6e 3260
119fc007 3261 err = devm_gpio_request_one(&pdev->dev, phy_reset,
962d8cdc 3262 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
64f10f6e 3263 "phy-reset");
ca2cc333 3264 if (err) {
07dcf8e9 3265 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
9269e556 3266 return err;
ca2cc333 3267 }
eb37c563
SW		 3268
3269 if (msec > 20)
3270 msleep(msec);
3271 else
3272 usleep_range(msec * 1000, msec * 1000 + 1000);
3273
962d8cdc 3274 gpio_set_value_cansleep(phy_reset, !active_high);
9269e556 3275
159a0760
QS		 3276 if (!phy_post_delay)
3277 return 0;
3278
3279 if (phy_post_delay > 20)
3280 msleep(phy_post_delay);
3281 else
3282 usleep_range(phy_post_delay * 1000,
3283 phy_post_delay * 1000 + 1000);
3284
9269e556 3285 return 0;
ca2cc333
SG		 3286}
3287#else /* CONFIG_OF */
9269e556 3288static int fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3289{
3290 /*
3291 * In case of platform probe, the reset has been done
3292 * by machine code.
3293 */
9269e556 3294 return 0;
ca2cc333
SG		 3295}
3296#endif /* CONFIG_OF */
3297
9fc095f1
FD		 3298static void
3299fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3300{
3301 struct device_node *np = pdev->dev.of_node;
9fc095f1
FD		 3302
3303 *num_tx = *num_rx = 1;
3304
3305 if (!np || !of_device_is_available(np))
3306 return;
3307
3308 /* parse the num of tx and rx queues */
73b1c90d 3309 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
b7bd75cf 3310
73b1c90d 3311 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
9fc095f1
FD		 3312
3313 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
b7bd75cf
FL		 3314 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3315 *num_tx);
9fc095f1
FD		 3316 *num_tx = 1;
3317 return;
3318 }
3319
3320 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
b7bd75cf
FL		 3321 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3322 *num_rx);
9fc095f1
FD		 3323 *num_rx = 1;
3324 return;
3325 }
3326
3327}
3328
4ad1ceec
TK		 3329static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3330{
3331 int irq_cnt = platform_irq_count(pdev);
3332
3333 if (irq_cnt > FEC_IRQ_NUM)
3334 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3335 else if (irq_cnt == 2)
3336 irq_cnt = 1; /* last for pps */
3337 else if (irq_cnt <= 0)
3338 irq_cnt = 1; /* At least 1 irq is needed */
3339 return irq_cnt;
3340}
3341
33897cc8 3342static int
ead73183
SH		 3343fec_probe(struct platform_device *pdev)
3344{
3345 struct fec_enet_private *fep;
5eb32bd0 3346 struct fec_platform_data *pdata;
ead73183
SH		 3347 struct net_device *ndev;
3348 int i, irq, ret = 0;
3349 struct resource *r;
ca2cc333 3350 const struct of_device_id *of_id;
43af940c 3351 static int dev_id;
407066f8 3352 struct device_node *np = pdev->dev.of_node, *phy_node;
b7bd75cf
FL		 3353 int num_tx_qs;
3354 int num_rx_qs;
4ad1ceec
TK		 3355 char irq_name[8];
3356 int irq_cnt;
ca2cc333 3357
9fc095f1
FD		 3358 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3359
ead73183 3360 /* Init network device */
80cca775 3361 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
f85de666 3362 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
83e519b6
FE		 3363 if (!ndev)
3364 return -ENOMEM;
ead73183
SH		 3365
3366 SET_NETDEV_DEV(ndev, &pdev->dev);
3367
3368 /* setup board info structure */
3369 fep = netdev_priv(ndev);
ead73183 3370
6b7e4008
LW		 3371 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3372 if (of_id)
3373 pdev->id_entry = of_id->data;
3374 fep->quirks = pdev->id_entry->driver_data;
3375
0c818594 3376 fep->netdev = ndev;
9fc095f1
FD		 3377 fep->num_rx_queues = num_rx_qs;
3378 fep->num_tx_queues = num_tx_qs;
3379
d1391930 3380#if !defined(CONFIG_M5272)
baa70a5c 3381 /* default enable pause frame auto negotiation */
6b7e4008 3382 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
baa70a5c 3383 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 3384#endif
baa70a5c 3385
5bbde4d2
NA		 3386 /* Select default pin state */
3387 pinctrl_pm_select_default_state(&pdev->dev);
3388
399db75b 3389 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 3390 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3391 if (IS_ERR(fep->hwp)) {
3392 ret = PTR_ERR(fep->hwp);
3393 goto failed_ioremap;
3394 }
3395
e6b043d5 3396 fep->pdev = pdev;
43af940c 3397 fep->dev_id = dev_id++;
ead73183 3398
ead73183
SH		 3399 platform_set_drvdata(pdev, ndev);
3400
29380905
LS		 3401 if ((of_machine_is_compatible("fsl,imx6q") ||
3402 of_machine_is_compatible("fsl,imx6dl")) &&
3403 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3404 fep->quirks |= FEC_QUIRK_ERR006687;
3405
de40ed31
NA		 3406 if (of_get_property(np, "fsl,magic-packet", NULL))
3407 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3408
407066f8
UKK		 3409 phy_node = of_parse_phandle(np, "phy-handle", 0);
3410 if (!phy_node && of_phy_is_fixed_link(np)) {
3411 ret = of_phy_register_fixed_link(np);
3412 if (ret < 0) {
3413 dev_err(&pdev->dev,
3414 "broken fixed-link specification\n");
3415 goto failed_phy;
3416 }
3417 phy_node = of_node_get(np);
3418 }
3419 fep->phy_node = phy_node;
3420
6c5f7808 3421 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 3422 if (ret < 0) {
94660ba0 3423 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 3424 if (pdata)
3425 fep->phy_interface = pdata->phy;
3426 else
3427 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3428 } else {
3429 fep->phy_interface = ret;
3430 }
3431
f4d40de3
SH		 3432 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3433 if (IS_ERR(fep->clk_ipg)) {
3434 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 3435 goto failed_clk;
3436 }
f4d40de3
SH		 3437
3438 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3439 if (IS_ERR(fep->clk_ahb)) {
3440 ret = PTR_ERR(fep->clk_ahb);
3441 goto failed_clk;
3442 }
3443
d851b47b
FD		 3444 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3445
daa7d392
WS		 3446 /* enet_out is optional, depends on board */
3447 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3448 if (IS_ERR(fep->clk_enet_out))
3449 fep->clk_enet_out = NULL;
3450
91c0d987
NA		 3451 fep->ptp_clk_on = false;
3452 mutex_init(&fep->ptp_clk_mutex);
9b5330ed
FD		 3453
3454 /* clk_ref is optional, depends on board */
3455 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3456 if (IS_ERR(fep->clk_ref))
3457 fep->clk_ref = NULL;
3458
6b7e4008 3459 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730
FL		 3460 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3461 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 3462 fep->clk_ptp = NULL;
217b5844 3463 fep->bufdesc_ex = false;
6605b730 3464 }
6605b730 3465
e8fcfcd5 3466 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 3467 if (ret)
3468 goto failed_clk;
3469
8fff755e
AL		 3470 ret = clk_prepare_enable(fep->clk_ipg);
3471 if (ret)
3472 goto failed_clk_ipg;
3473
25974d8a 3474 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
f4e9f3d2
FE		 3475 if (!IS_ERR(fep->reg_phy)) {
3476 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 3477 if (ret) {
3478 dev_err(&pdev->dev,
3479 "Failed to enable phy regulator: %d\n", ret);
9269e556 3480 clk_disable_unprepare(fep->clk_ipg);
5fa9c0fe
SG		 3481 goto failed_regulator;
3482 }
f6a4d607 3483 } else {
3f38c683
FD		 3484 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3485 ret = -EPROBE_DEFER;
3486 goto failed_regulator;
3487 }
f6a4d607 3488 fep->reg_phy = NULL;
5fa9c0fe
SG		 3489 }
3490
8fff755e
AL		 3491 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3492 pm_runtime_use_autosuspend(&pdev->dev);
14d2b7c1 3493 pm_runtime_get_noresume(&pdev->dev);
8fff755e
AL		 3494 pm_runtime_set_active(&pdev->dev);
3495 pm_runtime_enable(&pdev->dev);
3496
9269e556
FD		 3497 ret = fec_reset_phy(pdev);
3498 if (ret)
3499 goto failed_reset;
2ca9b2aa 3500
4ad1ceec 3501 irq_cnt = fec_enet_get_irq_cnt(pdev);
e2f8d555 3502 if (fep->bufdesc_ex)
4ad1ceec 3503 fec_ptp_init(pdev, irq_cnt);
e2f8d555
FE		 3504
3505 ret = fec_enet_init(ndev);
3506 if (ret)
3507 goto failed_init;
3508
4ad1ceec 3509 for (i = 0; i < irq_cnt; i++) {
3ded9f2b 3510 snprintf(irq_name, sizeof(irq_name), "int%d", i);
4ad1ceec
TK		 3511 irq = platform_get_irq_byname(pdev, irq_name);
3512 if (irq < 0)
3513 irq = platform_get_irq(pdev, i);
e2f8d555 3514 if (irq < 0) {
e2f8d555
FE		 3515 ret = irq;
3516 goto failed_irq;
3517 }
0d9b2ab1 3518 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 3519 0, pdev->name, ndev);
0d9b2ab1 3520 if (ret)
e2f8d555 3521 goto failed_irq;
de40ed31
NA		 3522
3523 fep->irq[i] = irq;
e2f8d555
FE		 3524 }
3525
b4d39b53 3526 init_completion(&fep->mdio_done);
e6b043d5
BW		 3527 ret = fec_enet_mii_init(pdev);
3528 if (ret)
3529 goto failed_mii_init;
3530
03c698c9
OS		 3531 /* Carrier starts down, phylib will bring it up */
3532 netif_carrier_off(ndev);
e8fcfcd5 3533 fec_enet_clk_enable(ndev, false);
5bbde4d2 3534 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 3535
ead73183
SH		 3536 ret = register_netdev(ndev);
3537 if (ret)
3538 goto failed_register;
3539
de40ed31
NA		 3540 device_init_wakeup(&ndev->dev, fep->wol_flag &
3541 FEC_WOL_HAS_MAGIC_PACKET);
3542
eb1d0640
FE		 3543 if (fep->bufdesc_ex && fep->ptp_clock)
3544 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3545
1b7bde6d 3546 fep->rx_copybreak = COPYBREAK_DEFAULT;
36cdc743 3547 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
8fff755e
AL		 3548
3549 pm_runtime_mark_last_busy(&pdev->dev);
3550 pm_runtime_put_autosuspend(&pdev->dev);
3551
ead73183
SH		 3552 return 0;
3553
3554failed_register:
e6b043d5
BW		 3555 fec_enet_mii_remove(fep);
3556failed_mii_init:
7a2bbd8d 3557failed_irq:
7a2bbd8d 3558failed_init:
32cba57b 3559 fec_ptp_stop(pdev);
f6a4d607
FE		 3560 if (fep->reg_phy)
3561 regulator_disable(fep->reg_phy);
9269e556
FD		 3562failed_reset:
3563 pm_runtime_put(&pdev->dev);
3564 pm_runtime_disable(&pdev->dev);
5fa9c0fe 3565failed_regulator:
8fff755e 3566failed_clk_ipg:
e8fcfcd5 3567 fec_enet_clk_enable(ndev, false);
ead73183 3568failed_clk:
82005b1c
JH		 3569 if (of_phy_is_fixed_link(np))
3570 of_phy_deregister_fixed_link(np);
407066f8 3571 of_node_put(phy_node);
d1616f07
FD		 3572failed_phy:
3573 dev_id--;
ead73183
SH		 3574failed_ioremap:
3575 free_netdev(ndev);
3576
3577 return ret;
3578}
3579
33897cc8 3580static int
ead73183
SH		 3581fec_drv_remove(struct platform_device *pdev)
3582{
3583 struct net_device *ndev = platform_get_drvdata(pdev);
3584 struct fec_enet_private *fep = netdev_priv(ndev);
82005b1c 3585 struct device_node *np = pdev->dev.of_node;
ead73183 3586
36cdc743 3587 cancel_work_sync(&fep->tx_timeout_work);
32cba57b 3588 fec_ptp_stop(pdev);
e163cc97 3589 unregister_netdev(ndev);
e6b043d5 3590 fec_enet_mii_remove(fep);
f6a4d607
FE		 3591 if (fep->reg_phy)
3592 regulator_disable(fep->reg_phy);
a069215c
FF		 3593 pm_runtime_put(&pdev->dev);
3594 pm_runtime_disable(&pdev->dev);
82005b1c
JH		 3595 if (of_phy_is_fixed_link(np))
3596 of_phy_deregister_fixed_link(np);
407066f8 3597 of_node_put(fep->phy_node);
ead73183 3598 free_netdev(ndev);
28e2188e 3599
ead73183
SH		 3600 return 0;
3601}
3602
dd66d386 3603static int __maybe_unused fec_suspend(struct device *dev)
ead73183 3604{
87cad5c3 3605 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3606 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 3607
da1774e5 3608 rtnl_lock();
04e5216d 3609 if (netif_running(ndev)) {
de40ed31
NA		 3610 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3611 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
45f5c327 3612 phy_stop(ndev->phydev);
31a6de34
RK		 3613 napi_disable(&fep->napi);
3614 netif_tx_lock_bh(ndev);
04e5216d 3615 netif_device_detach(ndev);
31a6de34
RK		 3616 netif_tx_unlock_bh(ndev);
3617 fec_stop(ndev);
f4c4a4e0 3618 fec_enet_clk_enable(ndev, false);
de40ed31
NA		 3619 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3620 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
ead73183 3621 }
da1774e5
RK		 3622 rtnl_unlock();
3623
de40ed31 3624 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
238f7bc7
FE		 3625 regulator_disable(fep->reg_phy);
3626
858eeb7d
NA		 3627 /* SOC supply clock to phy, when clock is disabled, phy link down
3628 * SOC control phy regulator, when regulator is disabled, phy link down
3629 */
3630 if (fep->clk_enet_out || fep->reg_phy)
3631 fep->link = 0;
3632
ead73183
SH		 3633 return 0;
3634}
3635
dd66d386 3636static int __maybe_unused fec_resume(struct device *dev)
ead73183 3637{
87cad5c3 3638 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3639 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 3640 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
238f7bc7 3641 int ret;
de40ed31 3642 int val;
238f7bc7 3643
de40ed31 3644 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
238f7bc7
FE		 3645 ret = regulator_enable(fep->reg_phy);
3646 if (ret)
3647 return ret;
3648 }
ead73183 3649
da1774e5 3650 rtnl_lock();
04e5216d 3651 if (netif_running(ndev)) {
f4c4a4e0
NA		 3652 ret = fec_enet_clk_enable(ndev, true);
3653 if (ret) {
3654 rtnl_unlock();
3655 goto failed_clk;
3656 }
de40ed31
NA		 3657 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3658 if (pdata && pdata->sleep_mode_enable)
3659 pdata->sleep_mode_enable(false);
3660 val = readl(fep->hwp + FEC_ECNTRL);
3661 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3662 writel(val, fep->hwp + FEC_ECNTRL);
3663 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3664 } else {
3665 pinctrl_pm_select_default_state(&fep->pdev->dev);
3666 }
ef83337d 3667 fec_restart(ndev);
31a6de34 3668 netif_tx_lock_bh(ndev);
6af42d42 3669 netif_device_attach(ndev);
dbc64a8e 3670 netif_tx_unlock_bh(ndev);
6af42d42 3671 napi_enable(&fep->napi);
45f5c327 3672 phy_start(ndev->phydev);
ead73183 3673 }
da1774e5 3674 rtnl_unlock();
04e5216d 3675
ead73183 3676 return 0;
13a097bd 3677
e8fcfcd5 3678failed_clk:
13a097bd
FE		 3679 if (fep->reg_phy)
3680 regulator_disable(fep->reg_phy);
3681 return ret;
ead73183
SH		 3682}
3683
8fff755e
AL		 3684static int __maybe_unused fec_runtime_suspend(struct device *dev)
3685{
3686 struct net_device *ndev = dev_get_drvdata(dev);
3687 struct fec_enet_private *fep = netdev_priv(ndev);
3688
3689 clk_disable_unprepare(fep->clk_ipg);
3690
3691 return 0;
3692}
3693
3694static int __maybe_unused fec_runtime_resume(struct device *dev)
3695{
3696 struct net_device *ndev = dev_get_drvdata(dev);
3697 struct fec_enet_private *fep = netdev_priv(ndev);
3698
3699 return clk_prepare_enable(fep->clk_ipg);
3700}
3701
3702static const struct dev_pm_ops fec_pm_ops = {
3703 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3704 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3705};
59d4289b 3706
ead73183
SH		 3707static struct platform_driver fec_driver = {
3708 .driver = {
b5680e0b 3709 .name = DRIVER_NAME,
87cad5c3 3710 .pm = &fec_pm_ops,
ca2cc333 3711 .of_match_table = fec_dt_ids,
ead73183 3712 },
b5680e0b 3713 .id_table = fec_devtype,
87cad5c3 3714 .probe = fec_probe,
33897cc8 3715 .remove = fec_drv_remove,
ead73183
SH		 3716};
3717
aaca2377 3718module_platform_driver(fec_driver);
1da177e4 3719
f8c0aca9 3720MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 3721MODULE_LICENSE("GPL");
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