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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
8fff755e | 27 | #include <linux/pm_runtime.h> |
1da177e4 LT |
28 | #include <linux/ptrace.h> |
29 | #include <linux/errno.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/interrupt.h> | |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
4c09eed9 JB |
37 | #include <linux/in.h> |
38 | #include <linux/ip.h> | |
39 | #include <net/ip.h> | |
79f33912 | 40 | #include <net/tso.h> |
4c09eed9 JB |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/icmp.h> | |
1da177e4 LT |
44 | #include <linux/spinlock.h> |
45 | #include <linux/workqueue.h> | |
46 | #include <linux/bitops.h> | |
6f501b17 SH |
47 | #include <linux/io.h> |
48 | #include <linux/irq.h> | |
196719ec | 49 | #include <linux/clk.h> |
ead73183 | 50 | #include <linux/platform_device.h> |
7f854420 | 51 | #include <linux/mdio.h> |
e6b043d5 | 52 | #include <linux/phy.h> |
5eb32bd0 | 53 | #include <linux/fec.h> |
ca2cc333 SG |
54 | #include <linux/of.h> |
55 | #include <linux/of_device.h> | |
56 | #include <linux/of_gpio.h> | |
407066f8 | 57 | #include <linux/of_mdio.h> |
ca2cc333 | 58 | #include <linux/of_net.h> |
5fa9c0fe | 59 | #include <linux/regulator/consumer.h> |
cdffcf1b | 60 | #include <linux/if_vlan.h> |
a68ab98e | 61 | #include <linux/pinctrl/consumer.h> |
c259c132 | 62 | #include <linux/prefetch.h> |
29380905 | 63 | #include <soc/imx/cpuidle.h> |
1da177e4 | 64 | |
080853af | 65 | #include <asm/cacheflush.h> |
196719ec | 66 | |
1da177e4 | 67 | #include "fec.h" |
1da177e4 | 68 | |
772e42b0 | 69 | static void set_multicast_list(struct net_device *ndev); |
d851b47b | 70 | static void fec_enet_itr_coal_init(struct net_device *ndev); |
772e42b0 | 71 | |
b5680e0b SG |
72 | #define DRIVER_NAME "fec" |
73 | ||
4d494cdc FD |
74 | #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) |
75 | ||
baa70a5c FL |
76 | /* Pause frame feild and FIFO threshold */ |
77 | #define FEC_ENET_FCE (1 << 5) | |
78 | #define FEC_ENET_RSEM_V 0x84 | |
79 | #define FEC_ENET_RSFL_V 16 | |
80 | #define FEC_ENET_RAEM_V 0x8 | |
81 | #define FEC_ENET_RAFL_V 0x8 | |
82 | #define FEC_ENET_OPD_V 0xFFF0 | |
8fff755e | 83 | #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ |
baa70a5c | 84 | |
b5680e0b SG |
85 | static struct platform_device_id fec_devtype[] = { |
86 | { | |
0ca1e290 | 87 | /* keep it for coldfire */ |
b5680e0b SG |
88 | .name = DRIVER_NAME, |
89 | .driver_data = 0, | |
0ca1e290 SG |
90 | }, { |
91 | .name = "imx25-fec", | |
2b30842b | 92 | .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR, |
0ca1e290 SG |
93 | }, { |
94 | .name = "imx27-fec", | |
2b30842b | 95 | .driver_data = FEC_QUIRK_MIB_CLEAR, |
b5680e0b SG |
96 | }, { |
97 | .name = "imx28-fec", | |
3d125f9c | 98 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | |
18803495 | 99 | FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, |
230dec61 SG |
100 | }, { |
101 | .name = "imx6q-fec", | |
ff43da86 | 102 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
cdffcf1b | 103 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | |
18803495 GU |
104 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | |
105 | FEC_QUIRK_HAS_RACC, | |
ca7c4a45 | 106 | }, { |
36803542 | 107 | .name = "mvf600-fec", |
18803495 | 108 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, |
95a77470 FD |
109 | }, { |
110 | .name = "imx6sx-fec", | |
111 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | | |
112 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | | |
f88c7ede | 113 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | |
18803495 | 114 | FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | |
ff7566b8 | 115 | FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, |
a51d3ab5 FD |
116 | }, { |
117 | .name = "imx6ul-fec", | |
118 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | | |
119 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | | |
99492ad4 FD |
120 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | |
121 | FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | | |
122 | FEC_QUIRK_HAS_COALESCE, | |
0ca1e290 SG |
123 | }, { |
124 | /* sentinel */ | |
125 | } | |
b5680e0b | 126 | }; |
0ca1e290 | 127 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 128 | |
ca2cc333 | 129 | enum imx_fec_type { |
a7dd3219 | 130 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
131 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
132 | IMX28_FEC, | |
230dec61 | 133 | IMX6Q_FEC, |
36803542 | 134 | MVF600_FEC, |
ba593e00 | 135 | IMX6SX_FEC, |
a51d3ab5 | 136 | IMX6UL_FEC, |
ca2cc333 SG |
137 | }; |
138 | ||
139 | static const struct of_device_id fec_dt_ids[] = { | |
140 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
141 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
142 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 143 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
36803542 | 144 | { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, |
ba593e00 | 145 | { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, |
a51d3ab5 | 146 | { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, |
ca2cc333 SG |
147 | { /* sentinel */ } |
148 | }; | |
149 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
150 | ||
49da97dc SG |
151 | static unsigned char macaddr[ETH_ALEN]; |
152 | module_param_array(macaddr, byte, NULL, 0); | |
153 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 154 | |
49da97dc | 155 | #if defined(CONFIG_M5272) |
1da177e4 LT |
156 | /* |
157 | * Some hardware gets it MAC address out of local flash memory. | |
158 | * if this is non-zero then assume it is the address to get MAC from. | |
159 | */ | |
160 | #if defined(CONFIG_NETtel) | |
161 | #define FEC_FLASHMAC 0xf0006006 | |
162 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
163 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
164 | #elif defined(CONFIG_CANCam) |
165 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
166 | #elif defined (CONFIG_M5272C3) |
167 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
168 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 169 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
170 | #else |
171 | #define FEC_FLASHMAC 0 | |
172 | #endif | |
43be6366 | 173 | #endif /* CONFIG_M5272 */ |
ead73183 | 174 | |
cdffcf1b | 175 | /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. |
fbbeefdd AL |
176 | * |
177 | * 2048 byte skbufs are allocated. However, alignment requirements | |
178 | * varies between FEC variants. Worst case is 64, so round down by 64. | |
1da177e4 | 179 | */ |
fbbeefdd | 180 | #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) |
1da177e4 | 181 | #define PKT_MINBUF_SIZE 64 |
1da177e4 | 182 | |
4c09eed9 JB |
183 | /* FEC receive acceleration */ |
184 | #define FEC_RACC_IPDIS (1 << 1) | |
185 | #define FEC_RACC_PRODIS (1 << 2) | |
3ac72b7b | 186 | #define FEC_RACC_SHIFT16 BIT(7) |
4c09eed9 JB |
187 | #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) |
188 | ||
2b30842b AL |
189 | /* MIB Control Register */ |
190 | #define FEC_MIB_CTRLSTAT_DISABLE BIT(31) | |
191 | ||
1da177e4 | 192 | /* |
6b265293 | 193 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
194 | * size bits. Other FEC hardware does not, so we need to take that into |
195 | * account when setting it. | |
196 | */ | |
562d2f8c | 197 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 198 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
199 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
200 | #else | |
201 | #define OPT_FRAME_SIZE 0 | |
202 | #endif | |
203 | ||
e6b043d5 BW |
204 | /* FEC MII MMFR bits definition */ |
205 | #define FEC_MMFR_ST (1 << 30) | |
206 | #define FEC_MMFR_OP_READ (2 << 28) | |
207 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
208 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
209 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
210 | #define FEC_MMFR_TA (2 << 16) | |
211 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
de40ed31 NA |
212 | /* FEC ECR bits definition */ |
213 | #define FEC_ECR_MAGICEN (1 << 2) | |
214 | #define FEC_ECR_SLEEP (1 << 3) | |
1da177e4 | 215 | |
c3b084c2 | 216 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 217 | |
22f6b860 SH |
218 | /* Transmitter timeout */ |
219 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 220 | |
baa70a5c FL |
221 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
222 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
de40ed31 NA |
223 | #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) |
224 | #define FEC_WOL_FLAG_ENABLE (0x1 << 1) | |
225 | #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) | |
baa70a5c | 226 | |
1b7bde6d NA |
227 | #define COPYBREAK_DEFAULT 256 |
228 | ||
79f33912 NA |
229 | /* Max number of allowed TCP segments for software TSO */ |
230 | #define FEC_MAX_TSO_SEGS 100 | |
231 | #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
232 | ||
233 | #define IS_TSO_HEADER(txq, addr) \ | |
234 | ((addr >= txq->tso_hdrs_dma) && \ | |
7355f276 | 235 | (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) |
79f33912 | 236 | |
e163cc97 LW |
237 | static int mii_cnt; |
238 | ||
7355f276 TK |
239 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, |
240 | struct bufdesc_prop *bd) | |
241 | { | |
242 | return (bdp >= bd->last) ? bd->base | |
145d6e29 | 243 | : (struct bufdesc *)(((void *)bdp) + bd->dsize); |
7355f276 | 244 | } |
36e24e2e | 245 | |
7355f276 TK |
246 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, |
247 | struct bufdesc_prop *bd) | |
248 | { | |
249 | return (bdp <= bd->base) ? bd->last | |
145d6e29 | 250 | : (struct bufdesc *)(((void *)bdp) - bd->dsize); |
ff43da86 FL |
251 | } |
252 | ||
7355f276 TK |
253 | static int fec_enet_get_bd_index(struct bufdesc *bdp, |
254 | struct bufdesc_prop *bd) | |
61a4427b | 255 | { |
7355f276 | 256 | return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; |
61a4427b NA |
257 | } |
258 | ||
7355f276 | 259 | static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) |
6e909283 NA |
260 | { |
261 | int entries; | |
262 | ||
7355f276 TK |
263 | entries = (((const char *)txq->dirty_tx - |
264 | (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; | |
6e909283 | 265 | |
7355f276 | 266 | return entries >= 0 ? entries : entries + txq->bd.ring_size; |
6e909283 NA |
267 | } |
268 | ||
c20e599b | 269 | static void swap_buffer(void *bufaddr, int len) |
b5680e0b SG |
270 | { |
271 | int i; | |
272 | unsigned int *buf = bufaddr; | |
273 | ||
7b487d07 | 274 | for (i = 0; i < len; i += 4, buf++) |
e453789a | 275 | swab32s(buf); |
b5680e0b SG |
276 | } |
277 | ||
1310b544 LW |
278 | static void swap_buffer2(void *dst_buf, void *src_buf, int len) |
279 | { | |
280 | int i; | |
281 | unsigned int *src = src_buf; | |
282 | unsigned int *dst = dst_buf; | |
283 | ||
284 | for (i = 0; i < len; i += 4, src++, dst++) | |
285 | *dst = swab32p(src); | |
286 | } | |
287 | ||
344756f6 RK |
288 | static void fec_dump(struct net_device *ndev) |
289 | { | |
290 | struct fec_enet_private *fep = netdev_priv(ndev); | |
4d494cdc FD |
291 | struct bufdesc *bdp; |
292 | struct fec_enet_priv_tx_q *txq; | |
293 | int index = 0; | |
344756f6 RK |
294 | |
295 | netdev_info(ndev, "TX ring dump\n"); | |
296 | pr_info("Nr SC addr len SKB\n"); | |
297 | ||
4d494cdc | 298 | txq = fep->tx_queue[0]; |
7355f276 | 299 | bdp = txq->bd.base; |
4d494cdc | 300 | |
344756f6 | 301 | do { |
5cfa3039 | 302 | pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", |
344756f6 | 303 | index, |
7355f276 | 304 | bdp == txq->bd.cur ? 'S' : ' ', |
4d494cdc | 305 | bdp == txq->dirty_tx ? 'H' : ' ', |
5cfa3039 JB |
306 | fec16_to_cpu(bdp->cbd_sc), |
307 | fec32_to_cpu(bdp->cbd_bufaddr), | |
308 | fec16_to_cpu(bdp->cbd_datlen), | |
4d494cdc | 309 | txq->tx_skbuff[index]); |
7355f276 | 310 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
344756f6 | 311 | index++; |
7355f276 | 312 | } while (bdp != txq->bd.base); |
344756f6 RK |
313 | } |
314 | ||
62a02c98 FD |
315 | static inline bool is_ipv4_pkt(struct sk_buff *skb) |
316 | { | |
317 | return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; | |
318 | } | |
319 | ||
4c09eed9 JB |
320 | static int |
321 | fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) | |
322 | { | |
323 | /* Only run for packets requiring a checksum. */ | |
324 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
325 | return 0; | |
326 | ||
327 | if (unlikely(skb_cow_head(skb, 0))) | |
328 | return -1; | |
329 | ||
62a02c98 FD |
330 | if (is_ipv4_pkt(skb)) |
331 | ip_hdr(skb)->check = 0; | |
4c09eed9 JB |
332 | *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
c4bc44c6 | 337 | static struct bufdesc * |
4d494cdc FD |
338 | fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, |
339 | struct sk_buff *skb, | |
340 | struct net_device *ndev) | |
1da177e4 | 341 | { |
c556167f | 342 | struct fec_enet_private *fep = netdev_priv(ndev); |
7355f276 | 343 | struct bufdesc *bdp = txq->bd.cur; |
6e909283 NA |
344 | struct bufdesc_ex *ebdp; |
345 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
346 | int frag, frag_len; | |
347 | unsigned short status; | |
348 | unsigned int estatus = 0; | |
349 | skb_frag_t *this_frag; | |
de5fb0a0 | 350 | unsigned int index; |
6e909283 | 351 | void *bufaddr; |
d6bf3143 | 352 | dma_addr_t addr; |
6e909283 | 353 | int i; |
1da177e4 | 354 | |
6e909283 NA |
355 | for (frag = 0; frag < nr_frags; frag++) { |
356 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
7355f276 | 357 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
6e909283 NA |
358 | ebdp = (struct bufdesc_ex *)bdp; |
359 | ||
5cfa3039 | 360 | status = fec16_to_cpu(bdp->cbd_sc); |
6e909283 NA |
361 | status &= ~BD_ENET_TX_STATS; |
362 | status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); | |
363 | frag_len = skb_shinfo(skb)->frags[frag].size; | |
364 | ||
365 | /* Handle the last BD specially */ | |
366 | if (frag == nr_frags - 1) { | |
367 | status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); | |
368 | if (fep->bufdesc_ex) { | |
369 | estatus |= BD_ENET_TX_INT; | |
370 | if (unlikely(skb_shinfo(skb)->tx_flags & | |
371 | SKBTX_HW_TSTAMP && fep->hwts_tx_en)) | |
372 | estatus |= BD_ENET_TX_TS; | |
373 | } | |
374 | } | |
375 | ||
376 | if (fep->bufdesc_ex) { | |
6b7e4008 | 377 | if (fep->quirks & FEC_QUIRK_HAS_AVB) |
53bb20d1 | 378 | estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); |
6e909283 NA |
379 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
380 | estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; | |
381 | ebdp->cbd_bdu = 0; | |
5cfa3039 | 382 | ebdp->cbd_esc = cpu_to_fec32(estatus); |
6e909283 NA |
383 | } |
384 | ||
385 | bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; | |
386 | ||
7355f276 | 387 | index = fec_enet_get_bd_index(bdp, &txq->bd); |
41ef84ce | 388 | if (((unsigned long) bufaddr) & fep->tx_align || |
6b7e4008 | 389 | fep->quirks & FEC_QUIRK_SWAP_FRAME) { |
4d494cdc FD |
390 | memcpy(txq->tx_bounce[index], bufaddr, frag_len); |
391 | bufaddr = txq->tx_bounce[index]; | |
6e909283 | 392 | |
6b7e4008 | 393 | if (fep->quirks & FEC_QUIRK_SWAP_FRAME) |
6e909283 NA |
394 | swap_buffer(bufaddr, frag_len); |
395 | } | |
396 | ||
d6bf3143 RK |
397 | addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, |
398 | DMA_TO_DEVICE); | |
399 | if (dma_mapping_error(&fep->pdev->dev, addr)) { | |
6e909283 NA |
400 | if (net_ratelimit()) |
401 | netdev_err(ndev, "Tx DMA memory map failed\n"); | |
402 | goto dma_mapping_error; | |
403 | } | |
404 | ||
5cfa3039 JB |
405 | bdp->cbd_bufaddr = cpu_to_fec32(addr); |
406 | bdp->cbd_datlen = cpu_to_fec16(frag_len); | |
be293467 TK |
407 | /* Make sure the updates to rest of the descriptor are |
408 | * performed before transferring ownership. | |
409 | */ | |
410 | wmb(); | |
5cfa3039 | 411 | bdp->cbd_sc = cpu_to_fec16(status); |
6e909283 NA |
412 | } |
413 | ||
c4bc44c6 | 414 | return bdp; |
6e909283 | 415 | dma_mapping_error: |
7355f276 | 416 | bdp = txq->bd.cur; |
6e909283 | 417 | for (i = 0; i < frag; i++) { |
7355f276 | 418 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
5cfa3039 JB |
419 | dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), |
420 | fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); | |
6e909283 | 421 | } |
c4bc44c6 | 422 | return ERR_PTR(-ENOMEM); |
6e909283 | 423 | } |
1da177e4 | 424 | |
4d494cdc FD |
425 | static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, |
426 | struct sk_buff *skb, struct net_device *ndev) | |
6e909283 NA |
427 | { |
428 | struct fec_enet_private *fep = netdev_priv(ndev); | |
6e909283 NA |
429 | int nr_frags = skb_shinfo(skb)->nr_frags; |
430 | struct bufdesc *bdp, *last_bdp; | |
431 | void *bufaddr; | |
d6bf3143 | 432 | dma_addr_t addr; |
6e909283 NA |
433 | unsigned short status; |
434 | unsigned short buflen; | |
435 | unsigned int estatus = 0; | |
436 | unsigned int index; | |
79f33912 | 437 | int entries_free; |
22f6b860 | 438 | |
7355f276 | 439 | entries_free = fec_enet_get_free_txdesc_num(txq); |
79f33912 NA |
440 | if (entries_free < MAX_SKB_FRAGS + 1) { |
441 | dev_kfree_skb_any(skb); | |
442 | if (net_ratelimit()) | |
443 | netdev_err(ndev, "NOT enough BD for SG!\n"); | |
444 | return NETDEV_TX_OK; | |
445 | } | |
446 | ||
4c09eed9 JB |
447 | /* Protocol checksum off-load for TCP and UDP. */ |
448 | if (fec_enet_clear_csum(skb, ndev)) { | |
8e7e6874 | 449 | dev_kfree_skb_any(skb); |
4c09eed9 JB |
450 | return NETDEV_TX_OK; |
451 | } | |
452 | ||
6e909283 | 453 | /* Fill in a Tx ring entry */ |
7355f276 | 454 | bdp = txq->bd.cur; |
c4bc44c6 | 455 | last_bdp = bdp; |
5cfa3039 | 456 | status = fec16_to_cpu(bdp->cbd_sc); |
0e702ab3 | 457 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 458 | |
22f6b860 | 459 | /* Set buffer length and buffer pointer */ |
9555b31e | 460 | bufaddr = skb->data; |
6e909283 | 461 | buflen = skb_headlen(skb); |
1da177e4 | 462 | |
7355f276 | 463 | index = fec_enet_get_bd_index(bdp, &txq->bd); |
41ef84ce | 464 | if (((unsigned long) bufaddr) & fep->tx_align || |
6b7e4008 | 465 | fep->quirks & FEC_QUIRK_SWAP_FRAME) { |
4d494cdc FD |
466 | memcpy(txq->tx_bounce[index], skb->data, buflen); |
467 | bufaddr = txq->tx_bounce[index]; | |
1da177e4 | 468 | |
6b7e4008 | 469 | if (fep->quirks & FEC_QUIRK_SWAP_FRAME) |
6e909283 NA |
470 | swap_buffer(bufaddr, buflen); |
471 | } | |
6aa20a22 | 472 | |
d6bf3143 RK |
473 | /* Push the data cache so the CPM does not get stale memory data. */ |
474 | addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); | |
475 | if (dma_mapping_error(&fep->pdev->dev, addr)) { | |
d842a31f DFB |
476 | dev_kfree_skb_any(skb); |
477 | if (net_ratelimit()) | |
478 | netdev_err(ndev, "Tx DMA memory map failed\n"); | |
479 | return NETDEV_TX_OK; | |
480 | } | |
1da177e4 | 481 | |
6e909283 | 482 | if (nr_frags) { |
c4bc44c6 | 483 | last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); |
fc75ba51 TK |
484 | if (IS_ERR(last_bdp)) { |
485 | dma_unmap_single(&fep->pdev->dev, addr, | |
486 | buflen, DMA_TO_DEVICE); | |
487 | dev_kfree_skb_any(skb); | |
c4bc44c6 | 488 | return NETDEV_TX_OK; |
fc75ba51 | 489 | } |
6e909283 NA |
490 | } else { |
491 | status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); | |
492 | if (fep->bufdesc_ex) { | |
493 | estatus = BD_ENET_TX_INT; | |
494 | if (unlikely(skb_shinfo(skb)->tx_flags & | |
495 | SKBTX_HW_TSTAMP && fep->hwts_tx_en)) | |
496 | estatus |= BD_ENET_TX_TS; | |
497 | } | |
498 | } | |
fc75ba51 TK |
499 | bdp->cbd_bufaddr = cpu_to_fec32(addr); |
500 | bdp->cbd_datlen = cpu_to_fec16(buflen); | |
6e909283 | 501 | |
ff43da86 FL |
502 | if (fep->bufdesc_ex) { |
503 | ||
504 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
6e909283 | 505 | |
ff43da86 | 506 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
6e909283 | 507 | fep->hwts_tx_en)) |
6605b730 | 508 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
4c09eed9 | 509 | |
6b7e4008 | 510 | if (fep->quirks & FEC_QUIRK_HAS_AVB) |
53bb20d1 | 511 | estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); |
befe8213 | 512 | |
6e909283 NA |
513 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
514 | estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; | |
515 | ||
516 | ebdp->cbd_bdu = 0; | |
5cfa3039 | 517 | ebdp->cbd_esc = cpu_to_fec32(estatus); |
6605b730 | 518 | } |
03191656 | 519 | |
7355f276 | 520 | index = fec_enet_get_bd_index(last_bdp, &txq->bd); |
6e909283 | 521 | /* Save skb pointer */ |
4d494cdc | 522 | txq->tx_skbuff[index] = skb; |
6e909283 | 523 | |
be293467 TK |
524 | /* Make sure the updates to rest of the descriptor are performed before |
525 | * transferring ownership. | |
526 | */ | |
527 | wmb(); | |
6e909283 | 528 | |
fb8ef788 DFB |
529 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
530 | * it's the last BD of the frame, and to put the CRC on the end. | |
531 | */ | |
6e909283 | 532 | status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); |
5cfa3039 | 533 | bdp->cbd_sc = cpu_to_fec16(status); |
fb8ef788 | 534 | |
22f6b860 | 535 | /* If this was the last BD in the ring, start at the beginning again. */ |
7355f276 | 536 | bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); |
1da177e4 | 537 | |
7a2a8451 ED |
538 | skb_tx_timestamp(skb); |
539 | ||
c4bc44c6 | 540 | /* Make sure the update to bdp and tx_skbuff are performed before |
7355f276 | 541 | * txq->bd.cur. |
c4bc44c6 KH |
542 | */ |
543 | wmb(); | |
7355f276 | 544 | txq->bd.cur = bdp; |
de5fb0a0 | 545 | |
de5fb0a0 | 546 | /* Trigger transmission start */ |
53bb20d1 | 547 | writel(0, txq->bd.reg_desc_active); |
1da177e4 | 548 | |
6e909283 | 549 | return 0; |
1da177e4 LT |
550 | } |
551 | ||
79f33912 | 552 | static int |
4d494cdc FD |
553 | fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, |
554 | struct net_device *ndev, | |
555 | struct bufdesc *bdp, int index, char *data, | |
556 | int size, bool last_tcp, bool is_last) | |
61a4427b NA |
557 | { |
558 | struct fec_enet_private *fep = netdev_priv(ndev); | |
61cd2ebb | 559 | struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); |
79f33912 NA |
560 | unsigned short status; |
561 | unsigned int estatus = 0; | |
d6bf3143 | 562 | dma_addr_t addr; |
61a4427b | 563 | |
5cfa3039 | 564 | status = fec16_to_cpu(bdp->cbd_sc); |
79f33912 | 565 | status &= ~BD_ENET_TX_STATS; |
61a4427b | 566 | |
79f33912 | 567 | status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); |
79f33912 | 568 | |
41ef84ce | 569 | if (((unsigned long) data) & fep->tx_align || |
6b7e4008 | 570 | fep->quirks & FEC_QUIRK_SWAP_FRAME) { |
4d494cdc FD |
571 | memcpy(txq->tx_bounce[index], data, size); |
572 | data = txq->tx_bounce[index]; | |
79f33912 | 573 | |
6b7e4008 | 574 | if (fep->quirks & FEC_QUIRK_SWAP_FRAME) |
79f33912 NA |
575 | swap_buffer(data, size); |
576 | } | |
577 | ||
d6bf3143 RK |
578 | addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); |
579 | if (dma_mapping_error(&fep->pdev->dev, addr)) { | |
79f33912 | 580 | dev_kfree_skb_any(skb); |
6e909283 | 581 | if (net_ratelimit()) |
79f33912 | 582 | netdev_err(ndev, "Tx DMA memory map failed\n"); |
61a4427b NA |
583 | return NETDEV_TX_BUSY; |
584 | } | |
585 | ||
5cfa3039 JB |
586 | bdp->cbd_datlen = cpu_to_fec16(size); |
587 | bdp->cbd_bufaddr = cpu_to_fec32(addr); | |
d6bf3143 | 588 | |
79f33912 | 589 | if (fep->bufdesc_ex) { |
6b7e4008 | 590 | if (fep->quirks & FEC_QUIRK_HAS_AVB) |
53bb20d1 | 591 | estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); |
79f33912 NA |
592 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
593 | estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; | |
594 | ebdp->cbd_bdu = 0; | |
5cfa3039 | 595 | ebdp->cbd_esc = cpu_to_fec32(estatus); |
79f33912 NA |
596 | } |
597 | ||
598 | /* Handle the last BD specially */ | |
599 | if (last_tcp) | |
600 | status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); | |
601 | if (is_last) { | |
602 | status |= BD_ENET_TX_INTR; | |
603 | if (fep->bufdesc_ex) | |
5cfa3039 | 604 | ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); |
79f33912 NA |
605 | } |
606 | ||
5cfa3039 | 607 | bdp->cbd_sc = cpu_to_fec16(status); |
79f33912 NA |
608 | |
609 | return 0; | |
610 | } | |
611 | ||
612 | static int | |
4d494cdc FD |
613 | fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, |
614 | struct sk_buff *skb, struct net_device *ndev, | |
615 | struct bufdesc *bdp, int index) | |
79f33912 NA |
616 | { |
617 | struct fec_enet_private *fep = netdev_priv(ndev); | |
79f33912 | 618 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
61cd2ebb | 619 | struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); |
79f33912 NA |
620 | void *bufaddr; |
621 | unsigned long dmabuf; | |
622 | unsigned short status; | |
623 | unsigned int estatus = 0; | |
624 | ||
5cfa3039 | 625 | status = fec16_to_cpu(bdp->cbd_sc); |
79f33912 NA |
626 | status &= ~BD_ENET_TX_STATS; |
627 | status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); | |
628 | ||
4d494cdc FD |
629 | bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; |
630 | dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; | |
41ef84ce | 631 | if (((unsigned long)bufaddr) & fep->tx_align || |
6b7e4008 | 632 | fep->quirks & FEC_QUIRK_SWAP_FRAME) { |
4d494cdc FD |
633 | memcpy(txq->tx_bounce[index], skb->data, hdr_len); |
634 | bufaddr = txq->tx_bounce[index]; | |
79f33912 | 635 | |
6b7e4008 | 636 | if (fep->quirks & FEC_QUIRK_SWAP_FRAME) |
79f33912 NA |
637 | swap_buffer(bufaddr, hdr_len); |
638 | ||
639 | dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, | |
640 | hdr_len, DMA_TO_DEVICE); | |
641 | if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { | |
642 | dev_kfree_skb_any(skb); | |
643 | if (net_ratelimit()) | |
644 | netdev_err(ndev, "Tx DMA memory map failed\n"); | |
645 | return NETDEV_TX_BUSY; | |
646 | } | |
647 | } | |
648 | ||
5cfa3039 JB |
649 | bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); |
650 | bdp->cbd_datlen = cpu_to_fec16(hdr_len); | |
79f33912 NA |
651 | |
652 | if (fep->bufdesc_ex) { | |
6b7e4008 | 653 | if (fep->quirks & FEC_QUIRK_HAS_AVB) |
53bb20d1 | 654 | estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); |
79f33912 NA |
655 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
656 | estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; | |
657 | ebdp->cbd_bdu = 0; | |
5cfa3039 | 658 | ebdp->cbd_esc = cpu_to_fec32(estatus); |
79f33912 NA |
659 | } |
660 | ||
5cfa3039 | 661 | bdp->cbd_sc = cpu_to_fec16(status); |
79f33912 NA |
662 | |
663 | return 0; | |
664 | } | |
665 | ||
4d494cdc FD |
666 | static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, |
667 | struct sk_buff *skb, | |
668 | struct net_device *ndev) | |
79f33912 NA |
669 | { |
670 | struct fec_enet_private *fep = netdev_priv(ndev); | |
671 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
672 | int total_len, data_left; | |
7355f276 | 673 | struct bufdesc *bdp = txq->bd.cur; |
79f33912 NA |
674 | struct tso_t tso; |
675 | unsigned int index = 0; | |
676 | int ret; | |
677 | ||
7355f276 | 678 | if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { |
79f33912 NA |
679 | dev_kfree_skb_any(skb); |
680 | if (net_ratelimit()) | |
681 | netdev_err(ndev, "NOT enough BD for TSO!\n"); | |
682 | return NETDEV_TX_OK; | |
683 | } | |
684 | ||
685 | /* Protocol checksum off-load for TCP and UDP. */ | |
686 | if (fec_enet_clear_csum(skb, ndev)) { | |
687 | dev_kfree_skb_any(skb); | |
688 | return NETDEV_TX_OK; | |
689 | } | |
690 | ||
691 | /* Initialize the TSO handler, and prepare the first payload */ | |
692 | tso_start(skb, &tso); | |
693 | ||
694 | total_len = skb->len - hdr_len; | |
695 | while (total_len > 0) { | |
696 | char *hdr; | |
697 | ||
7355f276 | 698 | index = fec_enet_get_bd_index(bdp, &txq->bd); |
79f33912 NA |
699 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); |
700 | total_len -= data_left; | |
701 | ||
702 | /* prepare packet headers: MAC + IP + TCP */ | |
4d494cdc | 703 | hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; |
79f33912 | 704 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); |
4d494cdc | 705 | ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); |
79f33912 NA |
706 | if (ret) |
707 | goto err_release; | |
708 | ||
709 | while (data_left > 0) { | |
710 | int size; | |
711 | ||
712 | size = min_t(int, tso.size, data_left); | |
7355f276 TK |
713 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
714 | index = fec_enet_get_bd_index(bdp, &txq->bd); | |
4d494cdc FD |
715 | ret = fec_enet_txq_put_data_tso(txq, skb, ndev, |
716 | bdp, index, | |
717 | tso.data, size, | |
718 | size == data_left, | |
79f33912 NA |
719 | total_len == 0); |
720 | if (ret) | |
721 | goto err_release; | |
722 | ||
723 | data_left -= size; | |
724 | tso_build_data(skb, &tso, size); | |
725 | } | |
726 | ||
7355f276 | 727 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
79f33912 NA |
728 | } |
729 | ||
730 | /* Save skb pointer */ | |
4d494cdc | 731 | txq->tx_skbuff[index] = skb; |
79f33912 | 732 | |
79f33912 | 733 | skb_tx_timestamp(skb); |
7355f276 | 734 | txq->bd.cur = bdp; |
79f33912 NA |
735 | |
736 | /* Trigger transmission start */ | |
6b7e4008 | 737 | if (!(fep->quirks & FEC_QUIRK_ERR007885) || |
53bb20d1 TK |
738 | !readl(txq->bd.reg_desc_active) || |
739 | !readl(txq->bd.reg_desc_active) || | |
740 | !readl(txq->bd.reg_desc_active) || | |
741 | !readl(txq->bd.reg_desc_active)) | |
742 | writel(0, txq->bd.reg_desc_active); | |
79f33912 NA |
743 | |
744 | return 0; | |
745 | ||
746 | err_release: | |
747 | /* TODO: Release all used data descriptors for TSO */ | |
748 | return ret; | |
749 | } | |
750 | ||
751 | static netdev_tx_t | |
752 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
753 | { | |
754 | struct fec_enet_private *fep = netdev_priv(ndev); | |
755 | int entries_free; | |
4d494cdc FD |
756 | unsigned short queue; |
757 | struct fec_enet_priv_tx_q *txq; | |
758 | struct netdev_queue *nq; | |
79f33912 NA |
759 | int ret; |
760 | ||
4d494cdc FD |
761 | queue = skb_get_queue_mapping(skb); |
762 | txq = fep->tx_queue[queue]; | |
763 | nq = netdev_get_tx_queue(ndev, queue); | |
764 | ||
79f33912 | 765 | if (skb_is_gso(skb)) |
4d494cdc | 766 | ret = fec_enet_txq_submit_tso(txq, skb, ndev); |
79f33912 | 767 | else |
4d494cdc | 768 | ret = fec_enet_txq_submit_skb(txq, skb, ndev); |
6e909283 NA |
769 | if (ret) |
770 | return ret; | |
61a4427b | 771 | |
7355f276 | 772 | entries_free = fec_enet_get_free_txdesc_num(txq); |
4d494cdc FD |
773 | if (entries_free <= txq->tx_stop_threshold) |
774 | netif_tx_stop_queue(nq); | |
61a4427b NA |
775 | |
776 | return NETDEV_TX_OK; | |
777 | } | |
778 | ||
14109a59 FL |
779 | /* Init RX & TX buffer descriptors |
780 | */ | |
781 | static void fec_enet_bd_init(struct net_device *dev) | |
782 | { | |
783 | struct fec_enet_private *fep = netdev_priv(dev); | |
4d494cdc FD |
784 | struct fec_enet_priv_tx_q *txq; |
785 | struct fec_enet_priv_rx_q *rxq; | |
14109a59 FL |
786 | struct bufdesc *bdp; |
787 | unsigned int i; | |
59d0f746 | 788 | unsigned int q; |
14109a59 | 789 | |
59d0f746 FL |
790 | for (q = 0; q < fep->num_rx_queues; q++) { |
791 | /* Initialize the receive buffer descriptors. */ | |
792 | rxq = fep->rx_queue[q]; | |
7355f276 | 793 | bdp = rxq->bd.base; |
4d494cdc | 794 | |
7355f276 | 795 | for (i = 0; i < rxq->bd.ring_size; i++) { |
14109a59 | 796 | |
59d0f746 FL |
797 | /* Initialize the BD for every fragment in the page. */ |
798 | if (bdp->cbd_bufaddr) | |
5cfa3039 | 799 | bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); |
59d0f746 | 800 | else |
5cfa3039 | 801 | bdp->cbd_sc = cpu_to_fec16(0); |
7355f276 | 802 | bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); |
59d0f746 FL |
803 | } |
804 | ||
805 | /* Set the last buffer to wrap */ | |
7355f276 | 806 | bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); |
5cfa3039 | 807 | bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); |
59d0f746 | 808 | |
7355f276 | 809 | rxq->bd.cur = rxq->bd.base; |
59d0f746 FL |
810 | } |
811 | ||
812 | for (q = 0; q < fep->num_tx_queues; q++) { | |
813 | /* ...and the same for transmit */ | |
814 | txq = fep->tx_queue[q]; | |
7355f276 TK |
815 | bdp = txq->bd.base; |
816 | txq->bd.cur = bdp; | |
59d0f746 | 817 | |
7355f276 | 818 | for (i = 0; i < txq->bd.ring_size; i++) { |
59d0f746 | 819 | /* Initialize the BD for every fragment in the page. */ |
5cfa3039 | 820 | bdp->cbd_sc = cpu_to_fec16(0); |
178e5f57 FD |
821 | if (bdp->cbd_bufaddr && |
822 | !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) | |
823 | dma_unmap_single(&fep->pdev->dev, | |
824 | fec32_to_cpu(bdp->cbd_bufaddr), | |
825 | fec16_to_cpu(bdp->cbd_datlen), | |
826 | DMA_TO_DEVICE); | |
59d0f746 FL |
827 | if (txq->tx_skbuff[i]) { |
828 | dev_kfree_skb_any(txq->tx_skbuff[i]); | |
829 | txq->tx_skbuff[i] = NULL; | |
830 | } | |
5cfa3039 | 831 | bdp->cbd_bufaddr = cpu_to_fec32(0); |
7355f276 | 832 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
59d0f746 FL |
833 | } |
834 | ||
835 | /* Set the last buffer to wrap */ | |
7355f276 | 836 | bdp = fec_enet_get_prevdesc(bdp, &txq->bd); |
5cfa3039 | 837 | bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); |
59d0f746 | 838 | txq->dirty_tx = bdp; |
14109a59 | 839 | } |
59d0f746 | 840 | } |
14109a59 | 841 | |
ce99d0d3 FL |
842 | static void fec_enet_active_rxring(struct net_device *ndev) |
843 | { | |
844 | struct fec_enet_private *fep = netdev_priv(ndev); | |
845 | int i; | |
846 | ||
847 | for (i = 0; i < fep->num_rx_queues; i++) | |
53bb20d1 | 848 | writel(0, fep->rx_queue[i]->bd.reg_desc_active); |
ce99d0d3 FL |
849 | } |
850 | ||
59d0f746 FL |
851 | static void fec_enet_enable_ring(struct net_device *ndev) |
852 | { | |
853 | struct fec_enet_private *fep = netdev_priv(ndev); | |
854 | struct fec_enet_priv_tx_q *txq; | |
855 | struct fec_enet_priv_rx_q *rxq; | |
856 | int i; | |
14109a59 | 857 | |
59d0f746 FL |
858 | for (i = 0; i < fep->num_rx_queues; i++) { |
859 | rxq = fep->rx_queue[i]; | |
7355f276 | 860 | writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); |
fbbeefdd | 861 | writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); |
14109a59 | 862 | |
59d0f746 FL |
863 | /* enable DMA1/2 */ |
864 | if (i) | |
865 | writel(RCMR_MATCHEN | RCMR_CMP(i), | |
866 | fep->hwp + FEC_RCMR(i)); | |
867 | } | |
14109a59 | 868 | |
59d0f746 FL |
869 | for (i = 0; i < fep->num_tx_queues; i++) { |
870 | txq = fep->tx_queue[i]; | |
7355f276 | 871 | writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); |
59d0f746 FL |
872 | |
873 | /* enable DMA1/2 */ | |
874 | if (i) | |
875 | writel(DMA_CLASS_EN | IDLE_SLOPE(i), | |
876 | fep->hwp + FEC_DMA_CFG(i)); | |
14109a59 | 877 | } |
59d0f746 | 878 | } |
14109a59 | 879 | |
59d0f746 FL |
880 | static void fec_enet_reset_skb(struct net_device *ndev) |
881 | { | |
882 | struct fec_enet_private *fep = netdev_priv(ndev); | |
883 | struct fec_enet_priv_tx_q *txq; | |
884 | int i, j; | |
885 | ||
886 | for (i = 0; i < fep->num_tx_queues; i++) { | |
887 | txq = fep->tx_queue[i]; | |
888 | ||
7355f276 | 889 | for (j = 0; j < txq->bd.ring_size; j++) { |
59d0f746 FL |
890 | if (txq->tx_skbuff[j]) { |
891 | dev_kfree_skb_any(txq->tx_skbuff[j]); | |
892 | txq->tx_skbuff[j] = NULL; | |
893 | } | |
894 | } | |
895 | } | |
14109a59 FL |
896 | } |
897 | ||
dbc64a8e RK |
898 | /* |
899 | * This function is called to start or restart the FEC during a link | |
900 | * change, transmit timeout, or to reconfigure the FEC. The network | |
901 | * packet processing for this device must be stopped before this call. | |
45993653 | 902 | */ |
1da177e4 | 903 | static void |
ef83337d | 904 | fec_restart(struct net_device *ndev) |
1da177e4 | 905 | { |
c556167f | 906 | struct fec_enet_private *fep = netdev_priv(ndev); |
4c09eed9 | 907 | u32 val; |
cd1f402c UKK |
908 | u32 temp_mac[2]; |
909 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 910 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 911 | |
106c314c FD |
912 | /* Whack a reset. We should wait for this. |
913 | * For i.MX6SX SOC, enet use AXI bus, we use disable MAC | |
914 | * instead of reset MAC itself. | |
915 | */ | |
6b7e4008 | 916 | if (fep->quirks & FEC_QUIRK_HAS_AVB) { |
106c314c FD |
917 | writel(0, fep->hwp + FEC_ECNTRL); |
918 | } else { | |
919 | writel(1, fep->hwp + FEC_ECNTRL); | |
920 | udelay(10); | |
921 | } | |
1da177e4 | 922 | |
45993653 UKK |
923 | /* |
924 | * enet-mac reset will reset mac address registers too, | |
925 | * so need to reconfigure it. | |
926 | */ | |
b82d44d7 GS |
927 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); |
928 | writel((__force u32)cpu_to_be32(temp_mac[0]), | |
929 | fep->hwp + FEC_ADDR_LOW); | |
930 | writel((__force u32)cpu_to_be32(temp_mac[1]), | |
931 | fep->hwp + FEC_ADDR_HIGH); | |
1da177e4 | 932 | |
45993653 | 933 | /* Clear any outstanding interrupt. */ |
e17f7fec | 934 | writel(0xffffffff, fep->hwp + FEC_IEVENT); |
1da177e4 | 935 | |
14109a59 FL |
936 | fec_enet_bd_init(ndev); |
937 | ||
59d0f746 | 938 | fec_enet_enable_ring(ndev); |
45993653 | 939 | |
59d0f746 FL |
940 | /* Reset tx SKB buffers. */ |
941 | fec_enet_reset_skb(ndev); | |
97b72e43 | 942 | |
45993653 | 943 | /* Enable MII mode */ |
ef83337d | 944 | if (fep->full_duplex == DUPLEX_FULL) { |
cd1f402c | 945 | /* FD enable */ |
45993653 UKK |
946 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
947 | } else { | |
cd1f402c UKK |
948 | /* No Rcv on Xmit */ |
949 | rcntl |= 0x02; | |
45993653 UKK |
950 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
951 | } | |
cd1f402c | 952 | |
45993653 UKK |
953 | /* Set MII speed */ |
954 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
955 | ||
d1391930 | 956 | #if !defined(CONFIG_M5272) |
18803495 | 957 | if (fep->quirks & FEC_QUIRK_HAS_RACC) { |
18803495 | 958 | val = readl(fep->hwp + FEC_RACC); |
3ac72b7b EN |
959 | /* align IP header */ |
960 | val |= FEC_RACC_SHIFT16; | |
18803495 | 961 | if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) |
3ac72b7b | 962 | /* set RX checksum */ |
18803495 GU |
963 | val |= FEC_RACC_OPTIONS; |
964 | else | |
965 | val &= ~FEC_RACC_OPTIONS; | |
966 | writel(val, fep->hwp + FEC_RACC); | |
32867fcc | 967 | writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); |
18803495 | 968 | } |
d1391930 | 969 | #endif |
4c09eed9 | 970 | |
45993653 UKK |
971 | /* |
972 | * The phy interface and speed need to get configured | |
973 | * differently on enet-mac. | |
974 | */ | |
6b7e4008 | 975 | if (fep->quirks & FEC_QUIRK_ENET_MAC) { |
cd1f402c UKK |
976 | /* Enable flow control and length check */ |
977 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 978 | |
230dec61 | 979 | /* RGMII, RMII or MII */ |
e813bb2b MP |
980 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || |
981 | fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || | |
982 | fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || | |
983 | fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
230dec61 SG |
984 | rcntl |= (1 << 6); |
985 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 986 | rcntl |= (1 << 8); |
45993653 | 987 | else |
cd1f402c | 988 | rcntl &= ~(1 << 8); |
45993653 | 989 | |
230dec61 | 990 | /* 1G, 100M or 10M */ |
45f5c327 PR |
991 | if (ndev->phydev) { |
992 | if (ndev->phydev->speed == SPEED_1000) | |
230dec61 | 993 | ecntl |= (1 << 5); |
45f5c327 | 994 | else if (ndev->phydev->speed == SPEED_100) |
230dec61 SG |
995 | rcntl &= ~(1 << 9); |
996 | else | |
997 | rcntl |= (1 << 9); | |
998 | } | |
45993653 UKK |
999 | } else { |
1000 | #ifdef FEC_MIIGSK_ENR | |
6b7e4008 | 1001 | if (fep->quirks & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 1002 | u32 cfgr; |
45993653 UKK |
1003 | /* disable the gasket and wait */ |
1004 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
1005 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
1006 | udelay(1); | |
1007 | ||
1008 | /* | |
1009 | * configure the gasket: | |
1010 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 1011 | * MII, 25 MHz, no loopback, no echo |
45993653 | 1012 | */ |
8d82f219 EB |
1013 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
1014 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
45f5c327 | 1015 | if (ndev->phydev && ndev->phydev->speed == SPEED_10) |
8d82f219 EB |
1016 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; |
1017 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
1018 | |
1019 | /* re-enable the gasket */ | |
1020 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 1021 | } |
45993653 UKK |
1022 | #endif |
1023 | } | |
baa70a5c | 1024 | |
d1391930 | 1025 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
1026 | /* enable pause frame*/ |
1027 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
1028 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
45f5c327 | 1029 | ndev->phydev && ndev->phydev->pause)) { |
baa70a5c FL |
1030 | rcntl |= FEC_ENET_FCE; |
1031 | ||
4c09eed9 | 1032 | /* set FIFO threshold parameter to reduce overrun */ |
baa70a5c FL |
1033 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); |
1034 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
1035 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
1036 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
1037 | ||
1038 | /* OPD */ | |
1039 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
1040 | } else { | |
1041 | rcntl &= ~FEC_ENET_FCE; | |
1042 | } | |
d1391930 | 1043 | #endif /* !defined(CONFIG_M5272) */ |
baa70a5c | 1044 | |
cd1f402c | 1045 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 1046 | |
84fe6182 SW |
1047 | /* Setup multicast filter. */ |
1048 | set_multicast_list(ndev); | |
1049 | #ifndef CONFIG_M5272 | |
1050 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
1051 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
1052 | #endif | |
1053 | ||
6b7e4008 | 1054 | if (fep->quirks & FEC_QUIRK_ENET_MAC) { |
230dec61 SG |
1055 | /* enable ENET endian swap */ |
1056 | ecntl |= (1 << 8); | |
1057 | /* enable ENET store and forward mode */ | |
1058 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
1059 | } | |
1060 | ||
ff43da86 FL |
1061 | if (fep->bufdesc_ex) |
1062 | ecntl |= (1 << 4); | |
6605b730 | 1063 | |
38ae92dc | 1064 | #ifndef CONFIG_M5272 |
b9eef55c JB |
1065 | /* Enable the MIB statistic event counters */ |
1066 | writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); | |
38ae92dc CH |
1067 | #endif |
1068 | ||
45993653 | 1069 | /* And last, enable the transmit and receive processing */ |
230dec61 | 1070 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
ce99d0d3 | 1071 | fec_enet_active_rxring(ndev); |
45993653 | 1072 | |
ff43da86 FL |
1073 | if (fep->bufdesc_ex) |
1074 | fec_ptp_start_cyclecounter(ndev); | |
1075 | ||
45993653 | 1076 | /* Enable interrupts we wish to service */ |
0c5a3aef NA |
1077 | if (fep->link) |
1078 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
1079 | else | |
1080 | writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); | |
d851b47b FD |
1081 | |
1082 | /* Init the interrupt coalescing */ | |
1083 | fec_enet_itr_coal_init(ndev); | |
1084 | ||
45993653 UKK |
1085 | } |
1086 | ||
1087 | static void | |
1088 | fec_stop(struct net_device *ndev) | |
1089 | { | |
1090 | struct fec_enet_private *fep = netdev_priv(ndev); | |
de40ed31 | 1091 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
42431dc2 | 1092 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
de40ed31 | 1093 | u32 val; |
45993653 UKK |
1094 | |
1095 | /* We cannot expect a graceful transmit stop without link !!! */ | |
1096 | if (fep->link) { | |
1097 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
1098 | udelay(10); | |
1099 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
31b7720c | 1100 | netdev_err(ndev, "Graceful transmit stop did not complete!\n"); |
45993653 UKK |
1101 | } |
1102 | ||
106c314c FD |
1103 | /* Whack a reset. We should wait for this. |
1104 | * For i.MX6SX SOC, enet use AXI bus, we use disable MAC | |
1105 | * instead of reset MAC itself. | |
1106 | */ | |
de40ed31 NA |
1107 | if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { |
1108 | if (fep->quirks & FEC_QUIRK_HAS_AVB) { | |
1109 | writel(0, fep->hwp + FEC_ECNTRL); | |
1110 | } else { | |
1111 | writel(1, fep->hwp + FEC_ECNTRL); | |
1112 | udelay(10); | |
1113 | } | |
1114 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
106c314c | 1115 | } else { |
de40ed31 NA |
1116 | writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); |
1117 | val = readl(fep->hwp + FEC_ECNTRL); | |
1118 | val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); | |
1119 | writel(val, fep->hwp + FEC_ECNTRL); | |
1120 | ||
1121 | if (pdata && pdata->sleep_mode_enable) | |
1122 | pdata->sleep_mode_enable(true); | |
106c314c | 1123 | } |
45993653 | 1124 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
230dec61 SG |
1125 | |
1126 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
de40ed31 NA |
1127 | if (fep->quirks & FEC_QUIRK_ENET_MAC && |
1128 | !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { | |
230dec61 | 1129 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
1130 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
1131 | } | |
1da177e4 LT |
1132 | } |
1133 | ||
1134 | ||
45993653 UKK |
1135 | static void |
1136 | fec_timeout(struct net_device *ndev) | |
1137 | { | |
1138 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1139 | ||
344756f6 RK |
1140 | fec_dump(ndev); |
1141 | ||
45993653 UKK |
1142 | ndev->stats.tx_errors++; |
1143 | ||
36cdc743 | 1144 | schedule_work(&fep->tx_timeout_work); |
54309fa6 FL |
1145 | } |
1146 | ||
36cdc743 | 1147 | static void fec_enet_timeout_work(struct work_struct *work) |
54309fa6 FL |
1148 | { |
1149 | struct fec_enet_private *fep = | |
36cdc743 | 1150 | container_of(work, struct fec_enet_private, tx_timeout_work); |
8ce5624f | 1151 | struct net_device *ndev = fep->netdev; |
54309fa6 | 1152 | |
36cdc743 RK |
1153 | rtnl_lock(); |
1154 | if (netif_device_present(ndev) || netif_running(ndev)) { | |
1155 | napi_disable(&fep->napi); | |
1156 | netif_tx_lock_bh(ndev); | |
1157 | fec_restart(ndev); | |
1158 | netif_wake_queue(ndev); | |
1159 | netif_tx_unlock_bh(ndev); | |
1160 | napi_enable(&fep->napi); | |
54309fa6 | 1161 | } |
36cdc743 | 1162 | rtnl_unlock(); |
45993653 UKK |
1163 | } |
1164 | ||
bfd4ecdd RK |
1165 | static void |
1166 | fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, | |
1167 | struct skb_shared_hwtstamps *hwtstamps) | |
1168 | { | |
1169 | unsigned long flags; | |
1170 | u64 ns; | |
1171 | ||
1172 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
1173 | ns = timecounter_cyc2time(&fep->tc, ts); | |
1174 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); | |
1175 | ||
1176 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
1177 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
1178 | } | |
1179 | ||
1da177e4 | 1180 | static void |
4d494cdc | 1181 | fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) |
1da177e4 LT |
1182 | { |
1183 | struct fec_enet_private *fep; | |
a2fe37b6 | 1184 | struct bufdesc *bdp; |
0e702ab3 | 1185 | unsigned short status; |
1da177e4 | 1186 | struct sk_buff *skb; |
4d494cdc FD |
1187 | struct fec_enet_priv_tx_q *txq; |
1188 | struct netdev_queue *nq; | |
de5fb0a0 | 1189 | int index = 0; |
79f33912 | 1190 | int entries_free; |
1da177e4 | 1191 | |
c556167f | 1192 | fep = netdev_priv(ndev); |
4d494cdc FD |
1193 | |
1194 | queue_id = FEC_ENET_GET_QUQUE(queue_id); | |
1195 | ||
1196 | txq = fep->tx_queue[queue_id]; | |
1197 | /* get next bdp of dirty_tx */ | |
1198 | nq = netdev_get_tx_queue(ndev, queue_id); | |
1199 | bdp = txq->dirty_tx; | |
1da177e4 | 1200 | |
de5fb0a0 | 1201 | /* get next bdp of dirty_tx */ |
7355f276 | 1202 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
de5fb0a0 | 1203 | |
7355f276 TK |
1204 | while (bdp != READ_ONCE(txq->bd.cur)) { |
1205 | /* Order the load of bd.cur and cbd_sc */ | |
c4bc44c6 | 1206 | rmb(); |
5cfa3039 | 1207 | status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); |
c4bc44c6 | 1208 | if (status & BD_ENET_TX_READY) |
f0b3fbea SH |
1209 | break; |
1210 | ||
7355f276 | 1211 | index = fec_enet_get_bd_index(bdp, &txq->bd); |
2b995f63 | 1212 | |
a2fe37b6 | 1213 | skb = txq->tx_skbuff[index]; |
2b995f63 | 1214 | txq->tx_skbuff[index] = NULL; |
5cfa3039 JB |
1215 | if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) |
1216 | dma_unmap_single(&fep->pdev->dev, | |
1217 | fec32_to_cpu(bdp->cbd_bufaddr), | |
1218 | fec16_to_cpu(bdp->cbd_datlen), | |
1219 | DMA_TO_DEVICE); | |
1220 | bdp->cbd_bufaddr = cpu_to_fec32(0); | |
7fafe803 TK |
1221 | if (!skb) |
1222 | goto skb_done; | |
de5fb0a0 | 1223 | |
1da177e4 | 1224 | /* Check for errors. */ |
0e702ab3 | 1225 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
1226 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
1227 | BD_ENET_TX_CSL)) { | |
c556167f | 1228 | ndev->stats.tx_errors++; |
0e702ab3 | 1229 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 1230 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 1231 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 1232 | ndev->stats.tx_window_errors++; |
0e702ab3 | 1233 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 1234 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 1235 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 1236 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 1237 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 1238 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 1239 | } else { |
c556167f | 1240 | ndev->stats.tx_packets++; |
6e909283 | 1241 | ndev->stats.tx_bytes += skb->len; |
1da177e4 LT |
1242 | } |
1243 | ||
ff43da86 FL |
1244 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
1245 | fep->bufdesc_ex) { | |
6605b730 | 1246 | struct skb_shared_hwtstamps shhwtstamps; |
ff43da86 | 1247 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 | 1248 | |
5cfa3039 | 1249 | fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); |
6605b730 FL |
1250 | skb_tstamp_tx(skb, &shhwtstamps); |
1251 | } | |
ff43da86 | 1252 | |
1da177e4 LT |
1253 | /* Deferred means some collisions occurred during transmit, |
1254 | * but we eventually sent the packet OK. | |
1255 | */ | |
0e702ab3 | 1256 | if (status & BD_ENET_TX_DEF) |
c556167f | 1257 | ndev->stats.collisions++; |
6aa20a22 | 1258 | |
22f6b860 | 1259 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 1260 | dev_kfree_skb_any(skb); |
7fafe803 | 1261 | skb_done: |
c4bc44c6 KH |
1262 | /* Make sure the update to bdp and tx_skbuff are performed |
1263 | * before dirty_tx | |
1264 | */ | |
1265 | wmb(); | |
4d494cdc | 1266 | txq->dirty_tx = bdp; |
6aa20a22 | 1267 | |
22f6b860 | 1268 | /* Update pointer to next buffer descriptor to be transmitted */ |
7355f276 | 1269 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
6aa20a22 | 1270 | |
22f6b860 | 1271 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 1272 | */ |
79f33912 | 1273 | if (netif_queue_stopped(ndev)) { |
7355f276 | 1274 | entries_free = fec_enet_get_free_txdesc_num(txq); |
4d494cdc FD |
1275 | if (entries_free >= txq->tx_wake_threshold) |
1276 | netif_tx_wake_queue(nq); | |
79f33912 | 1277 | } |
1da177e4 | 1278 | } |
ccea2968 | 1279 | |
c10bc0e7 | 1280 | /* ERR006358: Keep the transmitter going */ |
7355f276 | 1281 | if (bdp != txq->bd.cur && |
53bb20d1 TK |
1282 | readl(txq->bd.reg_desc_active) == 0) |
1283 | writel(0, txq->bd.reg_desc_active); | |
4d494cdc FD |
1284 | } |
1285 | ||
1286 | static void | |
1287 | fec_enet_tx(struct net_device *ndev) | |
1288 | { | |
1289 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1290 | u16 queue_id; | |
1291 | /* First process class A queue, then Class B and Best Effort queue */ | |
1292 | for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { | |
1293 | clear_bit(queue_id, &fep->work_tx); | |
1294 | fec_enet_tx_queue(ndev, queue_id); | |
1295 | } | |
1296 | return; | |
1da177e4 LT |
1297 | } |
1298 | ||
1b7bde6d NA |
1299 | static int |
1300 | fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) | |
1301 | { | |
1302 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1303 | int off; | |
1304 | ||
1305 | off = ((unsigned long)skb->data) & fep->rx_align; | |
1306 | if (off) | |
1307 | skb_reserve(skb, fep->rx_align + 1 - off); | |
1308 | ||
5cfa3039 JB |
1309 | bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); |
1310 | if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { | |
1b7bde6d NA |
1311 | if (net_ratelimit()) |
1312 | netdev_err(ndev, "Rx DMA memory map failed\n"); | |
1313 | return -ENOMEM; | |
1314 | } | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, | |
1310b544 | 1320 | struct bufdesc *bdp, u32 length, bool swap) |
1b7bde6d NA |
1321 | { |
1322 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1323 | struct sk_buff *new_skb; | |
1324 | ||
1325 | if (length > fep->rx_copybreak) | |
1326 | return false; | |
1327 | ||
1328 | new_skb = netdev_alloc_skb(ndev, length); | |
1329 | if (!new_skb) | |
1330 | return false; | |
1331 | ||
5cfa3039 JB |
1332 | dma_sync_single_for_cpu(&fep->pdev->dev, |
1333 | fec32_to_cpu(bdp->cbd_bufaddr), | |
1b7bde6d NA |
1334 | FEC_ENET_RX_FRSIZE - fep->rx_align, |
1335 | DMA_FROM_DEVICE); | |
1310b544 LW |
1336 | if (!swap) |
1337 | memcpy(new_skb->data, (*skb)->data, length); | |
1338 | else | |
1339 | swap_buffer2(new_skb->data, (*skb)->data, length); | |
1b7bde6d NA |
1340 | *skb = new_skb; |
1341 | ||
1342 | return true; | |
1343 | } | |
1344 | ||
7355f276 | 1345 | /* During a receive, the bd_rx.cur points to the current incoming buffer. |
1da177e4 LT |
1346 | * When we update through the ring, if the next incoming buffer has |
1347 | * not been given to the system, we just set the empty indicator, | |
1348 | * effectively tossing the packet. | |
1349 | */ | |
dc975382 | 1350 | static int |
4d494cdc | 1351 | fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) |
1da177e4 | 1352 | { |
c556167f | 1353 | struct fec_enet_private *fep = netdev_priv(ndev); |
4d494cdc | 1354 | struct fec_enet_priv_rx_q *rxq; |
2e28532f | 1355 | struct bufdesc *bdp; |
0e702ab3 | 1356 | unsigned short status; |
1b7bde6d NA |
1357 | struct sk_buff *skb_new = NULL; |
1358 | struct sk_buff *skb; | |
1da177e4 LT |
1359 | ushort pkt_len; |
1360 | __u8 *data; | |
dc975382 | 1361 | int pkt_received = 0; |
cdffcf1b JB |
1362 | struct bufdesc_ex *ebdp = NULL; |
1363 | bool vlan_packet_rcvd = false; | |
1364 | u16 vlan_tag; | |
d842a31f | 1365 | int index = 0; |
1b7bde6d | 1366 | bool is_copybreak; |
6b7e4008 | 1367 | bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; |
6aa20a22 | 1368 | |
0e702ab3 GU |
1369 | #ifdef CONFIG_M532x |
1370 | flush_cache_all(); | |
6aa20a22 | 1371 | #endif |
4d494cdc FD |
1372 | queue_id = FEC_ENET_GET_QUQUE(queue_id); |
1373 | rxq = fep->rx_queue[queue_id]; | |
1da177e4 | 1374 | |
1da177e4 LT |
1375 | /* First, grab all of the stats for the incoming packet. |
1376 | * These get messed up if we get called due to a busy condition. | |
1377 | */ | |
7355f276 | 1378 | bdp = rxq->bd.cur; |
1da177e4 | 1379 | |
5cfa3039 | 1380 | while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 1381 | |
dc975382 FL |
1382 | if (pkt_received >= budget) |
1383 | break; | |
1384 | pkt_received++; | |
1385 | ||
ed63f1dc | 1386 | writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); |
db3421c1 | 1387 | |
22f6b860 | 1388 | /* Check for errors. */ |
095098e1 | 1389 | status ^= BD_ENET_RX_LAST; |
22f6b860 | 1390 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
095098e1 TK |
1391 | BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | |
1392 | BD_ENET_RX_CL)) { | |
c556167f | 1393 | ndev->stats.rx_errors++; |
095098e1 TK |
1394 | if (status & BD_ENET_RX_OV) { |
1395 | /* FIFO overrun */ | |
1396 | ndev->stats.rx_fifo_errors++; | |
1397 | goto rx_processing_done; | |
1398 | } | |
1399 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | |
1400 | | BD_ENET_RX_LAST)) { | |
22f6b860 | 1401 | /* Frame too long or too short. */ |
c556167f | 1402 | ndev->stats.rx_length_errors++; |
095098e1 TK |
1403 | if (status & BD_ENET_RX_LAST) |
1404 | netdev_err(ndev, "rcv is not +last\n"); | |
22f6b860 | 1405 | } |
22f6b860 | 1406 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 1407 | ndev->stats.rx_crc_errors++; |
095098e1 TK |
1408 | /* Report late collisions as a frame error. */ |
1409 | if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) | |
1410 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
1411 | goto rx_processing_done; |
1412 | } | |
1da177e4 | 1413 | |
22f6b860 | 1414 | /* Process the incoming frame. */ |
c556167f | 1415 | ndev->stats.rx_packets++; |
5cfa3039 | 1416 | pkt_len = fec16_to_cpu(bdp->cbd_datlen); |
c556167f | 1417 | ndev->stats.rx_bytes += pkt_len; |
1da177e4 | 1418 | |
7355f276 | 1419 | index = fec_enet_get_bd_index(bdp, &rxq->bd); |
1b7bde6d | 1420 | skb = rxq->rx_skbuff[index]; |
ccdc4f19 | 1421 | |
1b7bde6d NA |
1422 | /* The packet length includes FCS, but we don't want to |
1423 | * include that when passing upstream as it messes up | |
1424 | * bridging applications. | |
1425 | */ | |
1310b544 LW |
1426 | is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, |
1427 | need_swap); | |
1b7bde6d NA |
1428 | if (!is_copybreak) { |
1429 | skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); | |
1430 | if (unlikely(!skb_new)) { | |
1431 | ndev->stats.rx_dropped++; | |
1432 | goto rx_processing_done; | |
1433 | } | |
5cfa3039 JB |
1434 | dma_unmap_single(&fep->pdev->dev, |
1435 | fec32_to_cpu(bdp->cbd_bufaddr), | |
1b7bde6d NA |
1436 | FEC_ENET_RX_FRSIZE - fep->rx_align, |
1437 | DMA_FROM_DEVICE); | |
1438 | } | |
1439 | ||
1440 | prefetch(skb->data - NET_IP_ALIGN); | |
1441 | skb_put(skb, pkt_len - 4); | |
1442 | data = skb->data; | |
3ac72b7b | 1443 | |
235bde1e FE |
1444 | if (!is_copybreak && need_swap) |
1445 | swap_buffer(data, pkt_len); | |
1446 | ||
3ac72b7b EN |
1447 | #if !defined(CONFIG_M5272) |
1448 | if (fep->quirks & FEC_QUIRK_HAS_RACC) | |
1449 | data = skb_pull_inline(skb, 2); | |
1450 | #endif | |
1451 | ||
cdffcf1b JB |
1452 | /* Extract the enhanced buffer descriptor */ |
1453 | ebdp = NULL; | |
1454 | if (fep->bufdesc_ex) | |
1455 | ebdp = (struct bufdesc_ex *)bdp; | |
1456 | ||
1457 | /* If this is a VLAN packet remove the VLAN Tag */ | |
1458 | vlan_packet_rcvd = false; | |
1459 | if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
5cfa3039 JB |
1460 | fep->bufdesc_ex && |
1461 | (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { | |
cdffcf1b JB |
1462 | /* Push and remove the vlan tag */ |
1463 | struct vlan_hdr *vlan_header = | |
1464 | (struct vlan_hdr *) (data + ETH_HLEN); | |
1465 | vlan_tag = ntohs(vlan_header->h_vlan_TCI); | |
cdffcf1b JB |
1466 | |
1467 | vlan_packet_rcvd = true; | |
1b7bde6d | 1468 | |
af5cbc98 | 1469 | memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); |
1b7bde6d | 1470 | skb_pull(skb, VLAN_HLEN); |
cdffcf1b JB |
1471 | } |
1472 | ||
1b7bde6d | 1473 | skb->protocol = eth_type_trans(skb, ndev); |
1da177e4 | 1474 | |
1b7bde6d NA |
1475 | /* Get receive timestamp from the skb */ |
1476 | if (fep->hwts_rx_en && fep->bufdesc_ex) | |
5cfa3039 | 1477 | fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), |
1b7bde6d NA |
1478 | skb_hwtstamps(skb)); |
1479 | ||
1480 | if (fep->bufdesc_ex && | |
1481 | (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { | |
5cfa3039 | 1482 | if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { |
1b7bde6d NA |
1483 | /* don't check it */ |
1484 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1485 | } else { | |
1486 | skb_checksum_none_assert(skb); | |
4c09eed9 | 1487 | } |
1b7bde6d | 1488 | } |
4c09eed9 | 1489 | |
1b7bde6d NA |
1490 | /* Handle received VLAN packets */ |
1491 | if (vlan_packet_rcvd) | |
1492 | __vlan_hwaccel_put_tag(skb, | |
1493 | htons(ETH_P_8021Q), | |
1494 | vlan_tag); | |
cdffcf1b | 1495 | |
1b7bde6d NA |
1496 | napi_gro_receive(&fep->napi, skb); |
1497 | ||
1498 | if (is_copybreak) { | |
5cfa3039 JB |
1499 | dma_sync_single_for_device(&fep->pdev->dev, |
1500 | fec32_to_cpu(bdp->cbd_bufaddr), | |
1b7bde6d NA |
1501 | FEC_ENET_RX_FRSIZE - fep->rx_align, |
1502 | DMA_FROM_DEVICE); | |
1503 | } else { | |
1504 | rxq->rx_skbuff[index] = skb_new; | |
1505 | fec_enet_new_rxbdp(ndev, bdp, skb_new); | |
22f6b860 | 1506 | } |
f0b3fbea | 1507 | |
22f6b860 SH |
1508 | rx_processing_done: |
1509 | /* Clear the status flags for this buffer */ | |
1510 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 1511 | |
22f6b860 SH |
1512 | /* Mark the buffer empty */ |
1513 | status |= BD_ENET_RX_EMPTY; | |
6aa20a22 | 1514 | |
ff43da86 FL |
1515 | if (fep->bufdesc_ex) { |
1516 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1517 | ||
5cfa3039 | 1518 | ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); |
ff43da86 FL |
1519 | ebdp->cbd_prot = 0; |
1520 | ebdp->cbd_bdu = 0; | |
1521 | } | |
be293467 TK |
1522 | /* Make sure the updates to rest of the descriptor are |
1523 | * performed before transferring ownership. | |
1524 | */ | |
1525 | wmb(); | |
1526 | bdp->cbd_sc = cpu_to_fec16(status); | |
6605b730 | 1527 | |
22f6b860 | 1528 | /* Update BD pointer to next entry */ |
7355f276 | 1529 | bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); |
36e24e2e | 1530 | |
22f6b860 SH |
1531 | /* Doing this here will keep the FEC running while we process |
1532 | * incoming frames. On a heavily loaded network, we should be | |
1533 | * able to keep up at the expense of system resources. | |
1534 | */ | |
53bb20d1 | 1535 | writel(0, rxq->bd.reg_desc_active); |
22f6b860 | 1536 | } |
7355f276 | 1537 | rxq->bd.cur = bdp; |
4d494cdc FD |
1538 | return pkt_received; |
1539 | } | |
1da177e4 | 1540 | |
4d494cdc FD |
1541 | static int |
1542 | fec_enet_rx(struct net_device *ndev, int budget) | |
1543 | { | |
1544 | int pkt_received = 0; | |
1545 | u16 queue_id; | |
1546 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1547 | ||
1548 | for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { | |
1c021bb7 UKK |
1549 | int ret; |
1550 | ||
1551 | ret = fec_enet_rx_queue(ndev, | |
4d494cdc | 1552 | budget - pkt_received, queue_id); |
1c021bb7 UKK |
1553 | |
1554 | if (ret < budget - pkt_received) | |
1555 | clear_bit(queue_id, &fep->work_rx); | |
1556 | ||
1557 | pkt_received += ret; | |
4d494cdc | 1558 | } |
dc975382 | 1559 | return pkt_received; |
1da177e4 LT |
1560 | } |
1561 | ||
4d494cdc FD |
1562 | static bool |
1563 | fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) | |
1564 | { | |
1565 | if (int_events == 0) | |
1566 | return false; | |
1567 | ||
5e62d98c | 1568 | if (int_events & FEC_ENET_RXF_0) |
4d494cdc | 1569 | fep->work_rx |= (1 << 2); |
ce99d0d3 FL |
1570 | if (int_events & FEC_ENET_RXF_1) |
1571 | fep->work_rx |= (1 << 0); | |
1572 | if (int_events & FEC_ENET_RXF_2) | |
1573 | fep->work_rx |= (1 << 1); | |
4d494cdc | 1574 | |
5e62d98c | 1575 | if (int_events & FEC_ENET_TXF_0) |
4d494cdc | 1576 | fep->work_tx |= (1 << 2); |
ce99d0d3 FL |
1577 | if (int_events & FEC_ENET_TXF_1) |
1578 | fep->work_tx |= (1 << 0); | |
1579 | if (int_events & FEC_ENET_TXF_2) | |
1580 | fep->work_tx |= (1 << 1); | |
4d494cdc FD |
1581 | |
1582 | return true; | |
1583 | } | |
1584 | ||
45993653 UKK |
1585 | static irqreturn_t |
1586 | fec_enet_interrupt(int irq, void *dev_id) | |
1587 | { | |
1588 | struct net_device *ndev = dev_id; | |
1589 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1590 | uint int_events; | |
1591 | irqreturn_t ret = IRQ_NONE; | |
1592 | ||
7a16807c | 1593 | int_events = readl(fep->hwp + FEC_IEVENT); |
94191fd6 | 1594 | writel(int_events, fep->hwp + FEC_IEVENT); |
4d494cdc | 1595 | fec_enet_collect_events(fep, int_events); |
45993653 | 1596 | |
61615cd2 | 1597 | if ((fep->work_tx || fep->work_rx) && fep->link) { |
7a16807c | 1598 | ret = IRQ_HANDLED; |
dc975382 | 1599 | |
94191fd6 NA |
1600 | if (napi_schedule_prep(&fep->napi)) { |
1601 | /* Disable the NAPI interrupts */ | |
80dc6a9f | 1602 | writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); |
94191fd6 NA |
1603 | __napi_schedule(&fep->napi); |
1604 | } | |
7a16807c | 1605 | } |
45993653 | 1606 | |
7a16807c RK |
1607 | if (int_events & FEC_ENET_MII) { |
1608 | ret = IRQ_HANDLED; | |
1609 | complete(&fep->mdio_done); | |
1610 | } | |
45993653 UKK |
1611 | return ret; |
1612 | } | |
1613 | ||
dc975382 FL |
1614 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
1615 | { | |
1616 | struct net_device *ndev = napi->dev; | |
dc975382 | 1617 | struct fec_enet_private *fep = netdev_priv(ndev); |
7a16807c RK |
1618 | int pkts; |
1619 | ||
7a16807c | 1620 | pkts = fec_enet_rx(ndev, budget); |
45993653 | 1621 | |
de5fb0a0 FL |
1622 | fec_enet_tx(ndev); |
1623 | ||
dc975382 | 1624 | if (pkts < budget) { |
6ad20165 | 1625 | napi_complete_done(napi, pkts); |
dc975382 FL |
1626 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); |
1627 | } | |
1628 | return pkts; | |
1629 | } | |
45993653 | 1630 | |
e6b043d5 | 1631 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 1632 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 1633 | { |
c556167f | 1634 | struct fec_enet_private *fep = netdev_priv(ndev); |
94660ba0 | 1635 | struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); |
e6b043d5 | 1636 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 1637 | |
49da97dc SG |
1638 | /* |
1639 | * try to get mac address in following order: | |
1640 | * | |
1641 | * 1) module parameter via kernel command line in form | |
1642 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
1643 | */ | |
1644 | iap = macaddr; | |
1645 | ||
ca2cc333 SG |
1646 | /* |
1647 | * 2) from device tree data | |
1648 | */ | |
1649 | if (!is_valid_ether_addr(iap)) { | |
1650 | struct device_node *np = fep->pdev->dev.of_node; | |
1651 | if (np) { | |
1652 | const char *mac = of_get_mac_address(np); | |
1653 | if (mac) | |
1654 | iap = (unsigned char *) mac; | |
1655 | } | |
1656 | } | |
ca2cc333 | 1657 | |
49da97dc | 1658 | /* |
ca2cc333 | 1659 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
1660 | */ |
1661 | if (!is_valid_ether_addr(iap)) { | |
1662 | #ifdef CONFIG_M5272 | |
1663 | if (FEC_FLASHMAC) | |
1664 | iap = (unsigned char *)FEC_FLASHMAC; | |
1665 | #else | |
1666 | if (pdata) | |
589efdc7 | 1667 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
1668 | #endif |
1669 | } | |
1670 | ||
1671 | /* | |
ca2cc333 | 1672 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
1673 | */ |
1674 | if (!is_valid_ether_addr(iap)) { | |
7d7628f3 DC |
1675 | *((__be32 *) &tmpaddr[0]) = |
1676 | cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); | |
1677 | *((__be16 *) &tmpaddr[4]) = | |
1678 | cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 1679 | iap = &tmpaddr[0]; |
1da177e4 LT |
1680 | } |
1681 | ||
ff5b2fab LS |
1682 | /* |
1683 | * 5) random mac address | |
1684 | */ | |
1685 | if (!is_valid_ether_addr(iap)) { | |
1686 | /* Report it and use a random ethernet address instead */ | |
1687 | netdev_err(ndev, "Invalid MAC address: %pM\n", iap); | |
1688 | eth_hw_addr_random(ndev); | |
1689 | netdev_info(ndev, "Using random MAC address: %pM\n", | |
1690 | ndev->dev_addr); | |
1691 | return; | |
1692 | } | |
1693 | ||
c556167f | 1694 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 1695 | |
49da97dc SG |
1696 | /* Adjust MAC if using macaddr */ |
1697 | if (iap == macaddr) | |
43af940c | 1698 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
1699 | } |
1700 | ||
e6b043d5 | 1701 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 1702 | |
e6b043d5 BW |
1703 | /* |
1704 | * Phy section | |
1705 | */ | |
c556167f | 1706 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 1707 | { |
c556167f | 1708 | struct fec_enet_private *fep = netdev_priv(ndev); |
45f5c327 | 1709 | struct phy_device *phy_dev = ndev->phydev; |
e6b043d5 | 1710 | int status_change = 0; |
1da177e4 | 1711 | |
e6b043d5 BW |
1712 | /* Prevent a state halted on mii error */ |
1713 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
1714 | phy_dev->state = PHY_RESUMING; | |
54309fa6 | 1715 | return; |
e6b043d5 | 1716 | } |
1da177e4 | 1717 | |
8ce5624f RK |
1718 | /* |
1719 | * If the netdev is down, or is going down, we're not interested | |
1720 | * in link state events, so just mark our idea of the link as down | |
1721 | * and ignore the event. | |
1722 | */ | |
1723 | if (!netif_running(ndev) || !netif_device_present(ndev)) { | |
1724 | fep->link = 0; | |
1725 | } else if (phy_dev->link) { | |
d97e7497 | 1726 | if (!fep->link) { |
6ea0722f | 1727 | fep->link = phy_dev->link; |
e6b043d5 BW |
1728 | status_change = 1; |
1729 | } | |
1da177e4 | 1730 | |
ef83337d RK |
1731 | if (fep->full_duplex != phy_dev->duplex) { |
1732 | fep->full_duplex = phy_dev->duplex; | |
d97e7497 | 1733 | status_change = 1; |
ef83337d | 1734 | } |
d97e7497 LS |
1735 | |
1736 | if (phy_dev->speed != fep->speed) { | |
1737 | fep->speed = phy_dev->speed; | |
1738 | status_change = 1; | |
1739 | } | |
1740 | ||
1741 | /* if any of the above changed restart the FEC */ | |
dbc64a8e | 1742 | if (status_change) { |
dbc64a8e | 1743 | napi_disable(&fep->napi); |
dbc64a8e | 1744 | netif_tx_lock_bh(ndev); |
ef83337d | 1745 | fec_restart(ndev); |
dbc64a8e | 1746 | netif_wake_queue(ndev); |
6af42d42 | 1747 | netif_tx_unlock_bh(ndev); |
dbc64a8e | 1748 | napi_enable(&fep->napi); |
dbc64a8e | 1749 | } |
d97e7497 LS |
1750 | } else { |
1751 | if (fep->link) { | |
f208ce10 RK |
1752 | napi_disable(&fep->napi); |
1753 | netif_tx_lock_bh(ndev); | |
c556167f | 1754 | fec_stop(ndev); |
f208ce10 RK |
1755 | netif_tx_unlock_bh(ndev); |
1756 | napi_enable(&fep->napi); | |
8d7ed0f0 | 1757 | fep->link = phy_dev->link; |
d97e7497 LS |
1758 | status_change = 1; |
1759 | } | |
1da177e4 | 1760 | } |
6aa20a22 | 1761 | |
e6b043d5 BW |
1762 | if (status_change) |
1763 | phy_print_status(phy_dev); | |
1764 | } | |
1da177e4 | 1765 | |
e6b043d5 | 1766 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 1767 | { |
e6b043d5 | 1768 | struct fec_enet_private *fep = bus->priv; |
8fff755e | 1769 | struct device *dev = &fep->pdev->dev; |
97b72e43 | 1770 | unsigned long time_left; |
8fff755e AL |
1771 | int ret = 0; |
1772 | ||
1773 | ret = pm_runtime_get_sync(dev); | |
b0c6ce24 | 1774 | if (ret < 0) |
8fff755e | 1775 | return ret; |
1da177e4 | 1776 | |
e6b043d5 | 1777 | fep->mii_timeout = 0; |
aac27c7a | 1778 | reinit_completion(&fep->mdio_done); |
e6b043d5 BW |
1779 | |
1780 | /* start a read op */ | |
1781 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
1782 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
1783 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
1784 | ||
1785 | /* wait for end of transfer */ | |
97b72e43 BS |
1786 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1787 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1788 | if (time_left == 0) { | |
1789 | fep->mii_timeout = 1; | |
31b7720c | 1790 | netdev_err(fep->netdev, "MDIO read timeout\n"); |
8fff755e AL |
1791 | ret = -ETIMEDOUT; |
1792 | goto out; | |
1da177e4 | 1793 | } |
1da177e4 | 1794 | |
8fff755e AL |
1795 | ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); |
1796 | ||
1797 | out: | |
1798 | pm_runtime_mark_last_busy(dev); | |
1799 | pm_runtime_put_autosuspend(dev); | |
1800 | ||
1801 | return ret; | |
7dd6a2aa | 1802 | } |
6aa20a22 | 1803 | |
e6b043d5 BW |
1804 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
1805 | u16 value) | |
1da177e4 | 1806 | { |
e6b043d5 | 1807 | struct fec_enet_private *fep = bus->priv; |
8fff755e | 1808 | struct device *dev = &fep->pdev->dev; |
97b72e43 | 1809 | unsigned long time_left; |
42ea4457 | 1810 | int ret; |
8fff755e AL |
1811 | |
1812 | ret = pm_runtime_get_sync(dev); | |
b0c6ce24 | 1813 | if (ret < 0) |
8fff755e | 1814 | return ret; |
42ea4457 MS |
1815 | else |
1816 | ret = 0; | |
1da177e4 | 1817 | |
e6b043d5 | 1818 | fep->mii_timeout = 0; |
aac27c7a | 1819 | reinit_completion(&fep->mdio_done); |
1da177e4 | 1820 | |
862f0982 SG |
1821 | /* start a write op */ |
1822 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1823 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1824 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1825 | fep->hwp + FEC_MII_DATA); | |
1826 | ||
1827 | /* wait for end of transfer */ | |
97b72e43 BS |
1828 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1829 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1830 | if (time_left == 0) { | |
1831 | fep->mii_timeout = 1; | |
31b7720c | 1832 | netdev_err(fep->netdev, "MDIO write timeout\n"); |
8fff755e | 1833 | ret = -ETIMEDOUT; |
e6b043d5 | 1834 | } |
1da177e4 | 1835 | |
8fff755e AL |
1836 | pm_runtime_mark_last_busy(dev); |
1837 | pm_runtime_put_autosuspend(dev); | |
1838 | ||
1839 | return ret; | |
e6b043d5 | 1840 | } |
1da177e4 | 1841 | |
e8fcfcd5 NA |
1842 | static int fec_enet_clk_enable(struct net_device *ndev, bool enable) |
1843 | { | |
1844 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1845 | int ret; | |
1846 | ||
1847 | if (enable) { | |
1848 | ret = clk_prepare_enable(fep->clk_ahb); | |
1849 | if (ret) | |
1850 | return ret; | |
01e5943a UKK |
1851 | |
1852 | ret = clk_prepare_enable(fep->clk_enet_out); | |
1853 | if (ret) | |
1854 | goto failed_clk_enet_out; | |
1855 | ||
e8fcfcd5 | 1856 | if (fep->clk_ptp) { |
91c0d987 | 1857 | mutex_lock(&fep->ptp_clk_mutex); |
e8fcfcd5 | 1858 | ret = clk_prepare_enable(fep->clk_ptp); |
91c0d987 NA |
1859 | if (ret) { |
1860 | mutex_unlock(&fep->ptp_clk_mutex); | |
e8fcfcd5 | 1861 | goto failed_clk_ptp; |
91c0d987 NA |
1862 | } else { |
1863 | fep->ptp_clk_on = true; | |
1864 | } | |
1865 | mutex_unlock(&fep->ptp_clk_mutex); | |
e8fcfcd5 | 1866 | } |
01e5943a UKK |
1867 | |
1868 | ret = clk_prepare_enable(fep->clk_ref); | |
1869 | if (ret) | |
1870 | goto failed_clk_ref; | |
e8fcfcd5 NA |
1871 | } else { |
1872 | clk_disable_unprepare(fep->clk_ahb); | |
01e5943a | 1873 | clk_disable_unprepare(fep->clk_enet_out); |
91c0d987 NA |
1874 | if (fep->clk_ptp) { |
1875 | mutex_lock(&fep->ptp_clk_mutex); | |
e8fcfcd5 | 1876 | clk_disable_unprepare(fep->clk_ptp); |
91c0d987 NA |
1877 | fep->ptp_clk_on = false; |
1878 | mutex_unlock(&fep->ptp_clk_mutex); | |
1879 | } | |
01e5943a | 1880 | clk_disable_unprepare(fep->clk_ref); |
e8fcfcd5 NA |
1881 | } |
1882 | ||
1883 | return 0; | |
9b5330ed FD |
1884 | |
1885 | failed_clk_ref: | |
1886 | if (fep->clk_ref) | |
1887 | clk_disable_unprepare(fep->clk_ref); | |
e8fcfcd5 NA |
1888 | failed_clk_ptp: |
1889 | if (fep->clk_enet_out) | |
1890 | clk_disable_unprepare(fep->clk_enet_out); | |
1891 | failed_clk_enet_out: | |
e8fcfcd5 NA |
1892 | clk_disable_unprepare(fep->clk_ahb); |
1893 | ||
1894 | return ret; | |
1895 | } | |
1896 | ||
c556167f | 1897 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1898 | { |
c556167f | 1899 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1900 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1901 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1902 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1903 | int phy_id; | |
43af940c | 1904 | int dev_id = fep->dev_id; |
562d2f8c | 1905 | |
407066f8 UKK |
1906 | if (fep->phy_node) { |
1907 | phy_dev = of_phy_connect(ndev, fep->phy_node, | |
1908 | &fec_enet_adjust_link, 0, | |
1909 | fep->phy_interface); | |
9558df3a AL |
1910 | if (!phy_dev) { |
1911 | netdev_err(ndev, "Unable to connect to phy\n"); | |
213a9922 | 1912 | return -ENODEV; |
9558df3a | 1913 | } |
407066f8 UKK |
1914 | } else { |
1915 | /* check for attached phy */ | |
1916 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
7f854420 | 1917 | if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) |
407066f8 UKK |
1918 | continue; |
1919 | if (dev_id--) | |
1920 | continue; | |
949bdd20 | 1921 | strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
407066f8 UKK |
1922 | break; |
1923 | } | |
1da177e4 | 1924 | |
407066f8 UKK |
1925 | if (phy_id >= PHY_MAX_ADDR) { |
1926 | netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); | |
949bdd20 | 1927 | strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
407066f8 UKK |
1928 | phy_id = 0; |
1929 | } | |
1930 | ||
1931 | snprintf(phy_name, sizeof(phy_name), | |
1932 | PHY_ID_FMT, mdio_bus_id, phy_id); | |
1933 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, | |
1934 | fep->phy_interface); | |
6fcc040f GU |
1935 | } |
1936 | ||
6fcc040f | 1937 | if (IS_ERR(phy_dev)) { |
31b7720c | 1938 | netdev_err(ndev, "could not attach to PHY\n"); |
6fcc040f | 1939 | return PTR_ERR(phy_dev); |
e6b043d5 | 1940 | } |
1da177e4 | 1941 | |
e6b043d5 | 1942 | /* mask with MAC supported features */ |
6b7e4008 | 1943 | if (fep->quirks & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1944 | phy_dev->supported &= PHY_GBIT_FEATURES; |
b44592ff | 1945 | phy_dev->supported &= ~SUPPORTED_1000baseT_Half; |
d1391930 | 1946 | #if !defined(CONFIG_M5272) |
baa70a5c | 1947 | phy_dev->supported |= SUPPORTED_Pause; |
d1391930 | 1948 | #endif |
baa70a5c | 1949 | } |
230dec61 SG |
1950 | else |
1951 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1952 | ||
e6b043d5 | 1953 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1954 | |
e6b043d5 BW |
1955 | fep->link = 0; |
1956 | fep->full_duplex = 0; | |
1da177e4 | 1957 | |
2220943a | 1958 | phy_attached_info(phy_dev); |
418bd0d4 | 1959 | |
e6b043d5 | 1960 | return 0; |
1da177e4 LT |
1961 | } |
1962 | ||
e6b043d5 | 1963 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1964 | { |
b5680e0b | 1965 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1966 | struct net_device *ndev = platform_get_drvdata(pdev); |
1967 | struct fec_enet_private *fep = netdev_priv(ndev); | |
407066f8 | 1968 | struct device_node *node; |
e7f4dc35 | 1969 | int err = -ENXIO; |
63c60732 | 1970 | u32 mii_speed, holdtime; |
6b265293 | 1971 | |
b5680e0b | 1972 | /* |
3d125f9c | 1973 | * The i.MX28 dual fec interfaces are not equal. |
b5680e0b SG |
1974 | * Here are the differences: |
1975 | * | |
1976 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1977 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1978 | * - external phys can only be configured by fec0 | |
1979 | * | |
1980 | * That is to say fec1 can not work independently. It only works | |
1981 | * when fec0 is working. The reason behind this design is that the | |
1982 | * second interface is added primarily for Switch mode. | |
1983 | * | |
1984 | * Because of the last point above, both phys are attached on fec0 | |
1985 | * mdio interface in board design, and need to be configured by | |
1986 | * fec0 mii_bus. | |
1987 | */ | |
3d125f9c | 1988 | if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { |
b5680e0b | 1989 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1990 | if (mii_cnt && fec0_mii_bus) { |
1991 | fep->mii_bus = fec0_mii_bus; | |
1992 | mii_cnt++; | |
1993 | return 0; | |
1994 | } | |
1995 | return -ENOENT; | |
b5680e0b SG |
1996 | } |
1997 | ||
e6b043d5 | 1998 | fep->mii_timeout = 0; |
1da177e4 | 1999 | |
e6b043d5 BW |
2000 | /* |
2001 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
2002 | * |
2003 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
2004 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
2005 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
2006 | * document. | |
e6b043d5 | 2007 | */ |
63c60732 | 2008 | mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); |
6b7e4008 | 2009 | if (fep->quirks & FEC_QUIRK_ENET_MAC) |
63c60732 UKK |
2010 | mii_speed--; |
2011 | if (mii_speed > 63) { | |
2012 | dev_err(&pdev->dev, | |
981a0547 | 2013 | "fec clock (%lu) too fast to get right mii speed\n", |
63c60732 UKK |
2014 | clk_get_rate(fep->clk_ipg)); |
2015 | err = -EINVAL; | |
2016 | goto err_out; | |
2017 | } | |
2018 | ||
2019 | /* | |
2020 | * The i.MX28 and i.MX6 types have another filed in the MSCR (aka | |
2021 | * MII_SPEED) register that defines the MDIO output hold time. Earlier | |
2022 | * versions are RAZ there, so just ignore the difference and write the | |
2023 | * register always. | |
2024 | * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. | |
2025 | * HOLDTIME + 1 is the number of clk cycles the fec is holding the | |
2026 | * output. | |
2027 | * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). | |
2028 | * Given that ceil(clkrate / 5000000) <= 64, the calculation for | |
2029 | * holdtime cannot result in a value greater than 3. | |
2030 | */ | |
2031 | holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; | |
2032 | ||
2033 | fep->phy_speed = mii_speed << 1 | holdtime << 8; | |
2034 | ||
e6b043d5 | 2035 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 2036 | |
e6b043d5 BW |
2037 | fep->mii_bus = mdiobus_alloc(); |
2038 | if (fep->mii_bus == NULL) { | |
2039 | err = -ENOMEM; | |
2040 | goto err_out; | |
1da177e4 LT |
2041 | } |
2042 | ||
e6b043d5 BW |
2043 | fep->mii_bus->name = "fec_enet_mii_bus"; |
2044 | fep->mii_bus->read = fec_enet_mdio_read; | |
2045 | fep->mii_bus->write = fec_enet_mdio_write; | |
391420f7 FF |
2046 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
2047 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
2048 | fep->mii_bus->priv = fep; |
2049 | fep->mii_bus->parent = &pdev->dev; | |
2050 | ||
407066f8 UKK |
2051 | node = of_get_child_by_name(pdev->dev.of_node, "mdio"); |
2052 | if (node) { | |
2053 | err = of_mdiobus_register(fep->mii_bus, node); | |
2054 | of_node_put(node); | |
2055 | } else { | |
2056 | err = mdiobus_register(fep->mii_bus); | |
2057 | } | |
2058 | ||
2059 | if (err) | |
e7f4dc35 | 2060 | goto err_out_free_mdiobus; |
1da177e4 | 2061 | |
e163cc97 LW |
2062 | mii_cnt++; |
2063 | ||
b5680e0b | 2064 | /* save fec0 mii_bus */ |
3d125f9c | 2065 | if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) |
b5680e0b SG |
2066 | fec0_mii_bus = fep->mii_bus; |
2067 | ||
e6b043d5 | 2068 | return 0; |
1da177e4 | 2069 | |
e6b043d5 BW |
2070 | err_out_free_mdiobus: |
2071 | mdiobus_free(fep->mii_bus); | |
2072 | err_out: | |
2073 | return err; | |
1da177e4 LT |
2074 | } |
2075 | ||
e6b043d5 | 2076 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 2077 | { |
e163cc97 LW |
2078 | if (--mii_cnt == 0) { |
2079 | mdiobus_unregister(fep->mii_bus); | |
e163cc97 LW |
2080 | mdiobus_free(fep->mii_bus); |
2081 | } | |
1da177e4 LT |
2082 | } |
2083 | ||
c556167f | 2084 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 2085 | struct ethtool_drvinfo *info) |
1da177e4 | 2086 | { |
c556167f | 2087 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 2088 | |
7826d43f JP |
2089 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
2090 | sizeof(info->driver)); | |
2091 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
2092 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
2093 | } |
2094 | ||
db65f35f PR |
2095 | static int fec_enet_get_regs_len(struct net_device *ndev) |
2096 | { | |
2097 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2098 | struct resource *r; | |
2099 | int s = 0; | |
2100 | ||
2101 | r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); | |
2102 | if (r) | |
2103 | s = resource_size(r); | |
2104 | ||
2105 | return s; | |
2106 | } | |
2107 | ||
2108 | /* List of registers that can be safety be read to dump them with ethtool */ | |
2109 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ | |
05f3b50e | 2110 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
db65f35f PR |
2111 | static u32 fec_enet_register_offset[] = { |
2112 | FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, | |
2113 | FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, | |
2114 | FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, | |
2115 | FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, | |
2116 | FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, | |
2117 | FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, | |
2118 | FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, | |
2119 | FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, | |
2120 | FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, | |
2121 | FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, | |
2122 | FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, | |
2123 | FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, | |
2124 | RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, | |
2125 | RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, | |
2126 | RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, | |
2127 | RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, | |
2128 | RMON_T_P_GTE2048, RMON_T_OCTETS, | |
2129 | IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, | |
2130 | IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, | |
2131 | IEEE_T_FDXFC, IEEE_T_OCTETS_OK, | |
2132 | RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, | |
2133 | RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, | |
2134 | RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, | |
2135 | RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, | |
2136 | RMON_R_P_GTE2048, RMON_R_OCTETS, | |
2137 | IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, | |
2138 | IEEE_R_FDXFC, IEEE_R_OCTETS_OK | |
2139 | }; | |
2140 | #else | |
2141 | static u32 fec_enet_register_offset[] = { | |
2142 | FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, | |
2143 | FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, | |
2144 | FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, | |
2145 | FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, | |
2146 | FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, | |
2147 | FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, | |
2148 | FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, | |
2149 | FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, | |
2150 | FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 | |
2151 | }; | |
2152 | #endif | |
2153 | ||
2154 | static void fec_enet_get_regs(struct net_device *ndev, | |
2155 | struct ethtool_regs *regs, void *regbuf) | |
2156 | { | |
2157 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2158 | u32 __iomem *theregs = (u32 __iomem *)fep->hwp; | |
2159 | u32 *buf = (u32 *)regbuf; | |
2160 | u32 i, off; | |
2161 | ||
2162 | memset(buf, 0, regs->len); | |
2163 | ||
2164 | for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { | |
2165 | off = fec_enet_register_offset[i] / 4; | |
2166 | buf[off] = readl(&theregs[off]); | |
2167 | } | |
2168 | } | |
2169 | ||
5ebae489 FL |
2170 | static int fec_enet_get_ts_info(struct net_device *ndev, |
2171 | struct ethtool_ts_info *info) | |
2172 | { | |
2173 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2174 | ||
2175 | if (fep->bufdesc_ex) { | |
2176 | ||
2177 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
2178 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
2179 | SOF_TIMESTAMPING_SOFTWARE | | |
2180 | SOF_TIMESTAMPING_TX_HARDWARE | | |
2181 | SOF_TIMESTAMPING_RX_HARDWARE | | |
2182 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
2183 | if (fep->ptp_clock) | |
2184 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
2185 | else | |
2186 | info->phc_index = -1; | |
2187 | ||
2188 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
2189 | (1 << HWTSTAMP_TX_ON); | |
2190 | ||
2191 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
2192 | (1 << HWTSTAMP_FILTER_ALL); | |
2193 | return 0; | |
2194 | } else { | |
2195 | return ethtool_op_get_ts_info(ndev, info); | |
2196 | } | |
2197 | } | |
2198 | ||
d1391930 GR |
2199 | #if !defined(CONFIG_M5272) |
2200 | ||
baa70a5c FL |
2201 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
2202 | struct ethtool_pauseparam *pause) | |
2203 | { | |
2204 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2205 | ||
2206 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
2207 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
2208 | pause->rx_pause = pause->tx_pause; | |
2209 | } | |
2210 | ||
2211 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
2212 | struct ethtool_pauseparam *pause) | |
2213 | { | |
2214 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2215 | ||
45f5c327 | 2216 | if (!ndev->phydev) |
0b146ca8 RK |
2217 | return -ENODEV; |
2218 | ||
baa70a5c FL |
2219 | if (pause->tx_pause != pause->rx_pause) { |
2220 | netdev_info(ndev, | |
2221 | "hardware only support enable/disable both tx and rx"); | |
2222 | return -EINVAL; | |
2223 | } | |
2224 | ||
2225 | fep->pause_flag = 0; | |
2226 | ||
2227 | /* tx pause must be same as rx pause */ | |
2228 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
2229 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
2230 | ||
2231 | if (pause->rx_pause || pause->autoneg) { | |
45f5c327 PR |
2232 | ndev->phydev->supported |= ADVERTISED_Pause; |
2233 | ndev->phydev->advertising |= ADVERTISED_Pause; | |
baa70a5c | 2234 | } else { |
45f5c327 PR |
2235 | ndev->phydev->supported &= ~ADVERTISED_Pause; |
2236 | ndev->phydev->advertising &= ~ADVERTISED_Pause; | |
baa70a5c FL |
2237 | } |
2238 | ||
2239 | if (pause->autoneg) { | |
2240 | if (netif_running(ndev)) | |
2241 | fec_stop(ndev); | |
45f5c327 | 2242 | phy_start_aneg(ndev->phydev); |
baa70a5c | 2243 | } |
dbc64a8e | 2244 | if (netif_running(ndev)) { |
dbc64a8e | 2245 | napi_disable(&fep->napi); |
dbc64a8e | 2246 | netif_tx_lock_bh(ndev); |
ef83337d | 2247 | fec_restart(ndev); |
dbc64a8e | 2248 | netif_wake_queue(ndev); |
6af42d42 | 2249 | netif_tx_unlock_bh(ndev); |
dbc64a8e | 2250 | napi_enable(&fep->napi); |
dbc64a8e | 2251 | } |
baa70a5c FL |
2252 | |
2253 | return 0; | |
2254 | } | |
2255 | ||
38ae92dc CH |
2256 | static const struct fec_stat { |
2257 | char name[ETH_GSTRING_LEN]; | |
2258 | u16 offset; | |
2259 | } fec_stats[] = { | |
2260 | /* RMON TX */ | |
2261 | { "tx_dropped", RMON_T_DROP }, | |
2262 | { "tx_packets", RMON_T_PACKETS }, | |
2263 | { "tx_broadcast", RMON_T_BC_PKT }, | |
2264 | { "tx_multicast", RMON_T_MC_PKT }, | |
2265 | { "tx_crc_errors", RMON_T_CRC_ALIGN }, | |
2266 | { "tx_undersize", RMON_T_UNDERSIZE }, | |
2267 | { "tx_oversize", RMON_T_OVERSIZE }, | |
2268 | { "tx_fragment", RMON_T_FRAG }, | |
2269 | { "tx_jabber", RMON_T_JAB }, | |
2270 | { "tx_collision", RMON_T_COL }, | |
2271 | { "tx_64byte", RMON_T_P64 }, | |
2272 | { "tx_65to127byte", RMON_T_P65TO127 }, | |
2273 | { "tx_128to255byte", RMON_T_P128TO255 }, | |
2274 | { "tx_256to511byte", RMON_T_P256TO511 }, | |
2275 | { "tx_512to1023byte", RMON_T_P512TO1023 }, | |
2276 | { "tx_1024to2047byte", RMON_T_P1024TO2047 }, | |
2277 | { "tx_GTE2048byte", RMON_T_P_GTE2048 }, | |
2278 | { "tx_octets", RMON_T_OCTETS }, | |
2279 | ||
2280 | /* IEEE TX */ | |
2281 | { "IEEE_tx_drop", IEEE_T_DROP }, | |
2282 | { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, | |
2283 | { "IEEE_tx_1col", IEEE_T_1COL }, | |
2284 | { "IEEE_tx_mcol", IEEE_T_MCOL }, | |
2285 | { "IEEE_tx_def", IEEE_T_DEF }, | |
2286 | { "IEEE_tx_lcol", IEEE_T_LCOL }, | |
2287 | { "IEEE_tx_excol", IEEE_T_EXCOL }, | |
2288 | { "IEEE_tx_macerr", IEEE_T_MACERR }, | |
2289 | { "IEEE_tx_cserr", IEEE_T_CSERR }, | |
2290 | { "IEEE_tx_sqe", IEEE_T_SQE }, | |
2291 | { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, | |
2292 | { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, | |
2293 | ||
2294 | /* RMON RX */ | |
2295 | { "rx_packets", RMON_R_PACKETS }, | |
2296 | { "rx_broadcast", RMON_R_BC_PKT }, | |
2297 | { "rx_multicast", RMON_R_MC_PKT }, | |
2298 | { "rx_crc_errors", RMON_R_CRC_ALIGN }, | |
2299 | { "rx_undersize", RMON_R_UNDERSIZE }, | |
2300 | { "rx_oversize", RMON_R_OVERSIZE }, | |
2301 | { "rx_fragment", RMON_R_FRAG }, | |
2302 | { "rx_jabber", RMON_R_JAB }, | |
2303 | { "rx_64byte", RMON_R_P64 }, | |
2304 | { "rx_65to127byte", RMON_R_P65TO127 }, | |
2305 | { "rx_128to255byte", RMON_R_P128TO255 }, | |
2306 | { "rx_256to511byte", RMON_R_P256TO511 }, | |
2307 | { "rx_512to1023byte", RMON_R_P512TO1023 }, | |
2308 | { "rx_1024to2047byte", RMON_R_P1024TO2047 }, | |
2309 | { "rx_GTE2048byte", RMON_R_P_GTE2048 }, | |
2310 | { "rx_octets", RMON_R_OCTETS }, | |
2311 | ||
2312 | /* IEEE RX */ | |
2313 | { "IEEE_rx_drop", IEEE_R_DROP }, | |
2314 | { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, | |
2315 | { "IEEE_rx_crc", IEEE_R_CRC }, | |
2316 | { "IEEE_rx_align", IEEE_R_ALIGN }, | |
2317 | { "IEEE_rx_macerr", IEEE_R_MACERR }, | |
2318 | { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, | |
2319 | { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, | |
2320 | }; | |
2321 | ||
f85de666 NY |
2322 | #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) |
2323 | ||
80cca775 | 2324 | static void fec_enet_update_ethtool_stats(struct net_device *dev) |
38ae92dc CH |
2325 | { |
2326 | struct fec_enet_private *fep = netdev_priv(dev); | |
2327 | int i; | |
2328 | ||
2329 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
80cca775 NY |
2330 | fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); |
2331 | } | |
2332 | ||
2333 | static void fec_enet_get_ethtool_stats(struct net_device *dev, | |
2334 | struct ethtool_stats *stats, u64 *data) | |
2335 | { | |
2336 | struct fec_enet_private *fep = netdev_priv(dev); | |
2337 | ||
2338 | if (netif_running(dev)) | |
2339 | fec_enet_update_ethtool_stats(dev); | |
2340 | ||
f85de666 | 2341 | memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); |
38ae92dc CH |
2342 | } |
2343 | ||
2344 | static void fec_enet_get_strings(struct net_device *netdev, | |
2345 | u32 stringset, u8 *data) | |
2346 | { | |
2347 | int i; | |
2348 | switch (stringset) { | |
2349 | case ETH_SS_STATS: | |
2350 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
2351 | memcpy(data + i * ETH_GSTRING_LEN, | |
2352 | fec_stats[i].name, ETH_GSTRING_LEN); | |
2353 | break; | |
2354 | } | |
2355 | } | |
2356 | ||
2357 | static int fec_enet_get_sset_count(struct net_device *dev, int sset) | |
2358 | { | |
2359 | switch (sset) { | |
2360 | case ETH_SS_STATS: | |
2361 | return ARRAY_SIZE(fec_stats); | |
2362 | default: | |
2363 | return -EOPNOTSUPP; | |
2364 | } | |
2365 | } | |
f85de666 | 2366 | |
2b30842b AL |
2367 | static void fec_enet_clear_ethtool_stats(struct net_device *dev) |
2368 | { | |
2369 | struct fec_enet_private *fep = netdev_priv(dev); | |
2370 | int i; | |
2371 | ||
2372 | /* Disable MIB statistics counters */ | |
2373 | writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); | |
2374 | ||
2375 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
2376 | writel(0, fep->hwp + fec_stats[i].offset); | |
2377 | ||
2378 | /* Don't disable MIB statistics counters */ | |
2379 | writel(0, fep->hwp + FEC_MIB_CTRLSTAT); | |
2380 | } | |
2381 | ||
f85de666 NY |
2382 | #else /* !defined(CONFIG_M5272) */ |
2383 | #define FEC_STATS_SIZE 0 | |
2384 | static inline void fec_enet_update_ethtool_stats(struct net_device *dev) | |
2385 | { | |
2386 | } | |
41e8e404 FE |
2387 | |
2388 | static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) | |
2389 | { | |
2390 | } | |
d1391930 | 2391 | #endif /* !defined(CONFIG_M5272) */ |
38ae92dc | 2392 | |
d851b47b FD |
2393 | /* ITR clock source is enet system clock (clk_ahb). |
2394 | * TCTT unit is cycle_ns * 64 cycle | |
2395 | * So, the ICTT value = X us / (cycle_ns * 64) | |
2396 | */ | |
2397 | static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) | |
2398 | { | |
2399 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2400 | ||
2401 | return us * (fep->itr_clk_rate / 64000) / 1000; | |
2402 | } | |
2403 | ||
2404 | /* Set threshold for interrupt coalescing */ | |
2405 | static void fec_enet_itr_coal_set(struct net_device *ndev) | |
2406 | { | |
2407 | struct fec_enet_private *fep = netdev_priv(ndev); | |
d851b47b FD |
2408 | int rx_itr, tx_itr; |
2409 | ||
d851b47b FD |
2410 | /* Must be greater than zero to avoid unpredictable behavior */ |
2411 | if (!fep->rx_time_itr || !fep->rx_pkts_itr || | |
2412 | !fep->tx_time_itr || !fep->tx_pkts_itr) | |
2413 | return; | |
2414 | ||
2415 | /* Select enet system clock as Interrupt Coalescing | |
2416 | * timer Clock Source | |
2417 | */ | |
2418 | rx_itr = FEC_ITR_CLK_SEL; | |
2419 | tx_itr = FEC_ITR_CLK_SEL; | |
2420 | ||
2421 | /* set ICFT and ICTT */ | |
2422 | rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); | |
2423 | rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); | |
2424 | tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); | |
2425 | tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); | |
2426 | ||
2427 | rx_itr |= FEC_ITR_EN; | |
2428 | tx_itr |= FEC_ITR_EN; | |
2429 | ||
2430 | writel(tx_itr, fep->hwp + FEC_TXIC0); | |
2431 | writel(rx_itr, fep->hwp + FEC_RXIC0); | |
ff7566b8 FD |
2432 | if (fep->quirks & FEC_QUIRK_HAS_AVB) { |
2433 | writel(tx_itr, fep->hwp + FEC_TXIC1); | |
2434 | writel(rx_itr, fep->hwp + FEC_RXIC1); | |
2435 | writel(tx_itr, fep->hwp + FEC_TXIC2); | |
2436 | writel(rx_itr, fep->hwp + FEC_RXIC2); | |
2437 | } | |
d851b47b FD |
2438 | } |
2439 | ||
2440 | static int | |
2441 | fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) | |
2442 | { | |
2443 | struct fec_enet_private *fep = netdev_priv(ndev); | |
d851b47b | 2444 | |
ff7566b8 | 2445 | if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) |
d851b47b FD |
2446 | return -EOPNOTSUPP; |
2447 | ||
2448 | ec->rx_coalesce_usecs = fep->rx_time_itr; | |
2449 | ec->rx_max_coalesced_frames = fep->rx_pkts_itr; | |
2450 | ||
2451 | ec->tx_coalesce_usecs = fep->tx_time_itr; | |
2452 | ec->tx_max_coalesced_frames = fep->tx_pkts_itr; | |
2453 | ||
2454 | return 0; | |
2455 | } | |
2456 | ||
2457 | static int | |
2458 | fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) | |
2459 | { | |
2460 | struct fec_enet_private *fep = netdev_priv(ndev); | |
d851b47b FD |
2461 | unsigned int cycle; |
2462 | ||
ff7566b8 | 2463 | if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) |
d851b47b FD |
2464 | return -EOPNOTSUPP; |
2465 | ||
2466 | if (ec->rx_max_coalesced_frames > 255) { | |
9f647a6d | 2467 | pr_err("Rx coalesced frames exceed hardware limitation\n"); |
d851b47b FD |
2468 | return -EINVAL; |
2469 | } | |
2470 | ||
2471 | if (ec->tx_max_coalesced_frames > 255) { | |
9f647a6d | 2472 | pr_err("Tx coalesced frame exceed hardware limitation\n"); |
d851b47b FD |
2473 | return -EINVAL; |
2474 | } | |
2475 | ||
2476 | cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); | |
2477 | if (cycle > 0xFFFF) { | |
9f647a6d | 2478 | pr_err("Rx coalesced usec exceed hardware limitation\n"); |
d851b47b FD |
2479 | return -EINVAL; |
2480 | } | |
2481 | ||
2482 | cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); | |
2483 | if (cycle > 0xFFFF) { | |
9f647a6d | 2484 | pr_err("Rx coalesced usec exceed hardware limitation\n"); |
d851b47b FD |
2485 | return -EINVAL; |
2486 | } | |
2487 | ||
2488 | fep->rx_time_itr = ec->rx_coalesce_usecs; | |
2489 | fep->rx_pkts_itr = ec->rx_max_coalesced_frames; | |
2490 | ||
2491 | fep->tx_time_itr = ec->tx_coalesce_usecs; | |
2492 | fep->tx_pkts_itr = ec->tx_max_coalesced_frames; | |
2493 | ||
2494 | fec_enet_itr_coal_set(ndev); | |
2495 | ||
2496 | return 0; | |
2497 | } | |
2498 | ||
2499 | static void fec_enet_itr_coal_init(struct net_device *ndev) | |
2500 | { | |
2501 | struct ethtool_coalesce ec; | |
2502 | ||
2503 | ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; | |
2504 | ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; | |
2505 | ||
2506 | ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; | |
2507 | ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; | |
2508 | ||
2509 | fec_enet_set_coalesce(ndev, &ec); | |
2510 | } | |
2511 | ||
1b7bde6d NA |
2512 | static int fec_enet_get_tunable(struct net_device *netdev, |
2513 | const struct ethtool_tunable *tuna, | |
2514 | void *data) | |
2515 | { | |
2516 | struct fec_enet_private *fep = netdev_priv(netdev); | |
2517 | int ret = 0; | |
2518 | ||
2519 | switch (tuna->id) { | |
2520 | case ETHTOOL_RX_COPYBREAK: | |
2521 | *(u32 *)data = fep->rx_copybreak; | |
2522 | break; | |
2523 | default: | |
2524 | ret = -EINVAL; | |
2525 | break; | |
2526 | } | |
2527 | ||
2528 | return ret; | |
2529 | } | |
2530 | ||
2531 | static int fec_enet_set_tunable(struct net_device *netdev, | |
2532 | const struct ethtool_tunable *tuna, | |
2533 | const void *data) | |
2534 | { | |
2535 | struct fec_enet_private *fep = netdev_priv(netdev); | |
2536 | int ret = 0; | |
2537 | ||
2538 | switch (tuna->id) { | |
2539 | case ETHTOOL_RX_COPYBREAK: | |
2540 | fep->rx_copybreak = *(u32 *)data; | |
2541 | break; | |
2542 | default: | |
2543 | ret = -EINVAL; | |
2544 | break; | |
2545 | } | |
2546 | ||
2547 | return ret; | |
2548 | } | |
2549 | ||
de40ed31 NA |
2550 | static void |
2551 | fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) | |
2552 | { | |
2553 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2554 | ||
2555 | if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { | |
2556 | wol->supported = WAKE_MAGIC; | |
2557 | wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; | |
2558 | } else { | |
2559 | wol->supported = wol->wolopts = 0; | |
2560 | } | |
2561 | } | |
2562 | ||
2563 | static int | |
2564 | fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) | |
2565 | { | |
2566 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2567 | ||
2568 | if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) | |
2569 | return -EINVAL; | |
2570 | ||
2571 | if (wol->wolopts & ~WAKE_MAGIC) | |
2572 | return -EINVAL; | |
2573 | ||
2574 | device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); | |
2575 | if (device_may_wakeup(&ndev->dev)) { | |
2576 | fep->wol_flag |= FEC_WOL_FLAG_ENABLE; | |
2577 | if (fep->irq[0] > 0) | |
2578 | enable_irq_wake(fep->irq[0]); | |
2579 | } else { | |
2580 | fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); | |
2581 | if (fep->irq[0] > 0) | |
2582 | disable_irq_wake(fep->irq[0]); | |
2583 | } | |
2584 | ||
2585 | return 0; | |
2586 | } | |
2587 | ||
9b07be4b | 2588 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
e6b043d5 | 2589 | .get_drvinfo = fec_enet_get_drvinfo, |
db65f35f PR |
2590 | .get_regs_len = fec_enet_get_regs_len, |
2591 | .get_regs = fec_enet_get_regs, | |
11d59289 | 2592 | .nway_reset = phy_ethtool_nway_reset, |
c1d7c48f | 2593 | .get_link = ethtool_op_get_link, |
d851b47b FD |
2594 | .get_coalesce = fec_enet_get_coalesce, |
2595 | .set_coalesce = fec_enet_set_coalesce, | |
38ae92dc | 2596 | #ifndef CONFIG_M5272 |
c1d7c48f RK |
2597 | .get_pauseparam = fec_enet_get_pauseparam, |
2598 | .set_pauseparam = fec_enet_set_pauseparam, | |
38ae92dc | 2599 | .get_strings = fec_enet_get_strings, |
c1d7c48f | 2600 | .get_ethtool_stats = fec_enet_get_ethtool_stats, |
38ae92dc CH |
2601 | .get_sset_count = fec_enet_get_sset_count, |
2602 | #endif | |
c1d7c48f | 2603 | .get_ts_info = fec_enet_get_ts_info, |
1b7bde6d NA |
2604 | .get_tunable = fec_enet_get_tunable, |
2605 | .set_tunable = fec_enet_set_tunable, | |
de40ed31 NA |
2606 | .get_wol = fec_enet_get_wol, |
2607 | .set_wol = fec_enet_set_wol, | |
9365fbf5 PR |
2608 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
2609 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
e6b043d5 | 2610 | }; |
1da177e4 | 2611 | |
c556167f | 2612 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 2613 | { |
c556167f | 2614 | struct fec_enet_private *fep = netdev_priv(ndev); |
45f5c327 | 2615 | struct phy_device *phydev = ndev->phydev; |
1da177e4 | 2616 | |
c556167f | 2617 | if (!netif_running(ndev)) |
e6b043d5 | 2618 | return -EINVAL; |
1da177e4 | 2619 | |
e6b043d5 BW |
2620 | if (!phydev) |
2621 | return -ENODEV; | |
2622 | ||
1d5244d0 BH |
2623 | if (fep->bufdesc_ex) { |
2624 | if (cmd == SIOCSHWTSTAMP) | |
2625 | return fec_ptp_set(ndev, rq); | |
2626 | if (cmd == SIOCGHWTSTAMP) | |
2627 | return fec_ptp_get(ndev, rq); | |
2628 | } | |
ff43da86 | 2629 | |
28b04113 | 2630 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
2631 | } |
2632 | ||
c556167f | 2633 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 2634 | { |
c556167f | 2635 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 2636 | unsigned int i; |
f0b3fbea SH |
2637 | struct sk_buff *skb; |
2638 | struct bufdesc *bdp; | |
4d494cdc FD |
2639 | struct fec_enet_priv_tx_q *txq; |
2640 | struct fec_enet_priv_rx_q *rxq; | |
59d0f746 FL |
2641 | unsigned int q; |
2642 | ||
2643 | for (q = 0; q < fep->num_rx_queues; q++) { | |
2644 | rxq = fep->rx_queue[q]; | |
7355f276 TK |
2645 | bdp = rxq->bd.base; |
2646 | for (i = 0; i < rxq->bd.ring_size; i++) { | |
59d0f746 FL |
2647 | skb = rxq->rx_skbuff[i]; |
2648 | rxq->rx_skbuff[i] = NULL; | |
2649 | if (skb) { | |
2650 | dma_unmap_single(&fep->pdev->dev, | |
5cfa3039 | 2651 | fec32_to_cpu(bdp->cbd_bufaddr), |
b64bf4b7 | 2652 | FEC_ENET_RX_FRSIZE - fep->rx_align, |
59d0f746 FL |
2653 | DMA_FROM_DEVICE); |
2654 | dev_kfree_skb(skb); | |
2655 | } | |
7355f276 | 2656 | bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); |
59d0f746 FL |
2657 | } |
2658 | } | |
4d494cdc | 2659 | |
59d0f746 FL |
2660 | for (q = 0; q < fep->num_tx_queues; q++) { |
2661 | txq = fep->tx_queue[q]; | |
7355f276 TK |
2662 | bdp = txq->bd.base; |
2663 | for (i = 0; i < txq->bd.ring_size; i++) { | |
59d0f746 FL |
2664 | kfree(txq->tx_bounce[i]); |
2665 | txq->tx_bounce[i] = NULL; | |
2666 | skb = txq->tx_skbuff[i]; | |
2667 | txq->tx_skbuff[i] = NULL; | |
f0b3fbea | 2668 | dev_kfree_skb(skb); |
730ee360 | 2669 | } |
f0b3fbea | 2670 | } |
59d0f746 | 2671 | } |
f0b3fbea | 2672 | |
59d0f746 FL |
2673 | static void fec_enet_free_queue(struct net_device *ndev) |
2674 | { | |
2675 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2676 | int i; | |
2677 | struct fec_enet_priv_tx_q *txq; | |
2678 | ||
2679 | for (i = 0; i < fep->num_tx_queues; i++) | |
2680 | if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { | |
2681 | txq = fep->tx_queue[i]; | |
94920128 | 2682 | dma_free_coherent(&fep->pdev->dev, |
7355f276 | 2683 | txq->bd.ring_size * TSO_HEADER_SIZE, |
59d0f746 FL |
2684 | txq->tso_hdrs, |
2685 | txq->tso_hdrs_dma); | |
2686 | } | |
2687 | ||
2688 | for (i = 0; i < fep->num_rx_queues; i++) | |
1b4b32c6 | 2689 | kfree(fep->rx_queue[i]); |
59d0f746 | 2690 | for (i = 0; i < fep->num_tx_queues; i++) |
1b4b32c6 | 2691 | kfree(fep->tx_queue[i]); |
59d0f746 FL |
2692 | } |
2693 | ||
2694 | static int fec_enet_alloc_queue(struct net_device *ndev) | |
2695 | { | |
2696 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2697 | int i; | |
2698 | int ret = 0; | |
2699 | struct fec_enet_priv_tx_q *txq; | |
2700 | ||
2701 | for (i = 0; i < fep->num_tx_queues; i++) { | |
2702 | txq = kzalloc(sizeof(*txq), GFP_KERNEL); | |
2703 | if (!txq) { | |
2704 | ret = -ENOMEM; | |
2705 | goto alloc_failed; | |
2706 | } | |
2707 | ||
2708 | fep->tx_queue[i] = txq; | |
7355f276 TK |
2709 | txq->bd.ring_size = TX_RING_SIZE; |
2710 | fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; | |
59d0f746 FL |
2711 | |
2712 | txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; | |
2713 | txq->tx_wake_threshold = | |
7355f276 | 2714 | (txq->bd.ring_size - txq->tx_stop_threshold) / 2; |
59d0f746 | 2715 | |
94920128 | 2716 | txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, |
7355f276 | 2717 | txq->bd.ring_size * TSO_HEADER_SIZE, |
59d0f746 FL |
2718 | &txq->tso_hdrs_dma, |
2719 | GFP_KERNEL); | |
2720 | if (!txq->tso_hdrs) { | |
2721 | ret = -ENOMEM; | |
2722 | goto alloc_failed; | |
2723 | } | |
8b7c9efa | 2724 | } |
59d0f746 FL |
2725 | |
2726 | for (i = 0; i < fep->num_rx_queues; i++) { | |
2727 | fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), | |
2728 | GFP_KERNEL); | |
2729 | if (!fep->rx_queue[i]) { | |
2730 | ret = -ENOMEM; | |
2731 | goto alloc_failed; | |
2732 | } | |
2733 | ||
7355f276 TK |
2734 | fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; |
2735 | fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; | |
59d0f746 FL |
2736 | } |
2737 | return ret; | |
2738 | ||
2739 | alloc_failed: | |
2740 | fec_enet_free_queue(ndev); | |
2741 | return ret; | |
f0b3fbea SH |
2742 | } |
2743 | ||
59d0f746 FL |
2744 | static int |
2745 | fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) | |
f0b3fbea | 2746 | { |
c556167f | 2747 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 2748 | unsigned int i; |
f0b3fbea SH |
2749 | struct sk_buff *skb; |
2750 | struct bufdesc *bdp; | |
4d494cdc | 2751 | struct fec_enet_priv_rx_q *rxq; |
f0b3fbea | 2752 | |
59d0f746 | 2753 | rxq = fep->rx_queue[queue]; |
7355f276 TK |
2754 | bdp = rxq->bd.base; |
2755 | for (i = 0; i < rxq->bd.ring_size; i++) { | |
b72061a3 | 2756 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
ffdce2cc RK |
2757 | if (!skb) |
2758 | goto err_alloc; | |
f0b3fbea | 2759 | |
1b7bde6d | 2760 | if (fec_enet_new_rxbdp(ndev, bdp, skb)) { |
730ee360 | 2761 | dev_kfree_skb(skb); |
ffdce2cc | 2762 | goto err_alloc; |
d842a31f | 2763 | } |
730ee360 | 2764 | |
4d494cdc | 2765 | rxq->rx_skbuff[i] = skb; |
5cfa3039 | 2766 | bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); |
ff43da86 FL |
2767 | |
2768 | if (fep->bufdesc_ex) { | |
2769 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
5cfa3039 | 2770 | ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); |
ff43da86 FL |
2771 | } |
2772 | ||
7355f276 | 2773 | bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); |
f0b3fbea SH |
2774 | } |
2775 | ||
2776 | /* Set the last buffer to wrap. */ | |
7355f276 | 2777 | bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); |
5cfa3039 | 2778 | bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); |
59d0f746 | 2779 | return 0; |
f0b3fbea | 2780 | |
59d0f746 FL |
2781 | err_alloc: |
2782 | fec_enet_free_buffers(ndev); | |
2783 | return -ENOMEM; | |
2784 | } | |
2785 | ||
2786 | static int | |
2787 | fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) | |
2788 | { | |
2789 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2790 | unsigned int i; | |
2791 | struct bufdesc *bdp; | |
2792 | struct fec_enet_priv_tx_q *txq; | |
2793 | ||
2794 | txq = fep->tx_queue[queue]; | |
7355f276 TK |
2795 | bdp = txq->bd.base; |
2796 | for (i = 0; i < txq->bd.ring_size; i++) { | |
4d494cdc FD |
2797 | txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); |
2798 | if (!txq->tx_bounce[i]) | |
ffdce2cc | 2799 | goto err_alloc; |
f0b3fbea | 2800 | |
5cfa3039 JB |
2801 | bdp->cbd_sc = cpu_to_fec16(0); |
2802 | bdp->cbd_bufaddr = cpu_to_fec32(0); | |
6605b730 | 2803 | |
ff43da86 FL |
2804 | if (fep->bufdesc_ex) { |
2805 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
5cfa3039 | 2806 | ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); |
ff43da86 FL |
2807 | } |
2808 | ||
7355f276 | 2809 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
f0b3fbea SH |
2810 | } |
2811 | ||
2812 | /* Set the last buffer to wrap. */ | |
7355f276 | 2813 | bdp = fec_enet_get_prevdesc(bdp, &txq->bd); |
5cfa3039 | 2814 | bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); |
f0b3fbea SH |
2815 | |
2816 | return 0; | |
ffdce2cc RK |
2817 | |
2818 | err_alloc: | |
2819 | fec_enet_free_buffers(ndev); | |
2820 | return -ENOMEM; | |
f0b3fbea SH |
2821 | } |
2822 | ||
59d0f746 FL |
2823 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
2824 | { | |
2825 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2826 | unsigned int i; | |
2827 | ||
2828 | for (i = 0; i < fep->num_rx_queues; i++) | |
2829 | if (fec_enet_alloc_rxq_buffers(ndev, i)) | |
2830 | return -ENOMEM; | |
2831 | ||
2832 | for (i = 0; i < fep->num_tx_queues; i++) | |
2833 | if (fec_enet_alloc_txq_buffers(ndev, i)) | |
2834 | return -ENOMEM; | |
2835 | return 0; | |
2836 | } | |
2837 | ||
1da177e4 | 2838 | static int |
c556167f | 2839 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 2840 | { |
c556167f | 2841 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 2842 | int ret; |
1da177e4 | 2843 | |
8fff755e | 2844 | ret = pm_runtime_get_sync(&fep->pdev->dev); |
b0c6ce24 | 2845 | if (ret < 0) |
8fff755e AL |
2846 | return ret; |
2847 | ||
5bbde4d2 | 2848 | pinctrl_pm_select_default_state(&fep->pdev->dev); |
e8fcfcd5 NA |
2849 | ret = fec_enet_clk_enable(ndev, true); |
2850 | if (ret) | |
8fff755e | 2851 | goto clk_enable; |
e8fcfcd5 | 2852 | |
1da177e4 LT |
2853 | /* I should reset the ring buffers here, but I don't yet know |
2854 | * a simple way to do that. | |
2855 | */ | |
1da177e4 | 2856 | |
c556167f | 2857 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea | 2858 | if (ret) |
681d2421 | 2859 | goto err_enet_alloc; |
f0b3fbea | 2860 | |
55dd2753 NA |
2861 | /* Init MAC prior to mii bus probe */ |
2862 | fec_restart(ndev); | |
2863 | ||
418bd0d4 | 2864 | /* Probe and connect to PHY when open the interface */ |
c556167f | 2865 | ret = fec_enet_mii_probe(ndev); |
681d2421 FE |
2866 | if (ret) |
2867 | goto err_enet_mii_probe; | |
ce5eaf02 | 2868 | |
29380905 LS |
2869 | if (fep->quirks & FEC_QUIRK_ERR006687) |
2870 | imx6q_cpuidle_fec_irqs_used(); | |
2871 | ||
ce5eaf02 | 2872 | napi_enable(&fep->napi); |
45f5c327 | 2873 | phy_start(ndev->phydev); |
4d494cdc FD |
2874 | netif_tx_start_all_queues(ndev); |
2875 | ||
de40ed31 NA |
2876 | device_set_wakeup_enable(&ndev->dev, fep->wol_flag & |
2877 | FEC_WOL_FLAG_ENABLE); | |
2878 | ||
22f6b860 | 2879 | return 0; |
681d2421 FE |
2880 | |
2881 | err_enet_mii_probe: | |
2882 | fec_enet_free_buffers(ndev); | |
2883 | err_enet_alloc: | |
2884 | fec_enet_clk_enable(ndev, false); | |
8fff755e AL |
2885 | clk_enable: |
2886 | pm_runtime_mark_last_busy(&fep->pdev->dev); | |
2887 | pm_runtime_put_autosuspend(&fep->pdev->dev); | |
681d2421 FE |
2888 | pinctrl_pm_select_sleep_state(&fep->pdev->dev); |
2889 | return ret; | |
1da177e4 LT |
2890 | } |
2891 | ||
2892 | static int | |
c556167f | 2893 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 2894 | { |
c556167f | 2895 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 2896 | |
45f5c327 | 2897 | phy_stop(ndev->phydev); |
d76cfae9 | 2898 | |
31a6de34 RK |
2899 | if (netif_device_present(ndev)) { |
2900 | napi_disable(&fep->napi); | |
2901 | netif_tx_disable(ndev); | |
8bbbd3c1 | 2902 | fec_stop(ndev); |
31a6de34 | 2903 | } |
1da177e4 | 2904 | |
45f5c327 | 2905 | phy_disconnect(ndev->phydev); |
418bd0d4 | 2906 | |
29380905 LS |
2907 | if (fep->quirks & FEC_QUIRK_ERR006687) |
2908 | imx6q_cpuidle_fec_irqs_unused(); | |
2909 | ||
80cca775 NY |
2910 | fec_enet_update_ethtool_stats(ndev); |
2911 | ||
e8fcfcd5 | 2912 | fec_enet_clk_enable(ndev, false); |
5bbde4d2 | 2913 | pinctrl_pm_select_sleep_state(&fep->pdev->dev); |
8fff755e AL |
2914 | pm_runtime_mark_last_busy(&fep->pdev->dev); |
2915 | pm_runtime_put_autosuspend(&fep->pdev->dev); | |
2916 | ||
db8880bc | 2917 | fec_enet_free_buffers(ndev); |
f0b3fbea | 2918 | |
1da177e4 LT |
2919 | return 0; |
2920 | } | |
2921 | ||
1da177e4 LT |
2922 | /* Set or clear the multicast filter for this adaptor. |
2923 | * Skeleton taken from sunlance driver. | |
2924 | * The CPM Ethernet implementation allows Multicast as well as individual | |
2925 | * MAC address filtering. Some of the drivers check to make sure it is | |
2926 | * a group multicast address, and discard those that are not. I guess I | |
2927 | * will do the same for now, but just remove the test if you want | |
2928 | * individual filtering as well (do the upper net layers want or support | |
2929 | * this kind of feature?). | |
2930 | */ | |
2931 | ||
6176e89c | 2932 | #define FEC_HASH_BITS 6 /* #bits in hash */ |
1da177e4 LT |
2933 | #define CRC32_POLY 0xEDB88320 |
2934 | ||
c556167f | 2935 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 2936 | { |
c556167f | 2937 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 2938 | struct netdev_hw_addr *ha; |
48e2f183 | 2939 | unsigned int i, bit, data, crc, tmp; |
1da177e4 | 2940 | unsigned char hash; |
01f8902b | 2941 | unsigned int hash_high = 0, hash_low = 0; |
1da177e4 | 2942 | |
c556167f | 2943 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
2944 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
2945 | tmp |= 0x8; | |
2946 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
2947 | return; |
2948 | } | |
1da177e4 | 2949 | |
4e831836 SH |
2950 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
2951 | tmp &= ~0x8; | |
2952 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
2953 | ||
c556167f | 2954 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
2955 | /* Catch all multicast addresses, so set the |
2956 | * filter to all 1's | |
2957 | */ | |
2958 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
2959 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
2960 | ||
2961 | return; | |
2962 | } | |
2963 | ||
01f8902b | 2964 | /* Add the addresses in hash register */ |
c556167f | 2965 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
2966 | /* calculate crc32 value of mac address */ |
2967 | crc = 0xffffffff; | |
2968 | ||
c556167f | 2969 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 2970 | data = ha->addr[i]; |
4e831836 SH |
2971 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
2972 | crc = (crc >> 1) ^ | |
2973 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
2974 | } |
2975 | } | |
4e831836 | 2976 | |
6176e89c | 2977 | /* only upper 6 bits (FEC_HASH_BITS) are used |
981a0547 | 2978 | * which point to specific bit in the hash registers |
4e831836 | 2979 | */ |
6176e89c | 2980 | hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; |
4e831836 | 2981 | |
01f8902b RS |
2982 | if (hash > 31) |
2983 | hash_high |= 1 << (hash - 32); | |
2984 | else | |
2985 | hash_low |= 1 << hash; | |
1da177e4 | 2986 | } |
01f8902b RS |
2987 | |
2988 | writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
2989 | writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1da177e4 LT |
2990 | } |
2991 | ||
22f6b860 | 2992 | /* Set a MAC change in hardware. */ |
009fda83 | 2993 | static int |
c556167f | 2994 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 2995 | { |
c556167f | 2996 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
2997 | struct sockaddr *addr = p; |
2998 | ||
44934fac LS |
2999 | if (addr) { |
3000 | if (!is_valid_ether_addr(addr->sa_data)) | |
3001 | return -EADDRNOTAVAIL; | |
3002 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); | |
3003 | } | |
1da177e4 | 3004 | |
9638d19e NA |
3005 | /* Add netif status check here to avoid system hang in below case: |
3006 | * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; | |
3007 | * After ethx down, fec all clocks are gated off and then register | |
3008 | * access causes system hang. | |
3009 | */ | |
3010 | if (!netif_running(ndev)) | |
3011 | return 0; | |
3012 | ||
c556167f UKK |
3013 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
3014 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 3015 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 3016 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 3017 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 3018 | return 0; |
1da177e4 LT |
3019 | } |
3020 | ||
7f5c6add | 3021 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
3022 | /** |
3023 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
3024 | * @dev: The FEC network adapter |
3025 | * | |
3026 | * Polled functionality used by netconsole and others in non interrupt mode | |
3027 | * | |
3028 | */ | |
47a5247f | 3029 | static void fec_poll_controller(struct net_device *dev) |
7f5c6add XJ |
3030 | { |
3031 | int i; | |
3032 | struct fec_enet_private *fep = netdev_priv(dev); | |
3033 | ||
3034 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
3035 | if (fep->irq[i] > 0) { | |
3036 | disable_irq(fep->irq[i]); | |
3037 | fec_enet_interrupt(fep->irq[i], dev); | |
3038 | enable_irq(fep->irq[i]); | |
3039 | } | |
3040 | } | |
3041 | } | |
3042 | #endif | |
3043 | ||
5bc26726 | 3044 | static inline void fec_enet_set_netdev_features(struct net_device *netdev, |
4c09eed9 JB |
3045 | netdev_features_t features) |
3046 | { | |
3047 | struct fec_enet_private *fep = netdev_priv(netdev); | |
3048 | netdev_features_t changed = features ^ netdev->features; | |
3049 | ||
3050 | netdev->features = features; | |
3051 | ||
3052 | /* Receive checksum has been changed */ | |
3053 | if (changed & NETIF_F_RXCSUM) { | |
3054 | if (features & NETIF_F_RXCSUM) | |
3055 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
3056 | else | |
3057 | fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; | |
8506fa1d | 3058 | } |
5bc26726 NA |
3059 | } |
3060 | ||
3061 | static int fec_set_features(struct net_device *netdev, | |
3062 | netdev_features_t features) | |
3063 | { | |
3064 | struct fec_enet_private *fep = netdev_priv(netdev); | |
3065 | netdev_features_t changed = features ^ netdev->features; | |
4c09eed9 | 3066 | |
5b40f709 | 3067 | if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { |
5bc26726 NA |
3068 | napi_disable(&fep->napi); |
3069 | netif_tx_lock_bh(netdev); | |
3070 | fec_stop(netdev); | |
3071 | fec_enet_set_netdev_features(netdev, features); | |
ef83337d | 3072 | fec_restart(netdev); |
4d494cdc | 3073 | netif_tx_wake_all_queues(netdev); |
8506fa1d RK |
3074 | netif_tx_unlock_bh(netdev); |
3075 | napi_enable(&fep->napi); | |
5bc26726 NA |
3076 | } else { |
3077 | fec_enet_set_netdev_features(netdev, features); | |
4c09eed9 JB |
3078 | } |
3079 | ||
3080 | return 0; | |
3081 | } | |
3082 | ||
009fda83 SH |
3083 | static const struct net_device_ops fec_netdev_ops = { |
3084 | .ndo_open = fec_enet_open, | |
3085 | .ndo_stop = fec_enet_close, | |
3086 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 3087 | .ndo_set_rx_mode = set_multicast_list, |
009fda83 SH |
3088 | .ndo_validate_addr = eth_validate_addr, |
3089 | .ndo_tx_timeout = fec_timeout, | |
3090 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 3091 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
3092 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3093 | .ndo_poll_controller = fec_poll_controller, | |
3094 | #endif | |
4c09eed9 | 3095 | .ndo_set_features = fec_set_features, |
009fda83 SH |
3096 | }; |
3097 | ||
53bb20d1 TK |
3098 | static const unsigned short offset_des_active_rxq[] = { |
3099 | FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 | |
3100 | }; | |
3101 | ||
3102 | static const unsigned short offset_des_active_txq[] = { | |
3103 | FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 | |
3104 | }; | |
3105 | ||
1da177e4 LT |
3106 | /* |
3107 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 3108 | * |
1da177e4 | 3109 | */ |
c556167f | 3110 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 3111 | { |
c556167f | 3112 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 3113 | struct bufdesc *cbd_base; |
4d494cdc | 3114 | dma_addr_t bd_dma; |
55d0218a | 3115 | int bd_size; |
59d0f746 | 3116 | unsigned int i; |
7355f276 TK |
3117 | unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : |
3118 | sizeof(struct bufdesc); | |
3119 | unsigned dsize_log2 = __fls(dsize); | |
55d0218a | 3120 | |
7355f276 | 3121 | WARN_ON(dsize != (1 << dsize_log2)); |
41ef84ce FD |
3122 | #if defined(CONFIG_ARM) |
3123 | fep->rx_align = 0xf; | |
3124 | fep->tx_align = 0xf; | |
3125 | #else | |
3126 | fep->rx_align = 0x3; | |
3127 | fep->tx_align = 0x3; | |
3128 | #endif | |
3129 | ||
59d0f746 | 3130 | fec_enet_alloc_queue(ndev); |
79f33912 | 3131 | |
7355f276 | 3132 | bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; |
1da177e4 | 3133 | |
8d4dd5cf | 3134 | /* Allocate memory for buffer descriptors. */ |
c0a1a0a6 LS |
3135 | cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, |
3136 | GFP_KERNEL); | |
4d494cdc | 3137 | if (!cbd_base) { |
79f33912 NA |
3138 | return -ENOMEM; |
3139 | } | |
3140 | ||
4d494cdc | 3141 | memset(cbd_base, 0, bd_size); |
1da177e4 | 3142 | |
49da97dc | 3143 | /* Get the Ethernet address */ |
c556167f | 3144 | fec_get_mac(ndev); |
44934fac LS |
3145 | /* make sure MAC we just acquired is programmed into the hw */ |
3146 | fec_set_mac_address(ndev, NULL); | |
1da177e4 | 3147 | |
8d4dd5cf | 3148 | /* Set receive and transmit descriptor base. */ |
59d0f746 | 3149 | for (i = 0; i < fep->num_rx_queues; i++) { |
7355f276 TK |
3150 | struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; |
3151 | unsigned size = dsize * rxq->bd.ring_size; | |
3152 | ||
3153 | rxq->bd.qid = i; | |
3154 | rxq->bd.base = cbd_base; | |
3155 | rxq->bd.cur = cbd_base; | |
3156 | rxq->bd.dma = bd_dma; | |
3157 | rxq->bd.dsize = dsize; | |
3158 | rxq->bd.dsize_log2 = dsize_log2; | |
53bb20d1 | 3159 | rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; |
7355f276 TK |
3160 | bd_dma += size; |
3161 | cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); | |
3162 | rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); | |
59d0f746 FL |
3163 | } |
3164 | ||
3165 | for (i = 0; i < fep->num_tx_queues; i++) { | |
7355f276 TK |
3166 | struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; |
3167 | unsigned size = dsize * txq->bd.ring_size; | |
3168 | ||
3169 | txq->bd.qid = i; | |
3170 | txq->bd.base = cbd_base; | |
3171 | txq->bd.cur = cbd_base; | |
3172 | txq->bd.dma = bd_dma; | |
3173 | txq->bd.dsize = dsize; | |
3174 | txq->bd.dsize_log2 = dsize_log2; | |
53bb20d1 | 3175 | txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; |
7355f276 TK |
3176 | bd_dma += size; |
3177 | cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); | |
3178 | txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); | |
59d0f746 | 3179 | } |
4d494cdc | 3180 | |
1da177e4 | 3181 | |
22f6b860 | 3182 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
3183 | ndev->watchdog_timeo = TX_TIMEOUT; |
3184 | ndev->netdev_ops = &fec_netdev_ops; | |
3185 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 3186 | |
dc975382 | 3187 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
322555f5 | 3188 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); |
dc975382 | 3189 | |
6b7e4008 | 3190 | if (fep->quirks & FEC_QUIRK_HAS_VLAN) |
cdffcf1b JB |
3191 | /* enable hw VLAN support */ |
3192 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
cdffcf1b | 3193 | |
6b7e4008 | 3194 | if (fep->quirks & FEC_QUIRK_HAS_CSUM) { |
79f33912 NA |
3195 | ndev->gso_max_segs = FEC_MAX_TSO_SEGS; |
3196 | ||
48496255 SG |
3197 | /* enable hw accelerator */ |
3198 | ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
79f33912 | 3199 | | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); |
48496255 SG |
3200 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; |
3201 | } | |
4c09eed9 | 3202 | |
6b7e4008 | 3203 | if (fep->quirks & FEC_QUIRK_HAS_AVB) { |
41ef84ce FD |
3204 | fep->tx_align = 0; |
3205 | fep->rx_align = 0x3f; | |
3206 | } | |
3207 | ||
09d1e541 NA |
3208 | ndev->hw_features = ndev->features; |
3209 | ||
ef83337d | 3210 | fec_restart(ndev); |
1da177e4 | 3211 | |
2b30842b AL |
3212 | if (fep->quirks & FEC_QUIRK_MIB_CLEAR) |
3213 | fec_enet_clear_ethtool_stats(ndev); | |
3214 | else | |
3215 | fec_enet_update_ethtool_stats(ndev); | |
80cca775 | 3216 | |
1da177e4 LT |
3217 | return 0; |
3218 | } | |
3219 | ||
ca2cc333 | 3220 | #ifdef CONFIG_OF |
9269e556 | 3221 | static int fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
3222 | { |
3223 | int err, phy_reset; | |
962d8cdc | 3224 | bool active_high = false; |
159a0760 | 3225 | int msec = 1, phy_post_delay = 0; |
ca2cc333 SG |
3226 | struct device_node *np = pdev->dev.of_node; |
3227 | ||
3228 | if (!np) | |
9269e556 | 3229 | return 0; |
ca2cc333 | 3230 | |
61e04ccb | 3231 | err = of_property_read_u32(np, "phy-reset-duration", &msec); |
a3caad0a | 3232 | /* A sane reset duration should not be longer than 1s */ |
61e04ccb | 3233 | if (!err && msec > 1000) |
a3caad0a SG |
3234 | msec = 1; |
3235 | ||
ca2cc333 | 3236 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
9269e556 FD |
3237 | if (phy_reset == -EPROBE_DEFER) |
3238 | return phy_reset; | |
3239 | else if (!gpio_is_valid(phy_reset)) | |
3240 | return 0; | |
07dcf8e9 | 3241 | |
159a0760 QS |
3242 | err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); |
3243 | /* valid reset duration should be less than 1s */ | |
3244 | if (!err && phy_post_delay > 1000) | |
3245 | return -EINVAL; | |
3246 | ||
962d8cdc | 3247 | active_high = of_property_read_bool(np, "phy-reset-active-high"); |
64f10f6e | 3248 | |
119fc007 | 3249 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
962d8cdc | 3250 | active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, |
64f10f6e | 3251 | "phy-reset"); |
ca2cc333 | 3252 | if (err) { |
07dcf8e9 | 3253 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
9269e556 | 3254 | return err; |
ca2cc333 | 3255 | } |
eb37c563 SW |
3256 | |
3257 | if (msec > 20) | |
3258 | msleep(msec); | |
3259 | else | |
3260 | usleep_range(msec * 1000, msec * 1000 + 1000); | |
3261 | ||
962d8cdc | 3262 | gpio_set_value_cansleep(phy_reset, !active_high); |
9269e556 | 3263 | |
159a0760 QS |
3264 | if (!phy_post_delay) |
3265 | return 0; | |
3266 | ||
3267 | if (phy_post_delay > 20) | |
3268 | msleep(phy_post_delay); | |
3269 | else | |
3270 | usleep_range(phy_post_delay * 1000, | |
3271 | phy_post_delay * 1000 + 1000); | |
3272 | ||
9269e556 | 3273 | return 0; |
ca2cc333 SG |
3274 | } |
3275 | #else /* CONFIG_OF */ | |
9269e556 | 3276 | static int fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
3277 | { |
3278 | /* | |
3279 | * In case of platform probe, the reset has been done | |
3280 | * by machine code. | |
3281 | */ | |
9269e556 | 3282 | return 0; |
ca2cc333 SG |
3283 | } |
3284 | #endif /* CONFIG_OF */ | |
3285 | ||
9fc095f1 FD |
3286 | static void |
3287 | fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) | |
3288 | { | |
3289 | struct device_node *np = pdev->dev.of_node; | |
9fc095f1 FD |
3290 | |
3291 | *num_tx = *num_rx = 1; | |
3292 | ||
3293 | if (!np || !of_device_is_available(np)) | |
3294 | return; | |
3295 | ||
3296 | /* parse the num of tx and rx queues */ | |
73b1c90d | 3297 | of_property_read_u32(np, "fsl,num-tx-queues", num_tx); |
b7bd75cf | 3298 | |
73b1c90d | 3299 | of_property_read_u32(np, "fsl,num-rx-queues", num_rx); |
9fc095f1 FD |
3300 | |
3301 | if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { | |
b7bd75cf FL |
3302 | dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", |
3303 | *num_tx); | |
9fc095f1 FD |
3304 | *num_tx = 1; |
3305 | return; | |
3306 | } | |
3307 | ||
3308 | if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { | |
b7bd75cf FL |
3309 | dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", |
3310 | *num_rx); | |
9fc095f1 FD |
3311 | *num_rx = 1; |
3312 | return; | |
3313 | } | |
3314 | ||
3315 | } | |
3316 | ||
4ad1ceec TK |
3317 | static int fec_enet_get_irq_cnt(struct platform_device *pdev) |
3318 | { | |
3319 | int irq_cnt = platform_irq_count(pdev); | |
3320 | ||
3321 | if (irq_cnt > FEC_IRQ_NUM) | |
3322 | irq_cnt = FEC_IRQ_NUM; /* last for pps */ | |
3323 | else if (irq_cnt == 2) | |
3324 | irq_cnt = 1; /* last for pps */ | |
3325 | else if (irq_cnt <= 0) | |
3326 | irq_cnt = 1; /* At least 1 irq is needed */ | |
3327 | return irq_cnt; | |
3328 | } | |
3329 | ||
33897cc8 | 3330 | static int |
ead73183 SH |
3331 | fec_probe(struct platform_device *pdev) |
3332 | { | |
3333 | struct fec_enet_private *fep; | |
5eb32bd0 | 3334 | struct fec_platform_data *pdata; |
ead73183 SH |
3335 | struct net_device *ndev; |
3336 | int i, irq, ret = 0; | |
3337 | struct resource *r; | |
ca2cc333 | 3338 | const struct of_device_id *of_id; |
43af940c | 3339 | static int dev_id; |
407066f8 | 3340 | struct device_node *np = pdev->dev.of_node, *phy_node; |
b7bd75cf FL |
3341 | int num_tx_qs; |
3342 | int num_rx_qs; | |
4ad1ceec TK |
3343 | char irq_name[8]; |
3344 | int irq_cnt; | |
ca2cc333 | 3345 | |
9fc095f1 FD |
3346 | fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); |
3347 | ||
ead73183 | 3348 | /* Init network device */ |
80cca775 | 3349 | ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + |
f85de666 | 3350 | FEC_STATS_SIZE, num_tx_qs, num_rx_qs); |
83e519b6 FE |
3351 | if (!ndev) |
3352 | return -ENOMEM; | |
ead73183 SH |
3353 | |
3354 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
3355 | ||
3356 | /* setup board info structure */ | |
3357 | fep = netdev_priv(ndev); | |
ead73183 | 3358 | |
6b7e4008 LW |
3359 | of_id = of_match_device(fec_dt_ids, &pdev->dev); |
3360 | if (of_id) | |
3361 | pdev->id_entry = of_id->data; | |
3362 | fep->quirks = pdev->id_entry->driver_data; | |
3363 | ||
0c818594 | 3364 | fep->netdev = ndev; |
9fc095f1 FD |
3365 | fep->num_rx_queues = num_rx_qs; |
3366 | fep->num_tx_queues = num_tx_qs; | |
3367 | ||
d1391930 | 3368 | #if !defined(CONFIG_M5272) |
baa70a5c | 3369 | /* default enable pause frame auto negotiation */ |
6b7e4008 | 3370 | if (fep->quirks & FEC_QUIRK_HAS_GBIT) |
baa70a5c | 3371 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; |
d1391930 | 3372 | #endif |
baa70a5c | 3373 | |
5bbde4d2 NA |
3374 | /* Select default pin state */ |
3375 | pinctrl_pm_select_default_state(&pdev->dev); | |
3376 | ||
399db75b | 3377 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
941e173a TB |
3378 | fep->hwp = devm_ioremap_resource(&pdev->dev, r); |
3379 | if (IS_ERR(fep->hwp)) { | |
3380 | ret = PTR_ERR(fep->hwp); | |
3381 | goto failed_ioremap; | |
3382 | } | |
3383 | ||
e6b043d5 | 3384 | fep->pdev = pdev; |
43af940c | 3385 | fep->dev_id = dev_id++; |
ead73183 | 3386 | |
ead73183 SH |
3387 | platform_set_drvdata(pdev, ndev); |
3388 | ||
29380905 LS |
3389 | if ((of_machine_is_compatible("fsl,imx6q") || |
3390 | of_machine_is_compatible("fsl,imx6dl")) && | |
3391 | !of_property_read_bool(np, "fsl,err006687-workaround-present")) | |
3392 | fep->quirks |= FEC_QUIRK_ERR006687; | |
3393 | ||
de40ed31 NA |
3394 | if (of_get_property(np, "fsl,magic-packet", NULL)) |
3395 | fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; | |
3396 | ||
407066f8 UKK |
3397 | phy_node = of_parse_phandle(np, "phy-handle", 0); |
3398 | if (!phy_node && of_phy_is_fixed_link(np)) { | |
3399 | ret = of_phy_register_fixed_link(np); | |
3400 | if (ret < 0) { | |
3401 | dev_err(&pdev->dev, | |
3402 | "broken fixed-link specification\n"); | |
3403 | goto failed_phy; | |
3404 | } | |
3405 | phy_node = of_node_get(np); | |
3406 | } | |
3407 | fep->phy_node = phy_node; | |
3408 | ||
6c5f7808 | 3409 | ret = of_get_phy_mode(pdev->dev.of_node); |
ca2cc333 | 3410 | if (ret < 0) { |
94660ba0 | 3411 | pdata = dev_get_platdata(&pdev->dev); |
ca2cc333 SG |
3412 | if (pdata) |
3413 | fep->phy_interface = pdata->phy; | |
3414 | else | |
3415 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
3416 | } else { | |
3417 | fep->phy_interface = ret; | |
3418 | } | |
3419 | ||
f4d40de3 SH |
3420 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
3421 | if (IS_ERR(fep->clk_ipg)) { | |
3422 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
3423 | goto failed_clk; |
3424 | } | |
f4d40de3 SH |
3425 | |
3426 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
3427 | if (IS_ERR(fep->clk_ahb)) { | |
3428 | ret = PTR_ERR(fep->clk_ahb); | |
3429 | goto failed_clk; | |
3430 | } | |
3431 | ||
d851b47b FD |
3432 | fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); |
3433 | ||
daa7d392 WS |
3434 | /* enet_out is optional, depends on board */ |
3435 | fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); | |
3436 | if (IS_ERR(fep->clk_enet_out)) | |
3437 | fep->clk_enet_out = NULL; | |
3438 | ||
91c0d987 NA |
3439 | fep->ptp_clk_on = false; |
3440 | mutex_init(&fep->ptp_clk_mutex); | |
9b5330ed FD |
3441 | |
3442 | /* clk_ref is optional, depends on board */ | |
3443 | fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); | |
3444 | if (IS_ERR(fep->clk_ref)) | |
3445 | fep->clk_ref = NULL; | |
3446 | ||
6b7e4008 | 3447 | fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; |
6605b730 FL |
3448 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
3449 | if (IS_ERR(fep->clk_ptp)) { | |
c29dc2d7 | 3450 | fep->clk_ptp = NULL; |
217b5844 | 3451 | fep->bufdesc_ex = false; |
6605b730 | 3452 | } |
6605b730 | 3453 | |
e8fcfcd5 | 3454 | ret = fec_enet_clk_enable(ndev, true); |
13a097bd FE |
3455 | if (ret) |
3456 | goto failed_clk; | |
3457 | ||
8fff755e AL |
3458 | ret = clk_prepare_enable(fep->clk_ipg); |
3459 | if (ret) | |
3460 | goto failed_clk_ipg; | |
3461 | ||
f4e9f3d2 FE |
3462 | fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
3463 | if (!IS_ERR(fep->reg_phy)) { | |
3464 | ret = regulator_enable(fep->reg_phy); | |
5fa9c0fe SG |
3465 | if (ret) { |
3466 | dev_err(&pdev->dev, | |
3467 | "Failed to enable phy regulator: %d\n", ret); | |
9269e556 | 3468 | clk_disable_unprepare(fep->clk_ipg); |
5fa9c0fe SG |
3469 | goto failed_regulator; |
3470 | } | |
f6a4d607 | 3471 | } else { |
3f38c683 FD |
3472 | if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { |
3473 | ret = -EPROBE_DEFER; | |
3474 | goto failed_regulator; | |
3475 | } | |
f6a4d607 | 3476 | fep->reg_phy = NULL; |
5fa9c0fe SG |
3477 | } |
3478 | ||
8fff755e AL |
3479 | pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); |
3480 | pm_runtime_use_autosuspend(&pdev->dev); | |
14d2b7c1 | 3481 | pm_runtime_get_noresume(&pdev->dev); |
8fff755e AL |
3482 | pm_runtime_set_active(&pdev->dev); |
3483 | pm_runtime_enable(&pdev->dev); | |
3484 | ||
9269e556 FD |
3485 | ret = fec_reset_phy(pdev); |
3486 | if (ret) | |
3487 | goto failed_reset; | |
2ca9b2aa | 3488 | |
4ad1ceec | 3489 | irq_cnt = fec_enet_get_irq_cnt(pdev); |
e2f8d555 | 3490 | if (fep->bufdesc_ex) |
4ad1ceec | 3491 | fec_ptp_init(pdev, irq_cnt); |
e2f8d555 FE |
3492 | |
3493 | ret = fec_enet_init(ndev); | |
3494 | if (ret) | |
3495 | goto failed_init; | |
3496 | ||
4ad1ceec TK |
3497 | for (i = 0; i < irq_cnt; i++) { |
3498 | sprintf(irq_name, "int%d", i); | |
3499 | irq = platform_get_irq_byname(pdev, irq_name); | |
3500 | if (irq < 0) | |
3501 | irq = platform_get_irq(pdev, i); | |
e2f8d555 | 3502 | if (irq < 0) { |
e2f8d555 FE |
3503 | ret = irq; |
3504 | goto failed_irq; | |
3505 | } | |
0d9b2ab1 | 3506 | ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, |
44a272dd | 3507 | 0, pdev->name, ndev); |
0d9b2ab1 | 3508 | if (ret) |
e2f8d555 | 3509 | goto failed_irq; |
de40ed31 NA |
3510 | |
3511 | fep->irq[i] = irq; | |
e2f8d555 FE |
3512 | } |
3513 | ||
b4d39b53 | 3514 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
3515 | ret = fec_enet_mii_init(pdev); |
3516 | if (ret) | |
3517 | goto failed_mii_init; | |
3518 | ||
03c698c9 OS |
3519 | /* Carrier starts down, phylib will bring it up */ |
3520 | netif_carrier_off(ndev); | |
e8fcfcd5 | 3521 | fec_enet_clk_enable(ndev, false); |
5bbde4d2 | 3522 | pinctrl_pm_select_sleep_state(&pdev->dev); |
03c698c9 | 3523 | |
ead73183 SH |
3524 | ret = register_netdev(ndev); |
3525 | if (ret) | |
3526 | goto failed_register; | |
3527 | ||
de40ed31 NA |
3528 | device_init_wakeup(&ndev->dev, fep->wol_flag & |
3529 | FEC_WOL_HAS_MAGIC_PACKET); | |
3530 | ||
eb1d0640 FE |
3531 | if (fep->bufdesc_ex && fep->ptp_clock) |
3532 | netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); | |
3533 | ||
1b7bde6d | 3534 | fep->rx_copybreak = COPYBREAK_DEFAULT; |
36cdc743 | 3535 | INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); |
8fff755e AL |
3536 | |
3537 | pm_runtime_mark_last_busy(&pdev->dev); | |
3538 | pm_runtime_put_autosuspend(&pdev->dev); | |
3539 | ||
ead73183 SH |
3540 | return 0; |
3541 | ||
3542 | failed_register: | |
e6b043d5 BW |
3543 | fec_enet_mii_remove(fep); |
3544 | failed_mii_init: | |
7a2bbd8d | 3545 | failed_irq: |
7a2bbd8d | 3546 | failed_init: |
32cba57b | 3547 | fec_ptp_stop(pdev); |
f6a4d607 FE |
3548 | if (fep->reg_phy) |
3549 | regulator_disable(fep->reg_phy); | |
9269e556 FD |
3550 | failed_reset: |
3551 | pm_runtime_put(&pdev->dev); | |
3552 | pm_runtime_disable(&pdev->dev); | |
5fa9c0fe | 3553 | failed_regulator: |
8fff755e | 3554 | failed_clk_ipg: |
e8fcfcd5 | 3555 | fec_enet_clk_enable(ndev, false); |
ead73183 | 3556 | failed_clk: |
82005b1c JH |
3557 | if (of_phy_is_fixed_link(np)) |
3558 | of_phy_deregister_fixed_link(np); | |
407066f8 | 3559 | of_node_put(phy_node); |
d1616f07 FD |
3560 | failed_phy: |
3561 | dev_id--; | |
ead73183 SH |
3562 | failed_ioremap: |
3563 | free_netdev(ndev); | |
3564 | ||
3565 | return ret; | |
3566 | } | |
3567 | ||
33897cc8 | 3568 | static int |
ead73183 SH |
3569 | fec_drv_remove(struct platform_device *pdev) |
3570 | { | |
3571 | struct net_device *ndev = platform_get_drvdata(pdev); | |
3572 | struct fec_enet_private *fep = netdev_priv(ndev); | |
82005b1c | 3573 | struct device_node *np = pdev->dev.of_node; |
ead73183 | 3574 | |
36cdc743 | 3575 | cancel_work_sync(&fep->tx_timeout_work); |
32cba57b | 3576 | fec_ptp_stop(pdev); |
e163cc97 | 3577 | unregister_netdev(ndev); |
e6b043d5 | 3578 | fec_enet_mii_remove(fep); |
f6a4d607 FE |
3579 | if (fep->reg_phy) |
3580 | regulator_disable(fep->reg_phy); | |
82005b1c JH |
3581 | if (of_phy_is_fixed_link(np)) |
3582 | of_phy_deregister_fixed_link(np); | |
407066f8 | 3583 | of_node_put(fep->phy_node); |
ead73183 | 3584 | free_netdev(ndev); |
28e2188e | 3585 | |
ead73183 SH |
3586 | return 0; |
3587 | } | |
3588 | ||
dd66d386 | 3589 | static int __maybe_unused fec_suspend(struct device *dev) |
ead73183 | 3590 | { |
87cad5c3 | 3591 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 3592 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 3593 | |
da1774e5 | 3594 | rtnl_lock(); |
04e5216d | 3595 | if (netif_running(ndev)) { |
de40ed31 NA |
3596 | if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) |
3597 | fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; | |
45f5c327 | 3598 | phy_stop(ndev->phydev); |
31a6de34 RK |
3599 | napi_disable(&fep->napi); |
3600 | netif_tx_lock_bh(ndev); | |
04e5216d | 3601 | netif_device_detach(ndev); |
31a6de34 RK |
3602 | netif_tx_unlock_bh(ndev); |
3603 | fec_stop(ndev); | |
f4c4a4e0 | 3604 | fec_enet_clk_enable(ndev, false); |
de40ed31 NA |
3605 | if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) |
3606 | pinctrl_pm_select_sleep_state(&fep->pdev->dev); | |
ead73183 | 3607 | } |
da1774e5 RK |
3608 | rtnl_unlock(); |
3609 | ||
de40ed31 | 3610 | if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) |
238f7bc7 FE |
3611 | regulator_disable(fep->reg_phy); |
3612 | ||
858eeb7d NA |
3613 | /* SOC supply clock to phy, when clock is disabled, phy link down |
3614 | * SOC control phy regulator, when regulator is disabled, phy link down | |
3615 | */ | |
3616 | if (fep->clk_enet_out || fep->reg_phy) | |
3617 | fep->link = 0; | |
3618 | ||
ead73183 SH |
3619 | return 0; |
3620 | } | |
3621 | ||
dd66d386 | 3622 | static int __maybe_unused fec_resume(struct device *dev) |
ead73183 | 3623 | { |
87cad5c3 | 3624 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 3625 | struct fec_enet_private *fep = netdev_priv(ndev); |
de40ed31 | 3626 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
238f7bc7 | 3627 | int ret; |
de40ed31 | 3628 | int val; |
238f7bc7 | 3629 | |
de40ed31 | 3630 | if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { |
238f7bc7 FE |
3631 | ret = regulator_enable(fep->reg_phy); |
3632 | if (ret) | |
3633 | return ret; | |
3634 | } | |
ead73183 | 3635 | |
da1774e5 | 3636 | rtnl_lock(); |
04e5216d | 3637 | if (netif_running(ndev)) { |
f4c4a4e0 NA |
3638 | ret = fec_enet_clk_enable(ndev, true); |
3639 | if (ret) { | |
3640 | rtnl_unlock(); | |
3641 | goto failed_clk; | |
3642 | } | |
de40ed31 NA |
3643 | if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { |
3644 | if (pdata && pdata->sleep_mode_enable) | |
3645 | pdata->sleep_mode_enable(false); | |
3646 | val = readl(fep->hwp + FEC_ECNTRL); | |
3647 | val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); | |
3648 | writel(val, fep->hwp + FEC_ECNTRL); | |
3649 | fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; | |
3650 | } else { | |
3651 | pinctrl_pm_select_default_state(&fep->pdev->dev); | |
3652 | } | |
ef83337d | 3653 | fec_restart(ndev); |
31a6de34 | 3654 | netif_tx_lock_bh(ndev); |
6af42d42 | 3655 | netif_device_attach(ndev); |
dbc64a8e | 3656 | netif_tx_unlock_bh(ndev); |
6af42d42 | 3657 | napi_enable(&fep->napi); |
45f5c327 | 3658 | phy_start(ndev->phydev); |
ead73183 | 3659 | } |
da1774e5 | 3660 | rtnl_unlock(); |
04e5216d | 3661 | |
ead73183 | 3662 | return 0; |
13a097bd | 3663 | |
e8fcfcd5 | 3664 | failed_clk: |
13a097bd FE |
3665 | if (fep->reg_phy) |
3666 | regulator_disable(fep->reg_phy); | |
3667 | return ret; | |
ead73183 SH |
3668 | } |
3669 | ||
8fff755e AL |
3670 | static int __maybe_unused fec_runtime_suspend(struct device *dev) |
3671 | { | |
3672 | struct net_device *ndev = dev_get_drvdata(dev); | |
3673 | struct fec_enet_private *fep = netdev_priv(ndev); | |
3674 | ||
3675 | clk_disable_unprepare(fep->clk_ipg); | |
3676 | ||
3677 | return 0; | |
3678 | } | |
3679 | ||
3680 | static int __maybe_unused fec_runtime_resume(struct device *dev) | |
3681 | { | |
3682 | struct net_device *ndev = dev_get_drvdata(dev); | |
3683 | struct fec_enet_private *fep = netdev_priv(ndev); | |
3684 | ||
3685 | return clk_prepare_enable(fep->clk_ipg); | |
3686 | } | |
3687 | ||
3688 | static const struct dev_pm_ops fec_pm_ops = { | |
3689 | SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) | |
3690 | SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) | |
3691 | }; | |
59d4289b | 3692 | |
ead73183 SH |
3693 | static struct platform_driver fec_driver = { |
3694 | .driver = { | |
b5680e0b | 3695 | .name = DRIVER_NAME, |
87cad5c3 | 3696 | .pm = &fec_pm_ops, |
ca2cc333 | 3697 | .of_match_table = fec_dt_ids, |
ead73183 | 3698 | }, |
b5680e0b | 3699 | .id_table = fec_devtype, |
87cad5c3 | 3700 | .probe = fec_probe, |
33897cc8 | 3701 | .remove = fec_drv_remove, |
ead73183 SH |
3702 | }; |
3703 | ||
aaca2377 | 3704 | module_platform_driver(fec_driver); |
1da177e4 | 3705 | |
f8c0aca9 | 3706 | MODULE_ALIAS("platform:"DRIVER_NAME); |
1da177e4 | 3707 | MODULE_LICENSE("GPL"); |