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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
8fff755e | 27 | #include <linux/pm_runtime.h> |
1da177e4 LT |
28 | #include <linux/ptrace.h> |
29 | #include <linux/errno.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/interrupt.h> | |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
4c09eed9 JB |
37 | #include <linux/in.h> |
38 | #include <linux/ip.h> | |
39 | #include <net/ip.h> | |
79f33912 | 40 | #include <net/tso.h> |
4c09eed9 JB |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/icmp.h> | |
1da177e4 LT |
44 | #include <linux/spinlock.h> |
45 | #include <linux/workqueue.h> | |
46 | #include <linux/bitops.h> | |
6f501b17 SH |
47 | #include <linux/io.h> |
48 | #include <linux/irq.h> | |
196719ec | 49 | #include <linux/clk.h> |
ead73183 | 50 | #include <linux/platform_device.h> |
7f854420 | 51 | #include <linux/mdio.h> |
e6b043d5 | 52 | #include <linux/phy.h> |
5eb32bd0 | 53 | #include <linux/fec.h> |
ca2cc333 SG |
54 | #include <linux/of.h> |
55 | #include <linux/of_device.h> | |
56 | #include <linux/of_gpio.h> | |
407066f8 | 57 | #include <linux/of_mdio.h> |
ca2cc333 | 58 | #include <linux/of_net.h> |
5fa9c0fe | 59 | #include <linux/regulator/consumer.h> |
cdffcf1b | 60 | #include <linux/if_vlan.h> |
a68ab98e | 61 | #include <linux/pinctrl/consumer.h> |
c259c132 | 62 | #include <linux/prefetch.h> |
29380905 | 63 | #include <soc/imx/cpuidle.h> |
1da177e4 | 64 | |
080853af | 65 | #include <asm/cacheflush.h> |
196719ec | 66 | |
1da177e4 | 67 | #include "fec.h" |
1da177e4 | 68 | |
772e42b0 | 69 | static void set_multicast_list(struct net_device *ndev); |
d851b47b | 70 | static void fec_enet_itr_coal_init(struct net_device *ndev); |
772e42b0 | 71 | |
b5680e0b SG |
72 | #define DRIVER_NAME "fec" |
73 | ||
4d494cdc FD |
74 | #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0)) |
75 | ||
baa70a5c FL |
76 | /* Pause frame feild and FIFO threshold */ |
77 | #define FEC_ENET_FCE (1 << 5) | |
78 | #define FEC_ENET_RSEM_V 0x84 | |
79 | #define FEC_ENET_RSFL_V 16 | |
80 | #define FEC_ENET_RAEM_V 0x8 | |
81 | #define FEC_ENET_RAFL_V 0x8 | |
82 | #define FEC_ENET_OPD_V 0xFFF0 | |
8fff755e | 83 | #define FEC_MDIO_PM_TIMEOUT 100 /* ms */ |
baa70a5c | 84 | |
b5680e0b SG |
85 | static struct platform_device_id fec_devtype[] = { |
86 | { | |
0ca1e290 | 87 | /* keep it for coldfire */ |
b5680e0b SG |
88 | .name = DRIVER_NAME, |
89 | .driver_data = 0, | |
0ca1e290 SG |
90 | }, { |
91 | .name = "imx25-fec", | |
18803495 | 92 | .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC, |
0ca1e290 SG |
93 | }, { |
94 | .name = "imx27-fec", | |
18803495 | 95 | .driver_data = FEC_QUIRK_HAS_RACC, |
b5680e0b SG |
96 | }, { |
97 | .name = "imx28-fec", | |
3d125f9c | 98 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | |
18803495 | 99 | FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, |
230dec61 SG |
100 | }, { |
101 | .name = "imx6q-fec", | |
ff43da86 | 102 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
cdffcf1b | 103 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | |
18803495 GU |
104 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | |
105 | FEC_QUIRK_HAS_RACC, | |
ca7c4a45 | 106 | }, { |
36803542 | 107 | .name = "mvf600-fec", |
18803495 | 108 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, |
95a77470 FD |
109 | }, { |
110 | .name = "imx6sx-fec", | |
111 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | | |
112 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | | |
f88c7ede | 113 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | |
18803495 | 114 | FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | |
ff7566b8 | 115 | FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, |
a51d3ab5 FD |
116 | }, { |
117 | .name = "imx6ul-fec", | |
118 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | | |
119 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | | |
120 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_BUG_CAPTURE | | |
121 | FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE, | |
0ca1e290 SG |
122 | }, { |
123 | /* sentinel */ | |
124 | } | |
b5680e0b | 125 | }; |
0ca1e290 | 126 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 127 | |
ca2cc333 | 128 | enum imx_fec_type { |
a7dd3219 | 129 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
130 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
131 | IMX28_FEC, | |
230dec61 | 132 | IMX6Q_FEC, |
36803542 | 133 | MVF600_FEC, |
ba593e00 | 134 | IMX6SX_FEC, |
a51d3ab5 | 135 | IMX6UL_FEC, |
ca2cc333 SG |
136 | }; |
137 | ||
138 | static const struct of_device_id fec_dt_ids[] = { | |
139 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
140 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
141 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 142 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
36803542 | 143 | { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, |
ba593e00 | 144 | { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, |
a51d3ab5 | 145 | { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, |
ca2cc333 SG |
146 | { /* sentinel */ } |
147 | }; | |
148 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
149 | ||
49da97dc SG |
150 | static unsigned char macaddr[ETH_ALEN]; |
151 | module_param_array(macaddr, byte, NULL, 0); | |
152 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 153 | |
49da97dc | 154 | #if defined(CONFIG_M5272) |
1da177e4 LT |
155 | /* |
156 | * Some hardware gets it MAC address out of local flash memory. | |
157 | * if this is non-zero then assume it is the address to get MAC from. | |
158 | */ | |
159 | #if defined(CONFIG_NETtel) | |
160 | #define FEC_FLASHMAC 0xf0006006 | |
161 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
162 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
163 | #elif defined(CONFIG_CANCam) |
164 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
165 | #elif defined (CONFIG_M5272C3) |
166 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
167 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 168 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
169 | #else |
170 | #define FEC_FLASHMAC 0 | |
171 | #endif | |
43be6366 | 172 | #endif /* CONFIG_M5272 */ |
ead73183 | 173 | |
cdffcf1b | 174 | /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. |
1da177e4 | 175 | */ |
cdffcf1b | 176 | #define PKT_MAXBUF_SIZE 1522 |
1da177e4 | 177 | #define PKT_MINBUF_SIZE 64 |
cdffcf1b | 178 | #define PKT_MAXBLR_SIZE 1536 |
1da177e4 | 179 | |
4c09eed9 JB |
180 | /* FEC receive acceleration */ |
181 | #define FEC_RACC_IPDIS (1 << 1) | |
182 | #define FEC_RACC_PRODIS (1 << 2) | |
183 | #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) | |
184 | ||
1da177e4 | 185 | /* |
6b265293 | 186 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
187 | * size bits. Other FEC hardware does not, so we need to take that into |
188 | * account when setting it. | |
189 | */ | |
562d2f8c | 190 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 191 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
192 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
193 | #else | |
194 | #define OPT_FRAME_SIZE 0 | |
195 | #endif | |
196 | ||
e6b043d5 BW |
197 | /* FEC MII MMFR bits definition */ |
198 | #define FEC_MMFR_ST (1 << 30) | |
199 | #define FEC_MMFR_OP_READ (2 << 28) | |
200 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
201 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
202 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
203 | #define FEC_MMFR_TA (2 << 16) | |
204 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
de40ed31 NA |
205 | /* FEC ECR bits definition */ |
206 | #define FEC_ECR_MAGICEN (1 << 2) | |
207 | #define FEC_ECR_SLEEP (1 << 3) | |
1da177e4 | 208 | |
c3b084c2 | 209 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 210 | |
22f6b860 SH |
211 | /* Transmitter timeout */ |
212 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 213 | |
baa70a5c FL |
214 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
215 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
de40ed31 NA |
216 | #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) |
217 | #define FEC_WOL_FLAG_ENABLE (0x1 << 1) | |
218 | #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) | |
baa70a5c | 219 | |
1b7bde6d NA |
220 | #define COPYBREAK_DEFAULT 256 |
221 | ||
79f33912 NA |
222 | #define TSO_HEADER_SIZE 128 |
223 | /* Max number of allowed TCP segments for software TSO */ | |
224 | #define FEC_MAX_TSO_SEGS 100 | |
225 | #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
226 | ||
227 | #define IS_TSO_HEADER(txq, addr) \ | |
228 | ((addr >= txq->tso_hdrs_dma) && \ | |
7355f276 | 229 | (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) |
79f33912 | 230 | |
e163cc97 LW |
231 | static int mii_cnt; |
232 | ||
7355f276 TK |
233 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, |
234 | struct bufdesc_prop *bd) | |
235 | { | |
236 | return (bdp >= bd->last) ? bd->base | |
237 | : (struct bufdesc *)(((unsigned)bdp) + bd->dsize); | |
238 | } | |
36e24e2e | 239 | |
7355f276 TK |
240 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, |
241 | struct bufdesc_prop *bd) | |
242 | { | |
243 | return (bdp <= bd->base) ? bd->last | |
244 | : (struct bufdesc *)(((unsigned)bdp) - bd->dsize); | |
ff43da86 FL |
245 | } |
246 | ||
7355f276 TK |
247 | static int fec_enet_get_bd_index(struct bufdesc *bdp, |
248 | struct bufdesc_prop *bd) | |
61a4427b | 249 | { |
7355f276 | 250 | return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; |
61a4427b NA |
251 | } |
252 | ||
7355f276 | 253 | static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) |
6e909283 NA |
254 | { |
255 | int entries; | |
256 | ||
7355f276 TK |
257 | entries = (((const char *)txq->dirty_tx - |
258 | (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; | |
6e909283 | 259 | |
7355f276 | 260 | return entries >= 0 ? entries : entries + txq->bd.ring_size; |
6e909283 NA |
261 | } |
262 | ||
c20e599b | 263 | static void swap_buffer(void *bufaddr, int len) |
b5680e0b SG |
264 | { |
265 | int i; | |
266 | unsigned int *buf = bufaddr; | |
267 | ||
7b487d07 | 268 | for (i = 0; i < len; i += 4, buf++) |
e453789a | 269 | swab32s(buf); |
b5680e0b SG |
270 | } |
271 | ||
1310b544 LW |
272 | static void swap_buffer2(void *dst_buf, void *src_buf, int len) |
273 | { | |
274 | int i; | |
275 | unsigned int *src = src_buf; | |
276 | unsigned int *dst = dst_buf; | |
277 | ||
278 | for (i = 0; i < len; i += 4, src++, dst++) | |
279 | *dst = swab32p(src); | |
280 | } | |
281 | ||
344756f6 RK |
282 | static void fec_dump(struct net_device *ndev) |
283 | { | |
284 | struct fec_enet_private *fep = netdev_priv(ndev); | |
4d494cdc FD |
285 | struct bufdesc *bdp; |
286 | struct fec_enet_priv_tx_q *txq; | |
287 | int index = 0; | |
344756f6 RK |
288 | |
289 | netdev_info(ndev, "TX ring dump\n"); | |
290 | pr_info("Nr SC addr len SKB\n"); | |
291 | ||
4d494cdc | 292 | txq = fep->tx_queue[0]; |
7355f276 | 293 | bdp = txq->bd.base; |
4d494cdc | 294 | |
344756f6 | 295 | do { |
5cfa3039 | 296 | pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", |
344756f6 | 297 | index, |
7355f276 | 298 | bdp == txq->bd.cur ? 'S' : ' ', |
4d494cdc | 299 | bdp == txq->dirty_tx ? 'H' : ' ', |
5cfa3039 JB |
300 | fec16_to_cpu(bdp->cbd_sc), |
301 | fec32_to_cpu(bdp->cbd_bufaddr), | |
302 | fec16_to_cpu(bdp->cbd_datlen), | |
4d494cdc | 303 | txq->tx_skbuff[index]); |
7355f276 | 304 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
344756f6 | 305 | index++; |
7355f276 | 306 | } while (bdp != txq->bd.base); |
344756f6 RK |
307 | } |
308 | ||
62a02c98 FD |
309 | static inline bool is_ipv4_pkt(struct sk_buff *skb) |
310 | { | |
311 | return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; | |
312 | } | |
313 | ||
4c09eed9 JB |
314 | static int |
315 | fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) | |
316 | { | |
317 | /* Only run for packets requiring a checksum. */ | |
318 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
319 | return 0; | |
320 | ||
321 | if (unlikely(skb_cow_head(skb, 0))) | |
322 | return -1; | |
323 | ||
62a02c98 FD |
324 | if (is_ipv4_pkt(skb)) |
325 | ip_hdr(skb)->check = 0; | |
4c09eed9 JB |
326 | *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
c4bc44c6 | 331 | static struct bufdesc * |
4d494cdc FD |
332 | fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, |
333 | struct sk_buff *skb, | |
334 | struct net_device *ndev) | |
1da177e4 | 335 | { |
c556167f | 336 | struct fec_enet_private *fep = netdev_priv(ndev); |
7355f276 | 337 | struct bufdesc *bdp = txq->bd.cur; |
6e909283 NA |
338 | struct bufdesc_ex *ebdp; |
339 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
340 | int frag, frag_len; | |
341 | unsigned short status; | |
342 | unsigned int estatus = 0; | |
343 | skb_frag_t *this_frag; | |
de5fb0a0 | 344 | unsigned int index; |
6e909283 | 345 | void *bufaddr; |
d6bf3143 | 346 | dma_addr_t addr; |
6e909283 | 347 | int i; |
1da177e4 | 348 | |
6e909283 NA |
349 | for (frag = 0; frag < nr_frags; frag++) { |
350 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
7355f276 | 351 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
6e909283 NA |
352 | ebdp = (struct bufdesc_ex *)bdp; |
353 | ||
5cfa3039 | 354 | status = fec16_to_cpu(bdp->cbd_sc); |
6e909283 NA |
355 | status &= ~BD_ENET_TX_STATS; |
356 | status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); | |
357 | frag_len = skb_shinfo(skb)->frags[frag].size; | |
358 | ||
359 | /* Handle the last BD specially */ | |
360 | if (frag == nr_frags - 1) { | |
361 | status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); | |
362 | if (fep->bufdesc_ex) { | |
363 | estatus |= BD_ENET_TX_INT; | |
364 | if (unlikely(skb_shinfo(skb)->tx_flags & | |
365 | SKBTX_HW_TSTAMP && fep->hwts_tx_en)) | |
366 | estatus |= BD_ENET_TX_TS; | |
367 | } | |
368 | } | |
369 | ||
370 | if (fep->bufdesc_ex) { | |
6b7e4008 | 371 | if (fep->quirks & FEC_QUIRK_HAS_AVB) |
53bb20d1 | 372 | estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); |
6e909283 NA |
373 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
374 | estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; | |
375 | ebdp->cbd_bdu = 0; | |
5cfa3039 | 376 | ebdp->cbd_esc = cpu_to_fec32(estatus); |
6e909283 NA |
377 | } |
378 | ||
379 | bufaddr = page_address(this_frag->page.p) + this_frag->page_offset; | |
380 | ||
7355f276 | 381 | index = fec_enet_get_bd_index(bdp, &txq->bd); |
41ef84ce | 382 | if (((unsigned long) bufaddr) & fep->tx_align || |
6b7e4008 | 383 | fep->quirks & FEC_QUIRK_SWAP_FRAME) { |
4d494cdc FD |
384 | memcpy(txq->tx_bounce[index], bufaddr, frag_len); |
385 | bufaddr = txq->tx_bounce[index]; | |
6e909283 | 386 | |
6b7e4008 | 387 | if (fep->quirks & FEC_QUIRK_SWAP_FRAME) |
6e909283 NA |
388 | swap_buffer(bufaddr, frag_len); |
389 | } | |
390 | ||
d6bf3143 RK |
391 | addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, |
392 | DMA_TO_DEVICE); | |
393 | if (dma_mapping_error(&fep->pdev->dev, addr)) { | |
6e909283 NA |
394 | if (net_ratelimit()) |
395 | netdev_err(ndev, "Tx DMA memory map failed\n"); | |
396 | goto dma_mapping_error; | |
397 | } | |
398 | ||
5cfa3039 JB |
399 | bdp->cbd_bufaddr = cpu_to_fec32(addr); |
400 | bdp->cbd_datlen = cpu_to_fec16(frag_len); | |
be293467 TK |
401 | /* Make sure the updates to rest of the descriptor are |
402 | * performed before transferring ownership. | |
403 | */ | |
404 | wmb(); | |
5cfa3039 | 405 | bdp->cbd_sc = cpu_to_fec16(status); |
6e909283 NA |
406 | } |
407 | ||
c4bc44c6 | 408 | return bdp; |
6e909283 | 409 | dma_mapping_error: |
7355f276 | 410 | bdp = txq->bd.cur; |
6e909283 | 411 | for (i = 0; i < frag; i++) { |
7355f276 | 412 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
5cfa3039 JB |
413 | dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), |
414 | fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); | |
6e909283 | 415 | } |
c4bc44c6 | 416 | return ERR_PTR(-ENOMEM); |
6e909283 | 417 | } |
1da177e4 | 418 | |
4d494cdc FD |
419 | static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, |
420 | struct sk_buff *skb, struct net_device *ndev) | |
6e909283 NA |
421 | { |
422 | struct fec_enet_private *fep = netdev_priv(ndev); | |
6e909283 NA |
423 | int nr_frags = skb_shinfo(skb)->nr_frags; |
424 | struct bufdesc *bdp, *last_bdp; | |
425 | void *bufaddr; | |
d6bf3143 | 426 | dma_addr_t addr; |
6e909283 NA |
427 | unsigned short status; |
428 | unsigned short buflen; | |
429 | unsigned int estatus = 0; | |
430 | unsigned int index; | |
79f33912 | 431 | int entries_free; |
22f6b860 | 432 | |
7355f276 | 433 | entries_free = fec_enet_get_free_txdesc_num(txq); |
79f33912 NA |
434 | if (entries_free < MAX_SKB_FRAGS + 1) { |
435 | dev_kfree_skb_any(skb); | |
436 | if (net_ratelimit()) | |
437 | netdev_err(ndev, "NOT enough BD for SG!\n"); | |
438 | return NETDEV_TX_OK; | |
439 | } | |
440 | ||
4c09eed9 JB |
441 | /* Protocol checksum off-load for TCP and UDP. */ |
442 | if (fec_enet_clear_csum(skb, ndev)) { | |
8e7e6874 | 443 | dev_kfree_skb_any(skb); |
4c09eed9 JB |
444 | return NETDEV_TX_OK; |
445 | } | |
446 | ||
6e909283 | 447 | /* Fill in a Tx ring entry */ |
7355f276 | 448 | bdp = txq->bd.cur; |
c4bc44c6 | 449 | last_bdp = bdp; |
5cfa3039 | 450 | status = fec16_to_cpu(bdp->cbd_sc); |
0e702ab3 | 451 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 452 | |
22f6b860 | 453 | /* Set buffer length and buffer pointer */ |
9555b31e | 454 | bufaddr = skb->data; |
6e909283 | 455 | buflen = skb_headlen(skb); |
1da177e4 | 456 | |
7355f276 | 457 | index = fec_enet_get_bd_index(bdp, &txq->bd); |
41ef84ce | 458 | if (((unsigned long) bufaddr) & fep->tx_align || |
6b7e4008 | 459 | fep->quirks & FEC_QUIRK_SWAP_FRAME) { |
4d494cdc FD |
460 | memcpy(txq->tx_bounce[index], skb->data, buflen); |
461 | bufaddr = txq->tx_bounce[index]; | |
1da177e4 | 462 | |
6b7e4008 | 463 | if (fep->quirks & FEC_QUIRK_SWAP_FRAME) |
6e909283 NA |
464 | swap_buffer(bufaddr, buflen); |
465 | } | |
6aa20a22 | 466 | |
d6bf3143 RK |
467 | /* Push the data cache so the CPM does not get stale memory data. */ |
468 | addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); | |
469 | if (dma_mapping_error(&fep->pdev->dev, addr)) { | |
d842a31f DFB |
470 | dev_kfree_skb_any(skb); |
471 | if (net_ratelimit()) | |
472 | netdev_err(ndev, "Tx DMA memory map failed\n"); | |
473 | return NETDEV_TX_OK; | |
474 | } | |
1da177e4 | 475 | |
6e909283 | 476 | if (nr_frags) { |
c4bc44c6 | 477 | last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); |
fc75ba51 TK |
478 | if (IS_ERR(last_bdp)) { |
479 | dma_unmap_single(&fep->pdev->dev, addr, | |
480 | buflen, DMA_TO_DEVICE); | |
481 | dev_kfree_skb_any(skb); | |
c4bc44c6 | 482 | return NETDEV_TX_OK; |
fc75ba51 | 483 | } |
6e909283 NA |
484 | } else { |
485 | status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); | |
486 | if (fep->bufdesc_ex) { | |
487 | estatus = BD_ENET_TX_INT; | |
488 | if (unlikely(skb_shinfo(skb)->tx_flags & | |
489 | SKBTX_HW_TSTAMP && fep->hwts_tx_en)) | |
490 | estatus |= BD_ENET_TX_TS; | |
491 | } | |
492 | } | |
fc75ba51 TK |
493 | bdp->cbd_bufaddr = cpu_to_fec32(addr); |
494 | bdp->cbd_datlen = cpu_to_fec16(buflen); | |
6e909283 | 495 | |
ff43da86 FL |
496 | if (fep->bufdesc_ex) { |
497 | ||
498 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
6e909283 | 499 | |
ff43da86 | 500 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
6e909283 | 501 | fep->hwts_tx_en)) |
6605b730 | 502 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
4c09eed9 | 503 | |
6b7e4008 | 504 | if (fep->quirks & FEC_QUIRK_HAS_AVB) |
53bb20d1 | 505 | estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); |
befe8213 | 506 | |
6e909283 NA |
507 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
508 | estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; | |
509 | ||
510 | ebdp->cbd_bdu = 0; | |
5cfa3039 | 511 | ebdp->cbd_esc = cpu_to_fec32(estatus); |
6605b730 | 512 | } |
03191656 | 513 | |
7355f276 | 514 | index = fec_enet_get_bd_index(last_bdp, &txq->bd); |
6e909283 | 515 | /* Save skb pointer */ |
4d494cdc | 516 | txq->tx_skbuff[index] = skb; |
6e909283 | 517 | |
be293467 TK |
518 | /* Make sure the updates to rest of the descriptor are performed before |
519 | * transferring ownership. | |
520 | */ | |
521 | wmb(); | |
6e909283 | 522 | |
fb8ef788 DFB |
523 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
524 | * it's the last BD of the frame, and to put the CRC on the end. | |
525 | */ | |
6e909283 | 526 | status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); |
5cfa3039 | 527 | bdp->cbd_sc = cpu_to_fec16(status); |
fb8ef788 | 528 | |
22f6b860 | 529 | /* If this was the last BD in the ring, start at the beginning again. */ |
7355f276 | 530 | bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); |
1da177e4 | 531 | |
7a2a8451 ED |
532 | skb_tx_timestamp(skb); |
533 | ||
c4bc44c6 | 534 | /* Make sure the update to bdp and tx_skbuff are performed before |
7355f276 | 535 | * txq->bd.cur. |
c4bc44c6 KH |
536 | */ |
537 | wmb(); | |
7355f276 | 538 | txq->bd.cur = bdp; |
de5fb0a0 | 539 | |
de5fb0a0 | 540 | /* Trigger transmission start */ |
53bb20d1 | 541 | writel(0, txq->bd.reg_desc_active); |
1da177e4 | 542 | |
6e909283 | 543 | return 0; |
1da177e4 LT |
544 | } |
545 | ||
79f33912 | 546 | static int |
4d494cdc FD |
547 | fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, |
548 | struct net_device *ndev, | |
549 | struct bufdesc *bdp, int index, char *data, | |
550 | int size, bool last_tcp, bool is_last) | |
61a4427b NA |
551 | { |
552 | struct fec_enet_private *fep = netdev_priv(ndev); | |
61cd2ebb | 553 | struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); |
79f33912 NA |
554 | unsigned short status; |
555 | unsigned int estatus = 0; | |
d6bf3143 | 556 | dma_addr_t addr; |
61a4427b | 557 | |
5cfa3039 | 558 | status = fec16_to_cpu(bdp->cbd_sc); |
79f33912 | 559 | status &= ~BD_ENET_TX_STATS; |
61a4427b | 560 | |
79f33912 | 561 | status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); |
79f33912 | 562 | |
41ef84ce | 563 | if (((unsigned long) data) & fep->tx_align || |
6b7e4008 | 564 | fep->quirks & FEC_QUIRK_SWAP_FRAME) { |
4d494cdc FD |
565 | memcpy(txq->tx_bounce[index], data, size); |
566 | data = txq->tx_bounce[index]; | |
79f33912 | 567 | |
6b7e4008 | 568 | if (fep->quirks & FEC_QUIRK_SWAP_FRAME) |
79f33912 NA |
569 | swap_buffer(data, size); |
570 | } | |
571 | ||
d6bf3143 RK |
572 | addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); |
573 | if (dma_mapping_error(&fep->pdev->dev, addr)) { | |
79f33912 | 574 | dev_kfree_skb_any(skb); |
6e909283 | 575 | if (net_ratelimit()) |
79f33912 | 576 | netdev_err(ndev, "Tx DMA memory map failed\n"); |
61a4427b NA |
577 | return NETDEV_TX_BUSY; |
578 | } | |
579 | ||
5cfa3039 JB |
580 | bdp->cbd_datlen = cpu_to_fec16(size); |
581 | bdp->cbd_bufaddr = cpu_to_fec32(addr); | |
d6bf3143 | 582 | |
79f33912 | 583 | if (fep->bufdesc_ex) { |
6b7e4008 | 584 | if (fep->quirks & FEC_QUIRK_HAS_AVB) |
53bb20d1 | 585 | estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); |
79f33912 NA |
586 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
587 | estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; | |
588 | ebdp->cbd_bdu = 0; | |
5cfa3039 | 589 | ebdp->cbd_esc = cpu_to_fec32(estatus); |
79f33912 NA |
590 | } |
591 | ||
592 | /* Handle the last BD specially */ | |
593 | if (last_tcp) | |
594 | status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); | |
595 | if (is_last) { | |
596 | status |= BD_ENET_TX_INTR; | |
597 | if (fep->bufdesc_ex) | |
5cfa3039 | 598 | ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); |
79f33912 NA |
599 | } |
600 | ||
5cfa3039 | 601 | bdp->cbd_sc = cpu_to_fec16(status); |
79f33912 NA |
602 | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static int | |
4d494cdc FD |
607 | fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, |
608 | struct sk_buff *skb, struct net_device *ndev, | |
609 | struct bufdesc *bdp, int index) | |
79f33912 NA |
610 | { |
611 | struct fec_enet_private *fep = netdev_priv(ndev); | |
79f33912 | 612 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
61cd2ebb | 613 | struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); |
79f33912 NA |
614 | void *bufaddr; |
615 | unsigned long dmabuf; | |
616 | unsigned short status; | |
617 | unsigned int estatus = 0; | |
618 | ||
5cfa3039 | 619 | status = fec16_to_cpu(bdp->cbd_sc); |
79f33912 NA |
620 | status &= ~BD_ENET_TX_STATS; |
621 | status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); | |
622 | ||
4d494cdc FD |
623 | bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; |
624 | dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; | |
41ef84ce | 625 | if (((unsigned long)bufaddr) & fep->tx_align || |
6b7e4008 | 626 | fep->quirks & FEC_QUIRK_SWAP_FRAME) { |
4d494cdc FD |
627 | memcpy(txq->tx_bounce[index], skb->data, hdr_len); |
628 | bufaddr = txq->tx_bounce[index]; | |
79f33912 | 629 | |
6b7e4008 | 630 | if (fep->quirks & FEC_QUIRK_SWAP_FRAME) |
79f33912 NA |
631 | swap_buffer(bufaddr, hdr_len); |
632 | ||
633 | dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, | |
634 | hdr_len, DMA_TO_DEVICE); | |
635 | if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { | |
636 | dev_kfree_skb_any(skb); | |
637 | if (net_ratelimit()) | |
638 | netdev_err(ndev, "Tx DMA memory map failed\n"); | |
639 | return NETDEV_TX_BUSY; | |
640 | } | |
641 | } | |
642 | ||
5cfa3039 JB |
643 | bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); |
644 | bdp->cbd_datlen = cpu_to_fec16(hdr_len); | |
79f33912 NA |
645 | |
646 | if (fep->bufdesc_ex) { | |
6b7e4008 | 647 | if (fep->quirks & FEC_QUIRK_HAS_AVB) |
53bb20d1 | 648 | estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); |
79f33912 NA |
649 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
650 | estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; | |
651 | ebdp->cbd_bdu = 0; | |
5cfa3039 | 652 | ebdp->cbd_esc = cpu_to_fec32(estatus); |
79f33912 NA |
653 | } |
654 | ||
5cfa3039 | 655 | bdp->cbd_sc = cpu_to_fec16(status); |
79f33912 NA |
656 | |
657 | return 0; | |
658 | } | |
659 | ||
4d494cdc FD |
660 | static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, |
661 | struct sk_buff *skb, | |
662 | struct net_device *ndev) | |
79f33912 NA |
663 | { |
664 | struct fec_enet_private *fep = netdev_priv(ndev); | |
665 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
666 | int total_len, data_left; | |
7355f276 | 667 | struct bufdesc *bdp = txq->bd.cur; |
79f33912 NA |
668 | struct tso_t tso; |
669 | unsigned int index = 0; | |
670 | int ret; | |
671 | ||
7355f276 | 672 | if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { |
79f33912 NA |
673 | dev_kfree_skb_any(skb); |
674 | if (net_ratelimit()) | |
675 | netdev_err(ndev, "NOT enough BD for TSO!\n"); | |
676 | return NETDEV_TX_OK; | |
677 | } | |
678 | ||
679 | /* Protocol checksum off-load for TCP and UDP. */ | |
680 | if (fec_enet_clear_csum(skb, ndev)) { | |
681 | dev_kfree_skb_any(skb); | |
682 | return NETDEV_TX_OK; | |
683 | } | |
684 | ||
685 | /* Initialize the TSO handler, and prepare the first payload */ | |
686 | tso_start(skb, &tso); | |
687 | ||
688 | total_len = skb->len - hdr_len; | |
689 | while (total_len > 0) { | |
690 | char *hdr; | |
691 | ||
7355f276 | 692 | index = fec_enet_get_bd_index(bdp, &txq->bd); |
79f33912 NA |
693 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); |
694 | total_len -= data_left; | |
695 | ||
696 | /* prepare packet headers: MAC + IP + TCP */ | |
4d494cdc | 697 | hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; |
79f33912 | 698 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); |
4d494cdc | 699 | ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); |
79f33912 NA |
700 | if (ret) |
701 | goto err_release; | |
702 | ||
703 | while (data_left > 0) { | |
704 | int size; | |
705 | ||
706 | size = min_t(int, tso.size, data_left); | |
7355f276 TK |
707 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
708 | index = fec_enet_get_bd_index(bdp, &txq->bd); | |
4d494cdc FD |
709 | ret = fec_enet_txq_put_data_tso(txq, skb, ndev, |
710 | bdp, index, | |
711 | tso.data, size, | |
712 | size == data_left, | |
79f33912 NA |
713 | total_len == 0); |
714 | if (ret) | |
715 | goto err_release; | |
716 | ||
717 | data_left -= size; | |
718 | tso_build_data(skb, &tso, size); | |
719 | } | |
720 | ||
7355f276 | 721 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
79f33912 NA |
722 | } |
723 | ||
724 | /* Save skb pointer */ | |
4d494cdc | 725 | txq->tx_skbuff[index] = skb; |
79f33912 | 726 | |
79f33912 | 727 | skb_tx_timestamp(skb); |
7355f276 | 728 | txq->bd.cur = bdp; |
79f33912 NA |
729 | |
730 | /* Trigger transmission start */ | |
6b7e4008 | 731 | if (!(fep->quirks & FEC_QUIRK_ERR007885) || |
53bb20d1 TK |
732 | !readl(txq->bd.reg_desc_active) || |
733 | !readl(txq->bd.reg_desc_active) || | |
734 | !readl(txq->bd.reg_desc_active) || | |
735 | !readl(txq->bd.reg_desc_active)) | |
736 | writel(0, txq->bd.reg_desc_active); | |
79f33912 NA |
737 | |
738 | return 0; | |
739 | ||
740 | err_release: | |
741 | /* TODO: Release all used data descriptors for TSO */ | |
742 | return ret; | |
743 | } | |
744 | ||
745 | static netdev_tx_t | |
746 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
747 | { | |
748 | struct fec_enet_private *fep = netdev_priv(ndev); | |
749 | int entries_free; | |
4d494cdc FD |
750 | unsigned short queue; |
751 | struct fec_enet_priv_tx_q *txq; | |
752 | struct netdev_queue *nq; | |
79f33912 NA |
753 | int ret; |
754 | ||
4d494cdc FD |
755 | queue = skb_get_queue_mapping(skb); |
756 | txq = fep->tx_queue[queue]; | |
757 | nq = netdev_get_tx_queue(ndev, queue); | |
758 | ||
79f33912 | 759 | if (skb_is_gso(skb)) |
4d494cdc | 760 | ret = fec_enet_txq_submit_tso(txq, skb, ndev); |
79f33912 | 761 | else |
4d494cdc | 762 | ret = fec_enet_txq_submit_skb(txq, skb, ndev); |
6e909283 NA |
763 | if (ret) |
764 | return ret; | |
61a4427b | 765 | |
7355f276 | 766 | entries_free = fec_enet_get_free_txdesc_num(txq); |
4d494cdc FD |
767 | if (entries_free <= txq->tx_stop_threshold) |
768 | netif_tx_stop_queue(nq); | |
61a4427b NA |
769 | |
770 | return NETDEV_TX_OK; | |
771 | } | |
772 | ||
14109a59 FL |
773 | /* Init RX & TX buffer descriptors |
774 | */ | |
775 | static void fec_enet_bd_init(struct net_device *dev) | |
776 | { | |
777 | struct fec_enet_private *fep = netdev_priv(dev); | |
4d494cdc FD |
778 | struct fec_enet_priv_tx_q *txq; |
779 | struct fec_enet_priv_rx_q *rxq; | |
14109a59 FL |
780 | struct bufdesc *bdp; |
781 | unsigned int i; | |
59d0f746 | 782 | unsigned int q; |
14109a59 | 783 | |
59d0f746 FL |
784 | for (q = 0; q < fep->num_rx_queues; q++) { |
785 | /* Initialize the receive buffer descriptors. */ | |
786 | rxq = fep->rx_queue[q]; | |
7355f276 | 787 | bdp = rxq->bd.base; |
4d494cdc | 788 | |
7355f276 | 789 | for (i = 0; i < rxq->bd.ring_size; i++) { |
14109a59 | 790 | |
59d0f746 FL |
791 | /* Initialize the BD for every fragment in the page. */ |
792 | if (bdp->cbd_bufaddr) | |
5cfa3039 | 793 | bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); |
59d0f746 | 794 | else |
5cfa3039 | 795 | bdp->cbd_sc = cpu_to_fec16(0); |
7355f276 | 796 | bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); |
59d0f746 FL |
797 | } |
798 | ||
799 | /* Set the last buffer to wrap */ | |
7355f276 | 800 | bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); |
5cfa3039 | 801 | bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); |
59d0f746 | 802 | |
7355f276 | 803 | rxq->bd.cur = rxq->bd.base; |
59d0f746 FL |
804 | } |
805 | ||
806 | for (q = 0; q < fep->num_tx_queues; q++) { | |
807 | /* ...and the same for transmit */ | |
808 | txq = fep->tx_queue[q]; | |
7355f276 TK |
809 | bdp = txq->bd.base; |
810 | txq->bd.cur = bdp; | |
59d0f746 | 811 | |
7355f276 | 812 | for (i = 0; i < txq->bd.ring_size; i++) { |
59d0f746 | 813 | /* Initialize the BD for every fragment in the page. */ |
5cfa3039 | 814 | bdp->cbd_sc = cpu_to_fec16(0); |
59d0f746 FL |
815 | if (txq->tx_skbuff[i]) { |
816 | dev_kfree_skb_any(txq->tx_skbuff[i]); | |
817 | txq->tx_skbuff[i] = NULL; | |
818 | } | |
5cfa3039 | 819 | bdp->cbd_bufaddr = cpu_to_fec32(0); |
7355f276 | 820 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
59d0f746 FL |
821 | } |
822 | ||
823 | /* Set the last buffer to wrap */ | |
7355f276 | 824 | bdp = fec_enet_get_prevdesc(bdp, &txq->bd); |
5cfa3039 | 825 | bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); |
59d0f746 | 826 | txq->dirty_tx = bdp; |
14109a59 | 827 | } |
59d0f746 | 828 | } |
14109a59 | 829 | |
ce99d0d3 FL |
830 | static void fec_enet_active_rxring(struct net_device *ndev) |
831 | { | |
832 | struct fec_enet_private *fep = netdev_priv(ndev); | |
833 | int i; | |
834 | ||
835 | for (i = 0; i < fep->num_rx_queues; i++) | |
53bb20d1 | 836 | writel(0, fep->rx_queue[i]->bd.reg_desc_active); |
ce99d0d3 FL |
837 | } |
838 | ||
59d0f746 FL |
839 | static void fec_enet_enable_ring(struct net_device *ndev) |
840 | { | |
841 | struct fec_enet_private *fep = netdev_priv(ndev); | |
842 | struct fec_enet_priv_tx_q *txq; | |
843 | struct fec_enet_priv_rx_q *rxq; | |
844 | int i; | |
14109a59 | 845 | |
59d0f746 FL |
846 | for (i = 0; i < fep->num_rx_queues; i++) { |
847 | rxq = fep->rx_queue[i]; | |
7355f276 | 848 | writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); |
d543a762 | 849 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); |
14109a59 | 850 | |
59d0f746 FL |
851 | /* enable DMA1/2 */ |
852 | if (i) | |
853 | writel(RCMR_MATCHEN | RCMR_CMP(i), | |
854 | fep->hwp + FEC_RCMR(i)); | |
855 | } | |
14109a59 | 856 | |
59d0f746 FL |
857 | for (i = 0; i < fep->num_tx_queues; i++) { |
858 | txq = fep->tx_queue[i]; | |
7355f276 | 859 | writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); |
59d0f746 FL |
860 | |
861 | /* enable DMA1/2 */ | |
862 | if (i) | |
863 | writel(DMA_CLASS_EN | IDLE_SLOPE(i), | |
864 | fep->hwp + FEC_DMA_CFG(i)); | |
14109a59 | 865 | } |
59d0f746 | 866 | } |
14109a59 | 867 | |
59d0f746 FL |
868 | static void fec_enet_reset_skb(struct net_device *ndev) |
869 | { | |
870 | struct fec_enet_private *fep = netdev_priv(ndev); | |
871 | struct fec_enet_priv_tx_q *txq; | |
872 | int i, j; | |
873 | ||
874 | for (i = 0; i < fep->num_tx_queues; i++) { | |
875 | txq = fep->tx_queue[i]; | |
876 | ||
7355f276 | 877 | for (j = 0; j < txq->bd.ring_size; j++) { |
59d0f746 FL |
878 | if (txq->tx_skbuff[j]) { |
879 | dev_kfree_skb_any(txq->tx_skbuff[j]); | |
880 | txq->tx_skbuff[j] = NULL; | |
881 | } | |
882 | } | |
883 | } | |
14109a59 FL |
884 | } |
885 | ||
dbc64a8e RK |
886 | /* |
887 | * This function is called to start or restart the FEC during a link | |
888 | * change, transmit timeout, or to reconfigure the FEC. The network | |
889 | * packet processing for this device must be stopped before this call. | |
45993653 | 890 | */ |
1da177e4 | 891 | static void |
ef83337d | 892 | fec_restart(struct net_device *ndev) |
1da177e4 | 893 | { |
c556167f | 894 | struct fec_enet_private *fep = netdev_priv(ndev); |
4c09eed9 | 895 | u32 val; |
cd1f402c UKK |
896 | u32 temp_mac[2]; |
897 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 898 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 899 | |
106c314c FD |
900 | /* Whack a reset. We should wait for this. |
901 | * For i.MX6SX SOC, enet use AXI bus, we use disable MAC | |
902 | * instead of reset MAC itself. | |
903 | */ | |
6b7e4008 | 904 | if (fep->quirks & FEC_QUIRK_HAS_AVB) { |
106c314c FD |
905 | writel(0, fep->hwp + FEC_ECNTRL); |
906 | } else { | |
907 | writel(1, fep->hwp + FEC_ECNTRL); | |
908 | udelay(10); | |
909 | } | |
1da177e4 | 910 | |
45993653 UKK |
911 | /* |
912 | * enet-mac reset will reset mac address registers too, | |
913 | * so need to reconfigure it. | |
914 | */ | |
6b7e4008 | 915 | if (fep->quirks & FEC_QUIRK_ENET_MAC) { |
45993653 | 916 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); |
5cfa3039 JB |
917 | writel((__force u32)cpu_to_be32(temp_mac[0]), |
918 | fep->hwp + FEC_ADDR_LOW); | |
919 | writel((__force u32)cpu_to_be32(temp_mac[1]), | |
920 | fep->hwp + FEC_ADDR_HIGH); | |
45993653 | 921 | } |
1da177e4 | 922 | |
45993653 | 923 | /* Clear any outstanding interrupt. */ |
e17f7fec | 924 | writel(0xffffffff, fep->hwp + FEC_IEVENT); |
1da177e4 | 925 | |
14109a59 FL |
926 | fec_enet_bd_init(ndev); |
927 | ||
59d0f746 | 928 | fec_enet_enable_ring(ndev); |
45993653 | 929 | |
59d0f746 FL |
930 | /* Reset tx SKB buffers. */ |
931 | fec_enet_reset_skb(ndev); | |
97b72e43 | 932 | |
45993653 | 933 | /* Enable MII mode */ |
ef83337d | 934 | if (fep->full_duplex == DUPLEX_FULL) { |
cd1f402c | 935 | /* FD enable */ |
45993653 UKK |
936 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
937 | } else { | |
cd1f402c UKK |
938 | /* No Rcv on Xmit */ |
939 | rcntl |= 0x02; | |
45993653 UKK |
940 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
941 | } | |
cd1f402c | 942 | |
45993653 UKK |
943 | /* Set MII speed */ |
944 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
945 | ||
d1391930 | 946 | #if !defined(CONFIG_M5272) |
18803495 GU |
947 | if (fep->quirks & FEC_QUIRK_HAS_RACC) { |
948 | /* set RX checksum */ | |
949 | val = readl(fep->hwp + FEC_RACC); | |
950 | if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) | |
951 | val |= FEC_RACC_OPTIONS; | |
952 | else | |
953 | val &= ~FEC_RACC_OPTIONS; | |
954 | writel(val, fep->hwp + FEC_RACC); | |
32867fcc | 955 | writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); |
18803495 | 956 | } |
d1391930 | 957 | #endif |
4c09eed9 | 958 | |
45993653 UKK |
959 | /* |
960 | * The phy interface and speed need to get configured | |
961 | * differently on enet-mac. | |
962 | */ | |
6b7e4008 | 963 | if (fep->quirks & FEC_QUIRK_ENET_MAC) { |
cd1f402c UKK |
964 | /* Enable flow control and length check */ |
965 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 966 | |
230dec61 | 967 | /* RGMII, RMII or MII */ |
e813bb2b MP |
968 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || |
969 | fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || | |
970 | fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || | |
971 | fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
230dec61 SG |
972 | rcntl |= (1 << 6); |
973 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 974 | rcntl |= (1 << 8); |
45993653 | 975 | else |
cd1f402c | 976 | rcntl &= ~(1 << 8); |
45993653 | 977 | |
230dec61 | 978 | /* 1G, 100M or 10M */ |
45f5c327 PR |
979 | if (ndev->phydev) { |
980 | if (ndev->phydev->speed == SPEED_1000) | |
230dec61 | 981 | ecntl |= (1 << 5); |
45f5c327 | 982 | else if (ndev->phydev->speed == SPEED_100) |
230dec61 SG |
983 | rcntl &= ~(1 << 9); |
984 | else | |
985 | rcntl |= (1 << 9); | |
986 | } | |
45993653 UKK |
987 | } else { |
988 | #ifdef FEC_MIIGSK_ENR | |
6b7e4008 | 989 | if (fep->quirks & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 990 | u32 cfgr; |
45993653 UKK |
991 | /* disable the gasket and wait */ |
992 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
993 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
994 | udelay(1); | |
995 | ||
996 | /* | |
997 | * configure the gasket: | |
998 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 999 | * MII, 25 MHz, no loopback, no echo |
45993653 | 1000 | */ |
8d82f219 EB |
1001 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
1002 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
45f5c327 | 1003 | if (ndev->phydev && ndev->phydev->speed == SPEED_10) |
8d82f219 EB |
1004 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; |
1005 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
1006 | |
1007 | /* re-enable the gasket */ | |
1008 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 1009 | } |
45993653 UKK |
1010 | #endif |
1011 | } | |
baa70a5c | 1012 | |
d1391930 | 1013 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
1014 | /* enable pause frame*/ |
1015 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
1016 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
45f5c327 | 1017 | ndev->phydev && ndev->phydev->pause)) { |
baa70a5c FL |
1018 | rcntl |= FEC_ENET_FCE; |
1019 | ||
4c09eed9 | 1020 | /* set FIFO threshold parameter to reduce overrun */ |
baa70a5c FL |
1021 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); |
1022 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
1023 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
1024 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
1025 | ||
1026 | /* OPD */ | |
1027 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
1028 | } else { | |
1029 | rcntl &= ~FEC_ENET_FCE; | |
1030 | } | |
d1391930 | 1031 | #endif /* !defined(CONFIG_M5272) */ |
baa70a5c | 1032 | |
cd1f402c | 1033 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 1034 | |
84fe6182 SW |
1035 | /* Setup multicast filter. */ |
1036 | set_multicast_list(ndev); | |
1037 | #ifndef CONFIG_M5272 | |
1038 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
1039 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
1040 | #endif | |
1041 | ||
6b7e4008 | 1042 | if (fep->quirks & FEC_QUIRK_ENET_MAC) { |
230dec61 SG |
1043 | /* enable ENET endian swap */ |
1044 | ecntl |= (1 << 8); | |
1045 | /* enable ENET store and forward mode */ | |
1046 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
1047 | } | |
1048 | ||
ff43da86 FL |
1049 | if (fep->bufdesc_ex) |
1050 | ecntl |= (1 << 4); | |
6605b730 | 1051 | |
38ae92dc | 1052 | #ifndef CONFIG_M5272 |
b9eef55c JB |
1053 | /* Enable the MIB statistic event counters */ |
1054 | writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); | |
38ae92dc CH |
1055 | #endif |
1056 | ||
45993653 | 1057 | /* And last, enable the transmit and receive processing */ |
230dec61 | 1058 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
ce99d0d3 | 1059 | fec_enet_active_rxring(ndev); |
45993653 | 1060 | |
ff43da86 FL |
1061 | if (fep->bufdesc_ex) |
1062 | fec_ptp_start_cyclecounter(ndev); | |
1063 | ||
45993653 | 1064 | /* Enable interrupts we wish to service */ |
0c5a3aef NA |
1065 | if (fep->link) |
1066 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
1067 | else | |
1068 | writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); | |
d851b47b FD |
1069 | |
1070 | /* Init the interrupt coalescing */ | |
1071 | fec_enet_itr_coal_init(ndev); | |
1072 | ||
45993653 UKK |
1073 | } |
1074 | ||
1075 | static void | |
1076 | fec_stop(struct net_device *ndev) | |
1077 | { | |
1078 | struct fec_enet_private *fep = netdev_priv(ndev); | |
de40ed31 | 1079 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
42431dc2 | 1080 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
de40ed31 | 1081 | u32 val; |
45993653 UKK |
1082 | |
1083 | /* We cannot expect a graceful transmit stop without link !!! */ | |
1084 | if (fep->link) { | |
1085 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
1086 | udelay(10); | |
1087 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
31b7720c | 1088 | netdev_err(ndev, "Graceful transmit stop did not complete!\n"); |
45993653 UKK |
1089 | } |
1090 | ||
106c314c FD |
1091 | /* Whack a reset. We should wait for this. |
1092 | * For i.MX6SX SOC, enet use AXI bus, we use disable MAC | |
1093 | * instead of reset MAC itself. | |
1094 | */ | |
de40ed31 NA |
1095 | if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { |
1096 | if (fep->quirks & FEC_QUIRK_HAS_AVB) { | |
1097 | writel(0, fep->hwp + FEC_ECNTRL); | |
1098 | } else { | |
1099 | writel(1, fep->hwp + FEC_ECNTRL); | |
1100 | udelay(10); | |
1101 | } | |
1102 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
106c314c | 1103 | } else { |
de40ed31 NA |
1104 | writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); |
1105 | val = readl(fep->hwp + FEC_ECNTRL); | |
1106 | val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); | |
1107 | writel(val, fep->hwp + FEC_ECNTRL); | |
1108 | ||
1109 | if (pdata && pdata->sleep_mode_enable) | |
1110 | pdata->sleep_mode_enable(true); | |
106c314c | 1111 | } |
45993653 | 1112 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
230dec61 SG |
1113 | |
1114 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
de40ed31 NA |
1115 | if (fep->quirks & FEC_QUIRK_ENET_MAC && |
1116 | !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { | |
230dec61 | 1117 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
1118 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
1119 | } | |
1da177e4 LT |
1120 | } |
1121 | ||
1122 | ||
45993653 UKK |
1123 | static void |
1124 | fec_timeout(struct net_device *ndev) | |
1125 | { | |
1126 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1127 | ||
344756f6 RK |
1128 | fec_dump(ndev); |
1129 | ||
45993653 UKK |
1130 | ndev->stats.tx_errors++; |
1131 | ||
36cdc743 | 1132 | schedule_work(&fep->tx_timeout_work); |
54309fa6 FL |
1133 | } |
1134 | ||
36cdc743 | 1135 | static void fec_enet_timeout_work(struct work_struct *work) |
54309fa6 FL |
1136 | { |
1137 | struct fec_enet_private *fep = | |
36cdc743 | 1138 | container_of(work, struct fec_enet_private, tx_timeout_work); |
8ce5624f | 1139 | struct net_device *ndev = fep->netdev; |
54309fa6 | 1140 | |
36cdc743 RK |
1141 | rtnl_lock(); |
1142 | if (netif_device_present(ndev) || netif_running(ndev)) { | |
1143 | napi_disable(&fep->napi); | |
1144 | netif_tx_lock_bh(ndev); | |
1145 | fec_restart(ndev); | |
1146 | netif_wake_queue(ndev); | |
1147 | netif_tx_unlock_bh(ndev); | |
1148 | napi_enable(&fep->napi); | |
54309fa6 | 1149 | } |
36cdc743 | 1150 | rtnl_unlock(); |
45993653 UKK |
1151 | } |
1152 | ||
bfd4ecdd RK |
1153 | static void |
1154 | fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, | |
1155 | struct skb_shared_hwtstamps *hwtstamps) | |
1156 | { | |
1157 | unsigned long flags; | |
1158 | u64 ns; | |
1159 | ||
1160 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
1161 | ns = timecounter_cyc2time(&fep->tc, ts); | |
1162 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); | |
1163 | ||
1164 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
1165 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
1166 | } | |
1167 | ||
1da177e4 | 1168 | static void |
4d494cdc | 1169 | fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) |
1da177e4 LT |
1170 | { |
1171 | struct fec_enet_private *fep; | |
a2fe37b6 | 1172 | struct bufdesc *bdp; |
0e702ab3 | 1173 | unsigned short status; |
1da177e4 | 1174 | struct sk_buff *skb; |
4d494cdc FD |
1175 | struct fec_enet_priv_tx_q *txq; |
1176 | struct netdev_queue *nq; | |
de5fb0a0 | 1177 | int index = 0; |
79f33912 | 1178 | int entries_free; |
1da177e4 | 1179 | |
c556167f | 1180 | fep = netdev_priv(ndev); |
4d494cdc FD |
1181 | |
1182 | queue_id = FEC_ENET_GET_QUQUE(queue_id); | |
1183 | ||
1184 | txq = fep->tx_queue[queue_id]; | |
1185 | /* get next bdp of dirty_tx */ | |
1186 | nq = netdev_get_tx_queue(ndev, queue_id); | |
1187 | bdp = txq->dirty_tx; | |
1da177e4 | 1188 | |
de5fb0a0 | 1189 | /* get next bdp of dirty_tx */ |
7355f276 | 1190 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
de5fb0a0 | 1191 | |
7355f276 TK |
1192 | while (bdp != READ_ONCE(txq->bd.cur)) { |
1193 | /* Order the load of bd.cur and cbd_sc */ | |
c4bc44c6 | 1194 | rmb(); |
5cfa3039 | 1195 | status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); |
c4bc44c6 | 1196 | if (status & BD_ENET_TX_READY) |
f0b3fbea SH |
1197 | break; |
1198 | ||
7355f276 | 1199 | index = fec_enet_get_bd_index(bdp, &txq->bd); |
2b995f63 | 1200 | |
a2fe37b6 | 1201 | skb = txq->tx_skbuff[index]; |
2b995f63 | 1202 | txq->tx_skbuff[index] = NULL; |
5cfa3039 JB |
1203 | if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) |
1204 | dma_unmap_single(&fep->pdev->dev, | |
1205 | fec32_to_cpu(bdp->cbd_bufaddr), | |
1206 | fec16_to_cpu(bdp->cbd_datlen), | |
1207 | DMA_TO_DEVICE); | |
1208 | bdp->cbd_bufaddr = cpu_to_fec32(0); | |
7fafe803 TK |
1209 | if (!skb) |
1210 | goto skb_done; | |
de5fb0a0 | 1211 | |
1da177e4 | 1212 | /* Check for errors. */ |
0e702ab3 | 1213 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
1214 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
1215 | BD_ENET_TX_CSL)) { | |
c556167f | 1216 | ndev->stats.tx_errors++; |
0e702ab3 | 1217 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 1218 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 1219 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 1220 | ndev->stats.tx_window_errors++; |
0e702ab3 | 1221 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 1222 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 1223 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 1224 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 1225 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 1226 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 1227 | } else { |
c556167f | 1228 | ndev->stats.tx_packets++; |
6e909283 | 1229 | ndev->stats.tx_bytes += skb->len; |
1da177e4 LT |
1230 | } |
1231 | ||
ff43da86 FL |
1232 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
1233 | fep->bufdesc_ex) { | |
6605b730 | 1234 | struct skb_shared_hwtstamps shhwtstamps; |
ff43da86 | 1235 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 | 1236 | |
5cfa3039 | 1237 | fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); |
6605b730 FL |
1238 | skb_tstamp_tx(skb, &shhwtstamps); |
1239 | } | |
ff43da86 | 1240 | |
1da177e4 LT |
1241 | /* Deferred means some collisions occurred during transmit, |
1242 | * but we eventually sent the packet OK. | |
1243 | */ | |
0e702ab3 | 1244 | if (status & BD_ENET_TX_DEF) |
c556167f | 1245 | ndev->stats.collisions++; |
6aa20a22 | 1246 | |
22f6b860 | 1247 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 1248 | dev_kfree_skb_any(skb); |
7fafe803 | 1249 | skb_done: |
c4bc44c6 KH |
1250 | /* Make sure the update to bdp and tx_skbuff are performed |
1251 | * before dirty_tx | |
1252 | */ | |
1253 | wmb(); | |
4d494cdc | 1254 | txq->dirty_tx = bdp; |
6aa20a22 | 1255 | |
22f6b860 | 1256 | /* Update pointer to next buffer descriptor to be transmitted */ |
7355f276 | 1257 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
6aa20a22 | 1258 | |
22f6b860 | 1259 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 1260 | */ |
79f33912 | 1261 | if (netif_queue_stopped(ndev)) { |
7355f276 | 1262 | entries_free = fec_enet_get_free_txdesc_num(txq); |
4d494cdc FD |
1263 | if (entries_free >= txq->tx_wake_threshold) |
1264 | netif_tx_wake_queue(nq); | |
79f33912 | 1265 | } |
1da177e4 | 1266 | } |
ccea2968 RK |
1267 | |
1268 | /* ERR006538: Keep the transmitter going */ | |
7355f276 | 1269 | if (bdp != txq->bd.cur && |
53bb20d1 TK |
1270 | readl(txq->bd.reg_desc_active) == 0) |
1271 | writel(0, txq->bd.reg_desc_active); | |
4d494cdc FD |
1272 | } |
1273 | ||
1274 | static void | |
1275 | fec_enet_tx(struct net_device *ndev) | |
1276 | { | |
1277 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1278 | u16 queue_id; | |
1279 | /* First process class A queue, then Class B and Best Effort queue */ | |
1280 | for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) { | |
1281 | clear_bit(queue_id, &fep->work_tx); | |
1282 | fec_enet_tx_queue(ndev, queue_id); | |
1283 | } | |
1284 | return; | |
1da177e4 LT |
1285 | } |
1286 | ||
1b7bde6d NA |
1287 | static int |
1288 | fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) | |
1289 | { | |
1290 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1291 | int off; | |
1292 | ||
1293 | off = ((unsigned long)skb->data) & fep->rx_align; | |
1294 | if (off) | |
1295 | skb_reserve(skb, fep->rx_align + 1 - off); | |
1296 | ||
5cfa3039 JB |
1297 | bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); |
1298 | if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { | |
1b7bde6d NA |
1299 | if (net_ratelimit()) |
1300 | netdev_err(ndev, "Rx DMA memory map failed\n"); | |
1301 | return -ENOMEM; | |
1302 | } | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
1307 | static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, | |
1310b544 | 1308 | struct bufdesc *bdp, u32 length, bool swap) |
1b7bde6d NA |
1309 | { |
1310 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1311 | struct sk_buff *new_skb; | |
1312 | ||
1313 | if (length > fep->rx_copybreak) | |
1314 | return false; | |
1315 | ||
1316 | new_skb = netdev_alloc_skb(ndev, length); | |
1317 | if (!new_skb) | |
1318 | return false; | |
1319 | ||
5cfa3039 JB |
1320 | dma_sync_single_for_cpu(&fep->pdev->dev, |
1321 | fec32_to_cpu(bdp->cbd_bufaddr), | |
1b7bde6d NA |
1322 | FEC_ENET_RX_FRSIZE - fep->rx_align, |
1323 | DMA_FROM_DEVICE); | |
1310b544 LW |
1324 | if (!swap) |
1325 | memcpy(new_skb->data, (*skb)->data, length); | |
1326 | else | |
1327 | swap_buffer2(new_skb->data, (*skb)->data, length); | |
1b7bde6d NA |
1328 | *skb = new_skb; |
1329 | ||
1330 | return true; | |
1331 | } | |
1332 | ||
7355f276 | 1333 | /* During a receive, the bd_rx.cur points to the current incoming buffer. |
1da177e4 LT |
1334 | * When we update through the ring, if the next incoming buffer has |
1335 | * not been given to the system, we just set the empty indicator, | |
1336 | * effectively tossing the packet. | |
1337 | */ | |
dc975382 | 1338 | static int |
4d494cdc | 1339 | fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) |
1da177e4 | 1340 | { |
c556167f | 1341 | struct fec_enet_private *fep = netdev_priv(ndev); |
4d494cdc | 1342 | struct fec_enet_priv_rx_q *rxq; |
2e28532f | 1343 | struct bufdesc *bdp; |
0e702ab3 | 1344 | unsigned short status; |
1b7bde6d NA |
1345 | struct sk_buff *skb_new = NULL; |
1346 | struct sk_buff *skb; | |
1da177e4 LT |
1347 | ushort pkt_len; |
1348 | __u8 *data; | |
dc975382 | 1349 | int pkt_received = 0; |
cdffcf1b JB |
1350 | struct bufdesc_ex *ebdp = NULL; |
1351 | bool vlan_packet_rcvd = false; | |
1352 | u16 vlan_tag; | |
d842a31f | 1353 | int index = 0; |
1b7bde6d | 1354 | bool is_copybreak; |
6b7e4008 | 1355 | bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; |
6aa20a22 | 1356 | |
0e702ab3 GU |
1357 | #ifdef CONFIG_M532x |
1358 | flush_cache_all(); | |
6aa20a22 | 1359 | #endif |
4d494cdc FD |
1360 | queue_id = FEC_ENET_GET_QUQUE(queue_id); |
1361 | rxq = fep->rx_queue[queue_id]; | |
1da177e4 | 1362 | |
1da177e4 LT |
1363 | /* First, grab all of the stats for the incoming packet. |
1364 | * These get messed up if we get called due to a busy condition. | |
1365 | */ | |
7355f276 | 1366 | bdp = rxq->bd.cur; |
1da177e4 | 1367 | |
5cfa3039 | 1368 | while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 1369 | |
dc975382 FL |
1370 | if (pkt_received >= budget) |
1371 | break; | |
1372 | pkt_received++; | |
1373 | ||
ed63f1dc | 1374 | writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); |
db3421c1 | 1375 | |
22f6b860 | 1376 | /* Check for errors. */ |
095098e1 | 1377 | status ^= BD_ENET_RX_LAST; |
22f6b860 | 1378 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
095098e1 TK |
1379 | BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | |
1380 | BD_ENET_RX_CL)) { | |
c556167f | 1381 | ndev->stats.rx_errors++; |
095098e1 TK |
1382 | if (status & BD_ENET_RX_OV) { |
1383 | /* FIFO overrun */ | |
1384 | ndev->stats.rx_fifo_errors++; | |
1385 | goto rx_processing_done; | |
1386 | } | |
1387 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | |
1388 | | BD_ENET_RX_LAST)) { | |
22f6b860 | 1389 | /* Frame too long or too short. */ |
c556167f | 1390 | ndev->stats.rx_length_errors++; |
095098e1 TK |
1391 | if (status & BD_ENET_RX_LAST) |
1392 | netdev_err(ndev, "rcv is not +last\n"); | |
22f6b860 | 1393 | } |
22f6b860 | 1394 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 1395 | ndev->stats.rx_crc_errors++; |
095098e1 TK |
1396 | /* Report late collisions as a frame error. */ |
1397 | if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) | |
1398 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
1399 | goto rx_processing_done; |
1400 | } | |
1da177e4 | 1401 | |
22f6b860 | 1402 | /* Process the incoming frame. */ |
c556167f | 1403 | ndev->stats.rx_packets++; |
5cfa3039 | 1404 | pkt_len = fec16_to_cpu(bdp->cbd_datlen); |
c556167f | 1405 | ndev->stats.rx_bytes += pkt_len; |
1da177e4 | 1406 | |
7355f276 | 1407 | index = fec_enet_get_bd_index(bdp, &rxq->bd); |
1b7bde6d | 1408 | skb = rxq->rx_skbuff[index]; |
ccdc4f19 | 1409 | |
1b7bde6d NA |
1410 | /* The packet length includes FCS, but we don't want to |
1411 | * include that when passing upstream as it messes up | |
1412 | * bridging applications. | |
1413 | */ | |
1310b544 LW |
1414 | is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, |
1415 | need_swap); | |
1b7bde6d NA |
1416 | if (!is_copybreak) { |
1417 | skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); | |
1418 | if (unlikely(!skb_new)) { | |
1419 | ndev->stats.rx_dropped++; | |
1420 | goto rx_processing_done; | |
1421 | } | |
5cfa3039 JB |
1422 | dma_unmap_single(&fep->pdev->dev, |
1423 | fec32_to_cpu(bdp->cbd_bufaddr), | |
1b7bde6d NA |
1424 | FEC_ENET_RX_FRSIZE - fep->rx_align, |
1425 | DMA_FROM_DEVICE); | |
1426 | } | |
1427 | ||
1428 | prefetch(skb->data - NET_IP_ALIGN); | |
1429 | skb_put(skb, pkt_len - 4); | |
1430 | data = skb->data; | |
1310b544 | 1431 | if (!is_copybreak && need_swap) |
b5680e0b SG |
1432 | swap_buffer(data, pkt_len); |
1433 | ||
cdffcf1b JB |
1434 | /* Extract the enhanced buffer descriptor */ |
1435 | ebdp = NULL; | |
1436 | if (fep->bufdesc_ex) | |
1437 | ebdp = (struct bufdesc_ex *)bdp; | |
1438 | ||
1439 | /* If this is a VLAN packet remove the VLAN Tag */ | |
1440 | vlan_packet_rcvd = false; | |
1441 | if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
5cfa3039 JB |
1442 | fep->bufdesc_ex && |
1443 | (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { | |
cdffcf1b JB |
1444 | /* Push and remove the vlan tag */ |
1445 | struct vlan_hdr *vlan_header = | |
1446 | (struct vlan_hdr *) (data + ETH_HLEN); | |
1447 | vlan_tag = ntohs(vlan_header->h_vlan_TCI); | |
cdffcf1b JB |
1448 | |
1449 | vlan_packet_rcvd = true; | |
1b7bde6d | 1450 | |
af5cbc98 | 1451 | memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); |
1b7bde6d | 1452 | skb_pull(skb, VLAN_HLEN); |
cdffcf1b JB |
1453 | } |
1454 | ||
1b7bde6d | 1455 | skb->protocol = eth_type_trans(skb, ndev); |
1da177e4 | 1456 | |
1b7bde6d NA |
1457 | /* Get receive timestamp from the skb */ |
1458 | if (fep->hwts_rx_en && fep->bufdesc_ex) | |
5cfa3039 | 1459 | fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), |
1b7bde6d NA |
1460 | skb_hwtstamps(skb)); |
1461 | ||
1462 | if (fep->bufdesc_ex && | |
1463 | (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { | |
5cfa3039 | 1464 | if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { |
1b7bde6d NA |
1465 | /* don't check it */ |
1466 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1467 | } else { | |
1468 | skb_checksum_none_assert(skb); | |
4c09eed9 | 1469 | } |
1b7bde6d | 1470 | } |
4c09eed9 | 1471 | |
1b7bde6d NA |
1472 | /* Handle received VLAN packets */ |
1473 | if (vlan_packet_rcvd) | |
1474 | __vlan_hwaccel_put_tag(skb, | |
1475 | htons(ETH_P_8021Q), | |
1476 | vlan_tag); | |
cdffcf1b | 1477 | |
1b7bde6d NA |
1478 | napi_gro_receive(&fep->napi, skb); |
1479 | ||
1480 | if (is_copybreak) { | |
5cfa3039 JB |
1481 | dma_sync_single_for_device(&fep->pdev->dev, |
1482 | fec32_to_cpu(bdp->cbd_bufaddr), | |
1b7bde6d NA |
1483 | FEC_ENET_RX_FRSIZE - fep->rx_align, |
1484 | DMA_FROM_DEVICE); | |
1485 | } else { | |
1486 | rxq->rx_skbuff[index] = skb_new; | |
1487 | fec_enet_new_rxbdp(ndev, bdp, skb_new); | |
22f6b860 | 1488 | } |
f0b3fbea | 1489 | |
22f6b860 SH |
1490 | rx_processing_done: |
1491 | /* Clear the status flags for this buffer */ | |
1492 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 1493 | |
22f6b860 SH |
1494 | /* Mark the buffer empty */ |
1495 | status |= BD_ENET_RX_EMPTY; | |
6aa20a22 | 1496 | |
ff43da86 FL |
1497 | if (fep->bufdesc_ex) { |
1498 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1499 | ||
5cfa3039 | 1500 | ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); |
ff43da86 FL |
1501 | ebdp->cbd_prot = 0; |
1502 | ebdp->cbd_bdu = 0; | |
1503 | } | |
be293467 TK |
1504 | /* Make sure the updates to rest of the descriptor are |
1505 | * performed before transferring ownership. | |
1506 | */ | |
1507 | wmb(); | |
1508 | bdp->cbd_sc = cpu_to_fec16(status); | |
6605b730 | 1509 | |
22f6b860 | 1510 | /* Update BD pointer to next entry */ |
7355f276 | 1511 | bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); |
36e24e2e | 1512 | |
22f6b860 SH |
1513 | /* Doing this here will keep the FEC running while we process |
1514 | * incoming frames. On a heavily loaded network, we should be | |
1515 | * able to keep up at the expense of system resources. | |
1516 | */ | |
53bb20d1 | 1517 | writel(0, rxq->bd.reg_desc_active); |
22f6b860 | 1518 | } |
7355f276 | 1519 | rxq->bd.cur = bdp; |
4d494cdc FD |
1520 | return pkt_received; |
1521 | } | |
1da177e4 | 1522 | |
4d494cdc FD |
1523 | static int |
1524 | fec_enet_rx(struct net_device *ndev, int budget) | |
1525 | { | |
1526 | int pkt_received = 0; | |
1527 | u16 queue_id; | |
1528 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1529 | ||
1530 | for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) { | |
1c021bb7 UKK |
1531 | int ret; |
1532 | ||
1533 | ret = fec_enet_rx_queue(ndev, | |
4d494cdc | 1534 | budget - pkt_received, queue_id); |
1c021bb7 UKK |
1535 | |
1536 | if (ret < budget - pkt_received) | |
1537 | clear_bit(queue_id, &fep->work_rx); | |
1538 | ||
1539 | pkt_received += ret; | |
4d494cdc | 1540 | } |
dc975382 | 1541 | return pkt_received; |
1da177e4 LT |
1542 | } |
1543 | ||
4d494cdc FD |
1544 | static bool |
1545 | fec_enet_collect_events(struct fec_enet_private *fep, uint int_events) | |
1546 | { | |
1547 | if (int_events == 0) | |
1548 | return false; | |
1549 | ||
1550 | if (int_events & FEC_ENET_RXF) | |
1551 | fep->work_rx |= (1 << 2); | |
ce99d0d3 FL |
1552 | if (int_events & FEC_ENET_RXF_1) |
1553 | fep->work_rx |= (1 << 0); | |
1554 | if (int_events & FEC_ENET_RXF_2) | |
1555 | fep->work_rx |= (1 << 1); | |
4d494cdc FD |
1556 | |
1557 | if (int_events & FEC_ENET_TXF) | |
1558 | fep->work_tx |= (1 << 2); | |
ce99d0d3 FL |
1559 | if (int_events & FEC_ENET_TXF_1) |
1560 | fep->work_tx |= (1 << 0); | |
1561 | if (int_events & FEC_ENET_TXF_2) | |
1562 | fep->work_tx |= (1 << 1); | |
4d494cdc FD |
1563 | |
1564 | return true; | |
1565 | } | |
1566 | ||
45993653 UKK |
1567 | static irqreturn_t |
1568 | fec_enet_interrupt(int irq, void *dev_id) | |
1569 | { | |
1570 | struct net_device *ndev = dev_id; | |
1571 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1572 | uint int_events; | |
1573 | irqreturn_t ret = IRQ_NONE; | |
1574 | ||
7a16807c | 1575 | int_events = readl(fep->hwp + FEC_IEVENT); |
94191fd6 | 1576 | writel(int_events, fep->hwp + FEC_IEVENT); |
4d494cdc | 1577 | fec_enet_collect_events(fep, int_events); |
45993653 | 1578 | |
61615cd2 | 1579 | if ((fep->work_tx || fep->work_rx) && fep->link) { |
7a16807c | 1580 | ret = IRQ_HANDLED; |
dc975382 | 1581 | |
94191fd6 NA |
1582 | if (napi_schedule_prep(&fep->napi)) { |
1583 | /* Disable the NAPI interrupts */ | |
80dc6a9f | 1584 | writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK); |
94191fd6 NA |
1585 | __napi_schedule(&fep->napi); |
1586 | } | |
7a16807c | 1587 | } |
45993653 | 1588 | |
7a16807c RK |
1589 | if (int_events & FEC_ENET_MII) { |
1590 | ret = IRQ_HANDLED; | |
1591 | complete(&fep->mdio_done); | |
1592 | } | |
45993653 | 1593 | |
81f35ffd PZ |
1594 | if (fep->ptp_clock) |
1595 | fec_ptp_check_pps_event(fep); | |
278d2404 | 1596 | |
45993653 UKK |
1597 | return ret; |
1598 | } | |
1599 | ||
dc975382 FL |
1600 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
1601 | { | |
1602 | struct net_device *ndev = napi->dev; | |
dc975382 | 1603 | struct fec_enet_private *fep = netdev_priv(ndev); |
7a16807c RK |
1604 | int pkts; |
1605 | ||
7a16807c | 1606 | pkts = fec_enet_rx(ndev, budget); |
45993653 | 1607 | |
de5fb0a0 FL |
1608 | fec_enet_tx(ndev); |
1609 | ||
dc975382 FL |
1610 | if (pkts < budget) { |
1611 | napi_complete(napi); | |
1612 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
1613 | } | |
1614 | return pkts; | |
1615 | } | |
45993653 | 1616 | |
e6b043d5 | 1617 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 1618 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 1619 | { |
c556167f | 1620 | struct fec_enet_private *fep = netdev_priv(ndev); |
94660ba0 | 1621 | struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); |
e6b043d5 | 1622 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 1623 | |
49da97dc SG |
1624 | /* |
1625 | * try to get mac address in following order: | |
1626 | * | |
1627 | * 1) module parameter via kernel command line in form | |
1628 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
1629 | */ | |
1630 | iap = macaddr; | |
1631 | ||
ca2cc333 SG |
1632 | /* |
1633 | * 2) from device tree data | |
1634 | */ | |
1635 | if (!is_valid_ether_addr(iap)) { | |
1636 | struct device_node *np = fep->pdev->dev.of_node; | |
1637 | if (np) { | |
1638 | const char *mac = of_get_mac_address(np); | |
1639 | if (mac) | |
1640 | iap = (unsigned char *) mac; | |
1641 | } | |
1642 | } | |
ca2cc333 | 1643 | |
49da97dc | 1644 | /* |
ca2cc333 | 1645 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
1646 | */ |
1647 | if (!is_valid_ether_addr(iap)) { | |
1648 | #ifdef CONFIG_M5272 | |
1649 | if (FEC_FLASHMAC) | |
1650 | iap = (unsigned char *)FEC_FLASHMAC; | |
1651 | #else | |
1652 | if (pdata) | |
589efdc7 | 1653 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
1654 | #endif |
1655 | } | |
1656 | ||
1657 | /* | |
ca2cc333 | 1658 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
1659 | */ |
1660 | if (!is_valid_ether_addr(iap)) { | |
7d7628f3 DC |
1661 | *((__be32 *) &tmpaddr[0]) = |
1662 | cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); | |
1663 | *((__be16 *) &tmpaddr[4]) = | |
1664 | cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 1665 | iap = &tmpaddr[0]; |
1da177e4 LT |
1666 | } |
1667 | ||
ff5b2fab LS |
1668 | /* |
1669 | * 5) random mac address | |
1670 | */ | |
1671 | if (!is_valid_ether_addr(iap)) { | |
1672 | /* Report it and use a random ethernet address instead */ | |
1673 | netdev_err(ndev, "Invalid MAC address: %pM\n", iap); | |
1674 | eth_hw_addr_random(ndev); | |
1675 | netdev_info(ndev, "Using random MAC address: %pM\n", | |
1676 | ndev->dev_addr); | |
1677 | return; | |
1678 | } | |
1679 | ||
c556167f | 1680 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 1681 | |
49da97dc SG |
1682 | /* Adjust MAC if using macaddr */ |
1683 | if (iap == macaddr) | |
43af940c | 1684 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
1685 | } |
1686 | ||
e6b043d5 | 1687 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 1688 | |
e6b043d5 BW |
1689 | /* |
1690 | * Phy section | |
1691 | */ | |
c556167f | 1692 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 1693 | { |
c556167f | 1694 | struct fec_enet_private *fep = netdev_priv(ndev); |
45f5c327 | 1695 | struct phy_device *phy_dev = ndev->phydev; |
e6b043d5 | 1696 | int status_change = 0; |
1da177e4 | 1697 | |
e6b043d5 BW |
1698 | /* Prevent a state halted on mii error */ |
1699 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
1700 | phy_dev->state = PHY_RESUMING; | |
54309fa6 | 1701 | return; |
e6b043d5 | 1702 | } |
1da177e4 | 1703 | |
8ce5624f RK |
1704 | /* |
1705 | * If the netdev is down, or is going down, we're not interested | |
1706 | * in link state events, so just mark our idea of the link as down | |
1707 | * and ignore the event. | |
1708 | */ | |
1709 | if (!netif_running(ndev) || !netif_device_present(ndev)) { | |
1710 | fep->link = 0; | |
1711 | } else if (phy_dev->link) { | |
d97e7497 | 1712 | if (!fep->link) { |
6ea0722f | 1713 | fep->link = phy_dev->link; |
e6b043d5 BW |
1714 | status_change = 1; |
1715 | } | |
1da177e4 | 1716 | |
ef83337d RK |
1717 | if (fep->full_duplex != phy_dev->duplex) { |
1718 | fep->full_duplex = phy_dev->duplex; | |
d97e7497 | 1719 | status_change = 1; |
ef83337d | 1720 | } |
d97e7497 LS |
1721 | |
1722 | if (phy_dev->speed != fep->speed) { | |
1723 | fep->speed = phy_dev->speed; | |
1724 | status_change = 1; | |
1725 | } | |
1726 | ||
1727 | /* if any of the above changed restart the FEC */ | |
dbc64a8e | 1728 | if (status_change) { |
dbc64a8e | 1729 | napi_disable(&fep->napi); |
dbc64a8e | 1730 | netif_tx_lock_bh(ndev); |
ef83337d | 1731 | fec_restart(ndev); |
dbc64a8e | 1732 | netif_wake_queue(ndev); |
6af42d42 | 1733 | netif_tx_unlock_bh(ndev); |
dbc64a8e | 1734 | napi_enable(&fep->napi); |
dbc64a8e | 1735 | } |
d97e7497 LS |
1736 | } else { |
1737 | if (fep->link) { | |
f208ce10 RK |
1738 | napi_disable(&fep->napi); |
1739 | netif_tx_lock_bh(ndev); | |
c556167f | 1740 | fec_stop(ndev); |
f208ce10 RK |
1741 | netif_tx_unlock_bh(ndev); |
1742 | napi_enable(&fep->napi); | |
8d7ed0f0 | 1743 | fep->link = phy_dev->link; |
d97e7497 LS |
1744 | status_change = 1; |
1745 | } | |
1da177e4 | 1746 | } |
6aa20a22 | 1747 | |
e6b043d5 BW |
1748 | if (status_change) |
1749 | phy_print_status(phy_dev); | |
1750 | } | |
1da177e4 | 1751 | |
e6b043d5 | 1752 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 1753 | { |
e6b043d5 | 1754 | struct fec_enet_private *fep = bus->priv; |
8fff755e | 1755 | struct device *dev = &fep->pdev->dev; |
97b72e43 | 1756 | unsigned long time_left; |
8fff755e AL |
1757 | int ret = 0; |
1758 | ||
1759 | ret = pm_runtime_get_sync(dev); | |
b0c6ce24 | 1760 | if (ret < 0) |
8fff755e | 1761 | return ret; |
1da177e4 | 1762 | |
e6b043d5 | 1763 | fep->mii_timeout = 0; |
aac27c7a | 1764 | reinit_completion(&fep->mdio_done); |
e6b043d5 BW |
1765 | |
1766 | /* start a read op */ | |
1767 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
1768 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
1769 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
1770 | ||
1771 | /* wait for end of transfer */ | |
97b72e43 BS |
1772 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1773 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1774 | if (time_left == 0) { | |
1775 | fep->mii_timeout = 1; | |
31b7720c | 1776 | netdev_err(fep->netdev, "MDIO read timeout\n"); |
8fff755e AL |
1777 | ret = -ETIMEDOUT; |
1778 | goto out; | |
1da177e4 | 1779 | } |
1da177e4 | 1780 | |
8fff755e AL |
1781 | ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); |
1782 | ||
1783 | out: | |
1784 | pm_runtime_mark_last_busy(dev); | |
1785 | pm_runtime_put_autosuspend(dev); | |
1786 | ||
1787 | return ret; | |
7dd6a2aa | 1788 | } |
6aa20a22 | 1789 | |
e6b043d5 BW |
1790 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
1791 | u16 value) | |
1da177e4 | 1792 | { |
e6b043d5 | 1793 | struct fec_enet_private *fep = bus->priv; |
8fff755e | 1794 | struct device *dev = &fep->pdev->dev; |
97b72e43 | 1795 | unsigned long time_left; |
42ea4457 | 1796 | int ret; |
8fff755e AL |
1797 | |
1798 | ret = pm_runtime_get_sync(dev); | |
b0c6ce24 | 1799 | if (ret < 0) |
8fff755e | 1800 | return ret; |
42ea4457 MS |
1801 | else |
1802 | ret = 0; | |
1da177e4 | 1803 | |
e6b043d5 | 1804 | fep->mii_timeout = 0; |
aac27c7a | 1805 | reinit_completion(&fep->mdio_done); |
1da177e4 | 1806 | |
862f0982 SG |
1807 | /* start a write op */ |
1808 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1809 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1810 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1811 | fep->hwp + FEC_MII_DATA); | |
1812 | ||
1813 | /* wait for end of transfer */ | |
97b72e43 BS |
1814 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1815 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1816 | if (time_left == 0) { | |
1817 | fep->mii_timeout = 1; | |
31b7720c | 1818 | netdev_err(fep->netdev, "MDIO write timeout\n"); |
8fff755e | 1819 | ret = -ETIMEDOUT; |
e6b043d5 | 1820 | } |
1da177e4 | 1821 | |
8fff755e AL |
1822 | pm_runtime_mark_last_busy(dev); |
1823 | pm_runtime_put_autosuspend(dev); | |
1824 | ||
1825 | return ret; | |
e6b043d5 | 1826 | } |
1da177e4 | 1827 | |
e8fcfcd5 NA |
1828 | static int fec_enet_clk_enable(struct net_device *ndev, bool enable) |
1829 | { | |
1830 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1831 | int ret; | |
1832 | ||
1833 | if (enable) { | |
1834 | ret = clk_prepare_enable(fep->clk_ahb); | |
1835 | if (ret) | |
1836 | return ret; | |
e8fcfcd5 NA |
1837 | if (fep->clk_enet_out) { |
1838 | ret = clk_prepare_enable(fep->clk_enet_out); | |
1839 | if (ret) | |
1840 | goto failed_clk_enet_out; | |
1841 | } | |
1842 | if (fep->clk_ptp) { | |
91c0d987 | 1843 | mutex_lock(&fep->ptp_clk_mutex); |
e8fcfcd5 | 1844 | ret = clk_prepare_enable(fep->clk_ptp); |
91c0d987 NA |
1845 | if (ret) { |
1846 | mutex_unlock(&fep->ptp_clk_mutex); | |
e8fcfcd5 | 1847 | goto failed_clk_ptp; |
91c0d987 NA |
1848 | } else { |
1849 | fep->ptp_clk_on = true; | |
1850 | } | |
1851 | mutex_unlock(&fep->ptp_clk_mutex); | |
e8fcfcd5 | 1852 | } |
9b5330ed FD |
1853 | if (fep->clk_ref) { |
1854 | ret = clk_prepare_enable(fep->clk_ref); | |
1855 | if (ret) | |
1856 | goto failed_clk_ref; | |
1857 | } | |
e8fcfcd5 NA |
1858 | } else { |
1859 | clk_disable_unprepare(fep->clk_ahb); | |
e8fcfcd5 NA |
1860 | if (fep->clk_enet_out) |
1861 | clk_disable_unprepare(fep->clk_enet_out); | |
91c0d987 NA |
1862 | if (fep->clk_ptp) { |
1863 | mutex_lock(&fep->ptp_clk_mutex); | |
e8fcfcd5 | 1864 | clk_disable_unprepare(fep->clk_ptp); |
91c0d987 NA |
1865 | fep->ptp_clk_on = false; |
1866 | mutex_unlock(&fep->ptp_clk_mutex); | |
1867 | } | |
9b5330ed FD |
1868 | if (fep->clk_ref) |
1869 | clk_disable_unprepare(fep->clk_ref); | |
e8fcfcd5 NA |
1870 | } |
1871 | ||
1872 | return 0; | |
9b5330ed FD |
1873 | |
1874 | failed_clk_ref: | |
1875 | if (fep->clk_ref) | |
1876 | clk_disable_unprepare(fep->clk_ref); | |
e8fcfcd5 NA |
1877 | failed_clk_ptp: |
1878 | if (fep->clk_enet_out) | |
1879 | clk_disable_unprepare(fep->clk_enet_out); | |
1880 | failed_clk_enet_out: | |
e8fcfcd5 NA |
1881 | clk_disable_unprepare(fep->clk_ahb); |
1882 | ||
1883 | return ret; | |
1884 | } | |
1885 | ||
c556167f | 1886 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1887 | { |
c556167f | 1888 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1889 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1890 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1891 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1892 | int phy_id; | |
43af940c | 1893 | int dev_id = fep->dev_id; |
562d2f8c | 1894 | |
407066f8 UKK |
1895 | if (fep->phy_node) { |
1896 | phy_dev = of_phy_connect(ndev, fep->phy_node, | |
1897 | &fec_enet_adjust_link, 0, | |
1898 | fep->phy_interface); | |
213a9922 NA |
1899 | if (!phy_dev) |
1900 | return -ENODEV; | |
407066f8 UKK |
1901 | } else { |
1902 | /* check for attached phy */ | |
1903 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
7f854420 | 1904 | if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) |
407066f8 UKK |
1905 | continue; |
1906 | if (dev_id--) | |
1907 | continue; | |
949bdd20 | 1908 | strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
407066f8 UKK |
1909 | break; |
1910 | } | |
1da177e4 | 1911 | |
407066f8 UKK |
1912 | if (phy_id >= PHY_MAX_ADDR) { |
1913 | netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); | |
949bdd20 | 1914 | strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
407066f8 UKK |
1915 | phy_id = 0; |
1916 | } | |
1917 | ||
1918 | snprintf(phy_name, sizeof(phy_name), | |
1919 | PHY_ID_FMT, mdio_bus_id, phy_id); | |
1920 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, | |
1921 | fep->phy_interface); | |
6fcc040f GU |
1922 | } |
1923 | ||
6fcc040f | 1924 | if (IS_ERR(phy_dev)) { |
31b7720c | 1925 | netdev_err(ndev, "could not attach to PHY\n"); |
6fcc040f | 1926 | return PTR_ERR(phy_dev); |
e6b043d5 | 1927 | } |
1da177e4 | 1928 | |
e6b043d5 | 1929 | /* mask with MAC supported features */ |
6b7e4008 | 1930 | if (fep->quirks & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1931 | phy_dev->supported &= PHY_GBIT_FEATURES; |
b44592ff | 1932 | phy_dev->supported &= ~SUPPORTED_1000baseT_Half; |
d1391930 | 1933 | #if !defined(CONFIG_M5272) |
baa70a5c | 1934 | phy_dev->supported |= SUPPORTED_Pause; |
d1391930 | 1935 | #endif |
baa70a5c | 1936 | } |
230dec61 SG |
1937 | else |
1938 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1939 | ||
e6b043d5 | 1940 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1941 | |
e6b043d5 BW |
1942 | fep->link = 0; |
1943 | fep->full_duplex = 0; | |
1da177e4 | 1944 | |
2220943a | 1945 | phy_attached_info(phy_dev); |
418bd0d4 | 1946 | |
e6b043d5 | 1947 | return 0; |
1da177e4 LT |
1948 | } |
1949 | ||
e6b043d5 | 1950 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1951 | { |
b5680e0b | 1952 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1953 | struct net_device *ndev = platform_get_drvdata(pdev); |
1954 | struct fec_enet_private *fep = netdev_priv(ndev); | |
407066f8 | 1955 | struct device_node *node; |
e7f4dc35 | 1956 | int err = -ENXIO; |
63c60732 | 1957 | u32 mii_speed, holdtime; |
6b265293 | 1958 | |
b5680e0b | 1959 | /* |
3d125f9c | 1960 | * The i.MX28 dual fec interfaces are not equal. |
b5680e0b SG |
1961 | * Here are the differences: |
1962 | * | |
1963 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1964 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1965 | * - external phys can only be configured by fec0 | |
1966 | * | |
1967 | * That is to say fec1 can not work independently. It only works | |
1968 | * when fec0 is working. The reason behind this design is that the | |
1969 | * second interface is added primarily for Switch mode. | |
1970 | * | |
1971 | * Because of the last point above, both phys are attached on fec0 | |
1972 | * mdio interface in board design, and need to be configured by | |
1973 | * fec0 mii_bus. | |
1974 | */ | |
3d125f9c | 1975 | if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { |
b5680e0b | 1976 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1977 | if (mii_cnt && fec0_mii_bus) { |
1978 | fep->mii_bus = fec0_mii_bus; | |
1979 | mii_cnt++; | |
1980 | return 0; | |
1981 | } | |
1982 | return -ENOENT; | |
b5680e0b SG |
1983 | } |
1984 | ||
e6b043d5 | 1985 | fep->mii_timeout = 0; |
1da177e4 | 1986 | |
e6b043d5 BW |
1987 | /* |
1988 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1989 | * |
1990 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1991 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1992 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1993 | * document. | |
e6b043d5 | 1994 | */ |
63c60732 | 1995 | mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000); |
6b7e4008 | 1996 | if (fep->quirks & FEC_QUIRK_ENET_MAC) |
63c60732 UKK |
1997 | mii_speed--; |
1998 | if (mii_speed > 63) { | |
1999 | dev_err(&pdev->dev, | |
2000 | "fec clock (%lu) to fast to get right mii speed\n", | |
2001 | clk_get_rate(fep->clk_ipg)); | |
2002 | err = -EINVAL; | |
2003 | goto err_out; | |
2004 | } | |
2005 | ||
2006 | /* | |
2007 | * The i.MX28 and i.MX6 types have another filed in the MSCR (aka | |
2008 | * MII_SPEED) register that defines the MDIO output hold time. Earlier | |
2009 | * versions are RAZ there, so just ignore the difference and write the | |
2010 | * register always. | |
2011 | * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. | |
2012 | * HOLDTIME + 1 is the number of clk cycles the fec is holding the | |
2013 | * output. | |
2014 | * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). | |
2015 | * Given that ceil(clkrate / 5000000) <= 64, the calculation for | |
2016 | * holdtime cannot result in a value greater than 3. | |
2017 | */ | |
2018 | holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; | |
2019 | ||
2020 | fep->phy_speed = mii_speed << 1 | holdtime << 8; | |
2021 | ||
e6b043d5 | 2022 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 2023 | |
e6b043d5 BW |
2024 | fep->mii_bus = mdiobus_alloc(); |
2025 | if (fep->mii_bus == NULL) { | |
2026 | err = -ENOMEM; | |
2027 | goto err_out; | |
1da177e4 LT |
2028 | } |
2029 | ||
e6b043d5 BW |
2030 | fep->mii_bus->name = "fec_enet_mii_bus"; |
2031 | fep->mii_bus->read = fec_enet_mdio_read; | |
2032 | fep->mii_bus->write = fec_enet_mdio_write; | |
391420f7 FF |
2033 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
2034 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
2035 | fep->mii_bus->priv = fep; |
2036 | fep->mii_bus->parent = &pdev->dev; | |
2037 | ||
407066f8 UKK |
2038 | node = of_get_child_by_name(pdev->dev.of_node, "mdio"); |
2039 | if (node) { | |
2040 | err = of_mdiobus_register(fep->mii_bus, node); | |
2041 | of_node_put(node); | |
2042 | } else { | |
2043 | err = mdiobus_register(fep->mii_bus); | |
2044 | } | |
2045 | ||
2046 | if (err) | |
e7f4dc35 | 2047 | goto err_out_free_mdiobus; |
1da177e4 | 2048 | |
e163cc97 LW |
2049 | mii_cnt++; |
2050 | ||
b5680e0b | 2051 | /* save fec0 mii_bus */ |
3d125f9c | 2052 | if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) |
b5680e0b SG |
2053 | fec0_mii_bus = fep->mii_bus; |
2054 | ||
e6b043d5 | 2055 | return 0; |
1da177e4 | 2056 | |
e6b043d5 BW |
2057 | err_out_free_mdiobus: |
2058 | mdiobus_free(fep->mii_bus); | |
2059 | err_out: | |
2060 | return err; | |
1da177e4 LT |
2061 | } |
2062 | ||
e6b043d5 | 2063 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 2064 | { |
e163cc97 LW |
2065 | if (--mii_cnt == 0) { |
2066 | mdiobus_unregister(fep->mii_bus); | |
e163cc97 LW |
2067 | mdiobus_free(fep->mii_bus); |
2068 | } | |
1da177e4 LT |
2069 | } |
2070 | ||
c556167f | 2071 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 2072 | struct ethtool_drvinfo *info) |
1da177e4 | 2073 | { |
c556167f | 2074 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 2075 | |
7826d43f JP |
2076 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
2077 | sizeof(info->driver)); | |
2078 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
2079 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
2080 | } |
2081 | ||
db65f35f PR |
2082 | static int fec_enet_get_regs_len(struct net_device *ndev) |
2083 | { | |
2084 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2085 | struct resource *r; | |
2086 | int s = 0; | |
2087 | ||
2088 | r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); | |
2089 | if (r) | |
2090 | s = resource_size(r); | |
2091 | ||
2092 | return s; | |
2093 | } | |
2094 | ||
2095 | /* List of registers that can be safety be read to dump them with ethtool */ | |
2096 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ | |
05f3b50e | 2097 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
db65f35f PR |
2098 | static u32 fec_enet_register_offset[] = { |
2099 | FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, | |
2100 | FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, | |
2101 | FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, | |
2102 | FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, | |
2103 | FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, | |
2104 | FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, | |
2105 | FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, | |
2106 | FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, | |
2107 | FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, | |
2108 | FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, | |
2109 | FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, | |
2110 | FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, | |
2111 | RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, | |
2112 | RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, | |
2113 | RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, | |
2114 | RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, | |
2115 | RMON_T_P_GTE2048, RMON_T_OCTETS, | |
2116 | IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, | |
2117 | IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, | |
2118 | IEEE_T_FDXFC, IEEE_T_OCTETS_OK, | |
2119 | RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, | |
2120 | RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, | |
2121 | RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, | |
2122 | RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, | |
2123 | RMON_R_P_GTE2048, RMON_R_OCTETS, | |
2124 | IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, | |
2125 | IEEE_R_FDXFC, IEEE_R_OCTETS_OK | |
2126 | }; | |
2127 | #else | |
2128 | static u32 fec_enet_register_offset[] = { | |
2129 | FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, | |
2130 | FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, | |
2131 | FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, | |
2132 | FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, | |
2133 | FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, | |
2134 | FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, | |
2135 | FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, | |
2136 | FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, | |
2137 | FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 | |
2138 | }; | |
2139 | #endif | |
2140 | ||
2141 | static void fec_enet_get_regs(struct net_device *ndev, | |
2142 | struct ethtool_regs *regs, void *regbuf) | |
2143 | { | |
2144 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2145 | u32 __iomem *theregs = (u32 __iomem *)fep->hwp; | |
2146 | u32 *buf = (u32 *)regbuf; | |
2147 | u32 i, off; | |
2148 | ||
2149 | memset(buf, 0, regs->len); | |
2150 | ||
2151 | for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { | |
2152 | off = fec_enet_register_offset[i] / 4; | |
2153 | buf[off] = readl(&theregs[off]); | |
2154 | } | |
2155 | } | |
2156 | ||
5ebae489 FL |
2157 | static int fec_enet_get_ts_info(struct net_device *ndev, |
2158 | struct ethtool_ts_info *info) | |
2159 | { | |
2160 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2161 | ||
2162 | if (fep->bufdesc_ex) { | |
2163 | ||
2164 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
2165 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
2166 | SOF_TIMESTAMPING_SOFTWARE | | |
2167 | SOF_TIMESTAMPING_TX_HARDWARE | | |
2168 | SOF_TIMESTAMPING_RX_HARDWARE | | |
2169 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
2170 | if (fep->ptp_clock) | |
2171 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
2172 | else | |
2173 | info->phc_index = -1; | |
2174 | ||
2175 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
2176 | (1 << HWTSTAMP_TX_ON); | |
2177 | ||
2178 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
2179 | (1 << HWTSTAMP_FILTER_ALL); | |
2180 | return 0; | |
2181 | } else { | |
2182 | return ethtool_op_get_ts_info(ndev, info); | |
2183 | } | |
2184 | } | |
2185 | ||
d1391930 GR |
2186 | #if !defined(CONFIG_M5272) |
2187 | ||
baa70a5c FL |
2188 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
2189 | struct ethtool_pauseparam *pause) | |
2190 | { | |
2191 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2192 | ||
2193 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
2194 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
2195 | pause->rx_pause = pause->tx_pause; | |
2196 | } | |
2197 | ||
2198 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
2199 | struct ethtool_pauseparam *pause) | |
2200 | { | |
2201 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2202 | ||
45f5c327 | 2203 | if (!ndev->phydev) |
0b146ca8 RK |
2204 | return -ENODEV; |
2205 | ||
baa70a5c FL |
2206 | if (pause->tx_pause != pause->rx_pause) { |
2207 | netdev_info(ndev, | |
2208 | "hardware only support enable/disable both tx and rx"); | |
2209 | return -EINVAL; | |
2210 | } | |
2211 | ||
2212 | fep->pause_flag = 0; | |
2213 | ||
2214 | /* tx pause must be same as rx pause */ | |
2215 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
2216 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
2217 | ||
2218 | if (pause->rx_pause || pause->autoneg) { | |
45f5c327 PR |
2219 | ndev->phydev->supported |= ADVERTISED_Pause; |
2220 | ndev->phydev->advertising |= ADVERTISED_Pause; | |
baa70a5c | 2221 | } else { |
45f5c327 PR |
2222 | ndev->phydev->supported &= ~ADVERTISED_Pause; |
2223 | ndev->phydev->advertising &= ~ADVERTISED_Pause; | |
baa70a5c FL |
2224 | } |
2225 | ||
2226 | if (pause->autoneg) { | |
2227 | if (netif_running(ndev)) | |
2228 | fec_stop(ndev); | |
45f5c327 | 2229 | phy_start_aneg(ndev->phydev); |
baa70a5c | 2230 | } |
dbc64a8e | 2231 | if (netif_running(ndev)) { |
dbc64a8e | 2232 | napi_disable(&fep->napi); |
dbc64a8e | 2233 | netif_tx_lock_bh(ndev); |
ef83337d | 2234 | fec_restart(ndev); |
dbc64a8e | 2235 | netif_wake_queue(ndev); |
6af42d42 | 2236 | netif_tx_unlock_bh(ndev); |
dbc64a8e | 2237 | napi_enable(&fep->napi); |
dbc64a8e | 2238 | } |
baa70a5c FL |
2239 | |
2240 | return 0; | |
2241 | } | |
2242 | ||
38ae92dc CH |
2243 | static const struct fec_stat { |
2244 | char name[ETH_GSTRING_LEN]; | |
2245 | u16 offset; | |
2246 | } fec_stats[] = { | |
2247 | /* RMON TX */ | |
2248 | { "tx_dropped", RMON_T_DROP }, | |
2249 | { "tx_packets", RMON_T_PACKETS }, | |
2250 | { "tx_broadcast", RMON_T_BC_PKT }, | |
2251 | { "tx_multicast", RMON_T_MC_PKT }, | |
2252 | { "tx_crc_errors", RMON_T_CRC_ALIGN }, | |
2253 | { "tx_undersize", RMON_T_UNDERSIZE }, | |
2254 | { "tx_oversize", RMON_T_OVERSIZE }, | |
2255 | { "tx_fragment", RMON_T_FRAG }, | |
2256 | { "tx_jabber", RMON_T_JAB }, | |
2257 | { "tx_collision", RMON_T_COL }, | |
2258 | { "tx_64byte", RMON_T_P64 }, | |
2259 | { "tx_65to127byte", RMON_T_P65TO127 }, | |
2260 | { "tx_128to255byte", RMON_T_P128TO255 }, | |
2261 | { "tx_256to511byte", RMON_T_P256TO511 }, | |
2262 | { "tx_512to1023byte", RMON_T_P512TO1023 }, | |
2263 | { "tx_1024to2047byte", RMON_T_P1024TO2047 }, | |
2264 | { "tx_GTE2048byte", RMON_T_P_GTE2048 }, | |
2265 | { "tx_octets", RMON_T_OCTETS }, | |
2266 | ||
2267 | /* IEEE TX */ | |
2268 | { "IEEE_tx_drop", IEEE_T_DROP }, | |
2269 | { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, | |
2270 | { "IEEE_tx_1col", IEEE_T_1COL }, | |
2271 | { "IEEE_tx_mcol", IEEE_T_MCOL }, | |
2272 | { "IEEE_tx_def", IEEE_T_DEF }, | |
2273 | { "IEEE_tx_lcol", IEEE_T_LCOL }, | |
2274 | { "IEEE_tx_excol", IEEE_T_EXCOL }, | |
2275 | { "IEEE_tx_macerr", IEEE_T_MACERR }, | |
2276 | { "IEEE_tx_cserr", IEEE_T_CSERR }, | |
2277 | { "IEEE_tx_sqe", IEEE_T_SQE }, | |
2278 | { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, | |
2279 | { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, | |
2280 | ||
2281 | /* RMON RX */ | |
2282 | { "rx_packets", RMON_R_PACKETS }, | |
2283 | { "rx_broadcast", RMON_R_BC_PKT }, | |
2284 | { "rx_multicast", RMON_R_MC_PKT }, | |
2285 | { "rx_crc_errors", RMON_R_CRC_ALIGN }, | |
2286 | { "rx_undersize", RMON_R_UNDERSIZE }, | |
2287 | { "rx_oversize", RMON_R_OVERSIZE }, | |
2288 | { "rx_fragment", RMON_R_FRAG }, | |
2289 | { "rx_jabber", RMON_R_JAB }, | |
2290 | { "rx_64byte", RMON_R_P64 }, | |
2291 | { "rx_65to127byte", RMON_R_P65TO127 }, | |
2292 | { "rx_128to255byte", RMON_R_P128TO255 }, | |
2293 | { "rx_256to511byte", RMON_R_P256TO511 }, | |
2294 | { "rx_512to1023byte", RMON_R_P512TO1023 }, | |
2295 | { "rx_1024to2047byte", RMON_R_P1024TO2047 }, | |
2296 | { "rx_GTE2048byte", RMON_R_P_GTE2048 }, | |
2297 | { "rx_octets", RMON_R_OCTETS }, | |
2298 | ||
2299 | /* IEEE RX */ | |
2300 | { "IEEE_rx_drop", IEEE_R_DROP }, | |
2301 | { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, | |
2302 | { "IEEE_rx_crc", IEEE_R_CRC }, | |
2303 | { "IEEE_rx_align", IEEE_R_ALIGN }, | |
2304 | { "IEEE_rx_macerr", IEEE_R_MACERR }, | |
2305 | { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, | |
2306 | { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, | |
2307 | }; | |
2308 | ||
2309 | static void fec_enet_get_ethtool_stats(struct net_device *dev, | |
2310 | struct ethtool_stats *stats, u64 *data) | |
2311 | { | |
2312 | struct fec_enet_private *fep = netdev_priv(dev); | |
2313 | int i; | |
2314 | ||
2315 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
2316 | data[i] = readl(fep->hwp + fec_stats[i].offset); | |
2317 | } | |
2318 | ||
2319 | static void fec_enet_get_strings(struct net_device *netdev, | |
2320 | u32 stringset, u8 *data) | |
2321 | { | |
2322 | int i; | |
2323 | switch (stringset) { | |
2324 | case ETH_SS_STATS: | |
2325 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
2326 | memcpy(data + i * ETH_GSTRING_LEN, | |
2327 | fec_stats[i].name, ETH_GSTRING_LEN); | |
2328 | break; | |
2329 | } | |
2330 | } | |
2331 | ||
2332 | static int fec_enet_get_sset_count(struct net_device *dev, int sset) | |
2333 | { | |
2334 | switch (sset) { | |
2335 | case ETH_SS_STATS: | |
2336 | return ARRAY_SIZE(fec_stats); | |
2337 | default: | |
2338 | return -EOPNOTSUPP; | |
2339 | } | |
2340 | } | |
d1391930 | 2341 | #endif /* !defined(CONFIG_M5272) */ |
38ae92dc | 2342 | |
32bc9b46 CH |
2343 | static int fec_enet_nway_reset(struct net_device *dev) |
2344 | { | |
45f5c327 | 2345 | struct phy_device *phydev = dev->phydev; |
32bc9b46 CH |
2346 | |
2347 | if (!phydev) | |
2348 | return -ENODEV; | |
2349 | ||
2350 | return genphy_restart_aneg(phydev); | |
2351 | } | |
2352 | ||
d851b47b FD |
2353 | /* ITR clock source is enet system clock (clk_ahb). |
2354 | * TCTT unit is cycle_ns * 64 cycle | |
2355 | * So, the ICTT value = X us / (cycle_ns * 64) | |
2356 | */ | |
2357 | static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) | |
2358 | { | |
2359 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2360 | ||
2361 | return us * (fep->itr_clk_rate / 64000) / 1000; | |
2362 | } | |
2363 | ||
2364 | /* Set threshold for interrupt coalescing */ | |
2365 | static void fec_enet_itr_coal_set(struct net_device *ndev) | |
2366 | { | |
2367 | struct fec_enet_private *fep = netdev_priv(ndev); | |
d851b47b FD |
2368 | int rx_itr, tx_itr; |
2369 | ||
d851b47b FD |
2370 | /* Must be greater than zero to avoid unpredictable behavior */ |
2371 | if (!fep->rx_time_itr || !fep->rx_pkts_itr || | |
2372 | !fep->tx_time_itr || !fep->tx_pkts_itr) | |
2373 | return; | |
2374 | ||
2375 | /* Select enet system clock as Interrupt Coalescing | |
2376 | * timer Clock Source | |
2377 | */ | |
2378 | rx_itr = FEC_ITR_CLK_SEL; | |
2379 | tx_itr = FEC_ITR_CLK_SEL; | |
2380 | ||
2381 | /* set ICFT and ICTT */ | |
2382 | rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); | |
2383 | rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); | |
2384 | tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); | |
2385 | tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); | |
2386 | ||
2387 | rx_itr |= FEC_ITR_EN; | |
2388 | tx_itr |= FEC_ITR_EN; | |
2389 | ||
2390 | writel(tx_itr, fep->hwp + FEC_TXIC0); | |
2391 | writel(rx_itr, fep->hwp + FEC_RXIC0); | |
ff7566b8 FD |
2392 | if (fep->quirks & FEC_QUIRK_HAS_AVB) { |
2393 | writel(tx_itr, fep->hwp + FEC_TXIC1); | |
2394 | writel(rx_itr, fep->hwp + FEC_RXIC1); | |
2395 | writel(tx_itr, fep->hwp + FEC_TXIC2); | |
2396 | writel(rx_itr, fep->hwp + FEC_RXIC2); | |
2397 | } | |
d851b47b FD |
2398 | } |
2399 | ||
2400 | static int | |
2401 | fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) | |
2402 | { | |
2403 | struct fec_enet_private *fep = netdev_priv(ndev); | |
d851b47b | 2404 | |
ff7566b8 | 2405 | if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) |
d851b47b FD |
2406 | return -EOPNOTSUPP; |
2407 | ||
2408 | ec->rx_coalesce_usecs = fep->rx_time_itr; | |
2409 | ec->rx_max_coalesced_frames = fep->rx_pkts_itr; | |
2410 | ||
2411 | ec->tx_coalesce_usecs = fep->tx_time_itr; | |
2412 | ec->tx_max_coalesced_frames = fep->tx_pkts_itr; | |
2413 | ||
2414 | return 0; | |
2415 | } | |
2416 | ||
2417 | static int | |
2418 | fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) | |
2419 | { | |
2420 | struct fec_enet_private *fep = netdev_priv(ndev); | |
d851b47b FD |
2421 | unsigned int cycle; |
2422 | ||
ff7566b8 | 2423 | if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) |
d851b47b FD |
2424 | return -EOPNOTSUPP; |
2425 | ||
2426 | if (ec->rx_max_coalesced_frames > 255) { | |
9f647a6d | 2427 | pr_err("Rx coalesced frames exceed hardware limitation\n"); |
d851b47b FD |
2428 | return -EINVAL; |
2429 | } | |
2430 | ||
2431 | if (ec->tx_max_coalesced_frames > 255) { | |
9f647a6d | 2432 | pr_err("Tx coalesced frame exceed hardware limitation\n"); |
d851b47b FD |
2433 | return -EINVAL; |
2434 | } | |
2435 | ||
2436 | cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); | |
2437 | if (cycle > 0xFFFF) { | |
9f647a6d | 2438 | pr_err("Rx coalesced usec exceed hardware limitation\n"); |
d851b47b FD |
2439 | return -EINVAL; |
2440 | } | |
2441 | ||
2442 | cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); | |
2443 | if (cycle > 0xFFFF) { | |
9f647a6d | 2444 | pr_err("Rx coalesced usec exceed hardware limitation\n"); |
d851b47b FD |
2445 | return -EINVAL; |
2446 | } | |
2447 | ||
2448 | fep->rx_time_itr = ec->rx_coalesce_usecs; | |
2449 | fep->rx_pkts_itr = ec->rx_max_coalesced_frames; | |
2450 | ||
2451 | fep->tx_time_itr = ec->tx_coalesce_usecs; | |
2452 | fep->tx_pkts_itr = ec->tx_max_coalesced_frames; | |
2453 | ||
2454 | fec_enet_itr_coal_set(ndev); | |
2455 | ||
2456 | return 0; | |
2457 | } | |
2458 | ||
2459 | static void fec_enet_itr_coal_init(struct net_device *ndev) | |
2460 | { | |
2461 | struct ethtool_coalesce ec; | |
2462 | ||
2463 | ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; | |
2464 | ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; | |
2465 | ||
2466 | ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; | |
2467 | ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; | |
2468 | ||
2469 | fec_enet_set_coalesce(ndev, &ec); | |
2470 | } | |
2471 | ||
1b7bde6d NA |
2472 | static int fec_enet_get_tunable(struct net_device *netdev, |
2473 | const struct ethtool_tunable *tuna, | |
2474 | void *data) | |
2475 | { | |
2476 | struct fec_enet_private *fep = netdev_priv(netdev); | |
2477 | int ret = 0; | |
2478 | ||
2479 | switch (tuna->id) { | |
2480 | case ETHTOOL_RX_COPYBREAK: | |
2481 | *(u32 *)data = fep->rx_copybreak; | |
2482 | break; | |
2483 | default: | |
2484 | ret = -EINVAL; | |
2485 | break; | |
2486 | } | |
2487 | ||
2488 | return ret; | |
2489 | } | |
2490 | ||
2491 | static int fec_enet_set_tunable(struct net_device *netdev, | |
2492 | const struct ethtool_tunable *tuna, | |
2493 | const void *data) | |
2494 | { | |
2495 | struct fec_enet_private *fep = netdev_priv(netdev); | |
2496 | int ret = 0; | |
2497 | ||
2498 | switch (tuna->id) { | |
2499 | case ETHTOOL_RX_COPYBREAK: | |
2500 | fep->rx_copybreak = *(u32 *)data; | |
2501 | break; | |
2502 | default: | |
2503 | ret = -EINVAL; | |
2504 | break; | |
2505 | } | |
2506 | ||
2507 | return ret; | |
2508 | } | |
2509 | ||
de40ed31 NA |
2510 | static void |
2511 | fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) | |
2512 | { | |
2513 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2514 | ||
2515 | if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { | |
2516 | wol->supported = WAKE_MAGIC; | |
2517 | wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; | |
2518 | } else { | |
2519 | wol->supported = wol->wolopts = 0; | |
2520 | } | |
2521 | } | |
2522 | ||
2523 | static int | |
2524 | fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) | |
2525 | { | |
2526 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2527 | ||
2528 | if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) | |
2529 | return -EINVAL; | |
2530 | ||
2531 | if (wol->wolopts & ~WAKE_MAGIC) | |
2532 | return -EINVAL; | |
2533 | ||
2534 | device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); | |
2535 | if (device_may_wakeup(&ndev->dev)) { | |
2536 | fep->wol_flag |= FEC_WOL_FLAG_ENABLE; | |
2537 | if (fep->irq[0] > 0) | |
2538 | enable_irq_wake(fep->irq[0]); | |
2539 | } else { | |
2540 | fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); | |
2541 | if (fep->irq[0] > 0) | |
2542 | disable_irq_wake(fep->irq[0]); | |
2543 | } | |
2544 | ||
2545 | return 0; | |
2546 | } | |
2547 | ||
9b07be4b | 2548 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
e6b043d5 | 2549 | .get_drvinfo = fec_enet_get_drvinfo, |
db65f35f PR |
2550 | .get_regs_len = fec_enet_get_regs_len, |
2551 | .get_regs = fec_enet_get_regs, | |
32bc9b46 | 2552 | .nway_reset = fec_enet_nway_reset, |
c1d7c48f | 2553 | .get_link = ethtool_op_get_link, |
d851b47b FD |
2554 | .get_coalesce = fec_enet_get_coalesce, |
2555 | .set_coalesce = fec_enet_set_coalesce, | |
38ae92dc | 2556 | #ifndef CONFIG_M5272 |
c1d7c48f RK |
2557 | .get_pauseparam = fec_enet_get_pauseparam, |
2558 | .set_pauseparam = fec_enet_set_pauseparam, | |
38ae92dc | 2559 | .get_strings = fec_enet_get_strings, |
c1d7c48f | 2560 | .get_ethtool_stats = fec_enet_get_ethtool_stats, |
38ae92dc CH |
2561 | .get_sset_count = fec_enet_get_sset_count, |
2562 | #endif | |
c1d7c48f | 2563 | .get_ts_info = fec_enet_get_ts_info, |
1b7bde6d NA |
2564 | .get_tunable = fec_enet_get_tunable, |
2565 | .set_tunable = fec_enet_set_tunable, | |
de40ed31 NA |
2566 | .get_wol = fec_enet_get_wol, |
2567 | .set_wol = fec_enet_set_wol, | |
9365fbf5 PR |
2568 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
2569 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
e6b043d5 | 2570 | }; |
1da177e4 | 2571 | |
c556167f | 2572 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 2573 | { |
c556167f | 2574 | struct fec_enet_private *fep = netdev_priv(ndev); |
45f5c327 | 2575 | struct phy_device *phydev = ndev->phydev; |
1da177e4 | 2576 | |
c556167f | 2577 | if (!netif_running(ndev)) |
e6b043d5 | 2578 | return -EINVAL; |
1da177e4 | 2579 | |
e6b043d5 BW |
2580 | if (!phydev) |
2581 | return -ENODEV; | |
2582 | ||
1d5244d0 BH |
2583 | if (fep->bufdesc_ex) { |
2584 | if (cmd == SIOCSHWTSTAMP) | |
2585 | return fec_ptp_set(ndev, rq); | |
2586 | if (cmd == SIOCGHWTSTAMP) | |
2587 | return fec_ptp_get(ndev, rq); | |
2588 | } | |
ff43da86 | 2589 | |
28b04113 | 2590 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
2591 | } |
2592 | ||
c556167f | 2593 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 2594 | { |
c556167f | 2595 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 2596 | unsigned int i; |
f0b3fbea SH |
2597 | struct sk_buff *skb; |
2598 | struct bufdesc *bdp; | |
4d494cdc FD |
2599 | struct fec_enet_priv_tx_q *txq; |
2600 | struct fec_enet_priv_rx_q *rxq; | |
59d0f746 FL |
2601 | unsigned int q; |
2602 | ||
2603 | for (q = 0; q < fep->num_rx_queues; q++) { | |
2604 | rxq = fep->rx_queue[q]; | |
7355f276 TK |
2605 | bdp = rxq->bd.base; |
2606 | for (i = 0; i < rxq->bd.ring_size; i++) { | |
59d0f746 FL |
2607 | skb = rxq->rx_skbuff[i]; |
2608 | rxq->rx_skbuff[i] = NULL; | |
2609 | if (skb) { | |
2610 | dma_unmap_single(&fep->pdev->dev, | |
5cfa3039 | 2611 | fec32_to_cpu(bdp->cbd_bufaddr), |
b64bf4b7 | 2612 | FEC_ENET_RX_FRSIZE - fep->rx_align, |
59d0f746 FL |
2613 | DMA_FROM_DEVICE); |
2614 | dev_kfree_skb(skb); | |
2615 | } | |
7355f276 | 2616 | bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); |
59d0f746 FL |
2617 | } |
2618 | } | |
4d494cdc | 2619 | |
59d0f746 FL |
2620 | for (q = 0; q < fep->num_tx_queues; q++) { |
2621 | txq = fep->tx_queue[q]; | |
7355f276 TK |
2622 | bdp = txq->bd.base; |
2623 | for (i = 0; i < txq->bd.ring_size; i++) { | |
59d0f746 FL |
2624 | kfree(txq->tx_bounce[i]); |
2625 | txq->tx_bounce[i] = NULL; | |
2626 | skb = txq->tx_skbuff[i]; | |
2627 | txq->tx_skbuff[i] = NULL; | |
f0b3fbea | 2628 | dev_kfree_skb(skb); |
730ee360 | 2629 | } |
f0b3fbea | 2630 | } |
59d0f746 | 2631 | } |
f0b3fbea | 2632 | |
59d0f746 FL |
2633 | static void fec_enet_free_queue(struct net_device *ndev) |
2634 | { | |
2635 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2636 | int i; | |
2637 | struct fec_enet_priv_tx_q *txq; | |
2638 | ||
2639 | for (i = 0; i < fep->num_tx_queues; i++) | |
2640 | if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { | |
2641 | txq = fep->tx_queue[i]; | |
2642 | dma_free_coherent(NULL, | |
7355f276 | 2643 | txq->bd.ring_size * TSO_HEADER_SIZE, |
59d0f746 FL |
2644 | txq->tso_hdrs, |
2645 | txq->tso_hdrs_dma); | |
2646 | } | |
2647 | ||
2648 | for (i = 0; i < fep->num_rx_queues; i++) | |
1b4b32c6 | 2649 | kfree(fep->rx_queue[i]); |
59d0f746 | 2650 | for (i = 0; i < fep->num_tx_queues; i++) |
1b4b32c6 | 2651 | kfree(fep->tx_queue[i]); |
59d0f746 FL |
2652 | } |
2653 | ||
2654 | static int fec_enet_alloc_queue(struct net_device *ndev) | |
2655 | { | |
2656 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2657 | int i; | |
2658 | int ret = 0; | |
2659 | struct fec_enet_priv_tx_q *txq; | |
2660 | ||
2661 | for (i = 0; i < fep->num_tx_queues; i++) { | |
2662 | txq = kzalloc(sizeof(*txq), GFP_KERNEL); | |
2663 | if (!txq) { | |
2664 | ret = -ENOMEM; | |
2665 | goto alloc_failed; | |
2666 | } | |
2667 | ||
2668 | fep->tx_queue[i] = txq; | |
7355f276 TK |
2669 | txq->bd.ring_size = TX_RING_SIZE; |
2670 | fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; | |
59d0f746 FL |
2671 | |
2672 | txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; | |
2673 | txq->tx_wake_threshold = | |
7355f276 | 2674 | (txq->bd.ring_size - txq->tx_stop_threshold) / 2; |
59d0f746 FL |
2675 | |
2676 | txq->tso_hdrs = dma_alloc_coherent(NULL, | |
7355f276 | 2677 | txq->bd.ring_size * TSO_HEADER_SIZE, |
59d0f746 FL |
2678 | &txq->tso_hdrs_dma, |
2679 | GFP_KERNEL); | |
2680 | if (!txq->tso_hdrs) { | |
2681 | ret = -ENOMEM; | |
2682 | goto alloc_failed; | |
2683 | } | |
8b7c9efa | 2684 | } |
59d0f746 FL |
2685 | |
2686 | for (i = 0; i < fep->num_rx_queues; i++) { | |
2687 | fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), | |
2688 | GFP_KERNEL); | |
2689 | if (!fep->rx_queue[i]) { | |
2690 | ret = -ENOMEM; | |
2691 | goto alloc_failed; | |
2692 | } | |
2693 | ||
7355f276 TK |
2694 | fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; |
2695 | fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; | |
59d0f746 FL |
2696 | } |
2697 | return ret; | |
2698 | ||
2699 | alloc_failed: | |
2700 | fec_enet_free_queue(ndev); | |
2701 | return ret; | |
f0b3fbea SH |
2702 | } |
2703 | ||
59d0f746 FL |
2704 | static int |
2705 | fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) | |
f0b3fbea | 2706 | { |
c556167f | 2707 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 2708 | unsigned int i; |
f0b3fbea SH |
2709 | struct sk_buff *skb; |
2710 | struct bufdesc *bdp; | |
4d494cdc | 2711 | struct fec_enet_priv_rx_q *rxq; |
f0b3fbea | 2712 | |
59d0f746 | 2713 | rxq = fep->rx_queue[queue]; |
7355f276 TK |
2714 | bdp = rxq->bd.base; |
2715 | for (i = 0; i < rxq->bd.ring_size; i++) { | |
b72061a3 | 2716 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
ffdce2cc RK |
2717 | if (!skb) |
2718 | goto err_alloc; | |
f0b3fbea | 2719 | |
1b7bde6d | 2720 | if (fec_enet_new_rxbdp(ndev, bdp, skb)) { |
730ee360 | 2721 | dev_kfree_skb(skb); |
ffdce2cc | 2722 | goto err_alloc; |
d842a31f | 2723 | } |
730ee360 | 2724 | |
4d494cdc | 2725 | rxq->rx_skbuff[i] = skb; |
5cfa3039 | 2726 | bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); |
ff43da86 FL |
2727 | |
2728 | if (fep->bufdesc_ex) { | |
2729 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
5cfa3039 | 2730 | ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); |
ff43da86 FL |
2731 | } |
2732 | ||
7355f276 | 2733 | bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); |
f0b3fbea SH |
2734 | } |
2735 | ||
2736 | /* Set the last buffer to wrap. */ | |
7355f276 | 2737 | bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); |
5cfa3039 | 2738 | bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); |
59d0f746 | 2739 | return 0; |
f0b3fbea | 2740 | |
59d0f746 FL |
2741 | err_alloc: |
2742 | fec_enet_free_buffers(ndev); | |
2743 | return -ENOMEM; | |
2744 | } | |
2745 | ||
2746 | static int | |
2747 | fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) | |
2748 | { | |
2749 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2750 | unsigned int i; | |
2751 | struct bufdesc *bdp; | |
2752 | struct fec_enet_priv_tx_q *txq; | |
2753 | ||
2754 | txq = fep->tx_queue[queue]; | |
7355f276 TK |
2755 | bdp = txq->bd.base; |
2756 | for (i = 0; i < txq->bd.ring_size; i++) { | |
4d494cdc FD |
2757 | txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); |
2758 | if (!txq->tx_bounce[i]) | |
ffdce2cc | 2759 | goto err_alloc; |
f0b3fbea | 2760 | |
5cfa3039 JB |
2761 | bdp->cbd_sc = cpu_to_fec16(0); |
2762 | bdp->cbd_bufaddr = cpu_to_fec32(0); | |
6605b730 | 2763 | |
ff43da86 FL |
2764 | if (fep->bufdesc_ex) { |
2765 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
5cfa3039 | 2766 | ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); |
ff43da86 FL |
2767 | } |
2768 | ||
7355f276 | 2769 | bdp = fec_enet_get_nextdesc(bdp, &txq->bd); |
f0b3fbea SH |
2770 | } |
2771 | ||
2772 | /* Set the last buffer to wrap. */ | |
7355f276 | 2773 | bdp = fec_enet_get_prevdesc(bdp, &txq->bd); |
5cfa3039 | 2774 | bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); |
f0b3fbea SH |
2775 | |
2776 | return 0; | |
ffdce2cc RK |
2777 | |
2778 | err_alloc: | |
2779 | fec_enet_free_buffers(ndev); | |
2780 | return -ENOMEM; | |
f0b3fbea SH |
2781 | } |
2782 | ||
59d0f746 FL |
2783 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
2784 | { | |
2785 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2786 | unsigned int i; | |
2787 | ||
2788 | for (i = 0; i < fep->num_rx_queues; i++) | |
2789 | if (fec_enet_alloc_rxq_buffers(ndev, i)) | |
2790 | return -ENOMEM; | |
2791 | ||
2792 | for (i = 0; i < fep->num_tx_queues; i++) | |
2793 | if (fec_enet_alloc_txq_buffers(ndev, i)) | |
2794 | return -ENOMEM; | |
2795 | return 0; | |
2796 | } | |
2797 | ||
1da177e4 | 2798 | static int |
c556167f | 2799 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 2800 | { |
c556167f | 2801 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 2802 | int ret; |
1da177e4 | 2803 | |
8fff755e | 2804 | ret = pm_runtime_get_sync(&fep->pdev->dev); |
b0c6ce24 | 2805 | if (ret < 0) |
8fff755e AL |
2806 | return ret; |
2807 | ||
5bbde4d2 | 2808 | pinctrl_pm_select_default_state(&fep->pdev->dev); |
e8fcfcd5 NA |
2809 | ret = fec_enet_clk_enable(ndev, true); |
2810 | if (ret) | |
8fff755e | 2811 | goto clk_enable; |
e8fcfcd5 | 2812 | |
1da177e4 LT |
2813 | /* I should reset the ring buffers here, but I don't yet know |
2814 | * a simple way to do that. | |
2815 | */ | |
1da177e4 | 2816 | |
c556167f | 2817 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea | 2818 | if (ret) |
681d2421 | 2819 | goto err_enet_alloc; |
f0b3fbea | 2820 | |
55dd2753 NA |
2821 | /* Init MAC prior to mii bus probe */ |
2822 | fec_restart(ndev); | |
2823 | ||
418bd0d4 | 2824 | /* Probe and connect to PHY when open the interface */ |
c556167f | 2825 | ret = fec_enet_mii_probe(ndev); |
681d2421 FE |
2826 | if (ret) |
2827 | goto err_enet_mii_probe; | |
ce5eaf02 | 2828 | |
29380905 LS |
2829 | if (fep->quirks & FEC_QUIRK_ERR006687) |
2830 | imx6q_cpuidle_fec_irqs_used(); | |
2831 | ||
ce5eaf02 | 2832 | napi_enable(&fep->napi); |
45f5c327 | 2833 | phy_start(ndev->phydev); |
4d494cdc FD |
2834 | netif_tx_start_all_queues(ndev); |
2835 | ||
de40ed31 NA |
2836 | device_set_wakeup_enable(&ndev->dev, fep->wol_flag & |
2837 | FEC_WOL_FLAG_ENABLE); | |
2838 | ||
22f6b860 | 2839 | return 0; |
681d2421 FE |
2840 | |
2841 | err_enet_mii_probe: | |
2842 | fec_enet_free_buffers(ndev); | |
2843 | err_enet_alloc: | |
2844 | fec_enet_clk_enable(ndev, false); | |
8fff755e AL |
2845 | clk_enable: |
2846 | pm_runtime_mark_last_busy(&fep->pdev->dev); | |
2847 | pm_runtime_put_autosuspend(&fep->pdev->dev); | |
681d2421 FE |
2848 | pinctrl_pm_select_sleep_state(&fep->pdev->dev); |
2849 | return ret; | |
1da177e4 LT |
2850 | } |
2851 | ||
2852 | static int | |
c556167f | 2853 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 2854 | { |
c556167f | 2855 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 2856 | |
45f5c327 | 2857 | phy_stop(ndev->phydev); |
d76cfae9 | 2858 | |
31a6de34 RK |
2859 | if (netif_device_present(ndev)) { |
2860 | napi_disable(&fep->napi); | |
2861 | netif_tx_disable(ndev); | |
8bbbd3c1 | 2862 | fec_stop(ndev); |
31a6de34 | 2863 | } |
1da177e4 | 2864 | |
45f5c327 | 2865 | phy_disconnect(ndev->phydev); |
418bd0d4 | 2866 | |
29380905 LS |
2867 | if (fep->quirks & FEC_QUIRK_ERR006687) |
2868 | imx6q_cpuidle_fec_irqs_unused(); | |
2869 | ||
e8fcfcd5 | 2870 | fec_enet_clk_enable(ndev, false); |
5bbde4d2 | 2871 | pinctrl_pm_select_sleep_state(&fep->pdev->dev); |
8fff755e AL |
2872 | pm_runtime_mark_last_busy(&fep->pdev->dev); |
2873 | pm_runtime_put_autosuspend(&fep->pdev->dev); | |
2874 | ||
db8880bc | 2875 | fec_enet_free_buffers(ndev); |
f0b3fbea | 2876 | |
1da177e4 LT |
2877 | return 0; |
2878 | } | |
2879 | ||
1da177e4 LT |
2880 | /* Set or clear the multicast filter for this adaptor. |
2881 | * Skeleton taken from sunlance driver. | |
2882 | * The CPM Ethernet implementation allows Multicast as well as individual | |
2883 | * MAC address filtering. Some of the drivers check to make sure it is | |
2884 | * a group multicast address, and discard those that are not. I guess I | |
2885 | * will do the same for now, but just remove the test if you want | |
2886 | * individual filtering as well (do the upper net layers want or support | |
2887 | * this kind of feature?). | |
2888 | */ | |
2889 | ||
2890 | #define HASH_BITS 6 /* #bits in hash */ | |
2891 | #define CRC32_POLY 0xEDB88320 | |
2892 | ||
c556167f | 2893 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 2894 | { |
c556167f | 2895 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 2896 | struct netdev_hw_addr *ha; |
48e2f183 | 2897 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
2898 | unsigned char hash; |
2899 | ||
c556167f | 2900 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
2901 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
2902 | tmp |= 0x8; | |
2903 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
2904 | return; |
2905 | } | |
1da177e4 | 2906 | |
4e831836 SH |
2907 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
2908 | tmp &= ~0x8; | |
2909 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
2910 | ||
c556167f | 2911 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
2912 | /* Catch all multicast addresses, so set the |
2913 | * filter to all 1's | |
2914 | */ | |
2915 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
2916 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
2917 | ||
2918 | return; | |
2919 | } | |
2920 | ||
2921 | /* Clear filter and add the addresses in hash register | |
2922 | */ | |
2923 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
2924 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
2925 | ||
c556167f | 2926 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
2927 | /* calculate crc32 value of mac address */ |
2928 | crc = 0xffffffff; | |
2929 | ||
c556167f | 2930 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 2931 | data = ha->addr[i]; |
4e831836 SH |
2932 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
2933 | crc = (crc >> 1) ^ | |
2934 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
2935 | } |
2936 | } | |
4e831836 SH |
2937 | |
2938 | /* only upper 6 bits (HASH_BITS) are used | |
2939 | * which point to specific bit in he hash registers | |
2940 | */ | |
2941 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
2942 | ||
2943 | if (hash > 31) { | |
2944 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
2945 | tmp |= 1 << (hash - 32); | |
2946 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
2947 | } else { | |
2948 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
2949 | tmp |= 1 << hash; | |
2950 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
2951 | } | |
1da177e4 LT |
2952 | } |
2953 | } | |
2954 | ||
22f6b860 | 2955 | /* Set a MAC change in hardware. */ |
009fda83 | 2956 | static int |
c556167f | 2957 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 2958 | { |
c556167f | 2959 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
2960 | struct sockaddr *addr = p; |
2961 | ||
44934fac LS |
2962 | if (addr) { |
2963 | if (!is_valid_ether_addr(addr->sa_data)) | |
2964 | return -EADDRNOTAVAIL; | |
2965 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); | |
2966 | } | |
1da177e4 | 2967 | |
9638d19e NA |
2968 | /* Add netif status check here to avoid system hang in below case: |
2969 | * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; | |
2970 | * After ethx down, fec all clocks are gated off and then register | |
2971 | * access causes system hang. | |
2972 | */ | |
2973 | if (!netif_running(ndev)) | |
2974 | return 0; | |
2975 | ||
c556167f UKK |
2976 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
2977 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 2978 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 2979 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 2980 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 2981 | return 0; |
1da177e4 LT |
2982 | } |
2983 | ||
7f5c6add | 2984 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
2985 | /** |
2986 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
2987 | * @dev: The FEC network adapter |
2988 | * | |
2989 | * Polled functionality used by netconsole and others in non interrupt mode | |
2990 | * | |
2991 | */ | |
47a5247f | 2992 | static void fec_poll_controller(struct net_device *dev) |
7f5c6add XJ |
2993 | { |
2994 | int i; | |
2995 | struct fec_enet_private *fep = netdev_priv(dev); | |
2996 | ||
2997 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
2998 | if (fep->irq[i] > 0) { | |
2999 | disable_irq(fep->irq[i]); | |
3000 | fec_enet_interrupt(fep->irq[i], dev); | |
3001 | enable_irq(fep->irq[i]); | |
3002 | } | |
3003 | } | |
3004 | } | |
3005 | #endif | |
3006 | ||
5bc26726 | 3007 | static inline void fec_enet_set_netdev_features(struct net_device *netdev, |
4c09eed9 JB |
3008 | netdev_features_t features) |
3009 | { | |
3010 | struct fec_enet_private *fep = netdev_priv(netdev); | |
3011 | netdev_features_t changed = features ^ netdev->features; | |
3012 | ||
3013 | netdev->features = features; | |
3014 | ||
3015 | /* Receive checksum has been changed */ | |
3016 | if (changed & NETIF_F_RXCSUM) { | |
3017 | if (features & NETIF_F_RXCSUM) | |
3018 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
3019 | else | |
3020 | fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; | |
8506fa1d | 3021 | } |
5bc26726 NA |
3022 | } |
3023 | ||
3024 | static int fec_set_features(struct net_device *netdev, | |
3025 | netdev_features_t features) | |
3026 | { | |
3027 | struct fec_enet_private *fep = netdev_priv(netdev); | |
3028 | netdev_features_t changed = features ^ netdev->features; | |
4c09eed9 | 3029 | |
5b40f709 | 3030 | if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { |
5bc26726 NA |
3031 | napi_disable(&fep->napi); |
3032 | netif_tx_lock_bh(netdev); | |
3033 | fec_stop(netdev); | |
3034 | fec_enet_set_netdev_features(netdev, features); | |
ef83337d | 3035 | fec_restart(netdev); |
4d494cdc | 3036 | netif_tx_wake_all_queues(netdev); |
8506fa1d RK |
3037 | netif_tx_unlock_bh(netdev); |
3038 | napi_enable(&fep->napi); | |
5bc26726 NA |
3039 | } else { |
3040 | fec_enet_set_netdev_features(netdev, features); | |
4c09eed9 JB |
3041 | } |
3042 | ||
3043 | return 0; | |
3044 | } | |
3045 | ||
009fda83 SH |
3046 | static const struct net_device_ops fec_netdev_ops = { |
3047 | .ndo_open = fec_enet_open, | |
3048 | .ndo_stop = fec_enet_close, | |
3049 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 3050 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 3051 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
3052 | .ndo_validate_addr = eth_validate_addr, |
3053 | .ndo_tx_timeout = fec_timeout, | |
3054 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 3055 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
3056 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3057 | .ndo_poll_controller = fec_poll_controller, | |
3058 | #endif | |
4c09eed9 | 3059 | .ndo_set_features = fec_set_features, |
009fda83 SH |
3060 | }; |
3061 | ||
53bb20d1 TK |
3062 | static const unsigned short offset_des_active_rxq[] = { |
3063 | FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 | |
3064 | }; | |
3065 | ||
3066 | static const unsigned short offset_des_active_txq[] = { | |
3067 | FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 | |
3068 | }; | |
3069 | ||
1da177e4 LT |
3070 | /* |
3071 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 3072 | * |
1da177e4 | 3073 | */ |
c556167f | 3074 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 3075 | { |
c556167f | 3076 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 3077 | struct bufdesc *cbd_base; |
4d494cdc | 3078 | dma_addr_t bd_dma; |
55d0218a | 3079 | int bd_size; |
59d0f746 | 3080 | unsigned int i; |
7355f276 TK |
3081 | unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : |
3082 | sizeof(struct bufdesc); | |
3083 | unsigned dsize_log2 = __fls(dsize); | |
55d0218a | 3084 | |
7355f276 | 3085 | WARN_ON(dsize != (1 << dsize_log2)); |
41ef84ce FD |
3086 | #if defined(CONFIG_ARM) |
3087 | fep->rx_align = 0xf; | |
3088 | fep->tx_align = 0xf; | |
3089 | #else | |
3090 | fep->rx_align = 0x3; | |
3091 | fep->tx_align = 0x3; | |
3092 | #endif | |
3093 | ||
59d0f746 | 3094 | fec_enet_alloc_queue(ndev); |
79f33912 | 3095 | |
7355f276 | 3096 | bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; |
1da177e4 | 3097 | |
8d4dd5cf | 3098 | /* Allocate memory for buffer descriptors. */ |
c0a1a0a6 LS |
3099 | cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, |
3100 | GFP_KERNEL); | |
4d494cdc | 3101 | if (!cbd_base) { |
79f33912 NA |
3102 | return -ENOMEM; |
3103 | } | |
3104 | ||
4d494cdc | 3105 | memset(cbd_base, 0, bd_size); |
1da177e4 | 3106 | |
49da97dc | 3107 | /* Get the Ethernet address */ |
c556167f | 3108 | fec_get_mac(ndev); |
44934fac LS |
3109 | /* make sure MAC we just acquired is programmed into the hw */ |
3110 | fec_set_mac_address(ndev, NULL); | |
1da177e4 | 3111 | |
8d4dd5cf | 3112 | /* Set receive and transmit descriptor base. */ |
59d0f746 | 3113 | for (i = 0; i < fep->num_rx_queues; i++) { |
7355f276 TK |
3114 | struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; |
3115 | unsigned size = dsize * rxq->bd.ring_size; | |
3116 | ||
3117 | rxq->bd.qid = i; | |
3118 | rxq->bd.base = cbd_base; | |
3119 | rxq->bd.cur = cbd_base; | |
3120 | rxq->bd.dma = bd_dma; | |
3121 | rxq->bd.dsize = dsize; | |
3122 | rxq->bd.dsize_log2 = dsize_log2; | |
53bb20d1 | 3123 | rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; |
7355f276 TK |
3124 | bd_dma += size; |
3125 | cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); | |
3126 | rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); | |
59d0f746 FL |
3127 | } |
3128 | ||
3129 | for (i = 0; i < fep->num_tx_queues; i++) { | |
7355f276 TK |
3130 | struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; |
3131 | unsigned size = dsize * txq->bd.ring_size; | |
3132 | ||
3133 | txq->bd.qid = i; | |
3134 | txq->bd.base = cbd_base; | |
3135 | txq->bd.cur = cbd_base; | |
3136 | txq->bd.dma = bd_dma; | |
3137 | txq->bd.dsize = dsize; | |
3138 | txq->bd.dsize_log2 = dsize_log2; | |
53bb20d1 | 3139 | txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; |
7355f276 TK |
3140 | bd_dma += size; |
3141 | cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); | |
3142 | txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); | |
59d0f746 | 3143 | } |
4d494cdc | 3144 | |
1da177e4 | 3145 | |
22f6b860 | 3146 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
3147 | ndev->watchdog_timeo = TX_TIMEOUT; |
3148 | ndev->netdev_ops = &fec_netdev_ops; | |
3149 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 3150 | |
dc975382 | 3151 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
322555f5 | 3152 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); |
dc975382 | 3153 | |
6b7e4008 | 3154 | if (fep->quirks & FEC_QUIRK_HAS_VLAN) |
cdffcf1b JB |
3155 | /* enable hw VLAN support */ |
3156 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
cdffcf1b | 3157 | |
6b7e4008 | 3158 | if (fep->quirks & FEC_QUIRK_HAS_CSUM) { |
79f33912 NA |
3159 | ndev->gso_max_segs = FEC_MAX_TSO_SEGS; |
3160 | ||
48496255 SG |
3161 | /* enable hw accelerator */ |
3162 | ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
79f33912 | 3163 | | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); |
48496255 SG |
3164 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; |
3165 | } | |
4c09eed9 | 3166 | |
6b7e4008 | 3167 | if (fep->quirks & FEC_QUIRK_HAS_AVB) { |
41ef84ce FD |
3168 | fep->tx_align = 0; |
3169 | fep->rx_align = 0x3f; | |
3170 | } | |
3171 | ||
09d1e541 NA |
3172 | ndev->hw_features = ndev->features; |
3173 | ||
ef83337d | 3174 | fec_restart(ndev); |
1da177e4 | 3175 | |
1da177e4 LT |
3176 | return 0; |
3177 | } | |
3178 | ||
ca2cc333 | 3179 | #ifdef CONFIG_OF |
33897cc8 | 3180 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
3181 | { |
3182 | int err, phy_reset; | |
962d8cdc | 3183 | bool active_high = false; |
a3caad0a | 3184 | int msec = 1; |
ca2cc333 SG |
3185 | struct device_node *np = pdev->dev.of_node; |
3186 | ||
3187 | if (!np) | |
a9b2c8ef | 3188 | return; |
ca2cc333 | 3189 | |
a3caad0a SG |
3190 | of_property_read_u32(np, "phy-reset-duration", &msec); |
3191 | /* A sane reset duration should not be longer than 1s */ | |
3192 | if (msec > 1000) | |
3193 | msec = 1; | |
3194 | ||
ca2cc333 | 3195 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
3196 | if (!gpio_is_valid(phy_reset)) |
3197 | return; | |
3198 | ||
962d8cdc | 3199 | active_high = of_property_read_bool(np, "phy-reset-active-high"); |
64f10f6e | 3200 | |
119fc007 | 3201 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
962d8cdc | 3202 | active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, |
64f10f6e | 3203 | "phy-reset"); |
ca2cc333 | 3204 | if (err) { |
07dcf8e9 | 3205 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 3206 | return; |
ca2cc333 | 3207 | } |
eb37c563 SW |
3208 | |
3209 | if (msec > 20) | |
3210 | msleep(msec); | |
3211 | else | |
3212 | usleep_range(msec * 1000, msec * 1000 + 1000); | |
3213 | ||
962d8cdc | 3214 | gpio_set_value_cansleep(phy_reset, !active_high); |
ca2cc333 SG |
3215 | } |
3216 | #else /* CONFIG_OF */ | |
0c7768a0 | 3217 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
3218 | { |
3219 | /* | |
3220 | * In case of platform probe, the reset has been done | |
3221 | * by machine code. | |
3222 | */ | |
ca2cc333 SG |
3223 | } |
3224 | #endif /* CONFIG_OF */ | |
3225 | ||
9fc095f1 FD |
3226 | static void |
3227 | fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) | |
3228 | { | |
3229 | struct device_node *np = pdev->dev.of_node; | |
9fc095f1 FD |
3230 | |
3231 | *num_tx = *num_rx = 1; | |
3232 | ||
3233 | if (!np || !of_device_is_available(np)) | |
3234 | return; | |
3235 | ||
3236 | /* parse the num of tx and rx queues */ | |
73b1c90d | 3237 | of_property_read_u32(np, "fsl,num-tx-queues", num_tx); |
b7bd75cf | 3238 | |
73b1c90d | 3239 | of_property_read_u32(np, "fsl,num-rx-queues", num_rx); |
9fc095f1 FD |
3240 | |
3241 | if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { | |
b7bd75cf FL |
3242 | dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", |
3243 | *num_tx); | |
9fc095f1 FD |
3244 | *num_tx = 1; |
3245 | return; | |
3246 | } | |
3247 | ||
3248 | if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { | |
b7bd75cf FL |
3249 | dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", |
3250 | *num_rx); | |
9fc095f1 FD |
3251 | *num_rx = 1; |
3252 | return; | |
3253 | } | |
3254 | ||
3255 | } | |
3256 | ||
33897cc8 | 3257 | static int |
ead73183 SH |
3258 | fec_probe(struct platform_device *pdev) |
3259 | { | |
3260 | struct fec_enet_private *fep; | |
5eb32bd0 | 3261 | struct fec_platform_data *pdata; |
ead73183 SH |
3262 | struct net_device *ndev; |
3263 | int i, irq, ret = 0; | |
3264 | struct resource *r; | |
ca2cc333 | 3265 | const struct of_device_id *of_id; |
43af940c | 3266 | static int dev_id; |
407066f8 | 3267 | struct device_node *np = pdev->dev.of_node, *phy_node; |
b7bd75cf FL |
3268 | int num_tx_qs; |
3269 | int num_rx_qs; | |
ca2cc333 | 3270 | |
9fc095f1 FD |
3271 | fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); |
3272 | ||
ead73183 | 3273 | /* Init network device */ |
9fc095f1 FD |
3274 | ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), |
3275 | num_tx_qs, num_rx_qs); | |
83e519b6 FE |
3276 | if (!ndev) |
3277 | return -ENOMEM; | |
ead73183 SH |
3278 | |
3279 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
3280 | ||
3281 | /* setup board info structure */ | |
3282 | fep = netdev_priv(ndev); | |
ead73183 | 3283 | |
6b7e4008 LW |
3284 | of_id = of_match_device(fec_dt_ids, &pdev->dev); |
3285 | if (of_id) | |
3286 | pdev->id_entry = of_id->data; | |
3287 | fep->quirks = pdev->id_entry->driver_data; | |
3288 | ||
0c818594 | 3289 | fep->netdev = ndev; |
9fc095f1 FD |
3290 | fep->num_rx_queues = num_rx_qs; |
3291 | fep->num_tx_queues = num_tx_qs; | |
3292 | ||
d1391930 | 3293 | #if !defined(CONFIG_M5272) |
baa70a5c | 3294 | /* default enable pause frame auto negotiation */ |
6b7e4008 | 3295 | if (fep->quirks & FEC_QUIRK_HAS_GBIT) |
baa70a5c | 3296 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; |
d1391930 | 3297 | #endif |
baa70a5c | 3298 | |
5bbde4d2 NA |
3299 | /* Select default pin state */ |
3300 | pinctrl_pm_select_default_state(&pdev->dev); | |
3301 | ||
399db75b | 3302 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
941e173a TB |
3303 | fep->hwp = devm_ioremap_resource(&pdev->dev, r); |
3304 | if (IS_ERR(fep->hwp)) { | |
3305 | ret = PTR_ERR(fep->hwp); | |
3306 | goto failed_ioremap; | |
3307 | } | |
3308 | ||
e6b043d5 | 3309 | fep->pdev = pdev; |
43af940c | 3310 | fep->dev_id = dev_id++; |
ead73183 | 3311 | |
ead73183 SH |
3312 | platform_set_drvdata(pdev, ndev); |
3313 | ||
29380905 LS |
3314 | if ((of_machine_is_compatible("fsl,imx6q") || |
3315 | of_machine_is_compatible("fsl,imx6dl")) && | |
3316 | !of_property_read_bool(np, "fsl,err006687-workaround-present")) | |
3317 | fep->quirks |= FEC_QUIRK_ERR006687; | |
3318 | ||
de40ed31 NA |
3319 | if (of_get_property(np, "fsl,magic-packet", NULL)) |
3320 | fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; | |
3321 | ||
407066f8 UKK |
3322 | phy_node = of_parse_phandle(np, "phy-handle", 0); |
3323 | if (!phy_node && of_phy_is_fixed_link(np)) { | |
3324 | ret = of_phy_register_fixed_link(np); | |
3325 | if (ret < 0) { | |
3326 | dev_err(&pdev->dev, | |
3327 | "broken fixed-link specification\n"); | |
3328 | goto failed_phy; | |
3329 | } | |
3330 | phy_node = of_node_get(np); | |
3331 | } | |
3332 | fep->phy_node = phy_node; | |
3333 | ||
6c5f7808 | 3334 | ret = of_get_phy_mode(pdev->dev.of_node); |
ca2cc333 | 3335 | if (ret < 0) { |
94660ba0 | 3336 | pdata = dev_get_platdata(&pdev->dev); |
ca2cc333 SG |
3337 | if (pdata) |
3338 | fep->phy_interface = pdata->phy; | |
3339 | else | |
3340 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
3341 | } else { | |
3342 | fep->phy_interface = ret; | |
3343 | } | |
3344 | ||
f4d40de3 SH |
3345 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
3346 | if (IS_ERR(fep->clk_ipg)) { | |
3347 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
3348 | goto failed_clk; |
3349 | } | |
f4d40de3 SH |
3350 | |
3351 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
3352 | if (IS_ERR(fep->clk_ahb)) { | |
3353 | ret = PTR_ERR(fep->clk_ahb); | |
3354 | goto failed_clk; | |
3355 | } | |
3356 | ||
d851b47b FD |
3357 | fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); |
3358 | ||
daa7d392 WS |
3359 | /* enet_out is optional, depends on board */ |
3360 | fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); | |
3361 | if (IS_ERR(fep->clk_enet_out)) | |
3362 | fep->clk_enet_out = NULL; | |
3363 | ||
91c0d987 NA |
3364 | fep->ptp_clk_on = false; |
3365 | mutex_init(&fep->ptp_clk_mutex); | |
9b5330ed FD |
3366 | |
3367 | /* clk_ref is optional, depends on board */ | |
3368 | fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); | |
3369 | if (IS_ERR(fep->clk_ref)) | |
3370 | fep->clk_ref = NULL; | |
3371 | ||
6b7e4008 | 3372 | fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; |
6605b730 FL |
3373 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
3374 | if (IS_ERR(fep->clk_ptp)) { | |
c29dc2d7 | 3375 | fep->clk_ptp = NULL; |
217b5844 | 3376 | fep->bufdesc_ex = false; |
6605b730 | 3377 | } |
6605b730 | 3378 | |
e8fcfcd5 | 3379 | ret = fec_enet_clk_enable(ndev, true); |
13a097bd FE |
3380 | if (ret) |
3381 | goto failed_clk; | |
3382 | ||
8fff755e AL |
3383 | ret = clk_prepare_enable(fep->clk_ipg); |
3384 | if (ret) | |
3385 | goto failed_clk_ipg; | |
3386 | ||
f4e9f3d2 FE |
3387 | fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
3388 | if (!IS_ERR(fep->reg_phy)) { | |
3389 | ret = regulator_enable(fep->reg_phy); | |
5fa9c0fe SG |
3390 | if (ret) { |
3391 | dev_err(&pdev->dev, | |
3392 | "Failed to enable phy regulator: %d\n", ret); | |
3393 | goto failed_regulator; | |
3394 | } | |
f6a4d607 FE |
3395 | } else { |
3396 | fep->reg_phy = NULL; | |
5fa9c0fe SG |
3397 | } |
3398 | ||
8fff755e AL |
3399 | pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); |
3400 | pm_runtime_use_autosuspend(&pdev->dev); | |
14d2b7c1 | 3401 | pm_runtime_get_noresume(&pdev->dev); |
8fff755e AL |
3402 | pm_runtime_set_active(&pdev->dev); |
3403 | pm_runtime_enable(&pdev->dev); | |
3404 | ||
2ca9b2aa SG |
3405 | fec_reset_phy(pdev); |
3406 | ||
e2f8d555 | 3407 | if (fep->bufdesc_ex) |
ca162a82 | 3408 | fec_ptp_init(pdev); |
e2f8d555 FE |
3409 | |
3410 | ret = fec_enet_init(ndev); | |
3411 | if (ret) | |
3412 | goto failed_init; | |
3413 | ||
3414 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
3415 | irq = platform_get_irq(pdev, i); | |
3416 | if (irq < 0) { | |
3417 | if (i) | |
3418 | break; | |
3419 | ret = irq; | |
3420 | goto failed_irq; | |
3421 | } | |
0d9b2ab1 | 3422 | ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, |
44a272dd | 3423 | 0, pdev->name, ndev); |
0d9b2ab1 | 3424 | if (ret) |
e2f8d555 | 3425 | goto failed_irq; |
de40ed31 NA |
3426 | |
3427 | fep->irq[i] = irq; | |
e2f8d555 FE |
3428 | } |
3429 | ||
b4d39b53 | 3430 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
3431 | ret = fec_enet_mii_init(pdev); |
3432 | if (ret) | |
3433 | goto failed_mii_init; | |
3434 | ||
03c698c9 OS |
3435 | /* Carrier starts down, phylib will bring it up */ |
3436 | netif_carrier_off(ndev); | |
e8fcfcd5 | 3437 | fec_enet_clk_enable(ndev, false); |
5bbde4d2 | 3438 | pinctrl_pm_select_sleep_state(&pdev->dev); |
03c698c9 | 3439 | |
ead73183 SH |
3440 | ret = register_netdev(ndev); |
3441 | if (ret) | |
3442 | goto failed_register; | |
3443 | ||
de40ed31 NA |
3444 | device_init_wakeup(&ndev->dev, fep->wol_flag & |
3445 | FEC_WOL_HAS_MAGIC_PACKET); | |
3446 | ||
eb1d0640 FE |
3447 | if (fep->bufdesc_ex && fep->ptp_clock) |
3448 | netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); | |
3449 | ||
1b7bde6d | 3450 | fep->rx_copybreak = COPYBREAK_DEFAULT; |
36cdc743 | 3451 | INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); |
8fff755e AL |
3452 | |
3453 | pm_runtime_mark_last_busy(&pdev->dev); | |
3454 | pm_runtime_put_autosuspend(&pdev->dev); | |
3455 | ||
ead73183 SH |
3456 | return 0; |
3457 | ||
3458 | failed_register: | |
e6b043d5 BW |
3459 | fec_enet_mii_remove(fep); |
3460 | failed_mii_init: | |
7a2bbd8d | 3461 | failed_irq: |
7a2bbd8d | 3462 | failed_init: |
32cba57b | 3463 | fec_ptp_stop(pdev); |
f6a4d607 FE |
3464 | if (fep->reg_phy) |
3465 | regulator_disable(fep->reg_phy); | |
5fa9c0fe | 3466 | failed_regulator: |
8fff755e AL |
3467 | clk_disable_unprepare(fep->clk_ipg); |
3468 | failed_clk_ipg: | |
e8fcfcd5 | 3469 | fec_enet_clk_enable(ndev, false); |
ead73183 | 3470 | failed_clk: |
407066f8 UKK |
3471 | failed_phy: |
3472 | of_node_put(phy_node); | |
ead73183 SH |
3473 | failed_ioremap: |
3474 | free_netdev(ndev); | |
3475 | ||
3476 | return ret; | |
3477 | } | |
3478 | ||
33897cc8 | 3479 | static int |
ead73183 SH |
3480 | fec_drv_remove(struct platform_device *pdev) |
3481 | { | |
3482 | struct net_device *ndev = platform_get_drvdata(pdev); | |
3483 | struct fec_enet_private *fep = netdev_priv(ndev); | |
3484 | ||
36cdc743 | 3485 | cancel_work_sync(&fep->tx_timeout_work); |
32cba57b | 3486 | fec_ptp_stop(pdev); |
e163cc97 | 3487 | unregister_netdev(ndev); |
e6b043d5 | 3488 | fec_enet_mii_remove(fep); |
f6a4d607 FE |
3489 | if (fep->reg_phy) |
3490 | regulator_disable(fep->reg_phy); | |
407066f8 | 3491 | of_node_put(fep->phy_node); |
ead73183 | 3492 | free_netdev(ndev); |
28e2188e | 3493 | |
ead73183 SH |
3494 | return 0; |
3495 | } | |
3496 | ||
dd66d386 | 3497 | static int __maybe_unused fec_suspend(struct device *dev) |
ead73183 | 3498 | { |
87cad5c3 | 3499 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 3500 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 3501 | |
da1774e5 | 3502 | rtnl_lock(); |
04e5216d | 3503 | if (netif_running(ndev)) { |
de40ed31 NA |
3504 | if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) |
3505 | fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; | |
45f5c327 | 3506 | phy_stop(ndev->phydev); |
31a6de34 RK |
3507 | napi_disable(&fep->napi); |
3508 | netif_tx_lock_bh(ndev); | |
04e5216d | 3509 | netif_device_detach(ndev); |
31a6de34 RK |
3510 | netif_tx_unlock_bh(ndev); |
3511 | fec_stop(ndev); | |
f4c4a4e0 | 3512 | fec_enet_clk_enable(ndev, false); |
de40ed31 NA |
3513 | if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) |
3514 | pinctrl_pm_select_sleep_state(&fep->pdev->dev); | |
ead73183 | 3515 | } |
da1774e5 RK |
3516 | rtnl_unlock(); |
3517 | ||
de40ed31 | 3518 | if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) |
238f7bc7 FE |
3519 | regulator_disable(fep->reg_phy); |
3520 | ||
858eeb7d NA |
3521 | /* SOC supply clock to phy, when clock is disabled, phy link down |
3522 | * SOC control phy regulator, when regulator is disabled, phy link down | |
3523 | */ | |
3524 | if (fep->clk_enet_out || fep->reg_phy) | |
3525 | fep->link = 0; | |
3526 | ||
ead73183 SH |
3527 | return 0; |
3528 | } | |
3529 | ||
dd66d386 | 3530 | static int __maybe_unused fec_resume(struct device *dev) |
ead73183 | 3531 | { |
87cad5c3 | 3532 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 3533 | struct fec_enet_private *fep = netdev_priv(ndev); |
de40ed31 | 3534 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
238f7bc7 | 3535 | int ret; |
de40ed31 | 3536 | int val; |
238f7bc7 | 3537 | |
de40ed31 | 3538 | if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { |
238f7bc7 FE |
3539 | ret = regulator_enable(fep->reg_phy); |
3540 | if (ret) | |
3541 | return ret; | |
3542 | } | |
ead73183 | 3543 | |
da1774e5 | 3544 | rtnl_lock(); |
04e5216d | 3545 | if (netif_running(ndev)) { |
f4c4a4e0 NA |
3546 | ret = fec_enet_clk_enable(ndev, true); |
3547 | if (ret) { | |
3548 | rtnl_unlock(); | |
3549 | goto failed_clk; | |
3550 | } | |
de40ed31 NA |
3551 | if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { |
3552 | if (pdata && pdata->sleep_mode_enable) | |
3553 | pdata->sleep_mode_enable(false); | |
3554 | val = readl(fep->hwp + FEC_ECNTRL); | |
3555 | val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); | |
3556 | writel(val, fep->hwp + FEC_ECNTRL); | |
3557 | fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; | |
3558 | } else { | |
3559 | pinctrl_pm_select_default_state(&fep->pdev->dev); | |
3560 | } | |
ef83337d | 3561 | fec_restart(ndev); |
31a6de34 | 3562 | netif_tx_lock_bh(ndev); |
6af42d42 | 3563 | netif_device_attach(ndev); |
dbc64a8e | 3564 | netif_tx_unlock_bh(ndev); |
6af42d42 | 3565 | napi_enable(&fep->napi); |
45f5c327 | 3566 | phy_start(ndev->phydev); |
ead73183 | 3567 | } |
da1774e5 | 3568 | rtnl_unlock(); |
04e5216d | 3569 | |
ead73183 | 3570 | return 0; |
13a097bd | 3571 | |
e8fcfcd5 | 3572 | failed_clk: |
13a097bd FE |
3573 | if (fep->reg_phy) |
3574 | regulator_disable(fep->reg_phy); | |
3575 | return ret; | |
ead73183 SH |
3576 | } |
3577 | ||
8fff755e AL |
3578 | static int __maybe_unused fec_runtime_suspend(struct device *dev) |
3579 | { | |
3580 | struct net_device *ndev = dev_get_drvdata(dev); | |
3581 | struct fec_enet_private *fep = netdev_priv(ndev); | |
3582 | ||
3583 | clk_disable_unprepare(fep->clk_ipg); | |
3584 | ||
3585 | return 0; | |
3586 | } | |
3587 | ||
3588 | static int __maybe_unused fec_runtime_resume(struct device *dev) | |
3589 | { | |
3590 | struct net_device *ndev = dev_get_drvdata(dev); | |
3591 | struct fec_enet_private *fep = netdev_priv(ndev); | |
3592 | ||
3593 | return clk_prepare_enable(fep->clk_ipg); | |
3594 | } | |
3595 | ||
3596 | static const struct dev_pm_ops fec_pm_ops = { | |
3597 | SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) | |
3598 | SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) | |
3599 | }; | |
59d4289b | 3600 | |
ead73183 SH |
3601 | static struct platform_driver fec_driver = { |
3602 | .driver = { | |
b5680e0b | 3603 | .name = DRIVER_NAME, |
87cad5c3 | 3604 | .pm = &fec_pm_ops, |
ca2cc333 | 3605 | .of_match_table = fec_dt_ids, |
ead73183 | 3606 | }, |
b5680e0b | 3607 | .id_table = fec_devtype, |
87cad5c3 | 3608 | .probe = fec_probe, |
33897cc8 | 3609 | .remove = fec_drv_remove, |
ead73183 SH |
3610 | }; |
3611 | ||
aaca2377 | 3612 | module_platform_driver(fec_driver); |
1da177e4 | 3613 | |
f8c0aca9 | 3614 | MODULE_ALIAS("platform:"DRIVER_NAME); |
1da177e4 | 3615 | MODULE_LICENSE("GPL"); |